WO2025246752A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置

Info

Publication number
WO2025246752A1
WO2025246752A1 PCT/CN2025/091226 CN2025091226W WO2025246752A1 WO 2025246752 A1 WO2025246752 A1 WO 2025246752A1 CN 2025091226 W CN2025091226 W CN 2025091226W WO 2025246752 A1 WO2025246752 A1 WO 2025246752A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
substrate
source
drain conductive
disposed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/091226
Other languages
English (en)
French (fr)
Other versions
WO2025246752A9 (zh
Inventor
鲁栋良
宋亮
李相喆
李信
侯盼
许家豪
姜龙
王江林
林子豪
赵丽红
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025246752A1 publication Critical patent/WO2025246752A1/zh
Publication of WO2025246752A9 publication Critical patent/WO2025246752A9/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/80—Constructional details
    • H10K50/84—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification

Definitions

  • This disclosure relates to the field of display technology, and more specifically, to a display panel and a display device.
  • alignment marks are usually set in the outer area to calibrate the position of the mask.
  • a passivation layer is usually applied to the side of the alignment marks away from the substrate. Because the passivation layer has a strong ability to isolate water and oxygen, the moisture in the lower layer cannot be effectively released, which makes it easy for the alignment marks to peel off from the passivation layer above.
  • the purpose of this disclosure is to overcome the problem of easy peeling between the alignment mark and the passivation layer, and to provide a display panel and display device.
  • a display panel having a display area and a peripheral area located around the display area.
  • the display panel includes a substrate, a planarization layer group, a first source/drain conductive layer, and a passivation layer.
  • the planarization layer group is disposed on one side of the substrate.
  • the first source/drain conductive layer is disposed on the side of the planarization layer group away from the substrate, and the first source/drain conductive layer includes a first alignment mark located in the peripheral area.
  • the passivation layer is disposed on the side of the first source/drain conductive layer away from the substrate, and the passivation layer has a moisture release port. The orthographic projection of the moisture release port on the substrate overlaps at least with the orthographic projection of the first alignment mark on the substrate.
  • the planarization layer group has an easy-peel region located around the first alignment mark, and the orthographic projection of the water vapor release port on the substrate overlaps with the orthographic projections of the first alignment mark and the easy-peel region on the substrate.
  • the orthographic projection of the first alignment mark and the easily peelable area on the substrate is located within the orthographic projection of the moisture release port on the substrate, exposing the side of the first alignment mark away from the substrate, the side of the first alignment mark, and the side of the easily peelable area away from the substrate.
  • the moisture release port includes a first moisture release hole and a second moisture release hole.
  • the orthographic projection of the first moisture release hole on the substrate overlaps with the orthographic projection of the first alignment mark on the substrate, and the orthographic projection of the second moisture release hole on the substrate overlaps with the orthographic projection of the easily peelable area on the substrate.
  • the first alignment mark includes a first alignment portion and a second alignment portion, the first alignment portion and the second alignment portion intersect each other, the first alignment portion extends along a first direction, the second alignment portion extends along a second direction, the second direction is perpendicular to the first direction, and the first moisture release hole includes a first strip portion and a second strip portion connected end to end, the first strip portion and the first alignment portion are parallel to each other, and the second strip portion and the second alignment portion are parallel to each other.
  • the passivation layer is provided with four first water vapor release holes, the first alignment portions of the four first water vapor release holes are spaced apart and symmetrical along a second direction, and the second alignment portions of the four first water vapor release holes are spaced apart and symmetrical along a first direction.
  • an easy-peeling area is formed around each of the first water vapor release holes, and the four easy-peeling areas are respectively provided with a plurality of second water vapor release holes arranged in an array.
  • the display panel further includes a partition layer, a plurality of pixel electrodes, a pixel defining layer, and a light-emitting material layer.
  • the partition layer is disposed on the same layer as the passivation layer and is located in the display area.
  • the plurality of pixel electrodes are disposed on the side of the passivation layer away from the substrate.
  • the pixel defining layer is disposed on the side of the pixel electrodes away from the substrate, and the pixel defining layer has pixel openings that expose each of the pixel electrodes.
  • the light-emitting material layer is disposed on the side of the pixel defining layer away from the substrate.
  • a partition groove is provided between two adjacent pixel openings, and the light-emitting material layer is partitioned in the partition groove. The partition groove penetrates the pixel defining layer and passes through at least a portion of the partition layer.
  • the partition groove includes a first groove segment and a second groove segment sequentially disposed along a direction away from the substrate.
  • the first groove segment penetrates the partition layer, and the second groove segment penetrates the pixel defining layer.
  • the orthographic projection of the first groove segment on the substrate is located within the orthographic projection of the second groove segment on the substrate.
  • the display panel further includes a transistor layer disposed between the first source-drain conductive layer and the substrate.
  • the transistor layer includes at least one transistor.
  • the first source-drain conductive layer includes a first source conductive portion and a first drain conductive portion.
  • the first source conductive portion and the second drain conductive portion are located in the display area.
  • the first source conductive portion is connected to the source of the transistor, and the first drain conductive portion is connected to the drain of the transistor.
  • the pixel electrode is connected to the first drain conductive portion.
  • the display panel further includes a second source/drain conductive layer and a third source/drain conductive layer.
  • the second source/drain conductive layer is disposed between the first source/drain conductive layer and the transistor layer
  • the third source/drain conductive layer is disposed between the second source/drain conductive layer and the transistor layer.
  • the planarization layer group includes a second planarization layer and a first planarization layer. The second planarization layer is located away from the first source/drain conductive layer and the third source/drain conductive layer. The first planarization layer is disposed between the second source/drain conductive layer and the third source/drain conductive layer.
  • the second source/drain conductive layer includes a second source conductive portion and a second drain conductive portion.
  • the third source/drain conductive layer covers...
  • the transistor includes a third source conductive portion and a third drain conductive portion.
  • the first source conductive portion is connected to the second source conductive portion through a first via on the second planarization layer.
  • the first drain conductive portion is connected to the second drain conductive portion through a second via on the second planarization layer.
  • the second source conductive portion is connected to the third source conductive portion through a third via on the first planarization layer.
  • the second drain conductive portion is connected to the third drain conductive portion through a fourth via on the first planarization layer.
  • the third source conductive portion is connected to the source of the transistor through a fifth via.
  • the third drain conductive portion is connected to the drain of the transistor through a sixth via.
  • the display panel further includes a third planarization layer disposed between the passivation layer and the first source/drain conductive layer, and the pixel electrode is connected to the first drain conductive portion through a seventh via on the third planarization layer.
  • the transistor layer includes a first active layer, a second active layer, a first gate, a second gate, and a third gate.
  • the first active layer is disposed on one side of the substrate, and the first gate is disposed on the side of the first active layer away from the substrate.
  • the orthographic projection of the first gate on the substrate overlaps with the orthographic projection of the channel region of the first active layer on the substrate to form a first transistor.
  • the second gate is disposed on the side of the first gate away from the substrate, the second active layer is disposed on the side of the second gate away from the substrate, and the third gate is disposed on the side of the second gate away from the substrate.
  • the second gate and the third gate overlap with the orthographic projection of the channel region of the second active layer on the substrate to form a second transistor.
  • the material of the first active layer is low-temperature polycrystalline silicon, and the material of the second active layer is indium gallium zinc oxide.
  • a display device including a display panel provided in one aspect of this disclosure.
  • the display panel disclosed herein includes a passivation layer, which has a moisture release port.
  • the orthographic projection of the moisture release port on the substrate overlaps at least with the orthographic projection of the first alignment mark on the substrate, so that moisture in the planarization layer group located on the side of the passivation layer closer to the substrate can be effectively released. This can prevent peeling between the first alignment mark and the passivation layer, avoid erosion of the first alignment mark, and accurately ensure the calibration accuracy of the first alignment mark with the mask, thereby ensuring the alignment accuracy of the mask and the film layer formed on the substrate.
  • Figure 1 is a cross-sectional schematic diagram of the display panel according to an embodiment of this disclosure.
  • Figure 2 is a schematic diagram of the peripheral area of the display panel according to an embodiment of the present disclosure when the exposure machine performs alignment by the seventh alignment mark during the formation of the patterned first active layer.
  • Figure 3 is a schematic diagram of the peripheral area of the display panel according to an embodiment of the present disclosure when the exposure machine aligns the patterned first gate using the sixth alignment mark.
  • Figure 4 is a schematic diagram of the peripheral area of the display panel according to an embodiment of the present disclosure when the exposure machine aligns with the fifth alignment mark during the formation of the patterned second gate.
  • Figure 5 is a schematic diagram of the peripheral area of the display panel according to an embodiment of this disclosure when the exposure machine aligns with the fourth alignment mark during the formation of the patterned second active layer.
  • Figure 6 is a schematic diagram of the peripheral area of the display panel according to an embodiment of the present disclosure when the exposure machine aligns the patterned third gate using the fourth alignment mark.
  • Figure 7 is a schematic diagram of the peripheral area of the display panel involved in this embodiment of the present disclosure when the exposure machine aligns with the fourth alignment mark during the formation of vias on the first interlayer dielectric layer.
  • Figure 8 is a schematic diagram of the peripheral area of the display panel involved in the embodiments of this disclosure when the exposure machine performs alignment by the sixth alignment mark during the formation of the patterned third source and drain conductive layer.
  • Figure 9 is a schematic diagram of the peripheral area of the display panel involved in this embodiment of the present disclosure when the exposure machine aligns with the third alignment mark during the formation of the protective layer.
  • Figure 10 is a schematic diagram of the peripheral area of the display panel involved in this embodiment of the present disclosure when a via is formed on the second planarization layer and the exposure machine is aligned with the third alignment mark.
  • Figure 11 is a schematic diagram of the peripheral area of the display panel according to an embodiment of the present disclosure when the exposure machine can perform alignment by a third alignment mark during the formation of a patterned second source/drain conductive layer.
  • Figure 12 is a schematic diagram of the peripheral area of the display panel involved in this embodiment of the present disclosure when a via is formed on the first planarization layer and the exposure machine is aligned with the second alignment mark.
  • Figure 13 is a schematic diagram of the peripheral area of the display panel involved in the embodiments of this disclosure when the exposure machine aligns the patterned first source and drain conductive layer using the second alignment mark.
  • Figure 14 is a schematic diagram of the peripheral area of the display panel involved in this embodiment of the present disclosure when a via is formed in the third planarization layer and the exposure machine is aligned with the first alignment mark.
  • Figure 15 is a schematic diagram of the peripheral area of the display panel according to an embodiment of the present disclosure when the exposure machine aligns the patterned pixel electrodes using the first alignment mark.
  • Figure 16 is a schematic diagram of the peripheral area of the display panel involved in this embodiment of the present disclosure when the exposure machine aligns with the sixth alignment mark during the formation of the pixel defining layer.
  • Figure 17 is a schematic diagram showing the positional relationship of multiple display areas and multiple alignment marks on the entire substrate according to an embodiment of this disclosure.
  • Figure 18 is a partial cross-sectional schematic diagram of the peripheral area of the display panel according to an embodiment of the present disclosure when the first alignment mark is on the first planarization layer.
  • Figure 19 is a partial cross-sectional schematic diagram of the peripheral area of the display panel involved in the embodiments of this disclosure when the passivation layer covers the first alignment mark.
  • Figure 20 is a partial cross-sectional schematic diagram of the peripheral area of the display panel involved in this embodiment of the present disclosure when a water vapor release port is provided on the passivation layer.
  • Figure 21 is a planar schematic diagram of the water vapor release port on the passivation layer involved in the embodiments of this disclosure when the first alignment mark and the easily peelable area located around the first alignment mark are directly removed.
  • Figure 22 is a planar schematic diagram of the water vapor release port on the passivation layer in the present disclosure embodiment when the water vapor release port includes a first water vapor release hole and a second water vapor release hole.
  • 210-Third gate layer 2101-Third gate, 211-First interlayer dielectric layer, 212-Second interlayer dielectric layer, 213-Protective layer, 214-First source/drain conductive layer, 2141-First source conductive portion, 2142-First drain conductive portion, 215-Second source/drain conductive layer, 2151-Second source conductive portion, 2152-Second drain conductive portion, 216-Third source/drain conductive layer, 2161-Third source conductive portion, 2162-Third drain conductive layer Electrical components, 217-Planarization layer group, 2171-First planarization layer, 2172-Second planarization layer, 218-Third planarization layer, 3-Light-emitting layer, 31-Pixel defining layer, 311-Pixel opening, 32-Light-emitting unit, 321-Pixel electrode, 322-Light-emitting material layer, 3
  • a barrier layer is usually set in the display area 100 of the display panel to separate the light-emitting material layer 322.
  • alignment marks 4 are usually set in the peripheral area 200 to align and calibrate the setting position of the mask.
  • the alignment marks 4 are located in the peripheral area 200 of the display panel, making them susceptible to water and oxygen erosion.
  • the material of the barrier layer is SiNx. Therefore, it is considered that a passivation layer 34 is formed on the side of the first alignment mark 41 away from the substrate 1 to isolate water and oxygen while forming the barrier layer.
  • the planarization layer group 217 under the first alignment mark 41 is an organic layer. The moisture in the planarization layer group 217 cannot be effectively released, which makes it easy for the first alignment mark 41 and the passivation layer 34 to peel off.
  • the present disclosure provides a display panel.
  • the display panel has a display area 100 and a peripheral area 200 located around the display area 100.
  • the display panel includes a substrate 1, a first source/drain conductive layer 214, and a passivation layer 34.
  • a planarization layer group 217 is disposed on one side of the substrate 1.
  • the first source/drain conductive layer 214 is disposed on the side of the planarization layer group 217 away from the substrate 1.
  • the first source/drain conductive layer 214 includes a first alignment mark 41, which is located in the peripheral area 200.
  • the passivation layer 34 is disposed on the side of the first source/drain conductive layer 214 away from the substrate 1.
  • the passivation layer 34 has a moisture release port 341.
  • the orthographic projection of the moisture release port 341 on the substrate 1 overlaps at least with the orthographic projection of the first alignment mark 41 on the substrate 1.
  • the passivation layer 34 is provided with a moisture release port 341.
  • the orthographic projection of the moisture release port 341 on the substrate 1 overlaps at least with the orthographic projection of the first alignment mark 41 on the substrate 1, so that the moisture in the planarization layer group 217 located on the side of the passivation layer 34 close to the substrate 1 can be effectively released. This can prevent the first alignment mark 41 from peeling off from the passivation layer 34, avoid the first alignment mark 41 from being eroded, and accurately ensure the calibration accuracy of the first alignment mark 41 with the mask, thereby ensuring the alignment accuracy of the mask and the film layer formed on the substrate 1.
  • a display panel generally includes a substrate 1, a driving circuit layer 2, and a light-emitting layer 3.
  • the driving circuit layer 2 is disposed on one side of the substrate 1, and the light-emitting layer 3 is disposed on the side of the driving circuit layer 2 away from the substrate 1.
  • the display panel may also include a buffer layer disposed between the substrate 1 and the driving circuit layer 2.
  • the substrate 1 can be an inorganic material or an organic material.
  • the substrate 1 can be made of glass materials such as soda-lime glass, quartz glass, or sapphire glass, or it can be made of metal materials such as stainless steel, aluminum, or nickel.
  • the substrate 1 may also be a flexible substrate 1, for example, the material of the substrate 1 may be polyimide (PI).
  • the substrate 1 may also be a composite of multiple materials.
  • the substrate 1 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer and a second polyimide layer stacked sequentially.
  • the driving circuit layer 2 includes a transistor layer.
  • the transistor layer may include a first buffer layer 202, a second buffer layer, a first active layer 203, a second active layer 204, a first gate insulating layer 205, a second gate insulating layer 206, a third gate insulating layer 207, a first gate layer 208, a second gate layer 209, a third gate layer 210, a first interlayer dielectric layer 211, and a second interlayer dielectric layer 212.
  • the first buffer layer 202 is disposed on one side of the substrate 1.
  • the first active layer is disposed on the side of the first buffer layer 202 away from the substrate 1.
  • the first gate insulating layer 205 is disposed on the side of the first active layer 203 away from the substrate 1.
  • the first gate layer 208 is disposed on the side of the first gate insulating layer 205 away from the substrate 1.
  • the second gate insulating layer 206 is disposed on the side of the first gate layer 208 away from the substrate 1.
  • the second gate layer 209 is disposed on the side of the second gate insulating layer 206 away from the substrate 1.
  • Layer 211 is disposed on the side of the second gate layer 209 away from the substrate 1
  • the second buffer layer is disposed on the side of the first interlayer dielectric layer 211 away from the substrate 1
  • the second active layer 204 is disposed on the side of the second buffer layer away from the substrate 1
  • the third gate insulating layer 207 is disposed on the side of the second active layer 204 away from the substrate 1
  • the third gate layer 210 is disposed on the side of the third gate insulating layer 207 away from the substrate 1
  • the second interlayer dielectric layer 212 is disposed on the side of the third gate layer 210 away from the substrate 1.
  • Both the first active layer 203 and the second active layer 204 may include a channel region.
  • the first gate layer 208 includes a first gate 2081, the orthographic projection of the first gate 2081 on the substrate 1 overlaps with the orthographic projection of the channel region of the first active layer 203 on the substrate 1, forming a first transistor 21.
  • the second gate layer 209 includes a second gate 2091, and the third gate layer 210 includes a third gate 2101, the second gate 2091 and the third gate 2101 overlap with the orthographic projection of the channel region of the second active layer 204 on the substrate 1, forming a second transistor 22.
  • the material of the first active layer 203 is low-temperature polysilicon (LTPS), and the material of the second active layer 204 is indium gallium zinc oxide (IGZO).
  • the first transistor 21 is a low-temperature polysilicon thin-film transistor
  • the second transistor 22 is an oxide thin-film transistor.
  • the transistor layer may also include a light-shielding layer 201, which is located between the first buffer layer 202 and the substrate 1.
  • the light-shielding layer 201 may overlap with the channel region of the first active layer 203 to shield the light irradiating the first transistor 21, thereby stabilizing the electrical characteristics of the first transistor 21.
  • the driving circuit layer 2 may further include a first source/drain conductive layer 214, a second source/drain conductive layer 215, a third source/drain conductive layer 216, a protective layer 213, and a planarization layer group 217.
  • the planarization layer group 217 includes a second planarization layer 2172 and a first planarization layer 2171.
  • the third source/drain metal layer is disposed on the surface of the second interlayer dielectric layer 212 away from the substrate 1.
  • the protective layer 213 is disposed on the side of the third source/drain metal layer away from the substrate 1.
  • the first planarization layer 2171 is disposed on the side of the protective layer 213 away from the substrate 1.
  • the second source/drain conductive layer 215 is disposed on the side of the first planarization layer 2171 away from the substrate 1.
  • the second planarization layer 2172 is disposed on the side of the second source/drain conductive layer 215 away from the substrate 1.
  • the first source/drain conductive layer 214 is disposed on the side of the second planarization layer 2172 away from the substrate 1.
  • the driving circuit layer 2 may also include a third planarization layer 218, which is disposed on the side of the first source/drain conductive layer 214 away from the substrate 1.
  • the first active layer 203 has two doped regions of different doping types on both sides of its channel region, which are the source and drain of the first transistor 21, respectively.
  • the second active layer 204 has two doped regions of different doping types on both sides of its channel region, which are the source and drain of the second transistor 22, respectively.
  • the first source-drain conductive layer 214 includes a first source conductive portion 2141 and a first drain conductive portion 2142.
  • the second source-drain conductive layer 215 includes a second source conductive portion 2151 and a second drain conductive portion 2152.
  • the third source-drain conductive layer 216 includes a third source conductive portion 2161 and a third drain conductive portion 2162.
  • the first source conductive portion 2141 is connected to the second source conductive portion 2151 through a first via on the second planarization layer 2172.
  • the first drain conductive portion 2142 is connected to the second drain conductive portion 2162 through the second planarization layer 2172.
  • the second via on layer 2172 is connected to the second drain conductive portion 2152.
  • the second source conductive portion 2151 is connected to the third source conductive portion 2161 through the third via on the first planarization layer 2171.
  • the second drain conductive portion 2152 is connected to the third drain conductive portion 2162 through the fourth via on the first planarization layer 2171.
  • the third source conductive portion 2161 is connected to the source of the transistor through the fifth via.
  • the third drain conductive portion 2162 is connected to the drain of the transistor through the sixth via.
  • the light-emitting layer 3 includes a pixel defining layer 31, which is disposed on the side of the third planarization layer 218 away from the array substrate.
  • the pixel defining layer 31 has multiple pixel openings 311.
  • the light-emitting layer 3 may include multiple light-emitting units 32, each disposed within a different pixel opening 311.
  • Each light-emitting unit 32 may include a pixel electrode 321, a light-emitting material layer 322, and a common electrode 323.
  • the pixel electrode 321 is located on the surface of the third planarization layer 218 away from the substrate 1.
  • the pixel electrode 321 is connected to the first drain conductive portion 2142 through a seventh via on the third planarization layer 218.
  • the light-emitting material layer 322 is disposed on the side of the pixel electrode 321 and pixel defining layer away from the substrate 1, and the common electrode 323 is disposed on the side of the light-emitting material layer 322 away from the substrate 1.
  • the pixel electrode 321 and the common electrode 323 can drive the light-emitting element to emit light to display an image.
  • the common electrode 323 can serve as the cathode, and the pixel electrode 321 can serve as the anode.
  • Light emission can be driven by applying a signal to the pixel electrode 321; the specific light emission principle will not be detailed here.
  • the light emission element may contain electroluminescent organic light-emitting materials and can be formed using processes such as vapor deposition.
  • the light emission element may include a hole injection layer, a hole transport layer, a light generation layer, an electron transport layer, and an electron injection layer sequentially stacked on the pixel electrode 321 layer. It should be noted that, depending on the emitted color, the light emission element may include a red light emission element, a green light emission element, and a blue light emission element.
  • the light-emitting material layer 322 protects multiple sub-light-emitting layers 3 groups connected in series, and a charge-generation layer (CGL) is provided between two adjacent sub-light-emitting layers 3 groups
  • the charge-generation layer is a common layer with strong conductivity, which can easily cause lateral leakage and crosstalk between two adjacent light-emitting units 32.
  • a partition layer 33 is provided on the side of the pixel electrode 321 near the substrate 1, and a partition groove 35 is provided in the part of the partition layer 33 and the pixel definition layer between two adjacent pixel openings 311, so that the light-emitting material layer 322 is isolated in the partition groove 35.
  • the common electrode 323 can be broken in the partition groove 35, or it can remain intact, without affecting the display effect.
  • the partition groove 35 includes a first groove segment 351 and a second groove segment 352 arranged sequentially along the direction away from the substrate 1.
  • the first groove segment 351 penetrates the partition layer 33, and the second groove segment 352 penetrates the pixel defining layer 31.
  • the orthographic projection of the first groove segment 351 on the substrate 1 is located within the orthographic projection of the second groove segment 352 on the substrate 1.
  • alignment marks 4 are usually set in the peripheral area 200.
  • the alignment marks 4 are used to calibrate the setting position of the mask.
  • the peripheral area 200 is set around the outer periphery of the display area 100.
  • Alignment mark 4 may include a first alignment mark 41, a second alignment mark 42, a third alignment mark 43, a fourth alignment mark 44, a fifth alignment mark 45, a sixth alignment mark 46, and a seventh alignment mark 47.
  • the first alignment mark 41 is located in the first source-drain conductive layer 214 and may be disposed in the same layer and with the same material as the first source conductive portion 2141 and the first drain conductive portion 2142.
  • the second alignment mark 42 is located in the second source-drain conductive layer 215.
  • the third alignment mark 43 is located in the third source-drain conductive layer 216.
  • the fourth alignment mark 44 is disposed in the same layer and with the second gate 2091.
  • the fifth alignment mark 45 is disposed in the same layer and with the first gate 2081.
  • the sixth alignment mark 46 is disposed in the same layer and with the first active layer 203.
  • the seventh alignment mark 47 is disposed in the same layer and with the light-shielding layer 201.
  • the first buffer layer 202 is transparent.
  • the exposure machine aligns the layers using the seventh alignment mark 47.
  • the first gate insulating layer 205 is transparent, and the exposure machine aligns it using the sixth alignment mark 46.
  • the exposure machine aligns it with the fifth alignment mark 45.
  • the second gate layer 209 has completed film deposition, and the entire second gate layer 209 formed by film deposition will form a first alignment protrusion at the position directly opposite the fifth alignment mark 45.
  • the second active layer 204 is transparent. During the formation of the patterned second active layer 204, the exposure machine aligns it with the fourth alignment mark 44.
  • the exposure machine can also align it using the fourth alignment mark 44.
  • the third gate layer 210 has completed film deposition, and the entire third gate layer 210 formed by film deposition will form a second alignment protrusion at the position directly opposite the fourth alignment mark 44.
  • the first interlayer dielectric layer 211 is transparent. When forming vias on the first interlayer dielectric layer 211, the exposure machine aligns with the fourth alignment mark 44.
  • the exposure machine can also be aligned using the sixth alignment mark 46.
  • the third source/drain conductive layer 216 has completed film deposition, and the entire third source/drain conductive layer 216 formed by film deposition will form a third alignment protrusion at the position directly opposite to the sixth alignment mark 46.
  • the protective layer 213 is transparent, and the exposure machine is aligned with the third alignment mark 43 when forming the protective layer 213.
  • the second planarization layer 2172 is transparent, and the exposure machine is aligned with the third alignment mark 43 when forming vias on the second planarization layer 2172.
  • the exposure machine can be aligned using the third alignment mark 43.
  • the second source/drain conductive layer 215 has completed film deposition, and the entire second source/drain conductive layer 215 formed by film deposition will form a fourth alignment protrusion at the position directly opposite to the third alignment mark 43.
  • the first planarization layer 2171 is transparent.
  • the exposure machine aligns with the second alignment mark 42.
  • the exposure machine can align using the second alignment mark 42.
  • the first source/drain conductive layer 214 has completed film deposition, and the entire first source/drain conductive layer 214 formed by film deposition will form a fifth alignment protrusion at the position directly opposite the second alignment mark 42.
  • the third planarization layer 218 is transparent. When forming vias on the third planarization layer 218, the exposure machine aligns with the first alignment mark 41.
  • the exposure machine can align it using the first alignment mark 41.
  • the pixel electrode 321 layer has completed film deposition.
  • the entire pixel electrode 321 layer formed by film deposition will form a sixth alignment protrusion at the position directly opposite to the first alignment mark 41.
  • the first gate insulating layer 205, the second gate insulating layer 206, the pixel defining layer 31, the first interlayer dielectric layer 211, the second interlayer dielectric layer 212, the second planarization layer 2172, the first planarization layer 2171, the third planarization layer 218, and the pixel defining layer 31 are transparent.
  • the exposure machine aligns it with the sixth alignment mark 46.
  • the first alignment mark 41 is disposed on the side of the first planarization layer 2171 away from the substrate 1.
  • the passivation layer 34 covers the first alignment mark 41.
  • the passivation layer 34 is provided with a first cover layer 36 on the side away from the substrate 1.
  • the first cover layer 36 is provided with a second cover layer 37 on the side away from the substrate 1.
  • the first cover layer 36 is disposed in the same layer and with the same material as the pixel electrode 321.
  • the second cover layer 37 is disposed in the same layer and with the same material as the common electrode 323.
  • a certain number of alignment marks 4 need to be set in the first direction and the second direction respectively.
  • a row of alignment marks 4 can be set at both ends of the substrate 5 along the second direction, and two sets of alignment marks 4 are set between the two rows of alignment marks 4 at intervals along the second direction.
  • Each set of alignment marks 4 may include three adjacent rows of alignment marks 4. Eleven columns of alignment marks 4 are set along the first direction, wherein two columns of alignment marks 4 are located at both ends of the substrate 5 along the first direction, and the remaining columns of alignment marks 4 are located between two adjacent columns of display areas 100 along the first direction.
  • a passivation layer 34 is provided between the pixel electrode 321 layer and the first alignment mark 41, covering the first alignment mark 41.
  • the passivation layer 34 is provided with a water vapor release port 341, the orthographic projection of the water vapor release port 341 on the substrate 1 overlapping with the orthographic projection of the first alignment mark 41 on the substrate 1. Water vapor between the passivation layer 34 and the first alignment mark 41 can escape through the water vapor release port 341, greatly reducing the possibility of peeling between the passivation layer 34 and the first alignment mark 41.
  • the passivation layer 34 has a strong ability to isolate water and oxygen, the moisture between the second planarization layer 2172 and the passivation layer 34 cannot be effectively released.
  • the movement of water vapor at the contact surface between the first alignment mark 41 and the passivation layer 34 intensifies, eventually leading to the peeling off of the passivation layer 34. Therefore, the coverage area of the water vapor release port 341 can be expanded so that the orthographic projection of the water vapor release port 341 on the substrate 1 overlaps with the orthographic projections of the first alignment mark 41 and the easily peelable area on the substrate 1.
  • the first alignment mark 41 is cross-shaped, including a first alignment portion 411 and a second alignment portion 412.
  • the first alignment portion 411 extends along a first direction
  • the second alignment portion 412 extends along a second direction.
  • the first direction and the second direction are perpendicular to each other, and the first alignment portion 411 and the second alignment portion 412 intersect each other.
  • the first alignment mark 41 and the easily peelable area located around the first alignment mark 41 can be directly removed. That is, the orthographic projection of the first alignment mark 41 on the substrate 1 and the orthographic projection of the easily peelable area on the substrate 1 are both located within the orthographic projection of the moisture release port 341 on the substrate 1.
  • the pixel electrode 321 and the common electrode 323 are directly covered on the side of the first alignment mark 41 and the second planarization layer 2172 away from the substrate 1.
  • Each first moisture release hole 3411 can also be provided on the passivation layer 34.
  • Each first moisture release hole 3411 includes a first strip-shaped portion 3413 and a second strip-shaped portion 3414 connected end-to-end.
  • the first strip-shaped portion 3413 is parallel to the first alignment portion 411
  • the second strip-shaped portion 3414 is parallel to the second alignment portion 412.
  • the first alignment portions 411 of the four first moisture release holes 3411 are spaced apart and symmetrical along a second direction
  • the second alignment portions 412 of the four first moisture release holes 3411 are spaced apart and symmetrical along a first direction.
  • Four easily peelable areas are formed around the first alignment mark 41.
  • Each of the four easily peelable areas is provided with a plurality of arrayed second moisture release holes 3412.
  • the plurality of second moisture release holes 3412 are arranged in multiple rows along the first direction and in multiple columns along the second direction. It can be understood that the plurality of second moisture release holes 3412 are arranged in a rectangular array.
  • This disclosure also provides a display device, which may include the display panel mentioned above in this disclosure.
  • a display device which may include the display panel mentioned above in this disclosure.
  • the specific structure and beneficial effects of the display panel have been described in detail above, and therefore will not be repeated here.
  • the display device in addition to the display panel, the display device also includes other necessary components and parts, such as the casing, circuit board, power cord, etc. Those skilled in the art can make corresponding additions according to the specific usage requirements of the display device, which will not be elaborated here.
  • Display devices can be traditional electronic devices, such as mobile phones, computers, televisions, and video recorders, or emerging wearable devices, such as virtual reality devices and augmented reality devices, which will not be listed here.

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Abstract

一种显示面板，该显示面板包括钝化层（34），所述钝化层（34）设有水汽释放口（341），所述水汽释放口（341）在衬底基板（1）上的正投影至少与所述第一对位标记在所述衬底基板（1）上的正投影交叠，使得位于钝化层（34）靠近衬底基板（1）的一侧的平坦化层组（217）中的水汽可以有效释放，可以防止第一对位标记（41)与钝化层（34）之间发生剥离，避免第一对位标记（41)被侵蚀，精确保证第一对位标记（41)对掩膜板的校准精度，从而保证掩膜板与衬底基板（1）上已形成膜层的对位精度。本公开还提供一种包括上述显示面板的显示装置。

Description

显示面板及显示装置
交叉引用
本公开要求于2024年5月31日提交的申请号为202410703867.7名称为“显示面板及显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
为了保证掩膜板与衬底基板上已形成膜层的对位精度，通常会在外围区设置对位标记，通过对位标记来校准掩膜板的设置位置。
为了防止水氧侵蚀对位标记，通常会在对位标记远离衬底基板的一侧覆盖钝化层，由于钝化层具有超强的隔绝水氧的能力，下层的水分无法有效释放出去，导致对位标记与上方的钝化层之间容易发生剥离。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服对位标记与钝化层之间容易发生剥离的问题，提供一种显示面板及显示装置。
根据本公开的一个方面，提供一种显示面板，具有显示区和位于所述显示区外围的外围区，该显示面板包括衬底基板、平坦化层组、第一源漏导电层和钝化层，平坦化层组设于所述衬底基板的一侧；第一源漏导电层设于所述平坦化层组远离所述衬底基板的一侧，所述第一源漏导电层包括第一对位标记，所述第一对位标记位于所述外围区；钝化层设于所述第一源漏导电层远离所述衬底基板的一侧，所述钝化层设有水汽释放口，所述水汽释放口在所述衬底基板上的正投影至少与所述第一对位标记在所述衬底基板上的正投影交叠。
在本公开的一个实施例中，所述平坦化层组具有易剥离区，所述易剥离区设于所述第一对位标记的外围，所述水汽释放口在所述衬底基板上的正投影与所述第一对位标记和所述易剥离区在所述衬底基板上的正投影均交叠。
在本公开的一个实施例中，所述第一对位标记和所述易剥离区在所述衬底基板上的正投影位于所述水汽释放口在所述衬底基板上的正投影内，露出所述第一对位标记远离所述衬底基板的一面、所述第一对位标记的侧面以及所述易剥离区远离衬底基板的一面。
在本公开的一个实施例中，所述水汽释放口包括第一水汽释放孔和第二水汽释放孔，所述第一水汽释放孔在衬底基板上的正投影与所述第一对位标记在所述衬底基板上的正投影交叠，所述第二水汽释放孔在衬底基板上的正投影与所述易剥离区在所述衬底基板上的正投影交叠。
在本公开的一个实施例中，所述第一对位标记包括第一对位部和第二对位部，所述第一对位部与所述第二对位部相互交叉，所述第一对位部沿第一方向延伸，所述第二对位部沿第二方向延伸，所述第二方向与所述第一方向相互垂直，所述第一水汽释放孔包括首尾相连的第一条形部和第二条形部，所述第一条形部与所述第一对位部相互平行，所述第二条形部与所述第二对位部相互平行。
在本公开的一个实施例中，所述钝化层上设有四个第一水汽释放孔，四个所述第一水汽释放孔的第一对位部沿第二方向间隔且对称，四个所述第一水汽释放孔的第二对位部沿第一方向间隔且对称。
在本公开的一个实施例中，各所述第一水汽释放孔的外围分别形成一个所述易剥离区，四个所述易剥离区分别设有多个阵列排布的所述第二水汽释放孔。
在本公开的一个实施例中，所述显示面板还包括隔断层、多个像素电极、像素界定层和发光材料层，隔断层与所述钝化层同层设置，且位于所述显示区；多个像素电极设于所述钝化层远离所述衬底基板的一侧；像素界定层设于所述像素电极远离所述衬底基板的一侧，所述像素界定层设有露出各个所述像素电极的像素开口；发光材料层设于所述像素界定层远离所述衬底基板的一侧；相邻两个所述像素开口之间设有隔断槽，所述发光材料层在所述隔断槽内被隔断，所述隔断槽贯穿所述像素界定层，并穿过至少部分所述隔断层。
在本公开的一个实施例中，所述隔断槽包括沿远离衬底基板的方向依次设置第一槽段和第二槽段，所述第一槽段贯穿所述隔断层，所述第二槽段贯穿所述像素界定层，所述第一槽段在所述衬底基板上的正投影位于所述第二槽段在所述衬底基板上的正投影内。
在本公开的一个实施例中，所述显示面板还包括晶体管层，所述晶体管层设于所述第一源漏导电层与所述衬底基板之间，所述晶体管层包括至少一个晶体管，所述第一源漏导电层包括第一源极导电部和第一漏极导电部，所述第一源极导电部和第二漏极导电部位于所述显示区，所述第一源极导电部与所述晶体管的源极连接，所述第一漏极导电部与所述晶体管的漏极连接，所述像素电极与所述第一漏极导电部连接。
在本公开的一个实施例中，所述显示面板还包括第二源漏导电层和第三源漏导电层，所述第二源漏导电层设于所述第一源漏导电层与所述晶体管层之间，所述第三源漏导电层设于所述第二源漏导电层与所述晶体管层之间，所述平坦化层组包括第二平坦化层和第一平坦化层，所述第二平坦化层远离所述第一源漏导电层与所述第二源漏导电层之间，所述第一平坦化层设于所述第二源漏导电层与所述第三源漏导电层之间，所述第二源漏导电层包括第二源极导电部和第二漏极导电部，所述第三源漏导电层包括第三源极导电部和第三漏极导电部，所述第一源极导电部通过所述第二平坦化层上的第一过孔与所述第二源极导电部连接，所述第一漏极导电部通过所述第二平坦化层上的第二过孔与所述第二漏极导电部连接，所述第二源极导电部通过所述第一平坦化层上的第三过孔与所述第三源极导电部连接，所述第二漏极导电部通过所述第一平坦化层上的第四过孔与所述第三漏极导电部连接，所述第三源极导电部通过第五过孔所述晶体管的源极连接，所述第三漏极导电部通过第六过孔与所述晶体管的漏极连接。
在本公开的一个实施例中，所述显示面板还包括第三平坦化层，所述第三平坦化层设于所述钝化层与所述第一源漏导电层之间，所述像素电极通过所述第三平坦化层上的第七过孔与所述第一漏极导电部连接。
在本公开的一个实施例中，所述晶体管层包括第一有源层、第二有源层、第一栅极、第二栅极和第三栅极，所述第一有源层设于所述衬底基板的一侧，所述第一栅极设于所述第一有源层远离所述衬底基板的一侧，所述第一栅极在所述衬底基板上的正投影与所述第一有源层的沟道区在所述衬底基板上的正投影交叠，形成第一晶体管，所述第二栅极设于所述第一栅极远离所述衬底基板的一侧，所述第二有源层设于所述第二栅极远离所述衬底基板的一侧，所述第三栅极设于所述第二栅极远离所述衬底基板的一侧，所述第二栅极和所述第三栅极与所述第二有源层的沟道区在所述衬底基板上的正投影交叠，形成第二晶体管，所述第一有源层的材料为低温多晶硅，所述第二有源层的材料为铟镓锌氧化物。
根据本公开的另一个方面，提供一种显示装置，包括本公开的一个方面所提供的显示面板。
本公开的显示面板包括钝化层，所述钝化层设有水汽释放口，所述水汽释放口在所述衬底基板上的正投影至少与所述第一对位标记在所述衬底基板上的正投影交叠，使得位于钝化层靠近衬底基板的一侧的平坦化层组中的水汽可以有效释放，可以防止第一对位标记与钝化层之间发生剥离，避免第一对位标记被侵蚀，精确保证第一对位标记的对掩膜板的校准精度，从而保证掩膜板与衬底基板上已形成膜层的对位精度。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例涉及的显示面板的截面示意图。
图2为在形成图案化的第一有源层时，曝光机通过第七对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图3为在形成图案化的第一栅极时，曝光机通过第六对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图4为在形成图案化的第二栅极时，曝光机与第五对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图5为在形成图案化的第二有源层时，曝光机与第四对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图6为在形成图案化的第三栅极时，曝光机通过第四对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图7为在第一层间介质层上形成过孔时，曝光机与第四对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图8为在形成图案化的第三源漏导电层，曝光机通过第六对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图9为在形成保护层时，曝光机与第三对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图10为在第二平坦化层上形成过孔，曝光机与第三对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图11为在形成图案化的第二源漏导电层，曝光机可以通过第三对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图12为在第一平坦化层上形成过孔，曝光机与第二对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图13为在形成图案化的第一源漏导电层，曝光机通过第二对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图14为在第三平坦化层形成过孔，曝光机与第一对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图15为在形成图案化的像素电极，曝光机通过第一对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图16为在形成像素界定层，曝光机与第六对位标记进行对位时，本公开实施例涉及的显示面板的外围区的示意图。
图17为本公开实施例涉及的多个显示区和多个对位标记在整面衬底上的位置关系示意图。
图18为第一对位标记在第一平坦化层上时，本公开实施例涉及的显示面板的外围区的局部截面示意图。
图19为钝化层覆盖第一对位标记时，本公开实施例涉及的显示面板的外围区的局部截面示意图。
图20为钝化层上设置水汽释放口时，本公开实施例涉及的显示面板的外围区的局部截面示意图。
图21为将第一对位标记和位于第一对位标记外围的易剥离区直接去掉时，本公开实施例涉及的钝化层上水汽释放口的平面示意图。
图22为本公开实施例涉及的水汽释放口包括第一水汽释放孔和第二水汽释放孔时，本公开实施例涉及的钝化层上水汽释放口的平面示意图。
图中：100-显示区；200-外围区；1-衬底基板，2-驱动电路层，21-第一晶体管，22-第二晶体管，201-遮光层，202-第一缓冲层，203-第一有源层，204-第二有源层，205-第一栅绝缘层，206-第二栅绝缘层，207-第三栅绝缘层，208-第一栅极层，2081-第一栅极，209-第二栅极层，2091-第二栅极，210-第三栅极层，2101-第三栅极，211-第一层间介质层，212-第二层间介质层，213-保护层，214-第一源漏导电层，2141-第一源极导电部，2142-第一漏极导电部，215-第二源漏导电层，2151-第二源极导电部，2152-第二漏极导电部，216-第三源漏导电层，2161-第三源极导电部，2162-第三漏极导电部，217-平坦化层组，2171-第一平坦化层，2172-第二平坦化层，218-第三平坦化层，3-发光层，31-像素界定层，311-像素开口，32-发光单元，321-像素电极，322-发光材料层，323-公共电极，33-隔断层，34-钝化层，341-水汽释放口，3411-第一水汽释放孔，3412-第二水汽释放孔，3413-第一条形部，3414-第二条形部，35-隔断槽，351-第一槽段，352-第二槽段，36-第一覆盖层，37-第二覆盖层，4-对位标记，41-第一对位标记，411-第一对位部，412-第二对位部，42-第二对位标记，43-第三对位标记，44-第四对位标记，45-第五对位标记，46-第六对位标记，47-第七对位标记，5-整面衬底。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
如图1和图17所示，为了防止不同的发光单元32之间发生串扰，影响显示效果，通常会在显示面板的显示区100设置隔断层将发光材料层322隔断。为了保证掩膜板与衬底基板1上已形成膜层的对位精度，通常会在外围区200设置对位标记4，通过对位标记4来对准校准掩膜板的设置位置。对位标记4位于显示面板的外围区200，使得对位标记4容易被水氧侵蚀，隔断层的材料为SiNx，因此考虑在形成隔断层的同时在第一对位标记41远离衬底基板1的一侧形成钝化层34隔绝水氧，而第一对位标记41下层的平坦化层组217为有机层，平坦化层组217中的水分无法有效释放出去，导致第一对位标记41与钝化层34之间容易发生剥离。
基于此，本公开实施方式提供一种显示面板。如图1至22所示，该显示面板具有显示区100和位于所述显示区100外围的外围区200，所述显示面板包括衬底基板1、第一源漏导电层214和钝化层34，平坦化层组217设于所述衬底基板1的一侧；第一源漏导电层214设于所述平坦化层组217远离所述衬底基板1的一侧，所述第一源漏导电层214包括第一对位标记41，所述第一对位标记41位于所述外围区200；钝化层34设于所述第一源漏导电层214远离所述衬底基板1的一侧，所述钝化层34设有水汽释放口341，所述水汽释放口341在所述衬底基板1上的正投影至少与所述第一对位标记41在所述衬底基板1上的正投影交叠。
所述钝化层34设有水汽释放口341，所述水汽释放口341在所述衬底基板1上的正投影至少与所述第一对位标记41在所述衬底基板1上的正投影交叠，使得位于钝化层34靠近衬底基板1的一侧的平坦化层组217中的水汽可以有效释放，可以防止第一对位标记41与钝化层34之间发生剥离，避免第一对位标记41被侵蚀，精确保证第一对位标记41的对掩膜板的校准精度，从而保证掩膜板与衬底基板1上已形成膜层的对位精度。
下面结合具体的实施例对本公开实施方式所涉及的显示面板进行详细说明。
如图1所示，显示面板一般可以包括衬底基板1、驱动电路层2和发光层3，驱动电路层2设于衬底基板1的一侧，发光层3设于驱动电路层2远离衬底基板1的一侧。另外，显示面板还可以包括缓冲层，缓冲层设于衬底基板1与驱动电路层2之间。
衬底基板1可以为无机材料的衬底基板1，也可以为有机材料的衬底基板1。举例而言，在本公开的一种实施方式中，衬底基板1的材料可以为钠钙玻璃(soda-lime glass)、石英玻璃、蓝宝石玻璃等玻璃材料，或者可以为不锈钢、铝、镍等金属材料。
在本公开的另一种实施方式中，衬底基板1也可以为柔性衬底基板1，例如衬底基板1的材料可以为聚酰亚胺(polyimide，PI)。衬底基板1还可以为多层材料的复合，举例而言，在本公开的一种实施方式中，衬底基板1可以包括依次层叠设置的底膜层(Bottom Film)、压敏胶层、第一聚酰亚胺层和第二聚酰亚胺层。
在显示区100，驱动电路层2包括晶体管层，晶体管层可以包括第一缓冲层202、第二缓冲层、第一有源层203、第二有源层204、第一栅绝缘层205、第二栅绝缘层206、第三栅绝缘层207、第一栅极层208、第二栅极层209、第三栅极层210、第一层间介质层211和第二层间介质层212。第一缓冲层202设于衬底基板1的一侧，第一有源设于第一缓冲层202远离衬底基板1的一侧，第一栅绝缘层205设于第一有源层203远离衬底基板1的一侧，第一栅极层208设于第一栅绝缘层205远离衬底基板1的一侧，第二栅绝缘层206设于第一栅极层208远离衬底基板1的一侧，第二栅极层209设于第二栅绝缘层206远离衬底基板1的一侧，第一层间介质层211设于第二栅极层209远离衬底基板1的一侧，第二缓冲层设于第一层间介质层211远离衬底基板1的一侧，第二有源层204设于第二缓冲层远离衬底基板1的一侧，第三栅绝缘层207设于第二有源层204远离衬底基板1的一侧，第三栅极层210设于第三栅绝缘层207远离衬底基板1的一侧，第二层间介质层212设于第三栅极层210远离衬底基板1的一侧。
第一有源层203和第二有源层204均可包括沟道区。第一栅极层208包括第一栅极2081，所述第一栅极2081在所述衬底基板1上的正投影与所述第一有源层203的沟道区在所述衬底基板1上的正投影交叠，形成第一晶体管21。第二栅极层209包括第二栅极2091，第三栅极层210包括第三栅极2101，所述第二栅极2091和所述第三栅极2101与所述第二有源层204的沟道区在所述衬底基板1上的正投影交叠，形成第二晶体管22，所述第一有源层203的材料为低温多晶硅(Low Temperature Poly-silicon，LTPS)，所述第二有源层204的材料为铟镓锌氧化物(indium gallium zinc oxide，IGZO)，因此第一晶体管21为低温多晶硅薄膜晶体管，第二晶体管22为氧化物薄膜晶体管。晶体管层还可以包括遮光层201，遮光层201位于在第一缓冲层202与衬底基板1之间，遮光层201可以与第一有源层203的沟道区交叠，以遮蔽照射向第一晶体管21的光线，使得第一晶体管21的电学特性稳定。
驱动电路层2还可以包括第一源漏导电层214、第二源漏导电层215、第三源漏导电层216、保护层213和平坦化层组217，平坦化层组217包括第二平坦化层2172和第一平坦化层2171，第三源漏金属层设于第二层间介质层212远离衬底基板1的表面，保护层213设于第三源漏金属层远离衬底基板1的一侧，第一平坦化层2171设于保护层213远离衬底基板1的一侧，第二源漏导电层215设于第一平坦化层2171远离衬底基板1的一侧，第二平坦化层2172设于第二源漏导电层215远离衬底基板1的一侧，第一源漏导电层214设于第二平坦化层2172远离衬底基板1的一侧。驱动电路层2还可以包括第三平坦化层218，第三平坦化层218设于第一源漏导电层214远离衬底基板1的一侧。
第一有源层203的沟道区两侧设有两个不同掺杂类型的掺杂区，分别为第一晶体管21的源极和漏极，第二有源层204的沟道区两侧设有两个不同掺杂类型的掺杂区，分别为第二晶体管22的源极和漏极。所述第一源漏导电层214包括第一源极导电部2141和第一漏极导电部2142，所述第二源漏导电层215包括第二源极导电部2151和第二漏极导电部2152，所述第三源漏导电层216包括第三源极导电部2161和第三漏极导电部2162，所述第一源极导电部2141通过所述第二平坦化层2172上的第一过孔与所述第二源极导电部2151连接，所述第一漏极导电部2142通过所述第二平坦化层2172上的第二过孔与所述第二漏极导电部2152连接，所述第二源极导电部2151通过所述第一平坦化层2171上的第三过孔与所述第三源极导电部2161连接，所述第二漏极导电部2152通过所述第一平坦化层2171上的第四过孔与所述第三漏极导电部2162连接，所述第三源极导电部2161通过第五过孔所述晶体管的源极连接，所述第三漏极导电部2162通过第六过孔与晶体管的漏极连接。
发光层3包括像素界定层31，像素界定层31设置于第三平坦化层218远离阵列基板的一侧。像素界定层31具有多个像素开口311，发光层3可以包括多个发光单元32，多个发光单元32分别设于不同的像素开口311内，每个发光单元32可以包括像素电极321、发光材料层322和公共电极323，像素电极321位于第三平坦化层218远离衬底基板1的表面，所述像素电极321通过所述第三平坦化层218上的第七过孔与所述第一漏极导电部2142连接，发光材料层322设于像素电极321和像素定义层远离衬底基板1的一侧，公共电极323设于发光材料层322远离衬底基板1的一侧。通过像素电极321和公共电极323可驱动发光元件发光，以显示图像。
公共电极323可作为阴极，像素电极321可作为阳极，可通过向像素电极321施加信号驱动发光元件发光，具体发光原理在此不再详述。发光元件可包含电致有机发光材料，并可采用蒸镀等工艺形成。例如，发光元件可包括依次层叠于像素电极321层上的空穴注入层、空穴传输层、光产生层、电子传输层和电子注入层。需要说明的是，发光元件根据发光颜色的不同，可以包括红色发光元件、绿色发光元件和蓝色发光元件。
由于发光材料层322保护相互串联的多个子发光层3组，相邻两个子发光层3组之间设有电荷产生层(charge-generation layer，CGL)，电荷产生层为共通层，具有较强的导电性，容易引起侧向漏电，容易导致相邻两个发光单元32之间发生串扰。为了尽量避免串扰问题出现，在像素电极321靠近衬底基板1的一侧设置隔断层33，在隔断层33和像素定义层位于相邻两个所述像素开口311之间的部分设置隔断槽35，将所述发光材料层322在所述隔断槽35内隔断，公共电极323在隔断槽35可以断裂，当然也可以不断裂，不会对显示效果造成影响。所述隔断槽35包括沿远离衬底基板1的方向依次设置第一槽段351和第二槽段352，所述第一槽段351贯穿所述隔断层33，所述第二槽段352贯穿所述像素界定层31，所述第一槽段351在所述衬底基板1上的正投影位于所述第二槽段352在所述衬底基板1上的正投影内。
如图2至图16所示，在显示面板的制作过程中，为了保证掩膜板与衬底基板1上已形成膜层的对位精度，使得掩膜工艺完成后，各个膜层的掩膜图案落在衬底基板1的对应位置上，通常会在外围区200设置对位标记4，通过对位标记4来校准掩膜板的设置位置。需要说明的是，外围区200围绕显示区100的外周设置。对位标记4可以包括第一对位标记41、第二对位标记42、第三对位标记43、第四对位标记44、第五对位标记45、第六对位标记46和第七对位标记47，第一对位标记41位于所述第一源漏导电层214，可以与第一源极导电部2141和第一漏极导电部2142同层同材料设置，第二对位标记42位于第二源漏导电层215，第三对位标记43位于第三源漏导电层216，第四对位标记44与第二栅极2091同层同材料设置，第五对位标记45与第一栅极2081同层同材料设置，第六对位标记46与第一有源层203同层同材料设置，第七对位标记47与遮光层201同层同材料设置。
第一缓冲层202是透明的，在形成图案化的第一有源层203时，曝光机通过第七对位标记47进行对位。在形成图案化的第一栅极2081时，第一栅绝缘层205是透明的，曝光机通过第六对位标记46进行对位。在形成图案化的第二栅极2091时，曝光机与第五对位标记45进行对位，此时第二栅极层209已经完成膜层沉积，膜层沉积所形成的整层第二栅极层209会在与第五对位标记45正对的位置形成第一对位凸起。第二有源层204是透明的，在形成图案化的第二有源层204时，曝光机与第四对位标记44进行对位。在形成图案化的第三栅极2101时，曝光机同样可以通过第四对位标记44进行对位，此时第三栅极层210已经完成膜层沉积，膜层沉积形成的整层第三栅极层210会在与第四对位标记44正对的位置形成第二对位凸起。第一层间介质层211是透明的，在第一层间介质层211上形成过孔时，曝光机与第四对位标记44进行对位。
在形成图案化的第三源漏导电层216时，曝光机同样可以通过第六对位标记46进行对位，此时第三源漏导电层216已经完成膜层沉积，膜层沉积形成的整层第三源漏导电层216会在与第六对位标记46正对的位置形成第三对位凸起。保护层213是透明的，在形成保护层213时，曝光机与第三对位标记43进行对位。第二平坦化层2172时透明的，在第二平坦化层2172上形成过孔时，曝光机与第三对位标记43进行对位。在形成图案化的第二源漏导电层215时，曝光机可以通过第三对位标记43进行对位，此时第二源漏导电层215已经完成膜层沉积，膜层沉积形成的整层第二源漏导电层215会在与第三对位标记43正对的位置形成第四对位凸起。第一平坦化层2171是透明的，在第一平坦化层2171上形成过孔时，曝光机与第二对位标记42进行对位。在形成图案化的第一源漏导电层214时，曝光机可以通过第二对位标记42进行对位，此时第一源漏导电层214已经完成膜层沉积，膜层沉积形成的整层第一源漏导电层214会在与第二对位标记42正对的位置形成第五对位凸起。第三平坦化层218是透明的，在第三平坦化层218形成过孔时，曝光机与第一对位标记41进行对位。
在形成图案化的像素电极321时，曝光机可以通过第一对位标记41进行对位，此时像素电极321层已经完成膜层沉积，膜层沉积形成的整层像素电极321层会在与第一对位标记41正对的位置形成第六对位凸起。第一栅绝缘层205、第二栅绝缘层206、像素界定层31、第一层间介质层211、第二层间介质层212、第二平坦化层2172、第一平坦化层2171、第三平坦化层218和像素界定层31是透明的，在形成像素界定层31时，曝光机与第六对位标记46进行对位。如图1所示，第一对位标记41设于第一平坦化层2171远离衬底基板1的一侧，钝化层34覆盖第一对位标记41，钝化层34远离衬底基板1的一侧设有第一覆盖层36，第一覆盖层36远离衬底基板1的一侧设有第二覆盖层37，第一覆盖层36与像素电极321同层同材料设置，第二覆盖层37与公共电极323同层同材料设置。
如图17所示，在显示面板的制作过程中，在一整面衬底5上设置多个显示区100，将各个显示面板的驱动电路层2和发光层3形成于不同的显示区100。为了保证对位精度，需要在第一方向和第二方向分别设置一定数量的对位标记4。在本实施例中，可以沿第二方向在整面衬底5的两端分别设置一行对位标记4，在两端的两行对位标记4之间设置沿第二方向间隔分布的两组对位标记4，每组对位标记4可以包括相邻设置的三行对位标记4。沿第一方向设置十一列对位标记4，其中两列对位标记4沿第一方向位于整面衬底5的两端，其余列的对位标记4沿第一方向位于相邻两列显示区100之间。
如图18至图22所示，为了避免第一对位标记41被水氧侵蚀，像素电极321层与第一对位标记41之间设有钝化层34，钝化层34覆盖第一对位标记41。所述钝化层34设有水汽释放口341，所述水汽释放口341在所述衬底基板1上的正投影与所述第一对位标记41在所述衬底基板1上的正投影交叠。钝化层34与第一对位标记41之间的水汽可以通过水汽释放口341逸出，大大避免了钝化层34与第一对位标记41之间出现剥离的可能性。
由于钝化层34具有超强的隔绝水氧的能力，第二平坦化层2172与钝化层34之间的水分无法有效释放出去，在经过像素电极321的形成过程的高温工艺时，水汽在第一对位标记41与钝化层34的接触面运动加剧，最终也会导致钝化层34剥离。因此可以扩大水汽释放口341的覆盖范围，使得所述水汽释放口341在所述衬底基板1上的正投影与所述第一对位标记41和所述易剥离区在所述衬底基板1上的正投影均交叠。
如图21所示，所述第一对位标记41为十字形，包括第一对位部411和第二对位部412，所述第一对位部411沿第一方向延伸，所述第二对位部412沿第二方向延伸，所述第一方向与所述第二方向相互垂直，所述第一对位部411与第二对位部412相互交叉。可以将第一对位标记41和位于第一对位标记41外围的易剥离区直接去掉，也就是第一对位标记41在衬底基板1上的正投影和易剥离区在衬底基板1上的正投影，均位于水汽释放口341在衬底基板1上的正投影内，直接在第一对位标记41和第二平坦化层2172远离衬底基板1的一侧覆盖将像素电极321，公共电极323覆盖像素电极321远离衬底基板1的一侧。
如图22所示，也可以在钝化层34上设置四个第一水汽释放孔3411，所述第一水汽释放孔3411包括首尾相连的第一条形部3413和第二条形部3414，所述第一条形部3413与所述第一对位部411相互平行，所述第二条形部3414与所述第二对位部412相互平行，四个第一水汽释放孔3411的第一对位部411沿第二方向间隔且对称，四个第一水汽释放孔3411的第二对位部412沿第一方向间隔且对称。第一对位标记41的外围形成四个易剥离区，四个所述易剥离区分别设有多个阵列排布的所述第二水汽释放孔3412，多个第二水汽释放孔3412沿第一方向排成多行，且沿第二方向排成多列。可以理解的是，多个第二水汽释放孔3412排成矩形阵列。
本公开实施方式还提供了一种显示装置，该显示装置可以包括本公开实施方式上面提到的显示面板。显示面板的具体结构和有益效果在上面已经进行了详细说明，因此，此处不再赘述。
需要说明的是，该显示装置除了显示面板以外，还包括其他必要的部件和组成，具体例如外壳、电路板、电源线，等等，本领域技术人员可根据该显示装置的具体使用要求进行相应地补充，在此不再赘述。
显示装置可以是传统电子设备，例如：手机、电脑、电视和摄录放影机，也可以是新兴的穿戴设备，例如：虚拟现实设备和增强现实设备，在此不一一进行列举。
需要说明的是，上述实施例之间是互通的，可以相互组合形成其他方案，本公开的方案并不局限于上述实施例中所记载的方案。本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (14)

  1. 一种显示面板，具有显示区和位于所述显示区外围的外围区，其中，所述显示面板包括：
    衬底基板；
    平坦化层组，设于所述衬底基板的一侧；
    第一源漏导电层，设于所述平坦化层组远离所述衬底基板的一侧，所述第一源漏导电层包括第一对位标记，所述第一对位标记位于所述外围区；
    钝化层，设于所述第一源漏导电层远离所述衬底基板的一侧，所述钝化层设有水汽释放口，所述水汽释放口在所述衬底基板上的正投影至少与所述第一对位标记在所述衬底基板上的正投影交叠。
  2. 根据权利要求1所述的显示面板，其中，所述平坦化层组具有易剥离区，所述易剥离区设于所述第一对位标记的外围，所述水汽释放口在所述衬底基板上的正投影与所述第一对位标记和所述易剥离区在所述衬底基板上的正投影均交叠。
  3. 根据权利要求2所述的显示面板，其中，所述第一对位标记和所述易剥离区在所述衬底基板上的正投影位于所述水汽释放口在所述衬底基板上的正投影内，露出所述第一对位标记远离所述衬底基板的一面、所述第一对位标记的侧面以及所述易剥离区远离衬底基板的一面。
  4. 根据权利要求2所述的显示面板，其中，所述水汽释放口包括第一水汽释放孔和第二水汽释放孔，所述第一水汽释放孔在衬底基板上的正投影与所述第一对位标记在所述衬底基板上的正投影交叠，所述第二水汽释放孔在衬底基板上的正投影与所述易剥离区在所述衬底基板上的正投影交叠。
  5. 根据权利要求4所述的显示面板，其中，所述第一对位标记包括第一对位部和第二对位部，所述第一对位部与所述第二对位部相互交叉，所述第一对位部沿第一方向延伸，所述第二对位部沿第二方向延伸，所述第二方向与所述第一方向相互垂直，所述第一水汽释放孔包括首尾相连的第一条形部和第二条形部，所述第一条形部与所述第一对位部相互平行，所述第二条形部与所述第二对位部相互平行。
  6. 根据权利要求5所述的显示面板，其中，所述钝化层上设有四个第一水汽释放孔，四个所述第一水汽释放孔的第一对位部沿第二方向间隔且对称，四个所述第一水汽释放孔的第二对位部沿第一方向间隔且对称。
  7. 根据权利要求5或6所述的显示面板，其中，各所述第一水汽释放孔的外围分别形成一个所述易剥离区，四个所述易剥离区分别设有多个阵列排布的所述第二水汽释放孔。
  8. 根据权利要求1所述的显示面板，其中，所述显示面板还包括：
    隔断层，与所述钝化层同层设置，且位于所述显示区；
    多个像素电极，设于所述钝化层远离所述衬底基板的一侧；
    像素界定层，设于所述像素电极远离所述衬底基板的一侧，所述像素界定层设有露出各个所述像素电极的像素开口；
    发光材料层，设于所述像素界定层远离所述衬底基板的一侧；
    相邻两个所述像素开口之间设有隔断槽，所述发光材料层在所述隔断槽内被隔断，所述隔断槽贯穿所述像素界定层，并穿过至少部分所述隔断层。
  9. 根据权利要求8所述的显示面板，其中，所述隔断槽包括沿远离衬底基板的方向依次设置第一槽段和第二槽段，所述第一槽段贯穿所述隔断层，所述第二槽段贯穿所述像素界定层，所述第一槽段在所述衬底基板上的正投影位于所述第二槽段在所述衬底基板上的正投影内。
  10. 根据权利要求8所述的显示面板，其中，所述显示面板还包括晶体管层，所述晶体管层设于所述第一源漏导电层与所述衬底基板之间，所述晶体管层包括至少一个晶体管，所述第一源漏导电层包括第一源极导电部和第一漏极导电部，所述第一源极导电部和第二漏极导电部位于所述显示区，所述第一源极导电部与所述晶体管的源极连接，所述第一漏极导电部与所述晶体管的漏极连接，所述像素电极与所述第一漏极导电部连接。
  11. 根据权利要求10所述的显示面板，其中，所述显示面板还包括第二源漏导电层和第三源漏导电层，所述第二源漏导电层设于所述第一源漏导电层与所述晶体管层之间，所述第三源漏导电层设于所述第二源漏导电层与所述晶体管层之间，所述平坦化层组包括第二平坦化层和第一平坦化层，所述第二平坦化层远离所述第一源漏导电层与所述第二源漏导电层之间，所述第一平坦化层设于所述第二源漏导电层与所述第三源漏导电层之间，所述第二源漏导电层包括第二源极导电部和第二漏极导电部，所述第三源漏导电层包括第三源极导电部和第三漏极导电部，所述第一源极导电部通过所述第二平坦化层上的第一过孔与所述第二源极导电部连接，所述第一漏极导电部通过所述第二平坦化层上的第二过孔与所述第二漏极导电部连接，所述第二源极导电部通过所述第一平坦化层上的第三过孔与所述第三源极导电部连接，所述第二漏极导电部通过所述第一平坦化层上的第四过孔与所述第三漏极导电部连接，所述第三源极导电部通过第五过孔所述晶体管的源极连接，所述第三漏极导电部通过第六过孔与所述晶体管的漏极连接。
  12. 根据权利要求11所述的显示面板，其中，所述显示面板还包括第三平坦化层，所述第三平坦化层设于所述钝化层与所述第一源漏导电层之间，所述像素电极通过所述第三平坦化层上的第七过孔与所述第一漏极导电部连接。
  13. 根据权利要求11所述的显示面板，其中，所述晶体管层包括第一有源层、第二有源层、第一栅极、第二栅极和第三栅极，所述第一有源层设于所述衬底基板的一侧，所述第一栅极设于所述第一有源层远离所述衬底基板的一侧，所述第一栅极在所述衬底基板上的正投影与所述第一有源层的沟道区在所述衬底基板上的正投影交叠，形成第一晶体管，所述第二栅极设于所述第一栅极远离所述衬底基板的一侧，所述第二有源层设于所述第二栅极远离所述衬底基板的一侧，所述第三栅极设于所述第二栅极远离所述衬底基板的一侧，所述第二栅极和所述第三栅极与所述第二有源层的沟道区在所述衬底基板上的正投影交叠，形成第二晶体管，所述第一有源层的材料为低温多晶硅，所述第二有源层的材料为铟镓锌氧化物。
  14. 一种显示装置，其中，包括权利要求1至13任一项所述的显示面板。
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