WO2025246730A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置

Info

Publication number
WO2025246730A1
WO2025246730A1 PCT/CN2025/090203 CN2025090203W WO2025246730A1 WO 2025246730 A1 WO2025246730 A1 WO 2025246730A1 CN 2025090203 W CN2025090203 W CN 2025090203W WO 2025246730 A1 WO2025246730 A1 WO 2025246730A1
Authority
WO
WIPO (PCT)
Prior art keywords
initialization
circuit region
voltage
heterogeneous
sub
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/090203
Other languages
English (en)
French (fr)
Inventor
张跳梅
王梦奇
陈文波
于子阳
吴建鹏
承天一
蒋志亮
胡明
陶璇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025246730A1 publication Critical patent/WO2025246730A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • This disclosure relates to the field of display panel technology, and more specifically, to a display panel and a display device.
  • the purpose of this disclosure is to overcome the shortcomings of the prior art and provide a display panel and display device that helps to reduce the voltage drop of the power signal on the display panel.
  • a display panel including an array of circuit regions, the circuit regions being provided with two pixel driving circuits for driving two sub-pixels respectively;
  • the display panel includes a substrate, a transistor layer, a first source/drain metal layer, a second source/drain metal layer, and a pixel layer that are stacked sequentially.
  • the transistor layer is provided with each thin-film transistor of the pixel driving circuit; at least one of the transistor layer and the first source/drain metal layer is provided with a voltage trace extending along the row direction.
  • the second source/drain metal layer is provided with a power voltage trace for loading power supply voltage
  • the first source/drain metal layer is provided with a power voltage conversion structure in the circuit area; the power voltage conversion structure is electrically connected to the power voltage trace and is used to simultaneously provide power supply voltage to the two pixel driving circuits in the circuit area.
  • the circuit region includes a non-heterogeneous circuit region and a heterogeneous circuit region.
  • the shape of the power supply voltage transfer structure in the heterogeneous circuit region is different from that in the non-heterogeneous circuit region, so that the first source-drain metal layer has a cross-line channel extending along the column direction in the heterogeneous circuit region.
  • the first source-drain metal layer is provided with a voltage jumper in the cross-line channel, and the voltage jumper is electrically connected to two adjacent voltage lines in the column direction.
  • the voltage trace includes a reference voltage trace disposed on the first source-drain metal layer and used for loading a reference voltage.
  • the heterogeneous circuit region includes a reference heterogeneous circuit region, and the voltage jumper includes a reference voltage jumper located in the reference heterogeneous circuit region, wherein the reference voltage jumper electrically connects two adjacent reference voltage traces along the column direction.
  • the voltage trace further includes an initialization voltage trace located in the transistor layer and used to apply an initialization voltage to the pixel driving circuit;
  • the heterogeneous circuit region further includes an initialization heterogeneous circuit region
  • the voltage jumper further includes an initialization voltage jumper, which is located in the initialization heterogeneous circuit region and makes two adjacent initialization voltage traces along the column direction electrically connected.
  • the reference voltage trace is interrupted at the cross-line channel in the initialization heterogeneous circuit area, and the initialization voltage jumper passes through the interruption gap of the reference voltage trace.
  • initialization voltage traces there are at least two types of initialization voltage traces, and in each of the initialization heterogeneous circuit regions, only one type of initialization voltage trace is provided with an initialization voltage jumper.
  • the power supply voltage transfer structure has a first sub-transfer structure, a second sub-transfer structure, and a third sub-transfer structure;
  • the first sub-transfer structure extends along the column direction and is located in the middle of the non-heterogeneous circuit region in the row direction, for simultaneously providing the driving power supply voltage to two pixel driving circuits;
  • the second sub-transfer structure and the third sub-transfer structure are respectively located on both sides of the first sub-transfer structure and are respectively electrically connected to the power supply voltage trace through vias;
  • the power supply voltage switching structure consists of a first sub-switching structure and a second sub-switching structure.
  • the first source/drain metal layer is further provided with an initialization voltage transfer structure in the circuit region, and the voltage trace includes an initialization voltage trace located in the transistor layer and used for loading an initialization voltage; the initialization voltage transfer structure is electrically connected to the initialization voltage trace and is used to simultaneously provide the initialization voltage to two pixel driving circuits in the circuit region.
  • the initialization voltage transfer structure in the non-heterogeneous circuit region has a different shape than the initialization voltage transfer structure in the heterogeneous circuit region, so that the initialization voltage transfer structure in the heterogeneous circuit region avoids the cross-line channel.
  • the initialization voltage transition structure in the non-heterogeneous circuit region, includes a fourth sub-transition structure, a fifth sub-transition structure, and a sixth sub-transition structure connected in sequence; the fifth sub-transition structure and the sixth sub-transition structure are respectively disposed on both sides of the fourth sub-transition structure in the row direction, and are respectively used to electrically connect with the initialization voltage trace through vias; the fourth sub-transition structure simultaneously provides the initialization voltage to two pixel driving circuits in the circuit region through vias;
  • the initialization voltage switching structure consists of the fourth sub-switching structure and the fifth sub-switching structure.
  • the circuit region includes a first sub-circuit region and a second sub-circuit region adjacent to each other along the row direction; the first sub-circuit region and the second sub-circuit region are respectively provided with the pixel driving circuit; the cross-line channel of the heterogeneous circuit region is provided in the first sub-circuit region of the heterogeneous circuit region;
  • the pattern of the first source/drain metal layer in the first sub-circuit region is symmetrically arranged with respect to the pattern in the second sub-circuit region.
  • the pattern of the first source/drain metal layer in the second sub-circuit region of the non-heterogeneous circuit region is the same as the pattern in the second sub-circuit region of the heterogeneous circuit region.
  • the pattern of the first source/drain metal layer in the first sub-circuit region of the heterogeneous circuit region is different from the pattern in the first sub-circuit region of the non-heterogeneous circuit region.
  • the pattern of the first source-drain metal layer in the area outside the cross-line channel of the first sub-circuit region of the heterogeneous circuit region is the same as the pattern of the first source-drain metal layer in the same area of the first sub-circuit region of the non-heterogeneous circuit region.
  • the pattern of the semiconductor layer in the first sub-circuit region is axially symmetrical with the pattern in the second sub-circuit region.
  • the non-heterogeneous circuit area and the heterogeneous circuit area are alternately arranged.
  • the non-heterogeneous circuit regions and the heterogeneous circuit regions are alternately arranged in the circuit region array.
  • the voltage trace includes a reference voltage trace disposed on the first source/drain metal layer and an initialization voltage trace disposed on the transistor layer; the reference voltage trace is used to apply a reference voltage, and the initialization voltage trace is used to apply an initialization voltage to the pixel driving circuit.
  • the heterogeneous circuit region includes a reference heterogeneous circuit region and an initialization heterogeneous circuit region; the first source-drain metal layer is provided with a reference voltage jumper in the reference heterogeneous circuit region to electrically connect two adjacent reference voltage lines; the first source-drain metal layer is provided with an initialization voltage jumper in the initialization heterogeneous circuit region to electrically connect two adjacent initialization voltage lines.
  • At least one reference heterogeneous circuit region is provided between two adjacent initialization heterogeneous circuit regions.
  • the initialization voltage trace includes a first initialization voltage trace for loading a first initialization voltage, a second initialization voltage trace for loading a second initialization voltage, and a third initialization voltage trace for loading a third initialization voltage;
  • the initialization heterogeneous circuit region includes a first initialization heterogeneous circuit region with a first initialization voltage jumper on the first source-drain metal layer, a second initialization heterogeneous circuit region with a second initialization voltage jumper on the first source-drain metal layer, and a third initialization heterogeneous circuit region with a third initialization voltage jumper on the first source-drain metal layer;
  • the first initialization voltage jumper electrically connects two adjacent first initialization voltage traces
  • the second initialization voltage jumper electrically connects two adjacent second initialization voltage traces
  • the third initialization voltage jumper electrically connects two adjacent third initialization voltage traces;
  • the first initialization heterogeneous circuit region, the second initialization heterogeneous circuit region, the third initialization heterogeneous circuit region and the second initialization heterogeneous circuit region are arranged in a periodic sequence.
  • the initialization voltage trace includes a first initialization voltage trace for loading a first initialization voltage, a second initialization voltage trace for loading a second initialization voltage, and a third initialization voltage trace for loading a third initialization voltage;
  • the initialization heterogeneous circuit region includes a first initialization heterogeneous circuit region with a first initialization voltage jumper on the first source-drain metal layer, a second initialization heterogeneous circuit region with a second initialization voltage jumper on the first source-drain metal layer, and a third initialization heterogeneous circuit region with a third initialization voltage jumper on the first source-drain metal layer;
  • the first initialization voltage jumper electrically connects two adjacent first initialization voltage traces
  • the second initialization voltage jumper electrically connects two adjacent second initialization voltage traces
  • the third initialization voltage jumper electrically connects two adjacent third initialization voltage traces;
  • the initialization heterogeneous circuit areas in one row are arranged periodically in the order of the first initialization heterogeneous circuit area, the second initialization heterogeneous circuit area, the third initialization heterogeneous circuit area, and the second initialization heterogeneous circuit area.
  • the initialization heterogeneous circuit area is arranged in a periodic sequence according to the third initialization heterogeneous circuit area, the second initialization heterogeneous circuit area, the first initialization heterogeneous circuit area, and the second initialization heterogeneous circuit area.
  • the voltage trace includes a reference voltage trace disposed on the first source/drain metal layer and an initialization voltage trace disposed on the transistor layer; the reference voltage trace is used to apply a reference power supply voltage, and the initialization voltage trace is used to apply an initialization voltage to the pixel driving circuit.
  • the heterogeneous circuit region includes a reference heterogeneous circuit region and an initialization heterogeneous circuit region; the first source-drain metal layer is provided with a reference voltage jumper in the reference heterogeneous circuit region to electrically connect two adjacent reference voltage traces; the first source-drain metal layer is provided with an initialization voltage jumper in the initialization heterogeneous circuit region to electrically connect two adjacent initialization voltage traces; each heterogeneous circuit region in the same circuit region column is the same.
  • the voltage trace includes an initialization voltage trace disposed on the transistor layer; the initialization voltage trace is used to apply an initialization voltage to the pixel driving circuit.
  • the circuit region has an initialization voltage transfer structure in the first source-drain metal layer.
  • the initialization voltage transfer structure is electrically connected to the initialization voltage trace and the thin film transistor through a via, so that the initialization voltage is applied to the pixel driving circuit.
  • the heterogeneous circuit region includes an initialization heterogeneous circuit region; the first source-drain metal layer is provided with an initialization voltage jumper in the initialization heterogeneous circuit region, and the two ends of the initialization voltage jumper are respectively electrically connected to two adjacent initialization voltage transfer structures in the same column.
  • the display panel further includes a second planarization layer, a third source-drain metal layer, and a third planarization layer stacked sequentially on the side of the second source-drain metal layer away from the first source-drain metal layer; the third source-drain metal layer is provided with a reference voltage grid; the pixel layer is disposed on the side of the third planarization layer away from the second source-drain metal layer; and a plurality of sub-pixels are disposed in the cutout holes of the reference voltage grid.
  • the reference voltage grid has a first reference voltage line segment extending along the column direction; along the row direction, the first reference voltage line segment is located between a blue sub-pixel and a red sub-pixel; wherein the distance between the first reference voltage line segment and the blue sub-pixel is greater than the distance between the first reference voltage line segment and the red sub-pixel.
  • a display device including the display panel.
  • Figure 1 is a schematic diagram of the film layer structure of the display panel in one embodiment of this disclosure.
  • Figure 2 is a schematic diagram of the distribution of the circuit area in the display panel in one embodiment of this disclosure.
  • Figure 3 is a schematic diagram of the reference voltage jumper and the initialization voltage jumper in one embodiment of this disclosure.
  • Figure 4 is a schematic diagram of a pixel driving circuit in one embodiment of this disclosure.
  • Figure 5-1 is a schematic diagram of the arrangement of heterogeneous circuit regions and non-heterogeneous circuit regions in one embodiment of this disclosure.
  • Figure 5-2 is a schematic diagram of the arrangement of heterogeneous circuit regions and non-heterogeneous circuit regions in one embodiment of this disclosure.
  • Figure 6 is a schematic diagram of the structure of a low-temperature polycrystalline silicon semiconductor layer in one embodiment of this disclosure.
  • Figure 7 is a schematic diagram of the structure of the first gate layer in one embodiment of this disclosure.
  • Figure 8 is a schematic diagram of the structure of the second gate layer in one embodiment of this disclosure.
  • Figure 9 is a schematic diagram of the structure of a metal oxide semiconductor layer in one embodiment of this disclosure.
  • Figure 10 is a schematic diagram of the structure of the third gate layer in one embodiment of this disclosure.
  • Figure 11 is a schematic diagram of the structure of the first source/drain metal layer in a non-heterogeneous circuit region in one embodiment of this disclosure.
  • Figure 12 is a schematic diagram of the structure of the second source/drain metal layer in one embodiment of this disclosure.
  • Figure 13 is a schematic diagram of the structure of the first source/drain metal layer in the reference heterogeneous circuit region in one embodiment of the present disclosure.
  • Figure 14 is a schematic diagram of the structure of the first source/drain metal layer in the first initialization heterogeneous circuit region in one embodiment of the present disclosure.
  • Figure 15 is a schematic diagram of the structure of the first source/drain metal layer in the second initialization heterogeneous circuit region in one embodiment of this disclosure.
  • Figure 16 is a schematic diagram of the structure of the first source/drain metal layer in the third initialization heterogeneous circuit region in one embodiment of this disclosure.
  • Figure 17 is a schematic diagram of the structure of the third gate layer in one embodiment of this disclosure.
  • Figure 18 is a schematic diagram of the structure of the third source/drain metal layer in one embodiment of this disclosure.
  • Figure 19 is a schematic diagram of the partial stacking of the second source/drain metal layer and the third source/drain metal layer and the arrangement of sub-pixels in one embodiment of this disclosure.
  • Figure 20-1 is a schematic diagram of the arrangement of heterogeneous circuit regions and non-heterogeneous circuit regions in one embodiment of this disclosure.
  • Figure 20-2 is a schematic diagram of the arrangement of heterogeneous circuit regions and non-heterogeneous circuit regions in one embodiment of this disclosure.
  • Figure 21 is a schematic diagram of the first initialization voltage jumper wire in one embodiment of this disclosure.
  • Figure 22 is a schematic diagram of the second initialization voltage jumper wire in one embodiment of this disclosure.
  • Figure 23 is a schematic diagram of a reference voltage jumper wire in one embodiment of this disclosure.
  • Figure 24 is a schematic diagram of the third initialization voltage jumper wire in one embodiment of this disclosure.
  • Figure 25 is a schematic diagram of the first initialization voltage jumper wire in one embodiment of this disclosure.
  • Figure 26 is a schematic diagram of the third initialization voltage jumper wire in one embodiment of this disclosure.
  • Figure 27 is a schematic diagram of the distribution of the second initialization heterogeneous circuit region in one embodiment of this disclosure.
  • Figure 28 is a schematic diagram of the distribution of the third initialization heterogeneous circuit region in one embodiment of this disclosure.
  • PA circuit area; PA1, first sub-circuit area; PA2, second sub-circuit area; PAN, Non-heterogeneous circuit region; PAM, heterogeneous circuit region; PAMS, reference heterogeneous circuit region; PAMT, initialization heterogeneous circuit region; PAMT1, first initialization heterogeneous circuit region; PAMT2, second initialization heterogeneous circuit region; PAMT3, third initialization heterogeneous circuit region; VDDL, power supply voltage trace; VLA, voltage jumper; VSSW, reference voltage grid; VSSW1, first reference voltage segment; VSSW2, second reference voltage segment; VSSW3, third reference voltage segment; VSL, reference voltage trace; VSLA, reference voltage jumper; VTL, initialization voltage trace; VTL1, first initialization voltage trace; VTL2, second initialization voltage trace; VTL3, Third Initialization Voltage Line; VTLA, Initialization Voltage Jumper; VTL1A, First Initialization Voltage Jumper; VTL2A, Second Initialization Voltage Line; VTLA, Initialization Voltage
  • Second sub-transition structure MA62. Fifth sub-transition structure; MA63. Sixth sub-transition structure; SBT, substrate; DRL, driving layer; TL, transistor layer; LS, light-shielding layer; LSCL, low-temperature polysilicon semiconductor layer; Buff1, first buffer layer; Buff2, second buffer layer; GI1, first gate insulating layer; GI2, second gate insulating layer; GT1, first gate layer; GT2, second gate layer; GT3, third gate layer; ILD, interlayer dielectric layer; SD1, first source/drain metal layer; SD2, second source/drain metal layer; SD3, third source/drain metal layer; PLN1, first planarization layer; PLN2, second planarization layer; PLN3, third planarization layer; Tanning layer; OSCL, Metal-Oxide-Semiconductor Layer; PDL, Pixel Definition Layer; COML, Common Electrode Layer; EL, Light Emitting Layer; ANL, Pixel Electrode Layer; PIXL, Pixel Layer; PIX
  • Structural layer A is located on the side of structural layer B that faces away from the substrate. This can be understood as structural layer A being formed on the side of structural layer B that faces away from the substrate. When structural layer B is a patterned structure, some structures of structural layer A may also be located at the same physical height as structural layer B or at a lower physical height than structural layer B, where the substrate serves as the height reference.
  • the thin-film transistor includes an active layer, a gate insulating layer, and a gate, stacked together.
  • the active layer is located within the semiconductor layer and includes a channel region and a first electrode and a second electrode located on opposite sides of the channel region.
  • the channel region retains semiconductor characteristics, and both the first and second electrodes are conductive.
  • the functions of the "first electrode” and the “second electrode” are sometimes interchanged; that is, the "first electrode” and the "second electrode” can be interchanged.
  • one of the "first electrode” and the "second electrode” is referred to as the first electrode of the transistor, and the other is referred to as the second electrode of the transistor.
  • the present disclosure provides a display panel and a display device using the display panel.
  • the display panel may include a substrate SBT, a driving layer DRL, and a pixel layer PIXL stacked sequentially; the pixel layer PIXL is provided with light-emitting elements (not shown in this figure) serving as sub-pixels PIX, and the driving layer DRL is provided with a pixel driving circuit for driving the sub-pixels PIX; each sub-pixel PIX can emit light under the drive of the pixel driving circuit to display an image.
  • the display panel also includes a thin film encapsulation layer TFE located on the side of the pixel layer PIXL away from the driving layer DRL, the thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.
  • the substrate SBT can be an inorganic material substrate SBT or an organic material substrate SBT; of course, it can also be a composite substrate formed by stacking inorganic and organic material substrate SBTs.
  • the material of the substrate SBT can be glass materials such as soda-lime glass, quartz glass, and sapphire glass.
  • the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinylphenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or combinations thereof.
  • the substrate SBT can also be a flexible substrate SBT, for example, the material of the substrate SBT may include polyimide.
  • any pixel driving circuit may include a thin-film transistor and a storage capacitor CST (not shown in the accompanying drawings).
  • the thin-film transistor may be selected from top-gate, bottom-gate, or dual-gate thin-film transistors; the material of the active layer of the thin-film transistor may be amorphous silicon semiconductor material, low-temperature polycrystalline silicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, carbon nanotube semiconductor material, or other types of semiconductor material; the thin-film transistor may be an N-type or P-type thin-film transistor.
  • any two transistors in a pixel driving circuit can be of the same or different types.
  • some transistors in a pixel driving circuit can be N-type transistors and some transistors can be P-type transistors.
  • the active layer of some transistors may be made of low-temperature polycrystalline silicon (LTPS) semiconductor material, and the active layer of some transistors may be made of metal-oxide-semiconductor (MODS) semiconductor material.
  • LTPS low-temperature polycrystalline silicon
  • MODS metal-oxide-semiconductor
  • the thin-film transistor is an LTPS transistor.
  • some thin-film transistors are LTPS transistors, and some thin-film transistors are MODS transistors.
  • the driving layer DRL may include a semiconductor layer (e.g., a low-temperature polysilicon semiconductor layer LSCL and a metal-oxide-semiconductor layer OSCL as shown in FIG. 1), a gate insulating layer (e.g., a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3 as shown in FIG. 1), a gate layer (e.g., a first gate layer GT1, a second gate layer GT2, and a third gate insulating layer GT3 as shown in FIG.
  • a semiconductor layer e.g., a low-temperature polysilicon semiconductor layer LSCL and a metal-oxide-semiconductor layer OSCL as shown in FIG. 1
  • a gate insulating layer e.g., a first gate insulating layer GI1, a second gate insulating layer GI2, and a third gate insulating layer GI3 as shown in FIG.
  • an interlayer dielectric layer ILD source/drain metal layers (e.g., a first source/drain metal layer SD1, a second source/drain metal layer SD2, and a third source/drain metal layer SD3 as shown in FIG. 1), and a planarization layer (e.g., a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3 as shown in FIG. 1), etc., stacked between the substrate SBT and the pixel layer PIXL.
  • source/drain metal layers e.g., a first source/drain metal layer SD1, a second source/drain metal layer SD2, and a third source/drain metal layer SD3 as shown in FIG. 1
  • a planarization layer e.g., a first planarization layer PLN1, a second planarization layer PLN2, and a third planarization layer PLN3 as shown in FIG.
  • Each thin-film transistor and storage capacitor CST can be formed by the semiconductor layer, the gate insulating layer, the gate layer, the interlayer dielectric layer ILD, the source/drain metal layer, etc.; of course, other film layers can also be used.
  • the positional relationship of each film layer can be determined according to the film layer structure of the thin-film transistor.
  • the semiconductor layer can be used to form the channel region of the transistor (as part of the active layer), and can also be formed into partial traces or conductive structures by conductorization if necessary.
  • the gate layer can be used to form one or more gate layer traces such as scan traces, reset control traces, and light emission control traces, or it can be used to form the gate of the transistor, or it can be used to form part or all of the electrode plates of the storage capacitor CST.
  • the source/drain metal layer can be used to form source/drain metal layer traces such as data traces and power supply voltage traces VDDL (see Figure 12), or it can be used to form part of the electrode plates of the storage capacitor CST.
  • the driving layer DRL can also include other film layers as needed, such as a light-shielding layer LS located between the semiconductor layer and the substrate SBT.
  • any one of the aforementioned semiconductor layer, gate layer, source/drain metal layer, etc. can be multiple layers.
  • the driving layer DRL may include two different semiconductor layers, or two or three source/drain metal layers, or two or three gate layers.
  • the insulating film layers (such as gate insulating layer, interlayer dielectric layer ILD, planarization layer, etc.) in the driving layer DRL can be added or reduced as needed, or new insulating film layers can be added as needed.
  • the driving layer DRL may also include a passivation layer (not specifically labeled in this figure), which may be disposed on the surface of the source/drain metal layer away from the substrate SBT in order to protect the source/drain metal layer.
  • a passivation layer (not specifically labeled in this figure), which may be disposed on the surface of the source/drain metal layer away from the substrate SBT in order to protect the source/drain metal layer.
  • the driving layer DRL may include a buffer layer (e.g., the first buffer layer Buff1 and the second buffer layer Buff2 shown in FIG1), a semiconductor layer, a gate insulating layer, a gate layer, an interlayer dielectric layer ILD, a source drain metal layer and a planarization layer stacked in sequence, and the thin film transistor formed therein is a top gate thin film transistor.
  • the driving layer DRL may include a first buffer layer Buff1, a low-temperature polysilicon semiconductor layer LSCL, a first gate insulating layer GI1, a first gate layer GT1, a second buffer layer Buff2, a second gate insulating layer GI2, a second gate layer GT2, an interlayer dielectric layer ILD, a metal oxide semiconductor layer OSCL, a third gate insulating layer, a third gate layer GT3, a first source drain metal layer SD1, a first planarization layer PLN1, a second source drain metal layer SD2, a second planarization layer PLN2, a third source drain metal layer SD3, and a third planarization layer PLN3, stacked sequentially.
  • the pixel layer PIXL may include a pixel electrode layer ANL, a light-emitting functional layer EL, and a common electrode layer COML stacked sequentially.
  • the pixel electrode layer ANL has multiple pixel electrodes in the display area of the display panel (not specifically labeled in the accompanying drawings).
  • the pixel definition layer PDL has multiple through-holes corresponding to the multiple pixel electrodes, with each pixel hole exposing at least a portion of the corresponding pixel electrode.
  • the pixel definition layer PDL covers the edge of the pixel electrode and exposes at least a portion of the internal area of the pixel electrode, so that the pixel definition layer PDL can effectively define the actual effective area of the pixel electrode (the area directly connected to the light-emitting functional layer EL), thereby defining the light-emitting area and light-emitting region of the sub-pixel PIX.
  • the common electrode layer COML covers the light-emitting functional layer EL as a common electrode.
  • the pixel electrodes and the common electrode layer COML provide electrons, holes, and other charge carriers to the light-emitting functional layer EL, causing the light-emitting functional layer EL to emit light.
  • the portion of the light-emitting functional layer EL located between the pixel electrodes and the common electrode layer COML can serve as the light-emitting functional unit of the sub-pixel PIX.
  • a pixel electrode, a common electrode layer (COML), and a light-emitting functional unit form a light-emitting element that serves as a sub-pixel (PIX).
  • One of the pixel electrode and the common electrode layer (COML) serves as the anode of the sub-pixel (PIX), and the other serves as the cathode.
  • the display panel is an OLED (Organic Light Emitting Diode) display substrate.
  • the light-emitting functional layer EL may include an organic light-emitting layer, and may include one or more of the following: a hole injection layer, a hole transport layer, an electron blocking layer, an electron transport layer, and an electron injection layer.
  • the organic light-emitting layer may include a host material and a guest material, wherein the guest material may be a fluorescent dopant or a phosphorescent dopant, and particularly may be a thermally activated delayed fluorescence material.
  • the display panel can also be other types of display panels, such as QLED (electroluminescent quantum dot) display panels, QD-OLED (electroluminescent quantum dot and organic light-emitting diode) display panels, or other types of display panels.
  • QLED electroactive quantum dot
  • QD-OLED electroactive quantum dot and organic light-emitting diode
  • the thin-film encapsulation layer TFE can be disposed on the surface of the pixel layer PIXL away from the substrate SBT, and it can include alternating layers of inorganic and organic encapsulation layers.
  • the inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing material aging of the pixel layer PIXL.
  • the edge of the inorganic encapsulation layer can be located in the peripheral area.
  • the organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce stress between the inorganic encapsulation layers.
  • the edge of the organic encapsulation layer can be located between the edge of the display area and the edge of the inorganic encapsulation layer.
  • the thin-film encapsulation layer TFE includes a first inorganic encapsulation layer, an organic encapsulation layer, and a second inorganic encapsulation layer sequentially stacked on the side of the pixel layer PIXL away from the substrate SBT (not specifically shown in the accompanying drawings).
  • the display panel may not have a thin-film encapsulation layer TFE, but may use other methods to encapsulate and protect the pixel layer PIXL.
  • the display panel may further include a touch metal layer (not specifically shown in the accompanying drawings), which may be disposed on the side of the thin-film transistor away from the pixel layer PIXL, so that the display panel has touch functionality.
  • a touch metal layer (not specifically shown in the accompanying drawings), which may be disposed on the side of the thin-film transistor away from the pixel layer PIXL, so that the display panel has touch functionality.
  • the driving layer DRL may further include a transistor layer TL, a first source-drain metal layer SD1, and a second source-drain metal layer SD2;
  • the transistor layer TL is a combination of various film layers disposed between the substrate SBT and the first source-drain metal layer SD1, which can form various thin-film transistors required for the pixel driving circuit.
  • the display area of the display panel may include arrayed circuit regions PA, each circuit region PA having two pixel driving circuits for driving two sub-pixels PIX respectively.
  • the circuit region PA may include a first sub-circuit region PA1 and a second sub-circuit region PA2 arranged adjacently along the row direction DH.
  • the first sub-circuit region PA1 contains the thin-film transistors of one pixel driving circuit
  • the second sub-circuit region PA2 contains the thin-film transistors of another pixel driving circuit.
  • the capacitors of the pixel driving circuits may also be disposed within the transistors.
  • at least a portion of the structure of the first source-drain metal layer SD1 can be used as part of the capacitors.
  • At least one of the transistor layer TL and the first source-drain metal layer SD1 may be provided with a voltage trace VL extending along the row direction DH.
  • the voltage trace VL may provide a power supply voltage to the pixel driving circuit or reduce the voltage drop of the power supply voltage applied to the pixel driving circuit or the sub-pixel PIX.
  • the voltage trace VL may include a reference voltage trace VSL for loading a reference voltage VSS.
  • the reference voltage trace VSL may be electrically connected to the common electrode layer COML of the pixel layer PIXL to reduce the voltage drop of the reference voltage VSS, improve the uniformity of the reference voltage VSS, and thereby improve the image quality of the display panel.
  • the reference voltage trace VSL can be electrically connected to the common electrode layer COML in the peripheral area of the display panel. Furthermore, the reference voltage trace VSL can be located on the first source/drain metal layer SD1 of the drive layer DRL.
  • the reference voltage trace VSL can be configured in a one-to-one correspondence with each circuit area row HPA.
  • each circuit area PA has one reference voltage trace VSL. This maximizes the density of reference voltage traces VSL, thereby improving the uniformity of the reference voltage VSS.
  • the voltage trace VL may include an initialization voltage trace VTL for applying an initialization voltage to the pixel driving circuit, so as to reset the voltage of the node or pixel electrode of the pixel driving circuit. Further, the voltage trace VL may be disposed on the transistor layer TL, for example, on the gate layer of the transistor layer TL. It is understood that in this embodiment, the initialization voltage applied to the pixel driving circuit may be one or more. When multiple initialization voltages are applied to the pixel driving circuit, the voltage values of the multiple initialization voltages may be the same or different, and different types of initialization voltages are applied to different initialization voltage traces VTL.
  • the initialization voltage trace VTL may include a first initialization voltage trace VTL1 located on the second gate layer GT2 (see Figure 8), and a second initialization voltage trace VTL2 (see Figure 10) and a third initialization voltage trace VTL3 (see Figure 10) located on the third gate layer GT3.
  • the first initialization voltage trace VTL1 has a seventeenth lower via region HA17 at its end, which is connected to the seventeenth upper via region HB17 via a via region.
  • the second initialization voltage trace VTL2 has a sixteenth lower via region HA16 at its end, which is connected to the sixteenth upper via region HB16 via a via region.
  • the third initialization voltage trace VTL3 has a fifteenth upper via region HB15 overlapping with the fifteenth lower via region HA15, which is connected to the fifteenth upper via region HB15 via a via region.
  • the first electrode of the electrode reset transistor T7 is electrically connected to the second initialization voltage trace VTL2.
  • the initialization voltage trace VTL can be entirely located in the first source-drain metal layer SD1.
  • Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of this disclosure.
  • the initialization voltage includes a first initialization voltage Vinit1, a second initialization voltage Vinit2, and a third initialization voltage Vinit3, which are respectively applied to different nodes of the pixel driving circuit. Therefore, the transistor layer TL needs to have a first initialization voltage trace VTL1 (see Figure 8) for applying the first initialization voltage Vinit1, a second initialization voltage trace VTL2 (see Figure 10) for applying the second initialization voltage Vinit2, and a third initialization voltage trace VTL3 (see Figure 10) for applying the third initialization voltage Vinit3.
  • Each row of circuit regions PA needs to have a corresponding first initialization voltage trace VTL1, second initialization voltage trace VTL2, and third initialization voltage trace VTL3.
  • the pixel driving circuit may include a first capacitor reset transistor T1, a threshold compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, an electrode reset transistor T7, a second capacitor reset transistor T8, and a storage capacitor CST.
  • threshold compensation transistor T2 is an N-type thin-film transistor, such as a metal oxide thin-film transistor; the other thin-film transistors are P-type thin-film transistors, such as low-temperature polycrystalline silicon thin-film transistors.
  • the first terminal of the first capacitor reset transistor T1 is used to load the first initialization voltage Vinit1, the gate is used to load the first capacitor reset control signal Rest1, and the second terminal is connected to the third node N3.
  • the first capacitor reset transistor T1 is used to load the first initialization voltage Vinit1 onto the third node N3 in response to the first capacitor reset control signal Rest1.
  • the first terminal of the threshold compensation transistor T2 is electrically connected to the third node N3, the second terminal is electrically connected to the first node N1, and the gate is used to load the first scan signal GN.
  • the threshold compensation transistor T2 is used to turn on in response to the first scan signal GN to write the first initialization voltage Vinit1 of the first capacitor reset transistor T1 into the first node N1.
  • the first terminal of the driving transistor T3 is connected to the second node N2, the second terminal is connected to the third node N3, and the gate is connected to the first node N1.
  • the driving transistor T3 is configured to output a driving current under the control of the voltage at the control terminal of the driving transistor T3.
  • the first terminal of the data writing transistor T4 is used to load the drive data signal Source, the second terminal is electrically connected to the second node N2, and the gate is used to load the second scan signal GP.
  • the gate of the data writing transistor T4 is used to load the second scan signal GP, while the drive data signal Source is loaded to the second node N2.
  • the first terminal of the first light-emitting control transistor T5 is electrically connected to the fifth node N5, the second terminal is connected to the second node N2, and the gate is used to load the enable signal EM.
  • the first terminal of the second light-emitting control transistor T6 is connected to the third node N3, the second terminal is connected to the fourth node N4, and the gate is used to load the enable signal EM.
  • the first and second light-emitting control transistors T5 and T6 are turned on in response to the enable signal EM.
  • the first terminal of the electrode reset transistor T7 is used to load the second initialization voltage Vinit2, the gate is used to load the second capacitor reset control signal Rest2, and the second terminal is connected to the fourth node N4.
  • the electrode reset transistor T7 is used to load the second initialization voltage Vinit2 to the fourth node N4 in response to the second capacitor reset control signal Rest2.
  • the first terminal of the second capacitor reset transistor T8 is used to apply the third initialization voltage Vinit3, and the gate is used to apply the second capacitor reset control signal Rest2.
  • the second terminal is connected to the second node N2.
  • the second capacitor reset transistor T8 is used to apply the third initialization voltage Vinit3 to the second node N2 in response to the second capacitor reset control signal Rest2.
  • the pixel electrode of the light-emitting element is electrically connected to the driving circuit (not specifically shown in this application), and the common electrode is used to apply the reference voltage VSS.
  • One end of the storage capacitor CST is connected to the first node N1, and the other end is connected to the fifth node N5.
  • the pixel driving circuit may also adopt other forms of pixel driving circuit, such as 7T1C (7 thin film transistors and 1 storage capacitor), 7T2C (7 thin film transistors and 2 storage capacitors), 5T1C (5 thin film transistors and 1 storage capacitor), etc.
  • the distribution of the power signal loaded on the voltage trace VL can be made gridded.
  • a voltage jumper VLA can be provided on the first source-drain metal layer SD1.
  • the voltage jumper VLA can electrically connect two adjacent identical voltage traces VL, thereby making the voltage trace VL gridded. This can further reduce the voltage drop of the power signal loaded on the voltage trace VL.
  • the circuit region PA can be divided into a non-heterogeneous circuit region PAN and a heterogeneous circuit region PAM according to whether a voltage jumper line VLA is provided (see FIG3).
  • the pattern of the first source-drain metal layer SD1 of the heterogeneous circuit region PAM is changed to provide the voltage jumper line VLA, thereby making the voltage signal distribution on the voltage trace VL gridded.
  • the second source-drain metal layer SD2 is provided with a power supply voltage trace VDDL for loading the power supply voltage VDD (see Figure 12), and the first source-drain metal layer SD1 is provided with a power supply voltage transfer structure VDLP (equivalent to the third bridging part MA3 described in this application) in the circuit area PA; the power supply voltage transfer structure VDLP is electrically connected to the power supply voltage trace VDDL, and is used to simultaneously provide the power supply voltage VDD to the two pixel driving circuits of the circuit area PA.
  • the shape of the power supply voltage transfer structure VDLP in the heterogeneous circuit region PAM is different from the shape of the power supply voltage transfer structure VDLP in the non-heterogeneous circuit region PAN, so that the first source-drain metal layer SD1 has a cross-line channel extending along the column direction in the heterogeneous circuit region PAM; the first source-drain metal layer SD1 is provided with a voltage jumper VLA in the cross-line channel, and the voltage jumper VLA is electrically connected to two adjacent voltage traces VL on the column direction DV.
  • the following description uses the pixel driving circuit shown in Figure 4 as an example to illustrate one type of film layer structure for a display panel. It is understood that the film layer structure of the display panel can change when the pixel driving circuit is changed. Even if the pixel driving circuit of the display panel is the same as the example in Figure 4, the film layer structure of the display panel can still be adjusted.
  • the LSCL is provided with an active layer of a first capacitor reset transistor T1, an active layer of a driving transistor T3, an active layer of a data writing transistor T4, an active layer of a first light-emitting control transistor T5, an active layer of a second light-emitting control transistor T6, an active layer of an electrode reset transistor T7, and an active layer of a second capacitor reset transistor T8.
  • the active layers of the transistors include the first electrode, the second electrode, and the channel region of the transistor.
  • the data writing transistor T4, the first light-emitting control transistor T5, and the first driving transistor T3 are electrically connected; the second driving transistor T3 and the first light-emitting control transistor T6 are electrically connected; and the second electrode reset transistor T7 and the second light-emitting control transistor T6 are electrically connected.
  • the first electrode of the first capacitor reset transistor T1 has a first lower via region HA1, and the second electrode of the first capacitor reset transistor T1 has a second lower via region HA2.
  • the first electrode of the data writing transistor T4 has a third lower via region HA3; the second electrode of the driving transistor T3 has a fourth lower via region HA4; the second electrode of the first light-emitting control transistor T5 has a fifth lower via region HA5; the second electrode of the second light-emitting control transistor T6 has a sixth lower via region HA6; the second electrode of the second capacitor reset transistor T8 has a seventh lower via region HA7; the first electrode of the first light-emitting control transistor T5 has an eighth lower via region HA8; the first electrode reset transistor T7 has a ninth lower via region HA9; and the first electrode of the second capacitor reset transistor T8 has a tenth lower via region HA10.
  • the channel region T4A of the data writing transistor and the channel region T5A of the first light-emitting control transistor are arranged along the column direction DV, and the channel regions T5A and T6A of the first and second light-emitting control transistors are arranged along the row direction DH.
  • the channel region T3A of the driving transistor and the channel region T7A of the electrode reset transistor are located between the channel regions T5A and T6A of the first and second light-emitting control transistors; along the column direction DV, the channel region T7A of the electrode reset transistor and the channel region T3A of the driving transistor are located on both sides of the channel region T5A of the first light-emitting control transistor.
  • FIG. 7 is a schematic diagram of the structure of the first gate layer GT1 in a circuit area PA of the exemplary display panel.
  • the first gate layer GT1 has a first capacitor reset control signal line RL1, a second capacitor reset control signal line RL2, a third scan signal trace GPL, an enable signal line EML, and a first electrode CP1 of a storage capacitor CST, all extending along the row direction DH.
  • the first capacitor reset control signal line RL1 extends along the row direction DH and is used to load the first capacitor reset control signal Rest1 onto the first capacitor reset transistor T1.
  • the second capacitor reset control signal line RL2 extends along the row direction DH and is used to load the second capacitor reset control signal Rest2 onto the second capacitor reset transistor T8.
  • the enable signal line EML extends along the row direction DH and overlaps sequentially with the channel region T5A of the first light-emitting transistor and the channel region T6A of the second light-emitting transistor, thus multiplexing it as the gate of the first light-emitting transistor T5 and the gate of the second light-emitting transistor T6.
  • the enable signal line EML can be used to load the enable signal EM.
  • the first electrode CP1 of the storage capacitor CST overlaps with the channel region T3A of the driving transistor, and is reused as the gate of the driving transistor T3.
  • the third scan signal trace GPL extends along the row direction DH, and can overlap with the channel region T4A of the data write transistor. The overlapping portion is reused as the gate of the data write transistor T4.
  • the first electrode CP1 of the storage capacitor CST overlaps with the channel region T3A of the driving transistor, and is reused as the gate of the driving transistor T3.
  • the first electrode CP1 of the storage capacitor CST has
  • FIG 8 is a schematic diagram of the structure of the second gate layer GT2 in a non-heterogeneous circuit area PAN of the exemplary display panel.
  • the second gate layer GT2 is provided with a first initialization voltage trace VTL1, a second electrode CP2 of the storage capacitor CST, and a second scan signal trace GNLB.
  • the first initialization voltage trace VTL1 extends along the row direction DH and can be used to load the first initialization voltage Vinit1.
  • the second electrode CP2 of the storage capacitor CST overlaps with the first electrode CP1 of the storage capacitor CST, and a clearance hole is provided to expose a portion of the first electrode CP1 of the storage capacitor CST.
  • the second scan signal trace GNLB extends along the row direction DH and is used to load the second scan signal.
  • the second electrode CP2 of the storage capacitor CST is provided with a fourteenth lower via area HA14.
  • the first initialization voltage trace VTL1 is provided with a seventeenth lower via area HA17 in any sub-circuit area (e.g., the first sub-circuit area PA1 or the second sub-circuit area PA2).
  • FIG 9 is a schematic diagram of the metal-oxide-semiconductor layer (OSCL) in a circuit area PA of this exemplary display panel.
  • the OSCL is provided with a second electrode, a first electrode, and a channel region for a threshold compensation transistor T2.
  • the channel region T1A of the first capacitor reset transistor is located on the side of the threshold compensation transistor's channel region T2A away from the channel region T3A of the driving transistor.
  • the channel region T2A of the threshold compensation transistor and the channel region T5A of the first light-emitting control transistor are located on opposite sides of the channel region T3A of the driving transistor.
  • the second electrode of the threshold compensation transistor T2 is provided with an eleventh lower via region HA11, and the first electrode of the threshold compensation transistor T2 is provided with a twelfth lower via region HA12.
  • FIG 10 is a schematic diagram of the structure of the third gate layer GT3 in a non-heterogeneous circuit area PAN of this exemplary display panel.
  • the third gate layer GT3 is provided with a second initialization voltage trace VTL2, a third initialization voltage trace VTL3, and a first scan signal trace GNLA.
  • the second initialization voltage trace VTL2 extends along the row direction DH and can be used to apply a second initialization voltage Vinit2.
  • the third initialization voltage trace VTL3 extends along the row direction DH and can be used to apply a third initialization voltage Vinit3.
  • the first scan signal trace GNLA extends along the row direction DH and overlaps with the channel region T2A of the threshold compensation transistor.
  • the overlapping portion is multiplexed as the second gate of the threshold compensation transistor T2.
  • the third initialization voltage trace VTL3 has a fifteenth lower via region HA15
  • the second initialization voltage trace VTL2 has a sixteenth lower via region HA16.
  • Figure 11 is a schematic diagram of the structure of the first source/drain metal layer SD1 in a non-heterogeneous circuit area PAN of the exemplary display panel.
  • the first source/drain metal layer SD1 is provided with a first bridging portion MA1 to a ninth bridging portion MA9.
  • a first bridging portion MA1 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2).
  • the first bridging portion MA1 has an eleventh upper via region HB11 and a thirteenth upper via region HB13; wherein, the eleventh upper via region HB11 overlaps with the eleventh lower via region HA11 and is connected through a via; the thirteenth upper via region HB13 overlaps with the thirteenth lower via region HA13 and is connected through a via.
  • the second electrode of the threshold compensation transistor T2 is electrically connected to the first electrode CP1 through the first bridging portion MA1.
  • a second bridging section MA2 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2).
  • the second bridging section MA2 has a second upper via region HB2, a fourth upper via region HB4, and a twelfth upper via region HB12.
  • the second upper via region HB2 overlaps with the second lower via region HA2 and is connected through a via;
  • the fourth upper via region HB4 overlaps with the fourth lower via region HA4 and is connected through a via;
  • the twelfth upper via region HB12 overlaps with the twelfth lower via region HA12 and is connected through a via.
  • the second terminal of the first capacitor reset transistor T1 is electrically connected to the second terminal of the driving transistor T3 through the second bridging section MA2, and the first terminal of the threshold compensation transistor T2 is electrically connected.
  • a third bridging section MA3 is provided in the circuit area PA.
  • the third bridging section MA3 has a fourteenth upper via region HB14, an eighth upper via region HB8, a nineteenth lower via region HA19, and a twenty-first lower via region HA21.
  • the fourteenth upper via region HB14 overlaps with the fourteenth lower via region HA14 and is connected through vias.
  • the eighth upper via region HB8 overlaps with the eighth lower via region HA8 and is connected through vias.
  • the nineteenth upper via region HB19 overlaps with the nineteenth lower via region HA19 and is connected through vias.
  • the twenty-first upper via region HB21 overlaps with the twenty-first lower via region HA21 and is connected through vias.
  • the second electrode CP2 of the storage capacitor CST and the first electrode of the first light-emitting control transistor T5 can be electrically connected to each other through the third bridging section MA3.
  • the third bridging portion MA3 in the non-heterogeneous circuit region PAN, has a first sub-transfer structure MA31, a second sub-transfer structure MA32, and a third sub-transfer structure MA33.
  • the first sub-transfer structure MA31 extends along the column direction DV and is located in the middle of the non-heterogeneous circuit region PAN in the row direction DH. It is used to provide power supply voltage VDD to two pixel driving circuits through vias.
  • the first sub-transfer structure MA31 has a nineteenth lower via region HA19.
  • the second sub-transfer structure MA32 has a twenty-first lower via region HA21; the third sub-transfer structure MA33 has a nineteenth lower via region HA19.
  • the second sub-transfer structure MA32 and the third sub-transfer structure MA33 are located on both sides of the first sub-transfer structure MA31 and are electrically connected to the power supply voltage trace VDDL through vias.
  • a fourth bridging section MA4 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2).
  • the fourth bridging section MA4 has a third upper via region HB3 and an eighteenth lower via region HA18.
  • the third upper via region HB3 overlaps with the third lower via region HA3 and is connected through a via.
  • the eighteenth upper via region HB18 overlaps with the eighteenth lower via region HA18 and is connected through a via.
  • the first terminal of the data writing transistor T4 is connected to the data signal trace DL (see Figure 12) through the fourth bridging section MA4.
  • a fifth bridging section MA5 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2).
  • the fifth bridging section MA5 has a fifth upper via region HB5 and a seventh upper via region HB7.
  • the fifth upper via region HB5 overlaps with the fifth lower via region HA5 and is connected through a via; the seventh upper via region HB7 overlaps with the seventh lower via region HA7 and is connected through a via.
  • the second terminal of the first light-emitting control transistor T5 is electrically connected to the first terminal of the second capacitor reset transistor T8 through the fifth bridging section MA5.
  • a sixth bridging section MA6 (equivalent to the initialization voltage transfer structure VTLP) is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2).
  • the sixth bridging section MA6 has a tenth upper via region HB10 and a fifteenth upper via region HB15.
  • the tenth upper via region HB10 overlaps with the tenth lower via region HA10 and is connected through a via.
  • the fifteenth upper via region HB15 overlaps with the fifteenth lower via region HA15 and is connected through a via.
  • the third initialization voltage trace VTL3 is electrically connected to the second terminal of the second capacitor reset transistor T8 through the sixth bridging section MA6.
  • the initialization voltage transfer structure VTLP includes a fourth sub-transfer structure MA61, a fifth sub-transfer structure MA62, and a sixth sub-transfer structure MA63.
  • the fourth sub-transfer structure MA61 is located at the connection between the first sub-circuit region PA1 and the second sub-circuit region PA2, and is used to simultaneously provide initialization voltages (e.g., a third initialization voltage Vinit3) to both pixel driving circuits.
  • the fifth sub-transfer structure MA62 is connected to the fourth sub-transfer structure MA61 and located in the second sub-circuit region PA2, and is electrically connected to VTL3 via a via.
  • the sixth sub-transfer structure MA63 is connected to the fourth sub-transfer structure MA61 and located in the first sub-circuit region PA1, and is electrically connected to VTL3 via a via.
  • the ends of the fifth sub-transfer structure MA62 and the sixth sub-transfer structure MA63 furthest from the fourth sub-transfer structure MA61 are each provided with a fifteenth upper via region HB15.
  • a seventh bridging section MA7 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2).
  • the seventh bridging section MA7 has a ninth upper via region HB9 and a sixteenth upper via region HB16.
  • the ninth upper via region HB9 overlaps with the ninth lower via region HA9 and is connected through a via.
  • the sixteenth upper via region HB16 overlaps with the sixteenth lower via region HA16 and is connected through a via.
  • the second initialization voltage trace VTL2 is electrically connected to the first electrode of the electrode reset transistor T7 through the seventh bridging section MA7.
  • an eighth bridging section MA8 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2).
  • the eighth bridging section MA8 has a first upper via region HB1 and a seventeenth upper via region HB17.
  • the first upper via region HB1 overlaps with the first lower via region HA1 and is connected through a via;
  • the seventeenth upper via region HB17 overlaps with the seventeenth lower via region HA17 and is connected through a via; thus, the first initialization voltage trace VTL1 is electrically connected to the first electrode of the first capacitor reset transistor T1 through the eighth bridging section MA8.
  • a ninth bridging section MA9 is provided in any sub-circuit region of circuit region PA (e.g., the first sub-circuit region PA1 or the second sub-circuit region PA2).
  • the ninth bridging section MA9 has a sixth upper via region HB6 and a twentieth lower via region HA20.
  • the ninth upper via region HB9 and the ninth lower via region HA9 overlap and are connected through vias; the twentieth upper via region HB20 and the twentieth lower via region HA20 overlap and are connected through vias.
  • the driving current generated by the pixel driving circuit can be transmitted to the ninth bridging section MA9, and then to the sub-pixel.
  • the first source-drain metal layer SD1 is further provided with a reference voltage trace VSL for loading the reference voltage VSS, and the reference voltage trace VSL extends along the row direction DH.
  • the reference voltage trace VSL is located between the second bridge portion MA2 and the eighth bridge portion MA8.
  • each circuit region row HPA is provided with a corresponding reference voltage trace VSL. In this way, a large distribution density of the reference voltage trace VSL can be ensured, thereby further reducing the voltage drop of the reference voltage VSS.
  • FIG 12 is a partial structural schematic diagram of the second source-drain metal layer SD2 in this exemplary display panel.
  • the second source-drain metal layer SD2 includes data signal traces DL and power supply voltage traces VDDL extending along the column direction DV.
  • the second source-drain metal layer SD2 also has a first conductive structure MB1.
  • the data signal trace DL is arranged in a one-to-one correspondence with the pixel driving circuit array.
  • the data signal trace DL has an eighteenth upper via region HB18.
  • the eighteenth upper via region HB18 overlaps with the eighteenth lower via region HA18 and is electrically connected via a via.
  • the data signal trace DL is electrically connected to the fourth bridging portion MA4 via a via, thereby connecting the data signal trace DL to the first electrode of the data writing transistor T4. This allows the driving data signal Source loaded on the data signal trace DL to be loaded onto the first electrode of the data writing transistor T4.
  • power supply voltage traces VDDL are configured one-to-one with pixel driving circuit columns.
  • each of the two power supply voltage traces VDDL has a nineteenth upper via region HB19 and a twenty-first upper via region HB21. These two via regions overlap with and are electrically connected to the two nineteenth lower via regions HA19 and the twenty-first lower via regions HB21 in the non-heterogeneous circuit area PAN vias.
  • the third bridging portion MA3 in the non-heterogeneous circuit area PAN is electrically connected to the two power supply voltage traces VDDL vias.
  • the two power supply voltage traces VDDL in the same circuit area column VPA are interconnected to form a single unit.
  • the power supply voltage trace VDDL may have a protrusion (not specified in this application), which may cover the channel region T2A of the threshold compensation transistor.
  • the protrusions of the two power supply voltage traces VDDL in the same circuit area column VPA are interconnected.
  • the first conductive structure MB1 has a twentieth upper via region HB20; the twentieth upper via region HB20 and the twentieth lower via region HA20 in the same sub-circuit region overlap and are electrically connected through vias. Furthermore, the pixel electrode of the sub-pixel is electrically connected to the first conductive structure MB1 in the corresponding sub-circuit region through vias; this allows the driving current generated by the pixel driving circuit in the sub-circuit region to be applied to the corresponding sub-pixel.
  • the initialization voltage includes a first initialization voltage Vinit1, a second initialization voltage Vinit2, and a third initialization voltage Vinit3.
  • the initialization voltage trace VTL includes a first initialization voltage trace VTL1 for loading the first initialization voltage Vinit1, a second initialization voltage trace VTL2 for loading the second initialization voltage Vinit2, and a third initialization voltage trace VTL3 for loading the third initialization voltage Vinit3.
  • the first initialization voltage trace VTL1 is disposed on the second gate layer GT2, and the second initialization voltage trace VTL2 and the third initialization voltage trace VTL3 are disposed on the third gate layer GT3. It is understood that in other embodiments of this disclosure, the first initialization voltage trace VTL1, the second initialization voltage trace VTL2, and the third initialization voltage trace VTL3 may also be disposed on other film layers.
  • the shape of the power supply voltage transfer structure VDLP in the heterogeneous circuit region PAM is different from the shape of the power supply voltage transfer structure VDLP in the non-heterogeneous circuit region PAN, so that the first source-drain metal layer SD1 has a cross-line channel extending along the column direction DV in the heterogeneous circuit region PAM.
  • the first source-drain metal layer SD1 is provided with a voltage jumper line VLA in the heterogeneous circuit region PAM, and the voltage jumper line VLA is electrically connected to two adjacent voltage traces VL that carry the same signal.
  • the voltage jumper VLA is used to electrically connect adjacent traces of the same voltage type VL.
  • the power supply voltage transfer structure VDLP simultaneously provides power supply voltage VDD to two pixel driving circuits in the driving circuit area PA, even if the power supply voltage transfer structure VDLP deforms to avoid the jumper channel, it will not affect the power supply to the pixel driving circuit.
  • a reference voltage trace VSL is disposed on the first source-drain metal layer SD1 and corresponds one-to-one with each circuit region row HPA, that is, each circuit region row HPA has a corresponding reference voltage trace VSL.
  • the heterogeneous circuit region PAM includes a reference heterogeneous circuit region PAMS.
  • the first source-drain metal layer SD1 has a reference voltage jumper VSLA, which serves as a voltage jumper VLA, in the cross-line channel of the reference heterogeneous circuit region PAMS.
  • the reference voltage jumper VSLA can electrically connect two adjacent reference voltage traces VSL.
  • the reference voltage jumper VSLA can be directly connected to the reference voltage trace VSL.
  • the heterogeneous circuit region PAM includes an initialization heterogeneous circuit region PAMT
  • the voltage jumper VLA includes an initialization voltage jumper VTLA located in the initialization heterogeneous circuit region PAMT and electrically connecting two adjacent initialization voltage traces VTL.
  • a reference voltage trace VSL is interrupted at the jumper channel of the initialization heterogeneous circuit region PAMT to form a break gap (as part of the jumper channel), and the initialization voltage jumper VTLA passes through the break gap of the reference voltage trace VSL.
  • VTLs there are at least two types of initialization voltage traces (VTLs); in each initialization heterogeneous circuit region (PAMT), only one type of initialization voltage trace (VTL) corresponding to an initialization voltage jumper (VTLA) is provided.
  • PAMT initialization heterogeneous circuit region
  • VTLA initialization voltage jumper
  • the initialization voltage trace VTL includes a first initialization voltage trace VTL1 for applying a first initialization voltage Vinit1 to the pixel driving circuit.
  • the initialization heterogeneous circuit region PAMT includes a first initialization heterogeneous circuit region PAMT1
  • the first source-drain metal layer SD1 has a cross-line channel in the first initialization heterogeneous circuit region PAMT1 and a first initialization voltage jumper VTL1A located in the cross-line channel; the two ends of the first initialization voltage jumper VTL1A are electrically connected to two adjacent first initialization voltage traces VTL1 respectively (see Figure 25).
  • the first source/drain metal layer SD1 has an eighth bridge portion MA8 in the circuit region PA.
  • the eighth bridge portion MA8 is connected to the first initialization voltage trace VTL1 through a via, and is also connected to the thin-film transistor of the pixel driving circuit through the via.
  • the two ends of the first initialization voltage jumper VTL1A are respectively electrically connected to the eighth bridge portion MA8 that is electrically connected to the two first initialization voltage traces VTL1.
  • the first initialization voltage jumper VTL1A connects the two eighth bridge portions MA8, thereby electrically connecting the two first initialization voltage traces VTL1.
  • two adjacent eighth bridge portions MA8 in the same column are electrically connected through the first initialization voltage jumper VTL1A located in the first initialization heterogeneous circuit region PAMT1, thereby electrically connecting the first initialization voltage traces VTL1 in adjacent rows (see FIG25).
  • the reference voltage trace VSL has a break gap CG, and the first initialization voltage jumper VTL1A passes through the break gap CG of the reference voltage trace VSL (as part of the jumper channel).
  • the reference voltage trace VSL is provided with a break gap CG in the first initialization heterogeneous circuit region PAMT1 and is a discontinuous set of multiple sub-traces, the sub-traces located in different circuit region rows HPA can be electrically connected through the reference voltage jumper VSLA (see Figure 23), thereby connecting the individual sub-traces to form a mesh, and thus making the reference voltage VSS distributed in a mesh on the first source-drain metal layer SD1.
  • the initialization voltage trace VTL includes a second initialization voltage trace VTL2 for applying a second initialization voltage Vinit2 to the pixel driving circuit; referring to Figures 15 and 27, the initialization heterogeneous circuit region PAMT includes a second initialization heterogeneous circuit region PAMT2, and the first source-drain metal layer SD1 has a cross-line channel in the second initialization heterogeneous circuit region PAMT2; the first source-drain metal layer SD1 has a second initialization voltage jumper VTL2A disposed in the cross-line channel (see Figure 15). The two ends of the second initialization voltage jumper VTL2A are electrically connected to two adjacent second initialization voltage traces VTL2 respectively (see Figure 22).
  • the first source/drain metal layer SD1 is provided with a seventh bridging portion MA7, which is connected to the second initialization voltage trace VTL2 via a via, and is also connected to the thin-film transistor of the pixel driving circuit via a via.
  • the two ends of the second initialization voltage jumper VTL2A are respectively electrically connected to the seventh bridging portion MA7 that is electrically connected to the two second initialization voltage traces VTL2.
  • the second initialization voltage jumper VTL2A connects the two seventh bridging portions MA7, thereby electrically connecting the two second initialization voltage traces VTL2.
  • two adjacent seventh bridging portions MA7 in the same column are electrically connected through the second initialization voltage jumper VTL2A located in the second initialization heterogeneous circuit region PAMT2, thereby electrically connecting the second initialization voltage traces VTL2 in adjacent rows (see FIG22 and FIG27).
  • the reference voltage trace VSL has a break gap CG, and the second initialization voltage jumper VTL2A passes through the break gap CG of the reference voltage trace VSL (as part of the jumper channel).
  • the reference voltage trace VSL is provided with a break gap CG in the second initialization heterogeneous circuit region PAMT2 and is a discontinuous set of multiple sub-traces, the sub-traces located in different circuit region rows HPA can be electrically connected through the reference voltage jumper VSLA, thereby connecting the individual sub-traces to form a mesh, and thus making the reference voltage VSS appear as a mesh on the first source-drain metal layer SD1.
  • the initialization voltage trace VTL includes a third initialization voltage trace VTL3 for applying a third initialization voltage Vinit3 to the pixel driving circuit.
  • the initialization heterogeneous circuit region PAMT includes a third initialization heterogeneous circuit region PAMT3.
  • the first source-drain metal layer SD1 has a cross-line channel in the third initialization heterogeneous circuit region PAMT3; the first source-drain metal layer SD1 provides a third initialization voltage jumper VTL3A in the cross-line channel of the third initialization heterogeneous circuit region PAMT3, and the two ends of the third initialization voltage jumper VTL3A are electrically connected to two adjacent third initialization voltage traces VTL3 respectively (see Figure 26).
  • the first source/drain metal layer SD1 has a sixth bridge portion MA6 in the circuit region PA.
  • the sixth bridge portion MA6 is connected to the third initialization voltage trace VTL3 through a via, and is also connected to the thin-film transistor of the pixel driving circuit through the via.
  • the two ends of the third initialization voltage jumper VTL3A are respectively electrically connected to the sixth bridge portion MA6 that is electrically connected to the two third initialization voltage traces VTL3.
  • the third initialization voltage jumper VTL3A connects the two sixth bridge portions MA6, thereby electrically connecting the two third initialization voltage traces VTL3.
  • two adjacent sixth bridge portions MA6 in the same column are electrically connected through the third initialization voltage jumper VTL3A located in the third initialization heterogeneous circuit region PAMT3, thereby electrically connecting the third initialization voltage traces VTL3 in two adjacent columns.
  • the reference voltage trace VSL has a break gap CG, and the third initialization voltage jumper VTL3A passes through the break gap CG of the reference voltage trace VSL (as part of the jumper channel).
  • the reference voltage trace VSL is a discontinuous set of multiple sub-traces with a break gap CG in the third initialization heterogeneous circuit region PAMT3
  • the sub-traces located in different circuit region rows HPA can be electrically connected through the reference voltage jumper VSLA, thereby connecting the sub-traces to form a mesh, and thus making the reference voltage VSS appear as a mesh on the first source-drain metal layer SD1.
  • the two pixel driving circuits in the circuit region PA can be arranged symmetrically overall, that is, symmetrically along an axis of symmetry extending along the column direction. It is understood that the symmetrical arrangement of the two pixel driving circuits in the circuit region PA does not mean that the patterns of each film layer of the circuit region PA are symmetrically arranged, but rather that the relative positions of the transistors of the two pixel driving circuits in the circuit region PA are substantially symmetrical.
  • the driving layer DRL can also have a symmetrically arranged pattern in at least a portion of the film layers of the circuit region PA.
  • the first light-emitting control transistor T5 in the first sub-circuit region PA1 and the first light-emitting control transistor T5 in the second sub-circuit region PA2 are arranged adjacent to each other, and the first terminals of the two first light-emitting control transistors T5 can be electrically connected to each other.
  • the power supply voltage transfer structure VDLP in circuit region PA can be electrically connected to the first terminals of the two first light-emitting control transistors T5 through a via.
  • the eighth lower via region HA8 and the eighth upper via region HB8 can be located on the boundary line between the first sub-circuit region PA1 and the second sub-circuit region PA2, which can reduce the number of vias and thus help improve the resolution of the display panel.
  • the cross-line channel of the heterogeneous circuit region PAM is disposed in the first sub-circuit region PA1 of the heterogeneous circuit region PAM.
  • the pattern of the first source-drain metal layer SD1 in the first sub-circuit region PA1 is axially symmetrically disposed with respect to the pattern in the second sub-circuit region PA2.
  • the pattern of the first source-drain metal layer SD1 in the second sub-circuit region PA2 of the non-heterogeneous circuit region PAN is the same as the pattern in the second sub-circuit region PA2 of the heterogeneous circuit region PAM; the pattern of the first source-drain metal layer SD1 in the first sub-circuit region PA1 of the heterogeneous circuit region PAM is different from the pattern in the first sub-circuit region PA1 of the non-heterogeneous circuit region PAN.
  • the pattern of the first source-drain metal layer SD1 in the area other than the cross-line channel in the first sub-circuit region PA1 of the heterogeneous circuit region PAM is the same as the pattern of the first source-drain metal layer SD1 in the same area of the first sub-circuit region PA1 of the non-heterogeneous circuit region PAN.
  • the third bridging portion MA3 is composed of a first sub-transfer structure MA31 and a second sub-transfer structure MA32. In other words, in the heterogeneous circuit region PAM, the third bridging portion MA3 does not have a third sub-transfer structure MA33 to avoid crossing the cross-line channel.
  • the first sub-transition structure MA31 is disposed at the connection between the first sub-circuit region PA1 and the second sub-circuit region PA2, and the second sub-transition structure MA32 is disposed in the second sub-circuit region PA2.
  • the first sub-circuit region PA1 of the non-heterogeneous circuit region PAN is provided with a third sub-transition structure MA33, while the first sub-circuit region PA1 of the heterogeneous circuit region PAM is not provided with a third sub-transition structure MA33.
  • the pixel driving circuit includes a threshold compensation transistor T2 for threshold compensation of the driving transistor T3.
  • any sub-circuit region e.g., either the first sub-circuit region PA1 or the second sub-circuit region PA2
  • a first bridging portion MA1 which electrically connects the second terminal of the threshold compensation transistor T2 to the gate of the driving transistor T3.
  • a voltage bridging line VLA is provided between the first bridging portion MA1 and the third bridging portion MA3.
  • the pixel driving circuit can reduce the leakage current of the first node N1 by setting the threshold compensation transistor T2 as a metal oxide transistor, thereby improving the voltage holding capability of the pixel driving circuit, reducing the risk of flickering of the display panel under low-frequency driving, and reducing the power consumption of the display panel.
  • the first source-drain metal layer SD1 is further provided with an initialization voltage transfer structure VTLP (e.g., the sixth bridge part MA6) in the circuit region PA.
  • the voltage trace VL includes an initialization voltage trace VTL (e.g., the third initialization voltage trace VTL3) located in the transistor layer and used to load the initialization voltage.
  • the initialization voltage transfer structure is electrically connected to the initialization voltage trace VTL and is used to simultaneously provide an initialization voltage (e.g., Vinit3) to the two pixel driving circuits in the circuit region PA.
  • the shape of the initial voltage transfer structure in the non-heterogeneous circuit region PAN is different from that in the heterogeneous circuit region PAM, so that the initial voltage transfer structure VTLP in the heterogeneous circuit region PAM avoids the cross-line channel.
  • the initialization voltage transfer structure VTLP in the heterogeneous circuit region PAM is also deformed to avoid the cross-line channel.
  • the two thin-film transistors connected to the initialization voltage transfer structure VTLP are arranged adjacently, so that the initialization voltage transfer structure VTLP simultaneously drives two pixel driving circuits through a via.
  • the second capacitor reset transistor T8 in the first sub-circuit region PA1 and the second capacitor reset transistor T8 in the second sub-circuit region PA2 are arranged adjacently, and the first terminals of the two second capacitor reset transistors T8 are shared and a tenth lower via region HA10 is provided.
  • the tenth lower via region HA10 and the tenth upper via region HB10 are located on the boundary line between the first sub-circuit region PA1 and the second sub-circuit region PA2.
  • the first source-drain metal layer SD1 is provided with a sixth bridge part MA6 as the initialization voltage transfer structure, which simultaneously applies a third initialization voltage Vinit3 to the second capacitor reset transistors T8 of the two sub-circuit regions through a via.
  • the sixth bridging section MA6 is composed of a fourth sub-transfer structure MA61 and a fifth sub-transfer structure MA62. In other words, in the heterogeneous circuit region PAM, the sixth bridging section MA6 does not have a sixth sub-transfer structure MA63 to avoid crossing the cross-line channel.
  • the fourth sub-transition structure MA61 is disposed at the connection between the first sub-circuit region PA1 and the second sub-circuit region PA2, and it has a tenth upper via region HB10; the fifth sub-transition structure MA62 is disposed in the second sub-circuit region PA2.
  • the first sub-circuit region PA1 of the non-heterogeneous circuit region PAN is provided with a sixth sub-transition structure MA63, while the first sub-circuit region PA1 of the heterogeneous circuit region PAM is not provided with a sixth sub-transition structure MA63.
  • the fifth upper via region HB15 which is electrically connected to the third initialization voltage trace VTL3, is not provided on the third initialization voltage jumper VTL3A, and therefore it can be disregarded as the sixth sub-transition structure MA63.
  • the fifth upper via region HB15 can be provided at the overlap between the third initialization voltage jumper VTL3A and the third initialization voltage trace VTL3, allowing the third initialization voltage jumper VTL3A to be directly electrically connected to the third initialization voltage trace VTL3 via.
  • the shape of the third gate layer GT3 in the non-heterogeneous circuit region PAN may differ from its shape in the heterogeneous circuit region PAM.
  • Figure 17 illustrates the structure of the third gate layer GT3 in the heterogeneous circuit region PAM in one embodiment.
  • Figure 10 illustrates the structure of the third gate layer GT3 in the non-heterogeneous circuit region PAN in one embodiment.
  • the third initialization voltage trace VTL3 has two bulges, each bulge having a fifteenth lower via region HA15 for electrical connection to the sixth bridge portion MA6 via.
  • the third initialization voltage trace VTL3 has a bulge in the first sub-circuit region PA1 for electrical connection to the sixth sub-transition structure MA63, and a bulge in the second sub-circuit region PA2 for electrical connection to the fifth sub-transition structure MA62.
  • the third initialization voltage trace VTL3 has one bulge; this bulge has a fifteenth lower via region HA15 for electrical connection to the sixth bridge portion MA6 via.
  • the third initialization voltage trace VTL3 has an enlargement for electrical connection with the fifth sub-transfer structure MA62 only in the second sub-circuit region PA2, and no enlargement for electrical connection with the sixth sub-transfer structure MA63 is provided in the first sub-circuit region PA1.
  • the third gate layer GT3 may have the same shape in both the non-heterogeneous circuit region PAN and the heterogeneous circuit region PAM.
  • the non-heterogeneous circuit area PAN and the heterogeneous circuit area PAM are alternately arranged. This ensures a gridded distribution of the power signal, guarantees grid density, and improves the uniformity of the power signal.
  • the non-heterogeneous circuit area PAN and the heterogeneous circuit area PAM are alternately arranged. This ensures a gridded distribution of the power signal, guarantees grid density, and improves the uniformity of the power signal.
  • the heterogeneous circuit area PAM is the same heterogeneous circuit area PAM.
  • At least one reference heterogeneous circuit region is provided between two adjacent initialization heterogeneous circuit regions (PAMTs) along the row direction DH.
  • PAMSs reference heterogeneous circuit regions
  • PAMTs initialization heterogeneous circuit regions
  • the first initialization heterogeneous circuit region PAMT1, the second initialization heterogeneous circuit region PAMT2, the third initialization heterogeneous circuit region PAMT3, and the second initialization heterogeneous circuit region PAMT2 are arranged periodically in sequence.
  • the grid density of the second initialization voltage Vinit2 is greater than that of the first initialization voltage Vinit1 and the third initialization voltage Vinit3, which allows the more critical second initialization voltage Vinit2 to have better signal stability, thereby improving the image quality of the display panel.
  • the number of first initialization heterogeneous circuit regions PAMT1 can be greater than that of the second initialization heterogeneous circuit regions PAMT2 and the third initialization heterogeneous circuit regions PAMT3.
  • the stability of the third initialization voltage Vinit3 is more critical to the stability of the pixel driving circuit
  • the number of third initialization heterogeneous circuit regions PAMT3 can be greater than that of the second initialization heterogeneous circuit regions PAMT2 and the first initialization heterogeneous circuit regions PAMT1.
  • N represents the non-heterogeneous circuit region PAN
  • S represents the reference heterogeneous circuit region PAMS
  • 1 represents the first initialized heterogeneous circuit region PAMT1
  • 2 represents the second initialized heterogeneous circuit region PAMT2
  • 3 represents the third initialized heterogeneous circuit region PAMT3
  • the heterogeneous circuit regions PAM are of the same type.
  • the circuit region column VPA containing the reference heterogeneous circuit region PAMS is marked as S; then the circuit region column VPA marked as S includes the non-heterogeneous circuit region PAN and the reference heterogeneous circuit region PAMS, which are alternately arranged along the column direction DV.
  • the circuit region column VPA containing the first initialized heterogeneous circuit region PAMT1 is marked as 1; then the circuit region column VPA marked as 1 includes the non-heterogeneous circuit region PAN and the first initialized heterogeneous circuit region PAMT1, which are alternately arranged along the column direction DV.
  • the circuit area column VPA containing the second initial heterogeneous circuit area PAMT2 is marked as 2
  • the circuit area column VPA marked as 2 includes the non-heterogeneous circuit area PAN and the second initial heterogeneous circuit area PAMT2, which are alternately arranged along the column direction DV.
  • the circuit area column VPA containing the third initial heterogeneous circuit area PAMT3 is marked as 3
  • the circuit area column VPA marked as 3 includes the non-heterogeneous circuit area PAN and the third initial heterogeneous circuit area PAMT3, which are alternately arranged along the column direction DV.
  • the arrangement of 24 consecutive circuit area columns VPA can be 1SS1SS2SS2SS3SS3SS2SS2SS (see Figures 21-24).
  • N represents the non-heterogeneous circuit region PAN
  • S represents the reference heterogeneous circuit region PAMS
  • 1 represents the first initialized heterogeneous circuit region PAMT1
  • 2 represents the second initialized heterogeneous circuit region PAMT2
  • 3 represents the third initialized heterogeneous circuit region PAMT3
  • the heterogeneous circuit regions PAM are of the same type.
  • the circuit region column VPA containing the reference heterogeneous circuit region PAMS is marked as S.
  • the circuit region column VPA marked as S includes the non-heterogeneous circuit region PAN and the reference heterogeneous circuit region PAMS, which are alternately arranged along the column direction DV.
  • the circuit region column VPA containing the first initialized heterogeneous circuit region PAMT1 is marked as 1.
  • the circuit region column VPA marked as 1 includes the non-heterogeneous circuit region PAN and the first initialized heterogeneous circuit region PAMT1, which are alternately arranged along the column direction DV. 1.
  • the circuit column VPA containing the second initialization heterogeneous circuit area PAMT2 is marked as 2.
  • the circuit column VPA marked as 2 includes the non-heterogeneous circuit area PAN and the second initialization heterogeneous circuit area PAMT2, which are alternately arranged along the column direction DV.
  • the circuit column VPA containing the third initialization heterogeneous circuit area PAMT3 is marked as 3.
  • the circuit column VPA marked as 3 includes the non-heterogeneous circuit area PAN and the third initialization heterogeneous circuit area PAMT3, which are alternately arranged along the column direction DV.
  • the arrangement of 24 consecutive circuit column VPAs can be 1SS3SS2SS2SS3SS1SS2SS2SS.
  • the driving layer DRL may further include a third source/drain metal layer SD3 located on the side of the second source/drain metal layer SD2 away from the first source/drain metal layer SD1; a second planarization layer PLN2 is disposed between the second source/drain metal layer SD2 and the third source/drain metal layer SD3, and a third planarization layer PLN3 is disposed on the side of the third source/drain metal layer SD3 away from the second source/drain metal layer SD2.
  • the driving layer DRL includes the second source/drain metal layer SD2, the second planarization layer PLN2, the third source/drain metal layer SD3, and the third planarization layer PLN3 stacked sequentially.
  • the third source/drain metal layer SD3 can be provided with a reference voltage grid VSSW, which can be electrically connected to the common electrode layer COML in the peripheral region. This can further reduce the voltage drop of the reference voltage VSS and improve the uniformity of the reference voltage VSS.
  • the reference voltage grid VSSW includes a first reference voltage segment VSSW1 extending along the column direction DV and a second reference voltage segment VSSW2 extending along the row direction DH; the two ends of the first reference voltage segment VSSW1 are directly or indirectly connected to the adjacent second reference voltage segment VSSW2, thereby forming a grid structure.
  • the reference voltage grid VSSW also includes a third reference voltage segment VSSW3 that connects the first reference voltage segment VSSW1 to the second reference voltage segment VSSW2.
  • the shape of the third reference voltage segment VSSW3 is not limited; for example, it can be a zigzag structure or a multi-branch structure with multiple connecting arms.
  • the adjacent ends of the first reference voltage segment VSSW1 and the second reference voltage segment VSSW2 are interconnected through the third reference voltage segment VSSW3, thereby forming a grid. It is understood that some portions of the third reference voltage segment VSSW3 may also extend along the row direction DH or along the column direction DV.
  • multiple sub-pixels are disposed within the cutouts of the reference voltage grid VSSW.
  • four sub-pixels may be disposed within the cutouts of the reference voltage grid VSSW.
  • four adjacent sub-pixels in the same row are located within the same cutout.
  • the reference voltage grid VSSW has a first reference voltage line segment VSSW1 extending along the column direction DV; along the row direction DH, the first reference voltage line segment VSSW1 is located between the blue sub-pixel BPIX and the red sub-pixel RPIX; wherein, the distance between the first reference voltage line segment VSSW1 and the blue sub-pixel BPIX is less than the distance between the first reference voltage line segment VSSW1 and the red sub-pixel RPIX.
  • a planar structure (not specifically labeled in the accompanying drawings) exists between the sub-pixel PIX and the second source/drain metal layer SD2.
  • This planar structure includes a sub-film layer located in the second planarization layer PLN2 and a sub-film layer located in the third planarization layer PLN3.
  • the planar portion beneath the sub-pixel PIX includes two planarization layers with a large thickness and strong planarization performance, which can improve the planarity of the sub-pixel PIX and reduce the possibility of color shift.
  • the second source/drain metal layer SD2 has a power supply voltage trace VDDL extending along the column direction DV.
  • the power supply voltage trace VDDL includes a light-shielding portion and a cutout portion arranged sequentially along the column direction DV (the light-shielding portion and the cutout portion are not labeled in the accompanying drawings).
  • At least one sub-pixel PIX is located on the light-shielding portion by its orthographic projection onto the second source/drain metal layer SD2. For example, a green sub-pixel PIX is disposed on the light-shielding portion.
  • This disclosure also provides a display device, which includes the display panel provided in the above embodiments.
  • the display device can be a smartphone screen, a smartwatch screen, or other types of display devices. Since the display device has any of the display panels described in the above-described display panel embodiments, it has the same beneficial effects, and will not be repeated here.

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Abstract

一种显示面板和显示装置。显示面板包括阵列分布的电路区（PA）；显示面板包括依次层叠设置的衬底基板（SBT）、晶体管层（TL）、第一源漏金属层（SD1）、第二源漏金属层（SD2）和像素层（PIXL）；第一源漏金属层（SD1）设置有电源电压转接结构（VDLP）；电源电压转接结构（VDLP）用于向两个像素驱动电路同时提供电源电压（VDD）；电路区（PA）包括非异构电路区（PAN）和异构电路区（PAM）；异构电路区（PAM）中的电源电压转接结构（VDLP）的形状与非异构电路区（PAN）中的电源电压转接结构（VDLP）的形状不同，以使得第一源漏金属层（SD1）在异构电路区（PAM）具有沿列方向延伸的跨线通道；第一源漏金属层（SD1）在跨线通道中设置有电压跨接线（VLA），电压跨接线（VLA）与在列方向上相邻的两个电压走线（VL）电连接。所述显示面板以及设置有所述显示面板的显示装置可以降低电源信号的压降。

Description

显示面板和显示装置
交叉引用
本公开要求于2024年05月27日提交的申请号为202410667161.X名称为“显示面板及显示装置”的中国专利申请的优先权，该中国专利申请的全部内容通过引用全部并入本文。
技术领域
本公开涉及显示面板技术领域，具体而言，涉及一种显示面板及显示装置。
背景技术
随着显示行业的迅速发展，人们对于显示面板的画质追求越来越高，柔性著称的有机发光二极管显示器应用而生。显示面板上的电源信号的压降是导致画质下降的一个重要因素，有必要提供新的设计方案以降低显示面板上的电源信号的压降。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
本公开的目的在于克服上述现有技术的不足，提供一种显示面板及显示装置，有助于降低显示面板上的电源信号的压降。
根据本公开的一个方面，提供一种显示面板，包括阵列分布的电路区，所述电路区设置有分别用于驱动两个子像素的两个像素驱动电路；
所述显示面板包括依次层叠设置的衬底基板、晶体管层、第一源漏金属层、第二源漏金属层和像素层；
所述晶体管层设置有所述像素驱动电路的各个薄膜晶体管；所述晶体管层和所述第一源漏金属层中的至少一者设置有沿行方向延伸的电压走线；
所述第二源漏金属层设置有用于加载电源电压的电源电压走线，所述第一源漏金属层在所述电路区设置有电源电压转接结构；所述电源电压转接结构与所述电源电压走线电连接，用于向所述电路区的两个像素驱动电路同时提供电源电压；
其中，所述电路区包括非异构电路区和异构电路区；所述异构电路区中的电源电压转接结构的形状与所述非异构电路区中的电源电压转接结构的形状不同，以使得所述第一源漏金属层在所述异构电路区具有沿列方向延伸的跨线通道；所述第一源漏金属层在所述跨线通道中设置有电压跨接线，所述电压跨接线与在列方向上相邻的两个所述电压走线电连接。
根据本公开的一种实施方式，所述电压走线包括设于所述第一源漏金属层且用于加载参考电压的参考电压走线；
所述异构电路区包括参考异构电路区，所述电压跨接线包括位于所述参考异构电路区的参考电压跨接线，所述参考电压跨接线使得沿所述列方向的相邻两个所述参考电压走线电连接。
根据本公开的一种实施方式，所述电压走线还包括位于所述晶体管层且用于向所述像素驱动电路加载初始化电压的初始化电压走线；
所述异构电路区还包括初始化异构电路区，所述电压跨接线还包括初始化电压跨接线，所述初始化电压跨接线位于所述初始化异构电路区且使得沿所述列方向相邻的两个初始化电压走线电连接；
其中，所述参考电压走线在所述初始化异构电路区的跨线通道处被隔断，所述初始化电压跨接线穿过所述参考电压走线的隔断缺口。
根据本公开的一种实施方式，所述初始化电压走线的种类至少为两种，在每个所述初始化异构电路区中，仅设置一种所述初始化电压走线对应的所述初始化电压跨接线。
根据本公开的一种实施方式，其中，在所述非异构电路区中，所述电源电压转接结构具有第一子转接结构、第二子转接结构和第三子转接结构；所述第一子转接结构沿所述列方向延伸且在所述行方向上位于所述非异构电路区的中部，用于向两个所述像素驱动电路同时提供所述驱动电源电压；所述第二子转接结构和所述第三子转接结构分别位于所述第一子转接结构的两侧且分别通过过孔与所述电源电压走线电连接；
在所述异构电路区中，所述电源电压转接结构由所述第一子转接结构和所述第二子转接结构组成。
根据本公开的一种实施方式，其中，所述第一源漏金属层在所述电路区还设置有初始化电压转接结构，所述电压走线包括位于所述晶体管层且用于加载初始化电压的初始化电压走线；所述初始化电压转接结构与所述初始化电压走线电连接，用于向所述电路区的两个像素驱动电路同时提供所述初始化电压；
其中，所述非异构电路区中的初始化电压转接结构的形状与所述异构电路区中的初始化电压转接结构的形状不同，以使得所述异构电路区中的初始化电压转接结构避让所述跨线通道。
根据本公开的一种实施方式，其中，在所述非异构电路区中，所述初始化电压转接结构包括依次连接的第四子转接结构、第五子转接结构和第六子转接结构；所述第五子转接结构和所述第六子转接结构在所述行方向上分别设置于所述第四子转接结构的两侧，分别用于通过过孔与所述初始化电压走线电连接；所述第四子转接结构通过过孔同时向所述电路区的两个像素驱动电路提供所述初始化电压；
在所述异构电路区中，所述初始化电压转接结构由所述第四子转接结构和所述第五子转接结构组成。
根据本公开的一种实施方式，其中，所述电路区包括沿所述行方向相邻的第一子电路区和第二子电路区；所述第一子电路区和所述第二子电路区分别设置所述像素驱动电路；所述异构电路区的跨线通道设置于所述异构电路区的第一子电路区；
所述非异构电路区中，所述第一源漏金属层在所述第一子电路区的图案与在所述第二子电路区的图案轴对称设置；
所述第一源漏金属层在所述非异构电路区的第二子电路区的图案与在所述异构电路区的第二子电路区的图案相同；
所述第一源漏金属层在所述异构电路区的第一子电路区的图案与在所述非异构电路区的第一子电路区的图案不同。
根据本公开的一种实施方式，其中，所述第一源漏金属层在所述异构电路区的第一子电路区的跨线通道以外的区域的图案，与所述第一源漏金属层在所述非异构电路区的第一子电路区的相同区域的图案相同。
根据本公开的一种实施方式，其中，在所述电路区中，半导体层在所述第一子电路区的图案与在所述第二子电路区的图案轴对称设置。
根据本公开的一种实施方式，其中，在所述电路区行中，所述非异构电路区和所述异构电路区交替设置。
根据本公开的一种实施方式，其中，在所述电路区列中，所述非异构电路区和所述异构电路区交替设置。
根据本公开的一种实施方式，其中，所述电压走线包括设于所述第一源漏金属层的参考电压走线和设于所述晶体管层的初始化电压走线；所述参考电压走线用于加载参考电压，所述初始化电压走线用于向所述像素驱动电路加载初始化电压；
所述异构电路区包括参考异构电路区和初始化异构电路区；所述第一源漏金属层在所述参考异构电路区设置有使得相邻两个所述参考电压走线电连接的参考电压跨接线；所述第一源漏金属层在所述初始化异构电路区设置有使得相邻两个所述初始化电压走线电连接的初始化电压跨接线；
沿所述行方向，相邻两个所述初始化异构电路区之间设置有至少一个所述参考异构电路区。
根据本公开的一种实施方式，其中，所述初始化电压走线包括用于加载第一初始化电压的第一初始化电压走线、用于加载第二初始化电压的第二初始化电压走线、用于加载第三初始化电压的第三初始化电压走线；所述初始化异构电路区包括在所述第一源漏金属层设置第一初始化电压跨接线的第一初始化异构电路区、在所述第一源漏金属层设置第二初始化电压跨接线的第二初始化异构电路区、在所述第一源漏金属层设置第三初始化电压跨接线的第三初始化异构电路区；所述第一初始化电压跨接线使得相邻两个第一初始化电压走线电连接，所述第二初始化电压跨接线使得相邻两个第二初始化电压走线电连接，所述第三初始化电压跨接线使得相邻两个第三初始化电压走线电连接；
在同行设置的异构初始化电压区中，所述第一初始化异构电路区、所述第二初始化异构电路区、所述第三初始化异构电路区和所述第二初始化异构电路区呈周期性依次排列。
根据本公开的一种实施方式，所述初始化电压走线包括用于加载第一初始化电压的第一初始化电压走线、用于加载第二初始化电压的第二初始化电压走线、用于加载第三初始化电压的第三初始化电压走线；所述初始化异构电路区包括在所述第一源漏金属层设置第一初始化电压跨接线的第一初始化异构电路区、在所述第一源漏金属层设置第二初始化电压跨接线的第二初始化异构电路区、在所述第一源漏金属层设置第三初始化电压跨接线的第三初始化异构电路区；所述第一初始化电压跨接线使得相邻两个第一初始化电压走线电连接，所述第二初始化电压跨接线使得相邻两个第二初始化电压走线电连接，所述第三初始化电压跨接线使得相邻两个第三初始化电压走线电连接；
每相邻两行设置的初始化异构电路区中，其中一行的所述初始化异构电路区按照所述第一初始化异构电路区、所述第二初始化异构电路区、所述第三初始化异构电路区和所述第二初始化异构电路区呈周期性依次排列；
相邻两行中的另一行初始化异构电路区中按照所述第三初始化异构电路区、所述第二初始化异构电路区、所述第一初始化异构电路区和所述第二初始化异构电路区呈周期性依次排列。
根据本公开的一种实施方式，其中，所述电压走线包括设于所述第一源漏金属层的参考电压走线和设于所述晶体管层的初始化电压走线；所述参考电压走线用于加载参考电源电压，所述初始化电压走线用于向所述像素驱动电路加载初始化电压；
所述异构电路区包括参考异构电路区和初始化异构电路区；所述第一源漏金属层在所述参考异构电路区设置有使得相邻两个参考电压走线电连接的参考电压跨接线；所述第一源漏金属层在所述初始化异构电路区设置有使得相邻两个初始化电压走线电连接的初始化电压跨接线；同一所述电路区列中的各个所述异构电路区相同。
根据本公开的一种实施方式，其中，所述电压走线包括设于所述晶体管层的初始化电压走线；所述初始化电压走线用于向所述像素驱动电路加载初始化电压；
所述电路区在所述第一源漏金属层设置有初始化电压转接结构，所述初始化电压转接结构通过过孔与所述初始化电压走线、所述薄膜晶体管电连接，以使得所述初始化电压加载至所述像素驱动电路；
所述异构电路区包括初始化异构电路区；所述第一源漏金属层在所述初始化异构电路区设置有初始化电压跨接线，所述初始化电压跨接线的两端分别与同列相邻的两个所述初始化电压转接结构电连接。
根据本公开的一种实施方式，其中，所述显示面板还包括依次层叠于所述第二源漏金属层远离所述第一源漏金属层一侧的第二平坦化层、第三源漏金属层和第三平坦化层；所述第三源漏金属层设置有参考电压网格；所述像素层设于所述第三平坦化层远离所述第二源漏金属层的一侧；所述参考电压网格的镂空孔内设置多个子像素。
根据本公开的一种实施方式，其中，
所述参考电压网格具有沿所述列方向延伸的第一参考电压线段；沿所述行方向，所述第一参考电压线段位于蓝色子像素和红色子像素之间；其中，所述第一参考电压线段与所述蓝色子像素之间的距离，大于所述第一参考电压线段与红色子像素之间的距离。
根据本公开的另一个方面，提供一种显示装置，包括所述显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开一种实施方式中，显示面板的膜层结构示意图。
图2为本公开一种实施方式中，显示面板中电路区的分布示意图。
图3为本公开一种实施方式中，参考电压跨接线和初始化电压跨接线的示意图。
图4为本公开一种实施方式中，像素驱动电路的示意图。
图5-1为本公开一种实施方式中，异构电路区与非异构电路区排布示意图。
图5-2为本公开一种实施方式中，异构电路区与非异构电路区排布示意图。
图6为本公开一种实施方式中，低温多晶硅半导体层的结构示意图。
图7为本公开一种实施方式中，第一栅极层的结构示意图。
图8为本公开一种实施方式中，第二栅极层的结构示意图。
图9为本公开一种实施方式中，金属氧化物半导体层的结构示意图。
图10为本公开一种实施方式中，第三栅极层的结构示意图。
图11为本公开一种实施方式中，非异构电路区中，第一源漏金属层的结构示意图。
图12为本公开一种实施方式中，第二源漏金属层的结构示意图。
图13为本公开一种实施方式中，参考异构电路区中，第一源漏金属层的结构示意图。
图14为本公开一种实施方式中，第一初始化异构电路区中，第一源漏金属层的结构示意图。
图15为本公开一种实施方式中，第二初始化异构电路区中，第一源漏金属层的结构示意图。
图16为本公开一种实施方式中，第三初始化异构电路区中，第一源漏金属层的结构示意图。
图17为本公开一种实施方式中，第三栅极层的结构示意图。
图18为本公开一种实施方式中，第三源漏金属层的结构示意图。
图19为本公开一种实施方式中，第二源漏金属层与第三源漏金属层局部叠层以及子像素排布的示意图。
图20-1为本公开一种实施方式中，异构电路区与非异构电路区排布示意图。
图20-2为本公开一种实施方式中，异构电路区与非异构电路区排布示意图。
图21为本公开一种实施方式中，第一初始化电压跨接线的示意图。
图22为本公开一种实施方式中，第二初始化电压跨接线的示意图。
图23为本公开一种实施方式中，参考电压跨接线的示意图。
图24为本公开一种实施方式中，第三初始化电压跨接线的示意图。
图25为本公开一种实施方式中，第一初始化电压跨接线的示意图。
图26为本公开一种实施方式中，第三初始化电压跨接线的示意图。
图27为本公开一种实施方式中，第二初始化异构电路区的分布示意图。
图28为本公开一种实施方式中，第三初始化异构电路区的分布示意图。
附图标记说明：
PA、电路区；PA1、第一子电路区；PA2、第二子电路区；PAN、
非异构电路区；PAM、异构电路区；PAMS、参考异构电路区；PAMT、初始化异构电路区；PAMT1、第一初始化异构电路区；PAMT2、第二初始化异构电路区；PAMT3、第三初始化异构电路区；VDDL、电源电压走线；VLA、电压跨接线；VSSW、参考电压网格；VSSW1、第一参考电压线段；VSSW2、第二参考电压线段；VSSW3、第三参考电压线段；VSL、参考电压走线；VSLA、参考电压跨接线；VTL、初始化电压走线；VTL1、第一初始化电压走线；VTL2、第二初始化电压走线；VTL3、第三初始化电压走线；VTLA、初始化电压跨接线；VTL1A、第一初始化电压跨接线；VTL2A、第二初始化电压跨接线；VTL3A、第三初始化电压跨接线；VTLP、初始化电压转接结构；MA1、第一桥接部；MA2、第二桥接部；MA3、第三桥接部；MA4、第四桥接部；MA5、第五桥接部；MA6、第六桥接部；MA7、第七桥接部；MA8、第八桥接部；MA9、第九桥接部；VDLP、电源电压转接结构；MA31、第一子转接结构；MA32、第二子转接结构；MA33、第三子转接结构；MA61、第四子转接结构；MA62、第五子转接结构；MA63、第六子转接结构；SBT、衬底基板；DRL、驱动层；TL、晶体管层；LS、遮光层；LSCL、低温多晶硅半导体层；Buff1、第一缓冲层；Buff2、第二缓冲层；GI1、第一栅极绝缘层；GI2、第二栅极绝缘层；GT1、第一栅极层；GT2、第二栅极层；GT3、第三栅极层；ILD、层间电介质层；SD1、第一源漏金属层；SD2、第二源漏金属层；SD3、第三源漏金属层；PLN1、第一平坦化层；PLN2、第二平坦化层；PLN3、第三平坦化层；OSCL、金属氧化物半导体层；PDL、像素定义层；COML、公共电极层；EL、发光功能层；ANL、像素电极层；PIXL、像素层；PIX、子像素；TFE、薄膜封装层；T1、第一电容复位晶体管；T2、阈值补偿晶体管；T3、驱动晶体管；T4、数据写入晶体管；T5、第一发光控制晶体管；T6、第二发光控制晶体管；T7、电极复位晶体管；T8、第二电容复位晶体管；CST、存储电容；CP1、第一电极；CP2、第二电极；Vinit1、第一初始化电压；Vinit2、第二初始化电压；Vinit3、第三初始化电压；Rest1、第一电容复位控制信号；Rest2、第二电容复位控制信号；N1、第一节点；N2、第二节点；N3、第三节点；N4、第四节点；N5、第五节点；GN、第一扫描信号；Source、驱动数据信号；GP、第二扫描信号；VDD、电源电压；VSS、参考电压；EM、使能信号；T1A、第一电容复位晶体管的沟道区；T2A、阈值补偿晶体管的沟道区；T3A、驱动晶体管的沟道区；T4A、数据写入晶体管的沟道区；T5A、第一发光控制晶体管的沟道区；T6A、第二发光控制晶体管的沟道区；T7A、电极复位晶体管的沟道区；T8A、第二电容复位晶体管的沟道区；HB1、第一上过孔区；HB2、第二上过孔区；HB3、第三上过孔区；HB4、第四上过孔区；HB5、第五上过孔区；HB6、第六上过孔区；HB7、第七上过孔区；HB8、第八上过孔区；HB9、第九上过孔区；HB10、第十上过孔区；HB11、第十一上过孔区；HB12、第十二上过孔区；HB13、第十三上过孔区；HB14、第十四上过孔区；HB15、第十五上过孔区；HB16、第十六上过孔区；HB17、第十七上过孔区；HB18、第十八上过孔区；HB19、第十九上过孔区；HB20、第二十上过孔区；HB21、第二十一上过孔区；HA1、第一下过孔区；HA2、第二下过孔区；HA3、第三下过孔区；HA4、第四下过孔区；HA5、第五下过孔区；HA6、第六下过孔区；HA7、第七下过孔区；HA8、第八下过孔区；HA9、第九下过孔区；HA10、第十下过孔区；HA11、第十一下过孔区；HA12、第十二下过孔区；HA13、第十三下过孔区；HA14、第十四下过孔区；HA15、第十五下过孔区；HA16、第十六下过孔区；HA17、第十七下过孔区；HA18、第十八下过孔区；HA19、第十九下过孔区；HA20、第二十下过孔区；HA21、第二十一下过孔区；RL1、第一电容复位控制信号线；RL2、第二电容复位控制信号线；EML、使能信号线；GNLA、第一扫描信号走线；GNLB、第二扫描信号走线；GPL、第三扫描信号走线；VL、电压走线；DH、行方向；DV、列方向；DL、数据信号走线；HPA、电路区行；VPA、电路区列；CG、断线缺口；RPIX、红色子像素；BPIX、蓝色子像素；GPIX、绿色子像素。
具体实施方式
现在将参考附图更全面地描述示例实施方式。然而，示例实施方式能够以多种形式实施，且不应被理解为限于在此阐述的实施方式；相反，提供这些实施方式使得本公开将全面和完整，并将示例实施方式的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。此外，附图仅为本公开的示意性图解，并非一定是按比例绘制。
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。
用语“一个”、“一”、“该”、“所述”和“至少一个”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等；用语“第一”、“第二”和“第三”等仅作为标记使用，不是对其对象的数量限制。
结构层A位于结构层B背离衬底基板的一侧，可以理解为，结构层A在结构层B背离衬底基板的一侧形成。当结构层B为图案化结构时，结构层A的部分结构也可以位于结构层B的同一物理高度或低于结构层B的物理高度，其中，衬底基板为高度基准。
在本公开实施方式中，薄膜晶体管包括层叠设置的有源层、栅极绝缘层和栅极。其中，有源层位于半导体层，且有源层包括沟道区和分别位于沟道区两侧的第一极和第二极。其中，沟道区保持半导体特性，第一极和第二极均被导体化。在本公开实施方式中，在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“第一极”及“第二极”的功能有时互相调换，即“第一极”和“第二极”可以互相调换。在本公开实施方式中，对于任意一个晶体管，将“第一极”和“第二极”中的一者称为该晶体管的第一极，且另一者称为该晶体管的第二极。
随着显示行业的迅速发展，人们对于显示装置的画质追求越来越高。显示面板上的电源信号的压降是导致显示面板画质下降的一个重要因素，有必要提供新的设计方案以降低显示面板上的电源信号的压降。
基于此，本公开实施方式提供一种显示面板以及应用该显示面板的显示装置。参见图1，显示面板可以包括依次层叠设置的衬底基板SBT、驱动层DRL和像素层PIXL；像素层PIXL中设置有作为子像素PIX的发光元件(本附图中未进行展示)，且驱动层DRL设置有用于驱动子像素PIX的像素驱动电路；各个子像素PIX可以在像素驱动电路的驱动下发光以显示画面。进一步的，显示面板还包括位于像素层PIXL远离驱动层DRL一侧的薄膜封装层TFE，薄膜封装层TFE可以对像素层PIXL进行封装保护。
可选的，衬底基板SBT可以为无机材料的衬底基板SBT，也可以为有机材料的衬底基板SBT；当然的，也可以为无机材料的衬底基板SBT和有机材料的衬底基板SBT层叠而成的复合基板。举例而言，在本公开的一些实施方式中，衬底基板SBT的材料可以为钠钙玻璃、石英玻璃、蓝宝石玻璃等玻璃材料。在本公开的另外一些实施方式中，衬底基板SBT的材料可以为聚甲基丙烯酸甲酯、聚乙烯醇、聚乙烯基苯酚、聚醚砜、聚酰亚胺、聚酰胺、聚缩醛、聚碳酸酯、聚对苯二甲酸乙二酯、聚萘二甲酸乙二酯或其组合。在本公开的另一些实施方式中，衬底基板SBT也可以为柔性衬底基板SBT，例如衬底基板SBT的材料可以包括聚酰亚胺。
可选的，在驱动层DRL中，任意一个像素驱动电路可以包括有薄膜晶体管和存储电容CST(本申请附图对此未做展示)。进一步地，薄膜晶体管可以选自顶栅型薄膜晶体管、底栅型薄膜晶体管或者双栅型薄膜晶体管；薄膜晶体管的有源层的材料可以为非晶硅半导体材料、低温多晶硅半导体材料、金属氧化物半导体材料、有机半导体材料、碳纳米管半导体材料或者其他类型的半导体材料；薄膜晶体管可以为N型薄膜晶体管或者P型薄膜晶体管。
可以理解的是，像素驱动电路中的各个晶体管中，任意两个晶体管之间的类型可以相同或者不相同。示例性地，在一些实施方式中，在一个像素驱动电路中，部分晶体管可以为N型晶体管且部分晶体管可以为P型晶体管。
再示例性地，在另一些实施方式中，在一个像素驱动电路中，部分晶体管的有源层的材料可以为低温多晶硅半导体材料，且部分晶体管的有源层的材料可以为金属氧化物半导体材料。在本公开的一些实施方式中，薄膜晶体管为低温多晶硅晶体管。在本公开的另外一些实施方式中，部分薄膜晶体管为低温多晶硅晶体管，部分薄膜晶体管为金属氧化物晶体管。
可选地，驱动层DRL可以包括层叠于衬底基板SBT和像素层PIXL之间的半导体层(例如图1所示的低温多晶硅半导体层LSCL和金属氧化物半导体层OSCL)、栅极绝缘层(例如图1所示的第一栅极绝缘层GI1、第二栅极绝缘层GI2和第三栅极绝缘层GI3)、栅极层(例如图1所示的第一栅极层GT1、第二栅极层GT2和第三栅极绝缘层GT3)、层间电介质层ILD、源漏金属层(例如图1所示的第一源漏金属层SD1、第二源漏金属层SD2和第三源漏金属层SD3)、平坦化层(例如图1所示的第一平坦化层PLN1、第二平坦化层PLN2和第三平坦化层PLN3)等。各个薄膜晶体管和存储电容CST可以由半导体层、栅极绝缘层、栅极层、层间电介质层ILD、源漏金属层等膜层形成；当然的，也可以借助其他膜层。其中，各个膜层的位置关系可以根据薄膜晶体管的膜层结构确定。进一步地，半导体层可以用于形成晶体管的沟道区(作为有源层的一部分)，在必要时也可以通过导体化而形成部分走线或者导电结构。栅极层可以用于形成扫描走线、复位控制走线、发光控制走线等栅极层走线中的一种或者多种，也可以用于形成晶体管的栅极，还可以用于形成存储电容CST的部分或者全部电极板。源漏金属层可以用于形成数据走线、电源电压走线VDDL(参见图12)等源漏金属层走线，也可以用于形成存储电容CST的部分电极板。当然的，在本公开的其他实施方式中，驱动层DRL还可以根据需要而包括其他膜层，例如还可以包括位于半导体层和衬底基板SBT之间的遮光层LS等。
根据需要，上述半导体层、栅极层、源漏金属层等膜层中的任意一种还可以为多层，例如驱动层DRL中可以包括不同的两层半导体层，或者包括两层或者三层源漏金属层或者包括两层或者三层的栅极层；相应的，驱动层DRL中的绝缘性膜层(例如栅极绝缘层、层间电介质层ILD、平坦化层等)可以适应性的增加或者减少，或者根据需要增设新的绝缘性膜层。
可选地，驱动层DRL还可以包括有钝化层(本附图对此未作具体标注)，钝化层可以设于源漏金属层远离衬底基板SBT的表面，以便保护源漏金属层。
作为一种示例，驱动层DRL可以包括依次层叠设置的缓冲层(例如图1所示的第一缓冲层Buff1和第二缓冲层Buff2)、半导体层、栅极绝缘层、栅极层、层间电介质层ILD、源漏金属层和平坦化层，如此所形成的薄膜晶体管为顶栅型薄膜晶体管。
在另一种示例中，参见图1，驱动层DRL可以包括依次层叠设置的第一缓冲层Buff1、低温多晶硅半导体层LSCL、第一栅极绝缘层GI1、第一栅极层GT1、第二缓冲层Buff2、第二栅极绝缘层GI2、第二栅极层GT2、层间电介质层ILD、金属氧化物半导体层OSCL、第三栅极绝缘层、第三栅极层GT3、第一源漏金属层SD1、第一平坦化层PLN1、第二源漏金属层SD2、第二平坦化层PLN2、第三源漏金属层SD3、第三平坦化层PLN3。
可选的，参见图1，像素层PIXL可以包括依次层叠设置的像素电极层ANL、发光功能层EL和公共电极层COML。其中，像素电极层ANL在显示面板的显示区具有多个像素电极(本申请附图中对此为做具体标注)。像素定义层PDL具有与多个像素电极一一对应设置的多个贯通的像素开口，任意一个像素开口暴露对应的像素电极的至少部分区域。例如，像素定义层PDL覆盖像素电极的边缘且暴露像素电极的至少部分内部区域，以使得像素定义层PDL可以有效的定义像素电极的实际有效区域(直接与发光功能层EL连接的区域)，进而定义子像素PIX的发光区域和发光面积。公共电极层COML作为公共电极而覆盖发光功能层EL。像素电极和公共电极层COML向发光功能层EL提供电子、空穴等载流子，以使得发光功能层EL发光。发光功能层EL位于像素电极和公共电极层COML之间的部分，可以作为子像素PIX的发光功能单元。像素电极、公共电极层COML、发光功能单元形成作为子像素PIX的发光元件。其中，像素电极和公共电极层COML中的一者作为子像素PIX的阳极，且另一者作为子像素PIX的阴极。
在该示例中，显示面板为OLED(有机发光二极管)显示基板。发光功能层EL可以包括有机发光层，以及可以包括有空穴注入层、空穴传输层、电子阻挡层、空穴阻挡层、电子传输层、电子注入层中的一种或者多种。进一步的，有机发光层可以包括发光层主体材料和发光层客体材料，该发光层客体材料可以为荧光掺杂剂或者磷光掺杂剂，尤其是可以为热激活延迟荧光材料。
可以理解的是，该显示面板还可以为其他类型的显示面板，例如还可以为QLED(电至发光量子点)显示面板、QD-OLED(电致发光量子点和有机发光二极管结合)显示面板或者其他类型的显示面板。
参见图1，薄膜封装层TFE可以设于像素层PIXL远离衬底基板SBT的表面，其可以包括交替层叠设置的无机封装层和有机封装层。无机封装层可以有效的阻隔外界的水分和氧气，避免水氧入侵像素层PIXL而导致中像素层PIXL的材料老化。
可选地，无机封装层的边缘可以位于外围区。有机封装层位于相邻的两层无机封装层之间，以便实现平坦化和减弱无机封装层之间的应力。其中，有机封装层的边缘可以位于显示区的边缘和无机封装层的边缘之间。
示例性地，薄膜封装层TFE包括依次层叠于像素层PIXL远离衬底基板SBT一侧的第一无机封装层、有机封装层和第二无机封装层(本申请附图对此未作具体展示)。当然的，在本公开的其他实施方式中，显示面板也可以不设置薄膜封装层TFE，而是采用其他方式对像素层PIXL进行封装和保护。
在本公开的一些实施方式中，显示面板还可以包括触控金属层(本申请附图对此未作具体展示)，触控金属层可以设置于薄膜晶体管远离像素层PIXL的一侧，以使得该显示面板具有触控功能。
在该实施方式中，参见图1，驱动层DRL还可以包括晶体管层TL、第一源漏金属层SD1和第二源漏金属层SD2；晶体管层TL为设置于衬底基板SBT和第一源漏金属层SD1之间的各个膜层的组合，其可以形成有像素驱动电路所需的各个薄膜晶体管。
参见图2，根据薄膜晶体管的位置，该显示面板的显示区可以包括阵列分布的电路区PA，每个电路区PA设置有分别用于驱动两个子像素PIX的两个像素驱动电路。具体的，电路区PA可以包括沿行方向DH相邻设置的第一子电路区PA1和第二子电路区PA2，第一子电路区PA1中设置有一个像素驱动电路的各个薄膜晶体管，第二子电路区PA2中设置有另一个像素驱动电路的各个薄膜晶体管。进一步的，像素驱动电路的各个电容板也可以设置有晶体管中。当然的，第一源漏金属层SD1的至少部分结构可以作为电容板的一部分。
在该实施方式中，参见图2，在晶体管层TL和第一源漏金属层SD1中的至少一者可以设置有沿行方向DH延伸的电压走线VL，该电压走线VL可以向像素驱动电路提供电源电压，或者降低加载至像素驱动电路或者子像素PIX的电源电压的压降。
在本公开的一种实施方式中，参见图3，电压走线VL可以包括用于加载参考电压VSS的参考电压走线VSL，该参考电压走线VSL可以与像素层PIXL的公共电极层COML电连接，以降低参考电压VSS的压降，提高参考电压VSS的均一性，进而提高显示面板的画质。
在一种示例中，参考电压走线VSL可以在显示面板的外围区，与公共电极层COML电连接。进一步的，参考电压走线VSL可以设置于驱动层DRL的第一源漏金属层SD1。
在该实施方式的一种示例中，参考电压走线VSL可以与电路区行HPA一一对应设置。换言之，每一行电路区PA均设置一个参考电压走线VSL。这样可以尽量提高参考电压走线VSL的设置密度，进而提高参考电压VSS的均一化效果。
在本公开的另一种实施方式中，参见图3，电压走线VL可以包括用于向像素驱动电路加载初始化电压的初始化电压走线VTL，以便对像素驱动电路的节点或者像素电极进行电压复位。进一步的，电压走线VL可以设置于晶体管层TL，例如设置于晶体管层TL中的栅极层。可以理解的是，在该实施方式中，加载至像素驱动电路的初始化电压可以为一种，也可以为多种。当加载至像素驱动电路的初始化电压为多种时，多种初始化电压的电压值可以相同或者不同，不同种类的初始化电压分别加载在不同的初始化电压走线VTL上。
举例而言，初始化电压走线VTL可以包括位于第二栅极层GT2的第一初始化电压走线VTL1(参见图8)，以及位于第三栅极层GT3的第二初始化电压走线VTL2(参见图10)和第三初始化电压走线VTL3(参见图10)。第一初始电压走线VL1的端部具有第十七下过孔区HA17，第十七下过孔区HA17与第十七上过孔区HB17之间通过过孔区连接，第二初始化电压走线VTL2的端部具有与第十六下过孔区HA16，第十六下过孔区HA16与第十六上过孔区HB16之间通过过孔区连接。其中，第三初始化电压走线VTL3具有与第十五下过孔区HA15交叠的第十五上过孔区HB15，第十五下过孔区HA15和第十五上过孔区HB15之间通过过孔区连接。这样，电极复位晶体管T7的第一极电连接至第二初始化电压走线VTL2。当然的，在本公开的其他实施方式中，初始化电压走线VTL可以全部设置于第一源漏金属层SD1中。
图4为本公开一种示例性实施方式中的像素驱动电路的等效电路图。在该驱动像素电路中，初始化电压包括分别加载至像素驱动电路的不同节点的第一初始化电压Vinit1、第二初始化电压Vinit2和第三初始化电压Vinit3，则该晶体管层TL需要设置用于加载第一初始化电压Vinit1的第一初始化电压走线VTL1(参见图8)、用于加载第二初始化电压Vinit2的第二初始化电压走线VTL2(参见图10)、用于加载第三初始化电压Vinit3的第三初始化电压走线VTL3(参见图10)。其中，每行电路区PA均需要设置有对应的第一初始化电压走线VTL1、第二初始化电压走线VTL2和第三初始化电压走线VTL3。
以图4所示例的像素驱动电路为例，该像素驱动电路可以包括第一电容复位晶体管T1、阈值补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6、电极复位晶体管T7、第二电容复位晶体管T8和存储电容CST。其中：
其中，阈值补偿晶体管T2为N型薄膜晶体管，如金属氧化物薄膜晶体管；其余薄膜晶体管为P型薄膜晶体管，如低温多晶硅薄膜晶体管。
参见图4，第一电容复位晶体管T1的第一极用于加载第一初始化电压Vinit1，栅极用于加载第一电容复位控制信号Rest1，第二极与第三节点N3连接。第一电容复位晶体管T1用于，响应第一电容复位控制信号Rest1而向第三节点N3加载第一初始化电压Vinit1。阈值补偿晶体管T2的第一极与第三节点N3电连接，第二极与第一节点N1电连接，栅极用于加载第一扫描信号GN；阈值补偿晶体管T2用于响应第一扫描信号GN而导通，以将第一电容复位晶体管T1的第一初始化电压Vinit1写入第一节点N1。驱动晶体管T3的第一极连接第二节点N2，第二极连接第三节点N3，栅极连接第一节点N1，驱动晶体管T3被配置为，能够在驱动晶体管T3的控制端上的电压的控制下输出驱动电流。数据写入晶体管T4的第一极用于加载驱动数据信号Source，第二极与第二节点N2电连接，栅极用于加载第二扫描信号GP，数据写入晶体管T4的栅极用于加载第二扫描信号GP，而将驱动数据信号Source加载至第二节点N2。第一发光控制晶体管T5的第一极与第五节点N5电连接，第二极与第二节点N2连接，栅极用于加载使能信号EM。第二发光控制晶体管T6的第一极与第三节点N3连接，第二极与第四节点N4连接，栅极用于加载使能信号EM。第一发光控制晶体管T5和第二发光控制晶体管T6用于响应使能信号EM而导通。电极复位晶体管T7的第一极用于加载第二初始化电压Vinit2，栅极用于加载第二电容复位控制信号Rest2，第二极与第四节点N4连接，电极复位晶体管T7用于，响应第二电容复位控制信号Rest2而向第四节点N4加载第二初始化电压Vinit2。第二电容复位晶体管T8第一极用于加载第三初始化电压Vinit3，栅极用于加载第二电容复位控制信号Rest2，第二极与第二节点N2连接，第二电容复位晶体管T8用于，响应第二电容复位控制信号Rest2而向第二节点N2加载第三初始化电压Vinit3。发光元件的像素电极与驱动电路电连接(本申请对此未做具体展示)，公共电极用于加载参考电压VSS。存储电容CST一端连接第一节点N1，另一端连接第五节点N5。
可以理解的是，在本公开实施方式中，像素驱动电路也可以采用其他形式的像素驱动电路，例如采用7T1C(7个薄膜晶体管和1个存储电容)、7T2C(7个薄膜晶体管和2个存储电容)、5T1C(5个薄膜晶体管和1个存储电容)等像素驱动电路。
在本公开实施方式中，参见图3，为了进一步降低电压走线VL上加载的电源信号的压降，可以使得电压走线VL所加载的电源信号的分布呈现网格化。在本公开实施方式中，可以在第一源漏金属层SD1上设置电压跨接线VLA，该电压跨接线VLA可以使得相邻的两个相同的电压走线VL之间电连接，进而使得电压走线VL呈网格化。这样可以进一步降低电压走线VL上加载的电源信号的压降。
在本公开实施方式中，参见图5，可以按照是否设置电压跨接线VLA(参见图3)而将电路区PA分为非异构电路区PAN和异构电路区PAM。相较于非异构电路区PAN，异构电路区PAM的第一源漏金属层SD1的图案有所改变以设置电压跨接线VLA，进而使得电压走线VL上的电压信号分布呈网格化。
具体的，所述第二源漏金属层SD2设置有用于加载电源电压VDD的电源电压走线VDDL(参见图12)，所述第一源漏金属层SD1在所述电路区PA设置有电源电压转接结构VDLP(等同于本申请所述的第三桥接部MA3)；所述电源电压转接结构VDLP与所述电源电压走线VDDL电连接，用于向所述电路区PA的两个像素驱动电路同时提供电源电压VDD。
异构电路区PAM中的电源电压转接结构VDLP的形状与非异构电路区PAN中的电源电压转接结构VDLP的形状不同，以使得所述第一源漏金属层SD1在所述异构电路区PAM具有沿列方向延伸的跨线通道；第一源漏金属层SD1在跨线通道中设置有电压跨接线VLA，电压跨接线VLA与在列方向DV上相邻的两个电压走线VL电连接。
如下，以显示面板的像素驱动电路为图4所示例的像素驱动电路为例，对显示面板的一种膜层结构做示例性的介绍。可以理解的是，当显示面板的像素驱动电路改变时，显示面板的膜层结构可以发生改变。即便显示面板的像素驱动电路与图4的示例一致，显示面板的膜层结构也可以进行调整。
参见图6为该示例性显示面板的一个PA中的低温多晶硅半导体层LSCL的结构示意图。参见图6，在任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中，低温多晶硅半导体层LSCL设置有第一电容复位晶体管T1的有源层、驱动晶体管T3有源层、数据写入晶体管T4有源层、第一发光控制晶体管T5有源层、第二发光控制晶体管T6有源层、电极复位晶体管T7有源层和第二电容复位晶体管T8有源层，晶体管的有源层包括晶体管的第一极、第二极和沟道区。
其中，数据写入晶体管T4的第二极、第一发光控制晶体管T5的第二极、驱动晶体管T3的第一极之间电连接，驱动晶体管T3的第二极和第二发光控制晶体管T6的第一极之间电连接，电极复位晶体管T7的第二极和第二发光控制晶体管T6的第二极之间电连接。其中，第一电容复位晶体管T1的第一极具有第一下过孔区HA1，第一电容复位晶体管T1的第二极具有第二下过孔区HA2；数据写入晶体管T4的第一极具有第三下过孔区HA3，驱动晶体管T3的第二极具有第四下过孔区HA4，第一发光控制晶体管T5的第二极具有第五下过孔区HA5，第二发光控制晶体管T6的第二极具有第六下过孔区HA6，第二电容复位晶体管T8的第二极具有第七下过孔区HA7，第一发光控制晶体管T5的第一极具有第八下过孔区HA8，电极复位晶体管T7的第一极具有第九下过孔区HA9，第二电容复位晶体管T8的第一极具有第十下过孔区HA10。
在一种示例中，数据写入晶体管的沟道区T4A和第一发光控制晶体管的沟道区T5A沿列方向DV排列，第一发光控制晶体管的沟道区T5A和第二发光控制晶体管的沟道区T6A沿行方向DH排列。沿行方向DH，驱动晶体管的沟道区T3A和电极复位晶体管的沟道区T7A位于第一发光控制晶体管的沟道区T5A和第二发光控制晶体管的沟道区T6A之间；沿列方向DV，电极复位晶体管的沟道区T7A和驱动晶体管的沟道区T3A位于第一发光控制晶体管的沟道区T5A的两侧。
图7为该示例性显示面板的一个电路区PA中的第一栅极层GT1的结构示意图。参见图7，第一栅极层GT1形成有沿行方向DH延伸的第一电容复位控制信号线RL1、第二电容复位控制信号线RL2、第三扫描信号走线GPL、使能信号线EML和存储电容CST的第一电极CP1；其中，第一电容复位控制信号线RL1沿行方向DH延伸，用于向第一电容复位晶体管T1加载第一电容复位控制信号Rest1；第二电容复位控制信号线RL2沿行方向DH延伸，用于向第二电容复位晶体管T8加载第二电容复位控制信号Rest2；使能信号线EML沿行方向DH延伸，且依次与第一发光控制晶体管的沟道区T5A和第二发光控制晶体管的沟道区T6A交叠，以复用为第一发光控制晶体管T5的栅极和第二发光控制晶体管T6的栅极。使能信号线EML可以用于加载使能信号EM。存储电容CST的第一电极CP1与驱动晶体管的沟道区T3A交叠，以复用为驱动晶体管T3的栅极；第三扫描信号走线GPL沿行方向DH延伸，第三扫描信号走线GPL可以与数据写入晶体管的沟道区T4A交叠，交叠部分复用为数据写入晶体管T4的栅极；存储电容CST的第一电极CP1与驱动晶体管的沟道区T3A交叠，以复用为驱动晶体管T3的栅极。其中，存储电容CST的第一电极CP1设置有第十三下过孔区HA13。
图8为该示例性显示面板的一个非异构电路区PAN中第二栅极层GT2的结构示意图。参见图8，第二栅极层GT2设置有第一初始化电压走线VTL1、存储电容CST的第二电极CP2和第二扫描信号走线GNLB；其中，第一初始化电压走线VTL1沿行方向DH延伸，可以用于加载第一初始化电压Vinit1；存储电容CST的第二电极CP2与存储电容CST的第一电极CP1交叠，且设置暴露存储电容CST的第一电极CP1部分区域的避让孔；第二扫描信号走线GNLB沿行方向DH延伸，用于加载第二扫描信号。在电路区PA中，存储电容CST的第二电极CP2设置有第十四下过孔区HA14。在电路区PA中，第一初始化电压走线VTL1在任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中均设置有第十七下过孔区HA17。
图9为该示例性显示面板的一个电路区PA中金属氧化物半导体层OSCL的结构示意图。参见图9，在电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中，金属氧化物半导体层OSCL设置有阈值补偿晶体管T2的第二极、第一极和沟道区，在一种示例中，沿列方向DV，第一电容复位晶体管的沟道区T1A位于阈值补偿晶体管的沟道区T2A远离驱动晶体管的沟道区T3A的一侧，阈值补偿晶体管的沟道区T2A与第一发光控制晶体管的沟道区T5A位于驱动晶体管的沟道区T3A的两侧。参见图9，在电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中，阈值补偿晶体管T2的第二极设置有第十一下过孔区HA11，阈值补偿晶体管T2的第一极设置有第十二下过孔区HA12。
图10为该示例性显示面板的一个非异构电路区PAN中第三栅极层GT3的结构示意图。参见图10，第三栅极层GT3设置有第二初始化电压走线VTL2、第三初始化电压走线VTL3和第一扫描信号走线GNLA。其中，第二初始化电压走线VTL2沿行方向DH延伸，第二初始化电压走线VTL2可以用于加载第二初始化电压Vinit2；第三初始化电压走线VTL3沿行方向DH延伸，第三初始化电压走线VTL3可以用于加载第三初始化电压Vinit3。第一扫描信号走线GNLA沿行方向DH延伸，第一扫描信号走线GNLA与阈值补偿晶体管的沟道区T2A交叠，两者交叠的部分复用为阈值补偿晶体管T2的第二栅极。参见图10，在非异构电路区PAN的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中，第三初始化电压走线VTL3具有第十五下过孔区HA15，第二初始化电压走线VTL2具有第十六下过孔区HA16。
图11为该示例性显示面板的一个非异构电路区PAN中第一源漏金属层SD1的结构示意图。参见图11，在电路区PA中，第一源漏金属层SD1设置有第一桥接部MA1～第九桥接部MA9。
参见图11，电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中设置有第一桥接部MA1。第一桥接部MA1具有第十一上过孔区HB11和第十三上过孔区HB13；其中，第十一上过孔区HB11与第十一下过孔区HA11交叠且通过过孔连接；第十三上过孔区HB13与第十三下过孔区HA13交叠且通过过孔连接。如此，阈值补偿晶体管T2的第二极通过第一桥接部MA1与第一电极CP1电连接。
参见图11，电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中设置有第二桥接部MA2。第二桥接部MA2具有第二上过孔区HB2、第四上过孔区HB4和第十二上过孔区HB12，第二上过孔区HB2与第二下过孔区HA2交叠，且通过过孔连接；第四上过孔区HB4与第四下过孔区HA4交叠，且通过过孔连接；第十二上过孔区HB12与第十二下过孔区HA12交叠，且通过过孔连接。这样，第一电容复位晶体管T1的第二极通过第二桥接部MA2与驱动晶体管T3的第二极电连接，阈值补偿晶体管T2的第一极电连接。
参见图11，在电路区PA中设置有一个第三桥接部MA3。第三桥接部MA3具有第十四上过孔区HB14、第八上过孔区HB8、第十九下过孔区HA19和第二十一下过孔区HA21，第十四上过孔区HB14与第十四下过孔区HA14交叠，且通过过孔连接。第八上过孔区HB8与第八下过孔区HA8交叠，且通过过孔连接。第十九上过孔区HB19与第十九下过孔区HA19交叠，且通过过孔连接，第二十一上过孔区HB21与第二十一下过孔区HA21交叠，且通过过孔连接。这样，存储电容CST的第二电极CP2和第一发光控制晶体管T5的第一极，可以通过第三桥接部MA3相互电连接。
在一种示例中，参见图11和图12，在非异构电路区PAN中，第三桥接部MA3具有第一子转接结构MA31、第二子转接结构MA32和第三子转接结构MA33。第一子转接结构MA31沿列方向DV延伸且在行方向DH上位于非异构电路区PAN的中部，用于通过过孔向两个像素驱动电路提供电源电压VDD，第一子转接结构MA31上设置有第十九下过孔区HA19。第二子转接结构MA32上设置有第二十一下过孔区HA21；第三子转接结构MA33上设置有第十九下过孔区HA19，其中，第二子转接结构MA32和第三子转接结构MA33分别位于第一子转接结构MA31的两侧且分别通过过孔与电源电压走线VDDL电连接。
参见图11，电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中设置有第四桥接部MA4。第四桥接部MA4具有第三上过孔区HB3和第十八下过孔区HA18，第三上过孔区HB3与第三下过孔区HA3交叠，且通过过孔连接，第十八上过孔区HB18与第十八下过孔区HA18交叠，且通过过孔连接。这样，数据写入晶体管T4的第一极通过第四桥接部MA4与数据信号走线DL(参见图12)连接。
参见图11，电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中设置有第五桥接部MA5。第五桥接部MA5具有第五上过孔区HB5和第七上过孔区HB7，第五上过孔区HB5与第五下过孔区HA5交叠，且通过过孔连接；第七上过孔区HB7与第七下过孔区HA7交叠，且通过过孔连接。这样，第一发光控制晶体管T5的第二极通过第五桥接部MA5与第二电容复位晶体管T8的第一极电连接。
参见图11，电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中设置有第六桥接部MA6(等同于初始化电压转接结构VTLP)。第六桥接部MA6具有第十上过孔区HB10和第十五上过孔区HB15，第十上过孔区HB10与第十下过孔区HA10交叠，且通过过孔连接，第十五上过孔区HB15与第十五下过孔区HA15交叠，且通过过孔连接；这样第三初始化电压走线VTL3通过第六桥接部MA6与第二电容复位晶体管T8的第二极电连接。
在一种示例中，参见图11，在非异构电路区PAN中，初始化电压转接结构VTLP包括第四子转接结构MA61、第五子转接结构MA62和第六子转接结构MA63。其中，第四子转接结构MA61位于第一子电路区PA1和第二子电路区PA2的连接处，且用于同时向两个像素驱动电路提供初始化电压(例如第三初始化电压Vinit3)。第五子转接结构MA62与第四子转接结构MA61相连且位于第二子电路区PA2，且通过过孔与VTL3电连接；第六子转接结构MA63与第四子转接结构MA61相连且位于第一子电路区PA1，且通过过孔与VTL3电连接。其中，第五子转接结构MA62和第六子转接结构MA63远离第四子转接结构MA61的端部均设置有第十五上过孔区HB15。
参见图11，电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中设置有第七桥接部MA7。第七桥接部MA7具有第九上过孔区HB9和第十六上过孔区HB16，第九上过孔区HB9与第九下过孔区HA9交叠，且通过过孔连接，第十六上过孔区HB16与第十六下过孔区HA16交叠，且通过过孔连接；这样第二初始化电压走线VTL2通过第七桥接部MA7与电极复位晶体管T7的第一极电连接。
参见图11，电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中设置有第八桥接部MA8。第八桥接部MA8具有第一上过孔区HB1和第十七上过孔区HB17，第一上过孔区HB1与第一下过孔区HA1交叠，且通过过孔连接；第十七上过孔区HB17与第十七下过孔区HA17交叠，且通过过孔连接；这样第一初始化电压走线VTL1通过第八桥接部MA8与第一电容复位晶体管T1的第一极电连接。
参见图11，电路区PA的任意一个子电路区(例如第一子电路区PA1或者第二子电路区PA2)中设置有第九桥接部MA9。第九桥接部MA9具有第六上过孔区HB6和第二十下过孔区HA20，第九上过孔区HB9与第九下过孔区HA9交叠，且通过过孔连接；第二十上过孔区HB20与第二十下过孔区HA20交叠，且通过过孔连接。如此，像素驱动电路所产生的驱动电流可以传输至第九桥接部MA9，进而传输至子像素。
参见图11，在该示例中，第一源漏金属层SD1还设置有用于加载参考电压VSS的参考电压走线VSL，参考电压走线VSL沿行方向DH延伸。在一种示例中，参考电压走线VSL位于第二桥接部MA2和第八桥接部MA8之间。在本公开的一种实施方式中，每个电路区行HPA均设置有对应的参考电压走线VSL。如此，可以保证参考电压走线VSL具有较大的分布密度，进而进一步减低参考电压VSS的压降。
图12为该示例性显示面板中第二源漏金属层SD2的局部结构示意图。参见图12，第二源漏金属层SD2包括沿列方向DV延伸的数据信号走线DL和电源电压走线VDDL。第二源漏金属层SD2还设置有第一导电结构MB1。
其中，数据信号走线DL与像素驱动电路列一一对应设置；数据信号走线DL在子电路区内具有第十八上过孔区HB18；第十八上过孔区HB18与第十八下过孔区HA18交叠且通过过孔电连接。如此，数据信号走线DL通过过孔与第四桥接部MA4电连接，进而使得数据信号走线DL与数据写入晶体管T4的第一极电连接，进而使得数据信号走线DL上加载的驱动数据信号Source能够加载至数据写入晶体管T4的第一极。
其中，电源电压走线VDDL与像素驱动电路列一一对应设置。在非异构电路区PAN中，两个电源电压走线VDDL分别设置有第十九上过孔区HB19、第二十一上过孔区HB21，第十九上过孔区HB19、第二十一上过孔区HB21分别与非异构电路区PAN中的两个第十九下过孔区HA19和第二十一下过孔区HB21交叠且通过过孔电连接。如此，非异构电路区PAN中的第三桥接部MA3通过两个过孔与两个电源电压走线VDDL电连接。进一步的，同一电路区列VPA中的两个电源电压走线VDDL相互连接而成为一个整体。在一种示例中，电源电压走线VDDL可以设置有突出部(本申请对此未做标注)，该电源电压走线VDDL的突出部可以覆盖阈值补偿晶体管的沟道区T2A。同一电路区列VPA中的两个电源电压走线VDDL的突出部相互连接。
其中，第一导电结构MB1具有第二十上过孔区HB20；同一子电路区中的第二十上过孔区HB20和第二十下过孔区HA20交叠且通过过孔电连接。进一步的，子像素的像素电极通过过孔与对应的子电路区中的第一导电结构MB1电连接；这使得子电路区中的像素驱动电路产生的驱动电流可以加载至对应的子像素。
在上述所示例的实施方式中，初始化电压包括第一初始化电压Vinit1、第二初始化电压Vinit2和第三初始化电压Vinit3。在该示例中，初始化电压走线VTL包括用于加载第一初始化电压Vinit1的第一初始化电压走线VTL1、用于加载第二初始化电压Vinit2的第二初始化电压走线VTL2和用于加载第三初始化电压Vinit3的第三初始化电压走线VTL3。在图8和图10的示例中，第一初始化电压走线VTL1设置于第二栅极层GT2，且第二初始化电压走线VTL2、第三初始化电压走线VTL3设置于第三栅极层GT3。可以理解的是，在本公开的其他实施方式中，第一初始化电压走线VTL1、第二初始化电压走线VTL2和第三初始化电压走线VTL3还可以设置在其他膜层。
在本公开实施方式中，异构电路区PAM中的电源电压转接结构VDLP的形状与非异构电路区PAN中的电源电压转接结构VDLP的形状不同，以使得第一源漏金属层SD1在异构电路区PAM中具有沿列方向DV延伸的跨线通道。第一源漏金属层SD1在异构电路区PAM中设置有电压跨接线VLA，电压跨接线VLA与相邻的两个加载相同信号的电压走线VL电连接。
可以理解的是，当驱动层DRL设置有多种电压走线VL时，电压跨接线VLA用于使得相邻的同一种电压走线VL电连接。在该实施方式中，由于电源电压转接结构VDLP同时向驱动电路区PA中的两个像素驱动电路提供电源电压VDD，因此即便电源电压转接结构VDLP变形以避让跨线通道，也不会影响向像素驱动电路的供电。
在本公开的一种实施方式中，参考电压走线VSL设于第一源漏金属层SD1且与各个电路区行HPA一一对应设置，即每个电路区行HPA中均设置有对应的参考电压走线VSL。在该实施方式中，异构电路区PAM包括参考异构电路区PAMS，参见图13，第一源漏金属层SD1在参考异构电路区PAMS的跨线通道中设置有作为电压跨接线VLA的参考电压跨接线VSLA，该参考电压跨接线VSLA可以使得相邻的两个参考电压走线VSL电连接。在该示例中，参考电压跨接线VSLA可以与参考电压走线VSL直接连接。
在本公开的一种实施方式中，异构电路区PAM包括初始化异构电路区PAMT，电压跨接线VLA包括位于初始化异构电路区PAMT且使得相邻两个初始化电压走线VTL电连接的初始化电压跨接线VTLA。进一步的，参考电压走线VSL在初始化异构电路区PAMT的跨线通道处被隔断而形成断线缺口(作为跨线通道的一部分)，初始化电压跨接线VTLA穿过参考电压走线VSL的断线缺口。
在该实施方式的一种示例中，初始化电压走线VTL的种类至少为两种；在每个初始化异构电路区PAMT中，仅设置一种初始化电压走线VTL对应的初始化电压跨接线VTLA。
在一种示例中，初始化电压走线VTL包括用于向像素驱动电路加载第一初始化电压Vinit1的第一初始化电压走线VTL1。参见图14，初始化异构电路区PAMT包括第一初始化异构电路区PAMT1，第一源漏金属层SD1在第一初始化异构电路区PAMT1具有跨线通道和位于跨线通道中的第一初始化电压跨接线VTL1A；第一初始化电压跨接线VTL1A的两端分别与相邻的两个第一初始化电压走线VTL1电连接(参见图25)。
在一种示例中，第一源漏金属层SD1在电路区PA中设置有第八桥接部MA8，第八桥接部MA8与第一初始化电压走线VTL1通过过孔连接，且通过过孔与像素驱动电路的薄膜晶体管连接。在第一初始化异构电路区PAMT1，第一初始化电压跨接线VTL1A的两端分别与两个第一初始化电压走线VTL1电连接的第八桥接部MA8电连接。这样，第一初始化电压跨接线VTL1A通过连接两个第八桥接部MA8，进而使得两个第一初始化电压走线VTL1电连接。举例而言，在图14的示例中，同列相邻的两个第八桥接部MA8通过位于第一初始化异构电路区PAMT1中的第一初始化电压跨接线VTL1A电连接，进而使得相邻两行的第一初始化电压走线VTL1电连接(参见图25)。
在一种示例中，在第一初始化异构电路区PAMT1中，参考电压走线VSL具有断线缺口CG，第一初始化电压跨接线VTL1A穿过参考电压走线VSL的断线缺口CG(作为跨线通道的一部分)。在该示例中，尽管参考电压走线VSL在第一初始化异构电路区PAMT1中设置断线缺口CG而呈不连续的多个子走线，但是位于不同电路区行HPA的子走线之间可以通过参考电压跨接线VSLA电连接(参见图23)，进而使得各个子走线相互连接成网，进而使得参考电压VSS在第一源漏金属层SD1上呈网格分布。
在一种示例中，初始化电压走线VTL包括用于向像素驱动电路加载第二初始化电压Vinit2的第二初始化电压走线VTL2；参见图15、图27，初始化异构电路区PAMT包括第二初始化异构电路区PAMT2，第一源漏金属层SD1在第二初始化异构电路区PAMT2具有跨线通道；第一源漏金属层SD1在跨线通道内设置有第二初始化电压跨接线VTL2A(参见图15)。第二初始化电压跨接线VTL2A的两端分别与相邻的两个第二初始化电压走线VTL2电连接(参见图22)。
在一种示例中，第一源漏金属层SD1设置有第七桥接部MA7，第七桥接部MA7与第二初始化电压走线VTL2通过过孔连接，且通过过孔与像素驱动电路的薄膜晶体管连接。在第二初始化异构电路区PAMT2，第二初始化电压跨接线VTL2A的两端分别与两个第二初始化电压走线VTL2电连接的第七桥接部MA7电连接。这样，第二初始化电压跨接线VTL2A通过连接两个第七桥接部MA7，进而使得两个第二初始化电压走线VTL2电连接。举例而言，在图15的示例中，同列相邻的两个第七桥接部MA7通过位于第二初始化异构电路区PAMT2中的第二初始化电压跨接线VTL2A电连接，进而使得相邻两行的第二初始化电压走线VTL2电连接(参见图22、图27)。
在一种示例中，参见图23，在第二初始化异构电路区PAMT2中，参考电压走线VSL具有断线缺口CG，第二初始化电压跨接线VTL2A穿过参考电压走线VSL的断线缺口CG(作为跨线通道的一部分)。在该示例中，尽管参考电压走线VSL在第二初始化异构电路区PAMT2中设置断线缺口CG而呈不连续的多个子走线，但是位于不同电路区行HPA的子走线之间可以通过参考电压跨接线VSLA电连接，进而使得各个子走线相互连接成网，进而使得参考电压VSS在第一源漏金属层SD1上呈网格分布。
在一种示例中，初始化电压走线VTL包括用于向像素驱动电路加载第三初始化电压Vinit3的第三初始化电压走线VTL3。参见图5、图16，初始化异构电路区PAMT包括第三初始化异构电路区PAMT3。第一源漏金属层SD1在第三初始化异构电路区PAMT3具有跨线通道；第一源漏金属层SD1在第三初始化异构电路区PAMT3的跨线通道中设置第三初始化电压跨接线VTL3A，第三初始化电压跨接线VTL3A的两端分别与相邻的两个第三初始化电压走线VTL3电连接(参见图26)。
在一种示例中，第一源漏金属层SD1在电路区PA中设置有第六桥接部MA6，第六桥接部MA6与第三初始化电压走线VTL3通过过孔连接，且通过过孔与像素驱动电路的薄膜晶体管连接。在第三初始化异构电路区PAMT3，第三初始化电压跨接线VTL3A的两端分别与两个第三初始化电压走线VTL3电连接的第六桥接部MA6电连接。这样，第三初始化电压跨接线VTL3A通过连接两个第六桥接部MA6，进而使得两个第三初始化电压走线VTL3电连接。举例而言，在图16的示例中，同列相邻的两个第六桥接部MA6通过位于第三初始化异构电路区PAMT3中的第三初始化电压跨接线VTL3A电连接，进而使得相邻两列的第三初始化电压走线VTL3电连接。
在一种示例中，在第三初始化异构电路区PAMT3中，参考电压走线VSL具有断线缺口CG，第三初始化电压跨接线VTL3A穿过参考电压走线VSL的断线缺口CG(作为跨线通道的一部分)。在该示例中，尽管参考电压走线VSL在第三初始化异构电路区PAMT3中设置断线缺口CG而呈不连续的多个子走线，但是位于不同电路区行HPA的子走线之间可以通过参考电压跨接线VSLA电连接，进而使得各个子走线相互连接成网，进而使得参考电压VSS在第一源漏金属层SD1上呈网格分布。
在本公开的一种实施方式中，电路区PA中的两个像素驱动电路在整体上可以采用对称设置，即整体上沿对称轴对称，该对称轴沿列方向延伸。可以理解的是，电路区PA中的两个像素驱动电路对称设置并非是指电路区PA的各个膜层的图案均呈对称设置，而是指电路区PA的两个像素驱动电路的晶体管的相对位置基本对称。当然的，驱动层DRL在电路区PA的至少部分膜层的图案可以呈对称设置。
在本公开的一种实施方式中，参见图6，第一子电路区PA1中的第一发光控制晶体管T5和第二子电路区PA2的第一发光控制晶体管T5相邻设置，两个第一发光控制晶体管T5第一极可以相互电连接。电路区PA中的电源电压转接结构VDLP可以通过一个过孔与两个第一发光控制晶体管T5第一极电连接。举例而言，第八下过孔区HA8和第八上过孔区HB8可以位于第一子电路区PA1和第二子电路区PA2的分界线上，这可以减少过孔数量，进而利于提高显示面板的分辨率。
在本公开的一种实施方式中，异构电路区PAM的跨线通道设置于异构电路区PAM的第一子电路区PA1中。参见图11，非异构电路区PAN中，第一源漏金属层SD1在第一子电路区PA1的图案与在第二子电路区PA2的图案轴对称设置。参见图11、图13～图16，第一源漏金属层SD1在非异构电路区PAN的第二子电路区PA2的图案与在异构电路区PAM的第二子电路区PA2的图案相同；第一源漏金属层SD1在异构电路区PAM的第一子电路区PA1的图案与在非异构电路区PAN的第一子电路区PA1的图案不同。进一步的，第一源漏金属层SD1在异构电路区PAM的第一子电路区PA1的跨线通道以外的区域的图案，与第一源漏金属层SD1在非异构电路区PAN的第一子电路区PA1的相同区域的图案相同。
在本公开的一种实施方式中，参见图13～图16，在异构电路区PAM中，第三桥接部MA3由第一子转接结构MA31和第二子转接结构MA32组成。换言之，在异构电路区PAM中，第三桥接部MA3没有设置第三子转接结构MA33以避让跨线通道。
在一种示例中，参见图13～图16，第一子转接结构MA31设置于第一子电路区PA1和第二子电路区PA2的连接处，第二子转接结构MA32设置于第二子电路区PA2中。非异构电路区PAN的第一子电路区PA1设置有第三子转接结构MA33，异构电路区PAM的第一子电路区PA1中不设置第三子转接结构MA33。
在本公开的一种实施方式中，像素驱动电路包括用于对驱动晶体管T3进行阈值补偿的阈值补偿晶体管T2。参见图13～图16，任意一个子电路区(例如第一子电路区PA1和第二子电路区PA2中的任意一个)设置有第一桥接部MA1，第一桥接部MA1使得阈值补偿晶体管T2的第二极与驱动晶体管T3的栅极电连接。在异构电路区PAM的第一子电路区PA1中，电压跨接线VLA设于第一桥接部MA1与第三桥接部MA3之间。
需要说明的是,本公开的显示面板中，像素驱动电路可以通过将阈值补偿晶体管T2设置为金属氧化物晶体管，减小第一节点N1的漏电，进而提高像素驱动电路的保压能力，降低显示面板在低频驱动下的闪烁风险并降低显示面板的功耗。
在本公开的一种实施方式中，第一源漏金属层SD1在电路区PA还设置有初始化电压转接结构VTLP(例如第六桥接部MA6)，电压走线VL包括位于晶体管层且用于加载初始化电压的初始化电压走线VTL(例如第三初始化电压走线VTL3)；初始化电压转接结构与初始化电压走线VTL电连接，用于向电路区PA的两个像素驱动电路同时提供初始化电压(例如Vinit3)。
其中，非异构电路区PAN中的初始化电压转接结构的形状与异构电路区PAM中的初始化电压转接结构的形状不同，以使得异构电路区PAM中的初始化电压转接结构VTLP避让跨线通道。
在该实施方式中，异构电路区PAM中的初始化电压转接结构VTLP也进行了形变，以避让跨线通道。
可选的，与初始化电压转接结构VTLP相连的两个薄膜晶体管相邻设置，以使得初始化电压转接结构VTLP通过一个过孔同时驱动两个像素驱动电路。举例而言，第一子电路区PA1中的第二电容复位晶体管T8和第二子电路区PA2中的第二电容复位晶体管T8相邻设置，且两个第二电容复位晶体管T8的第一极相互共用并设置第十下过孔区HA10。第十下过孔区HA10和第十上过孔区HB10位于第一子电路区PA1和第二子电路区PA2的分界线上。第一源漏金属层SD1设置有作为初始化电压转接结构的第六桥接部MA6，该第六桥接部MA6通过一个过孔同时向两个子电路区的第二电容复位晶体管T8加载第三初始化电压Vinit3。
在本公开的一种实施方式中，参见图13～图16，在异构电路区PAM中，第六桥接部MA6由第四子转接结构MA61和第五子转接结构MA62组成。换言之，在异构电路区PAM中，第六桥接部MA6没有设置第六子转接结构MA63以避让跨线通道。
在一种示例中，参见图13～图16，第四子转接结构MA61设置于第一子电路区PA1和第二子电路区PA2的连接处，其具有第十上过孔区HB10；第五子转接结构MA62设置于第二子电路区PA2中。非异构电路区PAN的第一子电路区PA1设置有第六子转接结构MA63，异构电路区PAM的第一子电路区PA1中不设置第六子转接结构MA63。
在图16的示例中，尽管第三初始化电压跨接线VTL3A的一部分与第六子转接结构MA63相同或者类似，但是第三初始化电压跨接线VTL3A上不设置与第三初始化电压走线VTL3电连接的第十五上过孔区HB15，其可以不被视为第六子转接结构MA63。当然的，第三初始化电压跨接线VTL3A与第三初始化电压走线VTL3的交叠位置也可以设置第十五上过孔区HB15，以使得第三初始化电压跨接线VTL3A直接通过过孔与第三初始化电压走线VTL3电连接。
在本公开实施方式中，第三栅极层GT3在非异构电路区PAN中的形状可以与在异构电路区PAM中的形状不同。图17示例了一种实施方式中第三栅极层GT3在异构电路区PAM中的结构。图10示例了一种实施方式中第三栅极层GT3在非异构电路区PAN中的结构。在非异构电路区PAN中，第三初始化电压走线VTL3具有两个膨大部，两个膨大部分别设置有第十五下过孔区HA15以便通过过孔与第六桥接部MA6电连接。换言之，在非异构电路区PAN，第三初始化电压走线VTL3在第一子电路区PA1中具有用于与第六子转接结构MA63电连接的膨大部，在第二子电路区PA2中具有用于与第五子转接结构MA62电连接的膨大部。在异构电路区PAM中，第三初始化电压走线VTL3具有一个膨大部；该膨大部具有第十五下过孔区HA15以便与第六桥接部MA6通过过孔电连接。换言之，在异构电路区PAM，第三初始化电压走线VTL3仅在第二子电路区PA2具有用于与第五子转接结构MA62电连接的膨大部，在第一子电路区PA1中不设置用于与第六子转接结构MA63电连接的膨大部。
当然的，在本公开的其他实施方式中，第三栅极层GT3在非异构电路区PAN和异构电路区PAM中的形状也可以相同。
在本公开的一种实施方式中，在电路区行HPA中，非异构电路区PAN和异构电路区PAM交替设置。如此，可以保证电源信号的网格化分布，确保网格密度和提高电源信号的均一性。
在本公开的一种实施方式中，在电路区列VPA中，非异构电路区PAN和异构电路区PAM交替设置。如此，可以保证电源信号的网格化分布，确保网格密度和提高电源信号的均一性。
在一种示例中，同一电路区列VPA中，异构电路区PAM为同一种异构电路区PAM。
在本公开的一种实施方式中，沿行方向DH，相邻两个初始化异构电路区PAMT之间设置有至少一个参考异构电路区PAMS。例如，沿行方向DH，相邻两个初始化异构电路区PAMT之间设置有两个参考异构电路区PAMS。这一方面，这使得参考电压走线VSSL在初始化异构电路区PAMT中被隔断的情况下依然可以保持网格化连接，另一方面使得参考电压VSS的网格密度大，进一步提高参考电压VSS的信号均一性(例如参见图27图28，图27为第二初始化异构电路区PAMT2和参考异构电路区PAMS的排布示意图，图28为第三初始化异构电路区PAMT3和参考异构电路区PAMS的排布示意图)。
在本公开的一种实施方式中，沿行方向DH，第一初始化异构电路区PAMT1、第二初始化异构电路区PAMT2、第三初始化异构电路区PAMT3和第二初始化异构电路区PAMT2呈周期性依次排列。在该实施方式中，第二初始化电压Vinit2的网格密度大于第一初始化电压Vinit1、第三初始化电压Vinit3的网格密度，可以使得更为关键的第二初始化电压Vinit2具有更好的信号稳定性，进而提高显示面板的画质。
可以理解的是，如果第一初始化电压Vinit1的稳定性对像素驱动电路的稳定性更为关键，也可以使得第一初始化异构电路区PAMT1的数量多于第二初始化异构电路区PAMT2、第三初始化异构电路区PAMT3；相应的，如果第三初始化电压Vinit3的稳定性对像素驱动电路的稳定性更为关键，也可以使得第三初始化异构电路区PAMT3的数量多于第二初始化异构电路区PAMT2、第一初始化异构电路区PAMT1。
在本公开的一种实施方式中，参见图5-1、图5-2(在图5-2中，N表示非异构电路区PAN、S表示参考异构电路区PAMS、1表示第一初始化异构电路区PAMT1、2表示第二初始化异构电路区PAMT2、3表示第三初始化异构电路区PAMT3)，同一电路区列VPA中，异构电路区PAM为同一种异构电路区PAM。在一种示例中，将参考异构电路区PAMS所在的电路区列VPA标记为S；则标记为S的电路区列VPA包括沿列方向DV依次交替设置的非异构电路区PAN、参考异构电路区PAMS。将第一初始化异构电路区PAMT1所在的的电路区列VPA标记为1，则标记为1的电路区列VPA包括沿列方向DV依次交替设置的非异构电路区PAN、第一初始化异构电路区PAMT1。将第二初始化异构电路区PAMT2所在的电路区列VPA标记为2，则标记为2的电路区列VPA包括沿列方向DV依次交替设置的非异构电路区PAN、第二初始化异构电路区PAMT2。将第三初始化异构电路区PAMT3所在的电路区列VPA标记为3，则标记为3的电路区列VPA包括沿列方向DV依次交替设置的非异构电路区PAN、第三初始化异构电路区PAMT3。在显示区的至少部分区域，连续24个电路区列VPA的排列方式可以为1SS1SS2SS2SS3SS3SS2SS2SS(参见图21～图24)。
在本公开的另一种实施方式中，参见图20-1、图20-2((在图20-2中，N表示非异构电路区PAN、S表示参考异构电路区PAMS、1表示第一初始化异构电路区PAMT1、2表示第二初始化异构电路区PAMT2、3表示第三初始化异构电路区PAMT3)，同一电路区列VPA中，异构电路区PAM为同一种异构电路区PAM。在一种示例中，将参考异构电路区PAMS所在的电路区列VPA标记为S，标记为S的电路区列VPA包括沿列方向DV依次交替设置的非异构电路区PAN、参考异构电路区PAMS。将第一初始化异构电路区PAMT1所在的电路区列VPA标记为1，标记为1的电路区列VPA包括沿列方向DV依次交替设置的非异构电路区PAN、第一初始化异构电路区PAMT1。将第二初始化异构电路区PAMT2所在的电路区列VPA标记为2，标记为2的电路区列VPA包括沿DV列方向依次交替设置的非异构电路区PAN、第二初始化异构电路区PAMT2。将第三初始化异构电路区PAMT3所在的电路区列VPA标记为3，标记为3的电路区列VPA包括沿列方向DV依次交替设置的非异构电路区PAN、第三初始化异构电路区PAMT3。在显示区的至少部分区域，连续24个电路区列VPA的排列方式可以为1SS3SS2SS2SS3SS1SS2SS2SS。这样，可以使得第一初始化电压跨接线VTL1A和第三初始化电压跨接线VTL3A的分布更为均匀，利于提高第一初始化电压Vinit1和第三初始化电压Vinit3的均一性(参见图25、图26)。
在本公开的一种实施方式中，参见图1，驱动层DRL还可以包括位于第二源漏金属层SD2远离第一源漏金属层SD1一侧的第三源漏金属层SD3；在第二源漏金属层SD2和第三源漏金属层SD3之间设置有第二平坦化层PLN2，在第三源漏金属层SD3远离第二源漏金属层SD2的一侧设置有第三平坦化层PLN3。换言之，驱动层DRL包括依次层叠设置的第二源漏金属层SD2、第二平坦化层PLN2、第三源漏金属层SD3、第三平坦化层PLN3。
在一种示例中，参见图18，第三源漏金属层SD3可以设置有参考电压网格VSSW，该参考电压网格VSSW可以在外围区与公共电极层COML电连接。这样可以进一步降低参考电压VSS的压降，提高参考电压VSS的均一性。
在一些实施方式中，参考电压网格VSSW包括沿列方向DV延伸的第一参考电压线段VSSW1和沿行方向DH延伸的第二参考电压线段VSSW2；第一参考电压线段VSSW1的两端分别于相邻的第二参考电压线段VSSW2直接或者间接连接，以此形成网格结构。
在一些示例中，参考电压网格VSSW还包括使得第一参考电压线段VSSW1与第二参考电压线段VSSW2连接的第三参考电压线段VSSW3；第三参考电压线段VSSW3的形状不做限制，例如可以为曲折结构，或者具有多个连接臂的多分支结构；第一参考电压线段VSSW1和第二参考电压线段VSSW2的相邻两端通过第三参考电压线段VSSW3相互连接，进而形成网格。可以理解的是，第三参考电压线段VSSW3的一些部分也可以沿行方向DH延伸或者沿列方向DV延伸。可选的，参见图19，参考电压网格VSSW的镂空孔内设置多个子像素PIX。例如，参考电压网格VSSW的镂空孔内可以设置有四个子像素PIX。在一种示例中，同行相邻的四个子像素PIX位于同一镂空内。
在本公开的一种实施方式中，参见图19，参考电压网格VSSW具有沿列方向DV延伸的第一参考电压线段VSSW1；沿所述行方向DH，第一参考电压线段VSSW1位于蓝色子像素BPIX和红色子像素RPIX之间；其中，第一参考电压线段VSSW1与蓝色子像素BPIX之间的距离，小于第一参考电压线段VSSW1与红色子像素RPIX之间的距离。
这样，可以避免参考电压网格VSSW的走线进入蓝色子像素PIX的范围内，避免蓝色子像素PIX的一侧被垫高而影响其平坦性，进而避免发生色偏问题。
在本公开的一种实施方式中，参见图19，所述子像素PIX与所述第二源漏金属层SD2之间具有平坦结构(本申请附图对此未作具体标注)，所述平坦结构包括位于所述第二平坦化层PLN2的子膜层和位于第三平坦化层PLN3的子膜层。在该示例中，子像素PIX下方的平坦部包括两层平坦化层，具有较大的厚度和较强的平坦性能，可以使子像素PIX的平坦性更好，降低色偏发生的可能性。
在本公开的一种实施方式中，参见图12，第二源漏金属层SD2具有沿列方向DV延伸的电源电压走线VDDL，电源电压走线VDDL包括沿列方向DV依次设置的遮光部和镂空部(本申请附图中对遮光部和镂空部未做标注)，至少一种子像素PIX在第二源漏金属层SD2的正投影位于遮光部上。例如，绿色子像素PIX设置于遮光部上。
本公开实施方式还提供一种显示装置，该显示装置包括上述实施方式的所提供的显示面板。
该显示装置可以为智能手机屏幕、智能手表屏幕或者其他类型的显示装置。由于该显示装置具有上述显示面板实施方式所描述的任意一种显示面板，因此具有相同的有益效果，本公开在此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由所附的权利要求指出。

Claims (20)

  1. 一种显示面板，包括阵列分布的电路区，所述电路区设置有分别用于驱动两个子像素的两个像素驱动电路；
    所述显示面板包括依次层叠设置的衬底基板、晶体管层、第一源漏金属层、第二源漏金属层和像素层；
    所述晶体管层设置有所述像素驱动电路的各个薄膜晶体管；所述晶体管层和所述第一源漏金属层中的至少一者设置有沿行方向延伸的电压走线；
    所述第二源漏金属层设置有用于加载电源电压的电源电压走线，所述第一源漏金属层在所述电路区设置有电源电压转接结构；所述电源电压转接结构与所述电源电压走线电连接，用于向所述电路区的两个像素驱动电路同时提供电源电压；
    其中，所述电路区包括非异构电路区和异构电路区；所述异构电路区中的电源电压转接结构的形状与所述非异构电路区中的电源电压转接结构的形状不同，以使得所述第一源漏金属层在所述异构电路区具有沿列方向延伸的跨线通道；所述第一源漏金属层在所述跨线通道中设置有电压跨接线，所述电压跨接线与在列方向上相邻的两个所述电压走线电连接。
  2. 根据权利要求1所述的显示面板，其中，所述电压走线包括设于所述第一源漏金属层且用于加载参考电压的参考电压走线；
    所述异构电路区包括参考异构电路区，所述电压跨接线包括位于所述参考异构电路区的参考电压跨接线，所述参考电压跨接线使得沿所述列方向的相邻两个所述参考电压走线电连接。
  3. 根据权利要求2所述的显示面板，其中，所述电压走线还包括位于所述晶体管层且用于向所述像素驱动电路加载初始化电压的初始化电压走线；
    所述异构电路区还包括初始化异构电路区，所述电压跨接线还包括初始化电压跨接线，所述初始化电压跨接线位于所述初始化异构电路区且使得沿所述列方向相邻的两个初始化电压走线电连接；
    其中，所述参考电压走线在所述初始化异构电路区的跨线通道处被隔断，所述初始化电压跨接线穿过所述参考电压走线的隔断缺口。
  4. 根据权利要求3所述的显示面板，其中，所述初始化电压走线的种类至少为两种，在每个所述初始化异构电路区中，仅设置一种所述初始化电压走线对应的所述初始化电压跨接线。
  5. 根据权利要求1所述的显示面板，其中，在所述非异构电路区中，所述电源电压转接结构具有第一子转接结构、第二子转接结构和第三子转接结构；所述第一子转接结构沿所述列方向延伸且在所述行方向上位于所述非异构电路区的中部，用于向两个所述像素驱动电路同时提供所述电源电压；所述第二子转接结构和所述第三子转接结构分别位于所述第一子转接结构的两侧且分别通过过孔与所述电源电压走线电连接；
    在所述异构电路区中，所述电源电压转接结构由所述第一子转接结构和所述第二子转接结构组成。
  6. 根据权利要求3所述的显示面板，其中，所述第一源漏金属层在所述电路区还设置有初始化电压转接结构，所述电压走线包括位于所述晶体管层且用于加载初始化电压的初始化电压走线；所述初始化电压转接结构与所述初始化电压走线电连接，用于向所述电路区的两个像素驱动电路同时提供所述初始化电压；
    其中，所述非异构电路区中的初始化电压转接结构的形状与所述异构电路区中的初始化电压转接结构的形状不同，以使得所述异构电路区中的初始化电压转接结构避让所述跨线通道。
  7. 根据权利要求6所述的显示面板，其中，在所述非异构电路区中，所述初始化电压转接结构包括依次连接的第四子转接结构、第五子转接结构和第六子转接结构；所述第五子转接结构和所述第六子转接结构在所述行方向上分别设置于所述第四子转接结构的两侧，分别通过过孔与所述初始化电压走线电连接；所述第四子转接结构通过过孔同时向所述电路区的两个像素驱动电路提供所述初始化电压；
    在所述异构电路区中，所述初始化电压转接结构由所述第四子转接结构和所述第五子转接结构组成。
  8. 根据权利要求1所述的显示面板，其中，所述电路区包括沿所述行方向相邻的第一子电路区和第二子电路区；所述第一子电路区和所述第二子电路区分别设置所述像素驱动电路；所述异构电路区的跨线通道设置于所述异构电路区的第一子电路区；
    所述非异构电路区中，所述第一源漏金属层在所述第一子电路区的图案与在所述第二子电路区的图案轴对称设置；
    所述第一源漏金属层在所述非异构电路区的第二子电路区的图案与在所述异构电路区的第二子电路区的图案相同；
    所述第一源漏金属层在所述异构电路区的第一子电路区的图案与在所述非异构电路区的第一子电路区的图案不同。
  9. 根据权利要求8所述的显示面板，其中，所述第一源漏金属层在所述异构电路区的第一子电路区的跨线通道以外的区域的图案，与所述第一源漏金属层在所述非异构电路区的第一子电路区的相同区域的图案相同。
  10. 根据权利要求8所述的显示面板，其中，在所述电路区中，半导体层在所述第一子电路区的图案与在所述第二子电路区的图案轴对称设置。
  11. 根据权利要求1所述的显示面板，其中，在所述电路区行中，所述非异构电路区和所述异构电路区交替设置。
  12. 根据权利要求1所述的显示面板，其中，在所述电路区列中，所述非异构电路区和所述异构电路区交替设置。
  13. 根据权利要求1所述的显示面板，其中，所述电压走线包括设于所述第一源漏金属层的参考电压走线和设于所述晶体管层的初始化电压走线；所述参考电压走线用于加载参考电压，所述初始化电压走线用于向所述像素驱动电路加载初始化电压；
    所述异构电路区包括参考异构电路区和初始化异构电路区；所述第一源漏金属层在所述参考异构电路区设置有使得相邻两个所述参考电压走线电连接的参考电压跨接线；所述第一源漏金属层在所述初始化异构电路区设置有使得相邻两个所述初始化电压走线电连接的初始化电压跨接线；
    沿所述行方向，相邻两个所述初始化异构电路区之间设置有至少一个所述参考异构电路区。
  14. 根据权利要求3所述的显示面板，其中，所述初始化电压走线包括用于加载第一初始化电压的第一初始化电压走线、用于加载第二初始化电压的第二初始化电压走线、用于加载第三初始化电压的第三初始化电压走线；所述初始化异构电路区包括在所述第一源漏金属层设置第一初始化电压跨接线的第一初始化异构电路区、在所述第一源漏金属层设置第二初始化电压跨接线的第二初始化异构电路区、在所述第一源漏金属层设置第三初始化电压跨接线的第三初始化异构电路区；所述第一初始化电压跨接线使得相邻两个第一初始化电压走线电连接，所述第二初始化电压跨接线使得相邻两个第二初始化电压走线电连接，所述第三初始化电压跨接线使得相邻两个第三初始化电压走线电连接；
    在同行设置的初始化异构电路区中，所述第一初始化异构电路区、所述第二初始化异构电路区、所述第三初始化异构电路区和所述第二初始化异构电路区呈周期性依次排列。
  15. 根据权利要求3所述的显示面板，其中，所述初始化电压走线包括用于加载第一初始化电压的第一初始化电压走线、用于加载第二初始化电压的第二初始化电压走线、用于加载第三初始化电压的第三初始化电压走线；所述初始化异构电路区包括在所述第一源漏金属层设置第一初始化电压跨接线的第一初始化异构电路区、在所述第一源漏金属层设置第二初始化电压跨接线的第二初始化异构电路区、在所述第一源漏金属层设置第三初始化电压跨接线的第三初始化异构电路区；所述第一初始化电压跨接线使得相邻两个第一初始化电压走线电连接，所述第二初始化电压跨接线使得相邻两个第二初始化电压走线电连接，所述第三初始化电压跨接线使得相邻两个第三初始化电压走线电连接；
    每相邻两行设置的初始化异构电路区中，其中一行的所述初始化异构电路区按照所述第一初始化异构电路区、所述第二初始化异构电路区、所述第三初始化异构电路区和所述第二初始化异构电路区呈周期性依次排列；
    相邻两行中的另一行初始化异构电路区中按照所述第三初始化异构电路区、所述第二初始化异构电路区、所述第一初始化异构电路区和所述第二初始化异构电路区呈周期性依次排列。
  16. 根据权利要求1所述的显示面板，其中，所述电压走线包括设于所述第一源漏金属层的参考电压走线和设于所述晶体管层的初始化电压走线；所述参考电压走线用于加载参考电压，所述初始化电压走线用于向所述像素驱动电路加载初始化电压；
    所述异构电路区包括参考异构电路区和初始化异构电路区；所述第一源漏金属层在所述参考异构电路区设置有使得相邻两个参考电压走线电连接的参考电压跨接线；所述第一源漏金属层在所述初始化异构电路区设置有使得相邻两个初始化电压走线电连接的初始化电压跨接线；同一所述电路区列中的各个所述异构电路区相同。
  17. 根据权利要求1所述的显示面板，其中，所述电压走线包括设于所述晶体管层的初始化电压走线；所述初始化电压走线用于向所述像素驱动电路加载初始化电压；
    所述电路区在所述第一源漏金属层设置有初始化电压转接结构，所述初始化电压转接结构通过过孔与所述初始化电压走线、所述薄膜晶体管电连接，以使得所述初始化电压加载至所述像素驱动电路；
    所述异构电路区包括初始化异构电路区；所述第一源漏金属层在所述初始化异构电路区设置有初始化电压跨接线，所述初始化电压跨接线的两端分别与同列相邻的两个所述初始化电压转接结构电连接。
  18. 根据权利要求1～17任意一项所述的显示面板，其中，所述显示面板还包括依次层叠于所述第二源漏金属层远离所述第一源漏金属层一侧的第二平坦化层、第三源漏金属层和第三平坦化层；所述第三源漏金属层设置有参考电压网格；所述像素层设于所述第三平坦化层远离所述第二源漏金属层的一侧；所述参考电压网格的镂空孔内设置多个子像素。
  19. 根据权利要求18所述的显示面板，其中，所述参考电压网格具有沿所述列方向延伸的第一参考电压线段；沿所述行方向，所述第一参考电压线段位于蓝色子像素和红色子像素之间；其中，所述第一参考电压线段与所述蓝色子像素之间的距离，大于所述第一参考电压线段与红色子像素之间的距离。
  20. 一种显示装置，包括权利要求1～19任意一项的所述显示面板。
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