WO2025246642A1 - 栅极驱动电路单元及其电路、显示基板及其制造方法、显示装置 - Google Patents

栅极驱动电路单元及其电路、显示基板及其制造方法、显示装置

Info

Publication number
WO2025246642A1
WO2025246642A1 PCT/CN2025/087160 CN2025087160W WO2025246642A1 WO 2025246642 A1 WO2025246642 A1 WO 2025246642A1 CN 2025087160 W CN2025087160 W CN 2025087160W WO 2025246642 A1 WO2025246642 A1 WO 2025246642A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
signal line
transistor
node
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/087160
Other languages
English (en)
French (fr)
Inventor
刘聪
宋江
胡明
邱海军
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025246642A1 publication Critical patent/WO2025246642A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2077—Display of intermediate tones by a combination of two or more gradation control methods

Definitions

  • This disclosure relates to the field of display technology, and in particular to a gate driving circuit unit, a gate driving circuit, a method for manufacturing a display substrate, a display substrate, and a display device.
  • GOA Gate driver on Array
  • This disclosure provides a gate driving circuit unit, a gate driving circuit, a method for manufacturing a display substrate, a display substrate, and a display device, which can improve the problems existing in the gate driving circuit unit in the related art.
  • a gate drive circuit unit comprising: a first input sub-circuit configured to control a voltage of a first node based on a signal at a first input terminal; a second input sub-circuit configured to control a voltage of a second node based on a signal at a second input terminal; a coupling sub-circuit configured to control a voltage of a third node based on the voltage of the first node; and a first output sub-circuit configured to transmit a signal at a third input terminal or a signal at a fourth input terminal to a first output terminal based on voltages applied to the second node and the third node.
  • the first input terminal receives a signal from the first signal line; the second input terminal receives a signal from the first potential signal line; the third input terminal receives a signal from the first clock signal line; and the fourth input terminal receives a signal from the second potential signal line.
  • the gate drive circuit unit further includes a first sustaining sub-circuit and a first reset sub-circuit;
  • the first input sub-circuit is electrically connected to the first signal line, the second clock signal line, and the first node, and is configured to input the signal of the first signal line to the first node under the signal control of the second clock signal line;
  • the second input sub-circuit is electrically connected to the first potential signal line, the second clock signal line, the second node, the first node, and the second potential signal line, and is configured to transmit the signal of the second potential signal line or the first potential signal line to the second node under the signal control of the first node and the second clock signal line;
  • the first sustaining sub-circuit is electrically connected to the second node, the first clock signal line, the second node, the first node, and the second potential signal line.
  • the first sustaining sub-circuit is configured to transmit the signal of the second potential signal line to the third node under the potential control of the second node;
  • the first output sub-circuit is electrically connected to the first clock signal line, the third node, the second node, and the second potential signal line, and is configured to transmit the signal of the first clock signal line or the second potential signal line to the first output terminal under the potential control of the third node and the second node;
  • the first reset sub-circuit is electrically connected to the first reset control terminal, the reset signal line, and one end of the coupling sub-circuit, and is configured to transmit the potential of the reset signal line to one end of the coupling sub-circuit under the signal control of the first reset control terminal.
  • the first input sub-circuit includes a first input transistor, the gate of which is electrically connected to the second clock signal line, the first electrode of which is electrically connected to the first signal line, and the second electrode of which is electrically connected to the first node;
  • the coupling sub-circuit includes a coupling capacitor, the first plate of which is electrically connected to the first node, and the second plate of which is electrically connected to the third node;
  • the first output sub-circuit includes a first output transistor and a second output transistor, the gate of which is electrically connected to the third node, the first electrode of which is electrically connected to the first clock signal line, the second electrode of which is electrically connected to the first output terminal, the gate of which is electrically connected to the second node, the second electrode of which is electrically connected to the second potential signal line, and the first electrode of which is electrically connected to the first output terminal.
  • the second input sub-circuit includes a second input transistor and a third input transistor.
  • the gate of the second input transistor is electrically connected to the first node, the first terminal of the second input transistor is electrically connected to the second potential signal line, and the second terminal of the second input transistor is electrically connected to the second node.
  • the gate of the third input transistor is electrically connected to the second clock signal line, the first terminal of the third input transistor is electrically connected to the first potential signal line, and the second terminal of the third input transistor is electrically connected to the second node.
  • the first sustaining sub-circuit includes a first sustaining transistor. The gate of the first sustaining transistor is electrically connected to the second node, the first terminal of the first sustaining transistor is electrically connected to the third node, and the second terminal of the first sustaining transistor is electrically connected to the second potential signal line.
  • the first reset sub-circuit includes a first reset transistor, the gate of the first reset transistor being the first reset control terminal, the first electrode of the first reset transistor being electrically connected to the reset signal line, and the second electrode of the first reset transistor being electrically connected to the third node.
  • the first reset control terminal is electrically connected to any one of the first signal line, the first node of the cascaded gate drive circuit unit in the gate drive circuit, the third node of the cascaded gate drive circuit unit in the gate drive circuit, and the first plate of the cascaded coupling capacitor in the gate drive circuit.
  • the first input sub-circuit further includes a fourth input transistor, the gate of which is electrically connected to the first potential signal line, the first terminal of which is electrically connected to the second terminal of the first input transistor, and the second terminal of which is electrically connected to the first plate of the coupling capacitor; or/and the first output sub-circuit further includes a first capacitor, the first plate of which is electrically connected to the gate of the second output transistor, and the second plate of which is electrically connected to the second terminal of the second output transistor.
  • the first signal line is a start signal line. Before the first signal line outputs a first low-level signal, the signal of the reset signal line is a high-level signal, and the high-level signal of the reset signal line is greater than the high-level signal of the first signal line. When the first signal line outputs a first low-level signal, the signal of the reset signal line is a low-level signal.
  • the gate drive circuit unit further includes at least one of a second reset sub-circuit and a second sustaining sub-circuit;
  • the first reset sub-circuit is electrically connected to one end of the coupling sub-circuit electrically connected to the third node
  • the second reset sub-circuit is electrically connected to a second reset control terminal, the reset signal line, and one end of the coupling sub-circuit electrically connected to the first node
  • the second reset sub-circuit is used to transmit the potential of the reset signal line to one end of the coupling sub-circuit electrically connected to the first node under the signal control of the second reset control terminal
  • the second sustaining sub-circuit is electrically connected to the second node, the second potential signal line, and one end of the coupling sub-circuit electrically connected to the first node
  • the second sustaining sub-circuit is used to transmit the signal of the second potential signal line to one end of the coupling sub-circuit electrically connected to the first node under the potential control of the second node.
  • the second reset sub-circuit includes a second reset transistor, the gate of which is the second reset control terminal, the first terminal of which is electrically connected to the reset signal line, and the second terminal of which is electrically connected to one end of the coupling sub-circuit electrically connected to the first node;
  • the second sustaining sub-circuit includes a second sustaining body transistor, the gate of which is electrically connected to the second node, the first terminal of which is electrically connected to one end of the coupling sub-circuit electrically connected to the first node, and the second terminal of which is electrically connected to the second potential signal line.
  • the gate drive circuit unit further includes a second output sub-circuit configured to transmit a signal from a fifth input terminal or a sixth input terminal to a second output terminal based on the voltage applied to the second node and the third node.
  • the fifth input terminal receives a signal from the first clock signal line
  • the sixth input terminal receives a signal from the second potential signal line.
  • the first clock signal line received by the fifth input terminal is different from the first clock signal line received by the third input terminal; the high potential in the first clock signal line received by the fifth input terminal is greater than the high potential in the first clock signal line received by the third input terminal; the low potential in the first clock signal line received by the fifth input terminal is less than the low potential in the first clock signal line received by the third input terminal; the second potential signal line received by the sixth input terminal is different from the second potential signal line received by the fourth input terminal; the potential in the second potential signal line received by the sixth input terminal is greater than the potential in the second potential signal line received by the fourth input terminal.
  • the signal in the first signal line is a start signal
  • the signal in the first potential signal line is a low potential
  • the signal in the second potential signal line is a high potential
  • the thin-film transistors in the gate drive circuit unit are all P-type.
  • a gate driving circuit including at least one cascaded circuit, each cascaded circuit including a plurality of gate driving circuit units connected in sequence, wherein the gate driving circuit units are the gate driving circuit units provided in the first aspect of this disclosure.
  • a method for manufacturing a display substrate comprising: providing a substrate; and manufacturing at least one cascaded circuit on the substrate, each cascaded circuit including a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit units are the gate driving circuit units provided in the first aspect of this disclosure.
  • a display substrate including the gate driving circuit unit provided in the first aspect of this disclosure.
  • the coupling sub-circuit in the gate driving circuit unit includes a coupling capacitor;
  • the first output sub-circuit includes a first output transistor and a second output transistor;
  • the display substrate includes a substrate and a gate metal layer disposed on one side of the substrate, the gate metal layer includes the second plate of the coupling capacitor and the gate of the first output transistor, and the second plate of the coupling capacitor and the gate of the first output transistor are directly connected.
  • the first output sub-circuit in the gate driving circuit unit further includes a first capacitor, the coupling capacitor and the first capacitor are arranged along a first direction; the gate metal layer further includes a second plate of the first capacitor and the gate of the second output transistor, and the second plate of the first capacitor and the gate of the second output transistor are directly connected; in a second direction, the first output transistor and the second output transistor are located on the same side of the coupling capacitor and the first capacitor, and the first direction intersects the second direction.
  • the second input sub-circuit in the gate driving circuit unit includes a second input transistor and a third input transistor;
  • the display substrate further includes a first sustaining sub-circuit and a first reset sub-circuit, the first sustaining sub-circuit including a first sustaining transistor;
  • the first reset sub-circuit including a first reset transistor;
  • the display substrate includes a semiconductor layer located between the substrate and the gate metal layer, the semiconductor layer including a continuous first semiconductor pattern, and the active portions of the second input transistor, the first sustaining transistor, and the first reset transistor are formed by the first semiconductor pattern.
  • the first semiconductor pattern includes a first sub-semiconductor pattern, a second sub-semiconductor pattern, and a third sub-semiconductor pattern, wherein the second sub-semiconductor pattern is connected between the first sub-semiconductor pattern and the third sub-semiconductor pattern, the extension direction of the first sub-semiconductor pattern is parallel to the extension direction of the third sub-semiconductor pattern, and the extension direction of the second sub-semiconductor pattern is non-linear; the first sub-semiconductor pattern includes the active portion of the second input transistor, the second sub-semiconductor pattern includes the active portion of the first sustaining transistor, and the third sub-semiconductor pattern includes the active portion of the first reset transistor.
  • the channel extension direction of the active portion of the second input transistor, the channel extension direction of the active portion of the first sustaining transistor, and the channel extension direction of the active portion of the first reset transistor are parallel to each other.
  • the first input sub-circuit in the gate drive circuit unit includes a first input transistor; the first input sub-circuit also includes a fourth input transistor; in the second direction, the first input transistor, the fourth input transistor, the second input transistor, the third input transistor, the first sustaining transistor, and the first reset transistor are all located on one side of the coupling capacitor and the first capacitor, and the first output transistor and the second output transistor are both located on the other side of the coupling capacitor and the first capacitor.
  • the display substrate includes a first clock signal line, a second clock signal line, a first potential signal line, a second potential signal line, and a reset signal line;
  • the first clock signal line includes a first sub-clock line and a second sub-clock line, and the signals in the first sub-clock line and the second sub-clock line are the same;
  • the second clock signal line includes a third sub-clock line and a fourth sub-clock line, and the signals in the third sub-clock line and the fourth sub-clock line are the same;
  • the second potential signal line includes a first sub-potential line and a second sub-potential line, and the signals in the first sub-potential line and the second sub-potential line are the same;
  • the first sub-clock line, the third sub-clock line, the first sub-potential line, the first potential signal line, the reset signal line, the fourth sub-clock line, the second sub-clock line, and the second sub-potential line are arranged sequentially along the second direction; the orthographic projection of the coupling capacitor
  • the orthographic projection of the first reset transistor on the substrate at least partially overlaps with the orthographic projection of the reset signal line on the substrate; the orthographic projection of the first capacitor on the substrate at least partially overlaps with the orthographic projections of the fourth sub-clock line and the second sub-clock line on the substrate; in the first direction, the first reset transistor and the first capacitor are located on the same side of the coupling capacitor; the orthographic projection of the second sub-potential line on the substrate is located on the side of the first output transistor and the second output transistor away from the coupling capacitor.
  • a display device including a gate driving circuit, the gate driving circuit including the gate driving circuit unit provided in the first aspect of this disclosure.
  • Figure 1 is a schematic diagram of a first type of gate drive circuit unit provided in some embodiments of this disclosure
  • Figure 2 is a waveform diagram of multiple signal lines or signals of a first type of gate drive circuit unit provided in some embodiments of this disclosure
  • Figure 3 is a second circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure.
  • Figure 4 is a third circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure.
  • Figure 5 is a waveform diagram of multiple signal lines or signals of a second type of gate drive circuit unit provided in some embodiments of this disclosure
  • Figure 6 is a fourth circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure.
  • Figure 7 is a fifth circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure.
  • Figure 8 is a sixth circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure.
  • Figure 9 is a schematic layout diagram of one of the gate drive circuit units provided in some embodiments of this disclosure.
  • Figure 10 is a schematic layout diagram of the semiconductor layer of a gate drive circuit unit provided in some embodiments of this disclosure.
  • Figure 11 is a schematic layout of the gate metal layer of a gate driving circuit unit provided in some embodiments of the present disclosure.
  • Figure 12 is a schematic layout of the capacitor metal layer of a gate drive circuit unit provided in some embodiments of this disclosure.
  • Figure 13 is a schematic layout of the second insulating layer of a gate drive circuit unit provided in some embodiments of the present disclosure
  • Figure 14 is a schematic layout of the first metal layer of a gate drive circuit unit provided in some embodiments of the present disclosure.
  • Figure 15 is a schematic layout of the third insulating layer of a gate drive circuit unit provided in some embodiments of the present disclosure.
  • Figure 16 is a schematic layout of the second metal layer of a gate drive circuit unit provided in some embodiments of the present disclosure.
  • gate drive circuit units require a large number of thin-film transistors and capacitors. These units occupy a significant area in the layout or display panel, resulting in structural complexity that hinders the narrow bezel requirements of display panels. While some gate drive circuit units have simplified structures, they still suffer from unstable high-performance signal output. The output signal potential is insufficient (e.g., the high-potential signal is not high enough, and the low-potential signal is not low enough), making it difficult for the gate drive circuit to stably output electrical signals that meet display or driving requirements.
  • the present disclosure provides a gate drive circuit unit that can improve or solve the above-mentioned technical problems.
  • This disclosure also provides a gate driving circuit, including at least one cascaded circuit, each cascaded circuit including a plurality of gate driving circuit units cascaded in sequence, the gate driving circuit units being the gate driving circuit units described above.
  • This disclosure also provides a method for manufacturing a display substrate, comprising: providing a substrate; and manufacturing at least one cascaded circuit on the substrate, each cascaded circuit including a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit units are the gate driving circuit units described above.
  • This disclosure also provides a display substrate, which includes the gate driving circuit unit described above.
  • This disclosure also provides a display device, which includes a gate driving circuit, the gate driving circuit including the gate driving circuit unit described above.
  • This disclosure provides a gate drive circuit unit, comprising: a first input sub-circuit configured to control the voltage of a first node based on a signal at a first input terminal; a second input sub-circuit configured to control the voltage of a second node based on a signal at a second input terminal; a coupling sub-circuit configured to control the voltage of a third node based on the voltage of the first node; and a first output sub-circuit configured to transmit a signal at a third input terminal or a signal at a fourth input terminal to a first output terminal based on the voltages applied to the second node and the third node.
  • Figure 1 is a schematic diagram of a first type of gate drive circuit unit provided in some embodiments of this disclosure
  • Figure 2 is a waveform diagram of multiple signal lines or signals of a first type of gate drive circuit unit provided in some embodiments of this disclosure.
  • Figure 3 is a second circuit diagram of a gate driving circuit unit provided in some embodiments of the present disclosure
  • Figure 4 is a third circuit diagram of a gate driving circuit unit provided in some embodiments of the present disclosure
  • Figure 5 is a waveform diagram of multiple signal lines or signals of a second type of gate driving circuit unit provided in some embodiments of the present disclosure
  • Figure 6 is a fourth circuit diagram of a gate driving circuit unit provided in some embodiments of the present disclosure
  • Figure 7 is a fifth circuit diagram of a gate driving circuit unit provided in some embodiments of the present disclosure.
  • Figure 8 is a sixth circuit diagram of a gate drive circuit unit provided in some embodiments of this disclosure.
  • the gate driving circuit unit 1000 includes a first input sub-circuit 100, a second input sub-circuit 400, a coupling sub-circuit 200, and a first output sub-circuit 300.
  • the first input sub-circuit 100 is configured to control the voltage of a first node N1 based on a signal from a first input terminal 101;
  • the second input sub-circuit 400 is configured to control the voltage of a second node N2 based on a signal from a second input terminal 102;
  • the coupling sub-circuit 200 is at least configured to control the voltage of a third node N3 based on the voltage of the first node N1;
  • the first output sub-circuit 300 is configured to transmit a signal from a third input terminal 103 or a signal from a fourth input terminal 104 to a first output terminal OUT1 based on the voltages applied to the second node N2 and the third node N3.
  • the gate drive circuit unit 1000 may also be referred to as a shift register.
  • the signal output by the first output terminal OUT1 can be a gate drive signal (scan drive signal), which can be provided to the pixel drive circuit.
  • the signal output by the first output terminal OUT1 can also be a cascade signal, which can be provided to the next stage or other cascaded gate drive circuit units 1000.
  • the coupling sub-circuit 200 may also be configured to control the voltage of the first node N1 based on the voltage of the third node N3. For instance, in one time phase, the coupling sub-circuit 200 may be configured to control the voltage of the third node N3 based on the voltage of the first node N1, and in another time phase, the coupling sub-circuit 200 may also be configured to control the voltage of the first node N1 based on the voltage of the third node N3.
  • the first input sub-circuit 100 is configured to control the voltage of the first node N1 based on the signal from the first input terminal 101; the second input sub-circuit 400 is configured to control the voltage of the second node N2 based on the signal from the second input terminal 102; the coupling sub-circuit 200 is configured to control the voltage of the third node N3 based on the voltage of the first node N1; and the first output sub-circuit 300 is configured to transmit the signal from the third input terminal 103 or the signal from the fourth input terminal 104 to the first output terminal OUT1 based on the voltages applied to the second node N2 and the third node N3.
  • the voltage of the third node N3 can be controlled according to the voltage of the first node N1, so that the electrical signal of the third node N3 can better match the display or driving requirements.
  • the high potential of the third node N3 can be made higher, or the low potential of the third node N3 can be made lower.
  • the signal of the third input terminal 103 can be better transmitted to the first output terminal OUT1.
  • the signal of the third input terminal 103 can be better isolated from the first output terminal OUT1, thereby improving the stability of the output signal of the gate drive circuit unit 1000.
  • the gate driving circuit unit 1000 includes the first input sub-circuit 100, the second input sub-circuit 400, the coupling sub-circuit 200, and the first output sub-circuit 300.
  • the gate driving circuit unit 1000 has a simple structure, and the number of thin-film transistors and capacitors included in the gate driving circuit unit 1000 is relatively small.
  • the area occupied by the gate driving circuit unit 1000 in the layout or display panel is relatively small. That is, the gate driving circuit unit 1000 has the effect of simple structure, which is beneficial to the narrow bezel of the display panel.
  • the gate drive circuit unit 1000 provided in this disclosure has the advantages of simple structure and stable output of electrical signals that meet display requirements.
  • the gate drive circuit unit 1000 satisfies at least one of the following conditions: the first input terminal 101 receives the signal of the first signal line STV; the second input terminal 102 receives the signal of the first potential signal line VGL; the third input terminal 103 receives the signal of the first clock signal line CB; and the fourth input terminal 104 receives the signal of the second potential signal line VGH.
  • the gate drive circuit unit 1000 simultaneously satisfies the following conditions: the first input terminal 101 receives the signal from the first signal line STV; the second input terminal 102 receives the signal from the first potential signal line VGL; the third input terminal 103 receives the signal from the first clock signal line CB; and the fourth input terminal 104 receives the signal from the second potential signal line VGH.
  • the gate drive circuit unit 1000 may satisfy some of the above conditions.
  • one of the signals on the first potential signal line VGL and the second potential signal line VGH is a low potential signal and the other is a high potential signal.
  • the signal of the first potential signal line VGL is used as a low potential signal and the signal of the second potential signal line VGH is used as a high potential signal for illustration, but it is not limited to this.
  • this disclosure uses the signal of the first signal line STV as the starting signal for illustration, but is not limited thereto.
  • this disclosure uses the third input terminal 103 receiving the signal of the first clock signal line CB as an example, but is not limited thereto.
  • this disclosure uses the fourth input terminal 104 receiving the signal of the second potential signal line VGH as an example, but is not limited thereto.
  • the signal of the first clock signal line CB and the signal of the second clock signal line CK are out of phase for at least a portion of the time.
  • the first clock signal line CB is the inverted signal of the second clock signal line CK, but this is not limited to that. As shown in Figure 2.
  • the third input terminal 103 receives the first clock signal line CB.
  • the signal of the first clock signal line CB is an electrical signal that alternates between high and low potentials.
  • the signal of the first clock signal line CB can also control the voltage of the third node N3 (e.g., through the coupling effect between the capacitor and the parasitic capacitance).
  • the potential of the third node N3 can be controlled simultaneously by the first output sub-circuit 300 (first output transistor T5). This reduces the number of thin-film transistors and capacitors included in the gate drive circuit unit 1000, resulting in a simple structure for the gate drive circuit unit 1000, which is beneficial for narrow bezels of the display panel.
  • the gate drive circuit unit 1000 further includes a first sustaining sub-circuit 500 and a first reset sub-circuit 600.
  • the first input sub-circuit 100 is electrically connected to the first signal line STV, the second clock signal line CK and the first node N1.
  • the first input sub-circuit 100 is used to input the signal of the first signal line STV to the first node N1 under the signal control of the second clock signal line CK.
  • the second input sub-circuit 400 is electrically connected to the first potential signal line VGL, the second clock signal line CK, the second node N2, the first node N1 and the second potential signal line VGH.
  • the second input sub-circuit 400 is used to transmit the signal of the second potential signal line VGH or the first potential signal line VGL to the second node N2 under the signal control of the first node N1 and the second clock signal line CK.
  • the first sustaining sub-circuit 500 is electrically connected to the second node N2, the third node N3 and the second potential signal line VGH.
  • the first sustaining sub-circuit 500 is used to transmit the signal of the second potential signal line VGH to the third node N3 under the potential control of the second node N2.
  • the first output sub-circuit 300 is electrically connected to the first clock signal line CB, the third node N3, the second node N2 and the second potential signal line VGH.
  • the first output sub-circuit 300 is used to transmit the signal of the first clock signal line CB or the second potential signal line VGH to the first output terminal OUT1 under the potential control of the third node N3 and the second node N2.
  • the first reset sub-circuit 600 is electrically connected to the first reset control terminal 601K, the reset signal line PCX, and one end of the coupling sub-circuit 200.
  • the first reset sub-circuit 600 is used to transmit the potential of the reset signal line PCX to one end of the coupling sub-circuit 200 under the signal control of the first reset control terminal 601K.
  • the first sustaining sub-circuit 500 is configured to transmit the signal of the second potential signal line VGH to the third node N3 according to the potential of the second node N2;
  • the first reset sub-circuit 600 is configured to transmit the potential of the reset signal line PCX to one end of the coupling sub-circuit 200 under the signal control of the first reset control terminal 601K.
  • the first input sub-circuit 100 includes a first input transistor T1, the gate of the first input transistor T1 is electrically connected to the second clock signal line CK, the first electrode of the first input transistor T1 is electrically connected to the first signal line STV, and the second electrode of the first input transistor T1 is electrically connected to the first node N1.
  • the coupling sub-circuit 200 includes a coupling capacitor C2, the first plate C2a of the coupling capacitor C2 is electrically connected to the first node N1, and the second plate C2b of the coupling capacitor C2 is electrically connected to the third node N3.
  • the first output sub-circuit 300 includes a first output transistor T5 and a second output transistor T4.
  • the gate of the first output transistor T5 is electrically connected to the third node N3.
  • the first electrode of the first output transistor T5 is electrically connected to the first clock signal line CB.
  • the second electrode of the first output transistor T5 is electrically connected to the first output terminal OUT1.
  • the gate of the second output transistor T4 is electrically connected to the second node N2.
  • the second electrode of the second output transistor T4 is electrically connected to the second potential signal line VGH.
  • the first electrode of the second output transistor T4 is electrically connected to the first output terminal OUT1.
  • the electrode/end on the left or lower side of the thin-film transistor is defined as the first electrode of the thin-film transistor
  • the electrode/end on the right or upper side of the thin-film transistor is defined as the second electrode of the thin-film transistor.
  • the first electrode of the thin-film transistor is one of the source and drain
  • the second electrode of the thin-film transistor is the other of the source and drain.
  • the source and drain of the thin-film transistor can be interchanged.
  • the second input sub-circuit 400 includes a second input transistor T2 and a third input transistor T3.
  • the gate of the second input transistor T2 is electrically connected to the first node N1
  • the first electrode of the second input transistor T2 is electrically connected to the second potential signal line VGH
  • the second electrode of the second input transistor T2 is electrically connected to the second node N2.
  • the gate of the third input transistor T3 is electrically connected to the second clock signal line CK
  • the first electrode of the third input transistor T3 is electrically connected to the first potential signal line VGL
  • the second electrode of the third input transistor T3 is electrically connected to the second node N2.
  • the first sustaining sub-circuit 500 includes a first sustaining transistor T6, the gate of the first sustaining transistor T6 is electrically connected to the second node N2, the first electrode of the first sustaining transistor T6 is electrically connected to the third node N3, and the second electrode of the first sustaining transistor T6 is electrically connected to the second potential signal line VGH.
  • the first reset sub-circuit 600 includes a first reset transistor T7, the gate of the first reset transistor T7 is the first reset control terminal 601K, the first terminal of the first reset transistor T7 is electrically connected to the reset signal line PCX, and the second terminal of the first reset transistor T7 is electrically connected to the third node N3.
  • the first reset control terminal 601K is electrically connected to any one of the following: the first signal line STV, the first node N1 of the cascaded gate drive circuit unit 1000 in the gate drive circuit, the third node N3 of the cascaded gate drive circuit unit 1000 in the gate drive circuit, and the first plate of the cascaded coupling capacitor C2 in the gate drive circuit.
  • Figures 1, 3, and 4 illustrate that the first reset control terminal 601K is electrically connected to the first signal line STV;
  • Figure 6 illustrates that the first reset control terminal 601K is electrically connected to the first node N1 of the cascaded previous stage gate drive circuit unit 1000 in the gate drive circuit (the first node of the previous stage gate drive circuit unit is N1(N-1)).
  • the first reset control terminal 601K can also be electrically connected to one of the third node N3 of the cascaded previous stage gate drive circuit unit 1000 in the gate drive circuit, and the first plate of the cascaded previous stage coupling capacitor C2 in the gate drive circuit.
  • the number of signal lines can be reduced without adding new signal lines separately, thereby simplifying the structure of the gate drive circuit unit 1000.
  • the first input sub-circuit 100 further includes a fourth input transistor T8, the gate of which is electrically connected to the first potential signal line VGL, the first terminal of which is electrically connected to the second terminal of the first input transistor T1, and the second terminal of which is electrically connected to the first plate C2a of the coupling capacitor C2; or/and, the first output sub-circuit 300 further includes a first capacitor C1, the first plate C1a of which is electrically connected to the gate of the second output transistor T4, and the second plate C1b of which is electrically connected to the second terminal of the second output transistor T4.
  • the fourth input transistor T8 can protect the first input transistor T1 and the second input transistor T2. For instance, when the potential of the first plate C2a of the coupling capacitor C2 or the fourth node N4 is too low, the fourth input transistor T8 can prevent the low potential of the first plate C2a of the coupling capacitor C2 or the fourth node N4 from flowing directly into the first node N1, thereby preventing damage to the first input transistor T1 and the second input transistor T2.
  • the first signal line STV is a start signal line.
  • the signal of the reset signal line PCX is a high-level signal (shown by the dashed box in Figure 5), and the high-level signal of the reset signal line PCX is greater than the high-level signal of the first signal line STV.
  • the signal of the reset signal line PCX is a low-level signal.
  • the reset signal line PCX is given a high-voltage signal before the first signal line STV turns into a low-voltage signal when powered on.
  • the high potential of the reset signal line PCX is greater than the high potential of the first signal line STV, causing the first reset transistor T7 to turn on and the third node N3 to be set to a high-voltage signal, ensuring that the first output transistor T5 is turned off and preventing erroneous output.
  • the waveform of the reset signal line PCX is shown in Figure 5.
  • the high potential time of the reset signal line PCX is before the first signal line STV, which is electrically connected to the first-stage gate drive circuit unit 1000, outputs a low potential.
  • the gate drive circuit unit 1000 further includes at least one of a second reset sub-circuit 700 and a second sustaining sub-circuit 800.
  • the first reset sub-circuit 600 is electrically connected to one end of the coupling sub-circuit 200 that is electrically connected to the third node N3.
  • the second reset sub-circuit 700 is electrically connected to the second reset control terminal 602K, the reset signal line PCX, and one end of the coupling sub-circuit 200 that is electrically connected to the first node N1.
  • the second reset sub-circuit 700 is used to transmit the potential of the reset signal line PCX to the one end of the coupling sub-circuit 200 that is electrically connected to the first node N1 under the signal control of the second reset control terminal 602K.
  • the second sustaining sub-circuit 800 is electrically connected to the second node N2, the second potential signal line VGH, and one end of the coupling sub-circuit 200 that is electrically connected to the first node N1.
  • the second sustaining sub-circuit 800 is used to transmit the signal of the second potential signal line VGH to the end of the coupling sub-circuit 200 that is electrically connected to the first node N1 under the potential control of the second node N2.
  • the second reset sub-circuit 700 includes a second reset transistor T9, the gate of the second reset transistor T9 is the second reset control terminal 602K, the first terminal of the second reset transistor T9 is electrically connected to the reset signal line PCX, and the second terminal of the second reset transistor T9 is electrically connected to one end of the coupling sub-circuit 200 that is electrically connected to the first node N1.
  • the second sustaining sub-circuit 800 includes a second sustaining transistor T10, the gate of the second sustaining transistor T10 is electrically connected to the second node N2, the first electrode of the second sustaining transistor T10 is electrically connected to one end of the coupling sub-circuit 200 which is electrically connected to the first node N1, and the second electrode of the second sustaining transistor T10 is electrically connected to the second potential signal line VGH.
  • the gate of the second reset transistor T9 is the second reset control terminal 602K, which is electrically connected to any one of the following: the first signal line STV, the first node N1 of the cascaded gate drive circuit unit 1000 in the gate drive circuit, the third node N3 of the cascaded gate drive circuit unit 1000 in the gate drive circuit, and the first plate of the cascaded coupling capacitor C2 in the gate drive circuit.
  • the first terminal of the second reset transistor T9 is electrically connected to the reset signal line PCX, and the second terminal of the second reset transistor T9 is electrically connected to the first plate C2a of the coupling capacitor C2.
  • the gate of the second sustaining transistor T10 is electrically connected to the second node N2
  • the first electrode of the second sustaining transistor T10 is electrically connected to the first plate C2a of the coupling capacitor C2
  • the second electrode of the second sustaining transistor T10 is electrically connected to the second potential signal line VGH.
  • the second reset transistor T9 of the second reset sub-circuit 700 resets the potential of the fourth node N4, thereby improving the stability of the potential of the fourth node N4.
  • the second sustaining body tube T10 of the second sustaining sub-circuit 800 maintains the stability of the potential of the fourth node N4.
  • the gate drive circuit unit 1000 further includes a second output sub-circuit 900, which is configured to transmit a signal from the fifth input terminal 105 or the sixth input terminal 106 to the second output terminal OUT2 based on the voltage applied to the second node N2 and the third node N3.
  • a second output sub-circuit 900 which is configured to transmit a signal from the fifth input terminal 105 or the sixth input terminal 106 to the second output terminal OUT2 based on the voltage applied to the second node N2 and the third node N3.
  • one of the first output terminal OUT1 and the second output terminal OUT2 can output a gate drive signal, and the other of the first output terminal OUT1 and the second output terminal OUT2 can output a stage transmission signal.
  • the second output sub-circuit 900 includes a third output transistor T12 and a fourth output transistor T11.
  • the gate of the third output transistor T12 is electrically connected to the third node N3, the first electrode of the third output transistor T12 is electrically connected to the first clock signal line CB, and the second electrode of the third output transistor T12 is electrically connected to the second output terminal OUT2.
  • the gate of the fourth output transistor T11 is electrically connected to the second node N2, the second electrode of the fourth output transistor T11 is electrically connected to the second potential signal line VGH, and the first electrode of the fourth output transistor T11 is electrically connected to the second output terminal OUT2.
  • first plate C1a of the first capacitor C1 is electrically connected to the gate of the second output transistor T4, and the second plate C1b of the first capacitor C1 is electrically connected to the second terminal of the second output transistor T4.
  • first plate C1a of the first capacitor C1 may also be electrically connected to the gate of the fourth output transistor T11, and the second plate C1b of the first capacitor C1 may be electrically connected to the second terminal of the fourth output transistor T11.
  • the first capacitor C1 may be electrically connected at corresponding positions on the gates of the second output transistor T4 and the fourth output transistor T11.
  • the fifth input terminal 105 receives the signal from the first clock signal line CB, and the sixth input terminal 106 receives the signal from the second potential signal line VGH.
  • the first clock signal line CB received by the fifth input terminal 105 is different from the first clock signal line CB received by the third input terminal 103.
  • the high potential in the first clock signal line CB received by the fifth input terminal 105 is greater than the high potential in the first clock signal line CB received by the third input terminal 103.
  • the low potential in the first clock signal line CB received by the fifth input terminal 105 is less than the low potential in the first clock signal line CB received by the third input terminal 103.
  • the second potential signal line VGH received by the sixth input terminal 106 is different from the second potential signal line VGH received by the fourth input terminal 104.
  • the potential in the second potential signal line VGH received by the sixth input terminal 106 is greater than the potential in the second potential signal line VGH received by the fourth input terminal 104.
  • the first clock signal line CB received by the first terminal of the third output transistor T12 is different from the first clock signal line CB received by the first terminal of the first output transistor T5; the high potential in the first clock signal line CB received by the first terminal of the third output transistor T12 is greater than the high potential in the first clock signal line CB received by the first terminal of the first output transistor T5; the low potential in the first clock signal line CB received by the first terminal of the third output transistor T12 is less than the low potential in the first clock signal line CB received by the first terminal of the first output transistor T5; the second potential signal line VGH received by the second terminal of the fourth output transistor T11 is different from the second potential signal line VGH received by the second terminal of the second output transistor T4; the potential in the second potential signal line VGH received by the second terminal of the fourth output transistor T11 is greater than the potential in the second potential signal line VGH received by the second terminal of the second output transistor T4.
  • the first terminal of the third output transistor T12 is electrically connected to the second output clock signal line CB2
  • the second terminal of the fourth output transistor T11 is electrically connected to the second output potential signal line VGH2
  • the first terminal of the first output transistor T5 is electrically connected to the first output clock signal line CB1
  • the second terminal of the second output transistor T4 is electrically connected to the first output potential signal line VGH1.
  • the first output terminal OUT1 can be configured to output a stage transmission signal
  • the second output terminal OUT2 can output a gate drive signal
  • the signal in the first signal line STV is a start signal
  • the signal in the first potential signal line VGL is a low potential
  • the signal in the second potential signal line VGH is a high potential
  • the thin-film transistors in the gate drive circuit unit 1000 are all P-type.
  • the signal in the first signal line STV is a start signal
  • the signal in the first potential signal line is a high potential
  • the signal in the second potential signal line is a low potential
  • the thin-film transistors in the gate drive circuit unit 1000 are all N-type, but not limited thereto.
  • the signal in the first signal line STV is the start signal
  • the signal in the first potential signal line VGL is at a low potential
  • the signal in the second potential signal line VGH is at a high potential.
  • the thin film transistors in the gate drive circuit unit 1000 are all P-type. However, in other embodiments or during operation, the signal in the first potential signal line VGL, the signal in the second potential signal line VGH, and the type of thin film transistor may not be limited to these. Please refer to Figures 1 and 2.
  • the second clock signal line CK is at a low voltage
  • the first input sub-circuit 100 is working, the first input transistor T1 is turned on, and the low voltage signal of the first signal line STV is written to the first node N1.
  • the fourth input transistor T8 is normally open, the low voltage signal is written to the fourth node N4. Due to the capacitive coupling effect of the coupling capacitor C2, the voltage of the third node N3 is pulled down. Since the signal of the first clock signal line CB is at a high voltage at this time, the first output sub-circuit 300 is working, so the first output transistor T5 is turned on, and the first output terminal OUT1 outputs a high voltage signal.
  • the first node N1 is at a low voltage
  • the second input sub-circuit 400 is working
  • the second input transistor T2 is turned on
  • the signal of the second potential signal line VGH is written to the second node N2
  • the second output transistor T4 is turned off.
  • the first clock signal line CB switches to a low voltage signal. Due to the inter-electrode capacitance of the thin-film transistor (the first output transistor T5), when the signal of the first clock signal line CB changes from a high potential to a low potential, the third node N3 is pulled low, ensuring that the first clock signal line CB outputs a low voltage signal normally. At this time, due to the effect of the first capacitor C1, the second node N2 maintains the high voltage signal of the previous moment, and the second output transistor T4 is turned off. The first output terminal OUT1 outputs a low voltage signal.
  • the high-voltage signal of the first signal line STV is written to the first node N1 and the fourth node N4. Due to the capacitive coupling effect of the coupling capacitor C2, the potential of the third node N3 is pulled high, and the first output transistor T5 is turned off.
  • the second input sub-circuit 400 is working, the third input transistor T3 is turning on, the second input transistor T2 is turning off, the signal of the first potential signal line VGL is written to the second node N2, the second output transistor T4 is turning on, and the first output terminal OUT1 outputs a high-potential signal (the signal of the second potential signal line VGH).
  • the first sustaining sub-circuit 500 is working, the first sustaining transistor T6 is turning on, and the signal of the second potential signal line VGH is written to the third node N3, ensuring that the first output transistor T5 is turned off.
  • the first reset sub-circuit 600 when the signal in the first signal line STV is low voltage, the first reset sub-circuit 600 operates, the first reset transistor T7 turns on, the PCX signal is written to the third node N3 to reset the third node N3, and in order to ensure that the third node N3 has a sufficiently low voltage at the next moment, so as to ensure that the low voltage signal of the first clock signal line CB can be output normally and reduce the output waveform loss due to the pull-down transistor Vth threshold (threshold voltage) problem, the signal of the reset signal line PCX is a low voltage signal.
  • the low potential of the reset signal line PCX can be set to be lower than the low potential in the first potential signal line VGL (when the signal in the first potential signal line VGL is at a low potential).
  • This disclosure also provides a gate driving circuit, which includes at least one cascaded circuit, each of the cascaded circuits including a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit unit is the gate driving circuit unit 1000 described in any one of the above, or the gate driving circuit unit is the gate driving circuit unit 1000 in combination of any of the above.
  • Figure 9 is a layout schematic diagram of a gate driving circuit unit 1000 according to some embodiments of the present disclosure
  • Figure 10 is a layout schematic diagram of the semiconductor layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure
  • Figure 11 is a layout schematic diagram of the gate metal layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure
  • Figure 12 is a layout schematic diagram of the capacitor metal layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure
  • Figure 13 is a layout schematic diagram of the second insulating layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure
  • Figure 14 is a layout schematic diagram of the first metal layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure
  • Figure 15 is a layout schematic diagram of the third insulating layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure
  • Figure 16 is a layout schematic diagram of the second metal layer of a gate driving circuit unit 1000 according to some embodiments of the present disclosure.
  • This disclosure also provides a method for manufacturing a display substrate, the method comprising: providing a substrate; and manufacturing at least one cascaded circuit on the substrate, each cascaded circuit comprising a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit unit is any one of the gate driving circuit units 1000 described above, or the gate driving circuit unit 1000 is a combination of any of the above-described gate driving circuit units 1000.
  • the method for manufacturing a display substrate includes the following steps S10 to S19.
  • Step S10 Provide a substrate.
  • the substrate may be glass or a flexible substrate, and the material of the substrate may be polyimide, but is not limited thereto.
  • Step S11 forms a semiconductor layer PO on one side of the substrate.
  • the semiconductor layer PO includes the active portion P1 of the first input transistor T1, the active portion P8 of the fourth input transistor T8, the active portion P2 of the second input transistor T2, the active portion P3 of the third input transistor T3, the active portion P6 of the first sustaining transistor T6, the active portion P7 of the first reset transistor T7, the active portion P5 of the first output transistor T5, and the active portion P4 of the second output transistor T4.
  • Step S12 A gate insulating layer GI (not shown in the figure) is formed on the side of the semiconductor layer PO away from the substrate.
  • Step S13 forms a gate metal layer Ge1 on the side of the gate insulating layer GI away from the substrate.
  • the gate metal layer Ge1 includes the gate G1 of the first input transistor T1, the gate G8 of the fourth input transistor T8, the gate G2 of the second input transistor T2, the gate G3 of the third input transistor T3, the gate G6 of the first sustaining transistor T6, the gate G7 of the first reset transistor T7, the gate G5 of the first output transistor T5, and the gate G4 of the second output transistor T4.
  • the gate metal layer Ge1 further includes the second plate C2b of the coupling capacitor and the second plate C1b of the first capacitor.
  • Step S14 A first insulating layer (not shown) is formed on the side of the gate metal layer Ge1 away from the gate metal layer Ge1.
  • Step S15 forms a capacitor metal layer Ge2 on the side of the gate insulating layer GI away from the first insulating layer.
  • the capacitor metal layer Ge2 includes the first plate C2a of the coupling capacitor and the first plate C1a of the first capacitor.
  • Step S16 forms a second insulating layer ILD on the side of the capacitor metal layer Ge2 away from the substrate.
  • Figure 13 illustrates multiple vias in the second insulating layer ILD.
  • Step S17 forms a first metal layer SD1 on the side of the second insulating layer ILD away from the substrate.
  • the first metal layer SD1 includes the first terminal S1 and the second terminal D1 of the first input transistor T1, the first terminal S8 and the second terminal D8 of the fourth input transistor T8, the first terminal S2 and the second terminal D2 of the second input transistor T2, the first terminal S3 and the second terminal D2 of the third input transistor T3, the first terminal S6 and the second terminal D6 of the first sustaining transistor T6, the first terminal S7 and the second terminal D7 of the first reset transistor T7, the first terminal S5 and the second terminal D5 of the first output transistor T5, and the first terminal S4 and the second terminal D4 of the second output transistor T4.
  • the first metal layer SD1 further includes a first sub-clock line CB-1 of the first clock signal line CB and a third sub-clock line CK-1 of the second clock signal line CK.
  • Step S18 forms a third insulating layer PLN on the side of the first metal layer SD1 away from the substrate.
  • the third insulating layer PLN can be a planar layer.
  • Figure 15 illustrates multiple vias in the third insulating layer PLN.
  • Step S19 forms a second metal layer SD2 on the side of the third insulating layer PLN away from the substrate.
  • the second metal layer SD2 includes the first sub-potential line VGH-1, the first potential signal line VGL, the reset signal line PCX, the fourth sub-clock line CK-2, the second sub-clock line CB-2, and the second sub-potential line VGH-2.
  • This disclosure also provides a display substrate 2000, which includes the gate driving circuit unit 1000 described in any one of the above descriptions, or the display substrate 2000 includes the gate driving circuit unit 1000 in combination of any of the above descriptions.
  • the display substrate 2000 may be manufactured using any of the above-described methods for manufacturing a display substrate 2000.
  • the display substrate 2000 may include at least one cascaded circuit, each cascaded circuit including a plurality of gate driving circuit units cascaded in sequence, wherein the gate driving circuit unit is any one of the gate driving circuit units 1000 described above, or the gate driving circuit unit is any combination of the gate driving circuit units 1000 described above.
  • the coupling sub-circuit 200 includes a coupling capacitor C2; the first output sub-circuit 300 includes a first output transistor T5 and a second output transistor T4; the display substrate 2000 includes the substrate and a gate metal layer Ge1 disposed on one side of the substrate, the gate metal layer Ge1 includes the second plate C2b of the coupling capacitor C2 and the gate of the first output transistor T5, and the second plate C2b of the coupling capacitor C2 and the gate of the first output transistor T5 are directly connected.
  • the gate metal layer Ge1 includes the second plate C2b of the coupling capacitor C2 and the gate of the first output transistor T5.
  • the second plate C2b of the coupling capacitor C2 and the gate of the first output transistor T5 are directly connected, which can reduce wiring and reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, which is helpful for narrow bezel design.
  • the first output sub-circuit 300 further includes a first capacitor C1, and the coupling capacitor C2 and the first capacitor C1 are arranged along a first direction Y;
  • the gate metal layer Ge1 further includes a second plate C1b of the first capacitor C1 and the gate of the second output transistor T4, and the second plate C1b of the first capacitor C1 and the gate of the second output transistor T4 are directly connected; in the second direction X, the first output transistor T5 and the second output transistor T4 are located on the same side of the coupling capacitor C2 and the first capacitor C1, and the first direction Y intersects the second direction X.
  • Figure 9 illustrates that the first direction Y is perpendicular to the second direction X, but is not limited thereto.
  • the display panel may include a display area and a border area, the display area and the border area having a dividing line, the first direction Y may be parallel to the extension direction of the dividing line between the display area and the border area, and the second direction X may be perpendicular to the extension direction of the dividing line between the display area and the border area, but is not limited thereto.
  • the coupling capacitor C2 and the first capacitor C1 are arranged along the first direction Y.
  • the first output transistor T5 and the second output transistor T4 are located on the same side of the coupling capacitor C2 and the first capacitor C1. This can reduce the length of the gate drive circuit unit 1000 in the first direction Y, which helps to provide a larger number of the gate drive circuit units 1000 in the first direction Y in a high-resolution display panel.
  • the second input sub-circuit 400 includes a second input transistor T2 and a third input transistor T3;
  • the display substrate 2000 further includes a first sustaining sub-circuit 500 and a first reset sub-circuit 600, the first sustaining sub-circuit 500 including a first sustaining transistor T6;
  • the first reset sub-circuit 600 including a first reset transistor T7;
  • the display substrate 2000 includes a semiconductor layer PO located between the substrate and the gate metal layer Ge1, the semiconductor layer PO including a continuous first semiconductor pattern PO1, and the active portion P2 of the second input transistor T2, the active portion P6 of the first sustaining transistor T6, and the active portion P7 of the first reset transistor T7 are formed by the first semiconductor pattern PO1.
  • the active portion P2 of the second input transistor T2, the active portion P6 of the first sustaining transistor T6, and the active portion P7 of the first reset transistor T7 are all formed by the first semiconductor pattern PO1.
  • the first semiconductor pattern PO1 is a continuous structure, which can reduce the number of vias and electrodes connecting the second input transistor T2, the first sustaining transistor T6, and the first reset transistor T7, and can reduce the number of wire changes. This is beneficial for reducing the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, and helps with narrow bezel design.
  • the active pattern/active portion P1 of the first input transistor T1 is configured as a U-shaped structure, and the active pattern/active portion P1 of the first input transistor T1 includes a first input sub-active portion P1-1 and a second sub-active portion P1-2, so that the first input transistor T1 is formed as a dual-gate structure.
  • the active pattern/active portion P1 of the first input transistor T1 is configured as a U-shaped structure
  • the first input transistor T1 is formed as a dual-gate structure
  • the gate G1 of the first input transistor T1 includes a first input sub-gate G11 and a second input sub-gate G12.
  • the first input sub-gate G11 of the first input transistor T1, the second input sub-gate G12 of the first input transistor T1, and the gate G3 of the third input transistor T3 are a continuous structure.
  • the active pattern/active part P1 of the first input transistor T1 is set to a U-shaped structure, so that the first input transistor T1 forms a dual-gate structure, and the first input transistor T1 occupies a smaller layout space while better realizing the connection between the gate G1 of the first input transistor T1 and the second clock signal line (third sub-clock line CK-1) and the gate G3 of the third input transistor T3.
  • the active portion P1 of the first input transistor T1, the active portion P8 of the fourth input transistor T8, and the active portion P3 of the third input transistor T3 included in the semiconductor layer PO are spaced apart from each other, and the active portions of these thin-film transistors are spaced apart from the active portions of other thin-film transistors in Figure 1 or Figure 9.
  • the first semiconductor pattern PO1 includes a first sub-semiconductor pattern PO1-1, a second sub-semiconductor pattern PO1-2, and a third sub-semiconductor pattern PO1-3.
  • the second sub-semiconductor pattern PO1-2 is connected between the first sub-semiconductor pattern PO1-1 and the third sub-semiconductor pattern PO1-3.
  • the extension direction of the first sub-semiconductor pattern PO1-1 is parallel to the extension direction of the third sub-semiconductor pattern PO1-3, and the extension direction of the second sub-semiconductor pattern PO1-2 is non-linear.
  • the first sub-semiconductor pattern PO1-1 includes the active portion P2 of the second input transistor T2
  • the second sub-semiconductor pattern PO1-2 includes the active portion P6 of the first holding transistor T6
  • the third sub-semiconductor pattern PO1-3 includes the active portion P7 of the first reset transistor T7.
  • the extension direction of the first sub-semiconductor pattern PO1-1 and the extension direction of the third sub-semiconductor pattern PO1-3 are both parallel to the first direction Y.
  • the extension direction of the first sub-semiconductor pattern PO1-1 and the extension direction of the third sub-semiconductor pattern PO1-3 may also be other directions besides the first direction Y.
  • the extension direction of the first sub-semiconductor pattern PO1-1 is parallel to the extension direction of the third sub-semiconductor pattern PO1-3, and the extension direction of the second sub-semiconductor pattern PO1-2 is non-linear. This can reduce the distance between the first sub-semiconductor pattern PO1-1 and the third sub-semiconductor pattern PO1-3, thereby helping to reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, which is conducive to narrow bezel design.
  • the channel extension direction of the active portion P2 of the second input transistor T2 the channel extension direction of the active portion P6 of the first sustaining transistor T6, and the channel extension direction of the active portion P7 of the first reset transistor T7 are parallel to each other.
  • the channel extension direction of the active portion P2 of the second input transistor T2 the channel extension direction of the active portion P6 of the first sustaining transistor T6, and the channel extension direction of the active portion P7 of the first reset transistor T7 are all parallel to the first direction Y.
  • the channel extension direction of the active portion P2 of the second input transistor T2 may also be other directions besides the first direction Y.
  • the channel extension direction of the active portion P2 of the second input transistor T2, the channel extension direction of the active portion P6 of the first sustaining transistor T6, and the channel extension direction of the active portion P7 of the first reset transistor T7 are parallel to each other. This helps to control the uniformity and carrier migration performance of the channels of the active portion P2 of the second input transistor T2, the active portion P6 of the first sustaining transistor T6, and the active portion P7 of the first reset transistor T7 during the manufacturing process of the display substrate 2000 or the display panel.
  • the first input sub-circuit 100 includes a first input transistor T1; the first input sub-circuit 100 also includes a fourth input transistor T8; in the second direction X, the first input transistor T1, the fourth input transistor T8, the second input transistor T2, the third input transistor T3, the first sustaining transistor T6, and the first reset transistor T7 are all located on one side of the coupling capacitor C2 and the first capacitor C1, and the first output transistor T5 and the second output transistor T4 are both located on the other side of the coupling capacitor C2 and the first capacitor C1.
  • the first input transistor T1, the fourth input transistor T8, the second input transistor T2, the third input transistor T3, the first holding transistor T6, and the first reset transistor T7 are located on both sides of the coupling capacitor C2 and the first capacitor C1 in the second direction X, along with the first output transistor T5 and the second output transistor T4.
  • the coupling capacitor C2 and the first capacitor C1 are arranged along the first direction Y, which helps to reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel, and is conducive to narrow bezel design.
  • the display substrate 2000 includes a first clock signal line CB, a second clock signal line CK, a first potential signal line VGL, a second potential signal line VGH and a reset signal line PCX;
  • the first clock signal line CB includes a first sub-clock line CB-1 and a second sub-clock line CB-2, and the signals in the first sub-clock line CB-1 and the second sub-clock line CB-2 are the same;
  • the second clock signal line CK includes a third sub-clock line CK-1 and a fourth sub-clock line CK-2, and the signals in the third sub-clock line CK-1 and the fourth sub-clock line CK-2 are the same;
  • the second potential signal line VGH includes a first sub-potential line VGH-1 and a second sub-potential line VGH-2, and the signals in the first sub-potential line VGH-1 and the second sub-potential line VGH-2 are the same;
  • the first sub-clock line CB-1, the third sub-clock line CK-1, the first sub-potential line VGH-1, the first potential signal line VGL, the reset signal line PCX, the fourth sub-clock line CK-2, the second sub-clock line CB-2, and the second sub-potential line VGH-2 are arranged sequentially along the second direction X;
  • the orthographic projection of the coupling capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the reset signal line PCX on the substrate, the orthographic projection of the fourth sub-clock line CK-2 on the substrate, and the orthographic projection of the second sub-clock line CB-2 on the substrate.
  • the first clock signal line CB includes a first sub-clock line CB-1 and a second sub-clock line CB-2, with the same signal in the first sub-clock line CB-1 and the second sub-clock line CB-2;
  • the second clock signal line CK includes a third sub-clock line CK-1 and a fourth sub-clock line CK-2, with the same signal in the third sub-clock line CK-1 and the fourth sub-clock line CK-2;
  • the second potential signal line VGH includes a first sub-potential line VGH-1 and a second sub-potential line VGH-2, with the same signal in the first sub-potential line VGH-1 and the second sub-potential line VGH-2.
  • some sub-routes are directly connected to the structure electrically connected to them, and the orthographic projection of some sub-routes on the substrate at least partially overlaps with the orthographic projection of the structure electrically connected to them on the substrate, so that it is not necessary to set long connection electrodes, and it is also beneficial to reduce the area occupied by the gate drive circuit unit 1000 or the gate drive circuit in the layout or display panel.
  • the inventors minimized the layout area of the gate drive circuit unit 1000 while considering its electrical performance.
  • the first input transistor T1, the fourth input transistor T8, the second input transistor T2, the third input transistor T3, the first sustaining transistor T6, the first reset transistor T7, the first output transistor T5, and the second output transistor T4 were arranged as shown in Figure 9.
  • the first sub-clock line CB-1, the third sub-clock line CK-1, the first sub-potential line VGH-1, the first potential signal line VGL, the reset signal line PCX, the fourth sub-clock line CK-2, the second sub-clock line CB-2, and the second sub-potential line VGH-2 were arranged sequentially along the second direction X.
  • the display substrate includes a first clock signal bus connected between a pad area (the pad area is electrically connected to a driver chip or circuit board, etc.) and a setting area of the gate drive circuit unit.
  • the first clock signal bus connects (leads out) a first sub-clock line CB-1 and a second sub-clock line CB-2, and the first clock signal bus provides the same electrical signal in the first sub-clock line CB-1 and the second sub-clock line CB-2.
  • the display substrate includes a second clock signal bus connected between a pad area (which is electrically connected to a driver chip or circuit board, etc.) and the setting area of the gate drive circuit unit.
  • the second clock signal bus connects (leads out) the third sub-clock line CK-1 and the fourth sub-clock line CK-2, and the second clock signal bus provides the same electrical signal in the third sub-clock line CK-1 and the fourth sub-clock line CK-2.
  • the display substrate includes a second potential signal bus connected between a pad area (which is electrically connected to a driver chip or circuit board, etc.) and the setting area of the gate drive circuit unit.
  • the second potential signal bus connects (leads out) the first sub-potential line VGH-1 and the second sub-potential line VGH-2, and the second potential signal bus provides the same electrical signal in the first sub-potential line VGH-1 and the second sub-potential line VGH-2.
  • the coupling sub-circuit 200 includes a coupling capacitor C2, the first plate C2a of which is electrically connected to the first node N1, and the second plate C2b of which is electrically connected to the third node N3.
  • the first output sub-circuit 300 includes a first output transistor T5 and a second output transistor T4.
  • the gate of the first output transistor T5 is electrically connected to the third node N3, the first electrode of the first output transistor T5 is electrically connected to the first clock signal line CB (the second sub-clock line CB-2), the second electrode of the first output transistor T5 is electrically connected to the first output terminal OUT1, the gate of the second output transistor T4 is electrically connected to the second node N2, the second electrode of the second output transistor T4 is electrically connected to the second potential signal line VGH (the second sub-potential line VGH-2), and the first electrode of the second output transistor T4 is electrically connected to the first output terminal OUT1.
  • the second input sub-circuit 400 includes a second input transistor T2 and a third input transistor T3.
  • the gate of the second input transistor T2 is electrically connected to the first node N1
  • the first electrode of the second input transistor T2 is electrically connected to the second potential signal line VGH (the first sub-potential line VGH-1)
  • the second electrode of the second input transistor T2 is electrically connected to the second node N2.
  • the gate of the third input transistor T3 is electrically connected to the second clock signal line CK (the third sub-clock line CK-1)
  • the first electrode of the third input transistor T3 is electrically connected to the first potential signal line VGL
  • the second electrode of the third input transistor T3 is electrically connected to the second node N2.
  • the first sustaining sub-circuit 500 includes a first sustaining transistor T6, the gate of the first sustaining transistor T6 is electrically connected to the second node N2, the first electrode of the first sustaining transistor T6 is electrically connected to the third node N3, and the second electrode of the first sustaining transistor T6 is electrically connected to the second potential signal line VGH (the first sub-potential line VGH-1).
  • the first reset sub-circuit 600 includes a first reset transistor T7, the gate of the first reset transistor T7 is the first reset control terminal 601K, the first electrode of the first reset transistor T7 is electrically connected to the reset signal line PCX, and the second electrode of the first reset transistor T7 is electrically connected to the third node N3.
  • the first input sub-circuit 100 further includes a fourth input transistor T8, the gate of which is electrically connected to the first potential signal line VGL, the first terminal of which is electrically connected to the second terminal of the first input transistor T1, and the second terminal of which is electrically connected to the first plate C2a of the coupling capacitor C2; or/and, the first output sub-circuit 300 further includes a first capacitor C1, the first plate C1a of which is electrically connected to the gate of the second output transistor T4, and the second plate C1b of which is electrically connected to the second terminal of the second output transistor T4.
  • the orthographic projection of the first reset transistor T7 on the substrate at least partially overlaps with the orthographic projection of the reset signal line PCX on the substrate;
  • the orthographic projection of the first capacitor C1 on the substrate, the orthographic projection of the fourth sub-clock line CK-2 on the substrate, and the orthographic projection of the second sub-clock line CB-2 on the substrate all at least partially overlap;
  • the first reset transistor T7 and the first capacitor C1 are located on the same side of the coupling capacitor C2;
  • the orthogonal projection of the second sub-potential line (VGH-2) onto the substrate is located on the side of the first output transistor T5 and the second output transistor T4 away from the coupling capacitor C2.
  • the orthographic projection of the first capacitor C1 on the substrate at least partially overlaps with the orthographic projections of the fourth sub-clock line CK-2 and the second sub-clock line CB-2 on the substrate; the orthographic projection of the first reset transistor T7 on the substrate at least partially overlaps with the orthographic projection of the reset signal line PCX on the substrate.
  • This disclosure also provides a display device, which includes a gate driving circuit, the gate driving circuit including the gate driving circuit unit 1000 described in any one of the above, or the gate driving circuit including the gate driving circuit unit 1000 in combination of any of the above.
  • This disclosure also provides a display device, a display substrate 2000, the display substrate 2000 including a gate driving circuit, the gate driving circuit including any one of the gate driving circuit units 1000 described above, or the gate driving circuit including any combination of the gate driving circuit units 1000 described above.
  • the display device may be a smartphone, laptop, television, tablet computer or other display, and some embodiments of this disclosure are not specifically limited.
  • a first input sub-circuit is configured to control the voltage of a first node based on a signal from a first input terminal; a second input sub-circuit is configured to control the voltage of a second node based on a signal from a second input terminal; a coupling sub-circuit is at least configured to control the voltage of a third node based on the voltage of the first node; and a first output sub-circuit is configured to transmit a signal from a third input terminal or a signal from a fourth input terminal to a first output terminal based on the voltages applied to the second and third nodes.
  • the voltage of the third node can be controlled according to the voltage of the first node, allowing the electrical signal of the third node to better match display or driving requirements. For example, the high potential of the third node can be made higher, or the low potential of the third node can be made lower.
  • the signal at the third input terminal can be better transmitted to the first output terminal.
  • the signal at the third input terminal can be better isolated from the first output terminal, thereby improving the stability of the output signal of the gate drive circuit unit.
  • the gate driving circuit unit includes the first input sub-circuit, the second input sub-circuit, the coupling sub-circuit, and the first output sub-circuit.
  • the gate driving circuit unit has a simple structure, and the number of thin-film transistors and capacitors included in the gate driving circuit unit is small. The area occupied by the gate driving circuit unit in the layout or display panel is small. That is, the gate driving circuit unit has the effect of simple structure, which is beneficial to the narrow bezel of the display panel.
  • the provided gate drive circuit unit has the advantages of simple structure and stable output of electrical signals that meet display requirements.

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Abstract

本公开公开一种栅极驱动电路单元、栅极驱动电路、显示基板的制造方法、显示基板及显示装置，包括：第一输入子电路(100)，被构造为根据第一输入端(101)的信号来控制第一节点(N1)的电压；第二输入子电路(400)，被构造为根据第二输入端(102)的信号来控制第二节点(N2)的电压；耦合子电路(200)，至少被构造为根据第一节点(N1)的电压来控制第三节点(N3)的电压；第一输出子电路(300)，被构造为根据施加到第二节点(N2)和第三节点(N3)的电压将第三输入端(103)的信号或第四输入端(104)的信号传输至第一输出端(OUT1)。

Description

栅极驱动电路单元及其电路、显示基板及其制造方法、显示装置
相关申请的交叉引用
本公开要求于2024年5月30日提交的申请号为2024106924810的中国专利申请的优先权，其全部内容通过引用合并于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种栅极驱动电路单元、栅极驱动电路、显示基板的制造方法、显示基板及显示装置。
背景技术
现有技术中，为了实现低成本和窄边框的目的，大部分都采用了GOA(Gate driver On Array，阵列基板行驱动)技术，栅极驱动电路单元即GOA单元。
然而，相关技术中栅极驱动电路单元存在一些问题，例如不能满足结构简化或稳定输出满足显示需求电信号的问题。
发明内容
本公开一些实施例提供了一种栅极驱动电路单元、栅极驱动电路、显示基板的制造方法、显示基板及显示装置，能够改善相关技术中栅极驱动电路单元存在的问题。
在本公开的第一方面，提供了一种栅极驱动电路单元，包括：第一输入子电路，被构造为根据第一输入端的信号来控制第一节点的电压；第二输入子电路，被构造为根据第二输入端的信号来控制第二节点的电压；耦合子电路，至少被构造为根据所述第一节点的电压来控制第三节点的电压；第一输出子电路，被构造为根据施加到所述第二节点和所述第三节点的电压将第三输入端的信号或第四输入端的信号传输至第一输出端。
在一些实施方式中，满足如下条件中至少之一：所述第一输入端接收第一信号线的信号；所述第二输入端接收第一电位信号线的信号；所述第三输入端接收第一时钟信号线的信号，所述第四输入端接收第二电位信号线的信号。
在一些实施方式中，栅极驱动电路单元还包括第一维持子电路和第一复位子电路；所述第一输入子电路电连接所述第一信号线、第二时钟信号线和所述第一节点，所述第一输入子电路用于在所述第二时钟信号线的信号控制下，将所述第一信号线的信号输入至所述第一节点；所述第二输入子电路电连接所述第一电位信号线、所述第二时钟信号线、所述第二节点、所述第一节点和所述第二电位信号线，所述第二输入子电路用于在所述第一节点和所述第二时钟信号线的信号控制下，将所述第二电位信号线或所述第一电位信号线的信号传输至所述第二节点；所述第一维持子电路电连接所述第二节点、所述第三节点和所述第二电位信号线，所述第一维持子电路用于在所述第二节点的电位控制下将所述第二电位信号线的信号传输至所述第三节点；所述第一输出子电路电连接所述第一时钟信号线、所述第三节点、所述第二节点和所述第二电位信号线，所述第一输出子电路用于在所述第三节点和所述第二节点的电位控制下，将所述第一时钟信号线或所述第二电位信号线的信号传输至所述第一输出端；所述第一复位子电路电连接第一复位控制端、复位信号线和所述耦合子电路的一端，所述第一复位子电路用于在所述第一复位控制端的信号控制下，将所述复位信号线的电位传输至所述耦合子电路的一端。
在一些实施方式中，所述第一输入子电路包括第一输入晶体管，所述第一输入晶体管的栅极电连接所述第二时钟信号线，所述第一输入晶体管的第一极电连接所述第一信号线，所述第一输入晶体管的第二极电连接所述第一节点；所述耦合子电路包括耦合电容，所述耦合电容的第一极板电连接所述第一节点，所述耦合电容的第二极板电连接所述第三节点；所述第一输出子电路包括第一输出晶体管和第二输出晶体管，所述第一输出晶体管的栅极电连接所述第三节点，所述第一输出晶体管的第一极电连接所述第一时钟信号线，所述第一输出晶体管的第二极电连接所述第一输出端，所述第二输出晶体管的栅极电连接所述第二节点，所述第二输出晶体管的第二极电连接所述第二电位信号线，所述第二输出晶体管的第一极电连接所述第一输出端。
在一些实施方式中，所述第二输入子电路包括第二输入晶体管和第三输入晶体管，所述第二输入晶体管的栅极电连接所述第一节点，所述第二输入晶体管的第一极电连接所述第二电位信号线，所述第二输入晶体管的第二极电连接所述第二节点，所述第三输入晶体管的栅极电连接所述第二时钟信号线，所述第三输入晶体管的第一极电连接所述第一电位信号线，所述第三输入晶体管的第二极电连接所述第二节点；所述第一维持子电路包括第一维持晶体管，所述第一维持晶体管的栅极电连接所述第二节点，所述第一维持晶体管的第一极电连接所述第三节点，所述第一维持晶体管的第二极电连接所述第二电位信号线。
在一些实施方式中，所述第一复位子电路包括第一复位晶体管，所述第一复位晶体管的栅极为所述第一复位控制端，所述第一复位晶体管的第一极电连接所述复位信号线，所述第一复位晶体管的第二极电连接所述第三节点。
在一些实施方式中，所述第一复位控制端电连接所述第一信号线、栅极驱动电路中级联的上一级所述栅极驱动电路单元的所述第一节点、所述栅极驱动电路中级联的上一级所述栅极驱动电路单元的所述第三节点、以及所述栅极驱动电路中级联的上一级所述耦合电容的第一极板中任一者。
在一些实施方式中，所述第一输入子电路还包括第四输入晶体管，所述第四输入晶体管的栅极电连接所述第一电位信号线，所述第四输入晶体管的第一极电连接所述第一输入晶体管的第二极，所述第四输入晶体管的第二极电连接所述耦合电容的第一极板；或/和所述第一输出子电路还包括第一电容，所述第一电容的第一极板电连接所述第二输出晶体管的栅极，所述第一电容的第二极板电连接所述第二输出晶体管的第二极。
在一些实施方式中，所述第一信号线为起始信号线，在所述第一信号线输出第一个低电位的信号前，所述复位信号线的信号为高电位信号，且所述复位信号线的高电位大于所述第一信号线的高电位；在所述第一信号线输出第一个低电位的信号开始，所述复位信号线的信号为低电位信号。
在一些实施方式中，所述栅极驱动电路单元还包括第二复位子电路和第二维持子电路中至少一者；所述第一复位子电路电连接所述耦合子电路与所述第三节点电连接的一端，所述第二复位子电路电连接第二复位控制端、所述复位信号线、以及所述耦合子电路与所述第一节点电连接的一端，所述第二复位子电路用于在所述第二复位控制端的信号控制下，将所述复位信号线的电位传输至所述耦合子电路与所述第一节点电连接的一端；所述第二维持子电路电连接所述第二节点、所述第二电位信号线、以及所述耦合子电路与所述第一节点电连接的一端，所述第二维持子电路用于在所述第二节点的电位控制下将所述第二电位信号线的信号传输至所述耦合子电路与所述第一节点电连接的一端。
在一些实施方式中，所述第二复位子电路包括第二复位晶体管，所述第二复位晶体管的栅极为所述第二复位控制端，所述第二复位晶体管的第一极电连接所述复位信号线，所述第二复位晶体管的第二极电连接所述耦合子电路电连接所述第一节点的一端；所述第二维持子电路包括第二维持体管，所述第二维持体管的栅极电连接所述第二节点，所述第二维持体管的第一极电连接所述耦合子电路电连接所述第一节点的一端，所述第二维持体管的第二极电连接所述第二电位信号线。
在一些实施方式中，栅极驱动电路单元还包括：第二输出子电路，被构造为根据施加到所述第二节点和所述第三节点的电压将第五输入端或第六输入端的信号传输至第二输出端。
在一些实施方式中，所述第五输入端接收第一时钟信号线的信号，所述第六输入端接收第二电位信号线的信号。
在一些实施方式中，所述第五输入端接接收的所述第一时钟信号线与所述第三输入端接收的所述第一时钟信号线不同；所述第五输入端接接收的所述第一时钟信号线中的高电位，大于所述第三输入端接收的所述第一时钟信号线中的高电位；所述第五输入端接接收的所述第一时钟信号线中的低电位，小于所述第三输入端接收的所述第一时钟信号线中的低电位；所述第六输入端接收的所述第二电位信号线与所述第四输入端接收的所述第二电位信号线不同；所述第六输入端接收的所述第二电位信号线中的电位，大于所述第四输入端接收的所述第二电位信号线中的电位。
在一些实施方式中，所述第一信号线中的信号为起始信号，所述第一电位信号线中的信号为低电位，所述第二电位信号线中的信号为高电位，所述栅极驱动电路单元中的薄膜晶体管均为P型。
在本公开的第二方面，提供了一种栅极驱动电路，包括至少一个级联电路，每个级联电路包括多个依次级联的栅极驱动电路单元，所述栅极驱动电路单元为本公开的第一方面提供的栅极驱动电路单元。
在本公开的第三方面，提供了一种显示基板的制造方法，包括：提供一基底；在所述基底上制造至少一个级联电路，每个级联电路包括多个依次级联的栅极驱动电路单元，所述栅极驱动电路单元为本公开的第一方面提供的栅极驱动电路单元。
在本公开的第四方面，提供了一种显示基板，包括本公开的第一方面提供的栅极驱动电路单元。
在一些实施方式中，所述栅极驱动电路单元中的耦合子电路包括耦合电容；所述第一输出子电路包括第一输出晶体管和第二输出晶体管；所述显示基板包括基底和设置于所述基底一侧的栅极金属层，所述栅极金属层包括所述耦合电容的第二极板和所述第一输出晶体管的栅极，且所述耦合电容的第二极板和所述第一输出晶体管的栅极直接相连。
在一些实施方式中，所述栅极驱动电路单元中的第一输出子电路还包括第一电容，所述耦合电容和所述第一电容沿第一方向排布；所述栅极金属层还包括所述第一电容的第二极板和所述第二输出晶体管的栅极，且所述第一电容的第二极板和所述第二输出晶体管的栅极直接相连；在第二方向上，所述第一输出晶体管和所述第二输出晶体管位于所述耦合电容和所述第一电容的同一侧，所述第一方向与所述第二方向相交。
在一些实施方式中，所述栅极驱动电路单元中的第二输入子电路包括第二输入晶体管和第三输入晶体管；所述显示基板还包括第一维持子电路和第一复位子电路，所述第一维持子电路包括第一维持晶体管；所述第一复位子电路包括第一复位晶体管；所述显示基板包括位于所述基底与所述栅极金属层之间的半导体层，所述半导体层包括一连续的第一半导体图案，所述第二输入晶体管的有源部、所述第一维持晶体管的有源部和所述第一复位晶体管的有源部由所述第一半导体图案形成。
在一些实施方式中，所述第一半导体图案包括第一子半导体图案、第二子半导体图案和第三子半导体图案，所述第二子半导体图案连在所述第一子半导体图案和所述第三子半导体图案之间，所述第一子半导体图案的延伸方向与所述第三子半导体图案的延伸方向平行，所述第二子半导体图案的延伸方向为非直线延伸；所述第一子半导体图案包括所述第二输入晶体管的有源部，所述第二子半导体图案包括所述第一维持晶体管的有源部，所述第三子半导体图案包括所述第一复位晶体管的有源部。
在一些实施方式中，所述第二输入晶体管的有源部的沟道延伸方向、所述第一维持晶体管的有源部的沟道延伸方向和所述第一复位晶体管的有源部的沟道延伸方向相互平行。
在一些实施方式中，所述栅极驱动电路单元中的第一输入子电路包括第一输入晶体管；所述第一输入子电路还包括第四输入晶体管；在所述第二方向上，所述第一输入晶体管、所述第四输入晶体管、所述第二输入晶体管、所述第三输入晶体管、所述第一维持晶体管和所述第一复位晶体管均位于所述耦合电容和所述第一电容的一侧，所述第一输出晶体管和所述第二输出晶体管均位于所述耦合电容和所述第一电容的另一侧。
在一些实施方式中，所述显示基板包括第一时钟信号线、第二时钟信号线、第一电位信号线、第二电位信号线和复位信号线；所述第一时钟信号线包括第一子时钟线和第二子时钟线，所述第一子时钟线和所述第二子时钟线中的信号相同；所述第二时钟信号线包括第三子时钟线和第四子时钟线，所述第三子时钟线和所述第四子时钟线中的信号相同；所述第二电位信号线包括第一子电位线和第二子电位线，所述第一子电位线和所述第二子电位线中的信号相同；所述第一子时钟线、所述第三子时钟线、所述第一子电位线、所述第一电位信号线、所述复位信号线、所述第四子时钟线、所述第二子时钟线和所述第二子电位线沿所述第二方向依次排布；所述耦合电容在所述基底上正投影与所述复位信号线在所述基底上的正投影、所述第四子时钟线在所述基底上的正投影、以及所述第二子时钟线在所述基底上的正投影均至少部分重叠。
在一些实施方式中，所述第一复位晶体管在所述基底上的正投影与所述复位信号线在所述基底上的正投影至少部分重叠；所述第一电容在所述基底上正投影与所述第四子时钟线在所述基底上的正投影、以及所述第二子时钟线在所述基底上的正投影均至少部分重叠；在所述第一方向上，所述第一复位晶体管和所述第一电容位于所述耦合电容的同一侧；所述第二子电位线在所述基底上的正投影位于所述第一输出晶体管和所述第二输出晶体管远离所述耦合电容的一侧。
在本公开的第五方面，提供了一种显示装置，包括栅极驱动电路，所述栅极驱动电路包括本公开的第一方面提供的栅极驱动电路单元。
附图说明
图1为本公开一些实施例提供的一种栅极驱动电路单元的第一种电路示意图；
图2为本公开一些实施例提供的一种栅极驱动电路单元的第一种的多个信号线或信号的波形示意图；
图3为本公开一些实施例提供的一种栅极驱动电路单元的第二种电路示意图；
图4为本公开一些实施例提供的一种栅极驱动电路单元的第三种电路示意图；
图5为本公开一些实施例提供的一种栅极驱动电路单元的第二种的多个信号线或信号的波形示意图；
图6为本公开一些实施例提供的一种栅极驱动电路单元的第四种电路示意图；
图7为本公开一些实施例提供的一种栅极驱动电路单元的第五种电路示意图；
图8为本公开一些实施例提供的一种栅极驱动电路单元的第六种电路示意图；
图9为本公开一些实施例提供的一种所述栅极驱动电路单元的版图示意图；
图10为本公开一些实施例提供的一种所述栅极驱动电路单元的半导体层的版图示意图；
图11为本公开一些实施例提供的一种所述栅极驱动电路单元的栅极金属层的版图示意图；
图12为本公开一些实施例提供的一种所述栅极驱动电路单元的电容金属层的版图示意图；
图13为本公开一些实施例提供的一种所述栅极驱动电路单元的第二绝缘层的版图示意图；
图14为本公开一些实施例提供的一种所述栅极驱动电路单元的第一金属层的版图示意图；
图15为本公开一些实施例提供的一种所述栅极驱动电路单元的第三绝缘层的版图示意图；
图16为本公开一些实施例提供的一种所述栅极驱动电路单元的第二金属层的版图示意图。
具体实施方式
为了更好的理解本说明书实施例提供的技术方案，下面通过附图以及具体实施例对本说明书实施例的技术方案做详细的说明，应当理解本说明书实施例以及实施例中的具体特征是对本说明书实施例技术方案的详细的说明，而不是对本说明书技术方案的限定，在不冲突的情况下，本说明书实施例以及实施例中的技术特征可以相互组合。
在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。术语“两个以上”包括两个或大于两个的情况。
在相关技术中，为了稳定输出高性能的电信号，栅极驱动电路单元需要较多数量的薄膜晶体管和较多数量的电容部件，栅极驱动电路单元在版图或显示面板中需要占据较大区域的面积，即栅极驱动电路单元存在结构复杂的问题，不利于显示面板的窄边框需求。在一些栅极驱动电路单元中，虽然简化了结构，但存在不能稳定输出高性能的电信号的问题，输出的电信号的电位不够(例如，输出的高电位信号的电位不够高，输出的低电位信号的电位不够低)，即栅极驱动电路难以稳定输出满足显示或驱动需求的电信号。
有鉴于此，本公开提供了一种栅极驱动电路单元能够改善或解决上述技术问题。
本公开还提供了一种栅极驱动电路，包括至少一个级联电路，每个级联电路包括多个依次级联的栅极驱动电路单元，栅极驱动电路单元为上述中的栅极驱动电路单元。
本公开还提供了一种显示基板的制造方法，包括：提供一基底；在基底上制造至少一个级联电路，每个级联电路包括多个依次级联的栅极驱动电路单元，栅极驱动电路单元为上述中的的栅极驱动电路单元。
本公开还提供了一种显示基板，显示基板包括上述中的栅极驱动电路单元。
本公开还提供了一种显示装置，显示装置包括栅极驱动电路，栅极驱动电路包括上述中的栅极驱动电路单元。
本公开提供了一种栅极驱动电路单元，包括：第一输入子电路，被构造为根据第一输入端的信号来控制第一节点的电压；第二输入子电路，被构造为根据第二输入端的信号来控制第二节点的电压；耦合子电路，至少被构造为根据所述第一节点的电压来控制第三节点的电压；第一输出子电路，被构造为根据施加到所述第二节点和所述第三节点的电压将第三输入端的信号或第四输入端的信号传输至第一输出端。
在下述详细介绍中，为了更好说明本公开的发明精神，以不同实施例进行了说明，但不同实施例的说明并不作为本公开中不同实施情况或实施特征的结合限定。
请参阅图1至图8，图1为本公开一些实施例提供的一种栅极驱动电路单元的第一种电路示意图；图2为本公开一些实施例提供的一种栅极驱动电路单元的第一种的多个信号线或信号的波形示意图；
图3为本公开一些实施例提供的一种栅极驱动电路单元的第二种电路示意图；图4为本公开一些实施例
提供的一种栅极驱动电路单元的第三种电路示意图；图5为本公开一些实施例提供的一种栅极驱动电路单元的第二种的多个信号线或信号的波形示意图；图6为本公开一些实施例提供的一种栅极驱动电路单元的第四种电路示意图；图7为本公开一些实施例提供的一种栅极驱动电路单元的第五种电路示意图；
图8为本公开一些实施例提供的一种栅极驱动电路单元的第六种电路示意图。
本公开提供了一种栅极驱动电路单元1000，如图1所示，栅极驱动电路单元1000包括第一输入子电路100、第二输入子电路400、耦合子电路200、第一输出子电路300。所述第一输入子电路100被构造为根据第一输入端101的信号来控制第一节点N1的电压；所述第二输入子电路400被构造为根据第二输入端102的信号来控制第二节点N2的电压；所述耦合子电路200至少被构造为根据所述第一节点N1的电压来控制第三节点N3的电压；所述第一输出子电路300被构造为根据施加到所述第二节点N2和所述第三节点N3的电压将第三输入端103的信号或第四输入端104的信号传输至第一输出端OUT1。
示例地，所述栅极驱动电路单元1000也可以称之为移位寄存器。
示例地，所述第一输出端OUT1输出的信号可以是栅极驱动信号(扫描驱动信号)，栅极驱动信号可以提供至像素驱动电路。
示例地，所述第一输出端OUT1输出的信号也可以是级传信号，级传信号可以提供至下一级或其他级级联的所述栅极驱动电路单元1000。
示例地，所述耦合子电路200也可以被构造为根据所述第三节点N3的电压来控制所述第一节点N1的电压。例如，在一个时间阶段，所述耦合子电路200被构造为根据所述第一节点N1的电压来控制所述第三节点N3的电压，在另一个时间阶段，所述耦合子电路200也可以被构造为根据所述第三节点N3的电压来控制所述第一节点N1的电压。
在本公开中，所述第一输入子电路100被构造为根据所述第一输入端101的信号来控制所述第一节点N1的电压；所述第二输入子电路400被构造为根据所述第二输入端102的信号来控制所述第二节点N2的电压；所述耦合子电路200至少被构造为根据所述第一节点N1的电压来控制所述第三节点N3的电压；所述第一输出子电路300被构造为根据施加到所述第二节点N2和所述第三节点N3的电压将所述第三输入端103的信号或所述第四输入端104的信号传输至所述第一输出端OUT1。通过设置所述耦合子电路200，使得可以根据所述第一节点N1的电压来控制第三节点N3的电压，使得所述第三节点N3的电信号更好的匹配显示或驱动需求，例如使得所述第三节点N3的高电位更加高，例如使得所述第三节点N3的低电位更加低，可以使得所述第一输出子电路300中与所述第三节点N3电连接的薄膜晶体管打开充分或关闭完全，从而使得与所述第三节点N3电连接的薄膜晶体管打开时，所述第三输入端103的信号可以更好的传输至所述第一输出端OUT1，从而使得与所述第三节点N3电连接的薄膜晶体管关闭时，所述第三输入端103的信号可以更好的与所述第一输出端OUT1隔离，从而提高了所述栅极驱动电路单元1000输出信号的稳定性。
在本公开中，所述栅极驱动电路单元1000包括所述第一输入子电路100、所述第二输入子电路400、所述耦合子电路200、所述第一输出子电路300，所述栅极驱动电路单元1000的结构简单，所述栅极驱动电路单元1000包括的薄膜晶体管和电容的数量较小，所述栅极驱动电路单元1000在版图或显示面板中需要占据的区域面积较小，即所述栅极驱动电路单元1000存在结构简单的效果，有利于所述显示面板的窄边框。
因此，在本公开中，提供的所述栅极驱动电路单元1000，同时具有结构简单和稳定输出满足显示需求的电信号的效果。
在一些实施方式中，如图1所示，所述栅极驱动电路单元1000满足如下条件中至少之一：所述第一输入端101接收第一信号线STV的信号；所述第二输入端102接收第一电位信号线VGL的信号；所述第三输入端103接收第一时钟信号线CB的信号，所述第四输入端104接收第二电位信号线VGH的信号。
需要说明的是，如图1所示，示例了所述栅极驱动电路单元1000同时满足如下条件：所述第一输入端101接收所述第一信号线STV的信号；所述第二输入端102接收所述第一电位信号线VGL的信号；所述第三输入端103接收所述第一时钟信号线CB的信号，所述第四输入端104接收所述第二电位信号线VGH的信号。但不限于此，在本公开另外一些实施方式中，所述栅极驱动电路单元1000可以满足上述中部分条件。
示例地，在一些实施例中，所述第一电位信号线VGL的信号和所述第二电位信号线VGH的信号中一者为低电位信号，另一者为高电位信号。
需要说明的是，如图1和图2所示，在本公开中，以所述第一电位信号线VGL的信号为低电位信号，以所述第二电位信号线VGH的信号为高电位信号举例说明，但不限于此。
示例地，如图1所示，在本公开中，以所述第一信号线STV的信号为起始信号举例说明，但不限于此。
示例地，如图1所示，在本公开中，以所述第三输入端103接收所述第一时钟信号线CB的信号举例说明，但不限于此。
示例地，如图1所示，在本公开中，以所述第四输入端104接收所述第二电位信号线VGH的信号举例说明，但不限于此。
示例地，在本公开中，第一时钟信号线CB的信号和第二时钟信号线CK的信号至少部分时间反相，例如所述第一时钟信号线CB为所述第二时钟信号线CK的反相信号，但不限于此。如图2所示。
示例地，所述第三输入端103接收所述第一时钟信号线CB，所述第一时钟信号线CB的信号为高电位和低电位交替的电信号，所述第一时钟信号线CB的信号还可以对所述第三节点N3的电压产生控制(例如，通过到电容或寄生电容之间的耦合效应)，从而可以通过所述第一输出子电路300(第一输出晶体管T5)同时控制所述第三节点N3的电位，从而可以减小所述栅极驱动电路单元1000所包括的薄膜晶体管和电容的数量较小，使得所述栅极驱动电路单元1000存在结构简单的效果，有利于显示面板的窄边框。
在一些实施方式中，如图1所示，在一些实施方式中，所述栅极驱动电路单元1000还包括第一维持子电路500、第一复位子电路600；
所述第一输入子电路100电连接所述第一信号线STV、第二时钟信号线CK和所述第一节点N1，所述第一输入子电路100用于在所述第二时钟信号线CK的信号控制下，将所述第一信号线STV的信号输入至所述第一节点N1；
所述第二输入子电路400电连接所述第一电位信号线VGL、所述第二时钟信号线CK、所述第二节点N2、所述第一节点N1和所述第二电位信号线VGH，所述第二输入子电路400用于在所述第一节点N1和所述第二时钟信号线CK的信号控制下，将所述第二电位信号线VGH或所述第一电位信号线VGL的信号传输至所述第二节点N2；
所述第一维持子电路500电连接所述第二节点N2、所述第三节点N3和所述第二电位信号线VGH，所述第一维持子电路500用于在所述第二节点N2的电位控制下将所述第二电位信号线VGH的信号传输至所述第三节点N3；
所述第一输出子电路300电连接所述第一时钟信号线CB、所述第三节点N3、所述第二节点N2和所述第二电位信号线VGH，所述第一输出子电路300用于在所述第三节点N3和所述第二节点N2的电位控制下，将所述第一时钟信号线CB或所述第二电位信号线VGH的信号传输至所述第一输出端OUT1；
所述第一复位子电路600电连接第一复位控制端601K、复位信号线PCX和所述耦合子电路200的一端，所述第一复位子电路600用于在所述第一复位控制端601K的信号控制下，将所述复位信号线PCX的电位传输至所述耦合子电路200的一端。
示例地，所述第一维持子电路500被构造为根据所述第二节点N2的电位将所述第二电位信号线VGH的信号传输至所述第三节点N3；
示例地，所述第一复位子电路600被构造为根据所述第一复位控制端601K的信号控制下，将所述复位信号线PCX的电位传输至所述耦合子电路200的一端。
在一些实施方式中，如图1所示，所述第一输入子电路100包括第一输入晶体管T1，所述第一输入晶体管T1的栅极电连接所述第二时钟信号线CK，所述第一输入晶体管T1的第一极电连接所述第一信号线STV，所述第一输入晶体管T1的第二极电连接所述第一节点N1；
所述耦合子电路200包括耦合电容C2，所述耦合电容C2的第一极板C2a电连接所述第一节点N1，所述耦合电容C2的第二极板C2b电连接所述第三节点N3；
所述第一输出子电路300包括第一输出晶体管T5和第二输出晶体管T4，所述第一输出晶体管T5的栅极电连接所述第三节点N3，所述第一输出晶体管T5的第一极电连接所述第一时钟信号线CB，所述第一输出晶体管T5的第二极电连接所述第一输出端OUT1，所述第二输出晶体管T4的栅极电连接所述第二节点N2，所述第二输出晶体管T4的第二极电连接所述第二电位信号线VGH，所述第二输出晶体管T4的第一极电连接所述第一输出端OUT1；
需要说明的是，如图1所示，在本公开中，定义薄膜晶体管的左侧或下侧的电极/一端为薄膜晶体管的第一极，薄膜晶体管的右侧或上侧的电极/一端为薄膜晶体管的第二极。薄膜晶体管的第一极为源极和漏极中一者，薄膜晶体管的第二极为源极和漏极中另一者，在一些实施情况中，薄膜晶体管的源极和漏极可以互换。
在一些实施方式中，如图1所示，所述第二输入子电路400包括第二输入晶体管T2和第三输入晶体管T3，所述第二输入晶体管T2的栅极电连接所述第一节点N1，所述第二输入晶体管T2的第一极电连接所述第二电位信号线VGH，所述第二输入晶体管T2的第二极电连接所述第二节点N2，所述第三输入晶体管T3的栅极电连接所述第二时钟信号线CK，所述第三输入晶体管T3的第一极电连接所述第一电位信号线VGL，所述第三输入晶体管T3的第二极电连接所述第二节点N2；
所述第一维持子电路500包括第一维持晶体管T6，所述第一维持晶体管T6的栅极电连接所述第二节点N2，所述第一维持晶体管T6的第一极电连接所述第三节点N3，所述第一维持晶体管T6的第二极电连接所述第二电位信号线VGH。
在一些实施方式中，如图1所示，所述第一复位子电路600包括第一复位晶体管T7，所述第一复位晶体管T7的栅极为所述第一复位控制端601K，所述第一复位晶体管T7的第一极电连接所述复位信号线PCX，所述第一复位晶体管T7的第二极电连接所述第三节点N3。
在一些实施方式中，如图1所示，所述第一复位控制端601K电连接所述第一信号线STV、栅极驱动电路中级联的上一级所述栅极驱动电路单元1000的所述第一节点N1、所述栅极驱动电路中级联的上一级所述栅极驱动电路单元1000的所述第三节点N3、以及所述栅极驱动电路中级联的上一级所述耦合电容C2的第一极板中任一者。
示例地，图1、图3和图4示意了，所述第一复位控制端601K电连接所述第一信号线STV；图6示意了所述第一复位控制端601K电连接所述栅极驱动电路中级联的上一级所述栅极驱动电路单元1000的所述第一节点N1(上一级所述栅极驱动电路单元的所述第一节点为N1(N-1))。所述第一复位控制端601K还可以电连接所述栅极驱动电路中级联的上一级所述栅极驱动电路单元1000的所述第三节点N3、以及所述栅极驱动电路中级联的上一级所述耦合电容C2的第一极板中一者。
示例地，通过此种的所述第一复位控制端601K电连接信号线或节点设置，不用额外单独增加新的信号线，可以减小信号线的数量，从而简化所述栅极驱动电路单元1000的结构。
在一些实施方式中，如图1所示，所述第一输入子电路100还包括第四输入晶体管T8，所述第四输入晶体管T8的栅极电连接所述第一电位信号线VGL，所述第四输入晶体管T8的第一极电连接所述第一输入晶体管T1的第二极，所述第四输入晶体管T8的第二极电连接所述耦合电容C2的第一极板C2a；或/和，所述第一输出子电路300还包括第一电容C1，所述第一电容C1的第一极板C1a电连接所述第二输出晶体管T4的栅极，所述第一电容C1的第二极板C1b电连接所述第二输出晶体管T4的第二极。
示例地，所述第四输入晶体管T8可以起到保护所述第一输入晶体管T1和所述第二输入晶体管T2的作用，例如，当所述耦合电容C2的第一极板C2a或所述第四节点N4的电位过低时，所述第四输入晶体管T8可以避免所述耦合电容C2的第一极板C2a或所述第四节点N4的过低的低电位直接流入至所述第一节点N1，从而避免了所述第一输入晶体管T1和所述第二输入晶体管T2损坏。
在一些实施方式中，请结合图1和图5所示，所述第一信号线STV为起始信号线，在所述第一信号线STV输出第一个低电位的信号前，所述复位信号线PCX的信号为高电位信号(图5中虚线框所示)，且所述复位信号线PCX的高电位大于所述第一信号线STV的高电位；在所述第一信号线STV输出第一个低电位的信号开始，所述复位信号线PCX的信号为低电位信号。
示例地，为了防止所述显示面板上电启亮时(所述显示面板点亮时)，所述第三节点N3的低电压误使所述第一输出晶体管T5打开而输出低压信号，所以在上电时，在所述第一信号线STV转变为低电压信号之前，所述复位信号线PCX给高电压信号，且所述复位信号线PCX的高电位大于所述第一信号线STV的高电位，使所述第一复位晶体管T7打开，所述第三节点N3置为高电压信号，保证所述第一输出晶体管T5关闭，防止误输出，所述复位信号线PCX波形如图5中所示，所述复位信号线PCX的高电位时间为第一级栅极驱动电路单元1000电连接的所述第一信号线STV输出低电位之前。
在一些实施方式中，如图3和图4所示，所述栅极驱动电路单元1000还包括第二复位子电路700和第二维持子电路800中至少一者；
所述第一复位子电路600电连接所述耦合子电路200与所述第三节点N3电连接的一端，所述第二复位子电路700电连接第二复位控制端602K、所述复位信号线PCX、以及所述耦合子电路200与所述第一节点N1电连接的一端，所述第二复位子电路700用于在所述第二复位控制端602K的信号控制下，将所述复位信号线PCX的电位传输至所述耦合子电路200与所述第一节点N1电连接的一端；
所述第二维持子电路800电连接所述第二节点N2、所述第二电位信号线VGH、以及所述耦合子电路200与所述第一节点N1电连接的一端，所述第二维持子电路800用于在所述第二节点N2的电位控制下将所述第二电位信号线VGH的信号传输至所述耦合子电路200与所述第一节点N1电连接的一端。
在一些实施方式中，如图3和图4所示，所述第二复位子电路700包括第二复位晶体管T9，所述第二复位晶体管T9的栅极为所述第二复位控制端602K，所述第二复位晶体管T9的第一极电连接所述复位信号线PCX，所述第二复位晶体管T9的第二极电连接所述耦合子电路200电连接所述第一节点N1的一端；
所述第二维持子电路800包括第二维持体管T10，所述第二维持体管T10的栅极电连接所述第二节点N2，所述第二维持体管T10的第一极电连接所述耦合子电路200电连接所述第一节点N1的一端，所述第二维持体管T10的第二极电连接所述第二电位信号线VGH。
示例地，如图3所示，所述第二复位晶体管T9的栅极为所述第二复位控制端602K，所述第二复位控制端602K电连接所述第一信号线STV、所述栅极驱动电路中级联的上一级所述栅极驱动电路单元1000的所述第一节点N1、所述栅极驱动电路中级联的上一级所述栅极驱动电路单元1000的所述第三节点N3、以及所述栅极驱动电路中级联的上一级所述耦合电容C2的第一极板中任一者。
示例地，如图3所示，所述第二复位晶体管T9的第一极电连接所述复位信号线PCX，所述第二复位晶体管T9的第二极电连接所述耦合电容C2的第一极板C2a。
示例地，如图4所示，所述第二维持体管T10的栅极电连接所述第二节点N2，所述第二维持体管T10的第一极电连接所述耦合电容C2的第一极板C2a，所述第二维持体管T10的第二极电连接所述第二电位信号线VGH。
示例地，如图2和图4所示，在第一阶段，t1时刻，所述第二复位子电路700的所述第二复位晶体管T9复位所述第四节点N4点的电位，提高所述第四节点N4点的电位的稳定性。
示例地，如图2和图4所示，在第三阶段，t3时刻，所述第二维持子电路800的所述第二维持体管T10维持所述第四节点N4的电位的稳定性。
在一些实施方式中，如图7和图8所示，所述栅极驱动电路单元1000还包括第二输出子电路900，所述第二输出子电路900被构造为根据施加到所述第二节点N2和所述第三节点N3的电压将第五输入端105或第六输入端106的信号传输至第二输出端OUT2。
示例地，所述第一输出端OUT1和所述第二输出端OUT2中一者可以输出栅极驱动信号，所述第一输出端OUT1和所述第二输出端OUT2中另一者可以输出级传信号。
示例地，所述第二输出子电路900包括第三输出晶体管T12和第四输出晶体管T11，所述第三输出晶体管T12的栅极电连接所述第三节点N3，所述第三输出晶体管T12的第一极电连接所述第一时钟信号线CB，所述第三输出晶体管T12的第二极电连接所述第二输出端OUT2，所述第四输出晶体管T11的栅极电连接所述第二节点N2，所述第四输出晶体管T11的第二极电连接所述第二电位信号线VGH，所述第四输出晶体管T11的第一极电连接所述第二输出端OUT2。
需要说明的是，所述第一电容C1的第一极板C1a电连接所述第二输出晶体管T4的栅极，所述第一电容C1的第二极板C1b电连接所述第二输出晶体管T4的第二极。在另外一些实施例中，也可以设置所述第一电容C1的第一极板C1a电连接所述第四输出晶体管T11的栅极，所述第一电容C1的第二极板C1b电连接所述第四输出晶体管T11的第二极。在另外一些实施例中，也可以在所述第二输出晶体管T4的栅极和所述第四输出晶体管T11的栅极的对应位置均设置电连接的所述第一电容C1。
在一些实施方式中，如图7和图8所示，所述第五输入端105接收所述第一时钟信号线CB的信号，所述第六输入端106接收所述第二电位信号线VGH的信号。
在一些实施方式中，如图7和图8所示，所述第五输入端105接接收的所述第一时钟信号线CB与所述第三输入端103接收的所述第一时钟信号线CB不同；
例如，所述第五输入端105接接收的所述第一时钟信号线CB中的高电位，大于所述第三输入端103接收的所述第一时钟信号线CB中的高电位；
例如，所述第五输入端105接接收的所述第一时钟信号线CB中的低电位，小于所述第三输入端103接收的所述第一时钟信号线CB中的低电位；
在一些实施方式中，如图7和图8所示，所述第六输入端106接收的所述第二电位信号线VGH与所述第四输入端104接收的所述第二电位信号线VGH不同；
例如，所述第六输入端106接收的所述第二电位信号线VGH中的电位，大于所述第四输入端104接收的所述第二电位信号线VGH中的电位。
示例地，以所述第二电位信号线VGH中的信号为高电位举例，所述第三输出晶体管T12的第一极接接收的所述第一时钟信号线CB与所述第一输出晶体管T5的第一极接收的所述第一时钟信号线CB不同；所述第三输出晶体管T12的第一极接接收的所述第一时钟信号线CB中的高电位，大于所述第一输出晶体管T5的第一极接收的所述第一时钟信号线CB中的高电位；所述第三输出晶体管T12的第一极接接收的所述第一时钟信号线CB中的低电位，小于所述第一输出晶体管T5的第一极接收的所述第一时钟信号线CB中的低电位；所述第四输出晶体管T11的第二极接收的所述第二电位信号线VGH与所述第二输出晶体管T4的第二极接收的所述第二电位信号线VGH不同；所述第四输出晶体管T11的第二极接收的所述第二电位信号线VGH中的电位，大于所述第二输出晶体管T4的第二极接收的所述第二电位信号线VGH中的电位。
示例地，图8中示意了，所述第三输出晶体管T12的第一极电连接第二输出时钟信号线CB2，所述第四输出晶体管T11的第二极电连接第二输出电位信号线VGH2；所述第一输出晶体管T5的第一极电连接第一输出时钟信号线CB1，所述第二输出晶体管T4的第二极电连接第一输出电位信号线VGH1。
示例地，当所述第五输入端105接接收的所述第一时钟信号线CB中的高电位大于所述第三输入端103接收的所述第一时钟信号线CB中的高电位，所述第五输入端105接接收的所述第一时钟信号线CB中的低电位小于所述第三输入端103接收的所述第一时钟信号线CB中的低电位，所述第六输入端106接收的所述第二电位信号线VGH中的电位大于所述第四输入端104接收的所述第二电位信号线VGH中的电位时，可以设置所述第一输出端OUT1输出级传信号，所述第二输出端OUT2输出栅极驱动信号。可以使得所述第三输出晶体管T12的栅极与源极形成较大电压差，可以更好的维持所述第三输出晶体管T12的打开性能，使得第一输出端OUT1更好的输出电信号。可以使得所述第四输出晶体管T11的栅极与源极形成较大电压差，可以更好的维持所述第四输出晶体管T11的关闭性能，避免第二输出端OUT2的输出电信号受到干扰。
在一些实施方式中，如图1至图8所示，所述第一信号线STV中的信号为起始信号，所述第一电位信号线VGL中的信号为低电位，所述第二电位信号线VGH中的信号为高电位，所述栅极驱动电路单元1000中的薄膜晶体管均为P型。
示例地，在另外一些实施方式中，所述第一信号线STV中的信号为起始信号，所述第一电位信号线中的信号为高电位，所述第二电位信号线中的信号为低电位，所述栅极驱动电路单元1000中的薄膜晶体管均为N型，但不限于此。
示例地，以图1所示的栅极驱动电路单元1000为例说明其工作过程，所述第一信号线STV中的信号为起始信号，所述第一电位信号线VGL中的信号为低电位，所述第二电位信号线VGH中的信号为高电位，所述栅极驱动电路单元1000中的薄膜晶体管均为P型，但在其他实施例中或工作过程中，所述第一电位信号线VGL中的信号、所述第二电位信号线VGH中的信号、薄膜晶体管的类型可以不限于此，请结合图1和图2所示。
在第一阶段，t1时刻，所述第二时钟信号线CK为低电压，所述第一输入子电路100工作，所述第一输入晶体管T1打开，所述第一信号线STV的低电压信号写入所述第一节点N1，由于所述第四输入晶体管T8常开，低电压信号写入所述第四节点N4点，由于所述耦合电容C2的电容耦合作用，拉低所述第三节点N3的电压，由于此时所述第一时钟信号线CB的信号是高电压，所述第一输出子电路300工作，所以所述第一输出晶体管T5打开，所述第一输出端OUT1输出高电压信号；同时，所述第一节点N1为低电压，所述第二输入子电路400工作，所述第二输入晶体管T2打开，所述第二电位信号线VGH的信号写入所述第二节点N2，所述第二输出晶体管T4关闭。
在第二阶段，t2时刻，所述第一时钟信号线CB转为低电压信号，由于薄膜晶体管(所述第一输出晶体管T5)存在极间电容，当所述第一时钟信号线CB的信号从高电位转变为低电位时，所述第三节点N3被拉低，保证所述第一时钟信号线CB低电压信号正常输出；此时由于所述第一电容C1作用，所述第二节点N2维持上一时刻高压信号，所述第二输出晶体管T4关闭；所述第一输出端OUT1输出低电压信号。
在第三阶段，t3时刻，所述第一信号线STV的高压信号写入所述第一节点N1、所述第四节点N4，由于所述耦合电容C2的电容耦合作用，所述第三节点N3的电位被拉高，所述第一输出晶体管T5关闭；此时所述第二输入子电路400工作，所述第三输入晶体管T3打开，所述第二输入晶体管T2关闭，所述第二节点N2写入所述第一电位信号线VGL的信号，所述第二输出晶体管T4打开，所述第一输出端OUT1输出高电位信号(所述第二电位信号线VGH的信号)；且由于所述第二节点N2低电压，所述第一维持子电路500工作，所述第一维持晶体管T6打开，所述第二电位信号线VGH的信号写入所述第三节点N3，保证所述第一输出晶体管T5关闭。
示例地，其中，所述第一信号线STV中的信号为低电压时，所述第一复位子电路600工作，所述第一复位晶体管T7打开，PCX信号写入所述第三节点N3，对所述第三节点N3进行复位，且为了下一时刻所述第三节点N3有足够的低电压，保证所述第一时钟信号线CB的低电压信号能够正常输出，降低输出波形收到下拉管Vth阈值(阈值电压)损耗问题，所述复位信号线PCX的信号为低电压信号。
示例地，为了提高所述复位信号线PCX的复位作用，可以设置所述复位信号线PCX的低电位较所述第一电位信号线VGL中的低电位更低(当所述第一电位信号线VGL中的信号为低电位时)。
本公开还提供了一种栅极驱动电路，栅极驱动电路包括至少一个级联电路，每个所述级联电路包括多个依次级联的栅极驱动电路单元，所述栅极驱动电路单元为上述中任一项所述的栅极驱动电路单元1000，或所述栅极驱动电路单元为上述中任几项结合的所述的栅极驱动电路单元1000。
请参阅图9至图16，图9为本公开一些实施例提供的一种所述栅极驱动电路单元1000的版图示意图；图10为本公开一些实施例提供的一种所述栅极驱动电路单元1000的半导体层的版图示意图；图11为本公开一些实施例提供的一种所述栅极驱动电路单元1000的栅极金属层的版图示意图；图12为本公开一些实施例提供的一种所述栅极驱动电路单元1000的电容金属层的版图示意图；图13为本公开一些实施例提供的一种所述栅极驱动电路单元1000的第二绝缘层的版图示意图；图14为本公开一些实施例提供的一种所述栅极驱动电路单元1000的第一金属层的版图示意图；图15为本公开一些实施例提供的一种所述栅极驱动电路单元1000的第三绝缘层的版图示意图；图16为本公开一些实施例提供的一种所述栅极驱动电路单元1000的第二金属层的版图示意图。图9至图16以图1所示的栅极驱动电路单元(第一种电路示意图)作为示例进行说明。
本公开还提供了一种显示基板的制造方法，显示基板的制造方法包括：提供一基底；在所述基底上制造至少一个级联电路，每个级联电路包括多个依次级联的栅极驱动电路单元，所述栅极驱动电路单元为上述中任一项所述的栅极驱动电路单元1000，或所述栅极驱动电路单元1000为上述中任几项结合的所述的栅极驱动电路单元1000。
示例地，在一些实施方式中，显示基板的制造方法包括下述的步骤S10至步骤S19。
步骤S10，提供一基底。
示例地，所述基底可以为玻璃或柔性基底，例如所述基底的材料可以为聚酰亚胺，但不限于此。
步骤S11，如图10所示，在所述基底的一侧形成半导体层PO。
示例地，所述半导体层PO包括所述第一输入晶体管T1的有源部P1、所述第四输入晶体管T8的有源部P8、所述第二输入晶体管T2的有源部P2、所述第三输入晶体管T3的有源部P3、所述第一维持晶体管T6的有源部P6、所述第一复位晶体管T7的有源部P7、所述第一输出晶体管T5的有源部P5和所述第二输出晶体管T4的有源部P4。
步骤S12，在所述半导体层PO远离所述基底的一侧形成栅极绝缘层GI(图图未示意)。
步骤S13，如图11所示，在所述栅极绝缘层GI远离所述基底的一侧形成栅极金属层Ge1。
示例地，所述栅极金属层Ge1包括所述第一输入晶体管T1的栅极G1、所述第四输入晶体管T8的栅极G8、所述第二输入晶体管T2的栅极G2、所述第三输入晶体管T3的栅极G3、所述第一维持晶体管T6的栅极G6、所述第一复位晶体管T7的栅极G7、所述第一输出晶体管T5的栅极G5和所述第二输出晶体管T4的栅极G4。
示例地，所述栅极金属层Ge1还包括所述耦合电容的第二极板C2b和所述第一电容的第二极板C1b。
步骤S14，在所述栅极金属层Ge1远离所述栅极金属层Ge1的一侧形成第一绝缘层(图未示意)。
步骤S15，如图12所示，在所述栅极绝缘层GI远离所述第一绝缘层的一侧形成电容金属层Ge2。
示例地，所述电容金属层Ge2包括所述耦合电容的第一极板C2a和所述第一电容的第一极板C1a。
步骤S16，如图13所示，在所述电容金属层Ge2远离所述基底的一侧形成第二绝缘层ILD。
示例地，图13中示意了所述第二绝缘层ILD中的多个过孔。
步骤S17，如图14所示，在所述第二绝缘层ILD远离所述基底的一侧形成第一金属层SD1。
示例地，所述第一金属层SD1包括所述第一输入晶体管T1的第一极S1和第二极D1、所述第四输入晶体管T8的第一极S8和第二极D8、所述第二输入晶体管T2的第一极S2和第二极D2、所述第三输入晶体管T3的第一极S3和第二极D2、所述第一维持晶体管T6的第一极S6和第二极D6、所述第一复位晶体管T7的第一极S7和第二极D7、所述第一输出晶体管T5的第一极S5和第二极D5、以及所述第二输出晶体管T4的第一极S4和第二极D4。
示例地，所述第一金属层SD1还包括所述第一时钟信号线CB的第一子时钟线CB-1，以及所述第二时钟信号线CK的第三子时钟线CK-1。
步骤S18，如图15所示，在所述第一金属层SD1层远离所述基底的一侧形成第三绝缘层PLN。
示例地，所述第三绝缘层PLN可以为平坦层。
示例地，图15中示意了所述第三绝缘层PLN中的多个过孔。
步骤S19，如图16所示，在所述第三绝缘层PLN远离所述基底的一侧形成第二金属层SD2。
示例地，所述第二金属层SD2包括所述第一子电位线VGH-1、所述第一电位信号线VGL、所述复位信号线PCX、所述第四子时钟线CK-2、所述第二子时钟线CB-2和所述第二子电位线VGH-2。
本公开还提供了一种显示基板2000，显示基板2000包括上述中任一项所述的栅极驱动电路单元1000，或显示基板2000包括上述中任几项结合的所述的栅极驱动电路单元1000。
示例地，显示基板2000可以采用上述中任一项的显示基板2000的制造方法制造而成。
示例地，显示基板2000可以包括至少一个级联电路，每个级联电路包括多个依次级联的栅极驱动电路单元，所述栅极驱动电路单元为上述中任一项所述的栅极驱动电路单元1000，或所述栅极驱动电路单元为上述中任几项结合的所述的栅极驱动电路单元1000。
在一些实施方式中，如图9和11所示，所述耦合子电路200包括耦合电容C2；所述第一输出子电路300包括第一输出晶体管T5和第二输出晶体管T4；所述显示基板2000包括所述基底和设置于所述基底一侧的栅极金属层Ge1，所述栅极金属层Ge1包括所述耦合电容C2的第二极板C2b和所述第一输出晶体管T5的栅极，且所述耦合电容C2的第二极板C2b和所述第一输出晶体管T5的栅极直接相连。
示例地，如图9和11所示，所述栅极金属层Ge1包括所述耦合电容C2的第二极板C2b和所述第一输出晶体管T5的栅极，且所述耦合电容C2的第二极板C2b和所述第一输出晶体管T5的栅极直接相连，可以减小换线，有利于减小栅极驱动电路单元1000或栅极驱动电路在版图或显示面板中需要占据的面积，有助窄边框设计。
在一些实施方式中，如图9和11所示，所述第一输出子电路300还包括第一电容C1，所述耦合电容C2和所述第一电容C1沿第一方向Y排布；所述栅极金属层Ge1还包括所述第一电容C1的第二极板C1b和所述第二输出晶体管T4的栅极，且所述第一电容C1的第二极板C1b和所述第二输出晶体管T4的栅极直接相连；在第二方向X上，所述第一输出晶体管T5和所述第二输出晶体管T4位于所述耦合电容C2和所述第一电容C1的同一侧，所述第一方向Y与所述第二方向X相交。
示例地，图9示例所述第一方向Y与所述第二方向X相互垂直，但不限于此。
示例地，显示面板可以包括显示区与边框区，所述显示区与所述边框区具有分界线，所述第一方向Y可以与所述显示区和所述边框区的分界线的延伸方向平行，所述第二方向X可以与所述显示区和所述边框区的分界线的延伸方向垂直，但不限于此。
示例地，如图9和11所示，所述耦合电容C2和所述第一电容C1沿所述第一方向Y排布，在所述第二方向X上，所述第一输出晶体管T5和所述第二输出晶体管T4位于所述耦合电容C2和所述第一电容C1的同一侧，可以减小栅极驱动电路单元1000在所述第一方向Y上的长度，有助于在高分辨率显示面板中，在所述第一方向Y上可以设置更多数量的所述栅极驱动电路单元1000。
在一些实施方式中，如图9和10所示，所述第二输入子电路400包括第二输入晶体管T2和第三输入晶体管T3；所述显示基板2000还包括第一维持子电路500和第一复位子电路600，所述第一维持子电路500包括第一维持晶体管T6；所述第一复位子电路600包括第一复位晶体管T7；所述显示基板2000包括位于所述基底与所述栅极金属层Ge1之间的半导体层PO，所述半导体层PO包括一连续的第一半导体图案PO1，所述第二输入晶体管T2的有源部P2、所述第一维持晶体管T6的有源部P6和所述第一复位晶体管T7的有源部P7由所述第一半导体图案PO1形成。
示例地，如图9和10所示，所述第二输入晶体管T2的有源部P2、所述第一维持晶体管T6的有源部P6和所述第一复位晶体管T7的有源部P7均由所述第一半导体图案PO1形成，所述第一半导体图案PO1为一连续的结构，可以减小所述第二输入晶体管T2、所述第一维持晶体管T6和所述第一复位晶体管T7之间电连接的过孔数量、电极数量，可以减小换线次数，有利于减小所述栅极驱动电路单元1000或所述栅极驱动电路在版图或显示面板中需要占据的面积，有助窄边框设计。
示例地，如图9和10所示，所述第一输入晶体管T1的有源图形/有源部P1设置为U型结构，所述第一输入晶体管T1的有源图形/有源部P1包括第一输入子有源部P1-1和第二子有源部P1-2，以使所述第一输入晶体管T1形成为双栅结构。
示例地，如图9至11所示，所述第一输入晶体管T1的有源图形/有源部P1设置为U型结构，所述第一输入晶体管T1形成为双栅结构，所述第一输入晶体管T1的栅极G1包括第一输入子栅极G11和第二输入子栅极G12。
示例地，如图9至11所示，所述第一输入晶体管T1的第一输入子栅极G11、所述第一输入晶体管T1的第二输入子栅极G12、所述第三输入晶体管T3的栅极G3为一连续的结构。
示例的，如图9至11所示，所述第一输入晶体管T1的有源图形/有源部P1设置为U型结构，使得所述第一输入晶体管T1形成双栅结构，而且使得所述第一输入晶体管T1在占用较小版图空间的情况下，更好的实现了所述第一输入晶体管T1的栅极G1与所述第二时钟信号线(第三子时钟线CK-1)和所述第三输入晶体管T3的栅极G3连接。
示例地，如图9和10所示，所述半导体层PO包括的所述第一输入晶体管T1的有源部P1、所述第四输入晶体管T8的有源部P8、所述第三输入晶体管T3的有源部P3为相互间隔的结构，这些薄膜晶体管的有源部与图1或图9中其他薄膜晶体管的有源部位间隔设置的结构。
在一些实施方式中，如图9和10所示，所述第一半导体图案PO1包括第一子半导体图案PO1-1、第二子半导体图案PO1-2和第三子半导体图案PO1-3，所述第二子半导体图案PO1-2连在所述第一子半导体图案PO1-1和所述第三子半导体图案PO1-3之间，所述第一子半导体图案PO1-1的延伸方向与所述第三子半导体图案PO1-3的延伸方向平行，所述第二子半导体图案PO1-2的延伸方向为非直线延伸；所述第一子半导体图案PO1-1包括所述第二输入晶体管T2的有源部P2，所述第二子半导体图案PO1-2包括所述第一维持晶体管T6的有源部P6，所述第三子半导体图案PO1-3包括所述第一复位晶体管T7的有源部P7。
示例地，如图9和10所示，所述第一子半导体图案PO1-1的延伸方向和所述第三子半导体图案PO1-3的延伸方向均与所述第一方向Y平行。
需要说明的是，在其他实施方式中，所述第一子半导体图案PO1-1的延伸方向和所述第三子半导体图案PO1-3的延伸方向也可以为所述第一方向Y之外的其他方向。
示例地，如图9和10所示，所述第一子半导体图案PO1-1的延伸方向与所述第三子半导体图案PO1-3的延伸方向平行，所述第二子半导体图案PO1-2的延伸方向为非直线延伸，可以减小所述第一子半导体图案PO1-1与所述第三子半导体图案PO1-3之间的距离，从而有利于减小栅极驱动电路单元1000或栅极驱动电路在版图或显示面板中需要占据的面积，有助窄边框设计。
在一些实施方式中，如图9和10所示，所述第二输入晶体管T2的有源部P2的沟道延伸方向、所述第一维持晶体管T6的有源部P6的沟道延伸方向和所述第一复位晶体管T7的有源部P7的沟道延伸方向相互平行。
示例地，如图9和10所示，所述第二输入晶体管T2的有源部P2的沟道延伸方向、所述第一维持晶体管T6的有源部P6的沟道延伸方向和所述第一复位晶体管T7的有源部P7的沟道延伸方向均与所述第一方向Y平行。
需要说明的是，在其他实施方式中，所述第二输入晶体管T2的有源部P2的沟道延伸方向、所述第一维持晶体管T6的有源部P6的沟道延伸方向和所述第一复位晶体管T7的有源部P7的沟道延伸方向也可以为所述第一方向Y之外的其他方向。
示例地，如图9和10所示，所述第二输入晶体管T2的有源部P2的沟道延伸方向、所述第一维持晶体管T6的有源部P6的沟道延伸方向和所述第一复位晶体管T7的有源部P7的沟道延伸方向相互平行，从而在显示基板2000或显示面板的制造过程中，有助于控制所述第二输入晶体管T2的有源部P2的沟道、所述第一维持晶体管T6的有源部P6的沟道和所述第一复位晶体管T7的有源部P7的沟道的均一性、载流子迁移性能。
在一些实施方式中，如图9和10所示，所述第一输入子电路100包括第一输入晶体管T1；所述第一输入子电路100还包括第四输入晶体管T8；在所述第二方向X上，所述第一输入晶体管T1、所述第四输入晶体管T8、所述第二输入晶体管T2、所述第三输入晶体管T3、所述第一维持晶体管T6和所述第一复位晶体管T7均位于所述耦合电容C2和所述第一电容C1的一侧，所述第一输出晶体管T5和所述第二输出晶体管T4均位于所述耦合电容C2和所述第一电容C1的另一侧。
示例地，如图9和10所示，所述第一输入晶体管T1、所述第四输入晶体管T8、所述第二输入晶体管T2、所述第三输入晶体管T3、所述第一维持晶体管T6和所述第一复位晶体管T7，与所述第一输出晶体管T5和所述第二输出晶体管T4在所述第二方向X上位于所述耦合电容C2和所述第一电容C1两侧，且所述耦合电容C2和所述第一电容C1沿所述第一方向Y排布，从而有利于减小栅极驱动电路单元1000或栅极驱动电路在版图或显示面板中需要占据的面积，有助窄边框设计。
在一些实施方式中，如图9、图14和图16所示，所述显示基板2000包括第一时钟信号线CB、第二时钟信号线CK、第一电位信号线VGL、第二电位信号线VGH和复位信号线PCX；
所述第一时钟信号线CB包括第一子时钟线CB-1和第二子时钟线CB-2，所述第一子时钟线CB-1和所述第二子时钟线CB-2中的信号相同；
所述第二时钟信号线CK包括第三子时钟线CK-1和第四子时钟线CK-2，所述第三子时钟线CK-1和所述第四子时钟线CK-2中的信号相同；
所述第二电位信号线VGH包括第一子电位线VGH-1和第二子电位线VGH-2，所述第一子电位线VGH-1和所述第二子电位线VGH-2中的信号相同；
所述第一子时钟线CB-1、所述第三子时钟线CK-1、所述第一子电位线VGH-1、所述第一电位信号线VGL、所述复位信号线PCX、所述第四子时钟线CK-2、所述第二子时钟线CB-2和所述第二子电位线VGH-2沿所述第二方向X依次排布；
所述耦合电容C2在所述基底上正投影与所述复位信号线PCX在所述基底上的正投影、所述第四子时钟线CK-2在所述基底上的正投影、以及所述第二子时钟线CB-2在所述基底上的正投影均至少部分重叠。
示例地，如图9、图14和图16所示，所述第一时钟信号线CB包括第一子时钟线CB-1和第二子时钟线CB-2，所述第一子时钟线CB-1和所述第二子时钟线CB-2中的信号相同；所述第二时钟信号线CK包括第三子时钟线CK-1和第四子时钟线CK-2，所述第三子时钟线CK-1和所述第四子时钟线CK-2中的信号相同；所述第二电位信号线VGH包括第一子电位线VGH-1和第二子电位线VGH-2，所述第一子电位线VGH-1和所述第二子电位线VGH-2中的信号相同。在这些信号线中，就近设置了两条子走线，可以使得与这些子走线电连接的结构(栅极、源极和漏极等)就近电连接，减小连接需要使用的过孔数量、电极数量，可以减小换线次数，不需要设置很长的连接电极，有利于减小栅极驱动电路单元1000或栅极驱动电路在版图或显示面板中需要占据的面积，有助窄边框设计。与此同时，一些子走线与与之电连接的结构直接相连，一些子走线在所述基底上的正投影与与之电连接的结构在所述基底上的正投影至少部分重叠，使得不需要设置很长的连接电极，也有利于减小栅极驱动电路单元1000或栅极驱动电路在版图或显示面板中需要占据的面积。
示例地，如图9、图14和图16所示，发明人在考虑栅极驱动电路单元1000的电性能的前提下，最大化的减小栅极驱动电路单元1000版图面积，所述第一输入晶体管T1、所述第四输入晶体管T8、所述第二输入晶体管T2、所述第三输入晶体管T3、所述第一维持晶体管T6、所述第一复位晶体管T7、所述第一输出晶体管T5和所述第二输出晶体管T4进行了图9所示的排布，为了适应这些薄膜晶体管的排布，从而设置了所述第一子时钟线CB-1、所述第三子时钟线CK-1、所述第一子电位线VGH-1、所述第一电位信号线VGL、所述复位信号线PCX、所述第四子时钟线CK-2、所述第二子时钟线CB-2和所述第二子电位线VGH-2沿所述第二方向X依次排布。
示例地，在一些实施方式中，所述显示基板包括第一时钟信号总线，所述第一时钟信号总线连接在焊盘区(所述焊盘区电连接驱动芯片或电路板等)和所述栅极驱动电路单元的设置区之间，所述第一时钟信号总线连接(引出)所述第一子时钟线CB-1和所述第二子时钟线CB-2，由所述第一时钟信号总线提供所述第一子时钟线CB-1和所述第二子时钟线CB-2中相同的电信号。
示例地，在一些实施方式中，所述显示基板包括第二时钟信号总线，所述第二时钟信号总线连接在焊盘区(所述焊盘区电连接驱动芯片或电路板等)和所述栅极驱动电路单元的设置区之间，所述第二时钟信号总线连接(引出)所述第三子时钟线CK-1和所述第四子时钟线CK-2，由所述第二时钟信号总线提供所述第三子时钟线CK-1和所述第四子时钟线CK-2中相同的电信号。
示例地，在一些实施方式中，所述显示基板包括第二电位信号总线，所述第二电位信号总线连接在焊盘区(所述焊盘区电连接驱动芯片或电路板等)和所述栅极驱动电路单元的设置区之间，所述第二电位信号总线连接(引出)所述第一子电位线VGH-1和所述第二子电位线VGH-2，由所述第二电位信号总线提供所述第一子电位线VGH-1和所述第二子电位线VGH-2中相同的电信号。
示例地，如图1、图9、图14和图16所示，所述第一输入子电路100包括第一输入晶体管T1，所述第一输入晶体管T1的栅极电连接所述第二时钟信号线CK(所述第三子时钟线CK-1)，所述第一输入晶体管T1的第一极电连接所述第一信号线STV，所述第一输入晶体管T1的第二极电连接所述第一节点N1。
示例地，如图1、图9、图14和图16所示，所述耦合子电路200包括耦合电容C2，所述耦合电容C2的第一极板C2a电连接所述第一节点N1，所述耦合电容C2的第二极板C2b电连接所述第三节点N3。
示例地，如图1、图9、图14和图16所示，所述第一输出子电路300包括第一输出晶体管T5和第二输出晶体管T4，所述第一输出晶体管T5的栅极电连接所述第三节点N3，所述第一输出晶体管T5的第一极电连接所述第一时钟信号线CB(所述第二子时钟线CB-2)，所述第一输出晶体管T5的第二极电连接所述第一输出端OUT1，所述第二输出晶体管T4的栅极电连接所述第二节点N2，所述第二输出晶体管T4的第二极电连接所述第二电位信号线VGH(所述第二子电位线VGH-2)，所述第二输出晶体管T4的第一极电连接所述第一输出端OUT1。
示例地，如图1、图9、图14和图16所示，所述第二输入子电路400包括第二输入晶体管T2和第三输入晶体管T3，所述第二输入晶体管T2的栅极电连接所述第一节点N1，所述第二输入晶体管T2的第一极电连接所述第二电位信号线VGH(所述第一子电位线VGH-1)，所述第二输入晶体管T2的第二极电连接所述第二节点N2，所述第三输入晶体管T3的栅极电连接所述第二时钟信号线CK(所述第三子时钟线CK-1)，所述第三输入晶体管T3的第一极电连接所述第一电位信号线VGL，所述第三输入晶体管T3的第二极电连接所述第二节点N2。
示例地，如图1、图9、图14和图16所示，所述第一维持子电路500包括第一维持晶体管T6，所述第一维持晶体管T6的栅极电连接所述第二节点N2，所述第一维持晶体管T6的第一极电连接所述第三节点N3，所述第一维持晶体管T6的第二极电连接所述第二电位信号线VGH(所述第一子电位线VGH-1)。
示例地，如图1、图9、图14和图16所示，所述第一复位子电路600包括第一复位晶体管T7，所述第一复位晶体管T7的栅极为所述第一复位控制端601K，所述第一复位晶体管T7的第一极电连接所述复位信号线PCX，所述第一复位晶体管T7的第二极电连接所述第三节点N3。
示例地，如图1、图9、图14和图16所示，所述第一输入子电路100还包括第四输入晶体管T8，所述第四输入晶体管T8的栅极电连接所述第一电位信号线VGL，所述第四输入晶体管T8的第一极电连接所述第一输入晶体管T1的第二极，所述第四输入晶体管T8的第二极电连接所述耦合电容C2的第一极板C2a；或/和，所述第一输出子电路300还包括第一电容C1，所述第一电容C1的第一极板C1a电连接所述第二输出晶体管T4的栅极，所述第一电容C1的第二极板C1b电连接所述第二输出晶体管T4的第二极。
在一些实施方式中，如图9、图14和图16所示，所述第一复位晶体管T7在所述基底上的正投影与所述复位信号线PCX在所述基底上的正投影至少部分重叠；
所述第一电容C1在所述基底上正投影与所述第四子时钟线CK-2在所述基底上的正投影、以及所述第二子时钟线CB-2在所述基底上的正投影均至少部分重叠；
在所述第一方向Y上，所述第一复位晶体管T7和所述第一电容C1位于所述耦合电容C2的同一侧；
所述第二子电位线(VGH-2)在所述基底上的正投影位于所述第一输出晶体管T5和所述第二输出晶体管T4远离所述耦合电容C2的一侧。
示例地，如图9、图14和图16所示，所述第一电容C1在所述基底上正投影与所述第四子时钟线CK-2在所述基底上的正投影、以及所述第二子时钟线CB-2在所述基底上的正投影均至少部分重叠；所述第一复位晶体管T7在所述基底上的正投影与所述复位信号线PCX在所述基底上的正投影至少部分重叠；通过此种设置，均可以减小栅极驱动电路单元1000或栅极驱动电路在版图或显示面板中需要占据的面积。
本公开还提供了一种显示装置，显示装置包括栅极驱动电路，所述栅极驱动电路包括上述中任一项所述的栅极驱动电路单元1000，或所述栅极驱动电路包括上述中任几项结合的所述栅极驱动电路单元1000。
本公开还提供了一种显示装置，显示装置显示基板2000，显示基板2000包括栅极驱动电路，所述栅极驱动电路包括上述中任一项所述的栅极驱动电路单元1000，或所述栅极驱动电路包括上述中任几项结合的所述栅极驱动电路单元1000。
示例地，显示装置可以是智能手机、笔记本电脑、电视、平板电脑或其他显示器，本公开一些实施例不作具体限定。
在本公开中，提供了一种栅极驱动电路单元、栅极驱动电路、显示基板的制造方法、显示基板及显示装置，所述第一输入子电路被构造为根据所述第一输入端的信号来控制所述第一节点的电压；所述第二输入子电路被构造为根据所述第二输入端的信号来控制所述第二节点的电压；所述耦合子电路至少被构造为根据所述第一节点的电压来控制所述第三节点的电压；所述第一输出子电路被构造为根据施加到所述第二节点和所述第三节点的电压将所述第三输入端的信号或所述第四输入端的信号传输至所述第一输出端。通过设置所述耦合子电路，使得可以根据所述第一节点的电压来控制第三节点的电压，使得所述第三节点的电信号更好的匹配显示或驱动需求，例如使得所述第三节点的高电位更加高，例如使得所述第三节点的低电位更加低，可以使得所述第一输出子电路中与所述第三节点电连接的薄膜晶体管打开充分或关闭完全，从而使得与所述第三节点电连接的薄膜晶体管打开时，所述第三输入端的信号可以更好的传输至所述第一输出端，从而使得与所述第三节点电连接的薄膜晶体管关闭时，所述第三输入端的信号可以更好的与所述第一输出端隔离，从而提高了所述栅极驱动电路单元输出信号的稳定性。
在本公开一些实施例中，所述栅极驱动电路单元包括所述第一输入子电路、所述第二输入子电路、所述耦合子电路、所述第一输出子电路，所述栅极驱动电路单元的结构简单，所述栅极驱动电路单元包括的薄膜晶体管和电容的数量较小，所述栅极驱动电路单元在版图或显示面板中需要占据的区域面积较小，即所述栅极驱动电路单元存在结构简单的效果，有利于所述显示面板的窄边框。
在本公开一些实施例中，提供的所述栅极驱动电路单元，同时具有结构简单和稳定输出满足显示需求的电信号的效果。
需要说明的是，上述各个实施例/示例中的技术特征可以相互结合而得到新的移位寄存器。
需要说明的是，在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详细描述的部分，可以参见其它实施例的相关描述。
以上实施例仅用以说明本公开的技术方案，而非对其限制；尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本公开各实施例技术方案的精神和范围。
尽管已描述了本说明书的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本说明书范围的所有变更和修改。
显然，本领域的技术人员可以对本说明书进行各种改动和变型而不脱离本说明书的精神和范围。这样，倘若本说明书的这些修改和变型属于本说明书权利要求及其等同技术的范围之内，则本说明书也意图包含这些改动和变型在内。

Claims (27)

  1. 一种栅极驱动电路单元，包括：
    第一输入子电路，被构造为根据第一输入端的信号来控制第一节点的电压；
    第二输入子电路，被构造为根据第二输入端的信号来控制第二节点的电压；
    耦合子电路，至少被构造为根据所述第一节点的电压来控制第三节点的电压；
    第一输出子电路，被构造为根据施加到所述第二节点和所述第三节点的电压将第三输入端的信号或第四输入端的信号传输至第一输出端。
  2. 根据权利要求1所述的栅极驱动电路单元，其中，满足如下条件中至少之一：
    所述第一输入端接收第一信号线的信号；
    所述第二输入端接收第一电位信号线的信号；
    所述第三输入端接收第一时钟信号线的信号，所述第四输入端接收第二电位信号线的信号。
  3. 根据权利要求2所述的栅极驱动电路单元，还包括第一维持子电路和第一复位子电路；
    所述第一输入子电路电连接所述第一信号线、第二时钟信号线和所述第一节点，所述第一输入子电路用于在所述第二时钟信号线的信号控制下，将所述第一信号线的信号输入至所述第一节点；
    所述第二输入子电路电连接所述第一电位信号线、所述第二时钟信号线、所述第二节点、所述第一节点和所述第二电位信号线，所述第二输入子电路用于在所述第一节点和所述第二时钟信号线的信号控制下，将所述第二电位信号线或所述第一电位信号线的信号传输至所述第二节点；
    所述第一维持子电路电连接所述第二节点、所述第三节点和所述第二电位信号线，所述第一维持子电路用于在所述第二节点的电位控制下将所述第二电位信号线的信号传输至所述第三节点；
    所述第一输出子电路电连接所述第一时钟信号线、所述第三节点、所述第二节点和所述第二电位信号线，所述第一输出子电路用于在所述第三节点和所述第二节点的电位控制下，将所述第一时钟信号线或所述第二电位信号线的信号传输至所述第一输出端；
    所述第一复位子电路电连接第一复位控制端、复位信号线和所述耦合子电路的一端，所述第一复位子电路用于在所述第一复位控制端的信号控制下，将所述复位信号线的电位传输至所述耦合子电路的一端。
  4. 根据权利要求3所述的栅极驱动电路单元，其中，所述第一输入子电路包括第一输入晶体管，所述第一输入晶体管的栅极电连接所述第二时钟信号线，所述第一输入晶体管的第一极电连接所述第一信号线，所述第一输入晶体管的第二极电连接所述第一节点；
    所述耦合子电路包括耦合电容，所述耦合电容的第一极板电连接所述第一节点，所述耦合电容的第二极板电连接所述第三节点；
    所述第一输出子电路包括第一输出晶体管和第二输出晶体管，所述第一输出晶体管的栅极电连接所述第三节点，所述第一输出晶体管的第一极电连接所述第一时钟信号线，所述第一输出晶体管的第二极电连接所述第一输出端，所述第二输出晶体管的栅极电连接所述第二节点，所述第二输出晶体管的第二极电连接所述第二电位信号线，所述第二输出晶体管的第一极电连接所述第一输出端。
  5. 根据权利要求4所述的栅极驱动电路单元，其中，所述第二输入子电路包括第二输入晶体管和第三输入晶体管，所述第二输入晶体管的栅极电连接所述第一节点，所述第二输入晶体管的第一极电连接所述第二电位信号线，所述第二输入晶体管的第二极电连接所述第二节点，所述第三输入晶体管的栅极电连接所述第二时钟信号线，所述第三输入晶体管的第一极电连接所述第一电位信号线，所述第三输入晶体管的第二极电连接所述第二节点；
    所述第一维持子电路包括第一维持晶体管，所述第一维持晶体管的栅极电连接所述第二节点，所述第一维持晶体管的第一极电连接所述第三节点，所述第一维持晶体管的第二极电连接所述第二电位信号线。
  6. 根据权利要求5所述的栅极驱动电路单元，其中，所述第一复位子电路包括第一复位晶体管，所述第一复位晶体管的栅极为所述第一复位控制端，所述第一复位晶体管的第一极电连接所述复位信号线，所述第一复位晶体管的第二极电连接所述第三节点。
  7. 根据权利要求6所述的栅极驱动电路单元，其中，所述第一复位控制端电连接所述第一信号线、栅极驱动电路中级联的上一级所述栅极驱动电路单元的所述第一节点、所述栅极驱动电路中级联的上一级所述栅极驱动电路单元的所述第三节点、以及所述栅极驱动电路中级联的上一级所述耦合电容的第一极板中任一者。
  8. 根据权利要求7所述的栅极驱动电路单元，其中，所述第一输入子电路还包括第四输入晶体管，所述第四输入晶体管的栅极电连接所述第一电位信号线，所述第四输入晶体管的第一极电连接所述第一输入晶体管的第二极，所述第四输入晶体管的第二极电连接所述耦合电容的第一极板；或/和
    所述第一输出子电路还包括第一电容，所述第一电容的第一极板电连接所述第二输出晶体管的栅极，所述第一电容的第二极板电连接所述第二输出晶体管的第二极。
  9. 根据权利要求3至8中任一项所述的栅极驱动电路单元，其中，所述第一信号线为起始信号线，在所述第一信号线输出第一个低电位的信号前，所述复位信号线的信号为高电位信号，且所述复位信号线的高电位大于所述第一信号线的高电位；
    在所述第一信号线输出第一个低电位的信号开始，所述复位信号线的信号为低电位信号。
  10. 根据权利要求3至8中任一项所述的栅极驱动电路单元，其中，所述栅极驱动电路单元还包括第二复位子电路和第二维持子电路中至少一者；
    所述第一复位子电路电连接所述耦合子电路与所述第三节点电连接的一端，所述第二复位子电路电连接第二复位控制端、所述复位信号线、以及所述耦合子电路与所述第一节点电连接的一端，所述第二复位子电路用于在所述第二复位控制端的信号控制下，将所述复位信号线的电位传输至所述耦合子电路与所述第一节点电连接的一端；
    所述第二维持子电路电连接所述第二节点、所述第二电位信号线、以及所述耦合子电路与所述第一节点电连接的一端，所述第二维持子电路用于在所述第二节点的电位控制下将所述第二电位信号线的信号传输至所述耦合子电路与所述第一节点电连接的一端。
  11. 根据权利要求10所述的栅极驱动电路单元，其中，所述第二复位子电路包括第二复位晶体管，所述第二复位晶体管的栅极为所述第二复位控制端，所述第二复位晶体管的第一极电连接所述复位信号线，所述第二复位晶体管的第二极电连接所述耦合子电路电连接所述第一节点的一端；
    所述第二维持子电路包括第二维持体管，所述第二维持体管的栅极电连接所述第二节点，所述第二维持体管的第一极电连接所述耦合子电路电连接所述第一节点的一端，所述第二维持体管的第二极电连接所述第二电位信号线。
  12. 根据权利要求1所述的栅极驱动电路单元，还包括：
    第二输出子电路，被构造为根据施加到所述第二节点和所述第三节点的电压将第五输入端或第六输入端的信号传输至第二输出端。
  13. 根据权利要求12所述的栅极驱动电路单元，其中，所述第五输入端接收第一时钟信号线的信号，所述第六输入端接收第二电位信号线的信号。
  14. 根据权利要求13所述的栅极驱动电路单元，其中，所述第五输入端接接收的所述第一时钟信号线与所述第三输入端接收的所述第一时钟信号线不同；
    所述第五输入端接接收的所述第一时钟信号线中的高电位，大于所述第三输入端接收的所述第一时钟信号线中的高电位；
    所述第五输入端接接收的所述第一时钟信号线中的低电位，小于所述第三输入端接收的所述第一时钟信号线中的低电位；
    所述第六输入端接收的所述第二电位信号线与所述第四输入端接收的所述第二电位信号线不同；
    所述第六输入端接收的所述第二电位信号线中的电位，大于所述第四输入端接收的所述第二电位信号线中的电位。
  15. 根据权利要求2至8中任一项所述的栅极驱动电路单元，其中，所述第一信号线中的信号为起始信号，所述第一电位信号线中的信号为低电位，所述第二电位信号线中的信号为高电位，所述栅极驱动电路单元中的薄膜晶体管均为P型。
  16. 一种栅极驱动电路，包括至少一个级联电路，每个级联电路包括多个依次级联的栅极驱动电路单元，所述栅极驱动电路单元为如权利要求1至15中任一项所述的栅极驱动电路单元。
  17. 一种显示基板的制造方法，包括：
    提供一基底；
    在所述基底上制造至少一个级联电路，每个级联电路包括多个依次级联的栅极驱动电路单元，所述栅极驱动电路单元为如权利要求1至15中任一项所述的栅极驱动电路单元。
  18. 一种显示基板，包括如权利要求1所述的栅极驱动电路单元。
  19. 根据权利要求18所述的显示基板，其中，所述耦合子电路包括耦合电容；
    所述第一输出子电路包括第一输出晶体管和第二输出晶体管；
    所述显示基板包括基底和设置于所述基底一侧的栅极金属层，所述栅极金属层包括所述耦合电容的第二极板和所述第一输出晶体管的栅极，且所述耦合电容的第二极板和所述第一输出晶体管的栅极直接相连。
  20. 根据权利要求19所述的显示基板，其中，所述第一输出子电路还包括第一电容，所述耦合电容和所述第一电容沿第一方向排布；
    所述栅极金属层还包括所述第一电容的第二极板和所述第二输出晶体管的栅极，且所述第一电容的第二极板和所述第二输出晶体管的栅极直接相连；
    在第二方向上，所述第一输出晶体管和所述第二输出晶体管位于所述耦合电容和所述第一电容的同一侧，所述第一方向与所述第二方向相交。
  21. 根据权利要求20所述的显示基板，其中，所述第二输入子电路包括第二输入晶体管和第三输入晶体管；
    所述显示基板还包括第一维持子电路和第一复位子电路，所述第一维持子电路包括第一维持晶体管；所述第一复位子电路包括第一复位晶体管；
    所述显示基板包括位于所述基底与所述栅极金属层之间的半导体层，所述半导体层包括一连续的第一半导体图案，所述第二输入晶体管的有源部、所述第一维持晶体管的有源部和所述第一复位晶体管的有源部由所述第一半导体图案形成。
  22. 根据权利要求21所述的显示基板，其中，所述第一半导体图案包括第一子半导体图案、第二子半导体图案和第三子半导体图案，所述第二子半导体图案连在所述第一子半导体图案和所述第三子半导体图案之间，所述第一子半导体图案的延伸方向与所述第三子半导体图案的延伸方向平行，所述第二子半导体图案的延伸方向为非直线延伸；
    所述第一子半导体图案包括所述第二输入晶体管的有源部，所述第二子半导体图案包括所述第一维持晶体管的有源部，所述第三子半导体图案包括所述第一复位晶体管的有源部。
  23. 根据权利要求22所述的显示基板，其中，所述第二输入晶体管的有源部的沟道延伸方向、所述第一维持晶体管的有源部的沟道延伸方向和所述第一复位晶体管的有源部的沟道延伸方向相互平行。
  24. 根据权利要求21所述的显示基板，其中，所述第一输入子电路包括第一输入晶体管；
    所述第一输入子电路还包括第四输入晶体管；
    在所述第二方向上，所述第一输入晶体管、所述第四输入晶体管、所述第二输入晶体管、所述第三输入晶体管、所述第一维持晶体管和所述第一复位晶体管均位于所述耦合电容和所述第一电容的一侧，所述第一输出晶体管和所述第二输出晶体管均位于所述耦合电容和所述第一电容的另一侧。
  25. 根据权利要求24所述的显示基板，其中，所述显示基板包括第一时钟信号线、第二时钟信号线、第一电位信号线、第二电位信号线和复位信号线；
    所述第一时钟信号线包括第一子时钟线和第二子时钟线，所述第一子时钟线和所述第二子时钟线中的信号相同；
    所述第二时钟信号线包括第三子时钟线和第四子时钟线，所述第三子时钟线和所述第四子时钟线中的信号相同；
    所述第二电位信号线包括第一子电位线和第二子电位线，所述第一子电位线和所述第二子电位线中的信号相同；
    所述第一子时钟线、所述第三子时钟线、所述第一子电位线、所述第一电位信号线、所述复位信号线、所述第四子时钟线、所述第二子时钟线和所述第二子电位线沿所述第二方向依次排布；
    所述耦合电容在所述基底上正投影与所述复位信号线在所述基底上的正投影、所述第四子时钟线在所述基底上的正投影、以及所述第二子时钟线在所述基底上的正投影均至少部分重叠。
  26. 根据权利要求25所述的显示基板，其中，所述第一复位晶体管在所述基底上的正投影与所述复位信号线在所述基底上的正投影至少部分重叠；
    所述第一电容在所述基底上正投影与所述第四子时钟线在所述基底上的正投影、以及所述第二子时钟线在所述基底上的正投影均至少部分重叠；
    在所述第一方向上，所述第一复位晶体管和所述第一电容位于所述耦合电容的同一侧；
    所述第二子电位线在所述基底上的正投影位于所述第一输出晶体管和所述第二输出晶体管远离所述耦合电容的一侧。
  27. 一种显示装置，包括栅极驱动电路，所述栅极驱动电路包括如权利要求1至15中任一项所述的栅极驱动电路单元。
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WO2022252092A1 (zh) * 2021-05-31 2022-12-08 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路和显示装置
CN113823213A (zh) * 2021-10-26 2021-12-21 京东方科技集团股份有限公司 栅极驱动电路、显示基板和显示装置
WO2023173259A1 (zh) * 2022-03-14 2023-09-21 京东方科技集团股份有限公司 移位寄存器单元及其驱动方法、栅极驱动电路及显示装置
CN118538142A (zh) * 2024-05-30 2024-08-23 京东方科技集团股份有限公司 栅极驱动电路单元及其电路、显示基板及其制造方法、显示装置

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