WO2025218405A1 - 显示基板及其制备方法、显示装置 - Google Patents

显示基板及其制备方法、显示装置

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Publication number
WO2025218405A1
WO2025218405A1 PCT/CN2025/082615 CN2025082615W WO2025218405A1 WO 2025218405 A1 WO2025218405 A1 WO 2025218405A1 CN 2025082615 W CN2025082615 W CN 2025082615W WO 2025218405 A1 WO2025218405 A1 WO 2025218405A1
Authority
WO
WIPO (PCT)
Prior art keywords
line
lines
sub
data
exemplary embodiment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2025/082615
Other languages
English (en)
French (fr)
Inventor
王梦奇
吴建鹏
于子阳
蒋志亮
胡明
邱海军
陶璇
张跳梅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025218405A1 publication Critical patent/WO2025218405A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • This article relates to but is not limited to the field of display technology, and specifically to a display substrate and a preparation method thereof, and a display device.
  • OLEDs Organic light-emitting diodes
  • QLEDs quantum-dot light-emitting diodes
  • advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost.
  • TFTs thin-film transistors
  • the present disclosure provides a display substrate, including a display area and a binding area arranged on one side of the display area, the display area including multiple circuit units forming multiple unit rows and multiple unit columns, at least one circuit unit including a pixel driving circuit, and the binding area including at least multiple data lead lines; the display area also includes multiple data signal lines and multiple data connection lines, the data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead lines through the data connection lines; at least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, the two horizontal sub-lines are arranged in different unit rows, and the two vertical sub-lines are arranged in different unit columns, and the first direction and the second direction intersect.
  • At least two horizontal sub-lines are provided in at least one unit row, and the two horizontal sub-lines connect different vertical sub-lines.
  • At least two vertical sub-lines are provided in at least one unit column, and the two vertical sub-lines connect different horizontal sub-lines.
  • an orthographic projection of the at least one horizontal sub-line on the display substrate at least partially overlaps with an orthographic projection of the at least one vertical sub-line on the display substrate.
  • the display area in a direction perpendicular to the display substrate, includes multiple conductive layers, the two horizontal sub-lines are arranged in the same conductive layer, the two vertical sub-lines are arranged in the same conductive layer, and the horizontal sub-lines and the vertical sub-lines are arranged in different conductive layers.
  • the multiple conductive layers include at least a first source-drain metal layer arranged on a substrate and a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, the horizontal sub-line is arranged in the first source-drain metal layer, and the vertical sub-line is arranged in the second source-drain metal layer.
  • the at least two horizontal sub-lines include at least a first horizontal sub-line and a second horizontal sub-line
  • the at least two vertical sub-lines include at least a first vertical sub-line and a second vertical sub-line
  • the data signal line is connected to the data lead-out line through the data connection line, including: the first end of the first vertical sub-line is connected to the data lead-out line, the second end of the first vertical sub-line extends in a direction away from the binding area and is connected to the first end of the first horizontal sub-line, the second end of the first horizontal sub-line extends in a direction close to the second vertical sub-line and is connected to the first end of the second vertical sub-line, the second end of the second vertical sub-line extends in a direction away from the binding area and is connected to the first end of the second horizontal sub-line, and the second end of the second horizontal sub-line extends in a direction close to the data signal line and is connected to the data signal line.
  • the display area further includes a plurality of first data connection blocks; in at least one circuit unit, the first data connection block is connected to the first end of the first horizontal sub-line, and the second end of the first vertical sub-line is connected to the first data connection block through a via; in at least another circuit unit, the first data connection block is connected to the first end of the second horizontal sub-line, and the second end of the second vertical sub-line is connected to the first data connection block through a via.
  • the display area further includes a plurality of data transfer bars, and in at least one circuit unit, the first end of the first horizontal sub-line is connected to the first data connection block through the data transfer bar; in at least another circuit unit, the first end of the second horizontal sub-line is connected to the first data connection block through the data transfer bar.
  • the first horizontal sub-line, the first data connection block and the data transfer bar are an interconnected integrated structure; in at least another circuit unit, the second horizontal sub-line, the first data connection block and the data transfer bar are an interconnected integrated structure.
  • the display area further includes a plurality of first dummy electrodes, and a position and a connection structure of at least one first dummy electrode in one circuit unit are the same as a position and a connection structure of at least one first data connection block in another circuit unit.
  • the first vertical sub-line is connected to at least one first dummy electrode through a via; in at least another circuit unit, the second vertical sub-line is connected to at least one first dummy electrode through a via.
  • the display area further includes a plurality of second data connection blocks; in at least one circuit unit, the second data connection block is connected to the second end of the first horizontal sub-line, and the first end of the second vertical sub-line is connected to the second data connection block through a via.
  • the display area further includes a plurality of second dummy electrodes, and a position and connection structure of at least one second dummy electrode in one circuit unit are identical to a position and connection structure of at least one second data connection block in another circuit unit.
  • the first vertical sub-line is connected to at least one second dummy electrode through a via; in at least another circuit unit, the second vertical sub-line is connected to at least one second dummy electrode through a via.
  • the present disclosure further provides a display device comprising the aforementioned display substrate.
  • the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a display area and a binding area disposed on one side of the display area, the display area comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit; the manufacturing method comprising:
  • a plurality of data signal lines and a plurality of data connection lines are formed in the display area, and a plurality of data lead-out lines are formed in the binding area, wherein the data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines through the data connection lines; at least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, wherein the two horizontal sub-lines are arranged in different unit rows, and the two vertical sub-lines are arranged in different unit columns, and the first direction and the second direction intersect.
  • FIG1 is a schematic structural diagram of a display device
  • FIG2 is a schematic structural diagram of a display substrate
  • FIG3 is a schematic diagram of a planar structure of a display area
  • FIG4 is a schematic diagram of a cross-sectional structure of a display area
  • FIG5 is an equivalent circuit diagram of a pixel driving circuit
  • FIG6 is a schematic diagram showing the structure of a data connection line in a display substrate
  • FIG8 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure.
  • FIGS. 10A and 10B are schematic diagrams of an embodiment of the present disclosure after forming a first conductive layer pattern
  • FIGS. 13A and 13B are schematic diagrams of an embodiment of the present disclosure after forming a third conductive layer pattern
  • FIG16 is a schematic diagram of an embodiment of the present disclosure after forming a first planar layer pattern
  • 17A and 17B are schematic diagrams of an embodiment of the present disclosure after forming a fifth conductive layer pattern
  • FIG17C is a schematic diagram of the connection between horizontal sub-lines and vertical sub-lines according to an exemplary embodiment of the present disclosure
  • FIG18 is a schematic diagram of an embodiment of the present disclosure after forming a second planar layer pattern
  • 19A and 19B are schematic diagrams of an embodiment of the present disclosure after forming an anode conductive layer pattern.
  • the scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such.
  • the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures.
  • the figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values shown in the figures.
  • ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.
  • orientation or positional relationships such as “middle,” “upper,” “lower,” “front,” “back,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside,” are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings.
  • This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure.
  • the positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.
  • the terms “mounted,” “connected,” and “connected” should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.
  • a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • the channel region refers to the region through which current primarily flows.
  • the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa.
  • the functions of “source electrode” and “drain electrode” may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, “source electrode” and “drain electrode” can be interchanged, and “source terminal” and “drain terminal” can be interchanged.
  • parallel refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°.
  • perpendicular refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced with “conductive film.”
  • insulating film may be replaced with “insulating layer.”
  • triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They may be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have some minor deformations due to tolerances, such as chamfers, rounded edges, and deformation.
  • the term "approximately” in this disclosure does not strictly define the boundaries, but allows for values within the range of process and measurement errors.
  • FIG1 is a schematic diagram of the structure of a display device.
  • the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array.
  • the timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver.
  • the data driver is respectively connected to a plurality of data signal lines (D1 to Dn).
  • the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm).
  • the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo).
  • the pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers.
  • At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit.
  • the circuit unit may include at least a pixel driving circuit, which is respectively connected to the scan signal lines, the light-emitting signal lines, and the data signal lines.
  • the light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit.
  • the timing controller may provide grayscale values and control signals suitable for the specifications of the data driver to the data driver, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver.
  • the data driver can generate data voltages to be supplied to data signal lines D1, D2, D3, ..., and Dn using grayscale values and control signals received from a timing controller. For example, the data driver can sample grayscale values using a clock signal and apply data voltages corresponding to the grayscale values to data signal lines D1 to Dn on a per-pixel basis, where n can be a natural number.
  • the scan driver can generate scan signals to be supplied to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, and the like from the timing controller. For example, the scan driver can sequentially supply scan signals having on-level pulses to scan signal lines S1 to Sm.
  • the scan driver can be configured as a shift register and can sequentially transmit scan start signals provided in the form of on-level pulses to the next-stage circuit under the control of a clock signal, where m can be a natural number.
  • the light driver can generate emission signals to be supplied to light signal lines E1, E2, E3, ..., and Eo by receiving clock signals, emission stop signals, and the like from the timing controller.
  • the light emitting driver may sequentially provide emission signals having off-level pulses to the light emitting signal lines E1 to Eo.
  • the light emitting driver may be configured as a shift register and may generate emission signals by sequentially transmitting emission stop signals provided in the form of off-level pulses to the next stage circuit under the control of a clock signal. o may be a natural number.
  • the pixel array may be provided on a display substrate.
  • FIG. 2 is a schematic diagram of the structure of a display substrate.
  • the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100.
  • the display area 100 may be a flat area including a plurality of sub-pixels that form a pixel array. The plurality of sub-pixels are configured to display dynamic images or still images.
  • the display area 100 may be referred to as an active area (AA).
  • the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.
  • the binding area 200 may include a lead area, a bending area, a driver chip area, and a binding pin area, which are sequentially arranged in a direction away from the display area.
  • the lead area is connected to the display area 100 and includes at least a data lead.
  • the bending area is connected to the lead area and may include at least a composite insulating layer provided with a groove, and the groove is configured to bend the binding area to the back of the display area.
  • the driver chip area may include an integrated circuit (IC), which is configured to be connected to a plurality of data lead lines.
  • the binding pin area may include a bonding pad, which is configured to be bonded and connected to an external flexible printed circuit (FPC).
  • FPC flexible printed circuit
  • the frame area 300 may include a circuit area, a power line area, a crack dam area, and a cutting area, which are sequentially arranged in a direction away from the display area 100.
  • the circuit area is connected to the display area 100 and may include at least a gate drive circuit, which is connected to the scanning signal line and the light-emitting signal line in the display area 100.
  • the power line area is connected to the circuit area and may include at least a frame power lead, which extends in a direction parallel to the edge of the display area and is connected to the cathode in the display area 100.
  • the crack dam area is connected to the power line area and may include at least a plurality of cracks provided on the composite insulating layer.
  • the cutting area is connected to the crack dam area and may include at least a cutting groove provided on the composite insulating layer. The cutting groove is configured so that after all the film layers of the display substrate are prepared, the cutting equipment can cut along the cutting groove respectively.
  • the lead line area in the binding area 200 and the power line area in the border area 300 can be provided with an isolation dam, and the isolation dam can extend in a direction parallel to the edge of the display area to form an annular structure surrounding the display area 100.
  • the edge of the display area is the edge of one side of the display area binding area or the border area.
  • FIG3 is a schematic diagram of a planar structure of a display area in a display substrate.
  • the display area may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4.
  • Each sub-pixel may include a circuit unit and a light-emitting unit.
  • the circuit unit may include at least a pixel driving circuit.
  • the pixel driving circuit is respectively connected to a scan signal line, a light-emitting signal line, and a data signal line.
  • the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit.
  • the light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel in which it is located.
  • the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.
  • the first subpixel P1 may be a red subpixel (R) that emits red light
  • the second subpixel P2 may be a blue subpixel (B) that emits blue light
  • the third subpixel P3 and the fourth subpixel P4 may be green subpixels (G) that emit green light.
  • the subpixels may be rectangular, diamond, pentagonal, or hexagonal in shape, and the four subpixels may be arranged in an RGBG pattern.
  • Figure 4 is a schematic cross-sectional view of the display region of a display substrate, illustrating the structure of four sub-pixels within the display region.
  • the display substrate may include a drive circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the drive circuit layer 102 facing away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 facing away from the substrate 101.
  • the display substrate may include other film layers, such as a touch-sensitive structure layer, which is not limited in this disclosure.
  • the substrate 101 may be a flexible substrate or a rigid substrate.
  • the driving circuit layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor.
  • the light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include a light-emitting device, which may include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer.
  • the organic light-emitting layer emits light of a corresponding color under the drive of the anode and the cathode.
  • the encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together.
  • the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, and the second encapsulation layer may be made of organic materials.
  • the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material/organic material/inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.
  • the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4.
  • the first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively;
  • the second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively;
  • the third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively;
  • the fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.
  • the first transistor T1 may be referred to as a first reset transistor, a gate electrode of the first transistor T1 is connected to the third scan signal line S3 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the third node N3 .
  • the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the fourth scan signal line S4 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .
  • the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1 , a first electrode of the third transistor T3 is connected to the second node N2 , and a second electrode of the third transistor T3 is connected to the third node N3 .
  • the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1 , a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2 .
  • the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.
  • the seventh transistor T7 may be referred to as a second reset transistor, a gate electrode of the seventh transistor T7 is connected to the second scan signal line S2 , a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2 , and a second electrode of the seventh transistor T7 is connected to the fourth node N4 .
  • the eighth transistor T8 may be referred to as a third reset transistor, a gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, a first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and a second electrode of the eighth transistor T8 is connected to the second node N2.
  • the first power line VDD is configured to provide a constant first voltage signal to the pixel driving circuit
  • the second power line VSS is configured to provide a constant second voltage signal to the light-emitting device, wherein the first voltage signal is a high-level signal and the second voltage signal is a low-level signal.
  • the first initial voltage signal, the second initial voltage signal, and the third initial voltage signal may be constant voltage signals, which are not limited in this disclosure.
  • the first transistor T1 to the eighth transistor T8 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the eighth transistor T8 may include P-type transistors and N-type transistors.
  • the first transistor T1 to the eighth transistor T8 may be low-temperature polysilicon transistors, or oxide transistors, or both low-temperature polysilicon transistors and metal oxide transistors.
  • the active layer of the low-temperature polysilicon transistor is made of low-temperature polysilicon (LTPS), and the active layer of the metal oxide transistor is made of metal oxide semiconductor (Oxide).
  • LTPS low-temperature polysilicon
  • Oxide metal oxide semiconductor
  • Integrating low-temperature polysilicon transistors and metal oxide transistors on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.
  • LTPO Low Temperature Polycrystalline + Oxide
  • the second transistor T2 may be a metal oxide transistor
  • the first transistor T1 and the third transistor T3 to the eighth transistor T8 may be low temperature polysilicon transistors.
  • Figure 6 is a schematic diagram of the structure of data connection lines in a display substrate.
  • the display area 100 may include multiple data signal lines 72, multiple first data connection lines 81, and multiple second data connection lines 82
  • the binding area 200 may include multiple data lead lines 80.
  • the multiple first data connection lines 81 may be in the form of straight lines or broken lines extending along a first direction X
  • the multiple data signal lines 72, multiple second data connection lines 82, and multiple data lead lines 80 may be in the form of straight lines or broken lines extending along a second direction Y.
  • At least one data signal line 72 is connected to multiple pixel drive circuits in a unit column, and the data signal line 72 is configured to provide data signals to the connected pixel drive circuit.
  • a plurality of first data connection lines 81 are arranged sequentially at set intervals in the second direction Y, and a plurality of second data connection lines 82 are arranged sequentially at set intervals in the first direction X, forming a structure arranged layer by layer outward.
  • the first end of the second data connection line 82 is connected to the data lead line 80 in the binding area 200, and the second end of the second data connection line 82 is connected to the first end of the first data connection line 81, and the second end of the first data connection line 81 is connected to the data signal line 72, so that the data signal line 72 in the display area is connected to the data lead line 80 in the binding area through the first data connection line 81 and the second data connection line 82, forming a FIP structure (also known as a FIAA structure).
  • the first data connection line 81 and the second data connection line 82 are collectively referred to as the data connection line.
  • the display area can be divided into a first area 110 and a second area 120 based on the presence or absence of the data connection lines.
  • the first area 110 can be the area where the first and second data connection lines 81 and 82 are provided (the dark area in FIG. 6 )
  • the second area 120 can be the area where the first and second data connection lines 81 and 82 are not provided (the area outside the dark area in FIG. 6 ).
  • the first area 110 can be referred to as a FIP area
  • the second area 120 can be referred to as a non-FIP area.
  • the display substrate includes a display area and a binding area disposed on one side of the display area.
  • the display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one of the circuit units including a pixel driving circuit.
  • the binding area includes at least a plurality of data lead lines.
  • the display area also includes a plurality of data signal lines, a plurality of first data connection lines, and a plurality of second data connection lines.
  • the data signal lines are configured to provide data signals to the pixel driving circuit.
  • the data lead lines are connected to the data signal lines via the first data connection lines and the second data connection lines.
  • At least one first data connection line includes at least two horizontal sub-lines extending along a first direction, the two horizontal sub-lines being disposed in different unit rows.
  • At least one second data connection line includes at least two vertical sub-lines extending along a second direction, the two vertical sub-lines being disposed in different unit columns, and the first direction and the second direction intersect.
  • At least two horizontal sub-lines are provided in at least one unit row, and the two horizontal sub-lines connect different vertical sub-lines.
  • At least two vertical sub-lines are provided in at least one unit column, and the two vertical sub-lines connect different horizontal sub-lines.
  • an orthographic projection of the at least one horizontal sub-line on the display substrate at least partially overlaps with an orthographic projection of the at least one vertical sub-line on the display substrate.
  • the two horizontal sub-lines are a first horizontal sub-line and a second horizontal sub-line
  • the two vertical sub-lines are a first vertical sub-line and a second vertical sub-line
  • the data signal line is connected to the data lead-out line through the data connection line, including: the first end of the first vertical sub-line is connected to the data lead-out line, the second end of the first vertical sub-line extends in a direction away from the binding area and is connected to the first end of the first horizontal sub-line, the second end of the first horizontal sub-line extends in a direction close to the second vertical sub-line and is connected to the first end of the second vertical sub-line, the second end of the second vertical sub-line extends in a direction away from the binding area and is connected to the first end of the second horizontal sub-line, and the second end of the second horizontal sub-line extends in a direction close to the data signal line and is connected to the data signal line.
  • Exemplary embodiments of the present disclosure provide a display substrate employing a fan-out in panel (FIP) structure.
  • the display substrate may include, within a plane parallel to the display substrate, a display area 100, a binding area 200 located on one side of the display area 100, and a border area 300 located on the other side of the display area 100.
  • the display substrate may include at least a driving structure layer disposed on a base and a light-emitting structure layer disposed on a side of the driving structure layer away from the base.
  • the driving structure layer of the display area 100 may include multiple circuit units, and the light-emitting structure layer of the display area 100 may include multiple light-emitting units.
  • the plurality of circuit units may form a plurality of unit rows and a plurality of unit columns, with the plurality of circuit units in each unit row being sequentially arranged along a first direction X, and the plurality of circuit units in each unit column being sequentially arranged along a second direction Y, thereby forming an array of circuit units arranged in an array, wherein the first direction X intersects the second direction Y.
  • the plurality of light-emitting units may form a plurality of light-emitting rows and a plurality of light-emitting columns, with the plurality of light-emitting units in each light-emitting row being sequentially arranged along a first direction X, and the plurality of light-emitting units in each light-emitting column being sequentially arranged along a second direction Y, thereby forming an array of light-emitting units arranged in an array.
  • At least one circuit unit may include at least a pixel driving circuit, and at least one circuit unit may include a light-emitting device, the light-emitting device being connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device being configured to emit light of corresponding brightness in response to a current output by the connected pixel driving circuit.
  • the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit
  • the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device.
  • the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.
  • FIG7 is a schematic diagram of the structure of a data connection line according to an exemplary embodiment of the present disclosure.
  • the display area 100 may include multiple data signal lines 72 and multiple data connection lines
  • the binding area 200 may include multiple data lead lines 80.
  • the multiple data signal lines 72 and the multiple data lead lines 80 may be in the shape of straight lines or zigzag lines extending along the second direction Y.
  • the multiple data connection lines may be in the shape of zigzag lines, including both straight lines extending along the first direction X and straight lines extending along the second direction Y.
  • the data signal lines 72 are configured to provide data signals to the connected pixel driving circuits, and the data signal lines 72 are connected to the data lead lines 80 via data connection lines.
  • the first ends of the multiple data connection lines are connected to the multiple data lead lines 80 in the binding area 200, and the second ends of the multiple data connection lines extend in a direction away from the binding area 200 and then connect to the multiple data signal lines 72.
  • the lead-out line area does not need to be set with a fan-shaped oblique line, thereby reducing the length of the second direction Y of the binding area, reducing the width of the lower frame, and increasing the screen-to-body ratio, which is conducive to achieving full-screen display.
  • the display area 100 may have a center line O, and the multiple data signal lines 72, the multiple data connection lines and the multiple data lead lines 80 may be mirror-symmetrical with respect to the center line O.
  • the center line O may be a straight line that bisects the multiple unit columns in the multiple display areas and extends along the second direction Y.
  • At least one data connection line may include at least two horizontal sub-lines and at least two vertical sub-lines
  • the shape of the horizontal sub-line may be a straight line or a folded line extending along the first direction X
  • the shape of the vertical sub-line may be a straight line or a folded line extending along the second direction Y
  • the two horizontal sub-lines may be arranged in different unit rows
  • the two vertical sub-lines may be arranged in different unit columns
  • the horizontal sub-lines and the vertical sub-lines are interconnected to form a folded line-shaped data connection line including the horizontal sub-lines and the vertical sub-lines.
  • At least two horizontal sub-lines may be provided in at least one unit row, and the two horizontal sub-lines may connect different vertical sub-lines.
  • At least two vertical sub-lines may be provided in at least one unit column, and the two vertical sub-lines may be connected to different horizontal sub-lines.
  • an orthographic projection of the at least one horizontal sub-line on the display substrate at least partially overlaps with an orthographic projection of the at least one vertical sub-line on the display substrate.
  • the two horizontal sub-lines may be a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2 extending along a first direction X
  • the two vertical sub-lines may be a first vertical sub-line 82-1 and a second vertical sub-line 82-2 extending along a second direction Y.
  • the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 are respectively arranged in different unit rows.
  • the first horizontal sub-line 81-1 may be arranged in a unit row close to the binding area
  • the second horizontal sub-line 81-2 may be arranged in a unit row on the side of the first horizontal sub-line 81-1 away from the binding area.
  • the first vertical sub-line 82-1 and the second vertical sub-line 82-2 are respectively arranged in different unit columns.
  • the first vertical sub-line 82-1 may be arranged in a unit column close to the center line O
  • the second vertical sub-line 82-2 may be arranged in a unit column on the side of the first vertical sub-line 82-1 away from the center line O.
  • the first horizontal sub-line 81-1 may be disposed on a side of the first vertical sub-line 82-1 away from the center line O
  • the second vertical sub-line 82-2 may be disposed on a side of the first horizontal sub-line 81-1 away from the center line O
  • the second horizontal sub-line 81-2 may be disposed on a side of the second vertical sub-line 82-2 away from the center line O.
  • the first horizontal sub-line 81-1 may be disposed on a side of the first vertical sub-line 82-1 away from the binding area
  • the second vertical sub-line 82-2 may be disposed on a side of the first horizontal sub-line 81-1 away from the binding area
  • the second horizontal sub-line 81-2 may be disposed on a side of the second vertical sub-line 82-2 away from the binding area.
  • the data signal line 72 is connected to the data lead-out line 80 through the data connection line, which may include: the first end of the first vertical sub-line 82-1 is connected to the data lead-out line 80, the second end of the first vertical sub-line 82-1 extends in a direction away from the binding area and is connected to the first end of the first horizontal sub-line 81-1, the second end of the first horizontal sub-line 81-1 extends in a direction away from the center line O (in a direction close to the second vertical sub-line 82-2) and is connected to the first end of the second vertical sub-line 82-2, the second end of the second vertical sub-line 82-2 extends in a direction away from the binding area and is connected to the first end of the second horizontal sub-line 81-2, and the second end of the second horizontal sub-line 81-2 extends in a direction away from the center line O (in a direction close to the data signal line 72) and is connected to the data signal line 72.
  • At least one horizontal sub-line may be connected to two vertical sub-lines.
  • a first end of the first horizontal sub-line 81-1 is connected to the first vertical sub-line 82-1
  • a second end of the first horizontal sub-line 81-1 is connected to the second vertical sub-line 82-2.
  • At least one vertical sub-line may be connected to two horizontal sub-lines.
  • a first end of the second vertical sub-line 82-2 is connected to the first horizontal sub-line 81-1
  • a second end of the second vertical sub-line 82-2 is connected to the second horizontal sub-line 81-2.
  • the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 can be referred to as a first data connection line 81
  • the first vertical sub-line 82-1 and the second vertical sub-line 82-2 can be referred to as a second data connection line 82
  • the data connection line may include a first data connection line 81 and a second data connection line 82
  • the first data connection line 81 may include a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2
  • the second data connection line 82 may include a first vertical sub-line 82-1 and a second vertical sub-line 82-2.
  • the number of data connection lines in the display area may be the same as the number of data signal lines, and each data signal line is connected to a corresponding lead line via a data connection line.
  • the number of data connection lines in the display area may be less than the number of data signal lines, and some of the data signal lines in the display area are connected to corresponding data lead lines via data connection lines, while other data signal lines are directly connected to the data lead lines. This disclosure is not limited herein.
  • the data lead-out line 80 may be directly connected to the data signal line 72 and the data connection line, or may be connected through a via hole, which is not limited in the present disclosure.
  • the display area can be divided into a first area 110 and a second area 120, the first area 110 can be an area where horizontal sub-lines and vertical sub-lines are set (the dark area in Figure 7), and the second area 120 can be an area where horizontal sub-lines and vertical sub-lines are not set (the area outside the dark area in Figure 7).
  • FIG8 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of region A in FIG7 .
  • the display region may include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit may include a pixel driving circuit, which is respectively connected to the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light emitting signal line 25, the first initial signal line 41, the second initial signal line 42, the third initial signal line 43, the first power line 71, and the data signal line 72.
  • the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, and the light-emitting signal line 25 are configured to respectively provide a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and a light-emitting control signal to the pixel driving circuit.
  • the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to respectively provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit.
  • the first power line 71 is configured to provide a first power signal to the pixel driving circuit.
  • the data signal line 72 is configured to provide a data signal to the pixel driving circuit.
  • the plurality of signal lines connected to the pixel driving circuit may be located within a corresponding circuit unit.
  • the shapes of the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the light-emitting signal line 25, the first initial signal line 41, the second initial signal line 42 and the third initial signal line 43 can be straight lines or broken lines with the main parts extending along the first direction X
  • the shapes of the first power line 71 and the data signal line 72 can be straight lines or broken lines with the main parts extending along the second direction Y.
  • a extends along direction B means that A can include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions.
  • a extends along direction B means “the main portion of A extends along direction B.”
  • the pixel driving circuit may include at least a storage capacitor and a plurality of transistors.
  • the storage capacitor may include a stacked first electrode plate and a second electrode plate.
  • the plurality of transistors may include a first transistor T1 serving as a first reset transistor, a second transistor T2 serving as a compensation transistor, a third transistor T3 serving as a drive transistor, a fourth transistor T4 serving as a data write transistor, a fifth transistor T5 serving as a first emission control transistor, a sixth transistor T6 serving as a second emission control transistor, a seventh transistor T7 serving as a second reset transistor, and an eighth transistor T8 serving as a third reset transistor.
  • the second transistor T2 may be a metal oxide transistor, and the first transistor T1, the third transistor T3, the third transistor T4, the fourth transistor T5, the fifth transistor T5, the fifth transistor T5, the sixth transistor T6, the sixth transistor T6, the seventh transistor T7, the seventh transistor T7, and the eighth transistor T8.
  • the gate electrode of the first transistor T1 is connected to the third scan signal line 23, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.
  • the gate electrode of the second transistor T2 is connected to the fourth scan signal line 24, and the first electrode of the second transistor T2 is connected to the first plate of the storage capacitor (which is also the gate electrode of the third transistor T3).
  • the first electrode of the third transistor T3 is respectively connected to the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8.
  • the gate electrode of the fourth transistor T4 is connected to the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected to the data signal line 72.
  • the gate electrode of the fifth transistor T5 is connected to the light emission signal line 25, and the first electrode of the fifth transistor T5 is connected to the first power supply line 71.
  • the gate electrode of the sixth transistor T6 is connected to the light emission signal line 25, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7.
  • the gate electrode of the seventh transistor T7 is connected to the second scanning signal line 22, and the first electrode of the seventh transistor T7 is connected to the second initial signal line 42.
  • the gate electrode of the eighth transistor T8 is connected to the second scanning signal line 22, and the first electrode of the eighth transistor T8 is connected to the third initial signal line 43.
  • the fourth scan signal line 24 may be disposed on a side of the storage capacitor (third transistor T3) opposite to the second direction Y, the first scan signal line 21 may be disposed on a side of the fourth scan signal line 24 away from the storage capacitor, the third scan signal line 23 and the second initial signal line 42 may be disposed on a side of the first scan signal line 21 away from the storage capacitor, and the first initial signal line 41 may be disposed on a side of the third scan signal line 23 away from the storage capacitor.
  • the light-emitting signal line 25 may be disposed on a side of the storage capacitor in the second direction Y, and the second scan signal line 22 and the third initial signal line 43 may be disposed on a side of the light-emitting signal line 25 away from the storage capacitor.
  • the orthographic projection of the second initial signal line 42 on the substrate at least partially overlaps with the orthographic projection of the third scan signal line 23 on the substrate, and the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second scan signal line 22 on the substrate.
  • At least one circuit unit may further include a first initial connection line 61.
  • the first initial connection line 61 may be in the shape of a straight line or a broken line, with a main portion extending along the second direction Y.
  • the first initial connection line 61 is connected to the first initial signal line 41.
  • the first initial signal line 41 and the first initial connection line 61 form a meshed connection structure for transmitting the first initial signal.
  • At least one circuit unit may further include a second initial connection line 62.
  • the second initial connection line 62 may be in the shape of a straight line or a broken line, with a main portion extending along the second direction Y.
  • the second initial connection line 62 is connected to the second initial signal line 42.
  • the second initial signal line 42 and the second initial connection line 62 form a meshed connection structure for transmitting the second initial signal.
  • the display area may further include a plurality of data connection lines, at least one of which may include a first horizontal sub-line 81-1, a second horizontal sub-line 81-2, a first vertical sub-line 82-1, and a second vertical sub-line 82-2.
  • the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 may be in the shape of a straight line or a broken line extending along the first direction X.
  • the first horizontal sub-line 81-1 may be arranged in the M+5th unit row, and the second horizontal sub-line 81-2 may be arranged in the Mth unit row.
  • the first vertical sub-line 82-1 and the second vertical sub-line 82-2 may be in the shape of a straight line or a broken line extending along the second direction Y.
  • the first vertical sub-line 82-1 may be arranged between the N+10th unit column and the N+11th unit column, and the second vertical sub-line 82-2 may be arranged between the Nth unit column and the N+1th unit column.
  • the first end of the first vertical sub-line 82-1 is connected to the data lead-out line of the binding area
  • the second end of the first vertical sub-line 82-1 extends in the opposite direction of the second direction Y (towards the direction close to the first horizontal sub-line 81-1), and is connected to the first end of the first horizontal sub-line 81-1
  • the second end of the first horizontal sub-line 81-1 extends in the opposite direction of the first direction X (towards the direction close to the second vertical sub-line 82-2)
  • the first end of the second vertical sub-line 82-2 extends in the opposite direction of the second direction Y (towards the direction close to the second horizontal sub-line 81-2)
  • the second end of the second horizontal sub-line 81-2 extends in the opposite direction of the first direction X (towards the direction close to the data signal line 72) and is connected to the data signal
  • At least one circuit unit may further include a data transfer bar 83 and a first data connection block 84.
  • the data transfer bar 83 may be in the shape of a bar extending along the second direction Y, and the first data connection block 84 may be in the shape of a block (e.g., a rectangle).
  • the first end of the data transfer bar 83 is connected to the first horizontal sub-line 81-1 or the second horizontal sub-line 81-2, and the second end of the data transfer bar 83 is connected to the first data connection block 84.
  • the first data connection block 84 is configured to connect to the first vertical sub-line 82-1 or the second vertical sub-line 82-2.
  • the first data connection block 84 is connected to the second horizontal sub-line 81-2 via the data transfer bar 83, and the second end of the second vertical sub-line 82-2 is connected to the first data connection block 84, thereby connecting the second end of the second vertical sub-line 82-2 to the first end of the second horizontal sub-line 81-2.
  • the first data connection block 84 is connected to the first horizontal sub-line 81-1 through the data transfer bar 83, and the second end of the first vertical sub-line 82-1 is connected to the first data connection block 84, realizing the connection between the second end of the first vertical sub-line 82-1 and the first end of the first horizontal sub-line 81-1.
  • At least one circuit unit may further include a second data connection block 85.
  • the second data connection block 85 may be block-shaped (e.g., rectangular) and connected to the second end of the first horizontal sub-line 81-1.
  • the second data connection block 85 is configured to connect to the first end of the second vertical sub-line 82-2.
  • the second data connection block 85 is connected to the second end of the first horizontal sub-line 81-1, and the first end of the second vertical sub-line 82-2 is connected to the second data connection block 85, thereby connecting the second end of the first horizontal sub-line 81-1 to the first end of the second vertical sub-line 82-2.
  • At least one circuit unit may further include a first dummy electrode 86.
  • the first dummy electrode 86 may be block-shaped (e.g., rectangular) and configured to connect to the vertical sub-line.
  • the position and connection structure of the first dummy electrode 86 in one circuit unit may be substantially the same as the position and connection structure of the first data connection block 84 in another circuit unit, except that the first dummy electrode 86 is isolated.
  • At least one circuit unit may further include a second dummy electrode 87.
  • the second dummy electrode 87 may be block-shaped (e.g., rectangular) and configured to be connected to the vertical sub-line.
  • the position and connection structure of the second dummy electrode 87 in one circuit unit may be substantially the same as the position and connection structure of the second data connection block 85 in another circuit unit, except that the second dummy electrode 87 is isolated.
  • the driving structure layer of the display area may include multiple conductive layers, the horizontal sub-lines may be arranged in the same conductive layer, the vertical sub-lines may be arranged in the same conductive layer, and the horizontal sub-lines and the vertical sub-lines may be arranged in different conductive layers.
  • the multiple conductive layers may include at least a first source-drain metal layer (SD1) arranged on a substrate and a second source-drain metal layer (SD2) arranged on a side of the first source-drain metal layer away from the substrate, the horizontal sub-line may be arranged in the first source-drain metal layer, and the vertical sub-line may be arranged in the second source-drain metal layer.
  • SD1 first source-drain metal layer
  • SD2 second source-drain metal layer
  • the first data connection block 84 , the second data connection block 85 , the first dummy electrode 86 , and the second dummy electrode 87 may be disposed in the first source-drain metal layer.
  • the following is an illustrative explanation of the preparation process of the display substrate.
  • the "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials.
  • Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition
  • coating can be carried out by any one or more of spraying, spin coating, and inkjet printing
  • etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this.
  • Thin film refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film” does not require a patterning process during the entire production process, the “thin film” can also be called a “layer”. If the "thin film” requires a patterning process during the entire production process, it is called a “thin film” before the patterning process and a “layer” after the patterning process. The “layer” after the patterning process contains at least one "pattern”.
  • a and B are disposed in the same layer means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate.
  • the orthographic projection of B is within the range of the orthographic projection of A” or "the orthographic projection of A contains the orthographic projection of B” means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.
  • the preparation process of the display substrate may include the following operations.
  • Forming a first semiconductor layer pattern may include sequentially depositing a first insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a first insulating layer disposed on the substrate, and a first semiconductor layer pattern disposed on the first insulating layer, as shown in FIG. 9 .
  • the first semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1, the third active layer 13 of the third transistor T3 to the eighth active layer 18 of the eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integrated structure connected to each other, and the first active layer 11 and the eighth active layer 18 are separately provided.
  • the first active layer 11 and the sixth active layer 16 may be located on one side of the third active layer 13 in the present circuit unit, and the fourth active layer 14 and the fifth active layer 15 may be located on the other side of the third active layer 13 in the present circuit unit.
  • the first active layer 11 and the fourth active layer 14 may be located on a side of the third active layer 13 in the present circuit unit opposite to the second direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 may be located on one side of the third active layer 13 in the present circuit unit in the second direction Y.
  • the third active layer 13 may have an ⁇ shape
  • the fourth active layer 14 and the sixth active layer 16 may have an L shape
  • the first active layer 11, the fifth active layer 15, the seventh active layer 17, and the eighth active layer 18 may have an I shape.
  • the first active layer 11 and the third to eighth active layers 13 to 18 may each include a first region, a second region, and a channel region located between the first and second regions.
  • the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be interconnected, and the first region 13-1 of the third active layer may serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer.
  • the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer may be interconnected, and the second region 13-2 of the third active layer may serve as the first region 16-1 of the sixth active layer.
  • the second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be interconnected, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer.
  • the first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer may be separately provided.
  • the first regions 15-1 of the fifth active layers of two adjacent circuit cells may be interconnected, and the fifth active layers of the two circuit cells may be interconnected as an integrated structure.
  • the fifth active layer of the Nth cell column and the fifth active layer of the N+1th cell column may be interconnected as an integrated structure
  • the fifth active layer of the N+2th cell column and the fifth active layer of the N+3th cell column may be interconnected as an integrated structure
  • the fifth active layer of the N+4th cell column and the fifth active layer of the N+5th cell column may be interconnected as an integrated structure
  • the fifth active layer of the N+6th cell column and the fifth active layer of the N+7th cell column may be interconnected as an integrated structure
  • the fifth active layer of the N+8th cell column and the fifth active layer of the N+9th cell column may be interconnected as an integrated structure
  • the fifth active layer of the N+10th cell column and the fifth active layer of the N+11th cell column may be interconnected as an integrated structure
  • the first region of the fifth active layer in each circuit unit is configured to be connected to the first power line formed subsequently, by forming the fifth active layers of adjacent circuit units into an integrated structure connected to each other, it can be ensured that the first electrodes of the fifth transistors T5 of adjacent circuit units have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.
  • the first semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary.
  • the first semiconductor layer of the Nth cell column and the first semiconductor layer of the N+1th cell column may be mirror-symmetrical with respect to a column boundary
  • the first semiconductor layer of the N+1th cell column and the first semiconductor layer of the N+2th cell column may be mirror-symmetrical with respect to a column boundary.
  • the shapes of the first semiconductor layers in multiple cell rows may be substantially the same.
  • the first semiconductor layer may be made of polycrystalline silicon (p-Si), i.e., the first transistor, the third transistor, the seventh transistor, and the like are LTPS transistors.
  • patterning the first semiconductor film through a patterning process may include: first forming an amorphous silicon (a-Si) film on the first insulating film, performing a dehydrogenation treatment on the amorphous silicon film, and then crystallizing the dehydrogenated amorphous silicon film to form a polycrystalline silicon film. Subsequently, patterning the polycrystalline silicon film to form a first semiconductor layer pattern.
  • forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on the substrate having the aforementioned pattern formed thereon, patterning the first conductive film through a patterning process to form a second insulating layer covering the first semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, as shown in FIG10A and FIG10B , where FIG10B is a plan view schematic diagram of the first conductive layer in FIG10A .
  • the first conductive layer may be referred to as a first gate metal (GATE1) layer.
  • the first conductive layer pattern of each circuit unit includes at least a first scan signal line 21 , a second scan signal line 22 , a third scan signal line 23 , a light emitting signal line 25 and a first plate 31 of a storage capacitor.
  • the first electrode plate 31 may be rectangular, with chamfered corners.
  • the orthographic projection of the first electrode plate 31 on the substrate at least partially overlaps the orthographic projection of the third active layer of the third transistor T3 on the substrate.
  • the first electrode plate 31 may serve as both the lower plate of the storage capacitor and the gate electrode of the third transistor T3.
  • the shape of the first scanning signal line 21 can be a straight line or a broken line with the main portion extending along the first direction X.
  • the first scanning signal line 21 can be located on the side of the first electrode 31 in the opposite direction of the second direction Y.
  • the area where the first scanning signal line 21 overlaps with the fourth active layer can serve as the gate electrode of the fourth transistor T4.
  • the shape of the second scanning signal line 22 can be a straight line or a broken line with the main portion extending along the first direction X.
  • the second scanning signal line 22 can be located on one side of the first electrode 31 in the second direction Y.
  • the area where the second scanning signal line 22 overlaps with the seventh active layer can serve as the gate electrode of the seventh transistor T7, and the area where the second scanning signal line 22 overlaps with the eighth active layer can serve as the gate electrode of the eighth transistor T8.
  • the shape of the third scan signal line 23 can be a straight line or a broken line with the main portion extending along the first direction X.
  • the third scan signal line 23 can be located on a side of the first scan signal line 21 away from the first electrode plate 31, and the area where the third scan signal line 23 overlaps with the first active layer can serve as the gate electrode of the first transistor T1.
  • the shape of the light-emitting signal line 25 can be a straight line or a broken line with the main portion extending along the first direction X.
  • the light-emitting signal line 25 can be located between the second scanning signal line 22 and the first electrode 31.
  • the area where the light-emitting signal line 25 overlaps with the fifth active layer can serve as the gate electrode of the fifth transistor T5
  • the area where the light-emitting signal line 25 overlaps with the sixth active layer can serve as the gate electrode of the sixth transistor T6.
  • the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23 and the light-emitting signal line 25 can be designed with non-equal widths, and the width is the dimension in the second direction Y, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines.
  • the present disclosure does not limit this.
  • the first scan signal line 21, the second scan signal line 22, the third scan signal line 23 and the light emitting signal line 25 may include an overlapping area with the first semiconductor layer and an area not overlapping with the first semiconductor layer, and the width of the signal line in the area overlapping with the first semiconductor layer may be greater than the width of the signal line in the area not overlapping with the first semiconductor layer.
  • the first conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary.
  • the first conductive layer of the Nth cell column and the first conductive layer of the N+1th cell column may be mirror-symmetric with respect to a column boundary
  • the first conductive layer of the N+1th cell column and the first conductive layer of the N+2th cell column may be mirror-symmetric with respect to a column boundary.
  • the shapes of the first conductive layers in multiple cell rows may be substantially the same.
  • the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer.
  • the first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of the first transistor T1 and the third transistor T3 to the eighth transistor T8 are all conductorized.
  • forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate having the aforementioned pattern formed thereon, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, as shown in FIG11A and FIG11B , where FIG11B is a plan view schematic diagram of the second conductive layer in FIG11A .
  • the second conductive layer may be referred to as a second gate metal (GATE2) layer.
  • the second conductive layer pattern of each circuit unit includes at least a second plate 32 of a storage capacitor, a shielding line 35 , and a first initial signal line 41 .
  • the outline of the second electrode plate 32 can be rectangular, and the corners of the rectangle can be chamfered.
  • the orthographic projection of the second electrode plate 32 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 31 on the substrate.
  • the second electrode plate 32 can serve as the upper plate of the storage capacitor, and the first electrode plate 31 and the second electrode plate 32 constitute the storage capacitor of the pixel driving circuit.
  • the second electrode plate 32 is provided with an opening 33.
  • the opening 33 can be rectangular and located in the middle of the second electrode plate 32, forming an annular structure.
  • the opening 33 exposes the third insulating layer covering the first electrode plate 31, and the orthographic projection of the first electrode plate 31 on the substrate includes the orthographic projection of the opening 33 on the substrate.
  • the opening 33 is configured to accommodate a thirteenth via hole to be formed later.
  • the thirteenth via hole is located within the opening 33 and exposes the first electrode plate 31, allowing a first connecting electrode to be formed later to connect to the first electrode plate 31.
  • a plate connecting bar 34 is provided on the second electrode plate 32.
  • the plate connecting bar 34 may be in the shape of a bar extending along the first direction X and may be provided on one side of the second electrode plate 32 in the first direction X or on a side opposite to the first direction X.
  • a first end of the plate connecting bar 34 is connected to the second electrode plate 32 in the current circuit unit, and a second end of the plate connecting bar 34 is connected to the second electrode plate 32 in an adjacent circuit unit in the first direction X or in the opposite direction to the first direction X.
  • the second plates 32 and plate connecting bars 34 of two adjacent circuit cells in a cell row are interconnected as an integrated structure. Since the second plates 32 in each circuit cell are connected to a subsequently formed first power line, by forming the second plates 32 of adjacent circuit cells into an integrated structure, the integrated second plates can be reused as power signal lines, ensuring that the second plates of adjacent circuit cells have the same potential. This improves panel uniformity, prevents display defects on the display substrate, and ensures the display quality of the display substrate.
  • the shape of the shielding line 35 can be a straight line or a broken line with the main part extending along the first direction X, and can be located between the first scanning signal line 21 and the second electrode 32.
  • the shielding line 35 is configured as a shielding layer of the second transistor T2, shielding the channel region of the second transistor T2, ensuring the electrical performance of the oxide second transistor T2, and is configured as the bottom gate electrode of the second transistor T2.
  • the shielding lines 35 may be designed with unequal widths, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines.
  • the first initial signal line 41 may be in the shape of a straight line or a zigzag line, with the main portion extending along the first direction X.
  • the first initial signal line 41 may be located on a side of the third scan signal line 23 away from the second electrode plate 32.
  • a first initial connection block 41-1 may be provided on the first initial signal line 41 of each circuit unit.
  • the first initial connection block 41-1 may be in the shape of a block (e.g., a rectangle) and connected to the first initial signal line 41.
  • the first initial connection block 41-1 is configured to be connected to the first region of the first active layer via a subsequently formed seventh connection electrode.
  • the first initial connection blocks 41-1 of some adjacent circuit cells in the first direction X may be interconnected to form an interconnected integral structure, such that some adjacent circuit cells share the same first initial connection block 41-1.
  • the first initial connection block 41-1 of the N+1th cell column and the first initial connection block 41-1 of the N+2th cell column are interconnected as an integral structure.
  • the first initial connection block 41-1 of the N+3th cell column and the first initial connection block 41-1 of the N+4th cell column are interconnected as an integral structure.
  • the second conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary.
  • the second conductive layer of the Nth cell column and the second conductive layer of the N+1th cell column may be mirror-symmetric with respect to a column boundary
  • the second conductive layer of the N+1th cell column and the second conductive layer of the N+2th cell column may be mirror-symmetric with respect to a column boundary.
  • the shapes of the second conductive layers in multiple cell rows may be substantially the same.
  • forming the second semiconductor layer pattern may include: sequentially depositing a fourth insulating film and a second semiconductor film on the substrate having the aforementioned pattern formed thereon, patterning the second semiconductor film through a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIG12A and FIG12B , where FIG12B is a plan view schematic diagram of the second semiconductor layer in FIG12A .
  • the second semiconductor layer pattern of each circuit unit includes at least a second active layer 12 of a second transistor T2 .
  • the second active layer 12 may be shaped like an “L”, and an orthographic projection of the second active layer 12 on the substrate at least partially overlaps an orthographic projection of the shielding line 35 on the substrate.
  • the first region 12 - 1 of the second active layer may be located on a side of the shielding line 35 away from the second electrode plate 32
  • the second region 12 - 2 of the second active layer may be located on a side of the shielding line 35 close to the second electrode plate 32 .
  • the second semiconductor layers of adjacent cell columns may be mirror-symmetrical with respect to a column boundary.
  • the second semiconductor layer of the Nth cell column and the second semiconductor layer of the N+1th cell column may be mirror-symmetrical with respect to a column boundary
  • the second semiconductor layer of the N+1th cell column and the second semiconductor layer of the N+2th cell column may be mirror-symmetrical with respect to a column boundary.
  • the shapes of the second semiconductor layers in multiple cell rows may be substantially the same.
  • the second semiconductor layer may be made of oxide, that is, the second transistor T2 is an oxide transistor.
  • the second semiconductor thin film may be made of indium gallium zinc oxide (IGZO), which has higher electron mobility than amorphous silicon.
  • forming the third conductive layer pattern may include: sequentially depositing a fifth insulating film and a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer, and a third conductive layer pattern disposed on the fifth insulating layer, as shown in FIG13A and FIG13B , where FIG13B is a plan view schematic diagram of the third conductive layer in FIG13A .
  • the second conductive layer may be referred to as a third gate metal (GATE3) layer.
  • the third conductive layer pattern of each circuit unit includes at least a fourth scan signal line 24 , a second preliminary signal line 42 , and a third preliminary signal line 43 .
  • the shape of the fourth scan signal line 24 can be a straight line or a broken line with the main portion extending along the first direction X.
  • the fourth scan signal line 24 can be located between the first scan signal line 21 and the second electrode plate 32.
  • the area where the fourth scan signal line 24 overlaps with the second active layer can serve as the gate electrode of the second transistor T2.
  • the orthographic projection of the fourth scan signal line 24 on the substrate at least partially overlaps with the orthographic projection of the shielding line 35 on the substrate, and the fourth scan signal line 24 and the shielding line 35 can be connected to the same signal source, so that the shielding line 35 can serve as the bottom gate electrode of the second transistor T2, and the fourth scan signal line 24 can serve as the top gate electrode of the second transistor T2, forming a second transistor T2 with a top-gate and bottom-gate structure.
  • the shape of the second initial signal line 42 can be a straight line or a broken line with the main part extending along the first direction X.
  • the second initial signal line 42 can be located on the side of the first scanning signal line 21 away from the second electrode plate 32.
  • a second initial connection block 42-1 can be provided on the second initial signal line 42 of each circuit unit.
  • the shape of the second initial connection block 42-1 can be block-shaped (such as a rectangle) and is connected to the second initial signal line 42.
  • the second initial connection block 42-1 is configured to be connected to the first area of the seventh active layer through the subsequently formed eighth connection electrode.
  • the positive projection of the second initial signal line 42 on the substrate at least partially overlaps with the positive projection of the third scanning signal line 23 on the substrate.
  • the second initial signal line 42 transmitting a constant voltage can shield the influence of the third scanning signal line 23 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.
  • the shape of the third initial signal line 43 can be a straight line or a broken line with the main part extending along the first direction X.
  • the third initial signal line 43 can be located between the second electrode plate 32 and the first initial signal line 41.
  • a third initial connection block 43-1 can be provided on the third initial signal line 43 of each circuit unit.
  • the shape of the third initial connection block 43-1 can be block-shaped (such as a rectangle) and is connected to the third initial signal line 43.
  • the third initial connection block 43-1 is configured to be connected to the first region of the eighth active layer through a ninth connection electrode formed subsequently.
  • the third initial connection blocks 43-1 of some adjacent circuit cells in the first direction X may be interconnected to form an interconnected integral structure, such that some adjacent circuit cells share the same third initial connection block 43-1.
  • the third initial connection block 43-1 of the Nth cell column and the third initial connection block 43-1 of the N+1th cell column are interconnected as an integral structure.
  • the third initial connection block 43-1 of the N+2th cell column and the third initial connection block 43-1 of the N+3th cell column are interconnected as an integral structure.
  • the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line 22 on the substrate.
  • the third initial signal line 43 transmitting a constant voltage can shield the influence of the second scanning signal line 22 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.
  • the third conductive layers of adjacent cell columns may be mirror-symmetric with respect to a column boundary.
  • the third conductive layer of the Nth cell column and the third conductive layer of the N+1th cell column may be mirror-symmetric with respect to a column boundary
  • the third conductive layer of the N+1th cell column and the third conductive layer of the N+2th cell column may be mirror-symmetric with respect to a column boundary.
  • the shapes of the third conductive layers in multiple cell rows may be substantially the same.
  • Forming a sixth insulating layer pattern may include: depositing a sixth insulating film on the substrate having the aforementioned pattern formed thereon, patterning the fifth insulating film using a patterning process to form a sixth insulating layer covering the third conductive layer, wherein the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 14 .
  • the multiple vias of each circuit unit include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16 and a seventeenth via V17.
  • the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second region of the first active layer, and the second via hole V2 is configured to connect a subsequently formed second connecting electrode to the second region of the first active layer through the via hole.
  • the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the third via hole V3 are etched away to expose the surface of the first region of the second active layer, and the third via hole V3 is configured to connect a subsequently formed first connecting electrode to the first region of the second active layer through the via hole.
  • the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer in the fourth via hole V4 are etched away to expose the surface of the second region of the second active layer, and the fourth via hole V4 is configured to connect a subsequently formed second connecting electrode to the second region of the second active layer through the via hole.
  • the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the first area of the third active layer (also the second area of the fourth active layer and the second area of the fifth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the first area of the third active layer (also the second area of the fourth active layer and the second area of the fifth active layer), and the fifth via hole V5 is configured to connect the subsequently formed fifth connecting electrode to the first area of the third active layer (also the second area of the fourth active layer and the second area of the fifth active layer) through the via hole.
  • the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the second area of the third active layer (also the first area of the sixth active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the second area of the third active layer (also the first area of the sixth active layer), and the sixth via hole V6 is configured to connect the subsequently formed second connecting electrode to the second area of the third active layer (also the first area of the sixth active layer) through the via hole.
  • the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the first area of the fourth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the seventh via hole V7 are etched away to expose the surface of the first area of the fourth active layer, and the seventh via hole V7 is configured to connect a subsequently formed third connecting electrode to the first area of the fourth active layer through the via hole.
  • the orthographic projection of the eighth via V8 on the substrate is located within the orthographic projection of the first region of the fifth active layer on the substrate.
  • the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the eighth via V8 are etched away, exposing the surface of the first region of the fifth active layer.
  • the eighth via V8 is configured to connect a subsequently formed fourth connection electrode to the first region of the fifth active layer through the via.
  • some of the adjacent circuit cells can share one eighth via V8.
  • the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second area of the sixth active layer (also the second area of the seventh active layer) on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the ninth via hole V9 are etched away to expose the surface of the second area of the sixth active layer (also the second area of the seventh active layer), and the ninth via hole V9 is configured to connect the subsequently formed sixth connecting electrode to the second area of the sixth active layer (also the second area of the seventh active layer) through the via hole.
  • the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via hole V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via hole V10 is configured to connect the subsequently formed eighth connecting electrode to the first region of the seventh active layer through the via hole.
  • the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the eleventh via hole V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via hole V11 is configured to connect a subsequently formed ninth connecting electrode to the first region of the eighth active layer through the via hole.
  • the orthographic projection of the twelfth via hole V12 on the substrate is located within the range of the orthographic projection of the second region of the eighth active layer on the substrate, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer in the twelfth via hole V12 are etched away to expose the surface of the second region of the eighth active layer.
  • the twelfth via hole V12 is configured to connect the subsequently formed fifth connecting electrode to the second region of the eighth active layer through the via hole.
  • the orthographic projection of the thirteenth via hole V13 on the substrate is located within the range of the orthographic projection of the opening 33 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer in the thirteenth via hole V13 are etched away to expose the surface of the first electrode 31, and the thirteenth via hole V13 is configured to connect the subsequently formed first connecting electrode to the first electrode 31 through the via hole.
  • the orthographic projection of the fourteenth via hole V14 on the substrate is located within the orthographic projection of the plate connecting bar 34 of the second electrode plate 32 on the substrate.
  • the sixth insulating layer, the fifth insulating layer, and the fourth insulating layer within the fourteenth via hole V14 are etched away, exposing the surface of the plate connecting bar 34.
  • the fourteenth via hole V14 is configured to connect a subsequently formed fourth connecting electrode to the plate connecting bar 34 through this via hole.
  • adjacent circuit cells in a cell row can share one fourteenth via hole V14.
  • the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 of the first initial signal line 41 on the substrate, the sixth insulating layer, the fifth insulating layer and the fourth insulating layer in the fifteenth via V15 are etched away to expose the surface of the first initial connection block 41-1, and the fifteenth via V15 is configured to connect the subsequently formed seventh connection electrode to the first initial connection block 41-1 through the via.
  • the adjacent circuit units share the same first initial connection block 41 - 1 , and thus some adjacent circuit units can share a fifteenth via V15 .
  • the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 of the second initial signal line 42 on the substrate, the sixth insulating layer in the sixteenth via V16 is etched away, exposing the surface of the second initial connection block 42-1, and the sixteenth via V16 is configured to connect the subsequently formed eighth connection electrode to the second initial connection block 42-1 through the via.
  • the orthographic projection of the seventeenth via V17 on the substrate is located within the range of the orthographic projection of the third initial connection block 43-1 of the third initial signal line 43 on the substrate, the sixth insulating layer in the seventeenth via V17 is etched away, exposing the surface of the third initial connection block 43-1, and the seventeenth via V17 is configured to connect the subsequently formed ninth connection electrode to the third initial connection block 43-1 through the via.
  • the adjacent circuit units share the same third initial connection block 43 - 1 , and thus some adjacent circuit units can share a seventeenth via V17 .
  • Forming a fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on the sixth insulating layer, as shown in FIG15A and FIG15B , where FIG15B is a plan view schematic diagram of the fourth conductive layer in FIG15A .
  • the fourth conductive layer may be referred to as a first source/drain metal (SD1) layer.
  • the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58 and a ninth connection electrode 59.
  • the first connection electrode 51 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the first connection electrode 51 is connected to the first region of the second active layer via a third via hole V3. A second end of the first connection electrode 51 extends along the second direction Y and is connected to the first electrode plate 31 via a thirteenth via hole V13.
  • the first electrode plate 31 also serves as the gate electrode of the third transistor T3
  • the first connection electrode 51 causes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 31 to have the same potential, forming a first node N1 of the pixel driving circuit.
  • the second connection electrode 52 may be in the shape of a strip with a main portion extending along the second direction Y.
  • the first end of the second connection electrode 52 is connected to the second region of the first active layer via a second via V2.
  • the second end of the second connection electrode 52 after extending along the second direction Y, is connected to the second region of the third active layer (also the first region of the sixth active layer) via a sixth via V6.
  • the portion between the first and second ends of the second connection electrode 52 is connected to the second region of the second active layer via a fourth via V4.
  • the second connection electrode 52 causes the second electrodes of the first transistor T1, the second electrodes of the second transistor T2, the second electrodes of the third transistor T3, and the first electrode of the sixth transistor T6 to have the same potential, forming a third node N3 of the pixel driving circuit.
  • the third connection electrode 53 may be in a block shape (eg, rectangular), connected to the first region of the fourth active layer through the seventh via hole V7, and configured to be connected to a subsequently formed data signal line.
  • the fourth connection electrode 54 may be in the shape of a strip extending along the second direction Y. A first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer via an eighth via hole V8. A second end of the fourth connection electrode 54 extends in a direction opposite to the second direction Y and is connected to the plate connection bar 34 via a fourteenth via hole V14. Because the plate connection bar 34 is connected to the second plate 32, the first electrode of the fifth transistor T5 in the circuit unit and the second plate 32 of the storage capacitor have the same potential.
  • some adjacent circuit units in one unit row share one eighth via hole V8 and one fourteenth via hole V14 , some adjacent circuit units may share one fourth connection electrode 54 .
  • At least one circuit unit may further include a power connection block 54-1.
  • the power connection block 54-1 may be in the shape of a bar extending along the first direction X.
  • a first end of the power connection block 54-1 is connected to the second end of the fourth connection electrode 54, and a second end of the power connection block 54-1 extends in a direction away from the fourth connection electrode 54.
  • the power connection block 54-1 is configured to be connected to a first power line formed subsequently.
  • the fourth connection electrode 54 and the power connection block 54-1 may be interconnected as an integral structure. Since some adjacent circuit units may share a fourth connection electrode 54, the fourth connection electrode 54 and the power connection block 54-1 in some two adjacent circuit units may be interconnected as an integral structure. This ensures that the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor in some adjacent circuit units have the same potential, which helps improve panel uniformity, prevents display defects on the display substrate, and ensures the display quality of the display substrate.
  • the fifth connection electrode 55 may be in the shape of a strip with a main portion extending along the second direction Y. A first end of the fifth connection electrode 55 is connected to the first region of the third active layer via a fifth via hole V5, and a second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer via a twelfth via hole V12.
  • the fifth connection electrode 55 causes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 to have the same potential, forming a second node N2 of the pixel driving circuit.
  • the sixth connection electrode 56 may be in a block shape (e.g., a rectangle) and is connected to the second region of the sixth active layer (also the second region of the seventh active layer) via a ninth via hole V9.
  • the sixth connection electrode 56 may simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.
  • the sixth connection electrode 56 is configured to be connected to an anode connection electrode formed subsequently.
  • the seventh connection electrode 57 may be in the shape of a strip extending along the first direction X.
  • a first end of the seventh connection electrode 57 is connected to the first region of the first active layer via a first via hole V1
  • a second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 via a fifteenth via hole V15.
  • the seventh connection electrode 57 enables the first initial signal transmitted by the first initial signal line 41 to be written into the first electrode of the first transistor T1.
  • the seventh connection electrodes 57 of some adjacent circuit units can be interconnected as a single unit. This ensures that the first electrodes of the first transistors T1 of some adjacent circuit units have the same potential, which helps improve the uniformity of the panel, avoids display defects on the display substrate, and ensures the display quality of the display substrate.
  • the seventh connection electrode 57 of the (N+1)th unit column and the seventh connection electrode 57 of the (N+2)th unit column are interconnected as a single unit.
  • the seventh connection electrode 57 of the (N+3)th unit column and the seventh connection electrode 57 of the (N+4)th unit column are interconnected as a single unit.
  • the eighth connection electrode 58 may be in the shape of a strip extending along the first direction X.
  • a first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer via a tenth via hole V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 via a sixteenth via hole V16.
  • the eighth connection electrode 58 enables the second initial signal transmitted by the second initial signal line 42 to be written into the first electrode of the seventh transistor T7.
  • the ninth connection electrode 59 may be in the shape of a strip extending along the first direction X.
  • a first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer via an eleventh via hole V11, and a second end of the ninth connection electrode 59 is connected to the third initial connection block 43-1 via a seventeenth via hole V17.
  • the ninth connection electrode 59 enables the third initial signal transmitted by the third initial signal line 43 to be written into the first electrode of the eighth transistor T8.
  • the ninth connection electrodes 59 of some adjacent circuit units can be interconnected as a single unit. This ensures that the first electrodes of the eighth transistors T8 of some adjacent circuit units have the same potential, which helps improve the uniformity of the panel, avoids display defects on the display substrate, and ensures the display quality of the display substrate.
  • the ninth connection electrode 59 of the Nth unit column and the ninth connection electrode 59 of the N+1th unit column are interconnected as a single unit.
  • the ninth connection electrode 59 of the N+2th unit column and the ninth connection electrode 59 of the N+3th unit column are interconnected as a single unit.
  • the fourth conductive layer of at least one circuit unit may further include a seventh connection block 57-1.
  • the seventh connection block 57-1 may be in the shape of a bar extending along the second direction Y and connected to the seventh connection electrode 57.
  • the seventh connection block 57-1 is configured to be connected to a first initial connection line formed subsequently.
  • the seventh connection block 57-1 may be disposed between some adjacent circuit units, and the adjacent circuit units share the same seventh connection block 57-1, and the seventh connection electrodes 57 and the shared seventh connection block 57-1 in the two circuit units are an integrated structure connected to each other.
  • the seventh connection block 57-1 may be disposed between the N-1th cell column and the Nth cell column.
  • the seventh connection block 57-1 may be disposed between the N+3th cell column and the N+4th cell column.
  • the seventh connection block 57-1 may be disposed between the N+7th cell column and the N+8th cell column.
  • the fourth conductive layer of at least one circuit unit may further include an eighth connection block 58-1.
  • the eighth connection block 58-1 may be shaped like a zigzag line extending along the second direction Y and connected to the eighth connection electrode 58.
  • the eighth connection block 58-1 is configured to be connected to a second initial connection line formed subsequently.
  • the eighth connection blocks 58-1 of some adjacent circuit cells may be interconnected, and the eighth connection electrodes 58 and the eighth connection blocks 58-1 in two circuit cells may be interconnected as an integral structure.
  • the eighth connection blocks 58-1 may be disposed in the (N+1)th cell column and the (N+2)th cell column.
  • the eighth connection blocks 58-1 may be disposed in the (N+5)th cell column and the (N+6)th cell column.
  • the eighth connection blocks 58-1 may be disposed in the (N+9)th cell column and the (N+10)th cell column.
  • the fifth conductive layer may further include a plurality of first traces.
  • the first traces may be straight or zigzag extending along the first direction X and may be located between the first scan signal line and the first initial signal line 41 .
  • At least one first trace may include a horizontal sub-line and a first power trace 91.
  • a first break K1 is provided between the horizontal sub-line and the first power trace 91.
  • the first break K1 can separate the horizontal sub-line from the first power trace 91, thereby isolating the horizontal sub-lines and the first power trace 91 on both sides of the first break K1 from each other.
  • the first traces in the Mth cell row may include a second horizontal sub-line 81-2 and a first power trace 91 arranged sequentially along the first direction X.
  • the first traces in the M+1th cell row may include a fourth horizontal sub-line 81-4 and a first power trace 91 arranged sequentially along the first direction X.
  • the first traces in the M+2th cell row may include a sixth horizontal sub-line 81-6 and a first power trace 91 arranged sequentially along the first direction X.
  • At least one first trace may include a horizontal sub-line and two first power traces 91.
  • a first break K1 is provided between each of the two first power traces 91 and the horizontal sub-line.
  • the first break K1 can cut off the horizontal sub-line from the first power trace 91.
  • the first traces in the (M+5)th cell row may include the first power trace 91, the first horizontal sub-line 81-1, and the first power trace 91, which are sequentially arranged along the first direction X.
  • At least one first trace may include two horizontal sub-lines and a first power trace 91.
  • a first break K1 may be provided between the two horizontal sub-lines.
  • the first break K1 may cut off the two horizontal sub-lines, thereby isolating the two horizontal sub-lines on either side of the first break K1 from each other.
  • a first break K1 may be provided between the horizontal sub-line and the first power trace 91.
  • the first break K1 may cut off the horizontal sub-line from the first power trace 91.
  • the first traces in the M+3th cell row may include the seventh horizontal sub-line 81-7, the fifth horizontal sub-line 81-5, and the first power trace 91, arranged in sequence along the first direction X.
  • the first traces in the M+4th cell row may include the eighth horizontal sub-line 81-8, the third horizontal sub-line 81-3, and the first power trace 91, arranged in sequence along the first direction X.
  • the first horizontal sub-line 81-1 in the M+5th unit row and the second horizontal sub-line 81-2 in the Mth unit row can be referred to as the first first data connection line 81, one end of the two horizontal sub-lines can be connected together through a second vertical sub-line formed subsequently, the other end of the first horizontal sub-line 81-1 is configured to be connected to the first vertical sub-line formed subsequently, and the other end of the second horizontal sub-line 81-2 is configured to be connected to a data signal line formed subsequently.
  • the third horizontal sub-line 81-3 in the M+4th unit row and the fourth horizontal sub-line 81-4 in the M+1th unit row can be referred to as the second first data connection line 81, and one end of the two horizontal sub-lines can be connected together through a subsequently formed fourth vertical sub-line, the other end of the third horizontal sub-line 81-3 is configured to be connected to the subsequently formed third vertical sub-line, and the other end of the fourth horizontal sub-line 81-4 is configured to be connected to a subsequently formed data signal line.
  • the fifth horizontal sub-line 81-5 in the M+3th unit row and the sixth horizontal sub-line 81-6 in the M+2th unit row can be referred to as the third first data connection line 81, one end of the two horizontal sub-lines can be connected together through a subsequently formed sixth vertical sub-line, the other end of the fifth horizontal sub-line 81-5 is configured to be connected to the subsequently formed fifth vertical sub-line, and the other end of the sixth horizontal sub-line 81-6 is configured to be connected to a subsequently formed data signal line.
  • the data transfer bar 83 and the first data connection block 84 may be disposed between the N+4th cell column and the N+5th cell column, with the first data connection block 84 connected to the sixth horizontal sub-line 81-6 via the data transfer bar 83.
  • the data transfer bar 83 and the first data connection block 84 can be arranged between the N+4th cell column and the N+5th cell column, with the first data connection block 84 connected to the seventh horizontal sub-line 81-7 via the data transfer bar 83.
  • the data transfer bar 83 and the first data connection block 84 can be arranged between the N+6th cell column and the N+7th cell column, with the first data connection block 84 connected to the fifth horizontal sub-line 81-5 via the data transfer bar 83.
  • the data transfer bar 83 and the first data connection block 84 can be arranged between the N+2th cell column and the N+3th cell column, with the first data connection block 84 connected to the eighth horizontal sub-line 81-8 via the data transfer bar 83.
  • the data transfer bar 83 and the first data connection block 84 can be arranged between the N+8th cell column and the N+9th cell column, with the first data connection block 84 connected to the third horizontal sub-line 81-3 via the data transfer bar 83.
  • the data transfer bar 83 and the first data connection block 84 can be set between the N+10th unit column and the N+11th unit column, and the first data connection block 84 is connected to the first horizontal sub-line 81-1 through the data transfer bar 83.
  • the second data connection block 85 may be provided between some of the circuit cells adjacent in the first direction X.
  • no second data connection block 85 is provided in the Mth to M+2th cell rows.
  • the second data connection block 85 may be provided between the N+4th cell column and the N+5th cell column and connected to the fifth horizontal sub-line 81-5.
  • the second data connection block 85 may be provided between the N+2th cell column and the N+3th cell column and connected to the third horizontal sub-line 81-3.
  • the second data connection block 85 may be provided between the Nth cell column and the N+1th cell column and connected to the first horizontal sub-line 81-1.
  • the horizontal sub-line and the second data connection block 85 may be an integral structure connected to each other.
  • At least one cell row may be provided with only the first data connection block 84.
  • one horizontal sub-line (the second horizontal sub-line 81-2, the fourth horizontal sub-line 81-4, or the sixth horizontal sub-line 81-6) may be provided in the Mth cell row to the M+2th cell row, and one end of the horizontal sub-line is connected to the first data connection block 84.
  • At least one cell row may be provided with both a first data connection block 84 and a second data connection block 85, and the first data connection block 84 and the second data connection block 85 are respectively provided at the ends of a horizontal sub-line in the first direction X.
  • the M+3th cell row is provided with two horizontal sub-lines (the fifth horizontal sub-line 81-5 and the seventh horizontal sub-line 81-7), and the M+4th cell row is provided with two horizontal sub-lines (the third horizontal sub-line 81-3 and the eighth horizontal sub-line 81-8).
  • one end of one horizontal sub-line is connected to the first data connection block 84, and the other two ends of the other horizontal sub-line are respectively connected to the first data connection block 84 and the second data connection block 85.
  • the first data connection block 84 and the second data connection block 85 may be located at both sides of the transverse sub-line in the second direction Y, respectively.
  • the orthographic projection of at least one horizontal sub-line on the substrate at least partially overlaps with the orthographic projection of the second initial signal line 42 on the substrate, so that the second initial signal line 42 with a constant potential can effectively shield the influence of voltage jumps in the horizontal sub-line on the pixel driving circuit.
  • the first traces may include only the first power trace 91 .
  • At least one circuit unit may further include a first dummy electrode 86.
  • the first dummy electrode 86 may be block-shaped (e.g., rectangular) and configured to connect to a subsequently formed vertical sub-line. In the first direction X, the first dummy electrode 86 may be disposed between some of the circuit units adjacent in the first direction X. In the second direction Y, the first dummy electrode 86 may be disposed on a side of the horizontal sub-line close to the second electrode plate 32.
  • the position and connection structure of the first dummy electrode 86 in one circuit unit can be substantially the same as the position and connection structure of the first data connection block 84 in another circuit unit, except that the first dummy electrode 86 is isolated and is neither connected to the horizontal sub-line nor to other electrodes.
  • the morphology and connection structure presented by the first dummy electrode 86 are substantially the same as those of the first data connection block 84. The present disclosure not only improves the uniformity of the subsequent etching process by designing the same transition area, but also enables different positions to achieve the same display effect under transmitted and reflected light, achieving shadow elimination, effectively avoiding the poor appearance of the display substrate and the occurrence of off-screen watermarks (mura), and improving display quality.
  • At least one circuit unit may further include a second dummy electrode 87.
  • the second dummy electrode 87 may be block-shaped (e.g., rectangular) and configured to connect to a subsequently formed vertical sub-line.
  • the second dummy electrode 87 may be disposed between some of the circuit units adjacent in the first direction X.
  • the second dummy electrode 87 may be disposed on a side of the horizontal sub-line away from the second electrode plate 32.
  • the position and connection structure of the second dummy electrode 87 in one circuit unit can be substantially the same as the position and connection structure of the second data connection block 85 in another circuit unit, except that the second dummy electrode 87 is isolated and is neither connected to the horizontal sub-line nor to other electrodes.
  • the morphology and connection structure presented by the second dummy electrode 87 are substantially the same as those of the second data connection block 85.
  • the present disclosure through the identical design of the transfer area, not only improves the uniformity of the subsequent etching process, but also enables different positions to achieve the same display effect under both transmitted and reflected light, achieving shadow elimination, effectively avoiding the poor appearance of the display substrate and the occurrence of off-screen watermarks (mura), and improving the display quality.
  • the first dummy electrode 86 and the second dummy electrode 87 may be respectively located on both sides of the transverse sub-line in the second direction Y.
  • Forming a first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the fourth conductive layer pattern, wherein a plurality of vias are provided on the first planar layer, as shown in FIG. 16 .
  • the plurality of vias in each circuit unit includes at least a twenty-first via V21 , a twenty-second via V22 , and a twenty-third via V23 .
  • the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the third connecting electrode 53 on the substrate, the first flat layer in the twenty-first via hole V21 is etched away to expose the surface of the third connecting electrode 53, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the third connecting electrode 53 through the via hole.
  • the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the power connection block 54-1 of the fourth connection electrode 54 on the substrate, the first flat layer within the twenty-second via V22 is etched away to expose the surface of the power connection block 54-1, and the twenty-second via V22 is configured to connect the subsequently formed first power line to the power connection block 54-1 through the via.
  • the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the sixth connecting electrode 56 on the substrate, the first flat layer within the twenty-third via hole V23 is etched away to expose the surface of the sixth connecting electrode 56, and the twenty-third via hole V23 is configured to connect the subsequently formed anode connecting electrode to the sixth connecting electrode 56 through the via hole.
  • At least one circuit unit may further include a twenty-fourth via V24.
  • the orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the seventh connecting block 57-1 on the substrate.
  • the first flat layer within the twenty-fourth via V24 is etched away, exposing the surface of the seventh connecting block 57-1.
  • the twenty-fourth via V24 is configured to connect a subsequently formed first initial connecting line to the seventh connecting block 57-1 through the via.
  • the twenty-fourth via V24 may be disposed between some adjacent circuit cells.
  • the twenty-fourth via V24 may be disposed between the (N+3)th cell column and the (N+4)th cell column.
  • the twenty-fourth via V24 may be disposed between the (N+7)th cell column and the (N+8)th cell column.
  • At least one circuit unit may further include a twenty-fifth via hole V25.
  • the orthographic projection of the twenty-fifth via hole V25 on the substrate is located within the range of the orthographic projection of the eighth connection block 58-1 on the substrate.
  • the first flat layer within the twenty-fifth via hole V25 is etched away, exposing the surface of the eighth connection block 58-1.
  • the twenty-fifth via hole V25 is configured to connect a subsequently formed second initial connection line to the eighth connection block 58-1 through the via hole.
  • the twenty-fifth via V25 may be disposed between some adjacent circuit cells.
  • the twenty-fifth via V25 may be disposed between the (N+1)th cell column and the (N+2)th cell column.
  • the twenty-fifth via V25 may be disposed between the (N+5)th cell column and the (N+6)th cell column.
  • the twenty-fifth via V25 may be disposed between the (N+9)th cell column and the (N+10)th cell column.
  • At least one circuit unit may further include a twenty-sixth via V26.
  • the orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the first data connection block 84 on the substrate.
  • the first flat layer within the twenty-sixth via V26 is etched away, exposing the surface of the first data connection block 84.
  • the twenty-sixth via V26 is configured to connect a subsequently formed vertical sub-line to the first data connection block 84 through the via.
  • At least one circuit unit may further include a twenty-seventh via hole V27.
  • the orthographic projection of the twenty-seventh via hole V27 on the substrate is located within the range of the orthographic projection of the second data connection block 85 on the substrate.
  • the first flat layer within the twenty-seventh via hole V27 is etched away, exposing the surface of the second data connection block 85.
  • the twenty-seventh via hole V27 is configured to connect a subsequently formed vertical sub-line to the second data connection block 85 through the via hole.
  • At least one circuit unit may further include a twenty-eighth via hole V28.
  • the orthographic projection of the twenty-eighth via hole V28 on the substrate is located within the range of the orthographic projection of the first dummy electrode 86 on the substrate.
  • the first flat layer within the twenty-eighth via hole V28 is etched away, exposing the surface of the first dummy electrode 86.
  • the twenty-eighth via hole V28 is configured to connect a subsequently formed vertical sub-line to the first dummy electrode 86 through the via hole.
  • At least one circuit unit may further include a twenty-ninth via hole V29.
  • the orthographic projection of the twenty-ninth via hole V29 on the substrate is located within the range of the orthographic projection of the second dummy electrode 87 on the substrate.
  • the first flat layer within the twenty-ninth via hole V29 is etched away, exposing the surface of the second dummy electrode 87.
  • the twenty-ninth via hole V29 is configured to connect a subsequently formed vertical sub-line to the second dummy electrode 87 through the via hole.
  • forming the fifth conductive layer may include: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on the first flat layer, as shown in FIG17A and FIG17B , where FIG17B is a plan view schematic diagram of the fifth conductive layer in FIG17A .
  • the fifth conductive layer may be referred to as a second source/drain metal (SD2) layer.
  • the fifth conductive layer of each circuit unit includes at least a first power line 71 , a data signal line 72 , and an anode connection electrode 73 .
  • the first power line 71 may be in the shape of a straight line or a zigzag line, with its main portion extending along the second direction Y.
  • the first power line 71 is connected to the power connection block 54-1 through the twenty-second via V32. Since the power connection block 54-1 is connected to the fourth connection electrode 54, and the fourth connection electrode 54 is respectively connected to the first region of the fifth active layer and the second plate 32 of the storage capacitor, the first power line 71 can write the first power signal to the fifth transistor T5 and the second plate 32 of the storage capacitor.
  • the first power line 71 may be a zigzag line with unequal width, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the first power line and the data signal line.
  • a power shielding block 74 may be provided on the first power line 71.
  • the power shielding block 74 may be block-shaped (e.g., rectangular) and may be provided on a side of the first power line 71 near the second transistor T2 and connected to the first power line 71.
  • the orthographic projection of the power shielding block 74 on the substrate at least partially overlaps with the orthographic projection of the second active layer of the second transistor T2 on the substrate.
  • the power shielding block 74 can shield the second active layer, preventing light emitted by the light-emitting device and light reflected from the film layer from reaching the oxide-containing second transistor T2. This can prevent characteristic drift of the oxide transistor due to light exposure, thereby improving the electrical characteristics of the oxide transistor.
  • the orthographic projections of the first power line 71 and the power shielding block 74 on the substrate at least partially overlap with the orthographic projections of the first connection electrode 51 on the substrate, so that the first power line 71 and the power shielding block 74 having a constant potential can effectively shield the influence of data voltage jumps and other signals on the first node N1 in the pixel driving circuit, thereby preventing the data voltage jumps and other signals from affecting the potential of the first node N1, thereby improving the driving performance of the pixel driving circuit.
  • the first power line 71 and the power shielding block 74 may be an integral structure connected to each other.
  • the data signal line 72 may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y.
  • the data signal line 72 is connected to the third connection electrode 53 through the twenty-first via hole V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via hole, the data signal line 72 is connected to the first electrode of the fourth transistor T4.
  • the data signal line 72 can write a data signal to the first electrode of the fourth transistor T4.
  • the anode connection electrode 73 may be in the shape of a strip extending along the second direction Y.
  • the anode connection electrode 73 is connected to the sixth connection electrode 56 via a twenty-third via hole V23.
  • the anode connection electrode 73 is configured to be connected to a subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer via the via hole, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light-emitting device to emit light.
  • the fifth conductive layer of at least one circuit unit may further include a first initial connection line 61.
  • the first initial connection line 61 may be in the form of a straight line or a zigzag line, with the main portion extending along the second direction Y.
  • the first initial connection line 61 is connected to the seventh connection block 57-1 via the twenty-fourth via V24. Since the seventh connection block 57-1 is connected to the seventh connection electrode 57, and the seventh connection electrode 57 is connected to the first initial signal line 41, interconnection is achieved between the first initial signal line 41 extending along the first direction X and the first initial connection line 61 extending along the second direction Y.
  • the first initial signal line 41 and the first initial connection line 61 form a meshed interconnected structure for transmitting the first initial signal. This effectively reduces the resistance of the first initial signal line and the voltage drop of the first initial signal, effectively improves the uniformity of the first initial signal in the display substrate, effectively improves display uniformity, and enhances display quality.
  • the first initial connection line 61 may be disposed between two first power lines 71 in some adjacent unit columns, and four first power lines 71 may be disposed between two adjacent first initial connection lines 61 in the first direction X.
  • the first initial connection line 61 may be disposed between the first power line 71 in the (N+3)th unit column and the first power line 71 in the (N+4)th unit column.
  • the first initial connection line 61 may be disposed between the first power line 71 in the (N+7)th unit column and the first power line 71 in the (N+8)th unit column.
  • the fifth conductive layer of at least one circuit unit may further include a second initial connection line 62.
  • the second initial connection line 62 may be shaped as a straight line or a zigzag line, with the main portion extending along the second direction Y.
  • the second initial connection line 62 is connected to the eighth connection block 58-1 via the twenty-fifth via V25. Since the eighth connection block 58-1 is connected to the eighth connection electrode 58, and the eighth connection electrode 58 is connected to the second initial signal line 42, interconnection is achieved between the second initial signal line 42 extending along the first direction X and the second initial connection line 62 extending along the second direction Y.
  • the second initial signal line 42 and the second initial connection line 62 form a meshed interconnected structure for transmitting the second initial signal. This effectively reduces the resistance of the second initial signal line and the voltage drop of the second initial signal, effectively improves the uniformity of the second initial signal in the display substrate, effectively improves display uniformity, and enhances display quality.
  • the second initial connection line 62 may be disposed between two first power lines 71 in some adjacent unit columns, and four first power lines 71 may be disposed between two second initial connection lines 62 adjacent in the first direction X.
  • the second initial connection line 62 may be disposed between the first power line 71 in the (N+1)th unit column and the first power line 71 in the (N+2)th unit column.
  • the second initial connection line 62 may be disposed between the first power line 71 in the (N+5)th unit column and the first power line 71 in the (N+6)th unit column.
  • the second initial connection line 62 may be disposed between the first power line 71 in the (N+9)th unit column and the first power line 71 in the (N+10)th unit column.
  • the first initial connection lines 61 and the second initial connection lines 62 may be alternately arranged, one second initial connection line 62 may be arranged between adjacent first initial connection lines 61 in the first direction X, and one first initial connection line 61 may be arranged between adjacent second initial connection lines 62 in the first direction X.
  • the fifth conductive layer of at least one circuit unit may also include a third initial connection line whose main part extends along the second direction Y.
  • the third initial connection line can be connected to the third initial signal line through a via to form a mesh-like interconnected structure for transmitting the third initial signal.
  • the present disclosure does not limit this.
  • the fifth conductive layer may further include a plurality of second traces.
  • the second traces may be in the shape of a straight line or a zigzag line, with the main portion extending along the second direction Y.
  • the second traces may be located between two data signal lines 72 in some adjacent unit columns.
  • Two first power lines 71 and two data signal lines 72 may be provided between two second traces adjacent in the first direction X.
  • a second trace may be located between the data signal line 72 in the Nth unit column and the data signal line 72 in the N+1th unit column.
  • a second trace may be located between the data signal line 72 in the N+2th unit column and the data signal line 72 in the N+3th unit column.
  • a second trace may be located between the data signal line 72 in the N+4th unit column and the data signal line 72 in the N+5th unit column.
  • At least one second trace may include a vertical sub-line and a second power trace 92.
  • a second break K2 may be provided between the vertical sub-line and the second power trace 92.
  • the second break K2 may disconnect the vertical sub-line from the second power trace 92, thereby isolating the vertical sub-line and the second power trace 92 on both sides of the second break K2 from each other.
  • the second trace located between the (N+6)th cell column and the (N+7)th cell column may include the second power trace 92 and the fifth vertical sub-line 82-5 sequentially arranged along the second direction Y.
  • the second trace located between the (N+8)th cell column and the (N+9)th cell column may include the second power trace 92 and the third vertical sub-line 82-3 sequentially arranged along the second direction Y.
  • the second trace located between the (N+10)th cell column and the (N+11)th cell column may include the second power trace 92 and the first vertical sub-line 82-1 sequentially arranged along the second direction Y.
  • the at least one second trace may include a vertical sub-line and two second power traces 92.
  • a second break K2 is provided between each of the two second power traces 92 and the vertical sub-line.
  • the second break K2 can separate the vertical sub-line from the second power trace 92.
  • the second trace located between the Nth cell column and the N+1th cell column may include the second power trace 92, the second vertical sub-line 82-2, and the second power trace 92, which are sequentially arranged along the second direction Y.
  • At least one second routing line may include two vertical sub-lines and a second power routing line 92.
  • a second break K2 may be provided between the two vertical sub-lines, and the second break K2 may cut off the two vertical sub-lines, so that the two vertical sub-lines on both sides of the second break K2 are insulated from each other.
  • a second break K2 is provided between the vertical sub-line and the second power routing line 92, and the second break K2 may cut off the vertical sub-line from the second power routing line 92.
  • the second routing line located between the N+2th unit column and the N+3th unit column may include the second power routing line 92, the fourth vertical sub-line 82-4, and the eighth vertical sub-line 82-8, which are sequentially arranged along the second direction Y.
  • the second routing line located between the N+4th unit column and the N+5th unit column may include the second power routing line 92, the sixth vertical sub-line 82-6, and the seventh vertical sub-line 82-7, which are sequentially arranged along the second direction Y.
  • one end of at least one vertical sub-line is configured to extend to the binding area and then connect to the data lead-out line, and the other end is connected to the first data connection block 84 through the twenty-sixth via V26, thereby realizing the interconnection between a vertical sub-line and a horizontal sub-line.
  • At least one vertical sub-line has one end connected to the second data connection block 85 through the twenty-seventh via V27 and the other end connected to the first data connection block 84 through the twenty-sixth via V26, thereby realizing the interconnection between one vertical sub-line and two horizontal sub-lines.
  • At least one vertical sub-line is further connected to the first dummy electrode 86 through the twenty-eighth via hole V28 , so that all positions of the display substrate present the same morphology and connection structure.
  • At least one vertical sub-line is further connected to the second dummy electrode 87 through a twenty-ninth via hole V29 , so that all positions of the display substrate present the same morphology and connection structure.
  • the first vertical sub-line 82-1 between the N+10th unit column and the N+11th unit column and the second vertical sub-line 82-2 between the Nth unit column and the N+1th unit column can be referred to as the first second data connection line 82
  • the first vertical sub-line 82-1 is connected to the first horizontal sub-line 81-1
  • the second vertical sub-line 82-2 is connected to the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2, respectively.
  • the third vertical sub-line 82-3 between the N+8th unit column and the N+9th unit column and the fourth vertical sub-line 82-4 between the N+2th unit column and the N+3th unit column can be referred to as the second second data connection line 82
  • the third vertical sub-line 82-3 is connected to the third horizontal sub-line 81-3
  • the fourth vertical sub-line 82-4 is connected to the third horizontal sub-line 81-3 and the fourth horizontal sub-line 81-4, respectively.
  • the fifth vertical sub-line 82-5 between the N+6th unit column and the N+7th unit column and the sixth vertical sub-line 82-6 between the N+4th unit column and the N+5th unit column can be referred to as the third second data connection line 82
  • the fifth vertical sub-line 82-5 is connected to the fifth horizontal sub-line 81-5
  • the sixth vertical sub-line 82-6 is connected to the fifth horizontal sub-line 81-5 and the sixth horizontal sub-line 81-6, respectively.
  • the seventh vertical sub-line 82 - 7 between the N+4th cell column and the N+5th cell column may be referred to as a fourth second data connection line 82 , and the seventh vertical sub-line 82 - 7 is connected to the seventh horizontal sub-line 81 - 7 .
  • the eighth vertical sub-line 82 - 8 between the (N+2)th unit column and the (N+3)th unit column may be referred to as a fifth second data connection line 82 , and the eighth vertical sub-line 82 - 8 is connected to the eighth horizontal sub-line 81 - 8 .
  • FIG17C is a schematic diagram illustrating the connection of horizontal and vertical sub-lines according to an exemplary embodiment of the present disclosure.
  • the plurality of data connection lines may include at least a first data connection line 80A, a second data connection line 80B, a third data connection line 80C, a fourth data connection line 80D, and a fifth data connection line 80E.
  • the first data connection line 80A may include at least a first first data connection line and a first second data connection line.
  • the first first data connection line may include at least a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2.
  • the first second data connection line may include at least a first vertical sub-line 82-1 and a second vertical sub-line 82-2.
  • the first horizontal sub-line 81-1 may be arranged in the M+5th unit row
  • the second horizontal sub-line 81-2 may be arranged in the Mth unit row
  • the first vertical sub-line 82-1 may be arranged between the N+10th unit column and the N+11th unit column
  • the second vertical sub-line 82-2 may be arranged between the Nth unit column and the N+1th unit column.
  • the first end of the first vertical sub-line 82-1 is connected to a data lead-out line in the binding area.
  • the second end of the first vertical sub-line 82-1 extends in the direction opposite to the second direction Y and is then connected to the first end of the first horizontal sub-line 81-1 via the first data connection block 84.
  • the second end of the first horizontal sub-line 81-1 extends in the first direction X or the direction opposite to the first direction X and is then connected to the first end of the second vertical sub-line 82-2 via the second data connection block 85.
  • the second end of the second vertical sub-line 82-2 extends in the direction opposite to the second direction Y and is then connected to the first end of the second horizontal sub-line 81-2 via the first data connection block 84.
  • the second end of the second horizontal sub-line 81-2 extends in the first direction X or the direction opposite to the first direction X and is then connected to a data signal line.
  • the second data connection line 80B may include at least a second first data connection line and a second second data connection line
  • the second first data connection line may include at least a third horizontal sub-line 81-3 and a fourth horizontal sub-line 81-4
  • the second second data connection line may include at least a third vertical sub-line 82-3 and a fourth vertical sub-line 82-4.
  • the first horizontal sub-line 81-1 may be arranged in the M+4th unit row
  • the fourth horizontal sub-line 81-4 may be arranged in the M+1th unit row
  • the third vertical sub-line 82-3 may be arranged between the N+8th unit column and the N+9th unit column
  • the fourth vertical sub-line 82-4 may be arranged between the N+2th unit column and the N+3th unit column.
  • the first end of the third vertical sub-line 82-3 is connected to another data lead-out line in the binding area.
  • the second end of the third vertical sub-line 82-3 extends in the direction opposite to the second direction Y and is then connected to the first end of the third horizontal sub-line 81-3 via the first data connection block 84.
  • the second end of the third horizontal sub-line 81-3 extends in the first direction X or the direction opposite to the first direction X and is then connected to the first end of the fourth vertical sub-line 82-4 via the second data connection block 85.
  • the second end of the fourth vertical sub-line 82-4 extends in the direction opposite to the second direction Y and is then connected to the first end of the fourth horizontal sub-line 81-4 via the first data connection block 84.
  • the second end of the fourth horizontal sub-line 81-4 extends in the first direction X or the direction opposite to the first direction X and is then connected to another data signal line.
  • the third data link line 80C may include at least a third first data link line and a third second data link line.
  • the third first data link line may include at least a fifth horizontal sub-line 81-5 and a sixth horizontal sub-line 81-6.
  • the third second data link line may include at least a fifth vertical sub-line 82-5 and a sixth vertical sub-line 82-6.
  • the fifth horizontal sub-line 81-5 may be arranged in the M+3th unit row
  • the sixth horizontal sub-line 81-6 may be arranged in the M+2th unit row
  • the fifth vertical sub-line 82-5 may be arranged between the N+6th unit column and the N+7th unit column
  • the sixth vertical sub-line 82-6 may be arranged between the N+4th unit column and the N+5th unit column.
  • the first end of the fifth vertical sub-line 82-5 is connected to another data lead-out line in the binding area.
  • the second end of the fifth vertical sub-line 82-5 extends in the direction opposite to the second direction Y and is then connected to the first end of the fifth horizontal sub-line 81-5 via a first data connection block 84.
  • the second end of the fifth horizontal sub-line 81-5 extends in the first direction X or the direction opposite to the first direction X and is then connected to the first end of the sixth vertical sub-line 82-6 via a second data connection block 85.
  • one second trace and two data signal lines 72 may be disposed between two first power lines 71 of adjacent cell columns, the two first power lines 71 may be mirror-symmetrical with respect to the second trace, and the two data signal lines 72 may be mirror-symmetrical with respect to the second trace.
  • the materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen.
  • the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-Si).
  • a light emitting structure layer may be prepared on the driving circuit layer.
  • the preparation process of the light emitting structure layer may include the following operations.
  • At least one of the first anode 90A, the second anode 90B, the third anode 90C and the fourth anode 90D may include an anode main body and an anode connecting portion that are connected to each other, the shape of the anode main body may be a diamond shape, the rectangular corners may be provided with arc-shaped chamfers, the shape of the anode connecting portion may be a strip shape, the first end of the anode connecting portion is connected to the anode main body, and the second end of the anode connecting portion extends in a direction away from the anode main body and is connected to the anode connecting electrode 73 through the anode via V30.
  • the orthographic projections of the first anode 90A, the third anode 90C, and the fourth anode 90D on the substrate do not overlap with the orthographic projection of the twenty-sixth via hole V26 (or the twenty-eighth via hole V28 ) on the substrate.
  • the orthographic projections of the first anode 90A, the third anode 90C, and the fourth anode 90D on the substrate do not overlap with the orthographic projection of the twenty-seventh via hole V27 (or the twenty-ninth via hole V29 ) on the substrate.
  • the orthographic projections of the first anode 90A, the third anode 90C, and the fourth anode 90D on the substrate do not overlap with the orthographic projections of the first data connection block 84 (or the first dummy electrode 86 ) and the second data connection block 85 (or the second dummy electrode 87 ) on the substrate.
  • an orthographic projection of the second anode 90B on the substrate at least partially overlaps with an orthographic projection of the twenty-sixth via hole V26 (or the twenty-eighth via hole V28 ) on the substrate.
  • an orthographic projection of the second anode 90B on the substrate at least partially overlaps with an orthographic projection of the twenty-seventh via hole V27 (or the twenty-ninth via hole V29 ) on the substrate.
  • the orthographic projection of the second anode 90B on the substrate at least partially overlaps with the orthographic projections of the twenty-sixth via hole V26 (or the twenty-eighth via hole V28 ) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29 ) on the substrate.
  • the second anode 90B may have an anode centerline, which may be in the shape of a broken line passing through the geometric center of the anode body of the second anode and extending along the first direction X.
  • the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) may be located on one side of the anode centerline in the second direction Y, and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) may be located on a side opposite to the second direction Y of the anode centerline, that is, the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) may be arranged one above the other with respect to the anode centerline.
  • the anode center line can be a broken line passing through the geometric center of the anode body of the second anode and extending along the first direction X.
  • the ratio of the first distance to the second distance may be approximately 0.9 to 1.1, ie, the twenty-sixth via hole V26 (or the twenty-eighth via hole V28 ) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29 ) may correspond to upper and lower positions relative to the anode centerline.
  • the anode conductive layer may have a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO/Ag/ITO.
  • ITO indium tin oxide
  • IZO indium zinc oxide
  • the subsequent manufacturing process may include: first forming a pixel definition layer, the pixel definition layer being provided with a plurality of pixel openings, the plurality of pixel openings respectively exposing a first anode, a second anode, a third anode, and a fourth anode; then forming an organic light-emitting layer using an evaporation or inkjet printing process; then forming a cathode on the organic light-emitting layer; and finally forming an encapsulation structure layer, which may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.
  • the first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of an organic material.
  • the second encapsulation layer is disposed between the first and third encapsulation layers to prevent external moisture from entering the light-emitting structure layer.
  • An exemplary embodiment of the present disclosure provides a display substrate, which effectively reduces the difference in the number of data connection line coupling unit columns in different unit rows by splitting a first data connection line with a longer extension length into two horizontal sub-lines, and arranging the two horizontal sub-lines in different unit rows, and can effectively reduce or even eliminate the appearance of diagonal watermarks at the two corners of the display area close to the binding area.
  • first horizontal sub-line 81-1 and a second horizontal sub-line 81-2 are substantially the same as the sum of the number of cell columns coupled to the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 in the present disclosure
  • the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 in the present disclosure are arranged in different cell rows, the number of cell columns coupled in the cell row where the first horizontal sub-line 81-1 is located is smaller, and the number of cell columns coupled in the cell row where the second horizontal sub-line 81-2 is located is smaller, and the number of cell columns coupled to the first horizontal sub-line 81-1 and the number of cell columns coupled to the second horizontal sub-line 81-2 are similar, thereby effectively reducing the difference in the number of cell columns coupled to the data connection lines
  • first data connection line 81 that is closer to the binding area in Figure 6 as an example, although the extension length of the first data connection line in Figure 6 is shorter and it is coupled with fewer unit columns, since the present disclosure splits the other first data connection lines into two horizontal sub-lines, the unit row where the first data connection line is located is provided with horizontal sub-lines of other data connection lines, which increases the number of data connection line coupled unit columns in the unit row and is close to the number of data connection line coupled unit columns in other unit rows, thereby effectively reducing the difference in the number of data connection line coupled unit columns in different unit rows.
  • the present disclosure effectively reduces the area of the first area (FIP area) by splitting the first data connection line with a longer extension length into two horizontal sub-lines and splitting the second data connection line with a longer extension length into two vertical sub-lines, which is beneficial to increasing the number of power lines and reducing the power signal voltage drop, and can effectively improve display uniformity, display quality and display quality.
  • the disclosed embodiment realizes the FIP structure by setting data connection lines in the display area, and connecting the data lead lines in the binding area to the data signal lines through the data connection lines, so that there is no need to set fan-shaped oblique lines in the lead line area, which effectively reduces the length of the lead line area, greatly reduces the width of the lower frame, and improves the screen-to-body ratio, which is conducive to achieving full-screen display.
  • the disclosed embodiment realizes a SIP structure by arranging a first power supply line and a second power supply line in the display area. This not only effectively reduces the resistance of the second power supply line and the voltage drop of the second power supply signal, thereby achieving low power consumption and effectively improving the uniformity of the second power supply signal in the display substrate, thereby effectively improving the display uniformity and improving the display quality, but also significantly reduces the width of the frame power supply lead, greatly reduces the frame width, improves the screen-to-body ratio, and facilitates the realization of full-screen display.
  • the first initial connection line and the first initial signal line form a mesh connection structure
  • the second initial connection line and the second initial signal line form a mesh connection structure
  • a first dummy electrode and a second dummy electrode are provided.
  • the morphology and connection structure presented by the first dummy electrode are substantially the same as those of the first data connection block, and the morphology and connection structure presented by the second dummy electrode are substantially the same as those of the second data connection block, so that the display area has a substantially identical transfer area structure, the uniformity of the etching process is improved, different areas can achieve the same display effect under transmitted and reflected light, and shadow elimination is realized, which effectively avoids the poor appearance of the display substrate and the occurrence of screen-off watermarks, and improves the display quality.
  • a second anode is provided to cover the transfer via on the first flat layer, and the two transfer vias are provided correspondingly at upper and lower positions relative to the center line of the anode, so that the anode has good flatness and can effectively improve color deviation.
  • the preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.
  • the structure and preparation process shown above in the present disclosure are merely exemplary.
  • the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.
  • the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • a pixel driving circuit such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.
  • the present disclosure also provides a method for manufacturing a display substrate, for producing the display substrate provided in the above-mentioned embodiment.
  • the display substrate includes a display area and a binding area disposed on one side of the display area.
  • the display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit includes a pixel driving circuit.
  • the manufacturing method may include:
  • a plurality of data signal lines and a plurality of data connection lines are formed in the display area, and a plurality of data lead-out lines are formed in the binding area, wherein the data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines through the data connection lines; at least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, wherein the two horizontal sub-lines are arranged in different unit rows, and the two vertical sub-lines are arranged in different unit columns, and the first direction and the second direction intersect.

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Abstract

一种显示基板及其制备方法、显示装置。显示基板包括显示区域和设置在所述显示区域一侧的绑定区域，所述显示区域包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述绑定区域至少包括多条数据引出线；所述显示区域还包括多条数据信号线和多条数据连接线，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述数据信号线通过所述数据连接线与所述数据引出线连接；至少一条数据连接线包括至少两条沿着第一方向延伸的横向子线和至少两条沿着第二方向延伸的竖向子线，所述两条横向子线设置在不同的单元行中，所述两条竖向子线设置在不同的单元列中。本公开可以减轻甚至消除斜纹水印。

Description

显示基板及其制备方法、显示装置
本申请要求于2024年4月18日提交中国专利局、申请号为202410472215.7、发明名称为“显示基板及其制备方法、显示装置”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本申请中。
技术领域
本文涉及但不限于显示技术领域，具体涉及一种显示基板及其制备方法、显示装置。
 背景技术
有机发光二极管(Organic Light Emitting Diode，简称OLED)和量子点发光二极管(Quantum-dot Light Emitting Diodes，简称QLED)为主动发光显示器件，具有自发光、广视角、高对比度、低耗电、极高反应速度、轻薄、可弯曲和成本低等优点。随着显示技术的不断发展，以OLED或QLED为发光器件、由薄膜晶体管(Thin Film Transistor，简称TFT)进行信号控制的柔性显示装置(Flexible Display)已成为目前显示领域的主流产品。
 发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制权利要求的保护范围。
一方面，本公开提供了一种显示基板，包括显示区域和设置在所述显示区域一侧的绑定区域，所述显示区域包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述绑定区域至少包括多条数据引出线；所述显示区域还包括多条数据信号线和多条数据连接线，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述数据信号线通过所述数据连接线与所述数据引出线连接；至少一条数据连接线包括至少两条沿着第一方向延伸的横向子线和至少两条沿着第二方向延伸的竖向子线，所述两条横向子线设置在不同的单元行中，所述两条竖向子线设置在不同的单元列中，所述第一方向和所述第二方向交叉。
在示例性实施方式中，至少一个单元行中设置有至少两条横向子线，所述两条横向子线连接不同的竖向子线。
在示例性实施方式中，至少一个单元列中设置有至少两条竖向子线，所述两条竖向子线连接不同的横向子线。
在示例性实施方式中，至少一条横向子线在显示基板上的正投影与至少一条竖向子线在显示基板上的正投影至少部分交叠。
在示例性实施方式中，在垂直于显示基板的方向上，所述显示区域包括多个导电层，所述两条横向子线设置在相同的导电层中，所述两条竖向子线设置在相同的导电层中，所述横向子线和所述竖向子线设置在不同的导电层中。
在示例性实施方式中，多个导电层至少包括设置在基底上的第一源漏金属层和设置在所述第一源漏金属层远离所述基底一侧的第二源漏金属层，所述横向子线设置在所述第一源漏金属层中，所述竖向子线设置在所述第二源漏金属层中。
在示例性实施方式中，所述至少两条横向子线至少包括第一横向子线和第二横向子线，所述至少两条竖向子线至少包括第一竖向子线和第二竖向子线；所述数据信号线通过所述数据连接线与所述数据引出线连接，包括：所述第一竖向子线的第一端与所述数据引出线连接，所述第一竖向子线的第二端向着远离所述绑定区域的方向延伸后，与所述第一横向子线的第一端连接，所述第一横向子线的第二端向着靠近所述第二竖向子线的方向延伸后，与所述第二竖向子线的第一端连接，所述第二竖向子线的第二端向着远离所述绑定区域的方向延伸后，与所述第二横向子线的第一端连接，所述第二横向子线的第二端向着靠近所述数据信号线的方向延伸后，与所述数据信号线连接。
在示例性实施方式中，所述显示区域还包括多个第一数据连接块；至少一个电路单元中，所述第一数据连接块与所述第一横向子线的第一端连接，所述第一竖向子线的第二端通过过孔与所述第一数据连接块连接；至少另一个电路单元中，所述第一数据连接块与所述第二横向子线的第一端连接，所述第二竖向子线的第二端通过过孔与所述第一数据连接块连接。
在示例性实施方式中，所述显示区域还包括多个数据转接条，至少一个电路单元中，所述第一横向子线的第一端通过所述数据转接条与所述第一数据连接块连接；至少另一个电路单元中，所述第二横向子线的第一端通过所述数据转接条与所述第一数据连接块连接。
在示例性实施方式中，至少一个电路单元中，所述第一横向子线、所述第一数据连接块和所述数据转接条为相互连接的一体结构；至少另一个电路单元中，所述第二横向子线、所述第一数据连接块和所述数据转接条为相互连接的一体结构。
在示例性实施方式中，所述显示区域还包括多个第一虚设电极，至少一个所述第一虚设电极在一个电路单元中的位置和连接结构与至少一个所述第一数据连接块在另一个电路单元中的位置和连接结构相同。
在示例性实施方式中，至少一个电路单元中，所述第一竖向子线通过过孔与至少一个所述第一虚设电极连接；至少另一个电路单元中，所述第二竖向子线通过过孔与至少一个所述第一虚设电极连接。
在示例性实施方式中，所述显示区域还包括多个第二数据连接块；至少一个电路单元中，所述第二数据连接块与所述第一横向子线的第二端连接，所述第二竖向子线的第一端通过过孔与所述第二数据连接块连接。
在示例性实施方式中，至少一个电路单元中，所述第一横向子线和所述第二数据连接块为相互连接的一体结构。
在示例性实施方式中，所述显示区域还包括多个第二虚设电极，至少一个所述第二虚设电极在一个电路单元中的位置和连接结构与至少一个所述第二数据连接块在另一个电路单元中的位置和连接结构相同。
在示例性实施方式中，至少一个电路单元中，所述第一竖向子线通过过孔与至少一个所述第二虚设电极连接；至少另一个电路单元中，所述第二竖向子线通过过孔与至少一个所述第二虚设电极连接。
另一方面，本公开还提供了一种显示装置，包括前述的显示基板。
又一方面，本公开还提供了一种显示基板的制备方法，所述显示基板包括显示区域和设置在所述显示区域一侧的绑定区域，所述显示区域包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路；所述制备方法包括：
在所述显示区域形成多条数据信号线和多条数据连接线，在所述绑定区域形成多条数据引出线，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述数据信号线通过所述数据连接线与所述数据引出线连接；至少一条数据连接线包括至少两条沿着第一方向延伸的横向子线和至少两条沿着第二方向延伸的竖向子线，所述两条横向子线设置在不同的单元行中，所述两条竖向子线设置在不同的单元列中，所述第一方向和所述第二方向交叉。
在阅读并理解了附图和详细描述后，可以明白其他方面。
 附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1为一种显示装置的结构示意图；
图2为一种显示基板的结构示意图；
图3为一种显示区域中显示区域的平面结构示意图；
图4为一种显示区域中显示区域的剖面结构示意图；
图5为一种像素驱动电路的等效电路图；
图6为一种显示基板中数据连接线的结构示意图；
图7为本公开示例性实施例一种数据连接线的结构示意图；
图8为本公开示例性实施例一种显示基板的结构示意图；
图9为本公开实施例形成第一半导体层图案后的示意图；
图10A和图10B为本公开实施例形成第一导电层图案后的示意图；
图11A和图11B为本公开实施例形成第二导电层图案后的示意图；
图12A和图12B为本公开实施例形成第二半导体层图案后的示意图；
图13A和图13B为本公开实施例形成第三导电层图案后的示意图；
图14为本公开实施例形成第六绝缘层图案后的示意图；
图15A和图15B为本公开实施例形成第四导电层图案后的示意图；
图16为本公开实施例形成第一平坦层图案后的示意图；
图17A和图17B为本公开实施例形成第五导电层图案后的示意图；
图17C为本公开示例性实施例横向子线和竖向子线连接的示意图；
图18为本公开实施例形成第二平坦层图案后的示意图；
图19A和图19B为本公开实施例形成阳极导电层图案后的示意图。
附图标记说明:11—第一有源层；            12—第二有源层；            13—第三有源层；14—第四有源层；            15—第五有源层；            16—第六有源层；17—第七有源层；            18—第八有源层；            21—第一扫描信号线；22—第二扫描信号线；       23—第三扫描信号线；       24—第四扫描信号线；25—发光信号线；            31—第一极板；              32—第二极板；33—开口；                  34—极板连接条；            35—遮挡线；41—第一初始信号线；        42—第二初始信号线；        43—第三初始信号线；51—第一连接电极；          52—第二连接电极；           53—第三连接电极；54—第四连接电极；          55—第五连接电极；           56—第六连接电极；57—第七连接电极；          58—第八连接电极；          59—第九连接电极；61—第一初始连接线；        62—第二初始连接线；        71—第一电源线；72—数据信号线；            73—阳极连接电极；          74—电源屏蔽块；80—数据引出线；            81—第一数据连接线；         82—第二数据连接线；83—数据转接条；            84—第一数据连接块；         85—第二数据连接块；86—第一虚设电极；           87—第二虚设电极；          91—第一电源走线；92—第二电源走线；          100—显示区域；             101—基底；102—驱动结构层；           103—发光结构层；           104—封装结构层；110—第一区域；             120—第二区域；             200—绑定区域；300—边框区域。
 具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。注意，实施方式可以以多个不同形式来实施。所属技术领域的普通技术人员可以很容易地理解一个事实，就是方式和内容可以在不脱离本公开的宗旨及其范围的条件下被变换为各种各样的形式。因此，本公开不应该被解释为仅限定在下面的实施方式所记载的内容中。在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开中的附图比例可以作为实际工艺中的参考，但不限于此。例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图，本公开的一个方式不局限于附图所示的形状或数值等。
本说明书中的“第一”、“第二”、“第三”等序数词是为了避免构成要素的混同而设置，而不是为了在数量方面上进行限定的。
在本说明书中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在说明书中说明的词句，根据情况可以适当地更换。
在本说明书中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以具体情况理解上述术语在本公开中的具体含义。
在本说明书中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区，并且电流能够流过漏电极、沟道区以及源电极。注意，在本说明书中，沟道区是指电流主要流过的区域。
在本说明书中，第一极可以为漏电极、第二极可以为源电极，或者第一极可以为源电极、第二极可以为漏电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本说明书中，“源电极”和“漏电极”可以互相调换，“源端”和“漏端”可以互相调换。
在本说明书中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本说明书中，“平行”是指两条直线状成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。另外，“垂直”是指两条直线状成的角度为80°以上且100°以下的状态，因此，也包括85°以上且95°以下的角度的状态。
在本说明书中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成为“导电膜”。与此同样，有时可以将“绝缘膜”换成为“绝缘层”。
本说明书中三角形、矩形、梯形、五边形或六边形等并非严格意义上的，可以是近似三角形、矩形、梯形、五边形或六边形等，可以存在公差导致的一些小变形，可以存在导角、弧边以及变形等。本公开中的“约”，是指不严格限定界限，允许工艺和测量误差范围内的数值。
图1为一种显示装置的结构示意图。如图1所示，显示装置可以包括时序控制器、数据驱动器、扫描驱动器、发光驱动器和像素阵列，时序控制器分别与数据驱动器、扫描驱动器和发光驱动器连接，数据驱动器分别与多个数据信号线(D1到Dn)连接，扫描驱动器分别与多个扫描信号线(S1到Sm)连接，发光驱动器分别与多个发光信号线(E1到Eo)连接。像素阵列可以包括多个子像素Pxij，i和j可以是自然数，至少一个子像素Pxij可以包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接，发光单元可以包括发光器件，发光器件与电路单元的像素驱动电路连接。在示例性实施方式中，时序控制器可以将适合于数据驱动器的规格的灰度值和控制信号提供到数据驱动器，可以将适合于扫描驱动器的规格的时钟信号、扫描起始信号等提供到扫描驱动器，可以将适合于发光驱动器的规格的时钟信号、发射停止信号等提供到发光驱动器。数据驱动器可以利用从时序控制器接收的灰度值和控制信号来产生将提供到数据信号线D1、D2、D3、……和Dn的数据电压。例如，数据驱动器可以利用时钟信号对灰度值进行采样，并且以像素行为单位将与灰度值对应的数据电压施加到数据信号线D1至Dn，n可以是自然数。扫描驱动器可以通过从时序控制器接收时钟信号、扫描起始信号等来产生将提供到扫描信号线S1、S2、S3、……和Sm的扫描信号。例如，扫描驱动器可以将具有导通电平脉冲的扫描信号顺序地提供到扫描信号线S1至Sm。例如，扫描驱动器可以被构造为移位寄存器的形式，并且可以在时钟信号的控制下顺序地将以导通电平脉冲形式提供的扫描起始信号传输到下一级电路的方式产生扫描信号，m可以是自然数。发光驱动器可以通过从时序控制器接收时钟信号、发射停止信号等来产生将提供到发光信号线E1、E2、E3、……和Eo的发射信号。例如，发光驱动器可以将具有截止电平脉冲的发射信号顺序地提供到发光信号线E1至Eo。例如，发光驱动器可以被构造为移位寄存器的形式，并且可以以在时钟信号的控制下顺序地将以截止电平脉冲形式提供的发射停止信号传输到下一级电路的方式产生发射信号，o可以是自然数。在示例性实施方式中，像素阵列可以设置在显示基板上。
图2为一种显示基板的结构示意图。如图2所示，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在示例性实施方式中，显示区域100可以是平坦的区域，包括组成像素阵列的多个子像素，多个子像素配置为显示动态图片或静止图像，显示区域100可以称为有效区域(Active Area，简称AA)。在示例性实施方式中，显示基板可以采用柔性基板，因而显示基板可以是可变形的，例如卷曲、弯曲、折叠或卷起。
在示例性实施方式中，绑定区域200可以包括沿着远离显示区域方向依次设置的引出线区、弯折区、驱动芯片区和绑定引脚区，引出线区连接到显示区域100，至少包括数据引出线。弯折区连接到引出线区，可以至少包括设置有凹槽的复合绝缘层，凹槽被配置为使绑定区域弯折到显示区域的背面。驱动芯片区可以包括集成电路(Integrated Circuit，简称IC)，集成电路被配置为与多条数据引出线连接。绑定引脚区可以包括绑定焊盘(Bonding Pad)，绑定焊盘被配置为与外部的柔性线路板(Flexible Printed Circuit，简称FPC)绑定连接。
在示例性实施方式中，边框区域300可以包括沿着远离显示区域100的方向依次设置的电路区、电源线区、裂缝坝区和切割区。电路区连接到显示区域100，可以至少包括栅极驱动电路，栅极驱动电路与显示区域100中的扫描信号线和发光信号线连接。电源线区连接到电路区，可以至少包括边框电源引线，边框电源引线沿着平行于显示区域边缘的方向延伸，与显示区域100中的阴极连接。裂缝坝区连接到电源线区，可以至少包括在复合绝缘层上设置的多个裂缝。切割区连接到裂缝坝区，可以至少包括在复合绝缘层上设置的切割槽，切割槽被配置为在显示基板的所有膜层制备完成后，切割设备分别沿着切割槽进行切割。
在示例性实施方式中，绑定区域200中的引出线区和边框区域300中的电源线区可以设置有隔离坝，隔离坝可以沿着平行于显示区域边缘的方向延伸，形成环绕显示区域100的环形结构，显示区域边缘是显示区域绑定区域或者边框区域一侧的边缘。
图3为一种显示基板中显示区域的平面结构示意图。如图3所示，显示区域可以包括以矩阵方式排布的多个像素单元P，至少一个像素单元P可以包括第一子像素P1、第二子像素P2、第三子像素P3和第四子像素P4。每个子像素可以均包括电路单元和发光单元，电路单元可以至少包括像素驱动电路，像素驱动电路分别与扫描信号线、发光信号线和数据信号线连接，像素驱动电路被配置为在扫描信号线和发光信号线的控制下，接收数据信号线传输的数据电压，向发光单元输出相应的电流。发光单元可以包括发光器件，发光器件与所在子像素的像素驱动电路连接，发光器件被配置为响应所在子像素的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，第一子像素P1可以是出射红色光线的红色子像素(R)，第二子像素P2可以是出射蓝色光线的蓝色子像素(B)，第三子像素P3和第四子像素P4可以是出射绿色光线的绿色子像素(G)。在示例性实施方式中，子像素的形状可以是矩形状、菱形、五边形或六边形，四个子像素可以采用RGBG方式排列。
在其它示例性实施方式中，像素单元可以包括三个子像素，三个子像素可以采用水平并列或者竖直并列等方式排列，本公开在此不做限定。
图4为一种显示基板中显示区域的剖面结构示意图，示意了显示区域中四个子像素的结构。如图4所示，在垂直于显示基板的平面上，显示基板可以包括设置在基底101上的驱动电路层102、设置在驱动电路层102远离基底101一侧的发光结构层103以及设置在发光结构层103远离基底101一侧的封装结构层104。在一些可能的实现方式中，显示基板可以包括其它膜层，如触控结构层等，本公开在此不做限定。
在示例性实施方式中，基底101可以是柔性基底，或者可以是刚性基底。驱动电路层102可以包括多个电路单元，每个电路单元可以至少包括由多个晶体管和存储电容构成的像素驱动电路。发光结构层103可以包括多个发光单元，每个发光单元可以包括发光器件，发光器件可以至少包括阳极、有机发光层和阴极，阳极与像素驱动电路连接，有机发光层与阳极连接，阴极与有机发光层连接，有机发光层在阳极和阴极驱动下出射相应颜色的光线。封装结构层104可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，形成无机材料/有机材料/无机材料叠层结构，可以保证外界水汽无法进入发光结构层103。
图5为一种像素驱动电路的等效电路示意图。在示例性实施方式中，像素驱动电路可以是3T1C、4T1C、5T1C、5T2C、6T1C、7T1C或8T1C结构。如图5所示，像素驱动电路可以包括8个晶体管(第一晶体管T1至第八晶体管T8)和1个存储电容C，像素驱动电路分别与10条信号线(第一扫描信号线S1、第二扫描信号线S2、第三扫描信号线S3、第四扫描信号线S4、发光信号线EM、第一初始信号线INIT1、第二初始信号线INIT2、第三初始信号线INIT3、数据信号线DATA和第一电源线VDD)连接。
在示例性实施方式中，像素驱动电路可以包括第一节点N1、第二节点N2、第三节点N3和第四节点N4。其中，第一节点N1分别与第二晶体管T2的第一极、第三晶体管T3的栅电极和存储电容C的第一端连接，第二节点N2分别与第三晶体管T3的第一极、第四晶体管T4的第二极、第五晶体管T5的第二极和第八晶体管T8的第二极连接，第三节点N3分别与第一晶体管T1的第二极、第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接，第四节点N4分别与第六晶体管T6的第二极和第七晶体管T7的第二极连接。
在示例性实施方式中，存储电容C的第一端与第一节点N1连接，存储电容C的第二端与第一电源线VDD连接。
在示例性实施方式中，第一晶体管T1可以称为第一复位晶体管，第一晶体管T1的栅电极与第三扫描信号线S3连接，第一晶体管T1的第一极与第一初始信号线INIT1连接，第一晶体管T1的第二极与第三节点N3连接。
在示例性实施方式中，第二晶体管T2可以称为补偿晶体管，第二晶体管T2的栅电极与第四扫描信号线S4连接，第二晶体管T2的第一极与第一节点N1连接，第二晶体管T2的第二极与第三节点N3连接。
在示例性实施方式中，第三晶体管T3可以称为驱动晶体管，第三晶体管T3的栅电极与第一节点N1连接，第三晶体管T3的第一极与第二节点N2连接，第三晶体管T3的第二极与第三节点N3连接。
在示例性实施方式中，第四晶体管T4可以称为数据写入晶体管，第四晶体管T4的栅电极与第一扫描信号线S1连接，第四晶体管T4的第一极与数据信号线DATA连接，第四晶体管T4的第二极与第二节点N2连接。
在示例性实施方式中，第五晶体管T5可以称为第一发光控制晶体管，第五晶体管T5的栅电极与发光信号线EM连接，第五晶体管T5的第一极与第一电源线VDD连接，第五晶体管T5的第二极与第二节点N2连接。
在示例性实施方式中，第六晶体管T6可以称为第二发光控制晶体管，第六晶体管T6的栅电极与发光信号线EM连接，第六晶体管T6的第一极与第三节点N3连接，第六晶体管T6的第二极与第四节点N4连接。
在示例性实施方式中，第七晶体管T7可以称为第二复位晶体管，第七晶体管T7的栅电极与第二扫描信号线S2连接，第七晶体管T7的第一极与第二初始信号线INIT2连接，第七晶体管T7的第二极与第四节点N4连接。
在示例性实施方式中，第八晶体管T8可以称为第三复位晶体管，第八晶体管T8的栅电极与第二扫描信号线S2连接，第八晶体管T8的第一极与第三初始信号线INIT3连接，第八晶体管T8的第二极与第二节点N2连接。
在示例性实施方式中，发光器件EL的第一极与第四节点N4连接，发光器件EL的第二极与第二电源线VSS连接。发光器件EL可以是OLED，包括叠设的第一极(阳极)、有机发光层和第二极(阴极)，或者可以是QLED，包括叠设的第一极(阳极)、量子点发光层和第二极(阴极)。
在示例性实施方式中，第一电源线VDD配置为向像素驱动电路提供恒定的第一电压信号，第二电源线VSS被配置为向发光器件提供恒定的第二电压信号，并且第一电压信号为高电平信号，第二电压信号为低电平信号。第一初始电压信号、第二初始电压信号和第三初始电压信号可以为恒压信号，本公开在此不做限定。
在示例性实施方式中，第一晶体管T1至第八晶体管T8可以是P型晶体管，或者可以是N型晶体管。像素驱动电路中采用相同类型的晶体管可以简化工艺流程，减少显示面板的工艺难度，提高产品的良率。在一些可能的实现方式中，第一晶体管T1至第八晶体管T8可以包括P型晶体管和N型晶体管。
在示例性实施方式中，第一晶体管T1至第八晶体管T8可以采用低温多晶硅晶体管，或者可以采用氧化物晶体管，或者可以采用低温多晶硅晶体管和金属氧化物晶体管。低温多晶硅晶体管的有源层采用低温多晶硅(Low Temperature Poly-Silicon，简称LTPS)，金属氧化物晶体管的有源层采用金属氧化物半导体(Oxide)。低温多晶硅晶体管具有迁移率高、充电快等优点，氧化物晶体管具有漏电流低等优点，将低温多晶硅晶体管和金属氧化物晶体管集成在一个显示基板上，形成LTPO(Low Temperature Polycrystalline+Oxide)显示基板，可以利用两者的优势，可以实现低频驱动，可以降低功耗，可以提高显示品质。
在示例性实施方式中，第二晶体管T2可以采用金属氧化物晶体管，第一晶体管T1、第三晶体管T3至第八晶体管T8可以采用低温多晶硅晶体管。
随着显示技术的发展，消费者对显示产品显示效果和显示品质的要求越来越高，全面屏和窄边框等产品以其较大的屏占比和超窄边框，已逐步成为显示产品的发展趋势，因此边框的窄化甚至无边框设计在OLED显示产品设计中越来越受到重视。一种显示基板中，采用扇出线位于面板(Fanout in Panel，简称FIP)结构，多条数据连接线设置在显示区域，多条数据连接线的一端与显示区域中的多条数据信号线对应连接，多条数据连接线的另一端延伸到绑定区域，通过引出线区的多条数据引出线与集成电路对应连接。由于引出线区不需要设置扇形状的斜线，减小了引出线区的宽度，因而缩减了下边框宽度。
图6为一种显示基板中数据连接线的结构示意图。如图6所示，显示区域100可以包括多条数据信号线72、多条第一数据连接线81和多条第二数据连接线82，绑定区域200可以包括多条数据引出线80。多条第一数据连接线81的形状可以为沿着第一方向X延伸的直线状或者折线状，多条数据信号线72、多条第二数据连接线82和多条数据引出线80的形状可以为沿着第二方向Y延伸的直线状或者折线状。
在示例性实施方式中，至少一条数据信号线72与一个单元列中的多个像素驱动电路连接，数据信号线72被配置为向所连接的像素驱动电路提供数据信号。多条第一数据连接线81在第二方向Y上以设定的间隔依次设置，多条第二数据连接线82在第一方向X上以设定的间隔依次设置，形成逐层向外排布的结构。第二数据连接线82的第一端与绑定区域200中的数据引出线80连接，第二数据连接线82的第二端与第一数据连接线81的第一端连接，第一数据连接线81的第二端与数据信号线72连接，使得显示区域中的数据信号线72通过第一数据连接线81和第二数据连接线82与绑定区域中的数据引出线80连接，形成FIP结构(也称为FIAA结构)。在示例性实施方式中，第一数据连接线81和第二数据连接线82一起称为数据连接线。
在示例性实施方式中，由于数据连接线设置在显示区域中的部分区域，因而可以按照有无数据连接线作为划分依据，显示区域可以划分为第一区域110和第二区域120，第一区域110可以是设置有第一数据连接线81和第二数据连接线82的区域(图6中的深色区域)，第二区域120可以是没有设置第一数据连接线81和第二数据连接线82的区域(图6中深色区域之外的区域)。在示例性实施方式中，第一区域110可以称为FIP区域，第二区域120可以称为非FIP区域。
目前，采用FIP结构的OLED显示装置存在斜纹水印(mura)等问题。经研究发现，斜纹水印问题是由于多条第一数据连接线耦合单元列的数量差距较大导致的。如图6所示，离绑定区域距离较远的第一数据连接线的延伸长度较长，其与较多的单元列耦合，离绑定区域距离较近的第一数据连接线的延伸长度较短，其与较少的单元列耦合。由于不同单元行中第一数据连接线耦合单元列的数量差距较大，使得显示区域靠近绑定区域一侧的两个角部出现斜纹水印。
为了消除斜纹水印，本公开示例性实施例提供了一种显示基板。在示例性实施方式中，显示基板包括显示区域和设置在所述显示区域一侧的绑定区域，所述显示区域包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述绑定区域至少包括多条数据引出线；所述显示区域还包括多条数据信号线、多条第一数据连接线、以及多条第二数据连接线，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述数据引出线通过所述第一数据连接线和所述第二数据连接线与所述数据信号线连接；至少一条第一数据连接线包括至少两条沿着第一方向延伸的横向子线，所述两条横向子线设置在不同的单元行中，至少一条第二数据连接线包括至少两条沿着第二方向延伸的竖向子线，所述两条竖向子线设置在不同的单元列中，所述第一方向和所述第二方向交叉。
在示例性实施方式中，至少一个单元行中设置有至少两条横向子线，所述两条横向子线连接不同的竖向子线。
在示例性实施方式中，至少一个单元列中设置有至少两条竖向子线，所述两条竖向子线连接不同的横向子线。
在示例性实施方式中，至少一条横向子线在显示基板上的正投影与至少一条竖向子线在显示基板上的正投影至少部分交叠。
在示例性实施方式中，所述两条横向子线为第一横向子线和第二横向子线，所述两条竖向子线为第一竖向子线和第二竖向子线；所述数据信号线通过所述数据连接线与所述数据引出线连接，包括：所述第一竖向子线的第一端与所述数据引出线连接，所述第一竖向子线的第二端向着远离所述绑定区域的方向延伸后，与所述第一横向子线的第一端连接，所述第一横向子线的第二端向着靠近所述第二竖向子线的方向延伸后，与所述第二竖向子线的第一端连接，所述第二竖向子线的第二端向着远离所述绑定区域的方向延伸后，与所述第二横向子线的第一端连接，所述第二横向子线的第二端向着靠近所述数据信号线的方向延伸后，与所述数据信号线连接。
本公开示例性实施例提供了一种显示基板，采用扇出线位于面板(Fanout in Panel，简称FIP)结构。在示例性实施方式中，在平行于显示基板的平面内，显示基板可以包括显示区域100、位于显示区域100一侧的绑定区域200以及位于显示区域100其它侧的边框区域300。在垂直于显示基板的方向上，显示基板可以至少包括设置在基底上的驱动结构层以及设置在驱动结构层远离基底一侧的发光结构层，显示区域100的驱动结构层可以包括多个电路单元，显示区域100的发光结构层可以包括多个发光单元。
在示例性实施方式中，多个电路单元可以形成多个单元行和多个单元列，每个单元行中的多个电路单元沿着第一方向X依次设置，每个单元列中的多个电路单元沿着第二方向Y依次设置，构成阵列排布的电路单元阵列，第一方向X与第二方向Y交叉。多个发光单元可以形成多个发光行和多个发光列，每个发光行中的多个发光单元沿着第一方向X依次设置，每个发光列中的多个发光单元沿着第二方向Y依次设置，构成阵列排布的发光单元阵列。在示例性实施方式中，至少一个电路单元可以至少包括像素驱动电路，至少一个电路单元可以包括发光器件，发光器件与对应电路单元的像素驱动电路连接，发光器件被配置为响应所连接的像素驱动电路输出的电流发出相应亮度的光。
在示例性实施方式中，本公开中所说的电路单元，是指按照像素驱动电路划分的区域，本公开中所说的发光单元，是指按照发光器件划分的区域。在示例性实施方式中，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是对应的，或者，发光单元在基底上正投影的位置与电路单元在基底上正投影的位置可以是不对应的。
图7为本公开示例性实施例一种数据连接线的结构示意图。如图7所示，显示区域100可以包括多条数据信号线72和多条数据连接线，绑定区域200可以包括多条数据引出线80。多条数据信号线72和多条数据引出线80的形状可以为沿着第二方向Y延伸的直线状或者折线状，多条数据连接线的形状可以为折线状，既包括沿着第一方向X延伸的直线状，又包括沿着第二方向Y延伸的直线状。数据信号线72被配置为向所连接的像素驱动电路提供数据信号，且数据信号线72通过数据连接线与数据引出线80连接。具体地，多条数据连接线的第一端与绑定区域200中的多条数据引出线80对应连接，多条数据连接线的第二端向着远离绑定区域200的方向延伸后，与多条数据信号线72对应连接，使得显示区域中的数据信号线72通过数据连接线与绑定区域中的数据引出线80连接，形成FIP结构(也称为FIAA结构)。由于数据连接线设置在显示区域，引出线区不需要设置扇形状的斜线，因而减小了绑定区域第二方向Y的长度，缩减了下边框宽度，提高了屏占比，有利于实现全面屏显示。
在示例性实施方式中，显示区域100可以具有中心线O，多条数据信号线72、多条数据连接线和多条数据引出线80可以相对于中心线O镜像对称，中心线O可以是平分多个显示区域中的多个单元列且沿着第二方向Y延伸的直线。
在示例性实施方式中，至少一条数据连接线可以包括至少两条横向子线和至少两条竖向子线，横向子线的形状可以为沿着第一方向X延伸的直线状或者折线状，竖向子线的形状可以为沿着第二方向Y延伸的直线状或者折线状，两条横向子线可以设置在不同的单元行中，两条竖向子线可以设置在不同的单元列中，且横向子线和竖向子线相互连接，形成包括横向子线和竖向子线的折线状的数据连接线。
在示例性实施方式中，至少一个单元行中可以设置有至少两条横向子线，两条横向子线可以连接不同的竖向子线。
在示例性实施方式中，至少一个单元列中可以设置有至少两条竖向子线，两条竖向子线可以连接不同的横向子线。
在示例性实施方式中，至少一条横向子线在显示基板上的正投影与至少一条竖向子线在显示基板上的正投影至少部分交叠。
在示例性实施方式中，两条横向子线可以是沿着第一方向X延伸的第一横向子线81-1和第二横向子线81-2，两条竖向子线可以是沿着第二方向Y延伸的第一竖向子线82-1和第二竖向子线82-2。第一横向子线81-1和第二横向子线81-2分别设置在不同的单元行中，第一横向子线81-1可以设置在靠近绑定区域的单元行中，第二横向子线81-2可以设置在第一横向子线81-1远离绑定区域一侧的单元行中。第一竖向子线82-1和第二竖向子线82-2分别设置在不同的单元列中，第一竖向子线82-1可以设置在靠近中心线O的单元列中，第二竖向子线82-2可以设置在第一竖向子线82-1远离中心线O一侧的单元列中。
在示例性实施方式中，在第一方向X上，第一横向子线81-1可以设置在第一竖向子线82-1远离中心线O的一侧，第二竖向子线82-2可以设置在第一横向子线81-1远离中心线O的一侧，第二横向子线81-2可以设置在第二竖向子线82-2远离中心线O的一侧。在第二方向Y上，第一横向子线81-1可以设置在第一竖向子线82-1远离绑定区域的一侧，第二竖向子线82-2可以设置在第一横向子线81-1远离绑定区域的一侧，第二横向子线81-2可以设置在第二竖向子线82-2远离绑定区域的一侧。
在示例性实施方式中，数据信号线72通过数据连接线与数据引出线80连接可以包括：第一竖向子线82-1的第一端与数据引出线80连接，第一竖向子线82-1的第二端向着远离绑定区域的方向延伸后，与第一横向子线81-1的第一端连接，第一横向子线81-1的第二端向着远离中心线O的方向(靠近第二竖向子线82-2的方向)延伸后，与第二竖向子线82-2的第一端连接，第二竖向子线82-2的第二端向着远离绑定区域的方向延伸后，与第二横向子线81-2的第一端连接，第二横向子线81-2的第二端向着远离中心线O的方向(靠近数据信号线72的方向)延伸后，与数据信号线72连接。
在示例性实施方式中，至少一条横向子线可以与两条竖向子线连接。例如，第一横向子线81-1的第一端与第一竖向子线82-1连接，第一横向子线81-1的第二端与第二竖向子线82-2连接。
在示例性实施方式中，至少一条竖向子线可以与两条横向子线连接。例如，第二竖向子线82-2的第一端与第一横向子线81-1连接，第二竖向子线82-2的第二端与第二横向子线81-2连接。
在示例性实施方式中，第一横向子线81-1和第二横向子线81-2可以称为第一数据连接线81，第一竖向子线82-1和第二竖向子线82-2可以称为第二数据连接线82，即数据连接线可以包括第一数据连接线81和第二数据连接线82，第一数据连接线81可以包括第一横向子线81-1和第二横向子线81-2，第二数据连接线82可以包括第一竖向子线82-1和第二竖向子线82-2。
在示例性实施方式中，显示区域中的数据连接线的数量与数据信号线的数量可以相同，每条数据信号线通过一条数据连接线与一条引出线对应连接。或者，显示区域中的数据连接线的数量可以小于数据信号线的数量，显示区域中的一部分数据信号线通过数据连接线与数据引出线对应连接，另一部分数据信号线与数据引出线直接连接，本公开在此不做限定。
在示例性实施方式中，数据引出线80与数据信号线72和数据连接线可以直接连接，或者可以通过过孔连接，本公开在此不做限定。
在示例性实施方式中，显示区域可以划分为第一区域110和第二区域120，第一区域110可以是设置有横向子线和竖向子线的区域(图7中的深色区域)，第二区域120可以是没有设置横向子线和竖向子线的区域(图7中深色区域之外的区域)。
图8为本公开示例性实施例一种显示基板的平面结构示意图，示意了图7中A区域的结构。在示例性实施方式中，显示区域可以包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元可以包括像素驱动电路，像素驱动电路分别与第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第四扫描信号线24、发光信号线25、第一初始信号线41、第二初始信号线42、第三初始信号线43、第一电源线71和数据信号线72连接。
在示例性实施方式中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第四扫描信号线24和发光信号线25被配置为分别向像素驱动电路提供第一扫描信号、第二扫描信号、第三扫描信号、第四扫描信号和发光控制信号，第一初始信号线41、第二初始信号线42和第三初始信号线43被配置为分别向像素驱动电路提供第一初始信号、第二初始信号和第三初始信号，第一电源线71被配置为向像素驱动电路提供第一电源信号，数据信号线72被配置为向像素驱动电路提供数据信号。其中，与像素驱动电路连接的多条信号线可以位于相应电路单元内。
在示例性实施方式中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、第四扫描信号线24、发光信号线25、第一初始信号线41、第二初始信号线42和第三初始信号线43的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第一电源线71和数据信号线72的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状。
本公开中，A沿着B方向延伸是指，A可以包括主要部分和与主要部分连接的次要部分，主要部分是线、线段或条形状体，主要部分沿着B方向伸展，且主要部分沿着B方向伸展的长度大于次要部分沿着其它方向伸展的长度。以下描述中所说的“A沿着B方向延伸”均是指“A的主体部分沿着B方向延伸”。
在示例性实施方式中，像素驱动电路可以至少包括存储电容和多个晶体管。存储电容可以包括叠设的第一极板和第二极板，多个晶体管可以包括作为第一复位晶体管的第一晶体管T1、作为补偿晶体管的第二晶体管T2、作为驱动晶体管的第三晶体管T3、作为数据写入晶体管的第四晶体管T4、作为第一发光控制晶体管的第五晶体管T5、作为第二发光控制晶体管的第六晶体管T6、作为第二复位晶体管的第七晶体管T7、以及作为第三复位晶体管的第八晶体管T8。其中，第二晶体管T2可以为金属氧化物晶体管，第一晶体管T1、第三晶体管T3至第八晶体管T8可以为低温多晶硅晶体管。
在示例性实施方式中，第一晶体管T1的栅电极与第三扫描信号线23连接，第一晶体管T1的第一极与第一初始信号线41连接，第一晶体管T1的第二极分别与第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极连接。第二晶体管T2的栅电极与第四扫描信号线24连接，第二晶体管T2的第一极和存储电容的第一极板(也是第三晶体管T3的栅电极)连接。第三晶体管T3的第一极分别与第四晶体管T4的第二极、第五晶体管T5的第二极和第八晶体管T8的第二极连接。第四晶体管T4的栅电极与第一扫描信号线21连接，第四晶体管T4的第一极与数据信号线72连接。第五晶体管T5的栅电极与发光信号线25连接，第五晶体管T5的第一极与第一电源线71连接。第六晶体管T6的栅电极与发光信号线25连接，第六晶体管T6的第二极与第七晶体管T7的第二极连接。第七晶体管T7的栅电极与第二扫描信号线22连接，第七晶体管T7的第一极与第二初始信号线42连接。第八晶体管T8的栅电极与第二扫描信号线22连接，第八晶体管T8的第一极与第三初始信号线43连接。
在示例性实施方式中，至少一个电路单元中，第四扫描信号线24可以设置在存储电容(第三晶体管T3)第二方向Y的反方向的一侧，第一扫描信号线21可以设置在第四扫描信号线24远离存储电容的一侧，第三扫描信号线23和第二初始信号线42可以设置在第一扫描信号线21远离存储电容的一侧，第一初始信号线41可以设置在第三扫描信号线23远离存储电容的一侧。发光信号线25可以设置在存储电容第二方向Y的一侧，第二扫描信号线22和第三初始信号线43可以设置在发光信号线25远离存储电容的一侧。
在示例性实施方式中，第二初始信号线42在基底上的正投影与第三扫描信号线23在基底上的正投影至少部分交叠，第三初始信号线43在基底上的正投影与第二扫描信号线22在基底上的正投影至少部分交叠。
在示例性实施方式中，至少一个电路单元还可以包括第一初始连接线61。第一初始连接线61的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，且与第一初始信号线41连接，第一初始信号线41和第一初始连接线61形成网状的传输第一初始信号的网状连通结构。
在示例性实施方式中，至少一个电路单元还可以包括第二初始连接线62。第二初始连接线62的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，且与第二初始信号线42连接，第二初始信号线42和第二初始连接线62形成网状的传输第二初始信号的网状连通结构。
在示例性实施方式中，显示区域还可以包括多条数据连接线，至少一条数据连接线可以包括第一横向子线81-1、第二横向子线81-2、第一竖向子线82-1和第二竖向子线82-2。第一横向子线81-1和第二横向子线81-2的形状可以是沿着第一方向X延伸的直线状或者折线状，第一横向子线81-1可以设置在第M+5单元行中，第二横向子线81-2可以设置在第M单元行中。第一竖向子线82-1和第二竖向子线82-2的形状可以是沿着第二方向Y延伸的直线状或者折线状，第一竖向子线82-1可以设置在第N+10单元列与第N+11单元列之间，第二竖向子线82-2可以设置在第N单元列与第N+1单元列之间。
在示例性实施方式中，第一竖向子线82-1的第一端与绑定区域的数据引出线连接，第一竖向子线82-1的第二端沿着第二方向Y的反方向(向着靠近第一横向子线81-1的方向)延伸后，与第一横向子线81-1的第一端连接，第一横向子线81-1的第二端沿着第一方向X的反方向(向着靠近第二竖向子线82-2的方向)延伸后，与第二竖向子线82-2的第一端连接，第二竖向子线82-2的第二端沿着第二方向Y的反方向(向着靠近第二横向子线81-2的方向)延伸后，与第二横向子线81-2的第一端连接，第二横向子线81-2的第二端沿着第一方向X的反方向(向着靠近数据信号线72的方向)延伸后，与数据信号线72连接。
在示例性实施方式中，至少一个电路单元还可以包括数据转接条83和第一数据连接块84。数据转接条83的形状可以为沿着第二方向Y延伸的条形状，第一数据连接块84的形状可以为块形(如矩形)状，数据转接条83的第一端与第一横向子线81-1或者第二横向子线81-2连接，数据转接条83的第二端与第一数据连接块84连接，第一数据连接块84被配置为与第一竖向子线82-1或者第二竖向子线82-2连接。例如，在第M单元行中，第一数据连接块84通过数据转接条83与第二横向子线81-2连接，第二竖向子线82-2的第二端与第一数据连接块84连接，实现了第二竖向子线82-2的第二端与第二横向子线81-2的第一端之间的连接。又如，在第M+5单元行中，第一数据连接块84通过数据转接条83与第一横向子线81-1连接，第一竖向子线82-1的第二端与第一数据连接块84连接，实现了第一竖向子线82-1的第二端与第一横向子线81-1的第一端之间的连接。
在示例性实施方式中，至少一个电路单元还可以包括第二数据连接块85。第二数据连接块85的形状可以为块形(如矩形)状，且与第一横向子线81-1的第二端连接，第二数据连接块85被配置为与第二竖向子线82-2的第一端连接。例如，在第M+5单元行中，第二数据连接块85与第一横向子线81-1的第二端连接，第二竖向子线82-2的第一端与第二数据连接块85连接，实现了第一横向子线81-1的第二端与第二竖向子线82-2的第一端之间的连接。
在示例性实施方式中，至少一个电路单元还可以包括第一虚设电极86，第一虚设电极86的形状可以为块形(如矩形)状，被配置为与竖向子线连接。第一虚设电极86在一个电路单元中的位置和连接结构可以与第一数据连接块84在另一个电路单元中的位置和连接结构基本上相同，所不同的是，第一虚设电极86为隔离设置。
在示例性实施方式中，至少一个电路单元还可以包括第二虚设电极87第二虚设电极87的形状可以为块形(如矩形)状，被配置为与竖向子线连接。第二虚设电极87在一个电路单元中的位置和连接结构可以与第二数据连接块85在另一个电路单元中的位置和连接结构基本上相同，所不同的是，第二虚设电极87为隔离设置。
在示例性实施方式中，在垂直于显示基板的方向上，显示区域的驱动结构层可以包括多个导电层，横向子线可以设置在相同的导电层中，竖向子线可以设置在相同的导电层中，横向子线和竖向子线可以设置在不同的导电层中。
在示例性实施方式中，多个导电层可以至少包括设置在基底上的第一源漏金属层(SD1)和设置在第一源漏金属层远离基底一侧的第二源漏金属层(SD2)，横向子线可以设置在第一源漏金属层中，竖向子线可以设置在第二源漏金属层中。
在示例性实施方式中，第一数据连接块84、第二数据连接块85、第一虚设电极86和第二虚设电极87可以设置在第一源漏金属层中。
下面通过显示基板的制备过程进行示例性说明。本公开所说的“图案化工艺”，对于金属材料、无机材料或透明导电材料，包括涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，对于有机材料，包括涂覆有机材料、掩模曝光和显影等处理。沉积可以采用溅射、蒸镀、化学气相沉积中的任意一种或多种，涂覆可以采用喷涂、旋涂和喷墨打印中的任意一种或多种，刻蚀可以采用干刻和湿刻中的任意一种或多种，本公开不做限定。“薄膜”是指将某一种材料在基底上利用沉积、涂覆或其它工艺制作出的一层薄膜。若在整个制作过程当中该“薄膜”无需图案化工艺，则该“薄膜”还可以称为“层”。若在整个制作过程当中该“薄膜”需图案化工艺，则在图案化工艺前称为“薄膜”，图案化工艺后称为“层”。经过图案化工艺后的“层”中包含至少一个“图案”。本公开所说的“A和B同层设置”是指，A和B通过同一次图案化工艺同时形成，膜层的“厚度”为膜层在垂直于显示基板方向上的尺寸。本公开示例性实施方式中，“B的正投影位于A的正投影的范围之内”或者“A的正投影包含B的正投影”是指，B的正投影的边界落入A的正投影的边界范围内，或者A的正投影的边界与B的正投影的边界重叠。
在示例性实施方式中，以72个电路单元(6个单元行12个单元列)为例，显示基板的制备过程可以包括如下操作。
(1)形成第一半导体层图案。在示例性实施方式中，形成第一半导体层图案可以包括：在基底上依次沉积第一绝缘薄膜和第一半导体薄膜，通过图案化工艺对第一半导体薄膜进行图案化，形成设置在基底上的第一绝缘层，以及设置在第一绝缘层上的第一半导体层图案，如图9所示。
在示例性实施方式中，每个电路单元的第一半导体层图案可以至少包括第一晶体管T1的第一有源层11、第三晶体管T3的第三有源层13至第八晶体管T8的第八有源层18，且第三有源层13至第七有源层17为相互连接的一体结构，第一有源层11和第八有源层18单独设置。
在示例性实施方式中，在第一方向X上，第一有源层11和第六有源层16可以位于本电路单元中第三有源层13的一侧，第四有源层14和第五有源层15可以位于本电路单元中第三有源层13的另一侧。在第二方向Y上，第一有源层11和第四有源层14可以位于本电路单元中第三有源层13第二方向Y的反方向的一侧，第五有源层15、第六有源层16、第七有源层17和第八有源层18可以位于本电路单元中第三有源层13第二方向Y的一侧。
在示例性实施方式中，第三有源层13的形状可以呈“Ω”字形状，第四有源层14和第六有源层16的形状可以呈“L”字形状，第一有源层11、第五有源层15、第七有源层17和第八有源层18的形状可以呈“I”字形状。
在示例性实施方式中，第一有源层11、第三有源层13至第八有源层18可以均包括第一区、第二区以及位于第一区和第二区之间的沟道区。在示例性实施方式中，第三有源层的第一区13-1、第四有源层的第二区14-2和第五有源层的第二区15-2可以相互连接，第三有源层的第一区13-1可以同时作为第四有源层的第二区14-2和第五有源层的第二区15-2。第三有源层的第二区13-2和第六有源层的第一区16-1可以相互连接，第三有源层的第二区13-2可以作为第六有源层的第一区16-1。第六有源层的第二区16-2和第七有源层的第二区17-2可以相互连接，第六有源层的第二区16-2可以作为第七有源层的第二区17-2。第一有源层的第一区11-1、第一有源层的第二区11-2、第四有源层的第一区14-1、第五有源层的第一区15-1、第七有源层的第一区17-1、第八有源层的第一区18-1和第八有源层的第二区18-2可以单独设置。
在示例性实施方式中，一个单元行中，部分相邻两个电路单元中的第五有源层的第一区15-1可以相互连接，两个电路单元中的第五有源层可以为相互连接的一体结构。例如，第N单元列的第五有源层和第N+1单元列的第五有源层可以为相互连接的一体结构，第N+2单元列的第五有源层和第N+3单元列的第五有源层可以为相互连接的一体结构，第N+4单元列的第五有源层和第N+5单元列的第五有源层可以为相互连接的一体结构，第N+6单元列的第五有源层和第N+7单元列的第五有源层可以为相互连接的一体结构，第N+8单元列的第五有源层和第N+9单元列的第五有源层可以为相互连接的一体结构，第N+10单元列的第五有源层和第N+11单元列的第五有源层可以为相互连接的一体结构。由于每个电路单元中的第五有源层的第一区被配置为与后续形成的第一电源线连接，通过将相邻电路单元的第五有源层形成相互连接的一体结构，可以保证相邻电路单元的第五晶体管T5的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，相邻单元列的第一半导体层可以相对于列分界线镜像对称。例如，第N单元列的第一半导体层和第N+1单元列的第一半导体层可以相对于列分界线镜像对称，第N+1单元列的第一半导体层和第N+2单元列的第一半导体层可以相对于列分界线镜像对称。在示例性实施方式中，多个单元行中第一半导体层的形状可以基本上相同。
在示例性实施方式中，第一半导体层可以采用多晶硅(p-Si)，即第一晶体管、第三晶体管至第七晶体管为LTPS晶体管。在示例性实施方式中，通过图案化工艺对第一半导体薄膜进行图案化可以包括：先在第一绝缘薄膜上形成非晶硅(a-si)薄膜，对非晶硅薄膜进行脱氢处理，对脱氢处理后的非晶硅薄膜进行结晶处理，形成多晶硅薄膜。随后，对多晶硅薄膜进行图案化，形成第一半导体层图案。
(2)形成第一导电层图案。在示例性实施方式中，形成第一导电层图案可以包括：在形成前述图案的基底上，依次沉积第二绝缘薄膜和第一导电薄膜，通过图案化工艺对第一导电薄膜进行图案化，形成覆盖第一半导体层图案的第二绝缘层，以及设置在第二绝缘层上的第一导电层图案，如图10A和图10B所示，图10B为图10A中第一导电层的平面示意图。在示例性实施方式中，第一导电层可以称为第一栅金属(GATE1)层。
在示例性实施方式中，每个电路单元的第一导电层图案至少包括：第一扫描信号线21、第二扫描信号线22、第三扫描信号线23、发光信号线25和存储电容的第一极板31。
在示例性实施方式中，第一极板31的形状可以为矩形状，矩形状的角部可以设置倒角，第一极板31在基底上的正投影与第三晶体管T3的第三有源层在基底上的正投影至少部分交叠。在示例性实施方式中，第一极板31可以同时作为存储电容的下极板和第三晶体管T3的栅电极。
在示例性实施方式中，第一扫描信号线21的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第一扫描信号线21可以位于第一极板31第二方向Y的反方向的一侧，第一扫描信号线21与第四有源层相重叠的区域可以作为第四晶体管T4的栅电极。
在示例性实施方式中，第二扫描信号线22的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第二扫描信号线22可以位于第一极板31第二方向Y的一侧，第二扫描信号线22与第七有源层相重叠的区域可以作为第七晶体管T7的栅电极，第二扫描信号线22与第八有源层相重叠的区域可以作为第八晶体管T8的栅电极。
在示例性实施方式中，第三扫描信号线23的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第三扫描信号线23可以位于第一扫描信号线21远离第一极板31的一侧，第三扫描信号线23与第一有源层相重叠的区域可以作为第一晶体管T1的栅电极。
在示例性实施方式中，发光信号线25的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，发光信号线25可以位于第二扫描信号线22和第一极板31之间，发光信号线25与第五有源层相重叠的区域可以作为第五晶体管T5的栅电极，发光信号线25与第六有源层相重叠的区域可以作为第六晶体管T6的栅电极。
在示例性实施方式中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23和发光信号线25可以为非等宽度设计，宽度为第二方向Y的尺寸，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容，本公开在此不做限定。
在示例性实施方式中，第一扫描信号线21、第二扫描信号线22、第三扫描信号线23和发光信号线25可以包括与第一半导体层相重叠区域和与第一半导体层不相重叠区域，与第一半导体层相重叠区域的信号线的宽度可以大于与第一半导体层不相重叠区域的信号线的宽度。
在示例性实施方式中，相邻单元列的第一导电层可以相对于列分界线镜像对称。例如，第N单元列的第一导电层和第N+1单元列的第一导电层可以相对于列分界线镜像对称，第N+1单元列的第一导电层和第N+2单元列的第一导电层可以相对于列分界线镜像对称。在示例性实施方式中，多个单元行中第一导电层的形状可以基本上相同。
在示例性实施方式中，形成第一导电层图案后，可以利用第一导电层作为遮挡，对第一半导体层进行导体化处理，被第一导电层遮挡区域的第一半导体层形成第一晶体管T1、第三晶体管T3至第八晶体管T8的沟道区域，未被第一导电层遮挡区域的第一半导体层被导体化，即第一晶体管T1、第三晶体管T3至第八晶体管T8的第一区和第二区均被导体化。
(3)形成第二导电层图案。在示例性实施方式中，形成第二导电层图案可以包括：在形成前述图案的基底上，依次沉积第三绝缘薄膜和第二导电薄膜，采用图案化工艺对第二导电薄膜进行图案化，形成覆盖第一导电层的第三绝缘层，以及设置在第三绝缘层上的第二导电层图案，如图11A和图11B所示，图11B为图11A中第二导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第二栅金属(GATE2)层。
在示例性实施方式中，每个电路单元的第二导电层图案至少包括：存储电容的第二极板32、遮挡线35和第一初始信号线41。
在示例性实施方式中，第二极板32的轮廓可以为矩形状，矩形状的角部可以设置倒角，第二极板32在基底上的正投影与第一极板31在基底上的正投影至少部分交叠，第二极板32可以作为存储电容的上极板，第一极板31和第二极板32构成像素驱动电路的存储电容。
在示例性实施方式中，第二极板32上设置有开口33，开口33的形状可以为矩形状，可以位于第二极板32的中部，使第二极板32形成环形结构。开口33暴露出覆盖第一极板31的第三绝缘层，且第一极板31在基底上的正投影包含开口33在基底上的正投影。在示例性实施方式中，开口33被配置为容置后续形成的第十三过孔，第十三过孔位于开口33内并暴露出第一极板31，使后续形成的第一连接电极与第一极板31连接。
在示例性实施方式中，第二极板32上设置有极板连接条34，极板连接条34的形状可以为沿着第一方向X延伸的条形状，可以设置在第二极板32第一方向X的一侧或者第一方向X的反方向的一侧。极板连接条34的第一端与本电路单元中的第二极板32连接，极板连接条34的第二端与第一方向X或者第一方向X的反方向相邻电路单元中的第二极板32连接。
在示例性实施方式中，一个单元行中，相邻两个电路单元中的第二极板32和极板连接条34为相互连接的一体结构。由于每个电路单元中的第二极板32与后续形成的第一电源线连接，通过将相邻电路单元的第二极板32形成相互连接的一体结构，一体结构的第二极板可以复用为电源信号线，可以保证相邻电路单元的第二极板具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，遮挡线35的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，可以位于第一扫描信号线21与第二极板32之间，遮挡线35被配置作为第二晶体管T2的遮挡层，遮挡第二晶体管T2的沟道区域，保证氧化物第二晶体管T2的电学性能，同时被配置为作为第二晶体管T2的底栅电极。
在示例性实施方式中，遮挡线35可以为非等宽度设计，不仅可以便于像素结构的布局，而且可以降低信号线之间的寄生电容。
在示例性实施方式中，第一初始信号线41的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第一初始信号线41可以位于第三扫描信号线23远离第二极板32的一侧。每个电路单元的第一初始信号线41上可以设置有第一初始连接块41-1，第一初始连接块41-1的形状可以为块形(如矩形)状，且与第一初始信号线41连接，第一初始连接块41-1被配置为通过后续形成的第七连接电极与第一有源层的第一区连接。
在示例性实施方式中，部分第一方向X相邻的电路单元的第一初始连接块41-1可以相互连接，形成相互连接的一体结构，使得部分相邻的电路单元共用同一个第一初始连接块41-1。例如，第N+1单元列的第一初始连接块41-1和第N+2单元列的第一初始连接块41-1为相互连接的一体结构。又如，第N+3单元列的第一初始连接块41-1和第N+4单元列的第一初始连接块41-1为相互连接的一体结构。
在示例性实施方式中，相邻单元列的第二导电层可以相对于列分界线镜像对称。例如，第N单元列的第二导电层和第N+1单元列的第二导电层可以相对于列分界线镜像对称，第N+1单元列的第二导电层和第N+2单元列的第二导电层可以相对于列分界线镜像对称。在示例性实施方式中，多个单元行中第二导电层的形状可以基本上相同。
(4)形成第二半导体层图案。在示例性实施方式中，形成第二半导体层图案可以包括：在形成前述图案的基底上，依次沉积第四绝缘薄膜和第二半导体薄膜，通过图案化工艺对第二半导体薄膜进行图案化，形成覆盖基底的第四绝缘层，以及设置在第四绝缘层上的第二半导体层图案，如图12A和图12B所示，图12B为图12A中第二半导体层的平面示意图。
在示例性实施方式中，每个电路单元的第二半导体层图案至少包括：第二晶体管T2的第二有源层12。
在示例性实施方式中，第二有源层12的形状可以呈“L”字形状，第二有源层12在基底上的正投影与遮挡线35在基底上的正投影至少部分交叠。
在示例性实施方式中，第二有源层的第一区12-1可以位于遮挡线35远离第二极板32的一侧，第二有源层的第二区12-2可以位于遮挡线35靠近第二极板32的一侧。
在示例性实施方式中，相邻单元列的第二半导体层可以相对于列分界线镜像对称。例如，第N单元列的第二半导体层和第N+1单元列的第二半导体层可以相对于列分界线镜像对称，第N+1单元列的第二半导体层和第N+2单元列的第二半导体层可以相对于列分界线镜像对称。在示例性实施方式中，多个单元行中第二半导体层的形状可以基本上相同。
在示例性实施方式中，第二半导体层可以采用氧化物，即第二晶体管T2为氧化物晶体管。在示例性实施方式中，第二半导体薄膜可以采用氧化铟镓锌(IGZO)，氧化铟镓锌(IGZO)的电子迁移率高于非晶硅。
(5)形成第三导电层图案。在示例性实施方式中，形成第三导电层图案可以包括：在形成前述图案的基底上，依次沉积第五绝缘薄膜和第三导电薄膜，采用图案化工艺对第三导电薄膜进行图案化，形成覆盖第二半导体层的第五绝缘层，以及设置在第五绝缘层上的第三导电层图案，如图13A和图13B所示，图13B为图13A中第三导电层的平面示意图。在示例性实施方式中，第二导电层可以称为第三栅金属(GATE3)层。
在示例性实施方式中，每个电路单元的第三导电层图案至少包括：第四扫描信号线24、第二初始信号线42和第三初始信号线43。
在示例性实施方式中，第四扫描信号线24的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第四扫描信号线24可以位于第一扫描信号线21与第二极板32之间，第四扫描信号线24与第二有源层相重叠的区域可以作为第二晶体管T2的栅电极。
在示例性实施方式中，第四扫描信号线24在基底上的正投影与遮挡线35在基底上的正投影至少部分交叠，第四扫描信号线24和遮挡线35可以连接相同的信号源，使得遮挡线35可以作为第二晶体管T2的底栅电极，第四扫描信号线24可以作为第二晶体管T2的顶栅电极，形成顶栅底栅结构的第二晶体管T2。
在示例性实施方式中，第二初始信号线42的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第二初始信号线42可以位于第一扫描信号线21远离第二极板32的一侧，每个电路单元的第二初始信号线42上可以设置有第二初始连接块42-1，第二初始连接块42-1的形状可以为块形(如矩形)状，且与第二初始信号线42连接，第二初始连接块42-1被配置为通过后续形成的第八连接电极与第七有源层的第一区连接。
在示例性实施方式中，第二初始信号线42在基底上的正投影与第三扫描信号线23在基底上的正投影至少部分交叠，传输恒定电压的第二初始信号线42可以屏蔽第三扫描信号线23对像素驱动电路的影响，提高像素驱动电路的驱动质量。
在示例性实施方式中，第三初始信号线43的形状可以为主体部分沿着第一方向X延伸的直线状或者折线状，第三初始信号线43可以位于第二极板32和第一初始信号线41之间，每个电路单元的第三初始信号线43上可以设置有第三初始连接块43-1，第三初始连接块43-1的形状可以为块形(如矩形)状，且与第三初始信号线43连接，第三初始连接块43-1被配置为通过后续形成的第九连接电极与第八有源层的第一区连接。
在示例性实施方式中，部分第一方向X相邻的电路单元的第三初始连接块43-1可以相互连接，形成相互连接的一体结构，使得部分相邻的电路单元共用同一个第三初始连接块43-1。例如，第N单元列的第三初始连接块43-1和第N+1单元列的第三初始连接块43-1为相互连接的一体结构。又如，第N+2单元列的第三初始连接块43-1和第N+3单元列的第三初始连接块43-1为相互连接的一体结构。
在示例性实施方式中，第三初始信号线43在基底上的正投影与第二扫描信号线22在基底上的正投影至少部分交叠，传输恒定电压的第三初始信号线43可以屏蔽第二扫描信号线22对像素驱动电路的影响，提高像素驱动电路的驱动质量。
在示例性实施方式中，相邻单元列的第三导电层可以相对于列分界线镜像对称。例如，第N单元列的第三导电层和第N+1单元列的第三导电层可以相对于列分界线镜像对称，第N+1单元列的第三导电层和第N+2单元列的第三导电层可以相对于列分界线镜像对称。在示例性实施方式中，多个单元行中第三导电层的形状可以基本上相同。
(6)形成第六绝缘层图案。在示例性实施方式中，形成第六绝缘层图案可以包括：在形成前述图案的基底上，沉积第六绝缘薄膜，采用图案化工艺对第五绝缘薄膜进行图案化，形成覆盖第三导电层的第六绝缘层，第六绝缘层上设置有多个过孔，如图14所示。
在示例性实施方式中，每个电路单元的多个过孔至少包括：第一过孔V1、第二过孔V2、第三过孔V3、第四过孔V4、第五过孔V5、第六过孔V6、第七过孔V7、第八过孔V8、第九过孔V9、第十过孔V10、第十一过孔V11、第十二过孔V12、第十三过孔V13、第十四过孔V14、第十五过孔V15、第十六过孔V16和第十七过孔V17。
在示例性实施方式中，第一过孔V1在基底上的正投影位于第一有源层的第一区在基底上的正投影的范围之内，第一过孔V1内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第一区的表面，第一过孔V1被配置为使后续形成的第七连接电极通过该过孔与第一有源层的第一区连接。
在示例性实施方式中，第二过孔V2在基底上的正投影位于第一有源层的第二区在基底上的正投影的范围之内，第二过孔V2内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第一有源层的第二区的表面，第二过孔V2被配置为使后续形成的第二连接电极通过该过孔与第一有源层的第二区连接。
在示例性实施方式中，第三过孔V3在基底上的正投影位于第二有源层的第一区在基底上的正投影的范围之内，第三过孔V3内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出第二有源层的第一区的表面，第三过孔V3被配置为使后续形成的第一连接电极通过该过孔与第二有源层的第一区连接。
在示例性实施方式中，第四过孔V4在基底上的正投影位于第二有源层的第二区在基底上的正投影的范围之内，第四过孔V4内的第六绝缘层和第五绝缘层被刻蚀掉，暴露出第二有源层的第二区的表面，第四过孔V4被配置为使后续形成的第二连接电极通过该过孔与第二有源层的第二区连接。
在示例性实施方式中，第五过孔V5在基底上的正投影位于第三有源层的第一区(也是第四有源层的第二区和第五有源层的第二区)在基底上的正投影的范围之内，第五过孔V5内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第一区(也是第四有源层的第二区和第五有源层的第二区)的表面，第五过孔V5被配置为使后续形成的第五连接电极通过该过孔与第三有源层的第一区(也是第四有源层的第二区和第五有源层的第二区)连接。
在示例性实施方式中，第六过孔V6在基底上的正投影位于第三有源层的第二区(也是第六有源层的第一区)在基底上的正投影的范围之内，第六过孔V6内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第三有源层的第二区(也是第六有源层的第一区)的表面，第六过孔V6被配置为使后续形成的第二连接电极通过该过孔与第三有源层的第二区(也是第六有源层的第一区)连接。
在示例性实施方式中，第七过孔V7在基底上的正投影位于第四有源层的第一区在基底上的正投影的范围之内，第七过孔V7内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第四有源层的第一区的表面，第七过孔V7被配置为使后续形成的第三连接电极通过该过孔与第四有源层的第一区连接。
在示例性实施方式中，第八过孔V8在基底上的正投影位于第五有源层的第一区在基底上的正投影的范围之内，第八过孔V8内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第五有源层的第一区的表面，第八过孔V8被配置为使后续形成的第四连接电极通过该过孔与第五有源层的第一区连接。在示例性实施方式中，由于一个单元行中部分相邻电路单元的第五有源层的第一区相互连接，因而部分相邻电路单元可以共用一个第八过孔V8。
在示例性实施方式中，第九过孔V9在基底上的正投影位于第六有源层的第二区(也是第七有源层的第二区)在基底上的正投影的范围之内，第九过孔V9内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第六有源层的第二区(也是第七有源层的第二区)的表面，第九过孔V9被配置为使后续形成的第六连接电极通过该过孔与第六有源层的第二区(也是第七有源层的第二区)连接。
在示例性实施方式中，第十过孔V10在基底上的正投影位于第七有源层的第一区在基底上的正投影的范围之内，第十过孔V10内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第七有源层的第一区的表面，第十过孔V10被配置为使后续形成的第八连接电极通过该过孔与第七有源层的第一区连接。
在示例性实施方式中，第十一过孔V11在基底上的正投影位于第八有源层的第一区在基底上的正投影的范围之内，第十一过孔V11内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第一区的表面，第十一过孔V11被配置为使后续形成的第九连接电极通过该过孔与第八有源层的第一区连接。
在示例性实施方式中，第十二过孔V12在基底上的正投影位于第八有源层的第二区在基底上的正投影的范围之内，第十二过孔V12内的第六绝缘层、第五绝缘层、第四绝缘层、第三绝缘层和第二绝缘层被刻蚀掉，暴露出第八有源层的第二区的表面，第十二过孔V12被配置为使后续形成的第五连接电极通过该过孔与第八有源层的第二区连接。
在示例性实施方式中，第十三过孔V13在基底上的正投影位于开口33在基底上的正投影的范围之内，第十三过孔V13内的第六绝缘层、第五绝缘层、第四绝缘层和第三绝缘层被刻蚀掉，暴露出第一极板31的表面，第十三过孔V13配置为使后续形成的第一连接电极通过该过孔与第一极板31连接。
在示例性实施方式中，第十四过孔V14在基底上的正投影位于第二极板32的极板连接条34在基底上的正投影的范围之内，第十四过孔V14内的第六绝缘层、第五绝缘层和第四绝缘层被刻蚀掉，暴露出极板连接条34的表面，第十四过孔V14被配置为使后续形成的第四连接电极通过该过孔与极板连接条34连接。在示例性实施方式中，由于一个单元行中相邻电路单元的第二极板32通过极板连接条34相互连接，因而一个单元行中相邻电路单元可以共用一个第十四过孔V14。
在示例性实施方式中，第十五过孔V15在基底上的正投影位于第一初始信号线41的第一初始连接块41-1在基底上的正投影的范围之内，第十五过孔V15内的第六绝缘层、第五绝缘层和第四绝缘层被刻蚀掉，暴露出第一初始连接块41-1的表面，第十五过孔V15被配置为使后续形成的第七连接电极通过该过孔与第一初始连接块41-1连接。
在示例性实施方式中，由于一个单元行中部分相邻电路单元的第一初始连接块41-1为相互连接的一体结构，相邻的电路单元共用同一个第一初始连接块41-1，因而部分相邻电路单元可以共用一个第十五过孔V15。
在示例性实施方式中，第十六过孔V16在基底上的正投影位于第二初始信号线42的第二初始连接块42-1在基底上的正投影的范围之内，第十六过孔V16内的第六绝缘层被刻蚀掉，暴露出第二初始连接块42-1的表面，第十六过孔V16被配置为使后续形成的第八连接电极通过该过孔与第二初始连接块42-1连接。
在示例性实施方式中，第十七过孔V17在基底上的正投影位于第三初始信号线43的第三初始连接块43-1在基底上的正投影的范围之内，第十七过孔V17内的第六绝缘层被刻蚀掉，暴露出第三初始连接块43-1的表面，第十七过孔V17被配置为使后续形成的第九连接电极通过该过孔与第三初始连接块43-1连接。
在示例性实施方式中，由于一个单元行中部分相邻电路单元的第三初始连接块43-1为相互连接的一体结构，相邻的电路单元共用同一个第三初始连接块43-1，因而部分相邻电路单元可以共用一个第十七过孔V17。
(7)形成第四导电层图案。在示例性实施方式中，形成第四导电层可以包括：在形成前述图案的基底上，沉积第四导电薄膜，采用图案化工艺对第四导电薄膜进行图案化，形成设置在第六绝缘层上的第四导电层，如图15A和图15B所示，图15B为图15A中第四导电层的平面示意图。在示例性实施方式中，第四导电层可以称为第一源漏金属(SD1)层。
在示例性实施方式中，每个电路单元的第四导电层至少包括：第一连接电极51、第二连接电极52、第三连接电极53、第四连接电极54、第五连接电极55、第六连接电极56、第七连接电极57、第八连接电极58和第九连接电极59。
在示例性实施方式中，第一连接电极51的形状可以为主体部分沿着第二方向Y延伸的条形状，第一连接电极51的第一端通过第三过孔V3与第二有源层的第一区连接，第一连接电极51的第二端沿着第二方向Y延伸后，通过第十三过孔V13与第一极板31连接。在示例性实施方式中，由于第一极板31同时作为第三晶体管T3的栅电极，因而第一连接电极51使第二晶体管T2的第一极、第三晶体管T3的栅电极和第一极板31具有相同的电位，形成像素驱动电路的第一节点N1。
在示例性实施方式中，第二连接电极52的形状可以为主体部分沿着第二方向Y延伸的条形状，第二连接电极52的第一端通过第二过孔V2与第一有源层的第二区连接，第二连接电极52的第二端沿着第二方向Y延伸后，通过第六过孔V6与第三有源层的第二区(也是第六有源层的第一区)连接，第二连接电极52的第一端和第二端之间的部分通过第四过孔V4与第二有源层的第二区连接。在示例性实施方式中，第二连接电极52使第一晶体管T1的第二极、第二晶体管T2的第二极、第三晶体管T3的第二极和第六晶体管T6的第一极具有相同的电位，形成像素驱动电路的第三节点N3。
在示例性实施方式中，第三连接电极53的形状可以为块形状(如矩形)，第三连接电极53通过第七过孔V7与第四有源层的第一区连接，第三连接电极53被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第四连接电极54的形状可以为沿着第二方向Y延伸的条形状，第四连接电极54的第一端通过第八过孔V8与第五有源层的第一区连接，第四连接电极54的第二端沿着第二方向Y的反方向延伸后，通过第十四过孔V14与极板连接条34连接。由于极板连接条34与第二极板32连接，因而实现了电路单元中第五晶体管T5的第一极和存储电容的第二极板32具有相同的电位。
在示例性实施方式中，由于一个单元行中部分相邻两个电路单元共用一个第八过孔V8和第十四过孔V14，因而部分相邻电路单元可以共用一个第四连接电极54。
在示例性实施方式中，至少一个电路单元还可以包括电源连接块54-1。电源连接块54-1的形状可以为沿着第一方向X延伸的条形状，电源连接块54-1的第一端与第四连接电极54的第二端连接，电源连接块54-1的第二端向着远离第四连接电极54的方向延伸，电源连接块54-1被配置为与后续形成的第一电源线连接。
在示例性实施方式中，至少一个电路单元中，第四连接电极54和电源连接块54-1可以为相互连接的一体结构。由于部分相邻电路单元可以共用一个第四连接电极54，因而部分相邻两个电路单元中的第四连接电极54和电源连接块54-1可以为相互连接的一体结构，可以保证部分相邻电路单元的第五晶体管T5的第一极和存储电容的第二极板32具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。
在示例性实施方式中，第五连接电极55的形状可以为主体部分沿着第二方向Y延伸的条形状，第五连接电极55的第一端通过第五过孔V5与第三有源层的第一区连接，第五连接电极55的第二端通过第十二过孔V12与第八有源层的第二区连接。在示例性实施方式中，由于第三有源层的第一区同时作为第四有源层的第二区和第五有源层的第二区，因而第五连接电极55使得第三晶体管T3的第一极、第四晶体管T4的第二极、第五晶体管T5的第二极和第八晶体管T8的第二极具有相同的电位，形成像素驱动电路的第二节点N2。
在示例性实施方式中，第六连接电极56的形状可以为块形状(如矩形)，第六连接电极56通过第九过孔V9与第六有源层的第二区(也是第七有源层的第二区)连接。在示例性实施方式中，第六连接电极56可以同时作为第六晶体管T6的第二极和第七晶体管T7的第二极，第六连接电极56被配置为与后续形成的阳极连接电极连接。
在示例性实施方式中，第七连接电极57的形状可以为沿着第一方向X延伸的条形状，第七连接电极57的第一端通过第一过孔V1与第一有源层的第一区连接，第七连接电极57的第二端通过第十五过孔V15与第一初始连接块41-1连接。在示例性实施方式中，由于第一初始连接块41-1与第一初始信号线41连接，因而第七连接电极57实现了第一初始信号线41传输的第一初始信号写入第一晶体管T1的第一极。
在示例性实施方式中，由于部分相邻的电路单元共用同一个第一初始连接块41-1，因而部分相邻的电路单元的第七连接电极57可以为相互连接的一体结构，可以保证部分相邻电路单元的第一晶体管T1的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。例如，第N+1单元列的第七连接电极57和第N+2单元列的第七连接电极57为相互连接的一体结构。又如，第N+3单元列的第七连接电极57和第N+4单元列的第七连接电极57为相互连接的一体结构。
在示例性实施方式中，第八连接电极58的形状可以为沿着第一方向X延伸的条形状，第八连接电极58的第一端通过第十过孔V10与第七有源层的第一区连接，第八连接电极58的第二端通过第十六过孔V16与第二初始连接块42-1连接。在示例性实施方式中，由于第二初始连接块42-1与第二初始信号线42连接，因而第八连接电极58实现了第二初始信号线42传输的第二初始信号写入第七晶体管T7的第一极。
在示例性实施方式中，第九连接电极59的形状可以为沿着第一方向X延伸的条形状，第九连接电极59的第一端通过第十一过孔V11与第八有源层的第一区连接，第九连接电极59的第二端通过第十七过孔V17与第三初始连接块43-1连接。在示例性实施方式中，由于第三初始连接块43-1与第三初始信号线43连接，因而第九连接电极59实现了第三初始信号线43传输的第三初始信号写入第八晶体管T8的第一极。
在示例性实施方式中，由于部分相邻的电路单元共用同一个第三初始连接块43-1，因而部分相邻的电路单元的第九连接电极59可以为相互连接的一体结构，可以保证部分相邻电路单元的第八晶体管T8的第一极具有相同的电位，有利于提高面板的均一性，避免显示基板的显示不良，保证显示基板的显示效果。例如，第N单元列的第九连接电极59和第N+1单元列的第九连接电极59为相互连接的一体结构。又如，第N+2单元列的第九连接电极59和第N+3单元列的第九连接电极59为相互连接的一体结构。
在示例性实施方式中，至少一个电路单元的第四导电层还可以包括第七连接块57-1。第七连接块57-1的形状可以为沿着第二方向Y延伸的条形状，且与第七连接电极57连接，第七连接块57-1被配置为与后续形成的第一初始连接线连接。
在示例性实施方式中，第七连接块57-1可以设置在部分相邻的电路单元之间，且相邻的电路单元共用同一个第七连接块57-1，两个电路单元中的第七连接电极57和共用第七连接块57-1为相互连接的一体结构。
在示例性实施方式中，第七连接块57-1可以设置在第N-1单元列和第N单元列之间。又如，第七连接块57-1可以设置在第N+3单元列和第N+4单元列之间。再如，第七连接块57-1可以设置在第N+7单元列和第N+8单元列之间。
在示例性实施方式中，至少一个电路单元的第四导电层还可以包括第八连接块58-1。第八连接块58-1的形状可以为沿着第二方向Y延伸的折线状，且与第八连接电极58连接，第八连接块58-1被配置为与后续形成的第二初始连接线连接。
在示例性实施方式中，部分相邻的电路单元的第八连接块58-1可以相互连接，两个电路单元中的第八连接电极58和第八连接块58-1为相互连接的一体结构。例如，第八连接块58-1可以设置在第N+1单元列和第N+2单元列中。又如，第八连接块58-1可以设置在第N+5单元列和第N+6单元列中。再如，第八连接块58-1可以设置在第N+9单元列和第N+10单元列中。
在示例性实施方式中，第五导电层还可以包括多条第一走线，第一走线的形状可以为沿着第一方向X延伸的直线状或者折线状，可以位于第一扫描信号线和第一初始信号线41之间。
在示例性实施方式中，至少一条第一走线可以包括一条横向子线和一条第一电源走线91，横向子线和第一电源走线91之间设置有第一断口K1，第一断口K1可以将横向子线与第一电源走线91截断，使得第一断口K1两侧的横向子线和第一电源走线91相互绝缘。例如，第M单元行中的第一走线可以包括沿着第一方向X依次设置的第二横向子线81-2和第一电源走线91。又如，第M+1单元行中的第一走线可以包括沿着第一方向X依次设置的第四横向子线81-4和第一电源走线91。再如，第M+2单元行中的第一走线可以包括沿着第一方向X依次设置的第六横向子线81-6和第一电源走线91。
在示例性实施方式中，至少一条第一走线可以包括一条横向子线和两条第一电源走线91，两条第一电源走线91与横向子线之间均设置有第一断口K1，第一断口K1可以将横向子线与第一电源走线91截断。例如，第M+5单元行中的第一走线可以包括沿着第一方向X依次设置的第一电源走线91、第一横向子线81-1和第一电源走线91。
在示例性实施方式中，至少一条第一走线可以包括两条横向子线和一条第一电源走线91，两条横向子线之间可以设置有第一断口K1，第一断口K1可以将两条横向子线截断，使得第一断口K1两侧的两条横向子线相互绝缘。横向子线和第一电源走线91之间设置有第一断口K1，第一断口K1可以将横向子线与第一电源走线91截断。例如，第M+3单元行中的第一走线可以包括沿着第一方向X依次设置的第七横向子线81-7、第五横向子线81-5和第一电源走线91。又如，第M+4单元行中的第一走线可以包括沿着第一方向X依次设置的第八横向子线81-8、第三横向子线81-3和第一电源走线91。
在示例性实施方式中，第M+5单元行中的第一横向子线81-1和第M单元行中的第二横向子线81-2可以称为第一条第一数据连接线81，两条横向子线的一端可以通过后续形成的第二竖向子线连接在一起，第一横向子线81-1的另一端被配置为与后续形成的第一竖向子线连接，第二横向子线81-2的另一端被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第M+4单元行中的第三横向子线81-3和第M+1单元行中的第四横向子线81-4可以称为第二条第一数据连接线81，两条横向子线的一端可以通过后续形成的第四竖向子线连接在一起，第三横向子线81-3的另一端被配置为与后续形成的第三竖向子线连接，第四横向子线81-4的另一端被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第M+3单元行中的第五横向子线81-5和第M+2单元行中的第六横向子线81-6可以称为第三条第一数据连接线81，两条横向子线的一端可以通过后续形成的第六竖向子线连接在一起，第五横向子线81-5的另一端被配置为与后续形成的第五竖向子线连接，第六横向子线81-6的另一端被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第M+3单元行中的第七横向子线81-7可以称为第四条第一数据连接线81，第七横向子线81-7的第一端被配置为与后续形成的第七竖向子线连接，第七横向子线81-7的第二端被配置为与后续形成的数据信号线连接。
在示例性实施方式中，第M+4单元行中的第八横向子线81-8可以称为第五条第一数据连接线81，第八横向子线81-8的第一端被配置为与后续形成的第八竖向子线连接，第八横向子线81-8的第二端被配置为与后续形成的数据信号线连接。
在示例性实施方式中，至少一个电路单元还可以包括数据转接条83和第一数据连接块84。数据转接条83的形状可以为沿着第二方向Y延伸的条形状，第一数据连接块84的形状可以为块形(如矩形)状，数据转接条83和第一数据连接块84可以设置在横向子线靠近第二极板32的一侧。数据转接条83的第一端与横向子线靠近第二极板32的一侧连接，数据转接条83的第二端向着第二极板32的方向延伸后，与横向子线连接，第一数据连接块84被配置为与后续形成的竖向子线连接。
在示例性实施方式中，数据转接条83和第一数据连接块84可以设置在部分第一方向X相邻的电路单元之间。例如，在第M单元行中，数据转接条83和第一数据连接块84可以设置在第N单元列和第N+1单元列之间，第一数据连接块84通过数据转接条83与第二横向子线81-2连接。又如，在第M+1单元行中，数据转接条83和第一数据连接块84可以设置在第N+2单元列和第N+3单元列之间，第一数据连接块84通过数据转接条83与第四横向子线81-4连接。再如，在第M+2单元行中，数据转接条83和第一数据连接块84可以设置在第N+4单元列和第N+5单元列之间，第一数据连接块84通过数据转接条83与第六横向子线81-6连接。再如，在第M+3单元行中，数据转接条83和第一数据连接块84可以设置在第N+4单元列和第N+5单元列之间，第一数据连接块84通过数据转接条83与第七横向子线81-7连接。以及，数据转接条83和第一数据连接块84可以设置在第N+6单元列和第N+7单元列之间，第一数据连接块84通过数据转接条83与第五横向子线81-5连接。再如，在第M+4单元行中，数据转接条83和第一数据连接块84可以设置在第N+2单元列和第N+3单元列之间，第一数据连接块84通过数据转接条83与第八横向子线81-8连接。以及，数据转接条83和第一数据连接块84可以设置在第N+8单元列和第N+9单元列之间，第一数据连接块84通过数据转接条83与第三横向子线81-3连接。再如，在第M+5单元行中，数据转接条83和第一数据连接块84可以设置在第N+10单元列和第N+11单元列之间，第一数据连接块84通过数据转接条83与第一横向子线81-1连接。
在示例性实施方式中，至少一个电路单元中，横向子线、数据转接条83和第一数据连接块84可以为相互连接的一体结构。
在示例性实施方式中，至少一个电路单元还可以包括第二数据连接块85。第二数据连接块85的形状可以为块形(如矩形)状，且与横向子线连接，第二数据连接块85被配置为与后续形成的竖向子线连接。
在示例性实施方式中，第二数据连接块85可以设置在部分第一方向X相邻的电路单元之间。例如，在第M单元行至第M+2单元行中没有设置第二数据连接块85。又如，在第M+3单元行中，第二数据连接块85可以设置在第N+4单元列和第N+5单元列之间，且与第五横向子线81-5连接。再如，在第M+4单元行中，第二数据连接块85可以设置在第N+2单元列和第N+3单元列之间，且与第三横向子线81-3连接。再如，在第M+5单元行中，第二数据连接块85可以设置在第N单元列和第N+1单元列之间，且与第一横向子线81-1连接。
在示例性实施方式中，至少一个电路单元中，横向子线和第二数据连接块85可以为相互连接的一体结构。
在示例性实施方式中，至少一个单元行中，可以仅设置有第一数据连接块84。例如，第M单元行至第M+2单元行中可以设置有一条横向子线(第二横向子线81-2、第四横向子线81-4或者第六横向子线81-6)，该横向子线的一端与第一数据连接块84连接。
在示例性实施方式中，至少一个单元行中，可以同时设置有第一数据连接块84和第二数据连接块85，且第一数据连接块84和第二数据连接块85分别设置在横向子线第一方向X的两端。例如，第M+3单元行中设置有两条横向子线(第五横向子线81-5和第七横向子线81-7)，第M+4单元行中设置有两条横向子线(第三横向子线81-3和第八横向子线81-8)。每个单元行中，一条横向子线的一端与第一数据连接块84连接，另一条横向子线的两端分别连接第一数据连接块84和第二数据连接块85。
在示例性实施方式中，相对于一条横向子线，第一数据连接块84和第二数据连接块85可以分别位于横向子线第二方向Y的两侧。
在示例性实施方式中，至少一条横向子线在基底上的正投影与第二初始信号线42在基底上的正投影至少部分交叠，使得具有恒定电位的第二初始信号线42可以有效屏蔽横向子线中电压跳变对像素驱动电路的影响。
在示例性实施方式中，至少一个单元行中，第一走线可以只包括第一电源走线91。
在示例性实施方式中，至少一个电路单元还可以包括第一虚设电极86，第一虚设电极86的形状可以为块形(如矩形)状，被配置为与后续形成的竖向子线连接。在第一方向X上，第一虚设电极86可以设置在部分第一方向X相邻的电路单元之间。在第二方向Y上，第一虚设电极86可以设置在横向子线靠近第二极板32的一侧。
在示例性实施方式中，第一虚设电极86在一个电路单元中的位置和连接结构可以与第一数据连接块84在另一个电路单元中的位置和连接结构基本上相同，所不同的是，第一虚设电极86为隔离设置，既不与横向子线连接，也不与其它电极连接。在示例性实施方式中，第一虚设电极86呈现出的形貌和连接结构与第一数据连接块84基本上相同。本公开通过转接区相同的设计，不仅可以提高后续刻蚀工艺的均一性，而且使得不同位置在透射及反射光下均能达到相同的显示效果，实现了消影，有效避免了显示基板的外观不良和熄屏水印(mura)的发生，提高了显示品质和显示质量。
在示例性实施方式中，至少一个电路单元还可以包括第二虚设电极87，第二虚设电极87的形状可以为块形(如矩形)状，被配置为与后续形成的竖向子线连接。在第一方向X上，第二虚设电极87可以设置在部分第一方向X相邻的电路单元之间。在第二方向Y上，第二虚设电极87可以设置在横向子线远离第二极板32的一侧。
在示例性实施方式中，第二虚设电极87在一个电路单元中的位置和连接结构可以与第二数据连接块85在另一个电路单元中的位置和连接结构基本上相同，所不同的是，第二虚设电极87为隔离设置，既不与横向子线连接，也不与其它电极连接。在示例性实施方式中，第二虚设电极87呈现出的形貌和连接结构与第二数据连接块85基本上相同。本公开通过转接区相同的设计，不仅可以提高后续刻蚀工艺的均一性，而且使得不同位置在透射及反射光下均能达到相同的显示效果，实现了消影，有效避免了显示基板的外观不良和熄屏水印(mura)的发生，提高了显示品质和显示质量。
在示例性实施方式中，相对于一条横向子线，第一虚设电极86和第二虚设电极87可以分别位于横向子线第二方向Y的两侧。
(8)形成第一平坦层图案。在示例性实施方式中，形成第一平坦层图案可以包括：在形成前述图案的基底上，涂覆第一平坦薄膜，采用图案化工艺对第一平坦薄膜进行图案化，形成覆盖第四导电层图案的第一平坦层，第一平坦层上设置有多个过孔，如图16所示。
在示例性实施方式中，每个电路单元中的多个过孔至少包括：第二十一过孔V21、第二十二过孔V22和第二十三过孔V23。
在示例性实施方式中，第二十一过孔V21在基底上的正投影位于第三连接电极53在基底上的正投影的范围之内，第二十一过孔V21内的第一平坦层被刻蚀掉，暴露出第三连接电极53的表面，第二十一过孔V21被配置为使后续形成的数据信号线通过该过孔与第三连接电极53连接。
在示例性实施方式中，第二十二过孔V22在基底上的正投影位于第四连接电极54的电源连接块54-1在基底上的正投影的范围之内，第二十二过孔V22内的第一平坦层被刻蚀掉，暴露出电源连接块54-1的表面，第二十二过孔V22被配置为使后续形成的第一电源线通过该过孔与电源连接块54-1连接。
在示例性实施方式中，第二十三过孔V23在基底上的正投影位于第六连接电极56在基底上的正投影的范围之内，第二十三过孔V23内的第一平坦层被刻蚀掉，暴露出第六连接电极56的表面，第二十三过孔V23被配置为使后续形成的阳极连接电极通过该过孔与第六连接电极56连接。
在示例性实施方式中，至少一个电路单元还可以包括第二十四过孔V24。第二十四过孔V24在基底上的正投影位于第七连接块57-1在基底上的正投影的范围之内，第二十四过孔V24内的第一平坦层被刻蚀掉，暴露出第七连接块57-1的表面，第二十四过孔V24被配置为使后续形成的第一初始连接线通过该过孔与第七连接块57-1连接。
在示例性实施方式中，第二十四过孔V24可以设置在部分相邻的电路单元之间。例如，第二十四过孔V24可以设置在第N+3单元列和第N+4单元列之间。又如，第二十四过孔V24可以设置在第N+7单元列和第N+8单元列之间。
在示例性实施方式中，至少一个电路单元还可以包括第二十五过孔V25。第二十五过孔V25在基底上的正投影位于第八连接块58-1在基底上的正投影的范围之内，第二十五过孔V25内的第一平坦层被刻蚀掉，暴露出第八连接块58-1的表面，第二十五过孔V25被配置为使后续形成的第二初始连接线通过该过孔与第八连接块58-1连接。
在示例性实施方式中，第二十五过孔V25可以设置在部分相邻的电路单元之间。例如，第二十五过孔V25可以设置在第N+1单元列和第N+2单元列之间。又如，第二十五过孔V25可以设置在第N+5单元列和第N+6单元列之间。再如，第二十五过孔V25可以设置在第N+9单元列和第N+10单元列之间。
在示例性实施方式中，至少一个电路单元还可以包括第二十六过孔V26。第二十六过孔V26在基底上的正投影位于第一数据连接块84在基底上的正投影的范围之内，第二十六过孔V26内的第一平坦层被刻蚀掉，暴露出第一数据连接块84的表面，第二十六过孔V26被配置为使后续形成的竖向子线通过该过孔与第一数据连接块84连接。
在示例性实施方式中，至少一个电路单元还可以包括第二十七过孔V27。第二十七过孔V27在基底上的正投影位于第二数据连接块85在基底上的正投影的范围之内，第二十七过孔V27内的第一平坦层被刻蚀掉，暴露出第二数据连接块85的表面，第二十七过孔V27被配置为使后续形成的竖向子线通过该过孔与第二数据连接块85连接。
在示例性实施方式中，至少一个电路单元还可以包括第二十八过孔V28。第二十八过孔V28在基底上的正投影位于第一虚设电极86在基底上的正投影的范围之内，第二十八过孔V28内的第一平坦层被刻蚀掉，暴露出第一虚设电极86的表面，第二十八过孔V28被配置为使后续形成的竖向子线通过该过孔与第一虚设电极86连接。
在示例性实施方式中，至少一个电路单元还可以包括第二十九过孔V29。第二十九过孔V29在基底上的正投影位于第二虚设电极87在基底上的正投影的范围之内，第二十九过孔V29内的第一平坦层被刻蚀掉，暴露出第二虚设电极87的表面，第二十九过孔V29被配置为使后续形成的竖向子线通过该过孔与第二虚设电极87连接。
(9)形成第五导电层图案。在示例性实施方式中，形成第五导电层可以包括：在形成前述图案的基底上，沉积第五导电薄膜，采用图案化工艺对第五导电薄膜进行图案化，形成设置在第一平坦层上的第五导电层，如图17A和图17B所示，图17B为图17A中第五导电层的平面示意图。在示例性实施方式中，第五导电层可以称为第二源漏金属(SD2)层。
在示例性实施方式中，每个电路单元的第五导电层至少包括：第一电源线71、数据信号线72和阳极连接电极73。
在示例性实施方式中，第一电源线71的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第一电源线71通过第二十二过孔V32与电源连接块54-1连接。由于电源连接块54-1与第四连接电极54连接，第四连接电极54分别与第五有源层的第一区和存储电容的第二极板32连接，因而实现了第一电源线71将第一电源信号写入第五晶体管T5和存储电容的第二极板32。
在示例性实施方式中，第一电源线71可以为非等宽度的折线，不仅可以便于像素结构的布局，而且可以降低第一电源线与数据信号线之间的寄生电容。
在示例性实施方式中，第一电源线71上可以设置有电源屏蔽块74。电源屏蔽块74的形状可以为块形(如矩形)状，可以设置在第一电源线71靠近第二晶体管T2的一侧，且与第一电源线71连接，电源屏蔽块74在基底上的正投影与第二晶体管T2的第二有源层在基底上的正投影至少部分交叠。在示例性实施方式中，电源屏蔽块74可以遮挡住第二有源层，阻挡发光器件的发光和膜层反射光照射到氧化物的第二晶体管T2，可以防止氧化物晶体管因光照发生特性漂移，提高了氧化物晶体管的电学特性。
在示例性实施方式中，第一电源线71和电源屏蔽块74在基底上的正投影与第一连接电极51在基底上的正投影至少部分交叠，因而具有恒定电位的第一电源线71和电源屏蔽块74可以有效屏蔽数据电压跳变和其它信号对像素驱动电路中第一节点N1的影响，避免了数据电压跳变和其它信号影响第一节点N1的电位，提高了像素驱动电路的驱动性能。
在示例性实施方式中，至少一个电路单元中，第一电源线71和电源屏蔽块74可以为相互连接的一体结构。
在示例性实施方式中，数据信号线72的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，数据信号线72通过第二十一过孔V21与第三连接电极53连接。由于第三连接电极53通过过孔与第四有源层的第一区连接，因而实现了数据信号线72与第四晶体管T4的第一极的连接，数据信号线72可以将数据信号写入第四晶体管T4的第一极。
在示例性实施方式中，阳极连接电极73的形状可以为沿着第二方向Y延伸的条形状，阳极连接电极73通过第二十三过孔V23与第六连接电极56连接，阳极连接电极73被配置为与后续形成的阳极连接。由于第六连接电极56通过过孔与第六有源层的第二区和第七有源层的第二区连接，因而可以实现后续形成的阳极与第六晶体管T6的第二极和第七晶体管T7的第二极的连接，像素驱动电路可以驱动发光器件发光。
在示例性实施方式中，至少一个电路单元的第五导电层还可以包括第一初始连接线61。第一初始连接线61的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第一初始连接线61通过第二十四过孔V24与第七连接块57-1连接。由于第七连接块57-1与第七连接电极57连接，第七连接电极57与第一初始信号线41连接，因而实现了沿着第一方向X延伸的第一初始信号线41和沿着第二方向Y延伸的第一初始连接线61之间的相互连接，第一初始信号线41和第一初始连接线61形成网状的传输第一初始信号的网状连通结构，不仅可以有效降低第一初始信号线的电阻，减小第一初始信号的压降，有效提升显示基板中第一初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第一初始连接线61可以设置在部分相邻单元列的两条第一电源线71之间，第一方向X相邻的两条第一初始连接线61之间可以设置有4条第一电源线71。例如，第一初始连接线61可以设置在第N+3单元列的第一电源线71和第N+4单元列的第一电源线71之间。又如，第一初始连接线61可以设置在第N+7单元列的第一电源线71和第N+8单元列的第一电源线71之间。
在示例性实施方式中，至少一个电路单元的第五导电层还可以包括第二初始连接线62。第二初始连接线62的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，第二初始连接线62通过第二十五过孔V25与第八连接块58-1连接。由于第八连接块58-1与第八连接电极58连接，第八连接电极58与第二初始信号线42连接，因而实现了沿着第一方向X延伸的第二初始信号线42和沿着第二方向Y延伸的第二初始连接线62之间的相互连接，第二初始信号线42和第二初始连接线62形成网状的传输第二初始信号的网状连通结构，不仅可以有效降低第二初始信号线的电阻，减小第二初始信号的压降，有效提升显示基板中第二初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
在示例性实施方式中，第二初始连接线62可以设置在部分相邻单元列的两条第一电源线71之间，第一方向X相邻的两条第二初始连接线62之间可以设置有4条第一电源线71。例如，第二初始连接线62可以设置在第N+1单元列的第一电源线71和第N+2单元列的第一电源线71之间。又如，第二初始连接线62可以设置在第N+5单元列的第一电源线71和第N+6单元列的第一电源线71之间。再如，第二初始连接线62可以设置在第N+9单元列的第一电源线71和第N+10单元列的第一电源线71之间。
在示例性实施方式中，在第一方向X上，第一初始连接线61和第二初始连接线62可以交替设置，第一方向X相邻的第一初始连接线61之间可以设置有一条第二初始连接线62，第一方向X相邻的第二初始连接线62之间可以设置有一条第一初始连接线61。
在一些可能的实施方式中，至少一个电路单元的第五导电层还可以包括主体部分沿着第二方向Y延伸的第三初始连接线，第三初始连接线可以通过过孔与第三初始信号线连接，形成网状的传输第三初始信号的网状连通结构，本公开在此不做限定。
在示例性实施方式中，第五导电层还可以包括多条第二走线，第二走线的形状可以为主体部分沿着第二方向Y延伸的直线状或者折线状，可以位于部分相邻单元列的两条数据信号线72之间，第一方向X相邻的两条第二走线之间可以设置有2条第一电源线71和2条数据信号线72。例如，第二走线可以位于第N单元列的数据信号线72与第N+1单元列的数据信号线72之间。又如，第二走线可以位于第N+2单元列的数据信号线72与第N+3单元列的数据信号线72之间。再如，第二走线可以位于第N+4单元列的数据信号线72与第N+5单元列的数据信号线72之间。
在示例性实施方式中，至少一条第二走线可以包括一条竖向子线和一条第二电源走线92，竖向子线和第二电源走线92之间可以设置有第二断口K2，第二断口K2可以将竖向子线与第二电源走线92截断，使得第二断口K2两侧的竖向子线和第二电源走线92相互绝缘。例如，位于第N+6单元列与第N+7单元列之间的第二走线可以包括沿着第二方向Y依次设置的第二电源走线92和第五竖向子线82-5。又如，位于第N+8单元列与第N+9单元列之间的第二走线可以包括沿着第二方向Y依次设置的第二电源走线92和第三竖向子线82-3。再如，位于第N+10单元列与第N+11单元列之间的第二走线可以包括沿着第二方向Y依次设置的第二电源走线92和第一竖向子线82-1。
在示例性实施方式中，至少一条第二走线可以包括一条竖向子线和两条第二电源走线92，两条第二电源走线92与竖向子线之间均设置有第二断口K2，第二断口K2可以将竖向子线与第二电源走线92截断。例如，位于第N单元列与第N+1单元列之间的第二走线可以包括沿着第二方向Y依次设置的第二电源走线92、第二竖向子线82-2和第二电源走线92。
在示例性实施方式中，至少一条第二走线可以包括两条竖向子线和一条第二电源走线92，两条竖向子线之间可以设置有第二断口K2，第二断口K2可以将两条竖向子线截断，使得第二断口K2两侧的两条竖向子线相互绝缘。竖向子线与第二电源走线92之间设置有第二断口K2，第二断口K2可以将竖向子线与第二电源走线92截断。例如，位于第N+2单元列与第N+3单元列之间的第二走线可以包括沿着第二方向Y依次设置的第二电源走线92、第四竖向子线82-4和第八竖向子线82-8。又如，位于第N+4单元列与第N+5单元列之间的第二走线可以包括沿着第二方向Y依次设置的第二电源走线92、第六竖向子线82-6和第七竖向子线82-7。
在示例性实施方式中，至少一条竖向子线一端被配置为延伸到绑定区域后与数据引出线连接，另一端通过第二十六过孔V26与第一数据连接块84连接，因而实现了一条竖向子线与一条横向子线的相互连接。
在示例性实施方式中，至少一条竖向子线一端通过第二十七过孔V27与第二数据连接块85连接，另一端通过第二十六过孔V26与第一数据连接块84连接，因而实现了一条竖向子线与两条横向子线的相互连接。
在示例性实施方式中，至少一条竖向子线还通过第二十八过孔V28与第一虚设电极86连接，使得显示基板各个位置呈现出相同的形貌和连接结构。
在示例性实施方式中，至少一条竖向子线还通过第二十九过孔V29与第二虚设电极87连接，使得显示基板各个位置呈现出相同的形貌和连接结构。
在示例性实施方式中，第N+10单元列与第N+11单元列之间的第一竖向子线82-1和第N单元列与第N+1单元列之间的第二竖向子线82-2可以称为第一条第二数据连接线82，第一竖向子线82-1与第一横向子线81-1连接，第二竖向子线82-2分别与第一横向子线81-1和第二横向子线81-2连接。
在示例性实施方式中，第N+8单元列与第N+9单元列之间的第三竖向子线82-3和第N+2单元列与第N+3单元列之间的第四竖向子线82-4可以称为第二条第二数据连接线82，第三竖向子线82-3与第三横向子线81-3连接，第四竖向子线82-4分别与第三横向子线81-3和第四横向子线81-4连接。
在示例性实施方式中，第N+6单元列与第N+7单元列之间的第五竖向子线82-5和第N+4单元列与第N+5单元列之间的第六竖向子线82-6可以称为第三条第二数据连接线82，第五竖向子线82-5与第五横向子线81-5连接，第六竖向子线82-6分别与第五横向子线81-5和第六横向子线81-6连接。
在示例性实施方式中，第N+4单元列与第N+5单元列之间的第七竖向子线82-7可以称为第四条第二数据连接线82，第七竖向子线82-7与第七横向子线81-7连接。
在示例性实施方式中，第N+2单元列与第N+3单元列之间的第八竖向子线82-8可以称为第五条第二数据连接线82，第八竖向子线82-8与第八横向子线81-8连接。
图17C为本公开示例性实施例横向子线和竖向子线连接的示意图。如图17A、图17B和图17C所示，多条数据连接线可以至少包括第一条数据连接线80A、第二条数据连接线80B、第三条数据连接线80C、第四条数据连接线80D和第五条数据连接线80E。
在示例性实施方式中，第一条数据连接线80A可以至少包括第一条第一数据连接线和第一条第二数据连接线，第一条第一数据连接线可以至少包括第一横向子线81-1和第二横向子线81-2，第一条第二数据连接线可以至少包括第一竖向子线82-1和第二竖向子线82-2。第一横向子线81-1可以设置在第M+5单元行中，第二横向子线81-2可以设置在第M单元行中，第一竖向子线82-1可以设置在第N+10单元列与第N+11单元列之间，第二竖向子线82-2可以设置在第N单元列与第N+1单元列之间。
在示例性实施方式中，第一竖向子线82-1的第一端与绑定区域中的一条数据引出线连接，第一竖向子线82-1的第二端沿着第二方向Y的反方向延伸后，通过第一数据连接块84与第一横向子线81-1的第一端连接。第一横向子线81-1的第二端沿着第一方向X或者第一方向X的反方向延伸后，通过第二数据连接块85与第二竖向子线82-2的第一端连接。第二竖向子线82-2的第二端沿着第二方向Y的反方向延伸后，通过第一数据连接块84与第二横向子线81-2的第一端连接。第二横向子线81-2的第二端沿着第一方向X或者第一方向X的反方向延伸后，与一条数据信号线连接。
在示例性实施方式中，第二条数据连接线80B可以至少包括第二条第一数据连接线和第二条第二数据连接线，第二条第一数据连接线可以至少包括第三横向子线81-3和第四横向子线81-4，第二条第二数据连接线可以至少包括第三竖向子线82-3和第四竖向子线82-4。第一横向子线81-1可以设置在第M+4单元行中，第四横向子线81-4可以设置在第M+1单元行中，第三竖向子线82-3可以设置在第N+8单元列与第N+9单元列之间，第四竖向子线82-4可以设置在第N+2单元列与第N+3单元列之间。
在示例性实施方式中，第三竖向子线82-3的第一端与绑定区域中的另一条数据引出线连接，第三竖向子线82-3的第二端沿着第二方向Y的反方向延伸后，通过第一数据连接块84与第三横向子线81-3的第一端连接。第三横向子线81-3的第二端沿着第一方向X或者第一方向X的反方向延伸后，通过第二数据连接块85与第四竖向子线82-4的第一端连接。第四竖向子线82-4的第二端沿着第二方向Y的反方向延伸后，通过第一数据连接块84与第四横向子线81-4的第一端连接。第四横向子线81-4的第二端沿着第一方向X或者第一方向X的反方向延伸后，与另一条数据信号线连接。
在示例性实施方式中，第三条数据连接线80C可以至少包括第三条第一数据连接线和第三条第二数据连接线，第三条第一数据连接线可以至少包括第五横向子线81-5和第六横向子线81-6，第三条第二数据连接线可以至少包括第五竖向子线82-5和第六竖向子线82-6。第五横向子线81-5可以设置在第M+3单元行中，第六横向子线81-6可以设置在第M+2单元行中，第五竖向子线82-5可以设置在第N+6单元列与第N+7单元列之间，第六竖向子线82-6可以设置在第N+4单元列与第N+5单元列之间。
在示例性实施方式中，第五竖向子线82-5的第一端与绑定区域中的又一条数据引出线连接，第五竖向子线82-5的第二端沿着第二方向Y的反方向延伸后，通过第一数据连接块84与第五横向子线81-5的第一端连接。第五横向子线81-5的第二端沿着第一方向X或者第一方向X的反方向延伸后，通过第二数据连接块85与第六竖向子线82-6的第一端连接。第六竖向子线82-6的第二端沿着第二方向Y的反方向延伸后，通过第一数据连接块84与第六横向子线81-6的第一端连接。第六横向子线81-6的第二端沿着第一方向X或者第一方向X的反方向延伸后，与又一条数据信号线连接。
在示例性实施方式中，第四条数据连接线80D可以至少包括第四条第一数据连接线和第四条第二数据连接线，第四条第一数据连接线可以至少包括第七横向子线81-7，第四条第二数据连接线可以至少包括第七竖向子线82-7。第七横向子线81-7可以设置在第M+3单元行中，第七竖向子线82-7可以设置在第N+4单元列与第N+5单元列之间。
在示例性实施方式中，第七竖向子线82-7的第一端与绑定区域中的又一条数据引出线连接，第七竖向子线82-7的第二端沿着第二方向Y的反方向延伸后，通过第一数据连接块84与第七横向子线81-7连接。第七横向子线81-7的第二端沿着第一方向X或者第一方向X的反方向延伸后，与又一条数据信号线连接。
在示例性实施方式中，第五条数据连接线80E可以至少包括第五条第一数据连接线和第五条第二数据连接线，第五条第一数据连接线可以至少包括第八横向子线81-8，第五条第二数据连接线可以至少包括第八竖向子线82-8。第八横向子线81-8可以设置在第M+4单元行中，第八竖向子线82-8可以设置在第N+2单元列与第N+3单元列之间。
在示例性实施方式中，第八竖向子线82-8的第一端与绑定区域中的又一条数据引出线连接，第八竖向子线82-8的第二端沿着第二方向Y的反方向延伸后，通过第一数据连接块84与第八横向子线81-8连接。第八横向子线81-8的第二端沿着第一方向X或者第一方向X的反方向延伸后，与又一条数据信号线连接。
在示例性实施方式中，第一电源走线91和第二电源走线92可以相互连接，形成网状连通结构，本公开在此不做限定。
在示例性实施方式中，第一电源走线91和第二电源走线92可以通过边框区域或者绑定区域与传输第二电源信号的电源引线连接，实现了第二电源线位于面板(VSS in Panel，简称SIP)结构，不仅可以有效降低第二电源线的电阻，减小第二电源信号的压降，实现低功耗，有效提升显示基板中第二电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量，而且可以大幅度减小边框电源引线的宽度，大大缩减了边框宽度，提高屏占比，有利于实现全面屏显示。
在示例性实施方式中，相邻单元列的第一电源线71可以相对于列分界线镜像对称，相邻单元列的数据信号线72可以相对于列分界线镜像对称。在示例性实施方式中，多个单元行中第一电源线71和数据信号线72的形状可以基本上相同。
在示例性实施方式中，至少一条第二走线在基底上的正投影与列分界线在基底上的正投影至少部分交叠。
在示例性实施方式中，在第一方向X上，一条第二走线和两条数据信号线72可以设置在相邻单元列的两条第一电源线71之间，两条第一电源线71可以相对于第二走线镜像对称，两条数据信号线72可以相对于第二走线镜像对称。
在示例性实施方式中，在第一方向X上，两条第一电源线71和两条数据信号线72可以设置在相邻的第二走线之间，两条第二走线可以相对于列分界线镜像对称。
(10)形成第二平坦层图案。在示例性实施方式中，形成第二平坦层图案可以包括：在形成前述图案的基底上，涂覆第二平坦薄膜，采用图案化工艺对第二平坦薄膜进行图案化，形成覆盖第五导电层图案的第二平坦层，第二平坦层上设置有多个阳极过孔V30，如图18所示。
在示例性实施方式中，每个电路单元的阳极过孔V30在基底上的正投影位于阳极连接电极73在基底上的正投影的范围之内，阳极过孔V30内的第二平坦层被去掉，暴露出阳极连接电极73的表面，阳极过孔V30被配置为使后续形成的阳极通过该过孔与阳极连接电极73连接。
至此，在基底上制备完成驱动电路层。在平行于显示基板的平面内，驱动电路层可以包括多个电路单元，每个电路单元可以包括像素驱动电路，以及与像素驱动电路连接的第一扫描信号线、第二扫描信号线、第三扫描信号线、第四扫描信号线、发光信号线、第一初始信号线、第二初始信号线、第三初始信号线、第一电源线和数据信号线。
在垂直于显示基板的平面内，驱动电路层可以包括在基底上依次设置的第一绝缘层、第一半导体层、第二绝缘层、第一导电层、第三绝缘层、第二导电层、第四绝缘层、第二半导体层、第五绝缘层、第三导电层、第六绝缘层、第四导电层、第一平坦层、第五导电层和第二平坦层。第一半导体层可以至少包括第一晶体管、第三晶体管至第八晶体管的有源层，第一导电层可以至少包括第一扫描信号线、第二扫描信号线、第三扫描信号线、发光信号线和存储电容的第一极板，第二导电层可以至少包括第一初始信号线和存储电容的第二极板，第二半导体层可以至少包括第二晶体管的有源层，第三导电层可以至少包括第二初始信号线、第三初始信号线和第四扫描信号线，第四导电层可以至少包括第一数据连接线和多个连接电极，第五导电层可以至少包括第一电源线、数据信号线、第一初始信号线、第二初始信号线和第二数据连接线。
在示例性实施方式中，基底可以是柔性基底，或者可以是刚性基底。刚性基底可以包括但不限于玻璃、石英中的一种或多种，柔性衬底可以为但不限于聚对苯二甲酸乙二醇酯、对苯二甲酸乙二醇酯、聚醚醚酮、聚苯乙烯、聚碳酸酯、聚芳基酸酯、聚芳酯、聚酰亚胺、聚氯乙烯、聚乙烯、纺织纤维中的一种或多种。在示例性实施方式中，柔性基底可以包括叠设的第一柔性材料层、第一无机材料层、半导体层、第二柔性材料层和第二无机材料层。第一、第二柔性材料层的材料可以采用聚酰亚胺(PI)、聚对苯二甲酸乙二酯(PET)或经表面处理的聚合物软膜等材料，第一、第二无机材料层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力，第一、第二无机材料层也称为阻挡(Barrier)层，半导体层的材料可以采用非晶硅(a-si)。
在示例性实施方式中，第一导电层、第二导电层、第三导电层、第四导电层和第五导电层可以采用金属材料，如银(Ag)、铜(Cu)、铝(Al)和钼(Mo)中的任意一种或多种，或上述金属的合金材料，如铝钕合金(AlNd)或钼铌合金(MoNb)，可以是单层结构，或者多层复合结构，如Mo/Cu/Mo等。第一绝缘层、第二绝缘层、第三绝缘层、第四绝缘层、第五绝缘层和第六绝缘层可以采用硅氧化物(SiOx)、硅氮化物(SiNx)和氮氧化硅(SiON)中的任意一种或多种，可以是单层、多层或复合层。第一平坦层和第二平坦层可以采用有机材料，如树脂等。
在示例性实施方式中，一个单元行中相邻两个电路单元中的像素驱动电路可以相对于列分界线基本上镜像对称，列分界线是位于相邻两个电路单元之间且沿着第二方向Y延伸的直线。例如，第N单元列的像素驱动电路和第N+1单元列的像素驱动电路可以相对于列分界线镜像对称。又如，第N+1单元列的像素驱动电路和第N+2单元列的像素驱动电路可以相对于列分界线镜像对称。
在示例性实施方式中，相邻两个电路单元中的像素驱动电路可以相对于列分界线基本上镜像对称可以包括如下任意一种或多种：一个单元行中相邻两个电路单元中的第一半导体层可以相对于列分界线镜像对称，一个单元行中相邻两个电路单元中的第一导电层可以相对于列分界线镜像对称，一个单元行中相邻两个电路单元中的第二导电层可以相对于列分界线镜像对称，一个单元行中相邻两个电路单元中的第二半导体层可以相对于列分界线镜像对称，一个单元行中相邻两个电路单元中的第三导电层可以相对于列分界线镜像对称，一个单元行中相邻两个电路单元中的第四导电层(除了第一走线和数据转接条)可以相对于列分界线镜像对称，一个单元行中相邻两个电路单元中的第五导电层可以相对于列分界线镜像对称(除了第二走线和阳极连接电极)。
在示例性实施方式中，制备完成驱动电路层后，可以在驱动电路层上制备发光结构层，发光结构层的制备过程可以包括如下操作。
[根据细则91更正 08.05.2025]
(11)形成阳极导电层图案。在示例性实施方式中，形成阳极导电层图案可以包括：在形成前述图案的基底上，沉积阳极导电薄膜，采用图案化工艺对阳极导电薄膜进行图案化，形成设置在第二平坦层上的阳极导电层，阳极导电层至少包括多个阳极图案，如图19A和图19B所示，图19B为图19A中阳极导电层的平面示意图。
在示例性实施方式中，多个阳极图案可以包括位于出射红色光线的红色发光单元的第一阳极90A、位于出射蓝色光线的蓝色发光单元的第二阳极90B、位于出射绿色光线的第一绿色发光单元的第三阳极90C和位于出射绿色光线的第二绿色发光单元的第四阳极90D，第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D可以分别通过阳极过孔V30与所在电路单元的阳极连接电极73连接。
在示例性实施方式中，第一阳极90A、第二阳极90B、第三阳极90C和第四阳极90D中的至少一个可以包括相互连接的阳极主体部和阳极连接部，阳极主体部的形状可以为菱形状，矩形状的角部可以设置圆弧状的倒角，阳极连接部的形状可以为条形状，阳极连接部的第一端与阳极主体部连接，阳极连接部的第二端向着远离阳极主体部的方向延伸后，通过阳极过孔V30与阳极连接电极73连接。
在示例性实施方式中，第一阳极90A、第三阳极90C和第四阳极90D在基底上的正投影与第二十六过孔V26(或者第二十八过孔V28)在基底上的正投影没有交叠。
在示例性实施方式中，第一阳极90A、第三阳极90C和第四阳极90D在基底上的正投影与第二十七过孔V27(或者第二十九过孔V29)在基底上的正投影没有交叠。
在示例性实施方式中，第一阳极90A、第三阳极90C和第四阳极90D在基底上的正投影与第一数据连接块84(或者第一虚设电极86)和第二数据连接块85(或者第二虚设电极87)在基底上的正投影没有交叠。
在示例性实施方式中，第二阳极90B在基底上的正投影与第二十六过孔V26(或者第二十八过孔V28)在基底上的正投影至少部分交叠。
在示例性实施方式中，第二阳极90B在基底上的正投影与第二十七过孔V27(或者第二十九过孔V29)在基底上的正投影至少部分交叠。
在示例性实施方式中，第二阳极90B在基底上的正投影与第二十六过孔V26(或者第二十八过孔V28)和第二十七过孔V27(或者第二十九过孔V29)在基底上的正投影至少部分交叠。
在示例性实施方式中，第二阳极90B可以具有阳极中心线，阳极中心线可以是经过第二阳极的阳极主体部的几何中心且沿着第一方向X延伸的折线状。第二十六过孔V26(或者第二十八过孔V28)可以位于阳极中心线第二方向Y的一侧，第二十七过孔V27(或者第二十九过孔V29)可以位于阳极中心线第二方向Y的反方向的一侧，即第二十六过孔V26(或者第二十八过孔V28)和第二十七过孔V27(或者第二十九过孔V29)可以相对于阳极中心线上下设置。
在示例性实施方式中，在第二方向Y上，第二十六过孔V26(或者第二十八过孔V28)的几何中心与阳极中心线之间具有第一距离，第二十七过孔V27(或者第二十九过孔V29)的几何中心与阳极中心线之间具有第二距离，阳极中心线可以是经过第二阳极的阳极主体部的几何中心且沿着第一方向X延伸的折线状。
在示例性实施方式中，第一距离与第二距离之比可以约为0.9至1.1，即第二十六过孔V26(或者第二十八过孔V28)和第二十七过孔V27(或者第二十九过孔V29)可以相对于阳极中心线上下位置对应。
在示例性实施方式中，第一距离与第二距离之比可以约为1.0左右。
在示例性实施方式中，阳极导电层可以采用单层结构，如氧化铟锡ITO或氧化铟锌IZO，或者可以采用多层复合结构，如ITO/Ag/ITO等。
在示例性实施方式中，后续制备流程可以包括：先形成像素定义层，像素定义层上设置有多个像素开口，多个像素开口分别暴露出第一阳极、第二阳极、第三阳极和第四阳极。随后采用蒸镀或喷墨打印工艺形成有机发光层，然后在有机发光层上形成阴极，随后形成封装结构层，封装结构层可以包括叠设的第一封装层、第二封装层和第三封装层，第一封装层和第三封装层可以采用无机材料，第二封装层可以采用有机材料，第二封装层设置在第一封装层和第三封装层之间，可以保证外界水汽无法进入发光结构层。
本公开示例性实施例提供了一种显示基板，通过将延伸长度较长的第一数据连接线拆分成两条横向子线，且两条横向子线设置在不同的单元行中，有效减小了不同单元行中数据连接线耦合单元列的数量差距，可以有效减轻甚至消除显示区域靠近绑定区域一侧的两个角部出现斜纹水印。
在示例性实施方式中，以图6中离绑定区域距离较远的一条第一数据连接线81为例，本公开将该第一数据连接线拆分成第一横向子线81-1和第二横向子线81-2后，虽然图6中该第一数据连接线81所耦合单元列的数量与本公开第一横向子线81-1和第二横向子线81-2所耦合单元列的数量之和基本上相同，但由于本公开的第一横向子线81-1和第二横向子线81-2设置在不同的单元行中，因而第一横向子线81-1所在单元行中所耦合单元列的数量较少，第二横向子线81-2所在单元行中所耦合单元列的数量较少，且第一横向子线81-1所耦合单元列的数量和第二横向子线81-2所耦合单元列的数量相近，因而有效减小了不同单元行中数据连接线耦合单元列的数量差距。
在示例性实施方式中，以图6中离绑定区域距离较近的一条第一数据连接线81为例，虽然图6中该第一数据连接线的延伸长度较短，其与较少的单元列耦合，但由于本公开将其它第一数据连接线拆分成两条横向子线，使得该第一数据连接线所在单元行中设置有其它数据连接线的横向子线，增加了该单元行中数据连接线耦合单元列的数量，且与其它单元行中数据连接线耦合单元列的数量相近，因而有效减小了不同单元行中数据连接线耦合单元列的数量差距。
比较图6和本公开的第一区域110可以看出，本公开通过将延伸长度较长的第一数据连接线拆分成两条横向子线，将延伸长度较长的第二数据连接线拆分成两条竖向子线，有效减小了第一区域(FIP区域)的面积，有利于增加电源走线的数量，有利于减小电源信号压降，可以有效提升显示均一性，提高了显示品质和显示质量。
本公开实施例通过在显示区域内设置数据连接线，绑定区域的数据引出线通过数据连接线与数据信号线连接，实现了FIP结构，使得引出线区中不需要设置扇形状的斜线，有效减小了引出线区的长度，大大缩减了下边框宽度，提高了屏占比，有利于实现全面屏显示。
本公开实施例通过在显示区域内设置第一电源走线和第二电源走线，实现了SIP结构，不仅可以有效降低第二电源线的电阻，减小第二电源信号的压降，实现低功耗，有效提升显示基板中第二电源信号的均一性，有效提升显示均一性，提高了显示品质和显示质量，而且可以大幅度减小边框电源引线的宽度，大大缩减了边框宽度，提高屏占比，有利于实现全面屏显示。
本公开实施例通过在显示区域内设置第一初始连接线和第二初始连接线，第一初始连接线和第一初始信号线构成网状连通结构，第二初始连接线和第二初始信号线构成网状连通结构，不仅可以有效降低初始信号线的电阻，减小初始信号的压降，有效提升显示基板中初始信号的均一性，有效提升显示均一性，提高了显示品质和显示质量。
本公开实施例通过设置第一虚设电极和第二虚设电极，第一虚设电极呈现出的形貌和连接结构与第一数据连接块基本上相同，第二虚设电极呈现出的形貌和连接结构与第二数据连接块基本上相同，使得显示区域具有基本上相同的转接区结构，提高了刻蚀工艺的均一性，不同区域在透射及反射光下能达到相同的显示效果，实现了消影，有效避免了显示基板的外观不良和熄屏水印的发生，提高了显示品质和显示质量。
本公开实施例通过设置第二阳极覆盖第一平坦层上的转接过孔，且两个转接过孔相对于阳极中心线上下位置对应设置，使得阳极具有良好的平坦性，可以有效改善色偏。
本公开的制备工艺可以很好地与现有制备工艺兼容，工艺实现简单，易于实施，生产效率高，生产成本低，良品率高。
本公开前述所示结构及其制备过程仅仅是一种示例性说明，在示例性实施方式中，可以根据实际需要变更相应结构以及增加或减少构图工艺，本公开在此不做限定。
在示例性实施方式中，本公开显示基板可以应用于具有像素驱动电路的显示装置中，如OLED、量子点显示(QLED)、发光二极管显示(Micro LED或Mini LED)或量子点发光二极管显示(QDLED)等，本公开在此不做限定。
本公开还提供一种显示基板的制备方法，以制作上述实施例提供的显示基板。在示例性实施方式中，所述显示基板包括显示区域和设置在所述显示区域一侧的绑定区域，所述显示区域包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路；所述制备方法可以包括：
在所述显示区域形成多条数据信号线和多条数据连接线，在所述绑定区域形成多条数据引出线，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述数据信号线通过所述数据连接线与所述数据引出线连接；至少一条数据连接线包括至少两条沿着第一方向延伸的横向子线和至少两条沿着第二方向延伸的竖向子线，所述两条横向子线设置在不同的单元行中，所述两条竖向子线设置在不同的单元列中，所述第一方向和所述第二方向交叉。
虽然本公开所揭露的实施方式如上，但应该注意，上述实施方式仅仅是示例性的，而不是限制性的。因此，本公开不限于在此具体示出和描述的内容。可以对实施的形式及细节进行多种修改、替换或省略，而不脱离本公开的范围。

Claims (18)

  1. 一种显示基板，包括显示区域和设置在所述显示区域一侧的绑定区域，所述显示区域包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路，所述绑定区域至少包括多条数据引出线；所述显示区域还包括多条数据信号线和多条数据连接线，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述数据信号线通过所述数据连接线与所述数据引出线连接；至少一条数据连接线包括至少两条沿着第一方向延伸的横向子线和至少两条沿着第二方向延伸的竖向子线，所述两条横向子线设置在不同的单元行中，所述两条竖向子线设置在不同的单元列中，所述第一方向和所述第二方向交叉。
  2. 根据权利要求1所述的显示基板，其中，至少一个单元行中设置有至少两条横向子线，所述两条横向子线连接不同的竖向子线。
  3. 根据权利要求1所述的显示基板，其中，至少一个单元列中设置有至少两条竖向子线，所述两条竖向子线连接不同的横向子线。
  4. 根据权利要求1所述的显示基板，其中，至少一条横向子线在显示基板上的正投影与至少一条竖向子线在显示基板上的正投影至少部分交叠。
  5. 根据权利要求1所述的显示基板，其中，在垂直于显示基板的方向上，所述显示区域包括多个导电层，所述两条横向子线设置在相同的导电层中，所述两条竖向子线设置在相同的导电层中，所述横向子线和所述竖向子线设置在不同的导电层中。
  6. 根据权利要求5所述的显示基板，其中，多个导电层至少包括设置在基底上的第一源漏金属层和设置在所述第一源漏金属层远离所述基底一侧的第二源漏金属层，所述横向子线设置在所述第一源漏金属层中，所述竖向子线设置在所述第二源漏金属层中。
  7. 根据权利要求1至6任一项所述的显示基板，其中，所述至少两条横向子线至少包括第一横向子线和第二横向子线，所述至少两条竖向子线至少包括第一竖向子线和第二竖向子线；所述数据信号线通过所述数据连接线与所述数据引出线连接，包括：所述第一竖向子线的第一端与所述数据引出线连接，所述第一竖向子线的第二端向着远离所述绑定区域的方向延伸后，与所述第一横向子线的第一端连接，所述第一横向子线的第二端向着靠近所述第二竖向子线的方向延伸后，与所述第二竖向子线的第一端连接，所述第二竖向子线的第二端向着远离所述绑定区域的方向延伸后，与所述第二横向子线的第一端连接，所述第二横向子线的第二端向着靠近所述数据信号线的方向延伸后，与所述数据信号线连接。
  8. 根据权利要求7所述的显示基板，其中，所述显示区域还包括多个第一数据连接块；至少一个电路单元中，所述第一数据连接块与所述第一横向子线的第一端连接，所述第一竖向子线的第二端通过过孔与所述第一数据连接块连接；至少另一个电路单元中，所述第一数据连接块与所述第二横向子线的第一端连接，所述第二竖向子线的第二端通过过孔与所述第一数据连接块连接。
  9. 根据权利要求8所述的显示基板，其中，所述显示区域还包括多个数据转接条，至少一个电路单元中，所述第一横向子线的第一端通过所述数据转接条与所述第一数据连接块连接；至少另一个电路单元中，所述第二横向子线的第一端通过所述数据转接条与所述第一数据连接块连接。
  10. 根据权利要求9所述的显示基板，其中，至少一个电路单元中，所述第一横向子线、所述第一数据连接块和所述数据转接条为相互连接的一体结构；至少另一个电路单元中，所述第二横向子线、所述第一数据连接块和所述数据转接条为相互连接的一体结构。
  11. 根据权利要求8所述的显示基板，其中，所述显示区域还包括多个第一虚设电极，至少一个所述第一虚设电极在一个电路单元中的位置和连接结构与至少一个所述第一数据连接块在另一个电路单元中的位置和连接结构相同。
  12. 根据权利要求11所述的显示基板，其中，至少一个电路单元中，所述第一竖向子线通过过孔与至少一个所述第一虚设电极连接；至少另一个电路单元中，所述第二竖向子线通过过孔与至少一个所述第一虚设电极连接。
  13. 根据权利要求7所述的显示基板，其中，所述显示区域还包括多个第二数据连接块；至少一个电路单元中，所述第二数据连接块与所述第一横向子线的第二端连接，所述第二竖向子线的第一端通过过孔与所述第二数据连接块连接。
  14. 根据权利要求13所述的显示基板，其中，至少一个电路单元中，所述第一横向子线和所述第二数据连接块为相互连接的一体结构。
  15. 根据权利要求13所述的显示基板，其中，所述显示区域还包括多个第二虚设电极，至少一个所述第二虚设电极在一个电路单元中的位置和连接结构与至少一个所述第二数据连接块在另一个电路单元中的位置和连接结构相同。
  16. 根据权利要求15所述的显示基板，其中，至少一个电路单元中，所述第一竖向子线通过过孔与至少一个所述第二虚设电极连接；至少另一个电路单元中，所述第二竖向子线通过过孔与至少一个所述第二虚设电极连接。
  17. 一种显示装置，包括如权利要求1至16任一项所述的显示基板。
  18. 一种显示基板的制备方法，所述显示基板包括显示区域和设置在所述显示区域一侧的绑定区域，所述显示区域包括形成多个单元行和多个单元列的多个电路单元，至少一个电路单元包括像素驱动电路；所述制备方法包括：
    在所述显示区域形成多条数据信号线和多条数据连接线，在所述绑定区域形成多条数据引出线，所述数据信号线被配置为向所述像素驱动电路提供数据信号，所述数据信号线通过所述数据连接线与所述数据引出线连接；至少一条数据连接线包括至少两条沿着第一方向延伸的横向子线和至少两条沿着第二方向延伸的竖向子线，所述两条横向子线设置在不同的单元行中，所述两条竖向子线设置在不同的单元列中，所述第一方向和所述第二方向交叉。
PCT/CN2025/082615 2024-04-18 2025-03-14 显示基板及其制备方法、显示装置 Pending WO2025218405A1 (zh)

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