WO2025199764A1 - 印刷电路板及印刷电路板的制备方法 - Google Patents

印刷电路板及印刷电路板的制备方法

Info

Publication number
WO2025199764A1
WO2025199764A1 PCT/CN2024/083902 CN2024083902W WO2025199764A1 WO 2025199764 A1 WO2025199764 A1 WO 2025199764A1 CN 2024083902 W CN2024083902 W CN 2024083902W WO 2025199764 A1 WO2025199764 A1 WO 2025199764A1
Authority
WO
WIPO (PCT)
Prior art keywords
insulating film
film layer
layer
circuit board
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2024/083902
Other languages
English (en)
French (fr)
Inventor
杨子霄
胡新毅
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
New H3C Technologies Co Ltd
Original Assignee
New H3C Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by New H3C Technologies Co Ltd filed Critical New H3C Technologies Co Ltd
Priority to PCT/CN2024/083902 priority Critical patent/WO2025199764A1/zh
Priority to CN202480000618.XA priority patent/CN120982214A/zh
Publication of WO2025199764A1 publication Critical patent/WO2025199764A1/zh
Pending legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses

Definitions

  • the present application relates to the technical field of circuit boards, and in particular to a printed circuit board and a method for preparing the printed circuit board.
  • the impedance of the signal during transmission is a key factor affecting the signal transmission quality.
  • the impedance of the signal during transmission in the existing printed circuit board needs to be optimized to achieve the purpose of improving the signal transmission quality.
  • the present application provides a printed circuit board and a method for preparing the printed circuit board.
  • a printed circuit board comprises:
  • the main layer includes multiple stacked insulating film layers, and the dielectric constants of adjacent insulating film layers are different; the main layer is provided with through holes penetrating the main layer, and the through holes include via holes penetrating each insulating film layer; among two adjacent insulating film layers, the average area of each cross-section of the via holes of one insulating film layer perpendicular to the stacking direction of the insulating film layers is a first area, and the dielectric constant is a first dielectric constant; the average area of each cross-section of the via holes of the other insulating film layer perpendicular to the stacking direction is a second area, and the dielectric constant is a second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area.
  • the orthographic projection of one of the via holes on a plane perpendicular to the stacking direction is the first projection
  • the orthographic projection of the other via hole on a plane perpendicular to the stacking direction is the first projection.
  • the orthographic projection on the plane is a second projection
  • the first projection falls on the second projection.
  • the main body layer further includes a plurality of pads, the pads are provided between two adjacent insulating film layers, and the through hole further includes a contact hole passing through the pads.
  • the outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction is the first edge
  • the edges of the positive projections of the two vias adjacent to the pad on the plane are the second edge and the third edge, respectively, and the second edge and the third edge are respectively located on the inner side of the first edge.
  • At least two of the insulating film layers in the main body layer are made of the same material, and the average areas of the via holes in the insulating film layers of the same material perpendicular to the stacking direction are substantially the same.
  • the total number of the insulating film layers is an odd number
  • the number of insulating film layers on both sides of the middle insulating film layer is the same
  • the materials and thicknesses of the two insulating film layers with the same number of insulating film layers spaced apart from the middle insulating film layer are the same.
  • the insulating film layer includes multiple insulating material layers arranged in a stacked manner, the total number of insulating material layers in the main layer is an odd number, and the number of insulating material layers on both sides of the middle insulating material layer is the same; the via includes sub-vias passing through each of the insulating material layers; in the insulating material layers on both sides of the middle insulating material layer, in the direction toward the middle insulating material layer, the cross-sectional area of the sub-vias of the insulating material layer perpendicular to the stacking direction gradually decreases.
  • the main body layer further includes a plurality of pads, each of which is provided between two adjacent insulating material layers, and the through hole further includes a contact hole passing through the pads.
  • the outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction is the fourth edge
  • the edges of the positive projections of the two sub-vias adjacent to the pad on the plane are the fifth edge and the sixth edge, respectively, and the fifth edge and the sixth edge are respectively located on the inner side of the fourth edge.
  • the signal line includes at least one of a differential signal line and a single-ended signal line.
  • forming the main body layer includes:
  • the portion of the opening located in the first insulating film layer is a first via hole
  • the material of the second insulating film layer in the area adjacent to the via hole is removed to form a second via hole, so that the area of the cross section of the second via hole perpendicular to the stacking direction is larger than the area of the cross section of the first via hole perpendicular to the stacking direction.
  • the main body layer includes two first insulating film layers and a second insulating film layer located between the two first insulating film layers, wherein the dielectric constant of the material of the first insulating film layer is greater than the dielectric constant of the second insulating film layer; forming the main body layer includes:
  • the first insulating film layer is respectively provided on two opposite surfaces of the second insulating film layer so that the first insulating film layer and the second insulating film layer are bonded to form a through-hole insulating film layer. And a first via hole connected to the second via hole.
  • the step of bonding the first insulating film layer to the second insulating film layer includes:
  • the second insulating film layer and the first insulating film layer that are stacked are pressed together to make the second insulating film layer adhere to the first insulating film layer.
  • the main body layer further includes a plurality of pads, the pads are provided between two adjacent insulating film layers, and the through hole includes a contact hole passing through the pads.
  • the insulating film layer includes a plurality of stacked insulating material layers; the via includes a sub-via that penetrates the insulating material layer; the printed circuit board further includes a conductive structure, the conductive structure including a conductive portion located in each of the sub-vias; and the steps of forming the main layer and the conductive structure include:
  • the main layer also includes a plurality of pads, the pads are provided between two adjacent insulating material layers, the through hole includes a contact hole passing through the pads, the contact hole and a sub-via adjacent to it are formed synchronously, and the conductive part is partially located in the contact hole.
  • Insulating material layers are respectively arranged on both sides of the structure obtained in the previous step, and the stacked insulating material layers are pressed together to bond the stacked insulating material layers together.
  • the total number of insulating material layers in the main layer is an odd number, and the number of insulating material layers on both sides of the middle insulating material layer is the same; the materials and thicknesses of the two insulating material layers with the same number of insulating material layers separated from the middle insulating material layer are the same.
  • the printed circuit board and the method for preparing the printed circuit board provided in the embodiments of the present application are such that, in two adjacent insulating film layers, the vias provided in the insulating film layer with the larger dielectric constant have a smaller average area of each cross-section parallel to the stacking direction of the insulating film layers. This helps to reduce the difference in impedance between adjacent vias and improve the continuity of impedance between adjacent vias, thereby reducing signal reflection during signal transmission, improving the return loss of the through-hole, and improving signal integrity.
  • the printed circuit board provided in the embodiments of the present application can make the impedance of each via substantially the same by adjusting the size of the vias in different insulating film layers, thereby effectively improving signal integrity.
  • FIG2 is a top view of a portion of the printed circuit board shown in FIG1 ;
  • FIG3 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application.
  • FIG4 is a top view of a portion of the printed circuit board shown in FIG3 ;
  • FIG5 is a partial cross-sectional view of a printed circuit board provided by yet another exemplary embodiment of the present application.
  • FIG6 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application.
  • FIG7 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application.
  • FIG8 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application.
  • FIG9 is a partial cross-sectional view of a printed circuit board provided by another exemplary embodiment of the present application.
  • 10 and 11 are diagrams showing simulation results of the printed circuit board shown in FIG5 ;
  • FIG13 is a flow chart of a method for preparing a printed circuit board provided by an exemplary embodiment of the present application.
  • FIG16 is a perspective schematic diagram of a partial structure of a first intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application.
  • FIG18 is a partial cross-sectional view of a third intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application.
  • FIG19 is a partial cross-sectional view of a fourth intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application.
  • FIG20 is a flow chart of a method for preparing a printed circuit board provided in yet another exemplary embodiment of the present application.
  • FIG23 is a perspective schematic diagram of a partial structure of a sixth intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application.
  • FIG24 is a partial cross-sectional view of a seventh intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application.
  • FIG25 is a partial cross-sectional view of an eighth intermediate structure of a printed circuit board provided by an exemplary embodiment of the present application.
  • FIG. 26 is a partial cross-sectional view of a ninth intermediate structure of a printed circuit board according to an exemplary embodiment of the present application.
  • first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other.
  • first information may also be referred to as second information, and similarly, second information may also be referred to as first information.
  • word “if” as used herein may be interpreted as "at the time of” or “when” or "in response to determining”.
  • a conductive layer 50' is provided between at least two adjacent insulating material layers 11' of the first insulating film layer 10', and a conductive layer 50' is provided between at least two adjacent insulating material layers 11' of the second insulating film layer 20'.
  • the conductive layer 50' located within the first insulating film layer 10' is provided with anti-pads 501' corresponding to each conductive structure 40'
  • the conductive layer 50' located within the second insulating film layer 20' is provided with anti-pads 502' corresponding to each conductive structure 40'.
  • anti-pads are openings that penetrate the conductive layer. As shown in Figure 2, the conductive structure 40' passes through the corresponding anti-pads 501' and 502' to prevent the conductive layer 50' from contacting the conductive structure 40'.
  • the impedance of the vias in each insulating film layer of the PCB is the same or has minimal differences can effectively improve signal reflection during signal transmission, improve the return loss of the differential vias, and enhance signal integrity.
  • the target impedance of the vias in each insulating film layer is determined based on the overall impedance requirements of the system, including the PCB and the electronic components connected to it. When the impedance of the vias in each insulating film layer is the same as or has minimal differences from the target impedance, signal quality is improved.
  • the inventors have discovered that a greater dielectric constant of the insulating film layer results in a lower impedance of the insulating film's via hole; a smaller diameter of the insulating film's via hole results in a lower impedance of the insulating film's via hole; and a larger anti-pad size of the conductive layer within the insulating film layer results in a higher impedance of the insulating film's via hole.
  • the impedance of the insulating film's via hole can be adjusted.
  • the material of the first insulating film layer 10 ′ is different from that of the second insulating film layer 20 ′.
  • the dielectric constant of the first insulating film layer 10 ′ is 3, the dielectric constant of the second insulating film layer 20 ′ is 4, and the target impedance of the via holes in each insulating film layer is 92 ohms. If the size of the anti-pad on the conductive layer of the first insulating film layer 10 ′ is the same as that of the anti-pad on the conductive layer of the second insulating film layer 20 ′, the impedance of the via hole in the first insulating film layer will be smaller than that of the via hole in the second insulating film layer.
  • Simulation software was used to simulate the first printed circuit board, yielding the following results: the impedance difference between the vias in each insulating film layer and the target impedance ranged from -2 ohms to 2 ohms.
  • the signal frequency was in the range of 0 to 26.56 GHz
  • the minimum return loss of the differential vias was -25 dB, indicating good signal integrity.
  • the sizes of each anti-pad in the first printed circuit board are referred to as ideal sizes.
  • the signal frequency range of 0 to 26.56 GHz refers to simulations performed at the fundamental frequency of 26.56 GHz for Ethernet 112G signals. The frequencies of the signals mentioned below are the same.
  • the size of the anti-pad on the conductive layer is limited by the traces located within the conductive layer, such as power signal lines. To avoid signal crosstalk and maintain the distance between traces adjacent to the anti-pad, a certain distance must be maintained between the traces and the anti-pad, resulting in the anti-pad on the conductive layer within the second insulating film layer being smaller than the ideal size.
  • the size of the anti-pad on the conductive layer within the second insulating film layer of the first PCB was reduced to the minimum size allowed by the process to produce a second PCB.
  • Simulation software was used to simulate the second PCB, yielding the following results: the maximum impedance of the vias in the first insulating film layer was 93 ohms, while the minimum impedance of the vias in the second insulating film layer was 84.5 ohms.
  • the maximum return loss of the differential vias was -16.5 dB, significantly reducing the signal integrity compared to the first PCB.
  • the PCB structure was further improved, reducing the aperture of the differential vias by 1 mil. This resulted in a third PCB.
  • Simulation software for this third PCB yielded the following results: the minimum impedance of the vias in the second insulating film layer was 89.5 ohms, while the maximum impedance of the vias in the first insulating film layer was 99.2 ohms.
  • the maximum return loss of the differential vias was -13.2 dB, significantly degrading the signal quality compared to the first PCB.
  • the present invention provides a printed circuit board and a method for manufacturing a printed circuit board, which can improve signal quality.
  • the printed circuit board and the printed circuit board in the present invention are described in detail below with reference to the accompanying drawings. The features of the following embodiments may complement or be combined with each other unless they conflict.
  • the embodiment of the present application provides a printed circuit board.
  • the printed circuit board includes a main body layer 10 , a conductive structure 20 , and a signal line 30 .
  • the main layer 10 includes a plurality of stacked insulating film layers 11; the dielectric materials of adjacent insulating film layers 11 are different, so that the dielectric constants of adjacent insulating film layers 11 are different; the main layer 10 is provided with a through hole 101 passing through the main layer 10, and the through hole 101 includes a via hole 111 passing through each insulating film layer 11; among two adjacent insulating film layers 11, the average area of each cross-section of the via hole 111 of one insulating film layer 11 perpendicular to the stacking direction X of the insulating film layer 11 is a first area, and the dielectric constant is the first dielectric constant; the average area of each cross-section of the via hole 111 of the other insulating film layer 11 perpendicular to the stacking direction is a second area, and the dielectric constant is the second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area.
  • the printed circuit board provided in the embodiment of the present application is configured such that the average area of each cross section of the via holes opened in the insulating film layer with a larger dielectric constant in two adjacent insulating film layers and parallel to the stacking direction of the insulating film layers is smaller, which helps to reduce the difference in impedance of the via holes in the adjacent insulating film layers, improve the continuity of the impedance of the adjacent via holes, and thus reduce signal reflection during signal transmission, improve the return loss of the through hole, and improve signal integrity; the printed circuit board provided in the embodiment of the present application can make the impedance of each via hole basically the same by adjusting the size of the via holes in different insulating film layers, effectively improving signal integrity. Wholeness.
  • the main body layer 10 further includes a plurality of conductive layers 40 .
  • Some conductive layers 40 are located between two adjacent insulating material layers 112 of the first insulating film layer 11 , while other conductive layers 40 are located between two adjacent insulating material layers 112 of the second insulating film layer 12 .
  • the conductive layers 40 may also be located between the first insulating film layer 11 and the second insulating film layer 12 .
  • the conductive layers 40 located between two adjacent insulating material layers 112 of the first insulating film layer 11 are provided with anti-pads 41
  • the conductive layers 40 located between two adjacent insulating material layers 112 of the second insulating film layer 12 are provided with anti-pads 42 .
  • the size of the anti-pad 41 provided on the conductive layer 40 between two adjacent insulating material layers 112 is smaller than the size of the anti-pad 42 provided on the conductive layer 40 between two adjacent insulating material layers 122. This configuration also helps to reduce the impedance difference between two adjacent vias.
  • two adjacent conductive structures 20 pass through the same anti-pad 42 , that is, the anti-pads corresponding to the two adjacent conductive structures 20 are connected.
  • the main body layer 10 may further include a pad structure 62.
  • the pad structures 62 are provided on two opposing surfaces of the main body layer 10, one corresponding to the conductive material portion 61.
  • the reflow ground via 102 further includes a contact hole 621 extending through the pad structure 62, with the conductive material portion 61 partially located within the contact hole 621.
  • Some pad structures 62 are provided on the same layer as the ground signal layer, and the ground signal layer is connected to each of the pad structures 62 provided on the same layer.
  • the ground signal layer is electrically connected to the conductive material portion 61 via the pad structures 62.
  • the pad structures 62 provided on the same layer and the ground signal layer may be an integral structure.
  • the main body layer 10 further includes a plurality of pads 50, and the through-hole 101 further includes a contact hole 51 extending through the pads 50.
  • the conductive structure 20 is in direct contact with the pads 50. Some of the pads 50 are connected to the signal lines 30, and the signal lines 30 are electrically connected to the conductive structure 20 through the pads 50 connected thereto. The provision of the pads 50 facilitates the electrical connection between the signal lines 30 and the conductive structure 20.
  • a pad 50 is provided between two adjacent insulating film layers 11.
  • the portions of the conductive structure 20 located within the two adjacent via holes 111 can be electrically connected via the pad 50, thereby improving the electrical connection reliability of the portions of the conductive structure 20 located within the two adjacent via holes 111.
  • the outer edge of the orthographic projection of the pad 50 onto a plane perpendicular to the stacking direction is a first edge 501.
  • the orthographic projection edges of the two vias 111 adjacent to the pad 50 onto the plane are a second edge 114 and a third edge 115, respectively.
  • the second edge 114 and the third edge 115 are located inward of the first edge 501.
  • the orthographic projection edge of the via with the larger average area onto the plane is the second edge 114
  • the orthographic projection edge of the via with the smaller average area onto the plane is the third edge 115.
  • This arrangement ensures that even if the geometric centers of two adjacent vias 111 shift relative to each other due to process variations during the manufacturing process, the portion of the conductive structure 20 located within the two adjacent vias 111 can be in contact with the pad 50 located between the two vias 111, thereby ensuring the electrical connection reliability of the portion of the conductive structure 20 located within the two adjacent vias 111.
  • some of the pads 50 connected to the conductive structure 20 on the printed circuit board are connected to the signal line 30. In other embodiments, all pads 50 on the main body layer may be connected to the signal line.
  • the orthographic projection of one via 111 on a plane perpendicular to the stacking direction is a first projection
  • the orthographic projection of the other via 111 on the plane is a second projection, with the first projection falling within the second projection. That is, of two adjacent vias 111 in the same through hole 101, the orthographic projection of the via 111 with a smaller average area on the plane is the first projection, and the orthographic projection of the via 111 with a larger average area on the plane is the second projection.
  • the size of the pad 50 can be set smaller, thereby reducing the impact of the pad 50 on the impedance of the via.
  • the via holes 111 of the same through hole 101 are coaxial.
  • the cross section of the via hole 111 perpendicular to the stacking direction X is circular. In this way, the via hole 111 is easy to process and the manufacturing process can be simplified. In other embodiments, the cross section of the via hole 111 perpendicular to the stacking direction X can be non-circular, for example, rectangular, irregular, or The shape, etc.
  • At least two insulating film layers 11 in the main layer 10 are made of the same material, and the vias 111 of the insulating film layers 11 made of the same material have substantially the same average area in each cross-section perpendicular to the stacking direction X.
  • substantially the same average area refers to the same average area, or a very small difference in average area.
  • the designed average areas are the same, but there may be a small difference in average area due to process errors. This configuration ensures that the vias in the insulating film layers 11 made of the same material have substantially the same impedance, which helps improve signal quality.
  • the total number of insulating film layers 11 in the main body layer 10 is an odd number
  • the number of insulating film layers 11 on either side of the central insulating film layer 11 is the same
  • the two insulating film layers 11 separated by the same number of insulating film layers 11 from the central insulating film layer 11 are made of the same material and have the same thickness.
  • the second insulating film layer 72 is the central insulating film layer, and no insulating film layer is interposed between the two first insulating film layers 71 and the second insulating film layer 72.
  • the two first insulating film layers 71 are made of the same material and have the same thickness.
  • the main body layer includes a first insulating film layer 71, two second insulating film layers 72 and two third insulating film layers 73; the two second insulating film layers 72 are located between the two third insulating film layers 73, and the first insulating film layer 71 is located between the two second insulating film layers 72; the first insulating film layer 71 is an insulating film layer located in the middle, and there is no insulating film layer between the two second insulating film layers 72 and the first insulating film layer 71, so the material and thickness of the two second insulating film layers 72 are the same; the two third insulating film layers 72 and the first insulating film layer 71 are the same.
  • the main body layer includes a third insulating film layer 73, two second insulating film layers 72, and two first insulating film layers 71.
  • the two second insulating film layers 72 are located between the two first insulating film layers 71, and the third insulating film layer 73 is located between the two second insulating film layers 72.
  • the third insulating film layer 73 is the insulating film layer located in the middle.
  • the two second insulating film layers 72 are made of the same material and have the same thickness
  • the two first insulating film layers 71 are made of the same material and have the same thickness.
  • the multiple conductive layers 40 in the main body layer 10 are symmetrically distributed on both sides of the insulating material layer located in the middle. This ensures that during the lamination process of the insulating material layers, the lamination forces on both sides of the insulating material layers and the conductive layers are more balanced, preventing deformation of the film layers and helping to improve the quality of the printed circuit board.
  • the shapes and sizes of the cross sections of the same via hole 111 perpendicular to the stacking direction X are substantially the same.
  • a pad 50 is provided between each adjacent insulating material layer 112.
  • the through hole 101 further includes a contact hole 51 extending through each pad 50.
  • the conductive structure 20 is in direct contact with the pad 50.
  • the orthographic projection of the pad 50 on the plane perpendicular to the stacking direction X is The outer edge of the fourth edge is the fourth edge, and the edges of the orthographic projections of the two sub-vias 113 adjacent to the pad 50 on the plane are the fifth edge and the sixth edge, respectively.
  • the fifth edge and the sixth edge are located on the inner side of the fourth edge. This arrangement ensures the reliability of the electrical connection between the two adjacent conductive parts.
  • At least one of the pads 50 is disposed on the same layer as the conductive layer 40 , and the pad 50 is located within the anti-pad of the conductive layer 40 disposed on the same layer.
  • the insulating film layer of the main layer 10 includes adjacent first insulating film layers 71 and second insulating film layers 72, the dielectric constant of the first insulating film layer 71 is greater than the dielectric constant of the second insulating film layer 72, and the through hole 101 includes a first via hole 711 passing through the first insulating film layer 71 and a second via hole 721 passing through the second insulating film layer 72, the average area of each cross section of the first via hole 711 perpendicular to the stacking direction X is a first area, the average area of each cross section of the second via hole 721 perpendicular to the stacking direction X is a second area, and the first area is smaller than the second area.
  • the first insulating film layers 71 and the second insulating film layers 72 are alternately arranged in the main body layer 10.
  • the main body layer 10 includes two first insulating film layers 71 and a second insulating film layer 72 located between the two first insulating film layers 71.
  • the main body layer 10 includes two second insulating film layers 72 and a first insulating film layer 71 located between the two second insulating film layers 72.
  • the main layer 10 further includes a third insulating film layer 73, and the dielectric constant of the material of the third insulating film layer 73 is greater than the dielectric constant of the material of the first insulating film layer 71;
  • the through hole 101 further includes a third via hole 731 passing through the third insulating film layer 73; the average area of each cross-section of the third via hole 731 perpendicular to the stacking direction X is a third area, and the third area is smaller than the first area.
  • the side of the second insulating film layer 72 away from the first insulating film layer 71 is provided with the third insulating film layer 73.
  • the main body layer includes two second insulating film layers 72 and a first insulating film layer 71 located between the two second insulating film layers 72.
  • the sides of the two second insulating film layers 72 away from the first insulating film layer 71 are respectively provided with the third insulating film layer 73.
  • edge film layer 73 in the direction toward the insulating film layer located in the middle (that is, the first insulating film layer 71), the average area of the via 111 gradually decreases.
  • the main body layer 10 includes two first insulating film layers 71 and two insulating film layers 72 located between the two first insulating film layers 71, and the third insulating film layer 73 is located between the two second insulating film layers 72; from the insulating film layer located in the middle (that is, the third insulating film layer 73) to the insulating film layers on both sides, the average area of the via 111 first increases and then decreases.
  • the main layer may include four or more insulating film layers with different dielectric constants, and the arrangement of the insulating film layers in the stacking direction can be selected according to needs.
  • Figure 10 is a graph showing the relationship between the impedance of the via and the test time
  • Figure 11 is a graph showing the relationship between the return loss and the signal frequency. According to Figures 10 and 11, it can be seen that the minimum impedance of the via in the insulating film layer is 88.2 ohms, and the maximum impedance of the via is 93.3 ohms. When the signal frequency is in the range of 0 to 26.56 GHz, the minimum return loss of the differential via is -21.6 dB.
  • the present application also provides a method for preparing a printed circuit board.
  • the preparation method includes the following steps: forming a main body layer; the main body layer includes a plurality of insulating film layers stacked together; the dielectric constants of adjacent insulating film layers are different; the main body layer is provided with through holes penetrating the main body layer, and the through holes include vias penetrating each insulating film layer; in two adjacent insulating film layers, the average area of each cross section of the via holes of one insulating film layer perpendicular to the stacking direction of the insulating film layers is a first area, and the dielectric constant is a first dielectric constant, and the average area of each cross section of the via holes of the other insulating film layer perpendicular to the stacking direction is a second area, and the dielectric constant is a second dielectric constant; the first dielectric constant is greater than the second dielectric constant, and the first area is smaller than the second area.
  • the main body layer also includes a signal line.
  • the printed circuit board is the printed circuit board shown in FIG. 3 .
  • the preparation method includes the following steps 110 to 140 .
  • an intermediate structure which includes a first insulating film layer, two second insulating film layers located on both sides of the first insulating film layer, and a signal line, wherein the dielectric constant of the material of the first insulating film layer is smaller than the dielectric constant of the second insulating film layer.
  • the intermediate structure includes three insulating film layers 11: a first insulating film layer 71 and two second insulating film layers 72, with the first insulating film layer 71 located between the two second insulating film layers 72. Both the first insulating film layer 71 and the second insulating film layer 72 include multiple insulating material layers 112.
  • the intermediate structure also includes multiple conductive layers 40, multiple solder pads 50, multiple solder pad structures 62, and multiple signal lines 30. Each conductive layer 40 is located between two adjacent insulating material layers 112, and the conductive layer 40 is provided with anti-pads 41 and 42. A solder pad 50 corresponding to the through hole 101 to be formed is provided between each adjacent insulating film layer 11.
  • the intermediate structure can be formed by the following steps: first, all the insulating material layers 112, the conductive layer 40, the pad structure 62 and the pad 50 of the main layer are stacked, a conductive layer is formed on the surface of part of the insulating material layer 112, a pad 50 is formed on the surface of part of the insulating material layer 112, and a pad structure 62 is formed on the surface of part of the insulating material layer 112, at least one pad is connected to the signal line and is located on the surface of the same insulating material layer; then, the stacked insulating material layers are pressed together so that the insulating material layers 112 are bonded together, and the two adjacent insulating material layers 112 are in direct contact, and the anti-pads 41 and 42 of the conductive layer are filled with the adjacent insulating material layers.
  • step 120 an opening is formed through the main layer, and the shapes and areas of the cross sections of the opening perpendicular to the stacking direction of the insulating film layer are substantially the same; the portion of the opening located in the first insulating film layer is a first via hole.
  • a first intermediate structure can be obtained as shown in Figure 14.
  • the openings 103 penetrate through each insulating film layer 11 and the corresponding pads 50.
  • step 130 material in the area of the second insulating film layer adjacent to the via hole is removed to form a second via hole, so that the cross-sectional area of the second via hole perpendicular to the stacking direction is larger than the cross-sectional area of the first via hole perpendicular to the stacking direction.
  • This step results in a second intermediate structure, shown in Figures 15 and 16 , which is the main layer.
  • contact holes 51 are formed on pads 50.
  • the main layer also has reflow vias 102 formed therein. Reflow vias 102 can be formed before or after the second vias are formed.
  • the portion of the opening located in the pad 50 is the first via; when the size of the contact hole 51 of the pad 50 is the same as the size of the adjacent second via 712, when a second drill bit is used to drill the second insulating film layer 72, the second drill bit removes the material of the area adjacent to the pad 50 and the via, thereby forming a contact hole.
  • the outer edge of the positive projection of the pad on the plane perpendicular to the stacking direction of the insulating film layer is the first edge
  • the edges of the positive projections of the two vias adjacent to the pad on the plane are the second edge and the third edge, respectively, and the second edge and the third edge are respectively located on the inner side of the first edge.
  • step 140 a conductive structure is formed in the through hole including the first via hole and the second via hole.
  • an electroplating process may be used to form the conductive structure in the through hole.
  • the method for preparing a printed circuit board further includes forming a conductive structure within the return ground via.
  • the step of forming the conductive structure within the return ground via can be performed simultaneously with step 140. This embodiment can produce the printed circuit board shown in FIG3 .
  • the intermediate structure may further include a third insulating film layer located on a side of each second insulating film layer away from the first insulating film layer, and the dielectric constant of the material of the third insulating film layer is smaller than the dielectric constant of the material of the second insulating film layer.
  • step 120 penetrates the third insulating film layer; in step 130, the second drill bit simultaneously removes the area of the third insulating film layer adjacent to the opening to obtain a sub-through hole located in the third insulating film layer; after step 130, the method for preparing a printed circuit board further includes: drilling the third insulating film layer using a third drill bit to remove the material of the area of the third insulating film layer adjacent to the sub-through hole to form a third via hole penetrating the third insulating film layer; The maximum outer diameter of the third drill bit is greater than the maximum outer diameter of the second drill bit.
  • the main body layer includes two second insulating film layers and a first insulating film layer located between the two second insulating film layers.
  • the dielectric constant of the material of the first insulating film layer is greater than the dielectric constant of the second insulating film layer.
  • At least one surface of at least one of the first insulating film layer and the second insulating film layer is provided with a signal line.
  • the preparation method includes the following steps 210 to 230.
  • step 210 a first via hole is formed through the first insulating film layer.
  • the first insulating film layer 71 includes multiple stacked insulating material layers 112 ; the third intermediate structure also includes a conductive layer 40 , a signal line 30 , and a pad 50 .
  • the conductive layer 40 is located on a surface of the first insulating film layer 71 .
  • the first insulating film layer 71 has two opposing surfaces provided with pads 50 and signal lines corresponding to the first vias 711 , respectively.
  • the signal lines 30 are connected to the pads 50 , and the first vias 711 penetrate each insulating film layer and the corresponding pads 50 .
  • the conductive layer 40 , the signal line 30 , the pad 50 and the insulating material layer 112 are stacked and then bonded together using a lamination process.
  • a first drill bit may be used to drill the first insulating film layer to form a first via hole.
  • bonding the second insulating film layer to the first insulating film layer can produce a fourth intermediate structure as shown in FIG19 .
  • the second insulating film layer 72 includes multiple insulating material layers 112
  • the fourth intermediate structure further includes a conductive layer 40 located between adjacent insulating material layers of the second insulating film layer 72 , a pad 50 located on a surface of the second insulating film layer 72 , a signal line 30 , and a pad structure.
  • bonding the second insulating film layer to the first insulating film layer includes laminating the second insulating film layer and the first insulating film layer, and laminating the layer to bond the second insulating film layer to the first insulating film layer.
  • an insulating material layer, a conductive layer, and a pad of the second insulating film layer are disposed on two opposing surfaces of the third intermediate structure in a laminating order of the film layers, and then laminating the layers.

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Abstract

本申请提供一种印刷电路板及印刷电路板的制备方法。印刷电路板包括主体层。主体层包括多个层叠设置的绝缘膜层，相邻所述绝缘膜层的介电常数不同；所述主体层设有贯穿所述主体层的通孔，所述通孔包括贯穿各所述绝缘膜层的过孔；相邻两个所述绝缘膜层中，其中一个所述绝缘膜层的过孔与所述绝缘膜层的层叠方向垂直的各截面的平均面积为第一面积，介电常数为第一介电常数，另一个所述绝缘膜层的过孔与所述层叠方向垂直的各截面的平均面积为第二面积，介电常数为第二介电常数；所述第一介电常数大于所述第二介电常数，所述第一面积小于所述第二面积。

Description

印刷电路板及印刷电路板的制备方法 技术领域
本申请涉及电路板技术领域，特别涉及一种印刷电路板及印刷电路板的制备方法。
背景技术
印刷电路板是重要的电子部件，是电子元器件的支撑体，是电子元器件电气连接的提供者。随着电子通信技术的发展，数据传输速率的要求也逐步提升，对印刷电路板的信号传输质量要求也越来越高。
信号在传输过程中的阻抗是影响信号传输质量的关键因素，现有的印刷电路板中信号在传输过程中的阻抗有待优化，以达到提升信号传输质量的目的。
发明内容
本申请提供了一种印刷电路板及印刷电路板的制备方法。
根据本申请实施例的第一方面，提供了一种印刷电路板。所述印刷电路板包括：
主体层，包括多个层叠设置的绝缘膜层，相邻所述绝缘膜层的介电常数不同；所述主体层设有贯穿所述主体层的通孔，所述通孔包括贯穿各所述绝缘膜层的过孔；相邻两个所述绝缘膜层中，其中一个所述绝缘膜层的过孔与所述绝缘膜层的层叠方向垂直的各截面的平均面积为第一面积，介电常数为第一介电常数，另一个所述绝缘膜层的过孔与所述层叠方向垂直的各截面的平均面积为第二面积，介电常数为第二介电常数；所述第一介电常数大于所述第二介电常数，所述第一面积小于所述第二面积。
在一个实施例中，同一所述通孔的相邻两个过孔中，其中一个所述过孔在与所述层叠方向垂直的平面上的正投影为第一投影，另一所述过孔在 所述平面上的正投影为第二投影，所述第一投影落在所述第二投影。
在一个实施例中，所述主体层还包括多个焊盘，相邻两个所述绝缘膜层之间设有所述焊盘，所述通孔还包括贯穿所述焊盘的接触孔。
在一个实施例中，所述焊盘在与所述层叠方向垂直的平面上的正投影的外边缘为第一边缘，与所述焊盘相邻的两个所述过孔在所述平面上的正投影的边缘分别为第二边缘和第三边缘，所述第二边缘及所述第三边缘分别位于所述第一边缘的内侧。
在一个实施例中，所述主体层中的至少两个所述绝缘膜层的材料相同，且材料相同的绝缘膜层的过孔与所述层叠方向垂直的各截面的平均面积基本相同。
在一个实施例中，所述绝缘膜层的总数为奇数，位于中间的绝缘膜层两侧的绝缘膜层的数量相同，与所述位于中间的绝缘膜层间隔的绝缘膜层数量相同的两个绝缘膜层的材料及厚度均相同。
在一个实施例中，同一所述过孔与所述层叠方向垂直的各截面的形状及尺寸均基本相同。
在一个实施例中，所述绝缘膜层包括多个层叠设置的绝缘材料层，所述主体层中绝缘材料层的总数为奇数，位于中间的绝缘材料层两侧的绝缘材料层的数量相同；所述过孔包括贯穿各所述绝缘材料层的子过孔；位于中间的绝缘材料层两侧的绝缘材料层中，在朝向所述位于中间的绝缘材料层的方向上，所述绝缘材料层的子过孔与所述层叠方向垂直的截面面积逐渐减小。
在一个实施例中，所述主体层还包括多个焊盘，相邻两个所述绝缘材料层之间均设有所述焊盘，所述通孔还包括贯穿所述焊盘的接触孔。
在一个实施例中，所述焊盘在与所述层叠方向垂直的平面上的正投影的外边缘为第四边缘，与所述焊盘相邻的两个所述子过孔在所述平面上的正投影的边缘分别为第五边缘和第六边缘，所述第五边缘及所述第六边缘分别位于所述第四边缘的内侧。
在一个实施例中，所述信号线包括差分信号线与单端信号线中的至少一种。
在一个实施例中，所述主体层的绝缘膜层包括相邻的第一绝缘膜层和第二绝缘膜层，所述第一绝缘膜层的介电常数大于所述第二绝缘膜层的介电常数，所述通孔包括贯穿所述第一绝缘膜层的第一过孔及贯穿所述第二绝缘膜层的第二过孔，所述第一过孔与所述层叠方向垂直的各截面的平均面积为第一面积，所述第二过孔与所述层叠方向垂直的各截面的平均面积为第二面积，所述第一面积小于所述第二面积；
所述主体层中所述第一绝缘膜层与所述第二绝缘膜层交替排布；或者，
所述主体层还包括第三绝缘膜层，所述第三绝缘膜层的材料介电常数小于所述第二绝缘膜层的材料的介电常数；所述通孔还包括贯穿所述第三绝缘膜层的第三过孔；所述第三过孔与所述层叠方向垂直的各截面的平均面积为第三面积，所述第三面积大于所述第二面积；所述第二绝缘膜层远离所述第一绝缘膜层的一侧设有所述第三绝缘膜层，或所述第一绝缘膜层远离所述第二绝缘膜层的一侧设有所述第三绝缘膜层。
根据本申请实施例的第二方面，提供了一种印刷电路板的制备方法，所述制备方法包括：
形成主体层；所述主体层包括多个层叠设置的绝缘膜层；相邻所述绝缘膜层的介电常数不同；所述主体层设有贯穿所述主体层的通孔，所述通孔包括贯穿各所述绝缘膜层的过孔；相邻两个所述绝缘膜层中，其中一个所述绝缘膜层的过孔与所述绝缘膜层的层叠方向垂直的各截面的平均面积为第一面积，介电常数为第一介电常数，另一个所述绝缘膜层的过孔与所述层叠方向垂直的各截面的平均面积为第二面积，介电常数为第二介电常数；所述第一介电常数大于所述第二介电常数，所述第一面积小于所述第二面积。
在一个实施例中，所述形成主体层，包括：
提供中间结构，所述中间结构包括第一绝缘膜层及位于所述第一绝缘 膜层两侧的两个第二绝缘膜层，所述第一绝缘膜层的材料的介电常数小于所述第二绝缘膜层的介电常数；
形成贯穿所述主体层的开孔，所述开孔与所述绝缘膜层的层叠方向垂直的各个截面的形状及面积均基本相同；所述开孔位于所述第一绝缘膜层的部分为第一过孔；
将所述第二绝缘膜层与所述过孔相邻的区域的材料去除，形成第二过孔，使所述第二过孔与所述层叠方向垂直的截面的面积大于所述第一过孔与所述层叠方向垂直的截面的面积。
在一个实施例中，所述形成贯穿所述主体层的开孔，包括：采用第一钻头对所述主体层进行钻孔，形成贯穿所述主体层的开孔；
所述将所述第二绝缘膜层与所述过孔相邻的区域的材料去除，包括：采用第二钻头对所述第二绝缘膜层进行钻孔，所述第二钻头的最大外径大于所述第一钻头的最大外径，所述第二钻头在钻孔时部分位于所述开孔内。
在一个实施例中，所述主体层包括两个第二绝缘膜层及位于两个所述第二绝缘膜层之间的第一绝缘膜层，所述第一绝缘膜层的材料的介电常数大于所述第二绝缘膜层的介电常数；所述形成主体层，包括：
形成贯穿第一绝缘膜层的第一过孔；
在所述第一绝缘膜层的相对两个表面分别设置所述第二绝缘膜层，使所述第一绝缘膜层与所述第二绝缘膜层粘合，形成贯穿所述第二绝缘膜层且与所述第一过孔连通的第二过孔；
或者，
所述主体层包括两个第一绝缘膜层及位于两个所述第一绝缘膜层之间的第二绝缘膜层，所述第一绝缘膜层的材料的介电常数大于所述第二绝缘膜层的介电常数；所述形成主体层，包括：
形成贯穿第二绝缘膜层的第二过孔；
在所述第二绝缘膜层的相对两个表面分别设置所述第一绝缘膜层，使所述第一绝缘膜层与所述第二绝缘膜层粘合，形成贯穿所述第一绝缘膜层 且与所述第二过孔连通的第一过孔。
在一个实施例中，所述使所述第一绝缘膜层与所述第二绝缘膜层粘合，包括：
对层叠设置的所述第二绝缘膜层与所述第一绝缘膜层叠设置进行压合，使所述第二绝缘膜层与所述第一绝缘膜层粘合。
在一个实施例中，所述主体层还包括多个焊盘，相邻两个所述绝缘膜层之间设有所述焊盘，所述通孔包括贯穿所述焊盘的接触孔。
在一个实施例中，所述焊盘在与所述层叠方向垂直的平面上的正投影的外边缘为第一边缘，与所述焊盘相邻的两个所述过孔在所述平面上的正投影的边缘分别为第二边缘和第三边缘，所述第二边缘及所述第三边缘分别位于所述第一边缘的内侧。
在一个实施例中，所述绝缘膜层包括多个层叠设置的绝缘材料层；所述过孔包括贯穿绝缘材料层的子过孔；所述印刷电路板还包括导电结构，所述导电结构包括位于各所述子过孔内的导电部；形成所述主体层及所述导电结构的步骤包括：
在一个绝缘材料层形成子过孔，并形成位于子过孔内的导电部；
重复执行以下步骤，直至形成所述主体层及所述导电结构：
在上一步骤得到的结构的相对两个表面分别设置未设有子过孔的绝缘材料层，并使层叠设置的绝缘材料层粘合；在未设子过孔的绝缘材料层上形成子过孔，并形成位于子过孔内的导电部。
在一个实施例中，所述主体层还包括多个焊盘，相邻两个所述绝缘材料层之间设有所述焊盘，所述通孔包括贯穿所述焊盘的接触孔，所述接触孔和与其相邻的一个所述子过孔同步形成，所述导电部部分位于所述接触孔内。
在一个实施例中，所述子过孔采用激光刻蚀工艺形成。
在一个实施例中，所述在上一步骤得到的结构的相对两个表面分别设置未设有子过孔的绝缘材料层，并使层叠设置的绝缘材料层粘合，包括：
在上一步骤得到的结构的两侧分别设置绝缘材料层，对层叠设置的绝缘材料层进行压合，使层叠设置的绝缘材料层粘合。
在一个实施例中，所述主体层中绝缘材料层的总数为奇数，位于中间的绝缘材料层两侧的绝缘材料层的数量相同；与所述位于中间的绝缘材料层间隔的绝缘材料层数量相同的两个绝缘材料层的材料及厚度均相同。
本申请实施例提供的印刷电路板及印刷电路板的制备方法，通过设置相邻两个绝缘膜层中，介电常数较大的绝缘膜层开设的过孔与绝缘膜层的层叠方向平行的各截面的平均面积较小，有助于减小相邻过孔的阻抗的差值，提升相邻过孔的阻抗的连续性，进而减少传输信号过程中的信号反射，改善通孔的回波损耗，提升信号完整性；本申请实施例提供的印刷电路板通过调节不同绝缘膜层过孔的尺寸，可使得各过孔的阻抗基本相同，有效提升信号完整性。
附图说明
图1是本申请一示例性实施例提供的印刷电路板的局部剖视图；
图2是图1所示的印刷电路板的部分结构的俯视图；
图3是本申请另一示例性实施例提供的印刷电路板的局部剖视图；
图4是图3所示的印刷电路板的部分结构的俯视图；
图5是本申请再一示例性实施例提供的印刷电路板的局部剖视图；
图6是本申请又一示例性实施例提供的印刷电路板的局部剖视图；
图7是本申请又一示例性实施例提供的印刷电路板的局部剖视图；
图8是本申请又一示例性实施例提供的印刷电路板的局部剖视图；
图9是本申请又一示例性实施例提供的印刷电路板的局部剖视图；
图10及图11是对图5所述的印刷电路板进行仿真得到的结果图；
图12是本申请一示例性实施例提供的印刷电路板的局部剖视图；
图13是本申请一示例性实施例提供的印刷电路板的制备方法的流程图；
图14是本申请一示例性实施例提供的印刷电路板的第一中间结构的局部剖视图；
图15是本申请一示例性实施例提供的印刷电路板的第二中间结构的局部剖视图；
图16是本申请一示例性实施例提供的印刷电路板的第一中间结构的局部结构的立体示意图；
图17是本申请另一示例性实施例提供的印刷电路板的制备方法的流程图；
图18是本申请一示例性实施例提供的印刷电路板的第三中间结构的局部剖视图；
图19是本申请一示例性实施例提供的印刷电路板的第四中间结构的局部剖视图；
图20是本申请再一示例性实施例提供的印刷电路板的制备方法的流程图；
图21是本申请一示例性实施例提供的印刷电路板的第五中间结构的局部剖视图；
图22是本申请一示例性实施例提供的印刷电路板的第六中间结构的局部剖视图；
图23是本申请一示例性实施例提供的印刷电路板的第六中间结构的局部结构的立体示意图；
图24是本申请一示例性实施例提供的印刷电路板的第七中间结构的局部剖视图；
图25是本申请一示例性实施例提供的印刷电路板的第八中间结构的局部剖视图；
图26是本申请一示例性实施例提供的印刷电路板的第九中间结构的局部剖视图。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相似的要素。以下示例性实施例中所描述的实施例并不代表与本申请相一致的所有实施例。相反，它们仅是与如所附权利要求书中所详述的、本申请的一些方面相一致的装置和方法的例子。
在本申请使用的术语是仅仅出于描述特定实施例的目的，而非旨在限制本申请。在本申请和所附权利要求书中所使用的单数形式的“一种”、“所述”和“该”也旨在包括多数形式，除非上下文清楚地表示其他含义。还应当理解，本文中使用的术语“和/或”是指并包含一个或多个相关联的列出项目的任何或所有可能组合。
应当理解，尽管在本申请可能采用术语第一、第二、第三等来描述各种信息，但这些信息不应限于这些术语。这些术语仅用来将同一类型的信息彼此区分开。例如，在不脱离本申请范围的情况下，第一信息也可以被称为第二信息，类似地，第二信息也可以被称为第一信息。取决于语境，如在此所使用的词语“如果”可以被解释成为“在……时”或“当……时”或“响应于确定”。
印刷电路板包括多个层叠设置的绝缘膜层及多个信号线，印刷电路板设有通孔，通孔内设有导电结构，信号线与导电结构电连接。信号线可以包括差分信号线，与差分信号线相连的导电结构所在的通孔为差分过孔，差分过孔的阻抗对差分信号线传输信号的信号完整性影响较大。
如图1所示，印刷电路板包括两个第一绝缘膜层10’、一个第二绝缘膜层20’、焊盘30’、导电结构40’及信号线60’。第二绝缘膜层20’位于两个第一绝缘膜层10’之间。第一绝缘膜层10’和第二绝缘膜层20’分别包括多个层叠设置的绝缘材料层11’。第一绝缘膜层10’的材料的介电常数小于第二绝缘膜层20’的材料的介电常数。部分焊盘30’位于两个 第一绝缘膜层10’远离第二绝缘膜层20’的表面，部分焊盘30’位于相邻两个绝缘材料层11’之间。印刷电路板设有差分过孔101’，差分过孔101’的孔径各处基本相同；差分过孔101’包括贯穿各绝缘膜层11’的过孔及贯穿焊盘30’的接触孔，导电结构40’位于差分过孔101’内。信号线60’通过焊盘30’与导电结构40’相连。所述印刷电路板还包括多个导电层50’，第一绝缘膜层10’的至少两个相邻绝缘材料层11’之间设有导电层50’，第二绝缘膜层20’的至少两个相邻绝缘材料层11’之间设有导电层50’，位于第一绝缘膜层10’内的导电层50’设有与各导电结构40’对应的反焊盘501’，位于第二绝缘膜层20’内的导电层50’设有与各导电结构40’对应的反焊盘502’。本申请中反焊盘为贯穿导电层的开孔。如图2所示，导电结构40’穿过对应的反焊盘501’、502’，以避免导电层50’与导电结构40’接触。
信号在经过导电结构传输过程中，印刷电路板的各个绝缘膜层的过孔的阻抗相同或差别很小时，可有效改善导电结构在传输信号的过程中的信号反射，改善差分过孔的回波损耗，提升信号完整性。根据包括印刷电路板及与印刷电路板相连的电子元器件的系统的总阻抗要求，确定出各个绝缘膜层的过孔的目标阻抗。在各个绝缘膜层的过孔的阻抗与目标阻抗相同或差别很小时，有助于提升信号质量。
发明人研究发现，绝缘膜层的介电常数越大，绝缘膜层的过孔的阻抗越小；绝缘膜层的过孔的孔径越小，绝缘膜层的过孔的阻抗越小；位于绝缘膜层内的导电层的反焊盘尺寸越大，绝缘膜层的过孔的阻抗越大。改变绝缘膜层的过孔的孔径及反焊盘的尺寸，可调节绝缘膜层的过孔的阻抗。
图1所示的印刷电路板中，第一绝缘膜层10’的材料与第二绝缘膜层20’的材料不同，第一绝缘膜层10’的介电常数为3，第二绝缘膜层20’的介电常数为4，各绝缘膜层的过孔的目标阻抗为92欧姆。若位于第一绝缘膜层10’的导电层的反焊盘的尺寸与位于第二绝缘膜层20’的导电层的反焊盘的尺寸相同，会使得第一绝缘膜层的过孔的阻抗小于第二绝缘膜的 过孔的阻抗。在各反焊盘的尺寸不受限制的情况下，可通过调节各反焊盘的尺寸，使位于第二绝缘膜层内的导电层的反焊盘的尺寸大于位于第一绝缘膜层内的导电层的反焊盘的尺寸，来减小第一绝缘膜层的过孔的阻抗与第二绝缘膜层的过孔的阻抗的差值，以使各绝缘膜层的过孔的阻抗与目标阻抗接近。在对各反焊盘的尺寸进行优化后，得到第一印刷电路板，采用仿真软件对第一印刷电路板进行仿真得出如下结果：各绝缘膜层的过孔的阻抗与目标阻抗的差值范围为-2欧姆～2欧姆，信号的频率在0～26.56GHz范围内时，差分过孔的回波损耗最小值为-25dB，信号完整性较好。第一印刷电路板中各反焊盘的尺寸称为理想尺寸。信号的频率在0～26.56GHz范围内指的是在以太网112G信号的基础频率26.56GHz的情况下进行仿真。后文所提到的信号的频率相同。
然而在印刷电路板的设计中，导电层的反焊盘的尺寸会受到位于导电层中走线例如电源信号线的限制，为避免信号串扰，保证与反焊盘相邻的走线之间的距离，走线与反焊盘需保证一定的距离，使得位于第二绝缘膜层内的导电层的反焊盘的尺寸小于理想尺寸。对第一印刷电路板的位于第二绝缘膜层内的导电层的反焊盘的尺寸减小至工艺允许最小尺寸后得到第二印刷电路板。采用仿真软件对第二印刷电路板进行仿真得出如下结果：第一绝缘膜层的过孔的阻抗的最大值为93欧姆，第二绝缘膜层的过孔的阻抗的最小值为84.5欧姆，信号的频率在0～26.56GHz范围内时，差分过孔的回波损耗的最大值为-16.5dB，与第一印刷电路板相比，信号完整性明显下降。
由于第二绝缘膜层的过孔的阻抗偏低，为了进一步提升信号质量，对印刷电路板的结构进一步改进，使差分过孔的孔径减小1mil，得到第三印刷电路板。采用仿真软件对第三印刷电路板进行仿真得出如下结果：第二绝缘膜层的过孔的阻抗的最小值为89.5欧姆，第一绝缘膜层的过孔的阻抗的最大值为99.2欧姆，信号的频率在0～26.56GHz范围内时，差分过孔的回波损耗的最大值为-13.2dB，与第一印刷电路板相比，信号质量明显下降。
由此可以发现，上述对差分过孔的孔径及反焊盘的尺寸的调整，无法有效提升信号质量。
本申请实施例提供了一种印刷电路板及印刷电路板的制备方法，可提升信号质量。下面结合附图，对本申请实施例中的印刷电路板及印刷电路板进行详细说明。在不冲突的情况下，下述的实施例中的特征可以相互补充或相互组合。
本申请实施例提供了一种印刷电路板。如图3所示，所述印刷电路板包括主体层10、导电结构20及信号线30。
所述主体层10包括多个层叠设置的绝缘膜层11；相邻所述绝缘膜层11介电材料不同，使得相邻绝缘膜层11的介电常数不同；所述主体层10设有贯穿所述主体层10的通孔101，所述通孔101包括贯穿各所述绝缘膜层11的过孔111；相邻两个所述绝缘膜层11中，其中一个所述绝缘膜层11的过孔111与所述绝缘膜层11的层叠方向X垂直的各截面的平均面积为第一面积，介电常数为第一介电常数，另一个所述绝缘膜层11的过孔111与所述层叠方向垂直的各截面的平均面积为第二面积，介电常数为第二介电常数；所述第一介电常数大于所述第二介电常数，所述第一面积小于所述第二面积。过孔111与层叠方向X的各个截面的面积均相同时，各个截面的面积与平均面积均相同；过孔111与层叠方向X垂直的各个截面的面积不全相同时，平均面积为所有截面的面积的平均值。所述导电结构20位于所述主体层10的通孔101内，将通孔101全部填满。所述信号线30与所述导电结构20电连接。
本申请实施例提供的印刷电路板，通过设置相邻两个绝缘膜层中，介电常数较大的绝缘膜层开设的过孔与绝缘膜层的层叠方向平行的各截面的平均面积较小，有助于减小相邻绝缘膜层的过孔的阻抗的差值，提升相邻过孔的阻抗的连续性，进而减少传输信号过程中的信号反射，改善通孔的回波损耗，提升信号完整性；本申请实施例提供的印刷电路板通过调节不同绝缘膜层过孔的尺寸，可使得各过孔的阻抗基本相同，有效提升信号完 整性。
在一个实施例中，所述信号线包括差分信号线与单端信号线中的至少一种。差分信号线与单端信号线的信号完整性受过孔的阻抗的影响较大，将与差分信号线与单端信号线相连的导电结构所在的通孔设计为上述的结构，可有效提升其传输的信号的完整性。与差分信号线相连的导电结构所在的通孔为差分过孔，所述主体层可设有多对差分过孔，同一对差分过孔的两个差分过孔相邻设置。单端信号线可以为并行总线。
在一个实施例中，如图3所示，所述第一绝缘膜层11及所述第二绝缘膜层12均包括多个层叠设置的绝缘材料层112。同一绝缘膜层的各绝缘材料层的厚度可相同。相邻绝缘材料层直接接触，不存在间隙。信号线30可位于相邻两个绝缘材料层112之间，也可位于主体层10的表面。
在一个实施例中，如图3所示，所述主体层10还包括多个导电层40，一些导电层40位于第一绝缘膜层11的相邻两个绝缘材料层112之间，另一些导电层40位于第二绝缘膜层12的相邻两个绝缘材料层112之间。导电层40还可位于第一绝缘膜层11与第二绝缘膜层12之间。位于第一绝缘膜层11的相邻两个绝缘材料层112之间的导电层40设有反焊盘41，位于第二绝缘膜层12的相邻两个绝缘材料层112之间的导电层40设有反焊盘42，每一导电层分别设有与导电结构20对应的反焊盘。导电结构20穿设其对应的反焊盘41、42，以避免导电层40与导电结构20接触而发生短路的情况。相邻两个导电结构20可穿过同一个反焊盘42。绝缘材料层填充反焊盘42。导电层40可以是接地信号层(GND层)，也可以是电源信号层(POWER层)。
在一个实施例中，如图3所示，相邻两个绝缘材料层112之间的导电层40开设的反焊盘41的尺寸小于两个绝缘材料层122之间的导电层40开设的反焊盘42的尺寸。如此设置，也有助于相邻两个过孔的阻抗的差值。
在一个实施例中，如图3所示，相邻两个导电结构20穿设同一个反焊盘42，也即是相邻两个导电结构20对应的反焊盘连通。
在一个实施例中，导电结构20可全部将其所在的通孔101填满。在其他实施例中，导电结构20可为空心结构，仅覆盖其所在的通孔101的孔壁。
在一个实施例中，如图3所示，所述主体层10还设有回流地过孔102，回流地过孔102贯穿主体层10，所述印刷电路板还包括位于回流地过孔102内的导电材料部61。回流地过孔102可减小导电结构20传输的信号的回流路径，有利于过孔的阻抗的控制。回流地过孔102与层叠方向X垂直的各个截面的面积及形状可均相同，例如回流地过孔102可呈圆柱形。
在一个实施例中，如图3所示，所述主体层10还可包括焊盘结构62，主体层10的相对两个表面分别设有与导电材料部61一一对应的焊盘结构62，回流地过孔102还包括贯穿焊盘结构62的接触孔621，导电材料部61部分位于接触孔621内。一些焊盘结构62与接地信号层同层设置，且接地信号层分别和与其同层设置的焊盘结构62相连，接地信号层通过焊盘结构62与导电材料部61电连接。同层设置的焊盘结构62与接地信号层可为一体结构。
在一个实施例中，如图3所示，所述主体层10还包括多个焊盘50，所述通孔101还包括贯穿所述焊盘50的接触孔51，所述导电结构20与所述焊盘50直接接触。其中一部分焊盘50与所述信号线30连接，信号线30通过与其相连的焊盘50与导电结构20电连接。焊盘50的设置便于信号线30与导电结构20的电连接。
在一个实施例中，如图3所示，所述主体层相对的两个表面中分别设有焊盘50，位于同一表面的焊盘50与导电结构20一一对应，导电结构20部分位于对应的焊盘50的接触孔51内。导电结构20的表面与焊盘50位于同一侧的表面可齐平。
在一个实施例中，如图3所示，相邻两个所述绝缘膜层11之间设有所述焊盘50。如此，在相邻两个过孔111的中心发生偏移时，导电结构20位于相邻两个过孔111内的部分可通过焊盘50电连接，有助于提升导电结构20位于相邻两个过孔111内的部分的电连接可靠性。
在一个实施例中，如图4所示，所述焊盘50的接触孔51在与所述层叠方向X垂直的平面上的正投影和与其相邻的其中一个过孔111朝向焊盘50在所述平面上的正投影重合。
在一个实施例中，如图4所示，所述焊盘50在与所述层叠方向垂直的平面上的正投影的外边缘为第一边缘501，与所述焊盘50相邻的两个所述过孔111在所述平面上的正投影的边缘分别为第二边缘114和第三边缘115，所述第二边缘114及所述第三边缘115分别位于所述第一边缘501的内侧。图4所示的实施例中，上述平均面积较大的过孔在所述平面上的正投影的边缘为第二边缘114，上述平均面积较小的过孔在所述平面上的正投影的边缘为第三边缘115。如此设置，即使在制备过程中由于工艺偏差导致相邻两个过孔111的几何中心发生相对偏移，也可保证导电结构20位于相邻两个过孔111内的部分与位于该两个过孔111之间的焊盘50接触，保证导电结构20位于相邻两个过孔111内的部分的电连接可靠性。
在一个实施例中，如图3所示，所述印刷电路板与导电结构20相连的焊盘50中，部分焊盘50与信号线30相连。在其他实施例中，主体层的各个焊盘50可均与信号线相连。
在一个实施例中，同一所述通孔101的相邻两个过孔111中，其中一个所述过孔111在与所述层叠方向垂直的平面上的正投影为第一投影，另一所述过孔111在所述平面上的正投影为第二投影，所述第一投影落在所述第二投影内。也即是，同一通孔101的相邻两个过孔111中，上述平均面积较小的过孔111在所述平面上的正投影为第一投影，上述平均面积较大的过孔111在所述平面上的正投影为第二投影。如此设置，可将焊盘50的尺寸设置得小一些，从而可减小焊盘50对过孔的阻抗的影响。
进一步地，同一通孔101的各个过孔111同轴。
在一个实施例中，如图4所示，所述过孔111与层叠方向X垂直的截面呈圆形。如此过孔111易于加工，可简化制备工艺。在其他实施例中，所述过孔111与层叠方向X垂直的截面可呈非圆形，例如可呈矩形、不规 则形状等。
在一个实施例中，所述主体层10中至少两个所述绝缘膜层11的材料相同，且材料相同的绝缘膜层11的过孔111与所述层叠方向X垂直的各截面的平均面积基本相同。其中平均面积基本相同指的是平均面积相同，或者平均面积差别很小，例如设计的平均面积相同，但由于工艺误差导致平均面积存在较小差别。如此设置，材料相同的绝缘膜层11的过孔的阻抗基本相同，有助于提升信号质量。
在一个实施例中，所述主体层10中的所述绝缘膜层11的总数为奇数，位于中间的绝缘膜层11两侧的绝缘膜层11的数量相同，与所述位于中间的绝缘膜层11间隔的绝缘膜层11数量相同的两个绝缘膜层11的材料及厚度均相同。在制备印刷电路板的过程中，可采用压合工艺使主体层的所有膜层粘合，上述设置可使得在对绝缘材料层进行压合过程中可使得各绝缘材料层两侧受到的作用力较平衡，可防止位于中间的绝缘膜层11发生变形，有助于提升印刷电路板的质量。
图3所示的实施例中，主体层10包括一个第一绝缘膜层71及位于第一绝缘膜层71两侧的两个第二绝缘膜层72，第一绝缘膜层71为位于中间的绝缘膜层，两个第二绝缘膜层72与第一绝缘膜层71之间均未间隔绝缘膜层，两个第二绝缘膜层71的材料及厚度均相同。图5所示的实施例中，主体层10包括两个第一绝缘膜层71及位于两个第一绝缘膜层71之间的一个第二绝缘膜层72，第二绝缘膜层72为位于中间的绝缘膜层，两个第一绝缘膜层71与第二绝缘膜层72之间均未间隔绝缘膜层，则两个第一绝缘膜层71的材料及厚度均相同。图6所示的实施例中，所述主体层包括一个第一绝缘膜层71、两个第二绝缘膜层72及两个第三绝缘膜层73；两个第二绝缘膜层72位于两个第三绝缘膜层73之间，第一绝缘膜层71位于两个第二绝缘膜层72之间；第一绝缘膜层71为位于中间的绝缘膜层，两个第二绝缘膜层72与第一绝缘膜层71之间均未间隔绝缘膜层，则两个第二绝缘膜层72的材料及厚度均相同；两个第三绝缘膜层72与第一绝缘膜层71 之间均间隔有一个绝缘膜层，则两个第三绝缘膜层73的材料及厚度均相同。图7所示的实施例中，所述主体层包括一个第三绝缘膜层73、两个第二绝缘膜层72及两个第一绝缘膜层71，两个第二绝缘膜层72位于两个第一绝缘膜层71之间，第三绝缘膜层73位于两个第二绝缘膜层72之间；第三绝缘膜层73为位于中间的绝缘膜层，两个第二绝缘膜层72的材料及厚度均相同，两个第一绝缘膜层71的材料及厚度均相同。
进一步地，所述主体层10中的多个导电层40在位于中间的绝缘材料层两侧对称分布。如此，可使得在对绝缘材料层进行压合过程中，各绝缘材料层及导电层两侧受到的压合作用力较平衡，防止膜层发生变形，有助于提升印刷电路板的质量。
在一个实施例中，如图3、图5至图8所示，同一所述过孔111与所述层叠方向X垂直的各截面的形状及尺寸均基本相同。
在另一实施例中，如图9所示，所述主体层10中绝缘材料层112的总数为奇数，位于中间的绝缘材料层112两侧的绝缘材料层112的数量相同；所述过孔111包括贯穿各所述绝缘材料层的子过孔113；位于中间的绝缘材料层112两侧的绝缘材料层112中，在朝向所述位于中间的绝缘材料层的方向上，所述子过孔113与所述层叠方向X垂直的截面面积逐渐减小。所述导电结构20包括多个导电部21，一个导电部21位于一个子过孔113内。在该实施例中，同一过孔111的不同子过孔113是在不同的同一步骤中形成的，同一导电结构20的不同导电部21是在不同的工艺步骤中形成的。各绝缘材料层112的子过孔113可采用激光刻蚀工艺形成。
进一步地，如图9所示，相邻两个所述绝缘材料层112之间均设有所述焊盘50，所述通孔101还包括贯穿各所述焊盘50的接触孔51，所述导电结构20与所述焊盘50直接接触。通过在相邻两个绝缘材料层之间设置焊盘50，在相邻两个子过孔113的中心发生偏移时，相邻两个导电部21可通过焊盘50电连接，可提升相邻两个导电部21电连接的可靠性。
进一步地，所述焊盘50在与所述层叠方向X垂直的平面上的正投影 的外边缘为第四边缘，与所述焊盘50相邻的两个所述子过孔113在所述平面上的正投影的边缘分别为第五边缘和第六边缘，所述第五边缘及所述第六边缘分别位于所述第四边缘的内侧。如此设置，可保证相邻两个导电部电连接的可靠性。
在一个实施例中，如图9所示，至少一个所述焊盘50与导电层40同层设置，且焊盘50位于与其同层设置的导电层40的反焊盘内。
在一个实施例中，如图3、图5至图8所示，所述主体层10的绝缘膜层包括相邻的第一绝缘膜层71和第二绝缘膜层72，所述第一绝缘膜层71的介电常数大于所述第二绝缘膜层72的介电常数，所述通孔101包括贯穿所述第一绝缘膜层71的第一过孔711及贯穿所述第二绝缘膜层72的第二过孔721，所述第一过孔711与所述层叠方向X垂直的各截面的平均面积为第一面积，所述第二过孔721与所述层叠方向X垂直的各截面的平均面积为第二面积，所述第一面积小于所述第二面积。
在一个实施例中，如图3及图5所示，所述主体层10中所述第一绝缘膜层71与所述第二绝缘膜层72交替排布。图3所示的实施例中，所述主体层10包括两个所述第一绝缘膜层71及位于两个第一绝缘膜层71之间的第二绝缘膜层72。图5所示的实施例中，所述主体层10包括两个第二绝缘膜层72及位于两个第二绝缘膜层72之间的第一绝缘膜层71。
在一个实施例中，如图6至图8所示，所述主体层10还包括第三绝缘膜层73，所述第三绝缘膜层73的材料介电常数大于所述第一绝缘膜层71的材料的介电常数；所述通孔101还包括贯穿所述第三绝缘膜层73的第三过孔731；所述第三过孔731与所述层叠方向X垂直的各截面的平均面积为第三面积，所述第三面积小于所述第一面积。
图6及图7所示的实施例中，所述第二绝缘膜层72远离所述第一绝缘膜层71的一侧设有所述第三绝缘膜层73。图6所示的实施例中，主体层包括两个第二绝缘膜层72及位于两个第二绝缘膜层72之间的第一绝缘膜层71，两个第二绝缘膜层72远离第一绝缘膜层71的一侧分别设有第三绝 缘膜层73；在朝向位于中间的绝缘膜层(也即是第一绝缘膜层71)的方向上，过孔111的所述平均面积逐渐减小。图7所示的实施例中，主体层10包括两个第一绝缘膜层71及位于两个第一绝缘膜层71之间的两个绝缘膜层72，第三绝缘膜层73位于两个第二绝缘膜层72之间；由位于中间的绝缘膜层(也即是第三绝缘膜层73)至两侧的绝缘膜层，过孔111的所述平均面积先增大后减小。图8所示的实施例中，所述第一绝缘膜层71远离所述第二绝缘膜层72的一侧设有所述第三绝缘膜层73，且主体层10包括两个第一绝缘膜层71，第三绝缘膜层73位于两个第一绝缘膜层71之间；由位于中间的绝缘膜层(也即是第三绝缘膜层73)至两侧的绝缘膜层，过孔111的所述平均面积先减小后增大。
需要说明的是，附图仅以主体层包括两种或三种不同介电常数的绝缘膜层为例进行示意，主体层可包括四种或四种以上不同介电常数的绝缘膜层，绝缘膜层在层叠方向上的排布方式可根据需要选择。
为验证本申请实施例提供的印刷电路板对信号质量的改善效果，采用仿真软件对本申请图5所示的印刷电路板的过孔进行仿真。经过模拟得到如图10及图11所示的结果。图10为过孔的阻抗与测试时间的关系曲线图，图11为回波损耗与信号频率的关系曲线图。根据图10及图11可知，绝缘膜层的过孔的最低阻抗为88.2欧姆，过孔的最高阻抗为93.3欧姆，信号的频率在0～26.56GHz范围内时，差分过孔的回波损耗的最小值为-21.6dB。
本申请图5所示的印刷电路板与第二印刷电路板和第三印刷电路板相比，可使得信号完整性明显提升。第二印刷电路板和第三印刷电路板中，第三印刷电路板的信号质量较好，根据第三印刷电路板的仿真结果可知，过孔的阻抗与目标阻抗的差值绝对值的最大值为7.2欧姆，差分过孔的回波损耗的最小值为-16.5dB；根据图5所示的印刷电路板的仿真结果可知，过孔的阻抗与目标阻抗的差值绝对值的最大值为3.8欧姆，差分过孔的回波损耗的最小值为-21.6dB。计算可得出，与第三印刷电路板相比，图5所示的印刷电路板可使得过孔的阻抗与目标阻抗的差值绝对值的最大值降低 47％，回波损耗提升31％，说明本申请实施例提供的印刷电路板可有效提升信号完整性。
本申请还提供了一种印刷电路板的制备方法。所述制备方法包括如下步骤：形成主体层；所述主体层包括多个层叠设置的绝缘膜层；相邻所述绝缘膜层的介电常数不同；所述主体层设有贯穿所述主体层的通孔，所述通孔包括贯穿各所述绝缘膜层的过孔；相邻两个所述绝缘膜层中，其中一个所述绝缘膜层的过孔与所述绝缘膜层的层叠方向垂直的各截面的平均面积为第一面积，介电常数为第一介电常数，另一个所述绝缘膜层的过孔与所述层叠方向垂直的各截面的平均面积为第二面积，介电常数为第二介电常数；所述第一介电常数大于所述第二介电常数，所述第一面积小于所述第二面积。所述主体层还包括信号线。所述制备方法还包括如下步骤：形成位于所述通孔内的导电结构。所述信号线与所述导电结构电连接。
实施例一
在该实施例中，所述印刷电路板为图3所示的印刷电路板，如图12所示，所述制备方法包括如下步骤110至步骤140。
在步骤110中，提供中间结构，所述中间结构包括第一绝缘膜层、位于所述第一绝缘膜层两侧的两个第二绝缘膜层及信号线，所述第一绝缘膜层的材料的介电常数小于所述第二绝缘膜层的介电常数。
如图13所示，所述中间结构包括三个绝缘膜层11：一个第一绝缘膜层71和两个第二绝缘膜层72，第一绝缘膜层71位于两个第二绝缘膜层72之间；第一绝缘膜层71和第二绝缘膜层72均包括多个绝缘材料层112；所述中间结构还包括多个导电层40、多个焊盘50、多个焊盘结构62及多个信号线30；每一导电层40位于相邻两个绝缘材料层112之间，导电层40设有反焊盘41、42；相邻两个绝缘膜层11之间分别设有与要形成的通孔101一一对应的焊盘50，中间结构的相对两个表面分别设有与要形成的通孔101一一对应的焊盘50；至少一个焊盘50与信号线30相连。在该步骤中焊盘50及焊盘结构62均为未设有接触孔的导电块。
在一个实施例中，所述中间结构可通过如下步骤形成：首先，将主体层的所有绝缘材料层112、导电层40、焊盘结构62及焊盘50层叠设置，部分绝缘材料层112的表面形成有导电层，部分绝缘材料层112的表面形成有焊盘50，部分绝缘材料层112的表面形成有焊盘结构62，至少一个焊盘与信号线相连且位于同一绝缘材料层的表面；随后，对层叠设置的绝缘材料层进行压合，使各绝缘材料层112粘合在一起，且相邻两个绝缘材料层112直接接触，导电层的反焊盘41、42被相邻的绝缘材料层填充。
在步骤120中，形成贯穿所述主体层的开孔，所述开孔与所述绝缘膜层的层叠方向垂直的各个截面的形状及面积均基本相同；所述开孔位于所述第一绝缘膜层的部分为第一过孔。
通过该步骤可得到如图14所示的第一中间结构。如图14所示，所述开孔103贯穿各绝缘膜层11及与其对应的焊盘50。
在一个实施例中，所述形成贯穿所述主体层的开孔，包括如下过程：采用第一钻头对所述主体层进行钻孔，形成贯穿所述主体层的开孔。采用第一钻头形成开孔，工艺简单，易于实现，可更好的控制开孔103的尺寸。采用第一钻头形成的开孔103与层叠方向X垂直的截面大致呈圆形。
在步骤130中，将所述第二绝缘膜层与所述过孔相邻的区域的材料去除，形成第二过孔，使所述第二过孔与所述层叠方向垂直的截面的面积大于所述第一过孔与所述层叠方向垂直的截面的面积。
通过该步骤可得到如图15及图16所示的第二中间结构，也即是主体层。如图15及图16所示，焊盘50形成有接触孔51。主体层还形成有回流地过孔102，回流地过孔102可在第二过孔形成之前形成，也可在第二过孔形成之后形成。
在一个实施例中，所述将所述第二绝缘膜层与所述过孔相邻的区域的材料去除，形成第二过孔的步骤，包括如下过程：采用第二钻头对所述第二绝缘膜层进行钻孔，所述第二钻头的最大外径大于所述第一钻头的最大外径，所述第二钻头在钻孔时部分位于所述开孔内。由于第二钻头的最大 外径大于第一钻头的最大外径，且第二钻头对第二绝缘膜层进行钻孔的过程中部分位于开孔内，则第二钻头可将第二绝缘膜层与开孔相邻的材料去除。
在一个实施例中，所述焊盘50的接触孔51的尺寸与相邻的第一过孔711的尺寸相同时，所述开孔位于所述焊盘50的部分为第一过孔；所述焊盘50的接触孔51的尺寸与相邻的第二过孔712的尺寸相同时，在采用第二钻头对第二绝缘膜层72进行钻孔时，第二钻头将焊盘50与过孔相邻的区域的材料去除，即形成接触孔。
在一个实施例中，所述焊盘在与绝缘膜层的层叠方向垂直的平面上的正投影的外边缘为第一边缘，与所述焊盘相邻的两个所述过孔在所述平面上的正投影的边缘分别为第二边缘和第三边缘，所述第二边缘及所述第三边缘分别位于所述第一边缘的内侧。
在步骤140中，在包括所述第一过孔和所述第二过孔的通孔内形成导电结构。
在一个实施例中，可采用电镀工艺在通孔内形成导电结构。
通过上述步骤110至步骤140制备印刷电路板的方法，只需采用一次层压工艺，有助于简化制备工艺。
在一个实施例中，所述印刷电路板的制备方法还包括：形成位于回流地过孔内的导电结构。所述形成位于回流地过孔内的导电结构的步骤可与步骤140同步进行。通过该实施例可得到如图3所示的印刷电路板。
在一个实施例中，所述中间结构还可包括位于各第二绝缘膜层远离第一绝缘膜层一侧的第三绝缘膜层，第三绝缘膜层的材料的介电常数小于第二绝缘膜层的材料的介电常数。在步骤120中形成的开孔贯穿第三绝缘膜层；在步骤130中第二钻头同时将第三绝缘膜层与开孔相邻的区域去除，得到位于第三绝缘膜层的子通孔；在步骤130之后，所述印刷电路板的制备方法还包括：采用第三钻头对第三绝缘膜层进行钻孔，将第三绝缘膜层与子通孔相邻的区域的材料去除，形成贯穿第三绝缘膜层的第三过孔；第 三钻头的最大外径大于第二钻头的最大外径。通过该实施例可得到如图6所示的印刷电路板。
实施例二
在该实施例中，所述主体层包括两个第二绝缘膜层及位于两个所述第二绝缘膜层之间的第一绝缘膜层，所述第一绝缘膜层的材料的介电常数大于所述第二绝缘膜层的介电常数；所述第一绝缘膜层与所述第二绝缘膜层中至少一个绝缘膜层的至少一个表面设有信号线。如图17所示，所述制备方法包括如下步骤210至步骤230。
在步骤210中，形成贯穿第一绝缘膜层的第一过孔。
通过该步骤可得到如图18所示的第三中间结构。如图18所示，所述第一绝缘膜层71包括多个层叠设置的绝缘材料层112；所述第三中间结构还包括导电层40、信号线30和焊盘50，导电层40位于第一绝缘膜层71的表面，第一绝缘膜层71的相对两个表面分别设有与第一过孔711一一对应焊盘50及信号线，信号线30与焊盘50相连，第一过孔711贯穿各绝缘膜层及与其对应的焊盘50。
在一个实施例中，在步骤210之前，先将导电层40、信号线30和焊盘50及绝缘材料层112层叠设置，再采用压合工艺使其粘合在一起。
在一个实施例中，可采用第一钻头对第一绝缘膜层进行钻孔形成第一过孔。
在步骤220中，在所述第一绝缘膜层的相对两个表面分别设置所述第二绝缘膜层，使所述第一绝缘膜层与所述第二绝缘膜层粘合，形成贯穿所述第二绝缘膜层且与所述第一过孔连通的第二过孔。
在一个实施例中，所述将所述第二绝缘膜层与所述第一绝缘膜层粘合后可得到如图19所示的第四中间结构。如图19所示，第二绝缘膜层72包括多个绝缘材料层112，所述第四中间结构还包括位于第二绝缘膜层72的相邻绝缘材料层之间的导电层40、位于第二绝缘膜层72表面的焊盘50、信号线30及焊盘结构。
在一个实施例中，所述将所述第二绝缘膜层与所述第一绝缘膜层粘合，包括：将所述第二绝缘膜层与所述第一绝缘膜层叠设置，进行压合，使所述第二绝缘膜层与所述第一绝缘膜层粘合。具体来说，按照膜层的层叠顺序，在第三中间结构的相对两个表面分别设置第二绝缘膜层的绝缘材料层、导电层和焊盘，再进行压合。
在所述第二绝缘膜层形成第二过孔及形成回流地过孔后，可得到如图15及图16所示的第二中间结构。
在步骤230中，在包括所述第一过孔和所述第二过孔的通孔内形成导电结构。
在一个实施例中，可采用电镀工艺形成导电结构。
通过该步骤可得到如图3所示的印刷电路板。
在一个实施例中，所述印刷电路板的制备方法还可包括如下步骤：形成贯穿主体层的回流地过孔；形成位于回流地过孔内的导电结构。形成回流地过孔与形成导电结构的步骤的相关描述参见实施例一，在此不再进行赘述。
在一个实施例中，在步骤230之前，所述印刷电路板的制备方法还可包括如下步骤：在两个所述第二绝缘膜层远离第一绝缘膜层的一侧分别设置第三绝缘膜层，进行压合，使所述第三绝缘膜层与所述第二绝缘膜层粘合；形成贯穿所述第三绝缘膜层的第三过孔。在该实施例中，所述通孔还包括第三过孔。通过该实施例可得到如图6所示的印刷电路板。
实施例三
本实施例仅描述与实施例二不同之处，相同之处不再进行赘述。
在该实施例中，所述主体层包括两个第一绝缘膜层及位于两个所述第一绝缘膜层之间的第二绝缘膜层，所述第一绝缘膜层的材料的介电常数大于所述第二绝缘膜层的介电常数。如图20所示，所述制备方法包括如下步骤310至步骤330。下面仅介绍与上一实施例不同之处，相同之处不再进行赘述。
在步骤310中，形成贯穿第二绝缘膜层的第二过孔。
通过该步骤可得到如图21所示的第五中间结构。
在步骤320中，在所述第二绝缘膜层的相对两个表面分别设置所述第一绝缘膜层，使所述第一绝缘膜层与所述第二绝缘膜层粘合，形成贯穿所述第一绝缘膜层且与所述第二过孔连通的第一过孔。
通过该步骤可得到如图22及如图23所示的第六中间结构。
在步骤330中，在包括所述第一过孔和所述第二过孔的通孔内形成导电结构。
通过该实施例可得到如图5所示的印刷电路板。
图7及图8所示的印刷电路板的制备过程与实施例三类似，不再进行赘述。
实施例四
在该实施例中，所述绝缘膜层包括多个层叠设置的绝缘材料层，至少一个所述绝缘材料层的至少一侧设有信号线；所述过孔包括贯穿绝缘材料层的子过孔；所述导电结构包括位于各所述子过孔内的导电部。所述制备方法包括如下过程：
首先，在一个绝缘材料层形成子过孔，并形成位于子过孔内的导电部；
随后，重复执行以下步骤，直至形成所述主体层及所述导电结构：
在上一步骤得到的结构的相对两个表面分别设置一个未设有子过孔的绝缘材料层，层叠设置的绝缘材料层粘合；在未设子过孔的绝缘材料层上形成子过孔，并形成位于子过孔内的导电部。
在一个实施中，可采用电镀工艺形成导电部。首先在上一步骤中得到的结构的两侧分别设置绝缘材料层，再形成开孔及位于开孔内的导电部，可使得相邻两个导电部接触较好，提升相邻导电部之间的电连接可靠性。
在一个实施例中，所述主体层中绝缘材料层的总数为奇数，位于中间的绝缘材料层两侧的绝缘材料层的数量相同；与所述中间的绝缘材料层间隔的绝缘材料层数量相同的两个绝缘材料层的材料及厚度均相同。最先形 成子过孔的绝缘材料层为主体层中位于中间的绝缘材料层。如此，可使得在每一次压合工艺中，各绝缘材料层的两侧受力平衡，可防止绝缘材料层在压合过程中发生变形。
在一个实施例中，所述在上一步骤得到的结构的相对两个表面分别设置一个未设有子过孔的绝缘材料层，并使层叠设置的绝缘材料层粘合的步骤，包括如下过程：在上一步骤得到的结构的两侧分别设置一个绝缘材料层，对层叠设置的绝缘材料层进行压合，使层叠设置的绝缘材料层粘合。具体来说，按照膜层的层叠顺序，在上一步骤得到的结构的相对两个表面分别设置绝缘材料层、焊盘、信号线及导电层，并对层叠设置的膜层进行压合。
在一个实施例中，所述主体层还包括多个焊盘，相邻两个所述绝缘材料层之间设有所述焊盘，所述通孔包括贯穿所述焊盘的接触孔，所述导电部部分位于所述接触孔内。
在一个实施例中，所述主体层中绝缘材料层的总数为奇数，位于中间的绝缘材料层两侧的绝缘材料层的数量相同；与所述位于中间的绝缘材料层间隔的绝缘材料层数量相同的两个绝缘材料层的材料及厚度均相同。
在一个实施例中，位于中间的绝缘材料层两侧的绝缘材料层中，在朝向所述位于中间的绝缘材料层的方向上，所述绝缘材料层的子过孔与所述层叠方向垂直的截面面积逐渐减小。
下面以图9所示的印刷电路板为例，介绍印刷电路板的形成过程：
首先，在一个绝缘材料层形成子过孔，并形成位于过孔内的导电结构。
在该步骤中，在绝缘材料层上形成子过孔之前，可在绝缘材料层的相对两个表面分别设置焊盘及导电层，位于绝缘材料层同一表面焊盘及导电层可同时形成，且焊盘位于导电层的反焊盘内。通过该步骤可得到如图24所示的第七中间结构。如图24所示，所述绝缘材料层112的相对两个表面分别设有焊盘50和导电层40；焊盘50形成有接触孔51，接触孔51与子过孔113连通；导电层40设有反焊盘41，与导电层40位于绝缘材料层同 一表面的焊盘50位于导电层40的反焊盘41内；导电部21穿过反焊盘41，且导电部21部分位于接触孔51内。
在一个实施例中，所述焊盘50的接触孔51与子过孔113采用激光刻蚀工艺形成。在由所述绝缘材料层112的一个表面至另一个表面的方向上，所述导电部21与所述表面平行的截面的面积逐渐增大。
随后，在上一步骤得到的中间结构也即是第七中间结构的相对两个表面分别设置绝缘材料层，并使未设子过孔的绝缘材料层与设有所述子过孔的绝缘材料层粘合；在未设子过孔的绝缘材料层上形成子过孔，并形成位于子过孔内的导电部。
在该步骤中，使未设子过孔的绝缘材料层与设有所述子过孔的绝缘材料层粘合后可得到如图25所示的第八中间结构。如图25所示，位于两侧的绝缘材料层112的表面分别设有焊盘50和导电层40。
在未设子过孔的绝缘材料层上形成子过孔，并形成位于子过孔内的导电部可得到如图26所示的第九中间结构。如图26所示，位于中间的绝缘材料层两侧的绝缘材料层中，在朝向位于中间的绝缘材料层的方向上，子过孔113与层叠方向垂直的截面的面积逐渐减小。
随后，在上一步骤中得到的结构两侧分别设置绝缘材料层，并对层叠设置的绝缘材料层进行压合，在未设子过孔的绝缘材料层上形成子过孔，并形成位于子过孔内的导电部。重复该步骤，直至得到印刷电路板。
本申请实施例提供的印刷电路板的方法的实施例与印刷电路板的实施例属于同一发明构思，相关细节及有益效果的描述可互相参见。
需要指出的是，在附图中，为了图示的清晰可能夸大了层和区域的尺寸。而且可以理解，当元件或层被称为在另一元件或层“上”时，它可以直接在其他元件上，或者可以存在中间的层。另外，可以理解，当元件或层被称为在另一元件或层“下”时，它可以直接在其他元件下，或者可以存在一个以上的中间的层或元件。另外，还可以理解，当层或元件被称为在两层或两个元件“之间”时，它可以为两层或两个元件之间唯一的层，或还可 以存在一个以上的中间层或元件。通篇相似的参考标记指示相似的元件。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本申请的其它实施方案。本申请旨在涵盖本申请的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本申请的一般性原理并包括本申请未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本申请的真正范围和精神由下面的权利要求指出。
应当理解的是，本申请并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本申请的范围仅由所附的权利要求来限制。

Claims (24)

  1. 一种印刷电路板，其特征在于，所述印刷电路板包括：
    主体层，包括多个层叠设置的绝缘膜层，相邻所述绝缘膜层的介电常数不同；所述主体层设有贯穿所述主体层的通孔，所述通孔包括贯穿各所述绝缘膜层的过孔；相邻两个所述绝缘膜层中，其中一个所述绝缘膜层的过孔与所述绝缘膜层的层叠方向垂直的各截面的平均面积为第一面积，介电常数为第一介电常数，另一个所述绝缘膜层的过孔与所述层叠方向垂直的各截面的平均面积为第二面积，介电常数为第二介电常数；所述第一介电常数大于所述第二介电常数，所述第一面积小于所述第二面积。
  2. 根据权利要求1所述的印刷电路板，其特征在于，同一所述通孔的相邻两个过孔中，其中一个所述过孔在与所述层叠方向垂直的平面上的正投影为第一投影，另一所述过孔在所述平面上的正投影为第二投影，所述第一投影落在所述第二投影内。
  3. 根据权利要求1所述的印刷电路板，其特征在于，所述主体层还包括多个焊盘，相邻两个所述绝缘膜层之间设有所述焊盘，所述通孔还包括贯穿所述焊盘的接触孔。
  4. 根据权利要求3所述的印刷电路板，其特征在于，所述焊盘在与所述层叠方向垂直的平面上的正投影的外边缘为第一边缘，与所述焊盘相邻的两个所述过孔在所述平面上的正投影的边缘分别为第二边缘和第三边缘，所述第二边缘及所述第三边缘分别位于所述第一边缘的内侧。
  5. 根据权利要求1所述的印刷电路板，其特征在于，所述主体层中的至少两个所述绝缘膜层的材料相同，且材料相同的绝缘膜层的过孔与所述层叠方向垂直的各截面的平均面积基本相同。
  6. 根据权利要求1所述的印刷电路板，其特征在于，所述绝缘膜层的总数为奇数，位于中间的绝缘膜层两侧的绝缘膜层的数量相同，与所述位于中间的绝缘膜层间隔的绝缘膜层数量相同的两个绝缘膜层的材料及厚度 均相同。
  7. 根据权利要求1所述的印刷电路板，其特征在于，同一所述过孔与所述层叠方向垂直的各截面的形状及尺寸均基本相同。
  8. 根据权利要求1所述的印刷电路板，其特征在于，所述绝缘膜层包括多个层叠设置的绝缘材料层，所述主体层中绝缘材料层的总数为奇数，位于中间的绝缘材料层两侧的绝缘材料层的数量相同；所述过孔包括贯穿各所述绝缘材料层的子过孔；位于中间的绝缘材料层两侧的绝缘材料层中，在朝向所述位于中间的绝缘材料层的方向上，所述绝缘材料层的子过孔与所述层叠方向垂直的截面面积逐渐减小。
  9. 根据权利要求8所述的印刷电路板，其特征在于，所述主体层还包括多个焊盘，相邻两个所述绝缘材料层之间均设有所述焊盘，所述通孔还包括贯穿所述焊盘的接触孔。
  10. 根据权利要求9所述的印刷电路板，其特征在于，所述焊盘在与所述层叠方向垂直的平面上的正投影的外边缘为第四边缘，与所述焊盘相邻的两个所述子过孔在所述平面上的正投影的边缘分别为第五边缘和第六边缘，所述第五边缘及所述第六边缘分别位于所述第四边缘的内侧。
  11. 根据权利要求1所述的印刷电路板，其特征在于，所述印刷电路板还包括信号线及位于所述通孔内的导电结构，所述信号线与所述导电结构电连接；所述信号线包括差分信号线与单端信号线中的至少一种。
  12. 根据权利要求1所述的印刷电路板，其特征在于，所述主体层的绝缘膜层包括相邻的第一绝缘膜层和第二绝缘膜层，所述第一绝缘膜层的介电常数大于所述第二绝缘膜层的介电常数，所述通孔包括贯穿所述第一绝缘膜层的第一过孔及贯穿所述第二绝缘膜层的第二过孔，所述第一过孔与所述层叠方向垂直的各截面的平均面积为第一面积，所述第二过孔与所述层叠方向垂直的各截面的平均面积为第二面积，所述第一面积小于所述第二面积；
    所述主体层中所述第一绝缘膜层与所述第二绝缘膜层交替排布；或者，
    所述主体层还包括第三绝缘膜层，所述第三绝缘膜层的材料介电常数小于所述第二绝缘膜层的材料的介电常数；所述通孔还包括贯穿所述第三绝缘膜层的第三过孔；所述第三过孔与所述层叠方向垂直的各截面的平均面积为第三面积，所述第三面积大于所述第二面积；所述第二绝缘膜层远离所述第一绝缘膜层的一侧设有所述第三绝缘膜层，或所述第一绝缘膜层远离所述第二绝缘膜层的一侧设有所述第三绝缘膜层。
  13. 一种印刷电路板的制备方法，其特征在于，所述制备方法包括：
    形成主体层；所述主体层包括多个层叠设置的绝缘膜层；相邻所述绝缘膜层的介电常数不同；所述主体层设有贯穿所述主体层的通孔，所述通孔包括贯穿各所述绝缘膜层的过孔；相邻两个所述绝缘膜层中，其中一个所述绝缘膜层的过孔与所述绝缘膜层的层叠方向垂直的各截面的平均面积为第一面积，介电常数为第一介电常数，另一个所述绝缘膜层的过孔与所述层叠方向垂直的各截面的平均面积为第二面积，介电常数为第二介电常数；所述第一介电常数大于所述第二介电常数，所述第一面积小于所述第二面积。
  14. 根据权利要求13所述的印刷电路板的制备方法，其特征在于，所述形成主体层，包括：
    提供中间结构，所述中间结构包括第一绝缘膜层及位于所述第一绝缘膜层两侧的两个第二绝缘膜层，所述第一绝缘膜层的材料的介电常数小于所述第二绝缘膜层的介电常数；
    形成贯穿所述主体层的开孔，所述开孔与所述绝缘膜层的层叠方向垂直的各个截面的形状及面积均基本相同；所述开孔位于所述第一绝缘膜层的部分为第一过孔；
    将所述第二绝缘膜层与所述过孔相邻的区域的材料去除，形成第二过孔，使所述第二过孔与所述层叠方向垂直的截面的面积大于所述第一过孔与所述层叠方向垂直的截面的面积。
  15. 根据权利要求14所述的印刷电路板的制备方法，其特征在于，所 述形成贯穿所述主体层的开孔，包括：采用第一钻头对所述主体层进行钻孔，形成贯穿所述主体层的开孔；
    所述将所述第二绝缘膜层与所述过孔相邻的区域的材料去除，包括：采用第二钻头对所述第二绝缘膜层进行钻孔，所述第二钻头的最大外径大于所述第一钻头的最大外径，所述第二钻头在钻孔时部分位于所述开孔内。
  16. 根据权利要求13所述的印刷电路板的制备方法，其特征在于，所述主体层包括两个第二绝缘膜层及位于两个所述第二绝缘膜层之间的第一绝缘膜层，所述第一绝缘膜层的材料的介电常数大于所述第二绝缘膜层的介电常数；所述形成主体层，包括：
    形成贯穿第一绝缘膜层的第一过孔；
    在所述第一绝缘膜层的相对两个表面分别设置所述第二绝缘膜层，使所述第一绝缘膜层与所述第二绝缘膜层粘合，形成贯穿所述第二绝缘膜层且与所述第一过孔连通的第二过孔；
    或者，
    所述主体层包括两个第一绝缘膜层及位于两个所述第一绝缘膜层之间的第二绝缘膜层，所述第一绝缘膜层的材料的介电常数大于所述第二绝缘膜层的介电常数；所述形成主体层，包括：
    形成贯穿第二绝缘膜层的第二过孔；
    在所述第二绝缘膜层的相对两个表面分别设置所述第一绝缘膜层，使所述第一绝缘膜层与所述第二绝缘膜层粘合，形成贯穿所述第一绝缘膜层且与所述第二过孔连通的第一过孔。
  17. 根据权利要求16所述的印刷电路板的制备方法，其特征在于，所述使所述第一绝缘膜层与所述第二绝缘膜层粘合，包括：
    对层叠设置的所述第二绝缘膜层与所述第一绝缘膜层叠设置进行压合，使所述第二绝缘膜层与所述第一绝缘膜层粘合。
  18. 根据权利要求14至17任一项所述的印刷电路板的制备方法，其特征在于，所述主体层还包括多个焊盘，相邻两个所述绝缘膜层之间设有 所述焊盘，所述通孔包括贯穿所述焊盘的接触孔。
  19. 根据权利要求18所述的印刷电路板的制备方法，其特征在于，所述焊盘在与所述层叠方向垂直的平面上的正投影的外边缘为第一边缘，与所述焊盘相邻的两个所述过孔在所述平面上的正投影的边缘分别为第二边缘和第三边缘，所述第二边缘及所述第三边缘分别位于所述第一边缘的内侧。
  20. 根据权利要求13所述的印刷电路板的制备方法，其特征在于，所述绝缘膜层包括多个层叠设置的绝缘材料层；所述过孔包括贯穿绝缘材料层的子过孔；所述印刷电路板还包括位于所述通孔内的导电结构，所述导电结构包括位于各所述子过孔内的导电部；形成所述主体层及所述导电结构的步骤包括：
    在一个绝缘材料层形成子过孔，并形成位于子过孔内的导电部；
    重复执行以下步骤，直至形成所述主体层及所述导电结构：
    在上一步骤得到的结构的相对两个表面分别设置未设有子过孔的绝缘材料层，并使层叠设置的绝缘材料层粘合；在未设子过孔的绝缘材料层上形成子过孔，并形成位于子过孔内的导电部。
  21. 根据权利要求20所述的印刷电路板的制备方法，其特征在于，所述主体层还包括多个焊盘，相邻两个所述绝缘材料层之间设有所述焊盘，所述通孔包括贯穿所述焊盘的接触孔，所述导电部部分位于所述接触孔内。
  22. 根据权利要求20所述的印刷电路板的制备方法，其特征在于，所述子过孔采用激光刻蚀工艺形成。
  23. 根据权利要求20所述的印刷电路板的制备方法，其特征在于，所述在上一步骤得到的结构的相对两个表面分别设置未设有子过孔的绝缘材料层，并使层叠设置的绝缘材料层粘合，包括：
    在上一步骤得到的结构的两侧分别设置绝缘材料层，对层叠设置的绝缘材料层进行压合，使层叠设置的绝缘材料层粘合。
  24. 根据权利要求23所述的印刷电路板的制备方法，其特征在于，所 述主体层中绝缘材料层的总数为奇数，位于中间的绝缘材料层两侧的绝缘材料层的数量相同；与所述位于中间的绝缘材料层间隔的绝缘材料层数量相同的两个绝缘材料层的材料及厚度均相同。
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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020046880A1 (en) * 1997-06-03 2002-04-25 Kabushiki Kaisha Toshiba Hybrid wiring board, semiconductor apparatus, flexible substrate, and fabrication method of hybrid wiring board
CN101101899A (zh) * 2006-06-01 2008-01-09 富士通株式会社 积层板及其制造方法、具有该积层板的电子元件和装置
WO2020263018A1 (ko) * 2019-06-28 2020-12-30 주식회사 아모센스 전자 소자 어셈블리 패키지, 전자 소자 모듈용 회로 기판 및 이의 제조 방법
CN115250568A (zh) * 2021-04-26 2022-10-28 三星电机株式会社 印刷电路板

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020046880A1 (en) * 1997-06-03 2002-04-25 Kabushiki Kaisha Toshiba Hybrid wiring board, semiconductor apparatus, flexible substrate, and fabrication method of hybrid wiring board
CN101101899A (zh) * 2006-06-01 2008-01-09 富士通株式会社 积层板及其制造方法、具有该积层板的电子元件和装置
WO2020263018A1 (ko) * 2019-06-28 2020-12-30 주식회사 아모센스 전자 소자 어셈블리 패키지, 전자 소자 모듈용 회로 기판 및 이의 제조 방법
CN115250568A (zh) * 2021-04-26 2022-10-28 三星电机株式会社 印刷电路板

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