Classifications

• • H—ELECTRICITY
  • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
  • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
  • H02P25/00—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details
  • H02P25/02—Arrangements or methods for the control of AC motors characterised by the kind of AC motor or by structural details characterised by the kind of motor
  • H02P25/06—Linear motors
  • H02P25/064—Linear motors of the synchronous type

Definitions

• This disclosure relates to a linear motor drive device.
• the inverter's switching operation is a source of electrical noise.
• stray capacitance inevitably arises between the motor's stator winding and its metal casing, creating a potential difference between the casing and the ground, generating common-mode noise.
• common-mode noise propagates to the system power supply via power cables connected to the casing. This conductive noise can have adverse effects on other electronic devices sharing the same power source.
• One known method for suppressing this conductive noise is to control the phase of the carrier signal in a motor drive device that includes multiple motors, such as multi-axis motors, and multiple inverters, thereby canceling out the noise generated by inverter operation.
• the device in Patent Document 1 in a configuration including N motors and N inverters, generates N vector quantities based on the magnitude of the noise current generated by each motor and the phase angle of the carrier signal used to control the drive of the inverter corresponding to each motor, and determines the phase angle of each carrier signal so that the sum of these N vector quantities is zero.
• an object of the present disclosure is to provide a linear motor drive device that can suppress noise.
• the linear motor drive device disclosed herein comprises a plurality of stator windings arranged in series and at least one housing for accommodating the plurality of stator windings.
• the plurality of stator windings includes a first group of stator windings and a second group of stator windings, with two adjacent stator windings belonging to the same group being electrically connected and two adjacent stator windings belonging to different groups being electrically insulated.
• the linear motor drive device further comprises a power conversion circuit having a first group of inverters connected to one end of the stator windings of the first group and a second group of inverters connected to one end of the stator windings of the second group; and a control circuit that generates a first carrier signal having a predetermined period for PWM control of the plurality of inverters of the first group and generates a second carrier signal having a period for PWM control of the plurality of inverters of the second group.
• the difference in phase between the first carrier signal and the second carrier signal is half the period or an odd multiple of half the period.
• noise can be suppressed.
• FIG. 6 is a diagram showing a linear motor drive device 600 and a portion of a linear motor driven by the linear motor drive device 600.
• FIG. 2 is a diagram showing a part of a drive unit 200 and a stator winding unit 10.
• FIG. FIG. 2 is a diagram showing the internal configuration of a drive unit 200.
• FIG. 10 is a diagram for explaining the effect of the first embodiment.
• FIG. 10 is a diagram showing the configuration of a phase control circuit 8A according to a second embodiment.
• 3 is a diagram showing an example of a first carrier signal Cwa and a second carrier signal Cwb;
• FIG. 10 is a diagram showing another example of the first carrier signal Cwa and the second carrier signal Cwb.
• FIG. 10 is a diagram showing the configuration of a phase control circuit 8B according to a third embodiment.
• FIG. 10 is a diagram illustrating a configuration of a phase control circuit 8C according to a modification of the third embodiment.
• FIG. 1 is a diagram showing a linear motor drive device 600 and a portion of a linear motor driven by the linear motor drive device 600.
• the linear motor drive device 600 comprises a host device 300, multiple drive units 200, and multiple stator winding units 10.
• the stator winding units 10 comprise multiple stator windings.
• the mover 400 is equipped with a permanent magnet.
• the mover 400 moves on the guide rail 500 due to the electromagnetic force generated by the stator winding.
• the movement state of multiple movers 400 can be managed by the host device 300. This allows the trajectories of multiple movers 400 to be freely controlled.
• Figure 2 shows a portion of the drive unit 200 and the stator winding unit 10.
• the drive unit 200 includes a power conversion circuit 2.
• the stator winding unit 10 comprises a first group of stator windings G1a and a second group of stator windings G1b.
• the first group of stator windings G1a includes stator windings 1a(1) to 1a(M).
• the second group of stator windings G1b includes stator windings 1b(1) to 1b(L).
• M + L N.
• stator windings 1a(1) to 1a(M) will be collectively referred to as stator winding 1a
• stator windings 1b(1) to 1b(L) will be collectively referred to as stator winding 1b
• stator windings 1a(1) to 1a(M) and 1b(1) to 1b(L) will be collectively referred to as stator winding 1.
• Stator windings 1 belonging to the same group are electrically and magnetically coupled to adjacent stator windings 1.
• Magnetic coupling refers to coupling due to mutual inductance between the windings.
• Electrical connection refers to a state in which the windings themselves are physically connected.
• Stator windings in different groups are electrically insulated, but magnetic coupling is acceptable.
• the second end (right end) of stator winding 1a(M) and the first end (left end) of stator winding 1b(1) are electrically insulated, but magnetic coupling is permitted.
• the stator winding 1 is housed in a housing 100.
• the stator winding 1 does not need to be completely covered by the housing 100; it may have a partially open structure.
• the power conversion circuit 2 includes a first group of inverters G4a and a second group of inverters G4b.
• the first group of inverters G4a includes inverters IVa(1) to IVa(M+1).
• the second group of inverters G4b includes inverters IVb(1) to IVb(L+1).
• inverters IVa(1) to IVa(M+1) will be collectively referred to as inverter IVa
• inverters IVb(1) to IVb(L+1) will be collectively referred to as inverter IVb
• inverters IVa(1) to IVa(M+1) and inverters IVb(1) to IVb(L+1) will be collectively referred to as inverter IV.
• switching elements 4Ua(1) to 4Ua(M+1) and 4La(1) to 4La(M+1) may be collectively referred to as the first group of switching elements 4a.
• switching elements 4Ub(1) to 4Ub(L+1) and 4Lb(1) to 4Lb(L+1) may be collectively referred to as the second group of switching elements 4b.
• switching elements 4Ua(1) to 4Ua(M+1), 4La(1) to 4La(M+1), 4Ub(1) to 4Ub(L+1), and 4Lb(1) to 4Lb(L+1) may be collectively referred to as switching element 4.
• An IGBT Insulated Gate Bipolar Transistor
• MOSFET Metal Oxide Semiconductor Field Effect Transistor
• the power conversion circuit 2 is not housed in the housing 100 that houses the stator winding 1, but is mounted on a circuit board inside the drive unit 200. Electromagnetic force is generated when the drive current supplied from the power conversion circuit 2 flows through the stator winding 1.
• FIG. 3 is a diagram showing the internal configuration of the drive unit 200.
• the drive unit 200 includes a control circuit 220 and a power conversion circuit 2.
• the control circuit 220 includes a motion control circuit 9, a phase control circuit 8, a first carrier signal generation circuit 7a, a second carrier signal generation circuit 7b, a first PWM (Pulse Width Modulation) signal generation circuit 5a, and a second PWM signal generation circuit 5b.
• PWM Pulse Width Modulation
• the first PWM signal generation circuit 5a generates a PWM signal for the first group of switching elements 4a.
• the first PWM signal generation circuit 5a has (M+1) comparators 6a(1) to 6a(M+1).
• the second PWM signal generation circuit 5b generates a PWM signal for the second group of switching elements 4b.
• the second PWM signal generation circuit 5b includes (L+1) comparators 6b(1) to 6b(L+1).
• the first carrier signal generation circuit 7a supplies a first carrier signal Cwa to the first PWM signal generation circuit 5a.
• the second carrier signal generation circuit 7b supplies a second carrier signal Cwb to the second PWM signal generation circuit 5b.
• the first carrier signal Cwa and the second carrier signal Cwb are periodic electrical signals having a predetermined period (T), and may be triangular waves, for example.
• the first carrier signal generation circuit 7a begins outputting the first carrier signal Cwa upon receiving a first timing signal Tma from the phase control circuit 8.
• the second carrier signal generation circuit 7b begins outputting the second carrier signal Cwb upon receiving a second timing signal Tmb from the phase control circuit 8.
• the phase control circuit 8 outputs a first timing signal Tma and a second timing signal Tmb to control the phase of the first carrier signal Cwa and the phase of the second carrier signal Cwb.
• the phase control circuit 8 adjusts the difference between the phase of the first carrier signal Cwa output from the first carrier signal generation circuit 7a and the phase of the second carrier signal Cwb output from the second carrier signal generation circuit 7b so that it is half (T/2) the period (T) of the first carrier signal Cwa and the second carrier signal Cwb, or an odd multiple (k x (T/2)) of half the period (T), where k is an odd number (including negative numbers).
• the motion control circuit 9 performs calculations based on commands from the higher-level device 300 and calculates the drive currents for the stator windings 1a(1) to 1a(M) and 1b(1) to 1b(L). Based on the calculation results, the motion control circuit 9 outputs a command signal Cda(i) to the comparator 6a(i) and a command signal Cdb(j) to the comparator 6b(j).
• i 1 to M+1
• j 1 to L+1.
• the motion control circuit 9 is included inside the drive unit 200 and is assumed to be housed in the same housing as the power conversion circuit 2, but it does not necessarily have to be housed in the same housing.
• Noise sources 3000a and 3000b which are electrical noises generated mainly due to the switching operation of the inverter, flow into the housing 100 via the stray capacitances 2000a and 2000b, and reach the system power supply via the earth wire 1000 or the shield of the power cable connected to the housing 100. This noise can adversely affect other electronic devices that share the same power source, and it is therefore necessary to keep the amount of propagation within allowable values defined by international standards, etc.
• phase of the control signal for the inverter that supplies power to each stator winding is inverted, which in turn inverts the phase of the noise current generated by the inverter's switching operation (4000a and 4000b in Figure 4), making it possible for the noises to cancel each other out.
• the first group of stator windings G1a and the second group of stator windings G1b are always driven by inverter operation with opposite phases, allowing noise to be canceled out by each other.
• the multiple stator windings are divided into two groups for the following reason.
• a phenomenon occurs in which unnecessary current that is not involved in motor motion control flows. This phenomenon occurs when two pairs of adjacent switching elements operate in opposite phases, and is a problem specific to when adjacent stators are electrically coupled. There is a concern that this unnecessary current may, for example, have a negative impact on power conversion efficiency or controllability, or increase noise.
• stator windings within the housing are divided into two groups, each driven by inverter operation in opposite phases.
• stator windings within the same group are driven by inverter operation in the same phase, so the problems described above do not occur.
• stator windings in different groups are driven by inverter operation in opposite phases, the noise currents flowing from the stator windings of the first and second groups are also in opposite phases. Therefore, the net noise currents within one drive unit 200 are canceled out, reducing the noise currents flowing to the outside.
• the phase control circuit 8 may have any specific circuit configuration as long as it has the function of adjusting the phase difference between the carrier signals Cwa and Cwb output from the two carrier signal generation circuits 7 a and 7 b so that the phase difference is half the period (T) of the carrier signals Cwa and Cwb or an odd multiple thereof.
• T the period of the carrier signals
• FIG. 5 is a diagram showing the configuration of a phase control circuit 8A according to the second embodiment.
• the phase control circuit 8A includes a clock circuit 20, a first counter circuit 11-1, and a second counter circuit 11-2.
• the clock circuit 20 does not need to be dedicated to use only within the phase control circuit 8A; it may be a clock circuit used for other circuit functions as needed.
• the clock circuit 20 generates a synchronization signal CLK to synchronize the operation of the first counter circuit 11-1 with the operation of the second counter circuit 11-2, and supplies this signal to the first counter circuit 11-1 and the second counter circuit 11-2.
• the first counter circuit 11-1 and the second counter circuit 11-2 perform counting in synchronization with the synchronization signal CLK output from the clock circuit 20.
• the first counter circuit 11-1 detects a rising edge of the synchronization signal CLK, it increments the first counter value CT1 by 1.
• the second counter circuit 11-2 detects a rising edge of the synchronization signal CLK, it increments the second counter value CT2 by 1.
• the first counter value CT1 reaches a preset first count value TH1
• the first counter circuit 11-1 outputs a first timing signal Tma to the first carrier signal generation circuit 7a.
• the second counter value CT2 reaches a preset second count value TH2
• the second counter circuit 11-2 outputs a second timing signal Tmb to the second carrier signal generation circuit 7b.
• the synchronization signal CLK can be of any format as long as it is a periodic electrical signal, but a rectangular wave with a fixed period is preferable.
• the first timing signal Tma and the second timing signal Tmb can also be of any format as long as they are electrical signals, but can be digital signals such as High (1) or Low (0), for example.
• the first counter circuit 11-1 and the second counter circuit 11-2 may be configured as discrete circuits using integrated circuits such as digital counter ICs (Integrated Circuits), or may be configured on a programmable device such as an FPGA (Field Programmable Gate Array).
• integrated circuits such as digital counter ICs (Integrated Circuits)
• FPGA Field Programmable Gate Array
• the first count value TH1 and the second count value TH2 are set so that the time difference between the timing when the first counter circuit 11-1 outputs the first timing signal Tma and the timing when the second counter circuit 11-2 outputs the second timing signal Tmb is half the period (T) of the first carrier signal Cwa and the second carrier signal Cwb, or an odd multiple (including negative odd numbers) of half the period (T).
• This configuration allows different groups of stator windings to be driven by opposite-phase inverter operation.
• Figure 6 shows an example of a first carrier signal Cwa and a second carrier signal Cwb.
• the time difference between the timing when the first counter circuit 11-1 outputs the first timing signal Tma and the timing when the second counter circuit 11-2 outputs the second timing signal Tmb is T/2. This allows the phase difference between the first carrier signal Cwa and the second carrier signal Cwb to be T/2.
• Figure 7 shows another example of the first carrier signal Cwa and the second carrier signal Cwb.
• the time difference between the timing when the first counter circuit 11-1 outputs the first timing signal Tma and the timing when the second counter circuit 11-2 outputs the second timing signal Tmb is 3T/2. This allows the phase difference between the first carrier signal Cwa and the second carrier signal Cwb to be 3T/2.
• a phase control circuit can be easily configured. It is easy to implement, as it is sufficient to provide two counter circuits and one clock circuit within one drive unit.
• FIG. 8 is a diagram showing the configuration of a phase control circuit 8B according to the third embodiment.
• the phase control circuit 8B includes a synchronization signal generating circuit 13 and a delay circuit 12.
• the synchronization signal generation circuit 13 generates a first timing signal Tma.
• the first timing signal Tma may take various forms as an electrical signal, for example, a digital signal that transitions from High (1) to Low (0) at a certain point in time.
• the synchronization signal generation circuit 13 outputs the first timing signal Tma to the first carrier signal generation circuit 7a as is, and also supplies it to the delay circuit 12.
• the delay circuit 12 delays the first timing signal Tma output from the synchronization signal generation circuit 13 by half the period (T) of the first carrier signal Cwa and the second carrier signal Cwb or an odd multiple of half the period (T) to generate the second timing signal Tmb, which it outputs to the second carrier signal generation circuit 7b.
• the specific configuration of the delay circuit 12 is not important.
• a phase control circuit can be easily configured. It is easy to implement, as it is sufficient to provide one synchronization signal generation circuit and one delay circuit within one drive unit.
• FIG. 9 is a diagram showing the configuration of a phase control circuit 8C according to a modification of the third embodiment.
• the phase control circuit 8C includes a synchronization signal generating circuit 13C and a delay circuit 12C.
• the synchronization signal generating circuit 13C generates a second timing signal Tmb, which is output to the second carrier signal generating circuit 7b as is, and also supplied to the delay circuit 12C.
• the delay circuit 12C delays the second timing signal Tmm output from the synchronization signal generation circuit 13C by half the period (T) of the first carrier signal Cwa and the second carrier signal Cwb or an odd multiple of half the period (T) to generate the first timing signal Tma, which is output to the first carrier signal generation circuit 7a.
• different groups of stator windings can also be driven with inverter operation in opposite phases.

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• Power Engineering (AREA)
• Control Of Linear Motors (AREA)
• Control Of Ac Motors In General (AREA)

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Citations (3)

• 2024
  • 2024-02-07 JP JP2024535385A patent/JP7570568B1/ja active Active
  • 2024-02-07 WO PCT/JP2024/004101 patent/WO2025169342A1/ja active Pending

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