WO2025112896A1 - 阵列基板、显示面板及显示装置 - Google Patents

阵列基板、显示面板及显示装置 Download PDF

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Publication number
WO2025112896A1
WO2025112896A1 PCT/CN2024/122583 CN2024122583W WO2025112896A1 WO 2025112896 A1 WO2025112896 A1 WO 2025112896A1 CN 2024122583 W CN2024122583 W CN 2024122583W WO 2025112896 A1 WO2025112896 A1 WO 2025112896A1
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Prior art keywords
conductive
along
array substrate
fan
conductive patterns
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PCT/CN2024/122583
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English (en)
French (fr)
Inventor
王梦奇
张跳梅
于子阳
蒋志亮
胡明
邱海军
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Publication of WO2025112896A1 publication Critical patent/WO2025112896A1/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/60—Arrangements for protection of devices protecting against electrostatic charges or discharges, e.g. Faraday shields

Definitions

  • the present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel and a display device.
  • OLED display panels have gradually become one of the mainstream products in the display field due to their excellent properties such as self-luminescence, no need for backlight, high contrast, thin thickness, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, simple structure and process. OLED display panels can be widely used in terminal products such as smart phones, tablets, TVs and wearable devices (such as watches).
  • the OLED display panel includes an array substrate and a light-emitting device disposed on the array substrate.
  • the array substrate includes a plurality of signal lines, which are used to transmit corresponding control signals to the array substrate to drive the display panel to display images. How to avoid static electricity accumulation on the signal line is a technical problem that needs to be solved in the display panel.
  • an array substrate includes a substrate, a plurality of pixel circuits, a first conductive layer and a second conductive layer.
  • the plurality of pixel circuits are arranged on the substrate, and the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns.
  • the first conductive layer includes a plurality of conductive patterns, the plurality of conductive patterns are spaced apart from the plurality of pixel circuits, and the pixel circuits include at least two contact portions spaced apart.
  • the second conductive layer is arranged on a side of the first conductive layer away from the substrate.
  • the second conductive layer includes a plurality of first signal lines, the plurality of first signal lines are spaced apart along a first direction, and all extend along a second direction; one of the first signal lines is electrically connected to at least one conductive pattern, and the first signal line is connected to at least two contact portions of the conductive pattern.
  • the first direction is the row direction in which the plurality of pixel circuits are arranged
  • the second direction is the column direction in which the plurality of pixel circuits are arranged.
  • the first conductive layer further comprises a plurality of first connection lines, the plurality of first connection lines are arranged at intervals along the second direction, and all extend along the first direction.
  • the second conductive layer further comprises a plurality of data lines, one data line is electrically connected to a column of pixel circuits; the plurality of data lines comprises a plurality of first data lines and a plurality of second data lines, the plurality of first data lines are respectively located on both sides of the plurality of second data lines; one first data line is connected to one first connection line.
  • the plurality of first signal lines comprises a plurality of fan-out lines, one fan-out line is electrically connected to one first connection line.
  • the plurality of conductive patterns comprises a plurality of first conductive patterns, the fan-out line is electrically connected to at least one first conductive pattern.
  • the fan-out line includes a plurality of fan-out sub-lines spaced apart along the second direction, and two ends of two adjacent fan-out sub-lines close to each other are electrically connected to the same first conductive pattern.
  • the first conductive pattern includes an extension portion and two contact portions, the extension portion extending along the first conductive pattern.
  • the fan-out sub-lines extend in two directions, the two contact portions are respectively connected to the two ends of the extension portion along the second direction, and the size of the contact portion along the first direction is larger than the size of the extension portion along the first direction.
  • the fan-out line is continuous along the second direction;
  • the first conductive pattern includes a plurality of contact portions and at least one extension portion alternately connected along the second direction, the extension portion extends along the second direction, and the size of the contact portion along the first direction is greater than the size of the extension portion along the first direction.
  • the fan-out line is electrically connected to the plurality of contact portions of the first conductive pattern.
  • the plurality of first conductive patterns are arranged in a plurality of columns along the first direction, and each column includes a plurality of first conductive patterns arranged along the second direction.
  • a fan-out line is electrically connected to the plurality of first conductive patterns in one column.
  • the plurality of first conductive patterns are evenly arranged, and the arrangement density of the pixel circuits is an integer multiple of the arrangement density of the first conductive patterns.
  • the array substrate includes a display area and a peripheral area surrounding the display area, and the plurality of pixel circuits are arranged in the display area.
  • the array substrate also includes a first power bus, which is located in the peripheral area and is configured to be electrically connected to the cathode of the light-emitting device.
  • the plurality of first signal lines also include a plurality of first power signal lines, and along the second direction, at least one end of the plurality of first power signal lines is electrically connected to the first power bus.
  • the plurality of conductive patterns also include a plurality of second conductive patterns, and one first power signal line is electrically connected to at least one second conductive pattern.
  • one first power signal line is electrically connected to a plurality of second conductive patterns, and the plurality of second conductive patterns are evenly arranged.
  • the plurality of conductive patterns include a plurality of first conductive patterns; the plurality of first conductive patterns have the same structure as the plurality of second conductive patterns, and the plurality of first conductive patterns have the same arrangement density as the plurality of second conductive patterns.
  • a display device comprising a plurality of light emitting devices and an array substrate as described in any one of the above embodiments, wherein the plurality of light emitting devices are arranged on the array substrate, and one light emitting device is connected to one pixel circuit of the array substrate.
  • a display device comprising the above-mentioned display panel.
  • FIG. 1 is a schematic diagram of a display device according to some embodiments.
  • FIG2 is a driving architecture diagram of a display device according to some further embodiments.
  • FIG3 is a cross-sectional structural diagram of a display panel according to some embodiments.
  • FIG4 is a top view of a first conductive layer and a second conductive layer according to some embodiments.
  • FIG5 is a partial enlarged view of area B in FIG4 ;
  • FIG6 is a cross-sectional view along the section line A1-A1 in FIG5;
  • FIG7 is a partial structural diagram of an array substrate according to some embodiments.
  • FIG8 is a top view of a first conductive layer and a second conductive layer according to some embodiments.
  • FIG9 is a partial enlarged view of the C area in FIG8;
  • FIG10 is a cross-sectional view along the section line A2-A2 in FIG9;
  • FIG11 is a diagram showing a connection structure between a first signal line and a conductive pattern according to some embodiments.
  • FIG. 12 is a top view of the structure of an array substrate without including the second conductive layer according to some embodiments.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • connection and its derivative expressions may be used.
  • connection should be understood in a broad sense.
  • connection can be a fixed connection, a detachable connection, or an integral connection; it can be a direct connection or an indirect connection through an intermediate medium.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of the layers and the area of the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • an embodiment of the present disclosure provides a display device 1000, which is a product having an image display function.
  • the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still image) and either text or image.
  • the display device 1000 may be a television, a laptop computer, a tablet computer, a personal digital assistant (PDA), a mobile phone (cell phone), a watch, a clock, a calculator, a GPS receiver/navigator, a camera, a display of a camera view (e.g., a display of a rear-view camera in a vehicle), a wearable device, an augmented reality (AR) device, a virtual reality (VR) device, a vehicle display, a flight display, or any other product or component having a display function.
  • the display device 1000 may be a mobile phone.
  • the display device 1000 may be an organic light-emitting diode display device, a quantum dot electroluminescent display device (Quantum Dot Light Emitting Diodes; abbreviated as: QLED) or a micro light-emitting diode (Mini/Micro Light Emitting Display; abbreviated as: MLED), etc.
  • QLED Quantum Dot Light Emitting Diodes
  • MLED micro light-emitting diode
  • the display device 1000 may be a flat display device, a curved display device or a foldable display device, etc.
  • the display device 1000 may be rectangular or circular, etc. The embodiments of the present disclosure do not specifically limit this.
  • the following takes an organic light-emitting diode display device in which the display device is rectangular and planar as an example to schematically illustrate some embodiments of the present disclosure, but the embodiments of the present disclosure are not limited to this, and also Any other display device may be considered as long as the same technical idea is applied.
  • the display device 1000 includes a display panel 1100 and a driving circuit board 1200.
  • the driving circuit board 1200 may include, for example, a timing controller (TCON), a power management chip DC/DC, and an adjustable resistor voltage divider circuit (generating Vcom) and other driving circuits.
  • the driving circuit board 1200 may also include other circuit structures, which are not listed here one by one.
  • the driving circuit board 1200 is electrically connected to the display panel 1100 and is used to transmit a control signal to the display panel 1100, thereby driving the display panel 1100 to realize image display.
  • the display device 1000 may also include a touch structure, an under-screen camera, and an under-screen fingerprint recognition sensor, so that the display device 1000 can realize a variety of different functions such as touch, photo taking, video recording, fingerprint recognition or face recognition, which are not specifically limited here.
  • the display panel 1100 has a display area AA and a peripheral area BB.
  • the peripheral area BB is at least located on one side of the display area AA.
  • the peripheral area BB is disposed around the display area AA.
  • the display area AA is an area on the display panel 1100 for displaying images.
  • the display area AA is provided with a plurality of sub-pixels P.
  • the sub-pixel P is the smallest light-emitting unit on the display panel 1100 and is used to display images.
  • the peripheral area BB can be used, for example, to set a gate driver circuit (Gate driver on Array, GOA for short) and control signal lines (such as clock signal lines, power supply voltage signal lines, etc.).
  • GOA gate driver on Array
  • control signal lines such as clock signal lines, power supply voltage signal lines, etc.
  • the multiple sub-pixels P may emit light of different colors.
  • the multiple sub-pixels P include a red light sub-pixel emitting red light, a green light sub-pixel emitting green light, and a blue light sub-pixel emitting blue light.
  • a plurality of sub-pixels P are arranged in a plurality of rows and a plurality of columns, each row includes a plurality of sub-pixels P arranged along a first direction X, and a plurality of rows of sub-pixels P are arranged along a second direction Y.
  • Each column includes a plurality of sub-pixels P arranged along a second direction Y, and a plurality of columns of sub-pixels P are arranged along the first direction X.
  • the first direction X and the second direction Y intersect, for example, the first direction X is perpendicular to the second direction Y.
  • the sub-pixel P includes a pixel circuit 120 and a light-emitting device 200.
  • the pixel circuit 120 includes a plurality of thin film transistors (TFT) and at least one capacitor Cst.
  • TFT thin film transistors
  • the pixel circuit 120 may be a "3T1C” circuit, a "7T1C” circuit, or an "8T1C” circuit, etc.
  • the embodiments of the present disclosure are not limited thereto, and any other pixel circuits may also be considered as long as the same technical concept is applied.
  • T refers to TFT
  • the number before “T” refers to the number of TFTs
  • C refers to the capacitor Cst
  • the number before “C” refers to the number of capacitors Cst.
  • the display panel 1100 includes a stacked array substrate 100, a light emitting device 200, and an encapsulation layer 300.
  • the display panel 1100 may also include a functional stack disposed on the side of the encapsulation layer 300 away from the array substrate 100.
  • the functional stack may be, for example, one or more of a touch function layer, an anti-reflection layer, a hardening layer, and an anti-fingerprint layer, so that the display panel can achieve corresponding functions.
  • the embodiments of the present disclosure do not specifically limit the types and quantities of the above-mentioned functional stacks.
  • the light emitting device 200 includes an anode 201, a light emitting functional layer 202 and a cathode layer 203 arranged in a stacked manner.
  • the cathode layers 203 of the plurality of light emitting devices 200 are connected to each other to form a continuous whole layer structure.
  • the display panel 1100 may also include
  • the pixel defining layer PDL is provided on a side of the anode 201 away from the array substrate 100 , and the pixel defining layer PDL includes a plurality of openings, and at least a portion of each light emitting functional layer 202 is located in one opening.
  • the encapsulation layer 300 is configured to reduce the risk of water vapor and oxygen in the external environment entering the light-emitting device 200, thereby increasing the service life of the display panel 1100.
  • the encapsulation layer 300 may be an encapsulation film or an encapsulation substrate.
  • the encapsulation layer 300 may be an encapsulation film, in which case the encapsulation layer 300 may include a first inorganic encapsulation layer 301, an organic encapsulation layer 302, and a second inorganic encapsulation layer 303 that are sequentially stacked.
  • the array substrate 100 includes a substrate 110 and a pixel circuit disposed on the substrate 110.
  • One pixel circuit is connected to a light-emitting device and is configured to drive the light-emitting device to emit light.
  • the substrate 110 may be a rigid substrate, and the material of the rigid substrate may include glass, for example.
  • the substrate 110 may be a flexible substrate, and the material of the flexible substrate may include any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).
  • the array substrate 100 may include a plurality of conductive layers, and the plurality of conductive layers are configured to form a plurality of pixel circuits and a plurality of signal lines for driving the pixel circuits.
  • the plurality of conductive layers may include a first semiconductor layer ACT1, a first gate conductive layer GT1, a second gate conductive layer GT2, a second semiconductor layer ACT2, a third gate conductive layer GT3, a first source-drain conductive layer SD1, and a second source-drain conductive layer SD2, which are sequentially arranged in a direction perpendicular to the substrate 110 and away from the substrate 110.
  • the array substrate may also include other conductive layers, such as a third source-drain conductive layer, which is not specifically limited here, as long as the same technical idea is adopted.
  • the thin film transistor TFT may include a semiconductor pattern 101 located in the first semiconductor layer ACT1, a gate 102 located in the first gate conductive layer GT1, and a source 103 and a drain 104 located in the first source-drain conductive layer SD1;
  • the storage capacitor Cst may include a first electrode C1 located in the first gate conductive layer GT1 and a second electrode C2 located in the second gate conductive layer GT2.
  • the array substrate 100 may further include an insulating layer between adjacent conductive layers, for example, the array substrate 100 may include a first gate insulating layer GI1 between the first semiconductor layer ACT1 and the first gate conductive layer GT1, a second gate insulating layer GI2 between the first gate conductive layer GT1 and the second gate conductive layer GT2, a first interlayer dielectric layer ILD1 between the second gate conductive layer GT2 and the second semiconductor layer ACT2, a second interlayer dielectric layer ILD2 between the second semiconductor layer ACT2 and the third gate conductive layer GT3, a first planar layer PLN1 between the third gate conductive layer GT3 and the first source-drain conductive layer SD1, and a second planar layer PLN2 between the first source-drain conductive layer SD1 and the second source-drain conductive layer SD2.
  • the array substrate 100 may further include other insulating film layers, which will not be described one by one here.
  • the array substrate 100 provided in the embodiment of the present disclosure includes a first conductive layer 10 and a second conductive layer 20 , wherein the second conductive layer 20 is disposed on a side of the first conductive layer 10 away from the substrate 110 .
  • the first conductive layer 10 includes a plurality of conductive patterns 11, and the plurality of conductive patterns 11 are spaced apart from the plurality of pixel circuits.
  • the spaced apart between the conductive patterns 11 and the plurality of pixel circuits means that the conductive patterns 11 are not directly connected to the pixel circuits 120, or the conductive patterns 11 are not used to transmit signals to the pixel circuits 120.
  • the pixel circuit may include a source and a drain located on the first source-drain conductive layer SD1.
  • the conductive pattern 11 is spaced from the source and drain of the pixel circuit; moreover, the conductive pattern 11 is not connected to other conductive layers (such as the first gate conductive layer and the second gate conductive layer, etc.) on the side of the first conductive layer 10 close to the substrate, and the semiconductor layer.
  • the second conductive layer 20 includes a plurality of first signal lines 21, which are arranged at intervals along a first direction X and extend along a second direction Y.
  • the first direction X is a row direction (horizontal direction in FIG. 4 ) in which the plurality of pixel circuits 120 are arranged
  • the second direction Y is a column direction in which the plurality of pixel circuits 120 are arranged.
  • the first direction X and the second direction Y intersect, for example, the first direction X is perpendicular to the second direction Y.
  • a first signal line 21 is electrically connected to at least one conductive pattern 11. Since the conductive pattern 11 is spaced apart from the pixel circuit, the first signal line 21 does not transmit electrical signals to the pixel circuit through the conductive pattern 11. Based on this, the position of the conductive pattern 11 can be arbitrarily set as long as it does not interfere with other structures of the array substrate (such as contact or electrical coupling).
  • the static electricity will gather at the protrusions, corners or other protruding sharp corners of the first signal line 21.
  • a via 105 is formed in the insulating layer between the first conductive layer 10 and the second conductive layer 20, and a portion of the first signal line 21 is located in the via 105, and a protrusion is formed in the via 105.
  • the first signal line 21 protrudes toward the side close to the substrate 110 to form a protrusion.
  • the conductive pattern 11 includes at least two contact portions 1112 arranged at intervals, and the first signal line 21 is connected to at least two contact portions 1112 of the conductive pattern 11, that is, the first signal line 21 includes two positions connected to the contact portions 1112. In this way, the first signal line 21 can form two protrusions at the position where it is connected to the conductive pattern 11, which is more conducive to the transmission of static electricity to the conductive pattern 11.
  • the first conductive layer 10 can be any one of the multiple conductive layers included in the array substrate 100 as shown in FIG3, except for the conductive layer farthest from the substrate 110, and the second conductive layer 20 can be any conductive layer on the side of the first conductive layer 10 far from the substrate 110.
  • the second conductive layer 20 can be a film layer for setting signal routing in the array substrate 100
  • the first conductive layer 10 is any conductive layer on the side of the second conductive layer 20 close to the substrate 110.
  • the first conductive layer 10 is a conductive layer adjacent to the second conductive layer 20.
  • the depth of the via hole in the insulating layer between the first conductive layer 10 and the second conductive layer 20 at the connection position between the first signal line 21 and the conductive pattern 11 can be reduced, thereby reducing the difficulty of connecting the first signal line 21 with the conductive pattern 11.
  • the first conductive layer 10 may be the third gate conductive layer GT3, and the second conductive layer 20 may be the first source-drain conductive layer SD1; or, the first conductive layer 10 may be the first source-drain conductive layer SD1, and the second conductive layer 20 may be the second source-drain conductive layer SD2; or, in the case where the array substrate includes the third source-drain conductive layer, the first conductive layer 10 may be the second source-drain conductive layer SD2, and the second conductive layer 20 may be the third source-drain conductive layer.
  • the first conductive layer 10 and the second conductive layer 20 may not be adjacent conductive layers.
  • the first conductive layer 10 may be the third gate conductive layer GT3, and the second conductive layer 20 can be a second source-drain conductive layer SD2. It is understandable that the first conductive layer 10 and the second conductive layer 20 can also be other suitable combinations, and the embodiments of the present disclosure will not be listed one by one, as long as the same technical ideas are adopted.
  • the first conductive layer 10 is the first source-drain conductive layer SD1
  • the second conductive layer 20 is the second source-drain conductive layer SD2.
  • the embodiments of the present application are not limited thereto, as long as the same technical concept is adopted.
  • the first conductive layer 10 further includes a plurality of first connection lines 12, which are arranged at intervals along the second direction Y and extend along the first direction X.
  • the second conductive layer 20 further includes a plurality of data lines 22, and one data line 22 is electrically connected to a column of pixel circuits.
  • the plurality of data lines 22 include a plurality of first data lines 221 and a plurality of second data lines 222, and the plurality of first data lines 221 are respectively located on both sides of the plurality of second data lines 222 along the first direction X.
  • the plurality of first data lines 221 may be located in the edge area AA2 of the display area AA along the first direction X, and the plurality of second data lines 222 may be located in the center area AA1 of the display area AA along the first direction X.
  • One first data line 221 is connected to one first connection line 12.
  • the plurality of first signal lines 21 included in the second conductive layer 20 include a plurality of fan-out lines 211, and one fan-out line 211 is electrically connected to one first connection line 12.
  • a plurality of fan-out lines 211 may be located in the central area AA1 of the display area AA along the first direction X.
  • the first data line 221 located in the edge area AA2 of the display area AA along the first direction X is connected to the central area AA1 of the display area AA along the first direction X through a first connection line 12 and a fan-out line 211 in sequence, and is led out from the edge of the central area AA1 close to the peripheral area.
  • the above-mentioned arrangement of the data line 22 is also called display area fan-out (Fanout In AA; abbreviated as: FIAA) or panel fan-out (Fanout In Panel; abbreviated as: FIP).
  • the fan-out line 211 is arranged in the central area AA1 of the display area AA, and is not used to transmit data signals to the pixel circuit of the central area AA1, that is, the fan-out line 211 is electrically insulated from the pixel circuit located on the side of the fan-out line 211 close to the substrate 110.
  • the fan-out line 211 is disposed in a single film layer, and is not connected to other structures except the first connection line 12 in the display area AA, resulting in a lack of a path for the generated static electricity to be released; and the fan-out line 211 extends between sub-pixels, and needs to avoid some conductive structures in the pixel circuit, so it has a certain pattern shape, such as corners or protrusions, and static electricity may accumulate at the corners or protrusion edges of the fan-out line 211. For the above reasons, static electricity is easily accumulated in the fan-out line, resulting in low reliability of the array substrate.
  • the plurality of conductive patterns 11 include a plurality of first conductive patterns 111, a fan-out line 211 is electrically connected to at least one first conductive pattern 111, and a protruding structure protruding toward a side close to the substrate 110 is formed at a position where the fan-out line 211 is connected to the first conductive pattern 111.
  • the static electricity when static electricity appears on the fan-out line 211, the static electricity will be transmitted toward the position where the fan-out line 211 is connected to the first conductive pattern 111, and then transmitted to the first conductive pattern 111, and the static electricity will be released on the first conductive pattern 111, which can improve the reliability of the array substrate.
  • the fan-out line 211 includes a plurality of fan-out sub-lines 2111 spaced apart along the second direction Y.
  • the fan-out line 211 includes a plurality of fan-out sub-lines 2111 that are disconnected from each other, and an opening 2112 is included between two adjacent fan-out sub-lines 2111.
  • the two ends that belong to two adjacent fan-out sub-lines 2111 and are close to each other are electrically connected to the same first conductive pattern 111, that is, the two adjacent fan-out sub-lines 2111 are electrically connected through one first conductive pattern 111.
  • the fan-out line 211 when the fan-out line 211 is transmitting current, the current can flow through each first conductive pattern 111, ensuring that the static electricity on the fan-out line 211 can be transmitted to the first conductive pattern 111 and released through the first conductive pattern 111.
  • the first conductive pattern 111 includes an extension portion 1111 and two contact portions 1112, the extension portion 1111 extends along the second direction Y, and the two contact portions 1112 are respectively connected to two ends of the extension portion 1111 along the second direction Y.
  • An opening 2112 is provided between two adjacent fan-out sub-lines 2111, and the orthographic projection of the opening 2112 on the substrate 110 overlaps with the orthographic projection of the extension portion 1111 on the substrate 110, and two ends belonging to two adjacent fan-out sub-lines 2111 and close to each other are respectively electrically connected to the two contact portions 1112 of the same first conductive pattern 111.
  • the size of the contact portion 1112 along the first direction X is greater than the size of the extension portion 1111 along the first direction X.
  • the fan-out line 211 is continuous along the second direction Y, that is, there is no opening on the fan-out line 211 , so that the fan-out line 211 is arranged in parallel with the first conductive pattern 111 , and the first conductive pattern 111 can not only release the static electricity on the fan-out line 211 , but also reduce the resistance of the fan-out line 211 .
  • the first conductive pattern 111 includes a plurality of contact portions 1112 and at least one extension portion 1111 alternately connected along the second direction Y.
  • the size of the contact portion 1112 along the first direction X is larger than the size of the extension portion 1111 along the first direction X, which is conducive to reducing the alignment accuracy requirement between the fan-out line 211 and the contact portion 1112, reducing the connection difficulty between the fan-out line 211 and the contact portion 1112, and increasing the contact area between the fan-out line 211 and the contact portion 1112, thereby reducing the resistance at the connection between the fan-out line 211 and the contact portion 1112.
  • the fan-out line 211 is electrically connected to the plurality of contact portions 1112 of the first conductive pattern 111.
  • the fan-out line 211 includes a plurality of connection points with the same first conductive pattern 111, which is conducive to increasing the connection reliability and stability between the fan-out line 211 and the same first conductive pattern 111, and is conducive to reducing the resistance of the fan-out line 211.
  • a contact portion 1112 is respectively provided at both ends of the first conductive pattern 111 along the second direction Y, and two adjacent contact portions 1112 are connected by an extension portion 1111.
  • the first conductive pattern 111 includes two contact portions 1112 and one extension portion 1111; or, referring to FIG11 , the first conductive pattern 111 may also include three contact portions 1112 and two extension portions 1111, and the first conductive pattern 111 may also include other numbers of two contact portions 1112 and extension portions 1111, as long as the same technical idea is adopted.
  • a plurality of first conductive patterns 111 are arranged in a plurality of columns along the first direction X, and each column includes at least one first conductive pattern 111 arranged along the second direction Y.
  • the first conductive pattern 111 is electrically connected, so that the density of the first conductive pattern 111 connected to the fan-out line 211 can be increased, and the static electricity generated at any position on the fan-out line 211 can be transmitted to the adjacent first conductive pattern 111, further improving the static electricity release effect of the fan-out line 211.
  • different filling patterns are used for the two, but the two are in the same film layer and are prepared together using the same film forming process.
  • a plurality of first conductive patterns 111 are evenly arranged, which is beneficial to improving the uniformity of the first conductive patterns 111 and improving the pattern uniformity of the first conductive layer 10.
  • the arrangement density of the pixel circuits 120 is an integer multiple of the arrangement density of the first conductive patterns 111.
  • the spacing of the first conductive patterns 111 in the second direction Y is an integer multiple of the spacing of the pixel circuits 120 in the second direction Y (the pitch of the pixel circuits 120), that is, a first conductive pattern 111 is provided on a side away from the substrate for each integer number of pixel circuits 120, which is beneficial to improving the uniformity of the structure of the array substrate 100 and reducing the risk of the display panel having a blanking problem due to the distribution difference of the first conductive patterns 111.
  • the arrangement density of the pixel circuits 120 is equal to the arrangement density of the first conductive patterns 111. In this way, the pattern uniformity of the first conductive layer 10 can be improved to the maximum extent, and the structural uniformity of the array substrate can be improved to the maximum extent.
  • the array substrate 100 further includes a first power bus VSS, which is located in the peripheral area BB.
  • the first power bus VSS is configured to be electrically connected to the cathode of the light-emitting device 200, that is, the first power bus VSS is electrically connected to the cathode layer 203.
  • the plurality of first signal lines 21 included in the second conductive layer 20 further include a plurality of first power signal lines 212, and at least one end of the plurality of first power signal lines 212 is electrically connected to the first power bus VSS along the second direction Y.
  • the plurality of first power signal lines 212 are arranged at intervals along the first direction X, and the plurality of first power signal lines 212 all extend along the second direction Y, and are then electrically connected to the cathode layer.
  • the plurality of first power signal lines 212 can reduce the resistance of the cathode layer, thereby reducing the voltage drop on the cathode layer, and improving the display uniformity of the display area AA.
  • the configuration method using the above-mentioned power auxiliary line 50 is also called SIP (VSS In Panel) technology.
  • the plurality of conductive patterns 11 further include a plurality of second conductive patterns 112.
  • a first power signal line 212 is electrically connected to at least one second conductive pattern 112.
  • the first power signal line 212 protrudes toward a side close to the substrate at a position where it is connected to the second conductive pattern 112 to form a protrusion.
  • the static electricity will accumulate at the protruding position of the first power signal line 212. That is, the static electricity will be transmitted to the connection position between the first power signal line 212 and the second conductive pattern 112, and transmitted to the second conductive pattern 112.
  • a tip discharge occurs at the edge or end of the second conductive pattern 112, thereby releasing the static electricity to the insulating layer in contact with the conductive pattern 112.
  • the static electricity usually has a small charge.
  • the insulating layer (such as a passivation layer or a planarization layer) can absorb and release a small amount of static electricity, thereby releasing the static electricity on the first power signal line 212. It can be understood that the static electricity charge is small. Although the insulating layer is electrically insulated, it can absorb static electricity and release it.
  • a first power signal line 212 and a plurality of second conductive patterns 112 is electrically connected, and multiple second conductive patterns 112 are evenly arranged.
  • the density of the second conductive patterns 112 connected to the first power signal line 212 can be increased.
  • the static electricity generated at any position on the first power signal line 212 can be transmitted to the adjacent second conductive patterns 112, further improving the static electricity release effect of the first power signal line 212.
  • the plurality of conductive patterns 11 include a plurality of first conductive patterns 111 and a plurality of second conductive patterns 112.
  • the plurality of first conductive patterns 111 have the same structure as the plurality of second conductive patterns 112, that is, the shape of the orthographic projection of the first conductive pattern 111 on the substrate is the same as the shape of the orthographic projection of the second conductive pattern 112 on the substrate, and the size of the orthographic projection of the first conductive pattern 111 on the substrate is equal to the size of the orthographic projection of the second conductive pattern 112 on the substrate.
  • the arrangement density of the plurality of first conductive patterns 111 and the plurality of second conductive patterns 112 is the same. In this way, the structural uniformity of the first conductive layer 10 can be further improved, and the risk of image fading in the display panel can be reduced.
  • the first conductive pattern 111 and the second conductive pattern 112 may also be different.
  • the first conductive pattern 111 includes two contact portions 1112
  • the second conductive pattern 112 may include one, three, or other number of contact portions; the embodiments of the present disclosure are not limited thereto, as long as the same technical concept is adopted.
  • the first power signal line 212 may also include a plurality of power sub-lines 2121 spaced apart along the second direction Y, and the structure of the fan-out sub-line 2111 is the same as the structure of the power sub-line 2121, that is, the shape and size of the orthographic projection of the fan-out sub-line 2111 on the substrate are respectively the same as the shape and size of the orthographic projection of the power sub-line 2121 on the substrate.
  • the first power signal line 212 may also be continuous along the second direction Y. This is beneficial to improving the structural uniformity of the second conductive layer 20.
  • the first power signal line 212 may also be continuous along the second direction Y.
  • the first power signal line 212 may also include a plurality of power sub-lines spaced apart along the second direction Y.
  • the embodiments of the present disclosure are not limited thereto, as long as the same technical concept is adopted.

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Abstract

一种阵列基板，所述阵列基板包括衬底、多个像素电路、第一导电层和第二导电层。多个像素电路设置于衬底上，且多个像素电路排列为多行和多列。第一导电层包括多个导电图案，多个导电图案与多个像素电路具有间隔，导电图案包括至少两个间隔设置的接触部。第二导电层设置于第一导电层远离衬底的一侧。第二导电层包括多条第一信号线，多条第一信号线沿第一方向间隔排布，且均沿第二方向延伸；一条第一信号线与至少一个导电图案电连接，且第一信号线与导电图案的至少两个接触部连接。

Description

阵列基板、显示面板及显示装置
本申请要求于2023年11月30日提交的、申请号为202311635363.8的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种阵列基板、显示面板及显示装置。
背景技术
有机发光二极管(Organic Light-Emitting Diode；简称：OLED)显示面板凭借其自发光、不需背光源、对比度高、厚度薄、视角广、反应速度快、可用于柔性面板、使用温度范围广、构造及制程较简单等优异性能，逐渐成为显示领域的主流产品之一，OLED显示面板可广泛应用于智能手机、平板电脑、电视和可穿戴设备(比如手表)等终端产品中。
OLED显示面板包括阵列基板以及设置于阵列基板上的发光器件。阵列基板包括多条信号线，信号线用于为阵列基板传输相应的控制信号，以驱动显示面板进行图像显示。如何避免信号线上发生静电积累，是显示面板中亟需解决的一个技术问题。
发明内容
一方面，提供一种阵列基板。所述阵列基板包括衬底、多个像素电路、第一导电层和第二导电层。所述多个像素电路设置于所述衬底上，且所述多个像素电路排列为多行和多列。所述第一导电层包括多个导电图案，所述多个导电图案与所述多个像素电路具有间隔，且所述像素电路包括至少两个间隔设置的接触部。所述第二导电层设置于所述第一导电层远离所述衬底的一侧。所述第二导电层包括多条第一信号线，所述多条第一信号线沿第一方向间隔排布，且均沿第二方向延伸；一条所述第一信号线与至少一个导电图案电连接，且所述第一信号线与所述导电图案的至少两个接触部连接。所述第一方向为所述多个像素电路排列的行方向，所述第二方向为所述多个像素电路排列的列方向。
在一些实施例中，所述第一导电层还包括多条第一连接线，所述多条第一连接线沿所述第二方向间隔排布，且均沿所述第一方向延伸。所述第二导电层还包括多条数据线，一条数据线与一列像素电路电连接；所述多条数据线包括多条第一数据线和多条第二数据线，所述多条第一数据线分别位于所述多条第二数据线的两侧；一条第一数据线与一条第一连接线连接。所述多条第一信号线包括多条扇出线，一条扇出线与一条第一连接线电连接。所述多个导电图案包括多个第一导电图案，所述扇出线与至少一个第一导电图案电连接。
在一些实施例中，所述扇出线包括沿所述第二方向间隔设置的多个扇出子线，相邻两个扇出子线的相互靠近的两端，与同一个第一导电图案电连接。
在一些实施例中，所述第一导电图案包括延伸部和两个接触部，所述延伸部沿所述第 二方向延伸，所述两个接触部分别与所述延伸部沿所述第二方向的两端连接，所述接触部沿所述第一方向的尺寸大于所述延伸部沿所述第一方向的尺寸。相邻两个扇出子线之间具有开口，相邻两个扇出子线的相互靠近的两端，分别与同一个第一导电图案的两个接触部电连接。
在一些实施例中，所述扇出线沿所述第二方向连续；所述第一导电图案包括沿所述第二方向交替连接的多个接触部和至少一个延伸部，所述延伸部沿所述第二方向延伸，所述接触部沿所述第一方向的尺寸大于所述延伸部沿所述第一方向的尺寸。所述扇出线与所述第一导电图案的多个接触部电连接。
在一些实施例中，所述多个第一导电图案沿所述第一方向排列为多列，每列包括沿所述第二方向排列的多个第一导电图案。一条扇出线与一列的多个第一导电图案电连接。
在一些实施例中，沿所述第二方向，所述多个第一导电图案均匀排布。所述像素电路的排布密度，为所述第一导电图案的排布密度的整数倍。
在一些实施例中，所述阵列基板包括显示区和围绕所述显示区的周边区，所述多个像素电路设置于所述显示区。所述阵列基板还包括第一电源总线，所述第一电源总线位于所述周边区，被配置为与发光器件的阴极电连接。所述多条第一信号线还包括多条第一电源信号线，沿所述第二方向，所述多条第一电源信号线的至少一端与所述第一电源总线电连接。所述多个导电图案还包括多个第二导电图案，一条第一电源信号线与至少一个第二导电图案电连接。
在一些实施例中，沿所述第二方向，一条第一电源信号线与多个第二导电图案电连接，且所述多个第二导电图案均匀排布。
在一些实施例中，所述多个导电图案包括多个第一导电图案；所述多个第一导电图案与所述多个第二导电图案的结构相同，且所述多个第一导电图案与所述多个第二导电图案的排布密度相同。
另一方面，提供一种显示装置。所述显示装置包括多个发光器件以及如上述任一实施例所述的阵列基板。所述多个发光器件设置于所述阵列基板上，且一个发光器件与阵列基板的一个像素电路连接。
又一方面，提供一种显示装置。所述显示装置包括上述显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的示意图；
图2为根据又一些实施例的显示装置的驱动架构图；
图3为根据一些实施例的显示面板的剖面结构图；
图4为根据一些实施例的第一导电层和第二导电层的俯视结构图；
图5为图4中B区域的局部放大图；
图6为沿图5中剖面线A1-A1的剖面图；
图7为根据一些实施例的阵列基板的局部结构图；
图8为根据一些实施例的第一导电层和第二导电层的俯视结构图；
图9为图8中C区域的局部放大图；
图10为沿图9中剖面线A2-A2的剖面图；
图11为根据一些实施例的第一信号线与导电图案的一种连接结构图；
图12为根据一些实施例的不包括第二导电层时阵列基板的俯视结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例”、“一些实施例”、“示例性实施例”、“示例”或“一些示例”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值 的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
参阅图1，本公开的实施例提供了一种显示装置1000，显示装置1000为具有图像显示功能的产品。示例性地，显示装置1000可以是显示不论运动(例如，视频)的还是固定(例如，静止图像)的且不论文字的还是图像的任何装置。
示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、个人数字助理(Personal Digital Assistant；简称：PDA)、移动电话(手机)、表、时钟、计算器、GPS接收器/导航仪、相机、相机视图的显示器(例如，车辆中后视相机的显示器)、可穿戴设备、增强现实(Augmented Reality；简称：AR)设备、虚拟现实(Virtual Reality；简称：VR)设备、车载显示器、飞行显示器等任何具有显示功能的产品或者部件。例如，如图1所示，显示装置1000可以为手机。
从显示装置1000的发光类型上看，上述显示装置1000可以是有机发光二极管显示装置、量子点电致发光显示装置(Quantum Dot Light Emitting Diodes；简称：QLED)或者微型发光二极管(Mini/Micro Light Emitting Display；简称：MLED)等。从显示装置1000的形态上看，上述显示装置1000可以是平面显示装置、曲面显示装置或者可折叠显示装置等。从显示装置1000的形状上看，上述显示装置1000可以是矩形或圆形等。本公开的实施例对此不做具体限定。下面以显示装置为矩形的、且为平面的有机发光二极管显示装置为例，对本公开的一些实施例进行示意性说明，但是本公开的实施方式不限于此，并且也 可以考虑任何其它显示装置，只要应用相同的技术思想即可。
参阅图2，在一些实施例中，显示装置1000包括显示面板1100和驱动电路板1200。驱动电路板1200比如可以包括时序控制器(Timing Controller；简称：TCON)，电源管理芯片DC/DC和可调电阻分压电路(生成Vcom)等驱动电路，驱动电路板1200还可以包括其他电路结构，此处不再一一列举。驱动电路板1200与显示面板1100电连接，用于向显示面板1100传输控制信号，进而驱动显示面板1100实现图像显示。除此之外，显示装置1000还可以包括触控结构、屏下摄像头以及屏下指纹识别传感器等，使得显示装置1000能够实现触控、拍照、录像、指纹识别或者人脸识别等多种不同功能，此处不做具体限定。
继续参阅图2，显示面板1100具有显示区AA和周边区BB，周边区BB至少位于显示区AA的一侧，示例性地，周边区BB围绕显示区AA设置。
显示区AA为显示面板1100上用于显示图像的区域，显示区AA设有多个子像素P，子像素P为显示面板1100上的最小发光单元，子像素P用于显示图像。周边区BB比如可以用于设置栅极驱动电路(Gate driver on Array，简称：GOA)以及控制信号线(比如时钟信号线、电源电压信号线等)等，当然，周边区BB的功能不限于此，不公开的实施例不再一一赘述。
其中，多个子像素P可以发射不同颜色的光线，比如，多个子像素P包括发射红色光线的红光子像素、发射绿色光线的绿光子像素和发射蓝色光线的蓝光子像素。
多个子像素P排列成多行和多列，每行包括沿第一方向X排列的多个子像素P，多行子像素P沿第二方向Y排列。每列包括沿第二方向Y排列的多个子像素P，多列子像素P沿第一方向X排列。其中，第一方向X和第二方向Y交叉，比如，第一方向X与第二方向Y垂直。
子像素P包括像素电路120和发光器件200。像素电路120包括多个薄膜晶体管(Thin Film Transistor；简称：TFT)和至少一个电容器Cst。示例性地，像素电路120可以为“3T1C”电路、“7T1C”电路或“8T1C”电路等，本公开的实施方式不限于此，并且也可以考虑任何其它像素电路，只要应用相同的技术思想即可。其中，“T”是指TFT，“T”前面的数字是指TFT的数量；“C”是指电容器Cst，“C”前面的数字是指电容器Cst的数量。
参阅图3，在一些实施例中，显示面板1100包括层叠设置的阵列基板100、发光器件200和封装层300。当然，显示面板1100还可以包括设置于封装层300远离阵列基板100一侧的功能叠层，功能叠层比如可以是触控功能层、减反射层、硬化层和抗指纹层中的一种或多种，以使显示面板能够实现相应的功能，本公开的实施例对上述功能叠层的种类和数量不做具体限定。
其中，发光器件200包括沿包括层叠设置的阳极201、发光功能层202和阴极层203。多个发光器件200的阴极层203相互连接形成连续的整层结构。显示面板1100还可以包 括像素界定层PDL，像素界定层PDL设置于阳极201远离阵列基板100的一侧，且像素界定层PDL包括多个开口，每个发光功能层202的至少部分位于一个开口内。
封装层300被配置为降低外界环境中的水汽和氧气进入发光器件200内的风险，进而提升显示面板1100的使用寿命。封装层300可以为封装薄膜，也可以为封装基板。示例性地，如图3所示，封装层300可以为封装薄膜，此时，封装层300可以包括依次层叠设置的第一无机封装层301、有机封装层302和第二无机封装层303。
阵列基板100包括衬底110和设置于衬底110上的像素电路。一个像素电路与一个发光器件连接，被配置为驱动发光器件进行发光。其中，衬底110可以为刚性衬底，刚性衬底的材料比如包括玻璃。或者，衬底110可以为柔性衬底，柔性衬底的材料比如包括聚酰亚胺(Polyimide；简称：PI)、聚碳酸酯(Polycarbonate；简称：PC)或者聚氯乙烯(Polyvinyl chloride；简称：PVC)中的任一种。
阵列基板100可以包括多个导电层，多个导电层被配置为形成多个像素电路以及用于驱动像素电路的多条信号线。多个导电层比如可以包括沿垂直于衬底110且远离衬底110的方向依次设置的第一半导体层ACT1、第一栅导电层GT1、第二栅导电层GT2、第二半导体层ACT2、第三栅导电层GT3、第一源漏导电层SD1和第二源漏导电层SD2。当然，阵列基板还可以包括其他导电层，比如还可以包括第三源漏导电层，此处不做具体限定，只要采用相同的技术思路即可。其中，薄膜晶体管TFT可以包括位于第一半导体层ACT1的半导体图案101、位于第一栅导电层GT1的栅极102和位于第一源漏导电层SD1的源极103和漏极104；存储电容器Cst可以包括位于第一栅导电层GT1的第一极板C1和位于第二栅导电层GT2的第二极板C2。
阵列基板100还可以包括位于相邻导电层之间的绝缘层，比如，阵列基板100可以包括位于第一半导体层ACT1与第一栅导电层GT1之间的第一栅绝缘层GI1、位于第一栅导电层GT1与第二栅导电层GT2之间的第二栅绝缘层GI2、位于第二栅导电层GT2与第二半导体层ACT2之间的第一层间介质层ILD1、位于第二半导体层ACT2与第三栅导电层GT3之间的第二层间介质层ILD2、位于第三栅导电层GT3与第一源漏导电层SD1之间的第一平坦层PLN1、以及位于第一源漏导电层SD1与第二源漏导电层SD2之间的第二平坦层PLN2。当然，阵列基板100还可以包括其他绝缘膜层，此处不再一一赘述。
参阅图4、图5和图6，本公开的实施例提供的阵列基板100，包括第一导电层10和第二导电层20，第二导电层20设置于第一导电层10远离衬底110的一侧。
第一导电层10包括多个导电图案11，多个导电图案11与多个像素电路具有间隔，导电图案11与多个像素电路具有间隔是指：导电图案11与像素电路120不直接接触连接，或者说导电图案11不被用于向像素电路120传输信号。示例性地，在第一导电层10为第一源漏导电层SD1的情况下，像素电路可以包括位于第一源漏导电层SD1上的源极和漏 极，导电图案与像素电路的源极和漏极具有间隔；而且，导电图案11与第一导电层10的靠近衬底一侧的其他导电层(比如第一栅导电层和第二栅导电层等)以及半导体层均不连接。
第二导电层20包括多条第一信号线21，多条第一信号线21沿第一方向X间隔排布，且均沿第二方向Y延伸。第一方向X为多个像素电路120排列的行方向(图4中的水平方向)，第二方向Y为所述多个像素电路120排列的列方向，第一方向X和第二方向Y相交，比如，第一方向X垂直于第二方向Y。
一条第一信号线21与至少一个导电图案11电连接，由于导电图案11与像素电路具有间隔，因此，第一信号线21不通过导电图案11向像素电路传输电信号，基于此，导电图案11的位置可以任意设置，只要不与阵列基板的其他结构发生干扰(比如接触或者电耦合)即可。
在第一信号线21上出现静电的情况下，静电会聚集在第一信号线21的凸起、拐角或者其他凸出的尖角位置。在第一信号线21与导电图案11的连接位置，在第一导电层10与第二导电层20之间的绝缘层中形成过孔105，第一信号线21的部分位于过孔105内，并在过孔105内形成凸起，换言之，第一信号线21向靠近衬底110的一侧凸出形成了凸起。基于此，静电会向第一信号线21与导电图案11的连接位置(第一信号线21位于过孔105内的部分)聚集，并且传输至导电图案11上，然后经导电图案11被释放，进而将第一信号线21上的静电释放。如图6所示，导电图案11包括至少两个间隔设置的接触部1112，且第一信号线21与导电图案11的至少两个接触部1112连接，即第一信号线21包括两个与接触部1112连接的位置，这样，第一信号线21在与导电图案11连接的位置可以形成两个凸起，更有利于静电向导电图案11上传输。
其中，第一导电层10可以为如图3所示的阵列基板100所包括的多个导电层中，除了距离衬底110最远的一个导电层之外的任意一者，第二导电层20可以为第一导电层10远离衬底110一侧的任意导电层。示例性地，第二导电层20可以为阵列基板100中用于设置信号走线的膜层，第一导电层10为第二导电层20的靠近衬底110一侧的任意导电层。比如，第一导电层10为与第二导电层20相邻的导电层。这样，可以降低第一信号线21与导电图案11连接位置处，且设置于第一导电层10与第二导电层20之间的绝缘层中的过孔的深度，降低第一信号线21与导电图案11之间的连接难度。
示例性地，第一导电层10可以为第三栅导电层GT3，且第二导电层20可以为第一源漏导电层SD1；或者，第一导电层10可以为第一源漏导电层SD1，且第二导电层20为第二源漏导电层SD2；或者，在阵列基板包括第三源漏导电层的情况下，第一导电层10可以为第二源漏导电层SD2，且第二导电层20为第三源漏导电层。当然，第一导电层10和第二导电层20也可以不是相邻的导电层，示例性地，第一导电层10可以为第三栅导电层 GT3，且第二导电层20可以为第二源漏导电层SD2。可以理解的是，第一导电层10和第二导电层20还可以为其他合适的组合，本公开的实施例不再一一列举，只要采用相同的技术思路即可。
本公开的以下实施例中，均以第一导电层10为第一源漏导电层SD1，且第二导电层20为第二源漏导电层SD2为例进行示例性说明，但是本申请的实施例不限于此，只要采用相同的技术思路即可。
在一些实施例中，如图4和图7所示，第一导电层10还包括多条第一连接线12，多条第一连接线12沿第二方向Y间隔排布，且均沿第一方向X延伸。第二导电层20还包括多条数据线22，一条数据线22与一列像素电路电连接。多条数据线22包括多条第一数据线221和多条第二数据线222，多条第一数据线221分别位于多条第二数据线222沿第一方向X的两侧，示例性地，多条第一数据线221可以位于显示区AA的沿第一方向X的边缘区域AA2，多条第二数据线222可以位于显示区AA的沿第一方向X的中心区域AA1。一条第一数据线221与一条第一连接线12连接。第二导电层20所包括的多条第一信号线21包括多条扇出线211，一条扇出线211与一条第一连接线12电连接。多条扇出线211可以位于显示区AA的沿第一方向X的中心区域AA1，基于此，位于显示区AA的沿第一方向X的边缘区域AA2的第一数据线221，依次通过一条第一连接线12和一条扇出线211，连接至显示区AA的沿第一方向X的中心区域AA1，并从中心区域AA1的靠近周边区的边缘引出，数据线22的上述设置方式也称为显示区扇出(Fanout In AA；简称：FIAA)或者面板中扇出(Fanout In Panel；简称：FIP)。有利于降低周边区沿第二方向Y的尺寸，即降低阵列基板100的边框宽度，有利于显示装置1000实现窄边框。扇出线211设置于显示区AA的中心区域AA1，且不用于对中心区域AA1的像素电路传输数据信号，也就是说，扇出线211与位于扇出线211的靠近衬底110的一侧的像素电路电绝缘。
相关技术中，扇出线211设置于单一膜层，且在显示区AA内不与除第一连接线12之外的其他结构连接，导致产生的静电缺乏释放的途径；而且扇出线211在子像素之间延伸，需要避让像素电路中的一些导电结构，因此具有一定的图案形状，例如存在拐角或者凸起，在扇出线211的拐角或者凸起的边缘处可能会积累静电。基于上述原因，静电容易在扇出线积累，导致阵列基板的可靠性较低。
参阅图5和图6，本公开的实施例中，为了解决上述问题，多个导电图案11包括多个第一导电图案111，一条扇出线211与至少一个第一导电图案111电连接，并且在扇出线211与第一导电图案111连接的位置，形成向靠近衬底110一侧凸出的凸起结构。基于此，在扇出线211上出现静电的情况下，静电会朝向扇出线211和第一导电图案111连接的位置传输，并传输至第一导电图案111上，静电在第一导电图案111上被释放，可以提升阵列基板的可靠性。
在一些实施例中，如图5和图6所示，扇出线211包括沿第二方向Y间隔设置的多个扇出子线2111，换言之，扇出线211包括多个相互断开的扇出子线2111，相邻两个扇出子线2111之间包括一个开口2112。分别属于相邻两个扇出子线2111且相互靠近的两端，与同一个第一导电图案111电连接，即相邻两个扇出子线2111通过一个第一导电图案111电连接。这样，扇出线211在传输电流的过程中，电流可以流经每一个第一导电图案111，确保扇出线211上的静电可以传输至第一导电图案111，并经第一导电图案111被释放掉。
参阅图5和图6，第一导电图案111包括延伸部1111和两个接触部1112，延伸部1111沿第二方向Y延伸，两个接触部1112分别与延伸部1111沿第二方向Y的两端连接。相邻两个扇出子线2111之间具有开口2112，开口2112在衬底110上的正投影，与延伸部1111在衬底110上的正投影交叠，分别属于相邻两个扇出子线2111且相互靠近的两端，分别与同一个第一导电图案111的两个接触部1112电连接。接触部1112沿第一方向X的尺寸大于延伸部1111沿第一方向X的尺寸，这样，有利于降低扇出子线2111与接触部1112之间对位精度要求，降低扇出子线2111与接触部1112之间的连接难度，并且增加扇出子线2111与接触部1112之间的接触面积，降低扇出子线2111与接触部1112连接处的电阻。
在另一些实施例中，参阅图8和图9，扇出线211沿第二方向Y连续，即扇出线211上没有开口，这样，扇出线211与第一导电图案111并联设置，第一导电图案111不仅可以释放扇出线211上的静电，还可以降低扇出线211的电阻。
参阅图9、图10和图11，第一导电图案111包括沿第二方向Y交替连接的多个接触部1112和至少一个延伸部1111，接触部1112沿第一方向X的尺寸大于延伸部1111沿第一方向X的尺寸，有利于降低扇出线211与接触部1112之间对位精度要求，降低扇出线211与接触部1112之间的连接难度，并且增加扇出线211与接触部1112之间的接触面积，降低扇出线211与接触部1112连接处的电阻。扇出线211与第一导电图案111的多个接触部1112电连接，换言之，扇出线211与同一个第一导电图案111之间包括多个连接点，这样，有利于增加扇出线211与同一个第一导电图案111之间的连接可靠性和稳定性，并且有利于降低扇出线211的电阻。
示例性地，第一导电图案111沿第二方向Y的两端分别设置一个接触部1112，且相邻两个接触部1112之间通过延伸部1111连接。比如，如图10所示，第一导电图案111包括两个接触部1112和一个延伸部1111；或者，参阅图11，第一导电图案111也可以包括三个接触部1112和两个延伸部1111，第一导电图案111还可以包括其他数量的两个接触部1112和延伸部1111，只要采用相同的技术思路即可。
在一些实施例中，如图12所示，多个第一导电图案111沿第一方向X排列为多列，每列包括沿第二方向Y排列的至少一个第一导电图案111。一条扇出线211与一列的多个 第一导电图案111电连接，这样，可以增加与扇出线211连接的第一导电图案111的密度，扇出线211上任意位置上产生的静电，都可以传输至邻近的第一导电图案111上，进一步提升扇出线211的静电释放效果。可以理解的是，在图12中，为了区分第一导电图案111和第二导电图案112，两者采用的不同的填充图案，但是两者处于同一膜层，且采用同一道成膜工艺一起制备形成。
如图12所示，沿第二方向Y，多个第一导电图案111均匀排布，有利于提升第一导电图案111的均一性，并提升第一导电层10的图案均一性。像素电路120的排布密度，为第一导电图案111的排布密度的整数倍，换言之，第一导电图案111在第二方向Y上的间距(第一导电图案111的Pitch)，为像素电路120在第二方向Y上的间距(像素电路120的Pitch)的整数倍，即每整数个像素电路120的远离衬底的一侧设有一个第一导电图案111，有利于提升阵列基板100的结构的均一性，降低显示面板因第一导电图案111的分布差异出现消影问题的风险。
示例性地，如图12所示，像素电路120的排布密度，与第一导电图案111的排布密度相等。这样，可以最大程度的提升第一导电层10的图案均一性，并且最大程度提升阵列基板的结构均一性。
如图7所示，阵列基板100还包括第一电源总线VSS，第一电源总线VSS位于周边区BB，第一电源总线VSS被配置为与发光器件200的阴极电连接，即第一电源总线VSS与阴极层203电连接。第二导电层20所包括的多条第一信号线21还包括多条第一电源信号线212，沿第二方向Y，多条第一电源信号线212的至少一端与第一电源总线VSS电连接。多条第一电源信号线212沿第一方向X间隔排布，且多条第一电源信号线212均沿第二方向Y延伸，进而与阴极层电连接，多条第一电源信号线212能够降低阴极层的电阻，进而降低阴极层上的电压降，提升显示区AA的显示均匀性。采用上述电源辅助线50的设置方式也被称为SIP(VSS In Panel)技术。
如图4和图8所示，多个导电图案11还包括多个第二导电图案112，一条第一电源信号线212与至少一个第二导电图案112电连接，第一电源信号线212在与第二导电图案112连接的位置，向靠近衬底的一侧凸出形成凸起，在第一电源信号线212上出现静电的情况下，静电会聚集在第一电源信号线212的凸起位置，也就是说，静电会向第一电源信号线212与第二导电图案112的连接位置传输，并且传输至第二导电图案112上，在第二导电图案112的边缘或者端部发生尖端放电，从而将静电释放至与导电图案112接触的绝缘层中，静电的电荷通常较少，绝缘层(比如钝化层或者平坦化层)可以吸收并释放掉少量静电荷，进而将第一电源信号线212上的静电释放。可以理解的是，静电电荷较少，绝缘层虽然电绝缘，但是可以吸收静电，并且将静电释放掉。
继续参阅图4和图8，沿第二方向Y，一条第一电源信号线212与多个第二导电图案 112电连接，且多个第二导电图案112均匀排布，这样，可以增加与第一电源信号线212连接的第二导电图案112的密度，第一电源信号线212上任意位置上产生的静电，都可以传输至邻近的第二导电图案112上，进一步提升第一电源信号线212的静电释放效果。
在一些实施例中，如图4和图8所示，多个导电图案11包括多个第一导电图案111和多个第二导电图案112。多个第一导电图案111与多个第二导电图案112的结构相同，也就是说，第一导电图案111在衬底上的正投影的形状，与第二导电图案112在衬底上的正投影的形状相同，且第一导电图案111在衬底上的正投影的大小，与第二导电图案112在衬底上的正投影的大小相等。多个第一导电图案111与多个第二导电图案112的排布密度相同。这样，可以进一步提升第一导电层10的结构均一性，降低显示面板出现消影的风险。
当然，在其他一些实施例中，第一导电图案111和第二导电图案112的也可以具有差异。比如，第一导电图案111包括两个接触部1112的情况下，第二导电图案112可以包括一个或者三个或者其他数量的接触部；本公开的实施例不限于此，只要采用相同的技术思路即可。
在一些实施例中，如图4所示，在扇出线211包括沿第二方向Y间隔设置的多个扇出子线2111的情况下，第一电源信号线212也可以包括沿第二方向Y间隔设置的多个电源子线2121，且扇出子线2111的结构与电源子线2121的结构相同，也就是说，扇出子线2111在衬底上的正投影的形状和大小，分别与电源子线2121在衬底上的正投影的形状和大小对应相同。或者，如图8所示，在扇出线211沿第二方向连续的情况下，第一电源信号线212也可以沿第二方向Y连续。有利于提升第二导电层20的结构均一性。
可以理解的是，在其他一些实施例中，在扇出线211包括沿第二方向Y间隔设置的多个扇出子线2111的情况下，第一电源信号线212还可以沿第二方向Y连续。或者，在扇出线211沿第二方向连续的情况下，第一电源信号线212还可以包括沿第二方向Y间隔设置的多个电源子线，当然，本公开的实施例不限于此，只要采用相同的技术思路即可。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种阵列基板，包括：
    衬底；
    多个像素电路，设置于所述衬底上，且所述多个像素电路排列为多行和多列；
    第一导电层，包括多个导电图案，所述多个导电图案与所述多个像素电路具有间隔，所述导电图案包括至少两个间隔设置的接触部；
    第二导电层，设置于所述第一导电层远离所述衬底的一侧，包括多条第一信号线，所述多条第一信号线沿第一方向间隔排布，且均沿第二方向延伸，一条第一信号线与至少一个导电图案电连接，且所述第一信号线与所述导电图案的至少两个接触部连接；所述第一方向为所述多个像素电路排列的行方向，所述第二方向为所述多个像素电路排列的列方向。
  2. 根据权利要求1所述的阵列基板，其中，
    所述第一导电层还包括多条第一连接线，所述多条第一连接线沿所述第二方向间隔排布，且均沿所述第一方向延伸；
    所述第二导电层还包括多条数据线，一条数据线与一列像素电路电连接；所述多条数据线包括多条第一数据线和多条第二数据线，所述多条第一数据线分别位于所述多条第二数据线的两侧；一条第一数据线与一条第一连接线连接；
    所述多条第一信号线包括多条扇出线，一条扇出线与一条第一连接线电连接；
    所述多个导电图案包括多个第一导电图案，所述扇出线与至少一个第一导电图案电连接。
  3. 根据权利要求2所述的阵列基板，其中，
    所述扇出线包括沿所述第二方向间隔设置的多个扇出子线，相邻两个扇出子线的相互靠近的两端，与同一个第一导电图案电连接。
  4. 根据权利要求3所述的阵列基板，其中，
    所述第一导电图案包括延伸部和两个接触部，所述延伸部沿所述第二方向延伸，所述两个接触部分别与所述延伸部沿所述第二方向排列的两端连接，所述接触部沿所述第一方向的尺寸大于所述延伸部沿所述第一方向的尺寸；
    相邻两个扇出子线之间具有开口，相邻两个扇出子线的相互靠近的两端，分别与同一个第一导电图案的两个接触部电连接。
  5. 根据权利要求2所述的阵列基板，其中，所述扇出线沿所述第二方向连续；
    所述第一导电图案包括沿所述第二方向交替连接的多个接触部和至少一个延伸部，所述延伸部沿所述第二方向延伸，所述接触部沿所述第一方向的尺寸大于所述延伸部沿所述第一方向的尺寸；
    所述扇出线与所述第一导电图案的多个接触部电连接。
  6. 根据权利要求2所述的阵列基板，其中，所述多个第一导电图案沿所述第一方向排 列为多列，一列包括沿所述第二方向排列的至少一个第一导电图案；
    一条扇出线与一列的多个第一导电图案电连接。
  7. 根据权利要求6所述的阵列基板，其中，沿所述第二方向，所述多个第一导电图案均匀排布；且所述像素电路的排布密度，为所述第一导电图案的排布密度的整数倍。
  8. 根据权利要求1～7中任一项所述的阵列基板，其中，所述阵列基板包括显示区和围绕所述显示区的周边区，所述多个像素电路设置于所述显示区；
    所述阵列基板还包括第一电源总线，所述第一电源总线位于所述周边区，被配置为与发光器件的阴极电连接；
    所述多条第一信号线还包括多条第一电源信号线，沿所述第二方向，所述多条第一电源信号线的至少一端与所述第一电源总线电连接；
    所述多个导电图案还包括多个第二导电图案，一条第一电源信号线与至少一个第二导电图案电连接。
  9. 根据权利要求8所述的阵列基板，其中，沿所述第二方向，一条第一电源信号线与多个第二导电图案电连接，且所述多个第二导电图案均匀排布。
  10. 根据权利要求8或9所述的阵列基板，其中，所述多个导电图案还包括多个第一导电图案；所述多个第一导电图案与所述多个第二导电图案的结构相同，且所述多个第一导电图案与所述多个第二导电图案的排布密度相同。
  11. 一种显示面板，包括：
    如权利要求1～10中任一项所述的阵列基板；
    多个发光器件，设置于所述阵列基板上，且一个发光器件与所述阵列基板的一个像素电路连接。
  12. 一种显示装置，包括：
    如权利要求11所述的显示面板；
    驱动电路板，与所述显示面板电连接，被配置为向所述显示面板传输控制信号。
PCT/CN2024/122583 2023-11-30 2024-09-29 阵列基板、显示面板及显示装置 Pending WO2025112896A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637925A (zh) * 2013-11-07 2015-05-20 乐金显示有限公司 用于显示面板的阵列基板及其制造方法
CN106449664A (zh) * 2016-11-30 2017-02-22 厦门天马微电子有限公司 一种显示面板以及电子设备
CN115172431A (zh) * 2022-07-27 2022-10-11 京东方科技集团股份有限公司 一种显示面板及显示装置
CN115241236A (zh) * 2022-06-20 2022-10-25 京东方科技集团股份有限公司 显示基板及显示装置
CN116185224A (zh) * 2023-01-13 2023-05-30 昆山国显光电有限公司 触控基板、触控显示装置和触控基板的制备方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104637925A (zh) * 2013-11-07 2015-05-20 乐金显示有限公司 用于显示面板的阵列基板及其制造方法
CN106449664A (zh) * 2016-11-30 2017-02-22 厦门天马微电子有限公司 一种显示面板以及电子设备
CN115241236A (zh) * 2022-06-20 2022-10-25 京东方科技集团股份有限公司 显示基板及显示装置
CN115172431A (zh) * 2022-07-27 2022-10-11 京东方科技集团股份有限公司 一种显示面板及显示装置
CN116185224A (zh) * 2023-01-13 2023-05-30 昆山国显光电有限公司 触控基板、触控显示装置和触控基板的制备方法

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