WO2025112686A1 - 存储器的制作方法及存储器、电子设备 - Google Patents

存储器的制作方法及存储器、电子设备 Download PDF

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Publication number
WO2025112686A1
WO2025112686A1 PCT/CN2024/113355 CN2024113355W WO2025112686A1 WO 2025112686 A1 WO2025112686 A1 WO 2025112686A1 CN 2024113355 W CN2024113355 W CN 2024113355W WO 2025112686 A1 WO2025112686 A1 WO 2025112686A1
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WIPO (PCT)
Prior art keywords
trench
layer
substrate
forming
bit line
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English (en)
French (fr)
Inventor
董博闻
李辉辉
李庚霏
胡琪
王桂磊
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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Publication of WO2025112686A1 publication Critical patent/WO2025112686A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/50—Peripheral circuit region structures

Definitions

  • the present disclosure relates to the technical field of integrated circuits, and in particular to a method for manufacturing a memory, a memory, and an electronic device.
  • the present disclosure provides a method for manufacturing a memory, comprising the following steps:
  • isolation trench forming an isolation trench, wherein the isolation trench penetrates the stacked structure along a direction perpendicular to the substrate, the isolation trench extending along a first direction and dividing the stacked structure of the memory cell area into at least one strip structure extending along the first direction, wherein the first direction is parallel to the substrate;
  • first semiconductor channel covers a trench wall of the first trench
  • first gate dielectric layer covers the first semiconductor channel
  • a first word line is formed, wherein the first word line includes a first horizontal portion formed in the first trench and a first vertical portion formed in the isolation trench, wherein the first horizontal portion covers the first gate dielectric layer, the first vertical portion is vertically disposed on the substrate, and the first horizontal portion is connected to the first vertical portion.
  • forming a first trench between adjacent first sub-layers includes:
  • the strip structure exposed by the second trench is removed by etching to form the first trench, and the first trench and the first sub-layer in the middle region are alternately arranged along a direction perpendicular to the substrate.
  • forming a first semiconductor channel and a first gate dielectric layer in the first trench includes:
  • the semiconductor material layer and the gate dielectric material layer in the second trench are removed, the semiconductor material layer in the first trench forms the first semiconductor channel, and the gate dielectric material layer in the first trench forms the first gate dielectric layer.
  • forming a first word line includes:
  • first horizontal portion in the first trench, the first horizontal portion covering the first gate dielectric layer and filling the first trench, and a sidewall of the second trench exposing a portion of a surface of the first horizontal portion;
  • the first vertical portion is formed to contact the exposed surface of the first horizontal portion and fill the second trench.
  • forming the first horizontal portion in the first trench includes:
  • the first gate conductive layer covers the gate dielectric material layer and fills the first trench and the second trench;
  • the first gate conductive layer in the second trench is removed by etching, and the first gate conductive layer in the first trench is retained to form the first horizontal portion.
  • the manufacturing method comprises:
  • the first gate conductive layer, the gate dielectric material layer and the semiconductor material layer in the second trench are sequentially etched and removed to expose the second trench.
  • the manufacturing method comprises:
  • the semiconductor material layer, the gate dielectric material layer and the first gate conductive layer in the second trench are removed based on the third trench etching.
  • forming the first vertical portion includes:
  • a second gate conductive layer is formed, wherein the second gate conductive layer at least fills the second trench to form the first vertical portion.
  • the first trench and the bit line region are spaced apart by a predetermined distance.
  • a selection region is defined in the stacked structure, the memory cell region and the bit line region are arranged along the first direction, the selection region is at one end of the bit line region along a second direction, and the second direction is parallel to the substrate and intersects with the first direction; the manufacturing method further includes:
  • the bit line region is etched to remove a portion of the stacked structure in the bit line region, and a fourth trench is formed between adjacent first sub-layers in the bit line region along a direction perpendicular to the substrate, wherein the fourth trench is disposed close to the selection region.
  • the manufacturing method further comprises:
  • a second word line is formed, the second word line includes a second horizontal portion formed in the fourth trench and a second vertical portion formed in the isolation trench, the second horizontal portion covers the second gate dielectric layer and fills the fourth trench, the second vertical portion is vertically arranged on the substrate, and the second horizontal portion and the second vertical portion are connected.
  • the first sublayer is a silicon oxide layer
  • the second sublayer is a semiconductor doping layer
  • the semiconductor doping layer in the bit line region forms a bit line extending along a second direction, and the second direction is parallel to the substrate and intersects with the first direction.
  • the manufacturing method further comprises:
  • An upper electrode is formed, the upper electrode covering the dielectric layer.
  • the first sub-layer is a silicon oxide layer
  • the second sub-layer is a silicon nitride layer
  • bit line in the air layer of the bit line region, wherein the bit line extends along a second direction parallel to the substrate and intersecting with the first direction;
  • a conductor layer is formed, the conductor layer filling the area where the air layer is not filled.
  • the manufacturing method further comprises:
  • the first sub-layer is removed by etching away a portion of the first sub-layer at one end away from the bit line region, exposing the conductive layer away from the bit line region. A portion of the surface at one end of the line region;
  • An upper electrode is formed, the upper electrode covering the dielectric layer.
  • the present disclosure provides a memory in another aspect, the memory comprising:
  • the first word line comprising a first vertical portion and at least one first horizontal portion, the first vertical portion being vertically disposed on the substrate, and at least one first horizontal portion being arranged at intervals in a direction perpendicular to the substrate and connected to the first vertical portion;
  • the memory cell column comprising at least one memory cell spaced apart and arranged in a direction perpendicular to the substrate;
  • the storage cell includes a cell transistor, the first horizontal portion serves as a gate of the cell transistor, the cell transistor includes a first gate dielectric layer and a first semiconductor channel sequentially arranged in a direction away from the first horizontal portion, and the cell transistor also includes a first source/drain and a second source/drain relatively arranged on both sides of the first semiconductor channel along a first direction, and the first direction is parallel to the substrate.
  • the first semiconductor channel surrounds the first horizontal portion.
  • the first semiconductor channel includes a connection channel located on one side of the first horizontal portion in a second direction, the second direction being parallel to the substrate and intersecting the first direction.
  • the first semiconductor channel is cup-shaped, and the first semiconductor channel is disposed on the first horizontal portion.
  • the memory cell further includes a capacitor, and along the first direction, the capacitor is disposed on one side of the cell transistor, and the capacitor is connected to the first source/drain of the cell transistor.
  • the capacitor includes a lower electrode, a dielectric layer, and an upper electrode, the lower electrode is connected to the first source/drain, and the dielectric layer is disposed between the upper electrode and the lower electrode.
  • the upper electrodes of a plurality of the capacitors are connected to each other to form a closed pattern.
  • a common upper electrode plate is provided in the closed pattern, and the common upper electrode plate is connected to the upper electrode.
  • the memory further comprises:
  • At least one bit line At least one of the bit lines is arranged at intervals along a direction perpendicular to the substrate, the bit line extends along a second direction, the bit line is connected to the second source/drain of the unit transistor arranged along the second direction, and the second direction is parallel to the substrate and intersects with the first direction.
  • the memory further comprises:
  • the second word line comprising a second vertical portion and at least one second horizontal portion, the second vertical portion being vertically disposed on the substrate, and at least one second horizontal portion being arranged at intervals in a direction perpendicular to the substrate and connected to the second vertical portion;
  • At least one selection transistor at least one of the selection transistors is arranged at intervals along a direction perpendicular to the substrate, the second horizontal portion serves as a gate of the selection transistor, the selection transistor comprises a second gate dielectric layer and a second semiconductor channel sequentially arranged in a direction away from the second horizontal portion, the selection transistor further comprises a third source/drain and a fourth source/drain relatively arranged on both sides of the second semiconductor channel along the second direction; the third source/drain of the selection transistor is connected to the bit line in a one-to-one correspondence.
  • the memory further comprises:
  • At least one selection line at least one of the selection lines is arranged at intervals along a direction perpendicular to the substrate, the selection line extends along the first direction, and the selection line is connected to the fourth source/drain of the selection transistor in a one-to-one correspondence.
  • yet another aspect of the present disclosure provides an electronic device, such as the memory described in the second aspect.
  • FIG. 1 is a flow chart of a method for manufacturing a memory provided in some embodiments.
  • FIG. 2 is a flow chart of a method for manufacturing a memory provided in some embodiments.
  • FIG. 3 is a flow chart of a method for manufacturing a memory provided in some embodiments.
  • FIG. 4 is a schematic diagram of a structure in which a stacked structure is formed on a substrate in some embodiments.
  • FIG. 5 is a top view of a stacked structure in some embodiments.
  • FIG. 6 is a schematic diagram of a structure after isolation trenches are formed in some embodiments.
  • FIG. 7 is a top view after forming isolation trenches in some embodiments.
  • FIG. 8 is a schematic diagram of a structure after an isolation layer is formed in some embodiments.
  • FIG. 9 is a schematic diagram of a structure after a first sub-groove is formed in some embodiments.
  • FIG. 10 is a top view after forming a first sub-trench in some embodiments.
  • FIG. 11 is a top view after the first sub-layer of the second region is removed in some embodiments.
  • FIG. 12 is a schematic structural diagram of a second region from a viewing angle after the first sub-layer is removed in some embodiments.
  • FIG. 13 is a schematic structural diagram of a second region from a perspective after a dielectric layer is formed in some embodiments.
  • FIG. 14 is a schematic structural diagram of a second region from a viewing angle after an upper electrode is formed in some embodiments.
  • FIG. 15 is a schematic structural diagram of a second region from a perspective after a common upper electrode plate is formed in some embodiments.
  • FIG. 16 is a schematic diagram of a structure after a second trench is formed in some embodiments.
  • FIG. 17 is a cross-sectional view parallel to the substrate along line A-A in FIG. 16 after forming a second trench in some embodiments.
  • FIG. 18 is a cross-sectional view perpendicular to the substrate along line B-B and line C-C in FIG. 16 after forming a second trench in some embodiments.
  • FIG. 19 is a cross-sectional view parallel to the substrate along line A-A in FIG. 16 after forming a first trench in some embodiments.
  • FIG. 20 is a cross-sectional view perpendicular to the substrate along line B-B and line C-C in FIG. 16 after forming the first trench in some embodiments.
  • Figure 21 is a cross-sectional view perpendicular to the substrate along the B-B line and the C-C line in Figure 16 after forming a semiconductor material layer in some embodiments.
  • Figure 22 is a cross-sectional view perpendicular to the substrate along the B-B line and the C-C line in Figure 16 after the gate dielectric material layer is formed in some embodiments.
  • FIG23 is a cross-sectional view perpendicular to the substrate along line B-B and line C-C in FIG16 after forming a first gate conductive layer in some embodiments.
  • Figure 24 is a cross-sectional view perpendicular to the substrate along the B-B line and the C-C line in Figure 16 after removing the first gate conductive layer in the second trench and the fifth trench in some embodiments.
  • Figure 25 is a cross-sectional view perpendicular to the substrate along the B-B line and the C-C line in Figure 16 after removing the gate dielectric material layer in the second trench and the fifth trench in some embodiments.
  • FIG26 is a cross-sectional view perpendicular to the substrate along line B-B and line C-C in FIG16 after forming the first horizontal portion and the second horizontal portion in some embodiments.
  • FIG27 is a cross-sectional view perpendicular to the substrate along line B-B and line C-C in FIG16 after forming a second gate conductive layer in some embodiments.
  • FIG. 28 is a cross-sectional view perpendicular to the substrate along line B-B and line C-C in FIG. 16 after forming the first word line and the second word line in some embodiments.
  • FIG29 is a cross-sectional view parallel to the substrate along line A-A in FIG16 after forming the third trench and the sixth trench in some embodiments.
  • Figure 30 is a cross-sectional view perpendicular to the substrate along the B-B line and the C-C line in Figure 16 after the third trench and the sixth trench are formed in some embodiments.
  • FIG. 31 is a cross-sectional view parallel to the substrate along line AA in FIG. 16 after forming the first horizontal portion and the second horizontal portion in some embodiments.
  • 32 is a cross-sectional view perpendicular to the substrate along line B-B and line C-C in FIG. 16 after forming the first horizontal portion and the second horizontal portion in some embodiments.
  • 33 is a cross-sectional view parallel to the substrate along line A-A in FIG. 16 after forming the first word line and the second word line in some embodiments.
  • 34 is a cross-sectional view perpendicular to the substrate along line B-B and line C-C in FIG. 16 after forming the first word line and the second word line in some embodiments.
  • FIG. 35 is a schematic diagram of a structure in which a stacked structure is formed on a substrate in some embodiments.
  • FIG. 36 is a schematic diagram of the structure after the isolation trench is formed in some embodiments.
  • FIG. 37 is a schematic diagram of the structure after the first isolation layer is formed in some embodiments.
  • FIG. 38 is a top view after forming a first isolation layer in some embodiments.
  • FIG. 39 is a schematic diagram of the structure after the second sub-groove is formed in some embodiments.
  • FIG. 40 is a top view after forming a second sub-trench in some embodiments.
  • Figure 41 is a cross-sectional view perpendicular to the substrate along the D-D line in Figure 40 after the second sub-groove is formed in some embodiments.
  • Figure 42 is a cross-sectional view perpendicular to the substrate along line D-D in Figure 40 after an air layer is formed in some embodiments.
  • Figure 43 is a cross-sectional view perpendicular to the substrate along line D-D in Figure 40 after the conductor layer is formed in some embodiments.
  • FIG. 44 is a schematic diagram of the structure after a second isolation layer is formed in some embodiments.
  • Figure 45 is a cross-sectional view parallel to the substrate along the E-E line in Figure 44 after the first sub-groove is formed in some embodiments.
  • Figure 46 is a schematic diagram of the structure after removing the first sublayer of the second region in some embodiments.
  • FIG. 47 is a schematic structural diagram of a second region from a perspective after a capacitor is formed in some embodiments.
  • FIG. 48 is a schematic structural diagram of a second region from a perspective after a common upper electrode plate is formed in some embodiments.
  • Figure 49 is a cross-sectional view parallel to the substrate along the E-E line in Figure 44 after the second trench and the fifth trench are formed in some embodiments.
  • Figure 50 is a cross-sectional view parallel to the substrate along line E-E in Figure 44 after the first trench and the fourth trench are formed in some embodiments.
  • Figure 51 is a cross-sectional view parallel to the substrate along the E-E line in Figure 44 after the first horizontal portion and the second horizontal portion are formed in some embodiments.
  • Figure 52 is a schematic diagram of the structure of a memory provided in some embodiments.
  • Figure 53 is a cross-sectional view parallel to the substrate along line F-F in Figure 52 of the memory provided in some embodiments.
  • Figure 54 is a cross-sectional view perpendicular to the substrate along the G-G line and the H-H line in Figure 52 of the memory provided in some embodiments.
  • Figure 55 is a cross-sectional view perpendicular to the substrate along line I-I in Figure 52 of the memory provided in some embodiments.
  • Figure 56 is a cross-sectional view perpendicular to the substrate along the J-J line in Figure 52 of the memory provided in some embodiments.
  • Figure 57 is a cross-sectional view perpendicular to the substrate along line I-I in Figure 52 of the memory provided in some embodiments.
  • Figure 58 is a cross-sectional view perpendicular to the substrate along the J-J line in Figure 52 of the memory provided in some embodiments.
  • BL bit line
  • WL1 first word line
  • WL2, second word line HS1, first horizontal portion
  • VP1 first vertical portion
  • HS2, second horizontal portion VP2, second vertical portion
  • SUC memory cell column
  • SU memory cell
  • MCT cell transistor
  • G1 gate of cell transistor
  • ST select transistor
  • G2 gate of select transistor
  • SL select line
  • Z1 storage cell area; Z2, bit line area; Z3, selection area; A1, first area; A2, second area; A11, Middle area;
  • the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
  • spatially relative terms such as “under,” “beneath,” “below,” “under,” “above,” “above,” and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as “under other elements” or “under it” or “under it” will be oriented as being “above” the other elements or features. Thus, the exemplary terms “under” and “under” may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
  • Embodiments of the invention are described herein with reference to cross-sectional views which are schematic representations of ideal embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and/or tolerances are anticipated.
  • embodiments of the present disclosure should not be limited to the particular shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques.
  • an implanted region shown as a rectangle typically has rounded or curved features and/or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region.
  • a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed.
  • the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present disclosure.
  • FIG. 1 shows a flow chart of a method for manufacturing a memory provided according to an exemplary embodiment of the present disclosure.
  • DRAM dynamic random access memory
  • the memory in this embodiment can also be other types of memories, such as static random access memory (SRAM), flash EPROM, ferroelectric random access memory (FRAM), and magnetic random access memory (MRAM).
  • SRAM static random access memory
  • FRAM ferroelectric random access memory
  • MRAM magnetic random access memory
  • some embodiments of the present disclosure provide a method for manufacturing a memory, comprising the following steps:
  • Step S110 providing a substrate, forming a stacked structure on the substrate, the stacked structure comprising first sub-layers and second sub-layers alternately spaced, and defining a memory cell region and a bit line region in the stacked structure.
  • Step S120 forming an isolation trench, the isolation trench penetrating the stacked structure in a direction perpendicular to the substrate, the isolation trench extending along a first direction to divide the stacked structure of the storage cell area into at least one strip structure extending along the first direction, and the first direction is parallel to the substrate.
  • Step S130 etching the middle region of the strip structure to remove part of the strip structure, and forming a first groove between adjacent first sub-layers along a direction perpendicular to the substrate.
  • Step S140 forming a first semiconductor channel and a first gate dielectric layer in the first trench, wherein the first semiconductor channel covers the trench wall of the first trench, and the first gate dielectric layer covers the first semiconductor channel.
  • Step S150 forming a first word line, the first word line comprising a first horizontal portion formed in the first trench and a first vertical portion formed in the isolation trench, the first horizontal portion covers the first gate dielectric layer, the first vertical portion is vertically disposed on the substrate, and the first horizontal portion and the first vertical portion are connected.
  • the substrate 100 may be a semiconductor substrate, and the material of the semiconductor substrate may include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), indium phosphide (InP) or other III/V semiconductor materials or II/VI semiconductor materials.
  • the semiconductor substrate may be a layered substrate including Si/SiGe, Si/SiC, silicon on insulator (SOI) or silicon germanium on insulator.
  • the substrate 100 may be a single-layer structure or a multi-layer structure.
  • the stacked structure 200 includes a first sublayer 210 and a second sublayer 220 alternately stacked in a direction (third direction D3) perpendicular to the top surface of the substrate 100.
  • the first sublayer 210 is a silicon oxide layer
  • the second sublayer 220 is a semiconductor doped layer (for example, a polysilicon layer).
  • the first sublayer 210 is a silicon oxide layer
  • the second sublayer 220 is a silicon nitride layer.
  • the second sub-layer 220 of the stacked structure 200 is disposed at a position for subsequently forming a storage unit SU.
  • the top layer and the bottom layer of the stacked structure 200 are both the first sub-layer 210 .
  • a memory cell region Z1 and a bit line region Z2 are divided based on the stacked structure 200.
  • the memory cell region Z1 is used to form memory cells SU arrayed above the substrate 100, and the bit line region Z2 is used to form bit lines BL.
  • the memory cell region Z1 and the bit line region Z2 are arranged along a first direction D1. As shown in FIG5 , along the first direction D1, an independent memory cell region Z1 can be defined on each side of the bit line region Z2.
  • a mask layer (not shown in the figure) is formed on the top surface of the stacked structure 200, the patterned mask layer exposes a portion of the top surface of the stacked structure 200 of the storage cell area Z1, the stacked structure 200 exposed by the patterned mask layer is etched away, and an isolation trench 130 is formed in the stacked structure 200, the isolation trench 130 exposes a portion of the top surface of the substrate 100, the isolation trench 130 divides the stacked structure 200 of the storage cell area Z1 into a plurality of strip structures 300, the strip structures 300 extend along the first direction D1, and the plurality of strip structures 300 are arranged at intervals along the second direction D2, that is, along the second direction D2, the strip structures 300 and the isolation trenches 130 are alternately arranged.
  • the middle region A11 of the strip structure 300 can be etched based on the isolation trench 130 (refer to FIG. 6 or FIG. 36), and first trenches 121 arranged at intervals along the third direction D3 are formed in the middle region A11 of the strip structure 300.
  • the first trenches 121 are arranged parallel to the substrate 100, and the strip structures 300 around the first trenches 121 shield the first trenches 121.
  • the middle region A11 of the strip structure 300, the first sublayer 210 (refer to FIG. 20) and the first trenches 121 are alternately arranged along the third direction D3.
  • the first trench 121 and the bit line region Z2 are spaced apart by a preset distance to avoid the subsequently formed first word line and the bit line region Z2 being too close to each other, thereby avoiding affecting the electrical isolation effect between devices in the memory.
  • a first semiconductor channel 161 and a first gate dielectric layer 171 are formed in the first trench 121 (refer to Figure 19 or Figure 50), and a suitable deposition process can be used to sequentially deposit a semiconductor material layer 410 and a gate dielectric material layer 420.
  • the semiconductor material layer 410 and the gate dielectric material layer 420 are stacked to cover the trench wall of the first trench 121 and the exposed surface of the strip structure 300, the isolation trench 130, and the stacked structure 200 of the bit line area Z2.
  • the semiconductor material layer 410 and the gate dielectric material layer 420 are etched by an etching process, and the strip structure 300 blocks the groove wall of the first groove 121 (refer to FIG. 19 or FIG. 50 ), and the semiconductor material layer 410 and the gate dielectric material layer 420 in the first groove 121 are etched and retained, and the first semiconductor channel 161 and the first gate dielectric material layer 420 are formed in the first groove 121.
  • the semiconductor material layer 410 and the gate dielectric material layer 420 covering the trench wall of the first trench 121 and the exposed surface of the strip structure 300, the isolation trench 130 and the stacked structure 200 of the bit line area Z2 are all etched away, thereby ensuring that there is no residual semiconductor material layer 410 and gate dielectric material layer 420 in the area outside the first trench 121.
  • the first horizontal portion HS1 and the first vertical portion VP1 of the first word line WL1 can be formed separately in different processes.
  • the first horizontal portion HS1 can be formed in the same process step as the first semiconductor channel 161 and the first gate dielectric layer 171; then, the first vertical portion VP1 is formed in the isolation trench 130; or, in some embodiments, the first horizontal portion HS1 and the first vertical portion VP1 of the first word line WL1 can be formed in the same process step.
  • the manufacturing method of the memory disclosed in the present invention forms a first groove parallel to the substrate in a strip structure.
  • the film layer forming the first semiconductor channel and the film layer forming the first gate dielectric layer cover the first groove and the exposed surface of other structures.
  • the strip structure is used to block the groove wall of the first groove, and the film layer in the first groove is retained to form the first semiconductor channel and the first gate dielectric layer.
  • the film layer outside the first groove is completely etched and removed to avoid the residual conductive film layer outside the first groove from forming a parasitic device in the storage unit, and to avoid the parasitic device from affecting the performance of the memory.
  • the number of three-dimensional stacked layers of the memory can be further increased, and the integration density of the memory can be improved.
  • step S130 of forming a first trench between adjacent first sub-layers includes the following steps:
  • Step S131 forming an isolation layer in the isolation trench.
  • Step S132 forming a second trench in the isolation layer, wherein a side wall of the second trench exposes a portion of the surface of the middle region of the strip structure.
  • Step S133 etching and removing the strip structure exposed by the second trench to form a first trench, wherein the first trench and the first sub-layer in the middle region are alternately arranged along a direction perpendicular to the substrate.
  • any suitable deposition process may be used to form an isolation layer 230, the isolation layer 230 fills the isolation trench 130, and the material of the isolation layer 230 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride. It is understood that the isolation layer 230 may be formed by one deposition or by multiple depositions.
  • step S132 referring to FIG. 17 or FIG. 49 , a portion of the isolation layer 230 close to the strip structure 300 is removed by etching to form a second trench 221 , wherein the second trench 221 exposes a portion of the surface of the middle region A11 of the strip structure 300 .
  • step S133 referring to FIG. 19 or FIG. 50, the strip structure 300 is etched based on the second groove 221 to remove part of the structure of the middle region A11, and the first grooves 121 arranged at intervals are formed in the middle region A11 along the third direction D3, and the first grooves 121 and the first sub-layer 210 are alternately arranged along the third direction D3.
  • the first grooves 121 can be formed by a wet etching process, and an etching solution is injected into the second groove 221 to remove part of the structure of the middle region A11 by etching with the etching solution, wherein the etching solution can remove the second sub-layer 220 or other film layers formed at the original position of the second sub-layer 220.
  • the manufacturing method of the memory disclosed in the present invention forms a second groove close to the strip structure in the isolation layer, and then etches the strip structure based on the side wall of the second groove to form the first groove, thereby reducing the step of etching the stacked structure to form a hole or groove that penetrates the stacked structure, reducing the process difficulty, and can not only improve the process efficiency and reduce the process cost, but also improve the product yield.
  • step S140: forming a first semiconductor channel and a first gate dielectric layer in the first trench includes the following steps:
  • Step S141 forming a semiconductor material layer, wherein the semiconductor material layer covers the groove wall of the first groove and the groove wall of the second groove.
  • Step S142 forming a gate dielectric material layer, wherein the gate dielectric material layer covers the semiconductor material layer.
  • Step S143 removing the semiconductor material layer and the gate dielectric material layer in the second trench, the semiconductor material layer in the first trench forms a first semiconductor channel, and the gate dielectric material layer in the first trench forms a first gate dielectric layer.
  • step S141 referring to FIGS. 20 and 21 , an atomic layer deposition (ALD) process may be used to deposit and form a semiconductor material layer 410, and the semiconductor material layer 410 covers the groove walls of the first groove 121, the groove walls of the second groove 221, and the top surface of the stacked structure 200.
  • ALD atomic layer deposition
  • the semiconductor material layer 410 may be single crystal silicon or polycrystalline silicon, or an oxide semiconductor layer.
  • the material of the oxide semiconductor layer 410 may include indium gallium zinc oxide.
  • the material of the oxide semiconductor layer 410 may include at least one of the following materials: zinc tin oxide (ZTO), indium zinc oxide (IZO), indium tin oxide (ITO), doped Indium tungsten oxide (IWO), zinc oxide ( ZnOx ), indium oxide ( InOx , In2O3 ), tin oxide ( SnO2 ), titanium oxide ( TiOx ), indium zinc oxide ( InSnOx ), zinc oxynitride ( ZnxOyNz ), magnesium zinc oxide ( MgxZnyOz ), indium zinc oxide ( InxZnyOz ), indium gallium zinc oxide (InxGayZnzOa), zirconium indium zinc oxide (ZrxInyZnzOa ) , hafnium indium zinc oxide ( Hf
  • an atomic layer deposition process may be used to deposit a gate dielectric material layer 420, and the gate dielectric material layer 420 covers the semiconductor material layer 410.
  • the material of the gate dielectric material layer may include at least one of aluminum oxide ( Al2O3 ), hafnium oxide ( HfO2 ), hafnium oxynitride (HfON), zirconium oxide ( ZrO2 ), tantalum oxide ( Ta2O5 ), titanium oxide ( TiO2 ), strontium titanium oxide ( SrTiO3 ), hafnium silicate (HfSiO), zirconium silicate (ZrSiO), and strontium silicate (SrSiO); or, the material of the gate dielectric material layer may include at least one of hafnium silicate nitride (HfSiON), zirconium silicate nitride (ZrSiON), and zirconium silicate nitride (SrSi
  • step S143 in some examples, referring to FIGS. 24 , 25 , and 26 , the gate dielectric material layer 420 and the semiconductor material layer 410 in the second trench 221 are removed sequentially from the center of the second trench 221 toward the trench wall.
  • a third trench 321 is formed on the periphery of the second trench 221 to expose the semiconductor material layer 410 in the second trench 221 , and the semiconductor material layer 410 and the gate dielectric material layer 420 in the second trench 221 are removed sequentially from the wall of the second trench 221 toward the center.
  • step S150 forming a first word line, includes the following steps:
  • Step S151 forming a first horizontal portion in the first trench, the first horizontal portion covers the first gate dielectric layer and fills the first trench, and a sidewall of the second trench exposes a portion of the surface of the first horizontal portion.
  • Step S152 forming a first vertical portion, the first vertical portion contacting the exposed surface of the first horizontal portion and filling the second trench.
  • step S151 a first horizontal portion is formed in the first trench, including the following steps:
  • Step S1511 forming a first gate conductive layer, the first gate conductive layer covers the gate dielectric material layer and fills the first trench and the second trench.
  • the first gate conductive layer 430 may be formed by depositing any deposition process including a chemical vapor deposition process (CVD), an atomic layer deposition process or sputtering, and the first gate conductive layer 430 fills the unfilled areas of the second trench 221 and the first trench 121.
  • CVD chemical vapor deposition process
  • atomic layer deposition process or sputtering
  • Step S1512 etching and removing the first gate conductive layer in the second trench, retaining the first gate conductive layer in the first trench, and forming a first horizontal portion.
  • This step may be performed before step S143 or after step S143.
  • the first gate conductive layer 430 , the gate dielectric material layer 420 , and the semiconductor material layer 410 in the second trench 221 may be sequentially etched away to expose the second trench 221 .
  • a portion of the isolation layer 230 around the second trench 221 is first etched away to form a third trench 321, wherein the third trench 321 exposes the semiconductor material layer 410 in the second trench 221; then, the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 are etched away based on the third trench 321.
  • a first vertical portion VP1 is formed, including: forming a second gate conductive layer 440 , wherein the second gate conductive layer 440 at least fills the second trench 221 to form the first vertical portion VP1 .
  • the material of the first gate conductive layer 430 and the material of the second gate conductive layer 440 may be selected from at least one of titanium or a titanium compound, tantalum or a tantalum compound, tungsten or a tungsten compound, and copper or a copper compound.
  • the materials of the first gate conductive layer 430 and the second gate conductive layer 440 may be the same or different.
  • a selection region Z3 is defined in the stacked structure 200, the memory cell region Z1 and the bit line region Z2 are arranged along a first direction D1, and the selection region Z3 is at one end of the bit line region Z2 along a second direction D2, and the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1.
  • the method for manufacturing a memory further includes the following steps:
  • the bit line region Z2 is etched to remove part of the stacked structure 200 in the bit line region Z2, and a fourth trench 421 is formed between adjacent first sub-layers 210 in the bit line region Z2 along a direction perpendicular to the substrate 100, and the fourth trench 421 is arranged near the selection region Z3.
  • the above steps can be performed simultaneously with step S130.
  • a part of the isolation layer 230 near the selection region Z3 is etched to form a fifth trench 521, and the fifth trench 521 exposes part of the stacked structure 200 in the bit line region Z2.
  • the stacked structure 200 in the bit line region Z2 is etched based on the fifth trench 521, and a fourth trench 421 is formed in the bit line region Z2.
  • the second semiconductor channel 261 and the second gate dielectric layer 271 are formed in the fourth trench 421.
  • the second semiconductor channel 261 covers the groove wall of the fourth trench 421, and the second gate dielectric layer 271 covers the second semiconductor channel 261.
  • the second word line WL2 is formed at the same time as the first word line WL1 is formed.
  • the second word line WL2 includes a second horizontal portion HS2 formed in the fourth trench 421 and a second vertical portion VP2 formed in the isolation trench 130.
  • the second horizontal portion HS2 covers the second gate dielectric layer 271 and fills the fourth trench 421.
  • the second vertical portion VP2 is vertically arranged on the substrate 100, and the second horizontal portion HS2 is connected to the second vertical portion VP2.
  • FIG2 shows a flow chart of the method for manufacturing a memory provided according to some embodiments of the present disclosure
  • FIG4-FIG34 are schematic diagrams of various stages of the method for manufacturing a memory.
  • the method for manufacturing a memory is introduced below in conjunction with FIG4-FIG34 and FIG52-FIG56.
  • the method for manufacturing a memory includes the following steps:
  • Step S210 Provide a substrate and form a stacked structure on the substrate, the stacked structure including alternating first sub-layers and second sub-layers, defining a memory cell region, a bit line region and a selection region in the stacked structure, the memory cell region and the bit line region are arranged along a first direction, and the selection region is at one end of the bit line region along a second direction.
  • the substrate 100 of this embodiment is the same as the substrate 100 in step S110 , and will not be described again herein.
  • the stacked structure 200 includes a first sublayer 210 and a second sublayer 220 alternately stacked along a third direction D3, the first sublayer 210 is a silicon oxide layer, the second sublayer 220 is a semiconductor doping layer, the semiconductor doping layer is a conductively doped polysilicon layer, and the semiconductor doping layer may have a P-type conductivity type or an N-type conductivity type.
  • the top layer and the bottom layer of the stacked structure 200 are both the first sublayer 210.
  • the stacked structure 200 is formed on the substrate 100, and the following implementation methods may be adopted:
  • a chemical vapor deposition process, an atomic layer deposition process or a sputtering process may be used to alternately deposit silicon oxide layers and semiconductor doping layers, and the cycle may be repeated several times to form a stacked structure 200.
  • the silicon oxide layers and semiconductor doping layers of the stacked structure 200 may be alternately stacked in multiple layers.
  • the stacked structure 200 is laid out according to the structure of the memory to be formed, and a memory cell area Z1, a bit line area Z2, and a selection area Z3 are defined on the stacked structure 200.
  • a memory cell area Z1 is defined on both sides of the bit line area Z2 along the first direction D1
  • a selection area Z3 is defined at one end of the bit line area Z2 along the second direction D2.
  • the first direction D1 is parallel to the substrate 100
  • the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1.
  • Step S220 forming an isolation trench, the isolation trench penetrating the stacked structure in a direction perpendicular to the substrate, the isolation trench extending along a first direction and dividing the stacked structure of the storage cell area into at least one strip structure extending along the first direction, the semiconductor doping layer in the bit line area forms a bit line extending along the second direction, and the semiconductor doping layer in the selection area forms a selection line extending along the first direction.
  • a first mask layer (not shown in the figures) is formed on the top surface of the stacked structure 200, the first mask layer exposes part of the top surface of the stacked structure 200 of the memory cell area Z1 and part of the top surface of the stacked structure 200 of the selection area Z3, the stacked structure 200 exposed by the mask layer is etched away to form an isolation trench 130, the isolation trench 130 divides the stacked structure 200 of the memory cell area Z1 into strip structures 300 extending along the first direction D1 and arranged at intervals along the second direction D2, and at the same time, the retained second sublayer 220 of the bit line area Z2 (hereinafter collectively referred to as the semiconductor doping layer) is directly formed into a bit line BL extending along the second direction D2 and arranged at intervals along the third direction D3 (refer to Figure 33), the retained semiconductor doping layer is directly formed into a selection line SL extending along the first direction D1 and arranged at intervals along the third direction D3
  • Step S230 forming an isolation layer in the isolation trench.
  • any one of the chemical vapor deposition process or the atomic layer deposition process can be selected.
  • a deposition process is used to deposit and form the isolation layer 230, which fills the isolation trench 130.
  • the material of the isolation layer 230 may include at least one of silicon oxide, silicon nitride or silicon oxynitride.
  • Step S240 forming a capacitor at one end of the memory cell region away from the bit line region.
  • a capacitor is formed at one end of the memory cell region away from the bit line region, comprising the following steps:
  • Step S241 etching and removing a portion of the first sub-layer at one end away from the bit line region, exposing a portion of the surface of the semiconductor doped layer at one end away from the bit line region.
  • the etching process may be performed to remove a portion of the first sub-layer 210 away from an end of the bit line region Z2 by the following steps:
  • the strip structure 300 in the memory cell region Z1 defines a first region A1 and a second region A2 (refer to FIG. 11) arranged in sequence away from the bit line region Z2.
  • the first region A1 is close to the bit line region Z2, and the second region A2 is away from the bit line region Z2.
  • a second mask layer (not shown in the figures) is formed on the top surface of the structure, and the second mask layer exposes the top surface of the isolation layer 230 connected to the second area A2.
  • the isolation layer 230 is etched based on the second mask layer to remove the isolation layer 230 connected to the second area A2, exposing a portion of the isolation trench 130 away from the bit line area Z2.
  • the isolation trench 130 exposed in this step is defined as a first sub-groove 131, and the first sub-groove 131 exposes the surface of the strip structure 300 of the second area A2.
  • the strip structure 300 is etched based on the first sub-groove 131 to remove the first sub-layer 210 (hereinafter collectively referred to as the silicon oxide layer) in the second area A2 to expose the surface of the semiconductor doping layer in the second area A2.
  • the silicon oxide layer in the second area A2 may be removed by etching using a dry process or a wet process.
  • Step S242 forming a dielectric layer, wherein the dielectric layer covers the exposed surface of the semiconductor doping layer.
  • a dielectric layer 610 is deposited by an atomic layer deposition process, and the dielectric layer 610 uniformly covers the exposed surface of the semiconductor doping layer in the second area A2.
  • the material of the dielectric layer 610 may include at least one of strontium titanate ( SrTiO3 ), aluminum oxide ( Al2O3 ), zirconium oxide (ZrO) or hafnium oxide ( HfO2 ).
  • Step S243 forming an upper electrode, wherein the upper electrode covers the dielectric layer.
  • an upper electrode 620 can be deposited by an atomic layer deposition process.
  • the upper electrode 620 covers the surface of the dielectric layer 610.
  • the material of the upper electrode 620 may include a high melting point metal, such as at least one of cobalt (Co), titanium (Ti), nickel (Ni), tungsten (W) and/or molybdenum (Mo); or, the material of the upper electrode 620 may also include a metal nitride, such as titanium nitride, titanium silicon nitride, titanium aluminum nitride, tantalum nitride, tantalum silicon nitride, tantalum aluminum nitride, and/or tungsten nitride.
  • the semiconductor doped layer covered by the dielectric layer 610 i.e., the semiconductor doped layer of the second region A2
  • the dielectric layer 610 and the upper electrode 620 form a capacitor 600 at one end of the storage cell region Z1 away from the bit line region Z2 (i.e., the second region A2)
  • the semiconductor doped layer covered by the dielectric layer 610 i.e., the semiconductor doped layer of the second region A2 serves as the lower electrode 630 of the capacitor 600.
  • step S243 the following steps are further performed after step S243:
  • Step S244 forming a common upper electrode plate, which covers the upper electrode and fills the unfilled areas between the semiconductor doping layers and the unfilled areas in the first sub-trench.
  • a common upper electrode 640 can be formed by any deposition process including a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or sputtering, and the common upper electrode 640 covers the surface of the upper electrode 620 of each capacitor 600 and fills the unfilled area between the semiconductor doping layers of the second area A2 and the unfilled area in the first sub-groove 131.
  • the material of the common upper plate 640 may include a semiconductor material doped with conductive ions or a conductive metal.
  • the material of the common upper plate 640 may include single crystal silicon or polycrystalline silicon, and the material of the common upper plate 640 may also include at least one of metal tungsten, cobalt, titanium and/or nickel. In this way, the area of the memory can be fully utilized and the storage capacity of the memory can be increased.
  • Step S250 forming a second trench in the isolation layer, a sidewall of the second trench exposing a portion of the surface of the middle region of the strip structure, and forming a fifth trench in the isolation layer, a sidewall of the fifth trench exposing a portion of the surface of the stacked structure of the bit line region.
  • a third mask layer (not shown in the figures) is formed on the top surface of the structure, the third mask layer defines the pattern of the second trench 221 and the fifth trench 521 , and the third mask layer is removed by etching to expose the isolation layer 230 .
  • the second trench 221 and the fifth trench 521 are formed respectively, the second trench 221 is arranged in the memory cell area Z1 (refer to FIG. 5 ), and the second trench 221 exposes a part of the surface of the middle area A11 of the strip structure 300.
  • the middle area A11 of the strip structure 300 refers to the middle area A11 of the first area A1 (refer to FIG. 11 ).
  • the fifth trench 521 is arranged close to the selection area Z3 (refer to FIG. 5 ), and the fifth trench 521 exposes a part of the surface of the stacked structure 200 of the bit line area Z2.
  • Step S260 Etch the middle area of the strip structure to remove part of the strip structure, and form a first groove between adjacent first sub-layers along a direction perpendicular to the substrate. At the same time, etch the bit line area to remove part of the stacked structure in the bit line area, and form a fourth groove between adjacent first sub-layers in the bit line area along a direction perpendicular to the substrate. The fourth groove is arranged close to the selection area.
  • the stacked structure 200 can be etched by a wet process to etch away the semiconductor doped layer exposed by the second trench 221, and a first trench 121 is formed in the middle area A11 of the first area A1 (refer to Figure 11).
  • the first trench 121 is connected to the second trench 221, and the first trench 121 divides the semiconductor doped layer of the storage cell area Z1 into two sections independently arranged on both sides of the first trench 121 along the first direction D1.
  • the semiconductor doped layer located on the left side of the first trench 121 serves as the first source/drain 181 of the cell transistor MCT in the subsequently formed storage cell SU, and the semiconductor doped layer located on the right side of the first trench 121 serves as the second source/drain 182 of the cell transistor MCT in the subsequently formed storage cell SU.
  • the first source/drain 181 is connected to the capacitor 600
  • the second source/drain 182 is connected to the bit line BL.
  • the semiconductor doping layer exposed by the fifth trench 521 is etched away, and a fourth trench 421 is formed in the middle area A11 of the bit line region Z2.
  • the fourth trench 421 is connected to the fifth trench 521, and the fourth trench 421 divides the semiconductor doping layer of the bit line region Z2 into two sections independently arranged on both sides of the fourth trench 421 along the second direction D2.
  • the portion close to the bit line BL serves as the third source/drain 281 of the selection transistor ST formed subsequently
  • the portion close to the selection region Z3 serves as the fourth source/drain 282 of the selection transistor ST formed subsequently. It can be seen that the third source/drain 281 is connected to the bit line BL, and the fourth source/drain 282 is connected to the selection line SL.
  • Step S270 A first semiconductor channel and a first gate dielectric layer are formed in the first trench, wherein the first semiconductor channel covers the trench wall of the first trench, and the first gate dielectric layer covers the first semiconductor channel. Meanwhile, a second semiconductor channel and a second gate dielectric layer are formed in the fourth trench, wherein the second semiconductor channel covers the trench wall of the fourth trench, and the second gate dielectric layer covers the second semiconductor channel.
  • the following implementation manner can be adopted, as shown in Figures 21, 22 and 23, to sequentially form a semiconductor material layer 410, a gate dielectric material layer 420 and a first gate conductive layer 430, the semiconductor material layer 410 covers the groove wall of the first groove 121, the groove wall of the second groove 221, the groove wall of the fourth groove 421 and the groove wall of the fifth groove 521, the gate dielectric material layer 420 covers the semiconductor material layer 410, and the first gate conductive layer 430 covers the gate dielectric material layer 420 and fills the unfilled area of the first groove 121, the unfilled area of the second groove 221, the unfilled area of the fourth groove 421 and the unfilled area of the fifth groove 521.
  • the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 and the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the fifth trench 521 are etched away, the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the first trench 121 are retained, and the first semiconductor channel 161, the first gate dielectric layer 171 and the first horizontal portion HS1 of the first word line WL1 are respectively formed, and the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the fourth trench 421 are retained, and the second semiconductor channel 261, the second gate dielectric layer 271 and the second horizontal portion HS2 of the second word line WL2 are respectively formed.
  • the semiconductor material layer 410 , the gate dielectric material layer 420 , and the first gate conductive layer 430 in the second trench 221 and the fifth trench 521 are removed by using the following implementations:
  • the first gate conductive layer 430 in the second trench 221 is removed by wet etching, and the first gate conductive layer 430 in the fifth trench 521 is removed at the same time, exposing the gate dielectric material layer 420 in the second trench 221 and the fifth trench 521.
  • the gate dielectric material layer 420 in the second trench 221 is removed by wet etching, and the gate dielectric material layer 420 in the fifth trench 521 is removed at the same time, exposing the semiconductor material layer 410 in the second trench 221 and the fifth trench 521.
  • the semiconductor material layer 410 in the second trench 221 is removed by wet etching, and the semiconductor material layer 410 in the fifth trench 521 is removed at the same time.
  • the layer 410 exposes the second trench 221 and the fifth trench 521 .
  • the first gate conductive layer 430, the gate dielectric material layer 420 and the semiconductor material layer 410 are removed layer by layer from the center of the trench to the trench wall.
  • the process is simple, the process steps are streamlined, the process time can be saved, and the process cost can be reduced.
  • the semiconductor material layer 410 , the gate dielectric material layer 420 , and the first gate conductive layer 430 in the second trench 221 and the fifth trench 521 are removed by using the following implementations:
  • a portion of the isolation layer 230 around the second trench 221 is etched away to form a third trench 321, which exposes the semiconductor material layer 410 located in the second trench 221.
  • a portion of the isolation layer 230 around the fifth trench 521 is etched away to form a sixth trench 621, which exposes the semiconductor material layer 410 located in the sixth trench 621.
  • a fourth mask layer can be formed on the top surface of the structure, the fourth mask layer exposes a portion of the top surface of the isolation layer 230 around the second trench 221 and a portion of the top surface of the isolation layer 230 around the fifth trench 521, and the isolation layer 230 exposed by the fourth trench 421 is etched away to form a third trench 321 around the second trench 221, and a sixth trench 621 is formed around the fifth trench 521.
  • the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 are removed layer by layer by etching based on the third trench 321, and the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the fifth trench 521 are removed layer by layer by etching based on the sixth trench 621.
  • the semiconductor material layer 410, the gate dielectric material layer 420 and the first gate conductive layer 430 in the second trench 221 and the fifth trench 521 can be removed layer by layer by using a wet process.
  • the film layer in the second trench 221 and the fifth trench 521 is etched from the trench wall to the center, which can ensure that the semiconductor material layer 410 in the second trench 221 and the fifth trench 521 is completely etched and removed, and the residual semiconductor material layer 410 in the second trench 221 or the fifth trench 521 is prevented from forming a parasitic device in the memory, thereby further improving the performance and quality of the memory.
  • the third trench 321 is formed outside the second trench 221, which can increase the size of the first vertical portion VP1 formed subsequently, and reduce the resistance of the first word line WL1; similarly, this embodiment can also reduce the resistance of the second word line WL2.
  • Step S280 forming a first word line and forming a second word line at the same time.
  • the first word line WL1 includes a first horizontal portion HS1 formed in the first trench 121 and a first vertical portion VP1 formed in the isolation trench 130, the first horizontal portion HS1 covers the first gate dielectric layer 171, the first vertical portion VP1 is vertically arranged on the substrate 100 and fills the second trench 221, and the first horizontal portion HS1 and the first vertical portion VP1 are connected.
  • the second word line WL2 includes a second horizontal portion HS2 formed in the fourth trench 421 and a second vertical portion VP2 formed in the isolation trench 130, the second horizontal portion HS2 covers the second gate dielectric layer 271, the second vertical portion VP2 is vertically arranged on the substrate 100 and fills the fifth trench 521, and the second horizontal portion HS2 is connected to the second vertical portion VP2.
  • the first horizontal portion HS1 of the first word line WL1 and the first horizontal portion HS1 of the second word line WL2 have been formed in step S270 , and only the first vertical portion VP1 of the first word line WL1 and the second vertical portion VP2 of the second word line WL2 need to be formed.
  • a second gate conductive layer 440 may be formed by deposition using any one of chemical vapor deposition, atomic layer deposition, physical vapor deposition or sputtering processes.
  • the second gate conductive layer 440 fills the second trench 221 and the fifth trench 521 , respectively. It is understandable that, in an embodiment of forming the third trench 321 and the sixth trench 621 , the second gate conductive layer 440 also fills the third trench 321 and the sixth trench 621 .
  • the second gate conductive layer 440 covering the top surface of the structure is removed by etching, and the second gate conductive layer 440 in the second trench 221 forms a first vertical portion VP1, and the first vertical portion VP1 covers the first horizontal portion HS1 and the first horizontal portion HS1 together form a first word line WL1.
  • the second gate conductive layer 440 in the second trench 221 and the third trench 321 together form the first vertical portion VP1.
  • the second gate conductive layer 440 in the fifth trench 521 forms a second vertical portion VP2, which covers the second horizontal portion HS2 and together forms a second word line WL2.
  • the second gate conductive layer 440 in the fifth trench 521 and the sixth trench 621 together forms a second vertical portion VP2.
  • the manufacturing method of the memory of this embodiment forms a three-dimensional structure based on a stacked structure formed by silicon oxide and a semiconductor doping layer.
  • the conductive ions in the semiconductor doping layer are activated by in-situ doping to make the semiconductor
  • the doped layer is conductive, so after the isolation trench is formed, the semiconductor doped layer in the bit line area directly forms the bit line, and the semiconductor doped layer in the selection area forms the selection line. There is no need to perform the step of replacing the conductive material, thereby improving the process efficiency.
  • the manufacturing method of the memory of the present embodiment forms the second trench and the fifth trench in the isolation layer, reducing the steps of etching the stacked structure; at the same time, the stacked structure is used to protect the first trench and the fourth trench, and the semiconductor material layer, the gate dielectric material layer and the first gate conductive layer in the second trench and the fifth trench are removed from the inside to the outside or from the outside to the inside, so as to avoid the residual conductive material to form parasitic devices and avoid the parasitic devices affecting the performance of the memory, which can further increase the number of three-dimensional stacked layers of the memory and improve the integration density of the memory.
  • the manufacturing method of the memory of this embodiment has a transistor with a lower off-state current formed in the memory, which can reduce the leakage of the memory, which is beneficial to reducing the power consumption of the memory, reducing the size of the device in the memory, and improving the array density of the device in the memory.
  • FIG3 shows a flow chart of the method for manufacturing a memory provided according to some embodiments of the present disclosure
  • FIG35-FIG53 are schematic diagrams of various stages of the method for manufacturing a memory.
  • the method for manufacturing a memory is introduced below in conjunction with FIG35-FIG53 and with reference to FIG52, FIG57, and FIG58.
  • the method for manufacturing a memory includes the following steps:
  • Step S310 Provide a substrate and form a stacked structure on the substrate, the stacked structure including alternating first sub-layers and second sub-layers, defining a memory cell region, a bit line region and a selection region in the stacked structure, the memory cell region and the bit line region are arranged along a first direction, and the selection region is at one end of the bit line region along a second direction.
  • the stacked structure 200 includes first sublayers 210 and second sublayers 220 alternately stacked along a third direction D3, wherein the first sublayer 210 is a silicon oxide layer and the second sublayer 220 is a silicon nitride layer.
  • the top and bottom layers of the stacked structure 200 are both first sublayers 210 (i.e., silicon oxide layers).
  • the stacked structure 200 is formed on the substrate 100, and the following implementation methods may be adopted:
  • a chemical vapor deposition process, an atomic layer deposition process or a sputtering process may be used to alternately deposit silicon oxide layers and silicon nitride layers, and the cycle may be repeated several times to form a stacked structure 200.
  • the silicon oxide layers and silicon nitride layers of the stacked structure 200 may be alternately stacked in 2 to 1024 layers or more.
  • the silicon oxide layers and silicon nitride layers may be alternately stacked in 48 layers, 64 layers, 128 layers, 256 layers or 512 layers, etc.
  • the stacked structure 200 is laid out according to the structure of the memory to be formed, and a memory cell area Z1, a bit line area Z2 and a selection area Z3 are defined on the stacked structure 200.
  • a memory cell area Z1 is defined on both sides of the bit line area Z2 along the first direction D1
  • a selection area Z3 is defined at one end of the bit line area Z2 along the second direction D2.
  • the first direction D1 is parallel to the substrate 100
  • the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1.
  • Step S320 forming an isolation trench, wherein the isolation trench vertically penetrates the stacked structure, and the isolation trench extends along a first direction to divide the stacked structure of the memory cell area into at least one strip structure extending along the first direction.
  • the implementation method of forming the isolation trench is the same as that of step S220 in the above embodiment, and will not be described again.
  • the stacked structure 200 includes alternating silicon oxide layers and silicon nitride layers. Therefore, after the isolation trench 130 is formed, the stacked structure 200 in which the bit line area Z2 is retained extends along the second direction D2, and the stacked structure 200 in which the selection area Z3 is retained extends along the first direction D1.
  • Step S330 etching and removing the entire second sub-layer, and forming an air layer in the area where the second sub-layer is removed.
  • etching to remove the entire second sub-layer includes the following steps:
  • Step S331 forming a first isolation layer, wherein the first isolation layer fills a portion of the isolation trench.
  • a chemical vapor deposition process or a physical vapor deposition process may be selected to deposit the first isolation layer 231 , and the material of the first isolation layer 231 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.
  • Step S332 etching and removing a portion of the first isolation layer to form a second sub-trench in the isolation trench, wherein the second sub-trench exposes a portion of the sidewall of the stacked structure.
  • the strip structure 300 in the memory cell region Z1 defines a first region A1 and a second region A2 arranged in sequence away from the bit line region Z2 , wherein the first region A1 is close to the bit line region Z2 and the second region A2 is away from the bit line region Z2 .
  • a fifth mask layer (not shown in the figure) is formed on the top surface of the structure.
  • the fifth mask layer exposes a portion of the top surface of the first isolation layer 231, and the first isolation layer 231 exposed by the fifth mask layer is etched away to expose a portion of the isolation trench 130.
  • the isolation trench 130 exposed in this step is defined as a second sub-trench 132, and the second sub-trench 132 exposes a portion of the side wall of the stacked structure 200 in the first area A1.
  • the retained first isolation layer 231 is used to support the architecture of the stacked structure 200.
  • Step S333 removing the entire second sub-layer based on the second sub-trench etching.
  • an etching solution is injected into the second sub-groove 132.
  • the etching solution can be a phosphoric acid solution.
  • the entire second sub-layer 220 that is, the silicon nitride layer, hereinafter collectively referred to as the silicon nitride layer
  • the entire silicon nitride layer is removed, and an air layer 240 is formed at the original position of the silicon nitride layer.
  • the silicon oxide layer and the air layer 240 are alternately arranged.
  • Step S340 forming a bit line in the air layer of the bit line region, wherein the bit line extends along a second direction, and the second direction is parallel to the substrate and intersects with the first direction.
  • the bit line BL is formed in the air layer 240 of the bit line region Z2 by the following implementation:
  • an atomic layer deposition process or a chemical vapor deposition process may be used to deposit a conductive metal material layer, and the conductive metal material layer fills the air layer 240 and a portion of the second sub-trench 132. Then, the conductive metal material layer outside the bit line region Z2 is removed by etching, and the conductive metal material layer in the air layer 240 of the bit line region Z2 is retained to form the bit line BL, which extends along the second direction D2 and is arranged at intervals along the third direction D3.
  • the material of the bit line BL may include at least one of titanium or titanium compounds, tantalum or tantalum compounds, tungsten or tungsten compounds, and copper or copper compounds; in some embodiments, the material of the bit line BL includes metal tungsten, so that the resistance of the bit line BL is smaller and the conductivity is better.
  • Step S350 forming a conductor layer, where the conductor layer fills the area not filled by the air layer.
  • an atomic layer deposition process or a chemical vapor deposition process may be used to deposit the material of the conductor layer 250 to fill the area where the air layer is not filled and the second sub-groove 132, and then the material of the conductor layer in the second sub-groove 132 is removed by etching, and a conductor layer 250 is formed in the area where the air layer 240 is not filled.
  • the conductor layer 250 of the selection zone Z3 forms selection lines SL, and the selection lines SL extend along the first direction D1 and are arranged at intervals along the third direction D3.
  • the material of the conductor layer 250 may include titanium or a titanium compound, tantalum or a tantalum compound. In some embodiments, the material of the conductor layer 250 includes titanium nitride.
  • a second isolation layer 232 is then filled in the second sub-trench 132 .
  • Step S360 forming a capacitor at one end of the memory cell region away from the bit line region.
  • forming a capacitor at one end of the memory cell region away from the bit line region comprises the following steps:
  • Step S361 etching and removing a portion of the first sub-layer away from one end of the bit line region, exposing a portion of the surface of the conductor layer away from the end of the bit line region.
  • a second mask layer (not shown in the figure) is formed on the top surface of the structure, and the second mask layer exposes the top surface of the first isolation layer 231 connected to the second area A2.
  • the first isolation layer 231 connected to the second area A2 is removed by etching based on the second mask layer to form a first sub-groove 131 connected to the second area A2, and the sidewalls of the first sub-groove 131 expose part of the surface of the silicon oxide layer and the conductor layer 250 of the second area A2.
  • the silicon oxide layer in the second area A2 is removed by etching based on the first sub-trench 131 , exposing the surface of the conductor layer 250 in the second area A2 .
  • Step S362 forming a dielectric layer, wherein the dielectric layer covers the surface exposed by the conductor layer.
  • a dielectric layer 610 is deposited by an atomic layer deposition process, and the dielectric layer 610 uniformly covers the exposed surface of the semiconductor doping layer in the second area A2.
  • the material of the dielectric layer 610 is the same as the material of the dielectric layer 610 formed in step S242 in the above embodiment, and will not be repeated here.
  • Step S363 forming an upper electrode, wherein the upper electrode covers the dielectric layer.
  • an upper electrode 620 may be formed by deposition using an atomic layer deposition process.
  • the upper electrode 620 covers the surface of the dielectric layer 610 .
  • the material of the upper electrode 620 is the same as the material used to form the upper electrode 620 in step S243 in the above embodiment, and will not be described again herein.
  • the conductive layer 250 covered by the dielectric layer 610 (i.e., the conductive layer 250 of the second region A2), the dielectric layer 610 and the upper electrode 620 form a capacitor 600 at one end of the storage cell region Z1 away from the bit line region Z2 (i.e., the second region A2), and the conductive layer 250 covered by the dielectric layer 610 (i.e., the conductive layer 250 of the second region A2) serves as the lower electrode 630 of the capacitor 600.
  • step S363 the following steps are further performed after step S363:
  • Step S364 forming a common upper electrode plate, which covers the upper electrode and fills the unfilled areas between the conductor layers 250 and the unfilled areas in the first sub-grooves.
  • the process of forming the common upper electrode plate 640 and the material and selection of the common upper electrode plate 640 are the same as those of S244 in the above-mentioned embodiment and will not be described in detail herein.
  • Step S370 forming a second trench, wherein the second trench exposes a portion of the sidewall of the first region, and forming a fifth trench, wherein a sidewall of the fifth trench exposes a portion of the sidewall of the bit line region.
  • a third mask layer (not shown in the figure) is formed on the top surface of the structure, and the third mask layer defines the pattern of the second groove 221 and the fifth groove 521.
  • the third mask layer is etched and removed to expose the first isolation layer 231 and the second isolation layer 232, thereby forming the second groove 221 and the fifth groove 521, respectively.
  • the second trench 221 and the bit line region Z2 are spaced apart by a predetermined distance.
  • the second trench 221 is disposed close to the strip structure 300 and exposes a portion of the sidewall of the strip structure 300 .
  • the fifth trench 521 is spaced apart from the selection area Z3 by a predetermined distance, and the fifth trench 521 is disposed close to the stack of the bit line area Z2 and exposes a portion of the sidewall of the stack of the bit line area Z2.
  • Step S380 Etch the middle area of the strip structure to remove part of the strip structure, and form a first groove between adjacent first sub-layers along a direction perpendicular to the substrate. At the same time, etch the bit line area to remove part of the stacked structure in the bit line area, and form a fourth groove between adjacent first sub-layers in the bit line area along a direction perpendicular to the substrate. The fourth groove is arranged close to the selection area.
  • the strip structure 300 is etched based on the second trench 221, and the conductor layer 250 exposed by the second trench 221 is etched away to form the first trench 121.
  • the first trench 121 divides the conductor layer 250 of the storage cell area Z1 into two sections independently arranged on both sides of the first trench 121 along the first direction D1.
  • the conductor layer 250 located on the left side of the first trench 121 serves as the first source/drain 181 of the unit transistor MCT in the storage cell SU to be formed subsequently, and the conductor layer 250 located on the right side of the first trench 121 serves as the second source/drain 182 of the unit transistor MCT in the storage cell SU to be formed subsequently.
  • the first source/drain 181 is connected to the capacitor 600, and the second source/drain 182 is connected to the bit line.
  • the bit line region Z2 is etched based on the fifth trench 521, and the conductive metal material layer exposed by the fifth trench 521 is removed to form a fourth trench 421.
  • the fourth trench 421 divides the conductive metal material layer of the bit line region Z2 into two sections independently arranged on both sides of the fourth trench 421 along the second direction D2, wherein the portion away from the selection line SL serves as the third source/drain 281 of the selection transistor ST formed subsequently, and the portion close to the selection region Z3 serves as the fourth source/drain 282 of the selection transistor ST formed subsequently. It can be seen that the third source/drain 281 is connected to the bit line BL, and the fourth source/drain 282 is connected to the selection line SL.
  • Step S390 A first semiconductor channel and a first gate dielectric layer are formed in the first trench, wherein the first semiconductor channel covers the trench wall of the first trench, and the first gate dielectric layer covers the first semiconductor channel. Meanwhile, a second semiconductor channel and a second gate dielectric layer are formed in the fourth trench, wherein the second semiconductor channel covers the trench wall of the fourth trench, and the second gate dielectric layer covers the second semiconductor channel.
  • Step S400 forming a first word line and forming a second word line at the same time.
  • step S390 and step S400 in some embodiments are the same as those of step S270 and step S280 in the above-mentioned embodiments, and will not be repeated here.
  • the method for manufacturing the memory of this embodiment can form a three-dimensional memory based on a stacked structure formed by silicon oxide and silicon nitride layers, or can form a three-dimensional memory based on a stacked structure formed by silicon oxide and semiconductor doping layers.
  • the method for manufacturing the memory has a wide range of applications.
  • a memory is provided, referring to FIGS. 52, 55, 56, 57, and 58, and to FIGS. 33 and 53, the memory includes a substrate 100, at least one first word line WL1, and at least one column of memory cell columns SUC;
  • the first word line WL1 includes a first vertical portion VP1 and at least one first horizontal portion HS1, the first vertical portion VP1 is vertically arranged on the substrate 100, and the at least one first horizontal portion HS1 is arranged at intervals in a direction perpendicular to the substrate 100 and connected to the first vertical portion VP1;
  • at least one column of memory cell columns SUC the memory cell column SUC includes at least one memory cell SU arranged at intervals in a direction perpendicular to the substrate 100;
  • the memory cell SU includes a cell transistor MCT, the first horizontal portion HS1 serves as a gate G1 of the cell transistor MCT, and the cell transistor MCT includes a first horizontal portion HS1 disposed along a direction away from the first
  • the cell transistor MCT further comprises a first source/drain 181 and a second source/drain 182 which are arranged on both sides of the first semiconductor channel 161 along the first direction D1, and the first direction D1 is parallel to the substrate 100.
  • the memory has no conductive film layer remaining in the process and no parasitic devices, which can improve the response speed of the semiconductor structure, avoid response delay, and improve the yield and electrical performance of the semiconductor structure.
  • the first word line WL1 includes a first vertical portion VP1 and at least one first horizontal portion HS1.
  • the first horizontal portion HS1 serves as the gate G1 of the cell transistor MCT.
  • the first horizontal portion HS is not limited by the length of the first vertical portion VP1 of the first word line WL1.
  • the first horizontal portion HS can increase the length of the gate G1 of the cell transistor MCT, thereby enhancing the control capability of the gate G1 of the cell transistor MCT.
  • the first semiconductor channel 161 at the position of the first horizontal portion HS1 can be protected to avoid damage to the first semiconductor channel 161 at the position of the first horizontal portion HS1 when removing the parasitic channel.
  • the first semiconductor channel 161 surrounds the first horizontal portion HS1 , and such a configuration can enhance the control capability of the gate G1 of the cell transistor MCT.
  • the first semiconductor channel 161 includes a connecting channel 1611, which is located on one side of the first horizontal portion HS1 in the second direction D2.
  • the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1. This configuration allows the first semiconductor channel 161 to further cover the first horizontal portion HS1, further enhancing the control capability of the gate G1 of the unit transistor MCT.
  • the first semiconductor channel 161 is cup-shaped, and the first semiconductor channel 161 is sleeved on the first horizontal portion HS1 .
  • first horizontal portion HS1 is connected to the first vertical portion VP1, and the entire outer peripheral surface of the first horizontal portion HS1 is covered by the first semiconductor channel 161 except for the area connected to the first vertical portion VP1.
  • the cross-sectional view of the first horizontal portion HS1 along the direction parallel to the substrate 100 is a square or a rectangle
  • the side surface of one side of the first horizontal portion HS1 is connected to the first vertical portion VP1
  • the remaining five surfaces of the first horizontal portion HS1 are covered by the first semiconductor channel 161.
  • the first semiconductor channel 161 covers a larger area of the first horizontal portion HS1, and the control capability of the gate G1 of the unit transistor MCT is greater.
  • the storage unit SU also includes a semiconductor doping layer 220a, the semiconductor doping layer 220a includes two sections arranged on both sides of the first semiconductor channel 161 relatively along the first direction D1, and the first source/drain 181 and the second source/drain 182 are respectively arranged in the semiconductor doping layer 220a on both sides of the first semiconductor channel 161.
  • the storage unit SU also includes a conductor layer 250, the conductor layer 250 includes two sections arranged on both sides of the first semiconductor channel 161 relatively along the first direction D1, and the first source/drain 181 and the second source/drain 182 are respectively arranged in the conductor layer 250 on both sides of the first semiconductor channel 161.
  • the storage unit SU further includes a memory device for storing data.
  • the memory device for storing data may be a capacitor 600 or a magnetic tunnel junction or a phase change element.
  • the storage unit SU further includes a capacitor 600 , which is disposed on one side of the cell transistor MCT along the first direction D1 , and is connected to the first source/drain 181 of the cell transistor MCT.
  • the capacitor 600 includes a lower electrode 630, a dielectric layer 610, and an upper electrode 620, wherein the lower electrode 630 is connected to the first source/drain 181, and the dielectric layer 610 is disposed between the upper electrode 620 and the lower electrode 630.
  • the dielectric layer 610 covers the lower electrode 630, and the upper electrode 620 covers the dielectric layer 610.
  • the lower electrode 630 of the capacitor 600 is disposed in the semiconductor doping layer 220a, the lower electrode 630 of the capacitor 600 and the first source/drain 181 are disposed on the same side, the first source/drain 181 is disposed close to the first semiconductor channel 161, and the lower electrode 630 of the capacitor 600 is disposed away from the first semiconductor channel 161.
  • the lower electrode 630 of the capacitor 600 is disposed in the conductive layer 250. Similarly, the lower electrode 630 of the capacitor 600 and the first source/drain 181 are disposed on the same side, the first source/drain 181 is disposed close to the first semiconductor channel 161, and the lower electrode 630 of the capacitor 600 is disposed away from the first semiconductor channel 161.
  • the upper electrodes 620 of multiple capacitors 600 are interconnected to form a closed pattern.
  • Such a configuration can increase the relative area of the upper electrode 620 and the lower electrode 630, thereby increasing the capacitance.
  • a common upper electrode plate 640 is provided in a closed pattern, and the common upper electrode plate 640 is connected to the upper electrode 620.
  • Such a configuration can increase the volume ratio of the capacitor 600 in the memory and increase the storage capacitance of the memory.
  • the memory also includes at least one bit line BL, the bit lines BL are arranged at intervals in a direction perpendicular to the substrate 100, the bit lines BL extend along a second direction D2, the bit lines BL are connected to second sources/drains of a plurality of unit transistors MCT arranged along the second direction D2, the second direction D2 is parallel to the substrate 100 and intersects with the first direction D1, and the bit lines BL are used to perform a read or write operation on the storage unit SU where the unit transistor MCT is located when the unit transistor MCT is turned on.
  • the memory also includes a second word line WL2, the second word line WL2 includes a second vertical portion VP2 and at least one second horizontal portion HS2, the second vertical portion VP2 is vertically arranged on the substrate 100, and the at least one second horizontal portion HS2 is arranged at intervals in a direction perpendicular to the substrate 100 and connected to the second vertical portion VP2.
  • the memory further includes at least one selection transistor ST, which is arranged at intervals along a direction perpendicular to the substrate 100, and the second horizontal portion HS2 serves as a gate G2 of the selection transistor ST.
  • the selection transistor ST includes a second gate dielectric layer 271 and a second semiconductor channel 261 sequentially arranged in a direction away from the second horizontal portion HS2, and the selection transistor ST further includes a third source/drain 281 and a fourth source/drain 282 relatively arranged on both sides of the second semiconductor channel 261 along the second direction D2; the third source/drain 281 of the selection transistor ST and the bit line BL are connected one-to-one.
  • the memory further includes at least one selection line SL, at least one selection line SL is arranged at intervals in a direction perpendicular to the substrate 100, the selection line SL extends in the first direction D1, and the selection line SL is connected to the fourth source/drain 282 of the selection transistor ST in a one-to-one correspondence.
  • the selection line SL is used to provide a voltage to the selection transistor ST, and control the conduction or cutoff of the selection transistor ST through the voltage, and then control the memory unit SU connected thereto through the bit line BL.
  • an electronic device comprising the memory in the above embodiment.
  • the electronic device may be a storage device, a mobile phone, a computer, a tablet computer, a television, an artificial intelligence device, etc.

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Abstract

本公开涉及一种存储器的制作方法及存储器、电子设备，涉及集成电路技术领域。为了在有限的衬底上做出尽可能多的器件单元，存储器的制作方法包括：在衬底（100）上形成第一子层（210）与第二子层（210）交替的叠层结构（200）；形成隔离沟槽（130）将叠层结构（200）划分成条形结构（300）；沿垂直于衬底（100）的方向，在相邻的第一子层（210）之间形成第一沟槽（121）；利用条形结构（300）对第一沟槽（121）的槽壁形成遮挡，于第一沟槽（121）中形成第一半导体沟道（161）和第一栅介质层（171），将第一沟槽（121）以外的膜层全部刻蚀去除，避免第一沟槽（121）以外残留的导电膜层形成寄生器件影响存储器的性能，能够提高存储器的三维堆叠的层数、提升集成密度。

Description

存储器的制作方法及存储器、电子设备
相关申请的交叉引用
本公开要求2023年12月01日申请的，申请号为202311640776.5，名称为“存储器的制作方法及存储器、电子设备”的中国专利申请的优先权，的中国专利申请的优先权，所述专利申请的全部内容通过引用结合在本公开中。
技术领域
本公开涉及集成电路技术领域，特别是涉及一种存储器的制作方法及存储器、电子设备。
背景技术
随着集成电路技术的发展，器件的关键尺寸日益缩小，单个芯片所包含的器件种类及数量随之增加，使得工艺生产中的任何微小差异都可能对器件性能造成影响。
为了尽可能降低产品的成本，人们希望在有限的衬底上做出尽可能多的器件单元。自从摩尔定律问世以来，业界提出了各种半导体结构设计和工艺优化，以满足人们对当前产品的需求。
发明内容
根据一些实施例，本公开一方面提供了一种存储器的制作方法，包括以下步骤：
提供衬底，在所述衬底上形成叠层结构，所述叠层结构包括交替堆叠的第一子层和第二子层，在所述叠层结构定义存储单元区和位线区；
形成隔离沟槽，所述隔离沟槽沿垂直于所述衬底的方向贯穿所述叠层结构，所述隔离沟槽沿第一方向延伸、将所述存储单元区的所述叠层结构划分成至少一个沿所述第一方向延伸的条形结构，所述第一方向平行于所述衬底；
刻蚀所述条形结构的中间区域，去除部分所述条形结构，沿垂直于所述衬底的方向，在相邻的所述第一子层之间形成第一沟槽；
于所述第一沟槽中形成第一半导体沟道和第一栅介质层，所述第一半导体沟道覆盖所述第一沟槽的槽壁，所述第一栅介质层覆盖所述第一半导体沟道；
形成第一字线，所述第一字线包括形成在所述第一沟槽中的第一水平部以及形成在所述隔离沟槽中的第一竖直部，所述第一水平部覆盖所述第一栅介质层，所述第一竖直部垂直设置在所述衬底上，所述第一水平部和所述第一竖直部相连。
根据一些实施例，在相邻的所述第一子层之间形成第一沟槽，包括：
于所述隔离沟槽中形成隔离层；
在所述隔离层中形成第二沟槽，所述第二沟槽的一侧壁暴露出所述条形结构的中间区域的部分表面；
刻蚀去除所述第二沟槽暴露出的所述条形结构，形成所述第一沟槽，所述中间区域的所述第一沟槽和所述第一子层沿垂直于所述衬底的方向交替设置。
根据一些实施例，于所述第一沟槽中形成第一半导体沟道和第一栅介质层，包括：
形成半导体材料层，所述半导体材料层覆盖所述第一沟槽的槽壁和所述第二沟槽的槽壁；
形成栅介质材料层，所述栅介质材料层覆盖所述半导体材料层；
去除所述第二沟槽中的所述半导体材料层和所述栅介质材料层，所述第一沟槽中的所述半导体材料层形成所述第一半导体沟道，所述第一沟槽中的所述栅介质材料层形成所述第一栅介质层。
根据一些实施例，形成第一字线，包括：
于所述第一沟槽中形成所述第一水平部，所述第一水平部覆盖所述第一栅介质层并填充所述第一沟槽，所述第二沟槽的一侧壁暴露出所述第一水平部的部分表面；
形成所述第一竖直部，所述第一竖直部接触所述第一水平部的暴露的表面并填充所述第二沟槽。
根据一些实施例，于所述第一沟槽中形成所述第一水平部，包括：
形成栅介质材料层之后，形成第一栅导电层，所述第一栅导电层覆盖所述栅介质材料层并填充所述第一沟槽和所述第二沟槽；
刻蚀去除所述第二沟槽中的所述第一栅导电层，保留所述第一沟槽中的所述第一栅导电层，形成所述第一水平部。
根据一些实施例，所述制作方法，包括：
依次刻蚀去除所述第二沟槽中的所述第一栅导电层、所述栅介质材料层和所述半导体材料层，暴露出所述第二沟槽。
根据一些实施例，所述制作方法，包括：
刻蚀去除所述第二沟槽的周围的部分所述隔离层，形成第三沟槽，所述第三沟槽暴露出位于所述第二沟槽中的所述半导体材料层；
基于所述第三沟槽刻蚀去除所述第二沟槽中的所述半导体材料层、所述栅介质材料层和所述第一栅导电层。
根据一些实施例，形成所述第一竖直部，包括：
形成第二栅导电层，所述第二栅导电层至少填充所述第二沟槽，形成所述第一竖直部。
根据一些实施例，沿所述第一方向，所述第一沟槽和所述位线区间隔预设距离。
根据一些实施例，在所述叠层结构定义选择区，所述存储单元区和所述位线区沿所述第一方向排列，所述选择区沿第二方向在所述位线区的一端，所述第二方向平行于所述衬底且与所述第一方向相交；所述制作方法，还包括：
刻蚀所述位线区，去除所述位线区的部分所述叠层结构，沿垂直于所述衬底的方向，在所述位线区中相邻的所述第一子层之间形成第四沟槽，所述第四沟槽靠近所述选择区设置。
根据一些实施例，所述制作方法，还包括：
于所述第一沟槽中形成所述第一半导体沟道和所述第一栅介质层的同时，于所述第四沟槽中形成第二半导体沟道和第二栅介质层，所述第二半导体沟道覆盖所述第四沟槽的槽壁，所述第二栅介质层覆盖所述第二半导体沟道；
形成所述第一字线的同时，形成第二字线，所述第二字线包括形成在所述第四沟槽的第二水平部以及形成在所述隔离沟槽的第二竖直部，所述第二水平部覆盖所述第二栅介质层并填充所述第四沟槽，所述第二竖直部垂直设置在所述衬底上，所述第二水平部和所述第二竖直部相连。
根据一些实施例，所述第一子层为氧化硅层，所述第二子层为半导体掺杂层，形成所述隔离沟槽之后，所述位线区的所述半导体掺杂层形成沿第二方向延伸的位线，所述第二方向平行于所述衬底且与所述第一方向相交。
根据一些实施例，所述制作方法，还包括：
刻蚀去除远离所述位线区的一端的部分所述第一子层，暴露出所述半导体掺杂层远离所述位线区的一端的部分表面；
形成介电层，所述介电层覆盖所述半导体掺杂层的暴露的表面；
形成上电极，所述上电极覆盖所述介电层。
根据一些实施例，所述第一子层为氧化硅层，所述第二子层为氮化硅层；于所述存储单元区形成隔离沟槽之后，所述制作方法包括：
刻蚀去除全部的所述第二子层，在所述第二子层被去除的区域形成空气层；
于所述位线区的所述空气层中形成位线，所述位线沿第二方向延伸，所述第二方向平行于所述衬底且与所述第一方向相交；
形成导体层，所述导体层填充所述空气层未被填充的区域。
根据一些实施例，所述制作方法，还包括：
刻蚀去除远离所述位线区的一端的部分所述第一子层，暴露出所述导体层远离所述位 线区的一端的部分表面；
形成介电层，所述介电层覆盖所述导体层的暴露的表面；
形成上电极，所述上电极覆盖所述介电层。
根据一些实施例，本公开另一方面提供了一种存储器，所述存储器包括：
衬底；
至少一条第一字线，所述第一字线包括第一竖直部以及至少一个第一水平部，所述第一竖直部垂直设置在所述衬底上，至少一个所述第一水平部沿垂直于所述衬底的方向间隔排列并与所述第一竖直部连接；
至少一列存储单元列，所述存储单元列包括沿垂直于所述衬底的方向间隔排列的至少一个存储单元；
所述存储单元包括单元晶体管，所述第一水平部作为所述单元晶体管的栅极，所述单元晶体管包括沿远离所述第一水平部的方向依次设置的第一栅介质层和第一半导体沟道，所述单元晶体管还包括沿第一方向相对设置在所述第一半导体沟道两侧的第一源/漏极和第二源/漏极，所述第一方向平行于所述衬底。
根据一些实施例，在平行于所述第一方向且垂直于所述衬底的平面中，所述第一半导体沟道环绕所述第一水平部。
根据一些实施例，所述第一半导体沟道包括连接沟道，连接沟道位于所述第一水平部在第二方向的一侧，所述第二方向平行于所述衬底且与所述第一方向相交。
根据一些实施例，所述第一半导体沟道为杯状，所述第一半导体沟道套设在所述第一水平部上。
根据一些实施例，所述存储单元还包括电容器，沿所述第一方向，所述电容器设置在所述单元晶体管的一侧，所述电容器和所述单元晶体管的所述第一源/漏极相连。
根据一些实施例，所述电容器包括下电极、介电层和上电极，所述下电极与所述第一源/漏极相连，所述介电层设置在所述上电极和所述下电极之间。
根据一些实施例，在平行于所述衬底的平面中，多个所述电容器的所述上电极相互连接，形成封闭图形。
根据一些实施例，在所述封闭图形内具有共用上极板，共用上极板与所述上电极连接。
根据一些实施例，所述存储器还包括：
至少一条位线，至少一条所述位线沿垂直于所述衬底的方向间隔排列，所述位线沿第二方向延伸，所述位线和沿所述第二方向排列的所述单元晶体管的所述第二源/漏极相连，所述第二方向平行于所述衬底且与所述第一方向相交。
根据一些实施例，所述存储器还包括：
第二字线，所述第二字线包括第二竖直部以及至少一个第二水平部，所述第二竖直部垂直设置在所述衬底上，至少一个所述第二水平部沿垂直于所述衬底的方向间隔排列并与所述第二竖直部连接；
至少一个选择晶体管，至少一个所述选择晶体管沿垂直于所述衬底的方向间隔排列，所述第二水平部作为所述选择晶体管的栅极，所述选择晶体管包括沿远离所述第二水平部的方向依次设置的第二栅介质层和第二半导体沟道，所述选择晶体管还包括沿所述第二方向相对设置在所述第二半导体沟道两侧的第三源/漏极和第四源/漏极；所述选择晶体管的所述第三源/漏极和所述位线一一对应连接。
根据一些实施例，所述存储器还包括：
至少一条选择线，至少一条所述选择线沿垂直于所述衬底的方向间隔排列，所述选择线沿所述第一方向延伸，且所述选择线和所述选择晶体管的所述第四源/漏极一一对应连接。
根据一些实施例，本公开又一方面提供了一种电子设备，如第二方面所述的存储器。
本公开的一个或多个实施例的细节在下面的附图和描述中提出。本公开的其他特征、目的和优点将从说明书、附图以及权利要求书变得明显。
附图说明
为了更清楚地说明本公开实施例或传统技术中的技术方案，下面将对实施例或传统技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为一些实施例中提供的存储器的制作方法的流程图。
图2为一些实施例中提供的存储器的制作方法的流程图。
图3为一些实施例中提供的存储器的制作方法的流程图。
图4为一些实施例中在衬底上形成叠层结构的结构示意图。
图5为一些实施例中叠层结构的俯视图。
图6为一些实施例中形成隔离沟槽之后的结构示意图。
图7为一些实施例中形成隔离沟槽之后的俯视图。
图8为一些实施例中形成隔离层之后的结构示意图。
图9为一些实施例中形成第一子沟槽之后的结构示意图。
图10为一些实施例中形成第一子沟槽之后的俯视图。
图11为一些实施例中去除第二区域的第一子层之后的俯视图。
图12为一些实施例中去除第一子层之后的第二区域的一视角的结构示意图。
图13为一些实施例中形成介电层之后的第二区域的一视角的结构示意图。
图14为一些实施例中形成上电极之后的第二区域的一视角的结构示意图。
图15为一些实施例中形成共用上极板之后的第二区域的一视角的结构示意图。
图16为一些实施例中形成第二沟槽之后的结构示意图。
图17为一些实施例中形成第二沟槽之后沿图16中A-A线的平行于衬底的剖面图。
图18为一些实施例中形成第二沟槽之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图19为一些实施例中形成第一沟槽之后沿图16中A-A线的平行于衬底的剖面图。
图20为一些实施例中形成第一沟槽之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图21为一些实施例中形成半导体材料层之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图22为一些实施例中形成栅介质材料层之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图23为一些实施例中形成第一栅导电层之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图24为一些实施例中去除第二沟槽和第五沟槽中的第一栅导电层之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图25为一些实施例中去除第二沟槽和第五沟槽中的栅介质材料层之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图26为一些实施例中形成第一水平部和第二水平部之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图27为一些实施例中形成第二栅导电层之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图28为一些实施例中形成第一字线和第二字线之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图29为一些实施例中形成第三沟槽和第六沟槽之后沿图16中A-A线的平行于衬底的剖面图。
图30为一些实施例中形成第三沟槽和第六沟槽之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图31为一些实施例中形成第一水平部和第二水平部之后沿图16中A-A线的平行于衬底的剖面图。
图32为一些实施例中形成第一水平部和第二水平部之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图33为一些实施例中形成第一字线和第二字线之后沿图16中A-A线的平行于衬底的剖面图。
图34为一些实施例中形成第一字线和第二字线之后沿图16中B-B线和C-C线的垂直于衬底的剖面图。
图35为一些实施例中在衬底上形成叠层结构的结构示意图。
图36为一些实施例中形成隔离沟槽之后的结构示意图。
图37为一些实施例中形成第一隔离层之后的结构示意图。
图38为一些实施例中形成第一隔离层之后的俯视图。
图39为一些实施例中形成第二子沟槽之后的结构示意图。
图40为一些实施例中形成第二子沟槽之后的俯视图。
图41为一些实施例中形成第二子沟槽之后的沿图40中D-D线的垂直于衬底的剖面图。
图42为一些实施例中形成空气层之后的沿图40中D-D线的垂直于衬底的剖面图。
图43为一些实施例中形成导体层之后的沿图40中D-D线的垂直于衬底的剖面图。
图44为一些实施例中形成第二隔离层之后的结构示意图。
图45为一些实施例中形成第一子沟槽之后的沿图44中E-E线的平行于衬底的剖面图。
图46为一些实施例中去除第二区域的第一子层之后的结构示意图。
图47为一些实施例中形成电容器之后第二区域的一视角的结构示意图。
图48为一些实施例中形成共用上极板之后第二区域的一视角的结构示意图。
图49为一些实施例中形成第二沟槽和第五沟槽之后的沿图44中E-E线的平行于衬底的剖面图。
图50为一些实施例中形成第一沟槽和第四沟槽之后的沿图44中E-E线的平行于衬底的剖面图。
图51为一些实施例中形成第一水平部和第二水平部之后的沿图44中E-E线的平行于衬底的剖面图。
图52为一些实施例中提供的存储器的结构示意图。
图53为一些实施例中提供的存储器的沿图52中F-F线的平行于衬底的剖面图。
图54为一些实施例中提供的存储器的沿图52中G-G线、H-H线的垂直于衬底的剖面图。
图55为一些实施例中提供的存储器的沿图52中I-I线的垂直于衬底的剖面图。
图56为一些实施例中提供的存储器的沿图52中J-J线的垂直于衬底的剖面图。
图57为一些实施例中提供的存储器的沿图52中I-I线的垂直于衬底的剖面图。
图58为一些实施例中提供的存储器的沿图52中J-J线的垂直于衬底的剖面图。
附图标记说明：
100、衬底；130、隔离沟槽；131、第一子沟槽；132、第二子沟槽；200、叠层结构；210、第一子层；220、第二子层；220a、半导体掺杂层；230、隔离层；231、第一隔离层；232、第二隔离层；240、空气层；250、导体层；300、条形结构；410、半导体材料层；420、栅介质材料层；430、第一栅导电层；440、第二栅导电层；121、第一沟槽；221、第二沟槽；321、第三沟槽；421、第四沟槽；521、第五沟槽；621、第六沟槽；161、第一半导体沟道；1611、连接沟道；171、第一栅介质层；261、第二半导体沟道；271、第二栅介质层；181、第一源/漏极；182、第二源/漏极；281、第三源/漏极；282、第四源/漏极；600、电容器；610、介电层；620、上电极；630、下电极；640、共用上极板；
BL、位线；WL1、第一字线；WL2、第二字线；HS1、第一水平部；VP1、第一竖直部；HS2、第二水平部；VP2、第二竖直部；SUC、存储单元列；SU、存储单元；MCT、单元晶体管；G1、单元晶体管的栅极；ST、选择晶体管；G2、选择晶体管的栅极；SL、选择线；
Z1、存储单元区；Z2、位线区；Z3、选择区；A1、第一区域；A2、第二区域；A11、 中间区域；
D1、第一方向；D2、第二方向；D3、第三方向。
具体实施方式
为了便于理解本公开，下面将参照相关附图对本公开进行更全面的描述。附图中给出了本公开的首选实施例。但是，本公开可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本公开的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本公开的技术领域的技术人员通常理解的含义相同。本文中在本公开的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本公开。
应当明白，当元件或层被称为“在...上”、“与...相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在...上”、“与...直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层、掺杂类型和/或部分，这些元件、部件、区、层、掺杂类型和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层、掺杂类型或部分与另一个元件、部件、区、层、掺杂类型或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层、掺杂类型或部分可表示为第二元件、部件、区、层或部分；举例来说，可以将第一掺杂类型成为第二掺杂类型，且类似地，可以将第二掺杂类型成为第一掺杂类型；第一掺杂类型与第二掺杂类型为不同的掺杂类型，譬如，第一掺杂类型可以为P型且第二掺杂类型可以为N型，或第一掺杂类型可以为N型且第二掺杂类型可以为P型。
空间关系术语例如“在...下”、“在...下面”、“下面的”、“在...之下”、“在...之上”、“上面的”等，在这里可以用于描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在...下面”和“在...下”可包括上和下两个取向。此外，器件也可以包括另外地取向(譬如，旋转90度或其它取向)，并且在此使用的空间描述语相应地被解释。
在此使用时，单数形式的“一”、“一个”和“所述/该”也可以包括复数形式，除非上下文清楚指出另外的方式。还应明白，当术语“组成”和/或“包括”在该说明书中使用时，可以确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。同时，在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
这里参考作为本公开的理想实施例(和中间结构)的示意图的横截面图来描述发明的实施例，这样可以预期由于例如制造技术和/或容差导致的所示形状的变化。因此，本公开的实施例不应当局限于在此所示的区的特定形状，而是包括由于例如制造技术导致的形状偏差。例如，显示为矩形的注入区在其边缘通常具有圆的或弯曲特征和/或注入浓度梯度，而不是从注入区到非注入区的二元改变。同样，通过注入形成的埋藏区可导致该埋藏区和注入进行时所经过的表面之间的区中的一些注入。因此，图中显示的区实质上是示意性的，它们的形状并不表示器件的区的实际形状，且并不限定本公开的范围。
本公开示例性的实施例中提供一种存储器的制作方法，如图1所示，图1示出了根据本公开一示例性的实施例提供的存储器的制作方法的流程图，本实施例对半导体结构不作限制，下面将以存储器为动态随机存储器(Dynamic Random Access Memory，DRAM)为例进行介绍，但本实施例并不以此为限，本实施例中的存储器还可以为其他类型的存储器，比如静态随机存取存储器(Static Random-Access Memory，SRAM)、快闪存储器(flash EPROM)、铁电存储器(Ferroelectric Random Access Memory，FRAM)、磁性随机存取存储器(Magnetic Random-Access Memory，MRAM)。
如图1所示，本公开一些实施例提供的一种存储器的制作方法，包括如下的步骤：
步骤S110：提供衬底，在衬底上形成叠层结构，叠层结构包括间隔交替的第一子层和第二子层，在叠层结构定义存储单元区和位线区。
步骤S120：形成隔离沟槽，隔离沟槽沿垂直于衬底的方向贯穿叠层结构，隔离沟槽沿第一方向延伸、将存储单元区的叠层结构划分成至少一个沿第一方向延伸的条形结构，第一方向平行于衬底。
步骤S130：刻蚀条形结构的中间区域，去除部分条形结构，沿垂直于衬底的方向，在相邻的第一子层之间形成第一沟槽。
步骤S140：于第一沟槽中形成第一半导体沟道和第一栅介质层，第一半导体沟道覆盖第一沟槽的槽壁，第一栅介质层覆盖第一半导体沟道。
步骤S150：形成第一字线，第一字线包括形成在第一沟槽中的第一水平部以及形成在隔离沟槽中的第一竖直部，第一水平部覆盖第一栅介质层，第一竖直部垂直设置在衬底上，第一水平部和第一竖直部相连。
在步骤S110中，参照图4或参照图35，衬底100可以为半导体衬底，半导体衬底的材料可以包括硅(Si)、硅锗(SiGe)、硅锗碳(SiGeC)、碳化硅(SiC)、砷化镓(GaAs)、砷化铟(InAs)、磷化铟(InP)或其它的III/V半导体材料或II/VI半导体材料。或者，还例如，半导体衬底可以是包括诸如Si/SiGe、Si/SiC、绝缘体上硅(SOI)或绝缘体上硅锗的层状衬底。衬底100可以为单层结构或多层结构。
参照图4或参照图35，叠层结构200包括沿垂直于衬底100的顶面的方向(第三方向D3)交替堆叠的第一子层210和第二子层220。在一些实施例中，参照图4，第一子层210为氧化硅层，第二子层220为半导体掺杂层(比如可以为多晶硅层)。在另一些实施例中，参照图35，第一子层210为氧化硅层，第二子层220为氮化硅层。
其中，叠层结构200的第二子层220设置的位置用于后续形成存储单元SU，本实施例中，叠层结构200的顶层和底层均为第一子层210。
参照图5，基于叠层结构200上划分出存储单元区Z1和位线区Z2，存储单元区Z1用于形成在衬底100上方阵列的存储单元SU，位线区Z2用于形成位线BL，存储单元区Z1和位线区Z2沿第一方向D1排列，参照图5所示，沿第一方向D1，可以在位线区Z2的两侧各自定义一独立的存储单元区Z1。
在步骤S120中，参照图5、图6、图7或参照图36，在叠层结构200的顶面形成掩膜层(图中未示出)，图形化掩膜层暴露出存储单元区Z1的叠层结构200的部分顶面，刻蚀去除被图形化后的掩膜层暴露出的叠层结构200，在叠层结构200中形成隔离沟槽130，隔离沟槽130暴露出衬底100的部分顶面，隔离沟槽130将存储单元区Z1的叠层结构200划分成多个条形结构300，条形结构300沿第一方向D1延伸，多个条形结构300沿第二方向D2间隔设置，也即沿第二方向D2，条形结构300和隔离沟槽130交替设置。
在步骤S130中，参照图17、图19、图20或图50，可以基于隔离沟槽130(参照图6或图36)刻蚀条形结构300的中间区域A11，在条形结构300的中间区域A11形成沿第三方向D3间隔排列的第一沟槽121，第一沟槽121平行于衬底100设置，第一沟槽121周围的条形结构300对第一沟槽121形成遮挡。形成第一沟槽121之后，沿第三方向D3，条形结构300的中间区域A11，第一子层210(参照图20)和第一沟槽121交替设置。
一些实施例中，沿第一方向D1，第一沟槽121和位线区Z2间隔预设距离，避免后续形成的第一字线和位线区Z2的距离过近，避免影响存储器中器件之间的电隔离效果。
在步骤S140中，参照图20-图26，或参照图29-图32，或参照图51，于第一沟槽121(参照图19或图50)中形成第一半导体沟道161和第一栅介质层171，可以采用合适的沉积工艺依次沉积形成半导体材料层410和栅介质材料层420，半导体材料层410和栅介质材料层420层叠覆盖第一沟槽121的槽壁以及条形结构300、隔离沟槽130以及位线区Z2的叠层结构200的暴露的表面。
然后，采用刻蚀工艺刻蚀半导体材料层410和栅介质材料层420，条形结构300对第一沟槽121(参照图19或图50)的槽壁形成遮挡，第一沟槽121中的半导体材料层410和栅介质材料层420被刻蚀保留，在第一沟槽121中形成第一半导体沟道161和第一栅介 质层171，而覆盖在第一沟槽121的槽壁以及条形结构300、隔离沟槽130以及位线区Z2的叠层结构200的暴露的表面的半导体材料层410和栅介质材料层420全部被刻蚀去除，从而确保第一沟槽121以外的区域没有残留的半导体材料层410和栅介质材料层420。
在步骤S150中，参照图27、图28、图33、图34、图52、图53，第一字线WL1的第一水平部HS1和第一竖直部VP1可以在不同的制程中分别形成，比如，第一水平部HS1可以和第一半导体沟道161、第一栅介质层171在同一制程步骤中形成；然后，在隔离沟槽130中形成第一竖直部VP1；或者，在一些实施例中，第一字线WL1的第一水平部HS1和第一竖直部VP1可以在同一制程步骤中形成。
本公开的存储器的制作方法，在条形结构中形成平行于衬底设置的第一沟槽，在制作第一半导体沟道和第一栅介质层的过程中，形成第一半导体沟道的膜层和形成第一栅介质层的膜层覆盖第一沟槽以及其他的结构的暴露的表面，利用条形结构对第一沟槽的槽壁形成遮挡，保留第一沟槽中的膜层形成第一半导体沟道和第一栅介质层，将第一沟槽以外的膜层全部刻蚀去除，避免第一沟槽以外存在残留的导电膜层在存储单元中形成寄生器件，避免寄生器件影响存储器的性能，可进一步提高存储器的三维堆叠的层数，提升存储器的集成密度。
在一些实施例中：步骤S130在相邻的第一子层之间形成第一沟槽，包括以下步骤：
步骤S131：于隔离沟槽中形成隔离层。
步骤S132：在隔离层中形成第二沟槽，第二沟槽的一侧壁暴露出条形结构的中间区域的部分表面。
步骤S133：刻蚀去除第二沟槽暴露出的条形结构，形成第一沟槽，中间区域的第一沟槽和第一子层沿垂直于衬底的方向交替设置。
在步骤S131中，参照图9，可以采用任一种合适的沉积工艺形成隔离层230，隔离层230填充隔离沟槽130，隔离层230的材料可以包括氧化硅、氮化硅、或氮氧化硅中的至少一种。可以理解的是，隔离层230可以一次沉积形成，也可以分为多次沉积形成。
在步骤S132中，参照图17或参照图49，刻蚀去除靠近条形结构300的部分隔离层230，形成第二沟槽221，第二沟槽221暴露出条形结构300的中间区域A11的部分表面。
在步骤S133中，参照图19或参照图50，基于第二沟槽221刻蚀条形结构300，去除中间区域A11的部分结构，沿第三方向D3，在中间区域A11形成间隔设置的第一沟槽121，且第一沟槽121和第一子层210沿第三方向D3交替设置。一些实施例中，可以采用湿法刻蚀工艺形成第一沟槽121，向第二沟槽221中注入刻蚀液，通过刻蚀液腐蚀去除中间区域A11的部分结构，其中，刻蚀液刻蚀去除的可以是第二子层220，也可以是在第二子层220的原本的位置形成的其他膜层。
本公开的存储器的制作方法，在隔离层中形成靠近条形结构的第二沟槽，然后基于第二沟槽的侧壁刻蚀条形结构形成第一沟槽，减少了刻蚀叠层结构形成贯穿叠层结构的孔或沟槽的工序，降低了制程难度，不仅能够提升制程效率、降低工艺成本，还能提高产品的良品率。
在一些实施例中，步骤S140：于第一沟槽中形成第一半导体沟道和第一栅介质层，包括以下步骤：
步骤S141：形成半导体材料层，半导体材料层覆盖第一沟槽的槽壁和第二沟槽的槽壁。
步骤S142：形成栅介质材料层，栅介质材料层覆盖半导体材料层。
步骤S143：去除第二沟槽中的半导体材料层和栅介质材料层，第一沟槽中的半导体材料层形成第一半导体沟道，第一沟槽中的栅介质材料层形成第一栅介质层。
在步骤S141中，参照图20、图21所示，可以采用原子层沉积工艺(Atomic Layer Deposition，ALD)沉积形成半导体材料层410，半导体材料层410覆盖第一沟槽121的槽壁和第二沟槽221的槽壁以及叠层结构200的顶面。
其中，半导体材料层410可以是单晶硅或多晶硅等，也可以是氧化物半导体层，氧化物半导体层410的材料可以包括铟镓锌氧化物。比如，氧化物半导体层410的材料可以包括以下材料中的至少一种：氧化锌锡(ZTO)、氧化铟锌(IZO)、氧化铟锡(ITO)、掺 钨氧化铟(IWO)、氧化锌(ZnOx)、氧化铟(InOx、In2O3)、氧化锡(SnO2)、氧化钛(TiOx)、氧化铟锌(InSnOx)、氮氧化锌(ZnxOyNz)、氧化镁锌(MgxZnyOz)、氧化铟锌(InxZnyOz)、氧化铟镓锌(InxGayZnzOa)、氧化锆铟锌(ZrxInyZnzOa)、氧化铪铟锌(HfxInyZnzOa)、氧化锡铟锌(SnxInyZnzOa)、氧化铝锡铟锌(AlxSnyInzZnaOd)、氧化硅铟锌(SixInyZnzOa)、氧化锌锡(ZnxSnyOz)、氧化铝锌锡(AlxZnySnzOa)、氧化镓锌锡(GaxZnySnzOa)、氧化锆锌锡(ZrxZnySnzOa)、氧化铟镓硅(InGaSiO)。
在步骤S142中，参照图22所示，可以采用原子层沉积工艺沉积形成栅介质材料层420，栅介质材料层420覆盖半导体材料层410。栅介质材料层的材料可以包括氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化铪(HfON)、氧化锆(ZrO2)、氧化钽(Ta2O5)、氧化钛(TiO2)、锶钛氧化物(SrTiO3)、硅酸铪(HfSiO)、硅酸锆(ZrSiO)、硅酸锶(SrSiO)中的至少一种；再或者，栅介质材料层的材料可以包括氮化硅酸铪(HfSiON)、氮化硅酸锆(ZrSiON)、氮化硅酸锆(SrSiON)中的至少一种。
在步骤S143中，在一些示例中，参照图24、图25、图26，自第二沟槽221的中心向槽壁的方向依次去除第二沟槽221中的栅介质材料层420和半导体材料层410。
在另一些示例中，参照图29所示，在第二沟槽221的外周形成第三沟槽321，暴露出第二沟槽221中的半导体材料层410，自第二沟槽221的槽壁向中心的方向依次去除第二沟槽221中的半导体材料层410和栅介质材料层420。
在一些实施例中，步骤S150，形成第一字线，包括以下步骤：
步骤S151：于第一沟槽中形成第一水平部，第一水平部覆盖第一栅介质层并填充第一沟槽，第二沟槽的一侧壁暴露出第一水平部的部分表面。
步骤S152：形成第一竖直部，第一竖直部接触第一水平部的暴露的表面并填充第二沟槽。
在步骤S151中，于第一沟槽中形成第一水平部，包括以下步骤：
步骤S1511：形成第一栅导电层，第一栅导电层覆盖栅介质材料层并填充第一沟槽和第二沟槽。
本步骤在步骤S142形成栅介质材料层420之后执行。参照图23所示，可以采用化学气相沉积工艺(Chemical Vapor Deposition，CVD)、原子层沉积工艺或溅射(sputtering)中的任一种沉积工艺沉积形成第一栅导电层430，第一栅导电层430填充第二沟槽221和第一沟槽121未填充的区域。
步骤S1512：刻蚀去除第二沟槽中的第一栅导电层，保留第一沟槽中的第一栅导电层，形成第一水平部。
本步骤可以在步骤S143之前执行，也可以在步骤S143之后执行。
在一些示例中，参照图24-图26所示，可以依次刻蚀去除第二沟槽221中的第一栅导电层430、栅介质材料层420和半导体材料层410，暴露出第二沟槽221。
在一些示例中，参照图29所示，先刻蚀去除第二沟槽221的周围的部分隔离层230，形成第三沟槽321，第三沟槽321暴露出位于第二沟槽221中的半导体材料层410；然后，基于第三沟槽321刻蚀去除第二沟槽221中的半导体材料层410、栅介质材料层420和第一栅导电层430。
在步骤S152中，形成第一竖直部VP1，包括：形成第二栅导电层440，第二栅导电层440至少填充第二沟槽221形成第一竖直部VP1。
其中，参照图23、图27所示，第一栅导电层430的材料、第二栅导电层440的材料可以选自钛或钛的化合物、钽或钽的化合物、钨或钨的化合物、铜或铜的化合物中的至少一种，第一栅导电层430和第二栅导电层440的材料可以相同也可以不同。
在一些实施例中，参照图4所示，在步骤S120中定义存储单元区Z1和位线区Z2的同时，在叠层结构200定义选择区Z3，存储单元区Z1和位线区Z2沿第一方向D1排列，选择区Z3沿第二方向D2在位线区Z2的一端，第二方向D2平行于衬底100且与第一方向D1相交。
在一些实施例中，存储器的制作方法，还包括以下步骤：
如图18、图50所示，参照图4，刻蚀位线区Z2，去除位线区Z2的部分叠层结构200，沿垂直于衬底100的方向，在位线区Z2中相邻的第一子层210之间形成第四沟槽421，第四沟槽421靠近选择区Z3设置。上述步骤可以和步骤S130同时执行，首先，刻蚀去除靠近选择区Z3的部分隔离层230，形成第五沟槽521，第五沟槽521暴露出位线区Z2的部分叠层结构200。基于第五沟槽521刻蚀位线区Z2的叠层结构200，在位线区Z2形成第四沟槽421。
如图31、图51所示，于第一沟槽121中形成第一半导体沟道161和第一栅介质层171的同时，于第四沟槽421中形成第二半导体沟道261和第二栅介质层271，第二半导体沟道261覆盖第四沟槽421的槽壁，第二栅介质层271覆盖第二半导体沟道261。
如图33、图52、图53所示，形成第一字线WL1的同时，形成第二字线WL2，第二字线WL2包括形成在第四沟槽421的第二水平部HS2以及形成在隔离沟槽130的第二竖直部VP2，第二水平部HS2覆盖第二栅介质层271并填充第四沟槽421，第二竖直部VP2垂直设置在衬底100上，第二水平部HS2和第二竖直部VP2相连。
本公开一些实施例提供了一种存储器的制作方法，如图2所示，图2示出了根据本公开一些实施例提供的存储器的制作方法的流程图，图4-图34为存储器的制作方法的各个阶段的示意图，下面结合图4-图34并参照图52-图56对存储器的制作方法进行介绍。如图2所示，存储器的制作方法，包括如下的步骤：
步骤S210：提供衬底，在衬底上形成叠层结构，叠层结构包括交替的第一子层和第二子层，在叠层结构定义存储单元区、位线区和选择区，存储单元区和位线区沿第一方向排列，选择区沿第二方向在位线区的一端。
参照图4，本实施例的衬底100和步骤S110中的衬底100相同，在此不再赘述。
参照图4、图5所示，叠层结构200包括沿第三方向D3交替堆叠的第一子层210和第二子层220，第一子层210为氧化硅层，第二子层220为半导体掺杂层，半导体掺杂层为导电掺杂的多晶硅层，半导体掺杂层可以具有P型导电类型或N型导电类型。叠层结构200的顶层和底层均为第一子层210。
在衬底100上形成叠层结构200，可以采用以下实施方式：
参照图4、图5所示，可以选用化学气相沉积工艺、原子层沉积工艺或溅射中的任一种沉积工艺交替沉积形成氧化硅层和半导体掺杂层，重复循环若干次形成叠层结构200。叠层结构200的氧化硅层和半导体掺杂层可以交替堆叠多层。
参照图5，根据待形成的存储器的结构对叠层结构200布局，在叠层结构200上定义出存储单元区Z1、位线区Z2和选择区Z3，一些实施例中，沿第一方向D1在位线区Z2的两侧各定义一存储单元区Z1，沿第二方向D2在位线区Z2的一端部定义出选择区Z3。第一方向D1平行于衬底100，第二方向D2平行于衬底100且与第一方向D1相交。
步骤S220：形成隔离沟槽，隔离沟槽沿垂直于衬底的方向贯穿叠层结构，隔离沟槽沿第一方向延伸、将存储单元区的叠层结构划分成至少一个沿第一方向延伸的条形结构，位线区的半导体掺杂层形成沿第二方向延伸的位线，选择区的半导体掺杂层形成沿第一方向延伸的选择线。
如图6、图7所示，参照图4、图5，在叠层结构200的顶面上形成第一掩膜层(图中未示出)，第一掩膜层暴露出存储单元区Z1的叠层结构200的部分顶面和选择区Z3的叠层结构200的部分顶面，刻蚀去除掩膜层暴露出的叠层结构200形成隔离沟槽130，隔离沟槽130将存储单元区Z1的叠层结构200划分成沿第一方向D1延伸、沿第二方向D2间隔排列的条形结构300，同时，位线区Z2被保留的第二子层220(以下统称为半导体掺杂层)直接形成为沿第二方向D2延伸、沿第三方向D3间隔排列的位线BL(参照图33)，被保留的半导体掺杂层直接形成为沿第一方向D1延伸、沿第三方向D3间隔排列的选择线SL(参照图33)，且选择区Z3的选择线SL和存储单元区Z1的条形结构300沿第二方向D2间隔设置。
步骤S230：于隔离沟槽中形成隔离层。
如图8所示，参照图6、图7，可以选择化学气相沉积工艺或原子层沉积工艺中任意 一种沉积工艺沉积形成隔离层230，隔离层230填充隔离沟槽130。隔离层230的材料可以包括氧化硅、氮化硅或氮氧化硅中的至少一种。
步骤S240：于存储单元区远离位线区的一端形成电容器。
于存储单元区远离位线区的一端形成电容器，包括以下步骤：
步骤S241：刻蚀去除远离位线区的一端的部分第一子层，暴露出半导体掺杂层远离位线区的一端的部分表面。
刻蚀去除远离位线区Z2的一端的部分第一子层210，可以采用以下步骤：
沿第一方向D1，在存储单元区Z1的条形结构300定义出沿远离位线区Z2依次排列的第一区域A1和第二区域A2(参照图11)，第一区域A1靠近位线区Z2，第二区域A2远离位线区Z2。
如图9、图10所示，在结构的顶面形成第二掩膜层(图中未示出)，第二掩膜层暴露出和第二区域A2相连的隔离层230的顶面，基于第二掩膜层刻蚀隔离层230，刻蚀去除和第二区域A2相连的隔离层230，暴露出远离位线区Z2的部分隔离沟槽130，将本步骤暴露出的隔离沟槽130定义为第一子沟槽131，第一子沟槽131暴露出第二区域A2的条形结构300的表面。
然后，参照图11、图12所示，基于第一子沟槽131刻蚀条形结构300，去除第二区域A2的第一子层210(以下统称为氧化硅层)，暴露出第二区域A2的半导体掺杂层的表面。
示例性的，可以采用干法工艺或湿法工艺刻蚀去除第二区域A2的氧化硅层。
步骤S242：形成介电层，介电层覆盖半导体掺杂层的暴露的表面。
如图13所示，参照图12，通过原子层沉积工艺沉积形成介电层610，介电层610均匀覆盖在第二区域A2的半导体掺杂层的暴露的表面上。介电层610的材料可以包括钛酸锶(SrTiO3)、氧化铝(Al2O3)、氧化锆(ZrO)或氧化铪(HfO2)中的至少一种。
步骤S243：形成上电极，上电极覆盖介电层。
如图14所示，参照图13，可以采用原子层沉积工艺沉积形成上电极620，上电极620覆盖介电层610的表面，上电极620的材料可以包括高熔点金属，诸如钴(Co)、钛(Ti)、镍(Ni)、钨(W)和/或钼(Mo)中的至少一种；或者，上电极620的材料还可以包括金属氮化物，诸如钛氮化物、钛硅氮化物、钛铝氮化物、钽氮化物、钽硅氮化物、钽铝氮化物、和/或钨氮化物。
介电层610覆盖的半导体掺杂层(也即第二区域A2的半导体掺杂层)、介电层610和上电极620在存储单元区Z1远离位线区Z2的一端(也即第二区域A2)形成电容器600，介电层610覆盖的半导体掺杂层(也即第二区域A2的半导体掺杂层)作为电容器600的下电极630。
在一些实施例中，在步骤S243之后还执行了以下步骤：
步骤S244：形成共用上极板，共用上极板覆盖上电极并填充半导体掺杂层之间未被填充的区域以及第一子沟槽中未被填充的区域。
如图15所示，参照图14，可以通过化学气相沉积工艺、物理气相沉积工艺、原子层沉积工艺或溅射中的任一种沉积工艺形成共用上极板640，共用上极板640覆盖各电容器600的上电极620的表面并填充第二区域A2的半导体掺杂层之间未被填充的区域以及第一子沟槽131中未被填充的区域。
共用上极板640的材料可以包括掺杂有导电离子的半导体材料或者导电金属。比如，共用上极板640的材料可以包括单晶硅或多晶硅，共用上极板640的材料也可以包括金属钨、钴、钛和/或镍中的至少一种。如此，能够充分利用存储器的面积，增加存储器的存储能力。
步骤S250：在隔离层中形成第二沟槽，第二沟槽的一侧壁暴露出条形结构的中间区域的部分表面，同时，在隔离层中形成第五沟槽，第五沟槽的一侧壁暴露出位线区的叠层结构的部分表面。
如图16、图17、图18所示，在结构的顶面形成第三掩膜层(图中未示出)，第三掩膜层定义有第二沟槽221和第五沟槽521的图案，刻蚀去除第三掩膜层暴露出隔离层230， 分别形成第二沟槽221和第五沟槽521，第二沟槽221设置在存储单元区Z1(参照图5)，第二沟槽221暴露出条形结构300的中间区域A11的部分表面，本实施例中，条形结构300的中间区域A11指的是第一区域A1(参照图11)的中间区域A11。第五沟槽521靠近选择区Z3(参照图5)设置，第五沟槽521暴露出位线区Z2的叠层结构200的部分表面。
步骤S260：刻蚀条形结构的中间区域，去除部分条形结构，沿垂直于衬底的方向，在相邻的第一子层之间形成第一沟槽，同时刻蚀位线区，去除位线区的部分叠层结构，沿垂直于衬底的方向，在位线区中相邻的第一子层之间形成第四沟槽，第四沟槽靠近选择区设置。
如图19、图20所示，参照图17、图18，可以采用湿法工艺刻蚀叠层结构200，刻蚀去除被第二沟槽221暴露出的半导体掺杂层，在第一区域A1(参照图11)的中间区域A11形成第一沟槽121，第一沟槽121和第二沟槽221连通，第一沟槽121将存储单元区Z1的半导体掺杂层划分成沿第一方向D1独立设置在第一沟槽121两侧的两段，参照图52、图55、图56所示，第一区域A1中，位于第一沟槽121左侧的半导体掺杂层作为后续形成的存储单元SU中单元晶体管MCT的第一源/漏极181，位于第一沟槽121右侧的半导体掺杂层作为后续形成的存储单元SU中单元晶体管MCT的第二源/漏极182，可以看出，第一源/漏极181和电容器600相连，第二源/漏极182和位线BL相连。
同时，如图19、图20所示，参照图17、图18，刻蚀去除被第五沟槽521暴露出的半导体掺杂层，在位线区Z2的中间区域A11形成第四沟槽421，第四沟槽421和第五沟槽521连通，且第四沟槽421将位线区Z2的半导体掺杂层划分成沿第二方向D2独立设置在第四沟槽421两侧的两段。参照图52、图55、图56所示，靠近位线BL的部分作为后续形成的选择晶体管ST的第三源/漏极281，靠近选择区Z3的部分作为后续形成的选择晶体管ST的第四源/漏极282，可以看出，第三源/漏极281和位线BL相连，第四源/漏极282和选择线SL相连。
步骤S270：于第一沟槽中形成第一半导体沟道和第一栅介质层，第一半导体沟道覆盖第一沟槽的槽壁，第一栅介质层覆盖第一半导体沟道，同时，于第四沟槽中形成第二半导体沟道和第二栅介质层，第二半导体沟道覆盖第四沟槽的槽壁，第二栅介质层覆盖第二半导体沟道。
可以采用以下实施方式，如图21、图22、图23所示，依次形成半导体材料层410、栅介质材料层420和第一栅导电层430，半导体材料层410覆盖第一沟槽121的槽壁、第二沟槽221的槽壁、第四沟槽421的槽壁和第五沟槽521的槽壁，栅介质材料层420覆盖半导体材料层410，第一栅导电层430覆盖栅介质材料层420并填充第一沟槽121未被填充的区域、第二沟槽221未被填充的区域、第四沟槽421未被填充的区域和第五沟槽521未被填充的区域。
如图26或如图32所示，刻蚀去除第二沟槽221中的半导体材料层410、栅介质材料层420和第一栅导电层430以及第五沟槽521中的半导体材料层410、栅介质材料层420和第一栅导电层430，第一沟槽121中的半导体材料层410、栅介质材料层420和第一栅导电层430被保留，并分别形成第一半导体沟道161、第一栅介质层171和第一字线WL1的第一水平部HS1，第四沟槽421中的半导体材料层410、栅介质材料层420和第一栅导电层430被保留，并分别形成第二半导体沟道261、第二栅介质层271和第二字线WL2的第二水平部HS2。
在一些实施例中，去除第二沟槽221和第五沟槽521中的半导体材料层410、栅介质材料层420和第一栅导电层430，采用以下实施方式：
如图24所示，参照图23，用湿法工艺刻蚀去除第二沟槽221中的第一栅导电层430，同时去除第五沟槽521中的第一栅导电层430，暴露出第二沟槽221和第五沟槽521中的栅介质材料层420。然后，如图25所示，参照图24，采用湿法工艺刻蚀去除第二沟槽221中的栅介质材料层420，同时去除第五沟槽521中的栅介质材料层420，暴露出第二沟槽221和第五沟槽521中的半导体材料层410。接着，如图26所示，参照图25，采用湿法工艺刻蚀去除第二沟槽221中的半导体材料层410，同时去除第五沟槽521中的半导体材料 层410，暴露出第二沟槽221和第五沟槽521。
自沟槽中心向槽壁的方向逐层去除第一栅导电层430、栅介质材料层420和半导体材料层410，制程工艺简单、制程步骤精简、能够节约制程时间、降低制程成本。
在一些实施例中，去除第二沟槽221和第五沟槽521中的半导体材料层410、栅介质材料层420和第一栅导电层430，采用以下实施方式：
首先，如图29、图30所示，刻蚀去除第二沟槽221的周围的部分隔离层230，形成第三沟槽321，第三沟槽321暴露出位于第二沟槽221中的半导体材料层410，同时，刻蚀去除第五沟槽521的周围的部分隔离层230，形成第六沟槽621，第六沟槽621暴露出位于第六沟槽621中的半导体材料层410。
可以在结构的顶面上形成第四掩膜层，第四掩膜层暴露出第二沟槽221周围的部分隔离层230的顶面和第五沟槽521周围的部分隔离层230的顶面，刻蚀去除被第四沟槽421暴露出的隔离层230，在第二沟槽221的外周形成第三沟槽321，同时在第五沟槽521的外周形成第六沟槽621。
然后，如图31所示，参照图30，基于第三沟槽321逐层刻蚀去除第二沟槽221中的半导体材料层410、栅介质材料层420和第一栅导电层430，同时基于第六沟槽621逐层刻蚀去除第五沟槽521中的半导体材料层410、栅介质材料层420和第一栅导电层430。
可以采用湿法工艺逐层刻蚀去除第二沟槽221和第五沟槽521中的半导体材料层410、栅介质材料层420和第一栅导电层430。自沟槽的槽壁向中心的方向刻蚀第二沟槽221和第五沟槽521中的膜层，能够确保第二沟槽221和第五沟槽521中的半导体材料层410全部被刻蚀去除，避免第二沟槽221或第五沟槽521中存在残留的半导体材料层410在存储器中形成寄生器件，进一步提升的存储器的性能和品质，并且，本实施例中在第二沟槽221外侧形成第三沟槽321，能够增大后续形成的第一竖直部VP1的尺寸，降低第一字线WL1的电阻；同样的，本实施例也能降低第二字线WL2的电阻。
步骤S280：形成第一字线，同时形成第二字线。
如图33、图34所示，第一字线WL1包括形成在第一沟槽121中的第一水平部HS1以及形成在隔离沟槽130中的第一竖直部VP1，第一水平部HS1覆盖第一栅介质层171，第一竖直部VP1垂直设置在衬底100上并填充第二沟槽221，第一水平部HS1和第一竖直部VP1相连。
如图33、图34所示，第二字线WL2包括形成在第四沟槽421的第二水平部HS2以及形成在隔离沟槽130的第二竖直部VP2，第二水平部HS2覆盖第二栅介质层271，第二竖直部VP2垂直设置在衬底100上并填充第五沟槽521，第二水平部HS2和第二竖直部VP2相连。
参照图26、图31、图32所示，第一字线WL1的第一水平部HS1和第二字线WL2的第一水平部HS1已经在步骤S270中形成，只需形成第一字线WL1的第一竖直部VP1和第二字线WL2的第二竖直部VP2。
如图27所示，可以选用化学气相沉积工艺、原子层沉积工艺、物理气相沉积工艺或溅镀中的任一种沉积工艺沉积形成第二栅导电层440，第二栅导电层440分别填充第二沟槽221和第五沟槽521，可以理解的是，在形成第三沟槽321和第六沟槽621的实施例中，第二栅导电层440还填充第三沟槽321和第六沟槽621。
如图28所示，刻蚀去除覆盖在结构顶面的第二栅导电层440，第二沟槽221中的第二栅导电层440形成第一竖直部VP1，第一竖直部VP1覆盖第一水平部HS1和第一水平部HS1共同形成第一字线WL1。在一些实施例中，第二沟槽221和第三沟槽321中的第二栅导电层440共同形成第一竖直部VP1。
第五沟槽521中的第二栅导电层440形成第二竖直部VP2，第二竖直部VP2覆盖第二水平部HS2和第二水平部HS2共同形成第二字线WL2。在一些实施例中，第五沟槽521和第六沟槽621中的第二栅导电层440共同形成第二竖直部VP2。
本实施例的存储器的制作方法，基于氧化硅和半导体掺杂层形成的叠层结构形成三维架构，在形成半导体掺杂层时通过原位掺杂激活半导体掺杂层中的导电离子，以使半导体 掺杂层具有导电性，如此，形成隔离沟槽后，位线区的半导体掺杂层直接形成位线，选择区的半导体掺杂层形成选择线，无需执行导电材料的置换的步骤，提高了制程效率。
本实施例的存储器的制作方法，在隔离层中形成第二沟槽和第五沟槽，减少刻蚀叠层结构的步骤；同时，利用叠层结构保护第一沟槽和第四沟槽，采用由内向外或由外向内的方式去除第二沟槽和第五沟槽中的半导体材料层、栅介质材料层和第一栅导电层，避免导电材料残留形成寄生器件，避免寄生器件影响存储器的性能，可进一步提高存储器的三维堆叠的层数，提升存储器的集成密度。
本实施例的存储器的制作方法，在存储器中形成的晶体管具有较低的关态电流，可以降低存储器的漏电，有利于降低存储器的功耗、降低存储器中器件的尺寸，提高存储器中器件的阵列密度。
本公开一些实施例提供了一种存储器的制作方法，如图3所示，图3示出了根据本公开一些实施例提供的存储器的制作方法的流程图，图35-图53为存储器的制作方法的各个阶段的示意图，下面结合图35-图53并参照图52、图57、图58对存储器的制作方法进行介绍。如图3所示，存储器的制作方法，包括如下的步骤：
步骤S310：提供衬底，在衬底上形成叠层结构，叠层结构包括交替的第一子层和第二子层，在叠层结构定义存储单元区、位线区和选择区，存储单元区和位线区沿第一方向排列，选择区沿第二方向在位线区的一端。
参照图35所示，叠层结构200包括沿第三方向D3交替堆叠的第一子层210和第二子层220，第一子层210为氧化硅层，第二子层220为氮化硅层。叠层结构200的顶层和底层均为第一子层210(也即氧化硅层)。
一些实施例中，在衬底100上形成叠层结构200，可以采用以下实施方式：
参照图35所示，可以选用化学气相沉积工艺、原子层沉积工艺或溅射中的任一种沉积工艺交替沉积形成氧化硅层和氮化硅层，重复循环若干次形成叠层结构200。叠层结构200的氧化硅层和氮化硅层可以交替堆叠2层～1024层或更多层。例如，氧化硅层和氮化硅层可以交替堆叠48层、64层、128层、256层或512层等。
参照图5，根据待形成的存储器的结构对叠层结构200布局，在叠层结构200上定义出存储单元区Z1、位线区Z2和选择区Z3，本实施例中，沿第一方向D1在位线区Z2的两侧各定义一存储单元区Z1，沿第二方向D2在位线区Z2的一端部定义出选择区Z3。第一方向D1平行于衬底100，第二方向D2平行于衬底100且与第一方向D1相交。
步骤S320：形成隔离沟槽，隔离沟槽垂直贯穿叠层结构，隔离沟槽沿第一方向延伸、将存储单元区的叠层结构划分成至少一个沿第一方向延伸的条形结构。
形成隔离沟槽的实施方式和上述实施例中步骤S220中的实施方式相同，在此不再赘述。
一些实施例和上述实施例的区别之处在于，如图36所示，参照图36，叠层结构200包括交替设置的氧化硅层和氮化硅层，因此，形成隔离沟槽130之后，位线区Z2被保留的叠层结构200沿第二方向D2延伸，选择区Z3被保留的叠层结构200沿第一方向D1延伸。
步骤S330：刻蚀去除全部的第二子层，在第二子层被去除的区域形成空气层。
本实施例中，刻蚀去除全部的第二子层，包括以下步骤：
步骤S331：形成第一隔离层，第一隔离层填充部分隔离沟槽。
如图37所示，可以选择化学气相沉积工艺或物理气相沉积工艺沉积第一隔离层231，第一隔离层231的材料可以包括氧化硅、氮化硅或氮氧化硅中的至少一种。
步骤S332：刻蚀去除部分第一隔离层，在隔离槽中形成第二子沟槽，第二子沟槽暴露出叠层结构的部分侧壁。
如图38所示，沿第一方向D1，在存储单元区Z1的条形结构300定义出沿远离位线区Z2依次排列的第一区域A1和第二区域A2，第一区域A1靠近位线区Z2，第二区域A2远离位线区Z2。
本实施例中，如图39、图40、图41所示，在结构的顶面上形成第五掩膜层(图中未 示出)，第五掩膜层暴露出第一隔离层231的部分顶面，刻蚀去除第五掩膜层暴露出的第一隔离层231，暴露出部分隔离沟槽130，一些实施例中，将本步骤中暴露出的隔离沟槽130定义为第二子沟槽132，第二子沟槽132暴露出第一区域A1的叠层结构200的部分侧壁，保留的第一隔离层231用于支撑叠层结构200的架构。
步骤S333：基于第二子沟槽刻蚀去除全部的第二子层。
如图42所示，参照39、图40、图41，向第二子沟槽132中注入刻蚀液，刻蚀液可以为磷酸溶液，通过刻蚀液溶解去除全部的第二子层220(也即氮化硅层，以下统称为氮化硅层)，去除全部的氮化硅层，在氮化硅层原本的位置形成空气层240，沿第三方向D3，氧化硅层和空气层240交替设置。
步骤S340：于位线区的空气层中形成位线，位线沿第二方向延伸，第二方向平行于衬底且与第一方向相交。
于位线区Z2的空气层240中形成位线BL，采用以下实施方式：
参照图42、图53，可以采用原子层沉积工艺或化学气相沉积工艺沉积导电金属材料层，导电金属材料层填充空气层240以及部分第二子沟槽132。然后，刻蚀去除位线区Z2以外的导电金属材料层，位线区Z2的空气层240中的导电金属材料层被保留形成位线BL，位线BL沿第二方向D2延伸，沿第三方向D3间隔排列。
位线BL的材料可以包括钛或钛的化合物、钽或钽的化合物、钨或钨的化合物、铜或铜的化合物中的至少一种；一些实施例中位线BL的材料包括金属钨，如此，位线BL的电阻更小、导电性更好。
步骤S350：形成导体层，导体层填充空气层未被填充的区域。
如图43所示，参照图42，可以采用原子层沉积工艺或化学气相沉积工艺沉积导体层250的材料填充空气层未被填充的区域以及第二子沟槽132，然后刻蚀去除第二子沟槽132中的导体层的材料，在空气层240未被填充的区域形成导体层250。参照图53，选择区Z3的导体层250形成选择线SL，选择线SL沿第一方向D1延伸、沿第三方向D3间隔排列。
导体层250的材料可以包括钛或钛的化合物、钽或钽的化合物，一些实施例中，导体层250的材料包括氮化钛。
如图44所示，参照图43，然后于第二子沟槽132中填充第二隔离层232。
步骤S360：于存储单元区远离位线区的一端形成电容器。
一些实施例中，于存储单元区远离位线区的一端形成电容器，包括以下步骤：
步骤S361：刻蚀去除远离位线区的一端的部分第一子层，暴露出导体层远离位线区的一端的部分表面。
如图45所示，参照图44，在结构的顶面形成第二掩膜层(图中未示出)，第二掩膜层暴露出和第二区域A2相连的第一隔离层231的顶面，基于第二掩膜层刻蚀去除和第二区域A2相连的第一隔离层231，形成和第二区域A2相连的第一子沟槽131，第一子沟槽131的侧壁暴露出第二区域A2的氧化硅层和导体层250的部分表面。
然后，如图46所示，参照图45，基于第一子沟槽131刻蚀去除第二区域A2的氧化硅层，暴露出第二区域A2的导体层250的表面。
步骤S362：形成介电层，介电层覆盖被导体层暴露的表面。
参照图47所示，通过原子层沉积工艺沉积形成介电层610，介电层610均匀覆盖在第二区域A2的半导体掺杂层的暴露的表面上。介电层610的材料和上述实施例中步骤S242中形成介电层610的材料相同，在此不再赘述。
步骤S363：形成上电极，上电极覆盖介电层。
参照图47所示，可以采用原子层沉积工艺沉积形成上电极620，上电极620覆盖介电层610的表面，上电极620的材料和上述实施例中步骤S243中形成上电极620的材料相同，在此不再赘述。
介电层610覆盖的导体层250(也即第二区域A2的导体层250)、介电层610和上电极620在存储单元区Z1远离位线区Z2的一端(也即第二区域A2)形成电容器600，介电层610覆盖的导体层250(也即第二区域A2的导体层250)作为电容器600的下电极630。
在一些实施例中，在步骤S363之后还执行了以下步骤：
步骤S364：形成共用上极板，共用上极板覆盖上电极并填充导体层250之间未被填充的区域以及第一子沟槽中未被填充的区域。
参照图48所示，一些实施例中，形成共用上极板640的制程以及共用上极板640的材料和选择和上述实施例中S244相同，在此不再赘述。
步骤S370：形成第二沟槽，第二沟槽暴露出第一区域的部分侧壁，同时形成第五沟槽，第五沟槽的一侧壁暴露出位线区的部分侧壁。
如图49所示，在结构的顶面形成第三掩膜层(图中未示出)，第三掩膜层定义有第二沟槽221和第五沟槽521的图案，刻蚀去除第三掩膜层暴露出第一隔离层231和第二隔离层232，分别形成第二沟槽221和第五沟槽521。
沿第一方向D1，第二沟槽221和位线区Z2间隔预设距离，第二沟槽221靠近条形结构300设置，并暴露出条形结构300的部分侧壁。
沿第二方向D2，第五沟槽521和选择区Z3间隔预设距离，第五沟槽521靠近位线区Z2的叠层设置，并暴露出位线区Z2的叠层的部分侧壁。
步骤S380：刻蚀条形结构的中间区域，去除部分条形结构，沿垂直于衬底的方向，在相邻的第一子层之间形成第一沟槽，同时刻蚀位线区，去除位线区的部分叠层结构，沿垂直于衬底的方向，在位线区中相邻的第一子层之间形成第四沟槽，第四沟槽靠近选择区设置。
如图50所示，基于第二沟槽221刻蚀条形结构300，刻蚀去除被第二沟槽221暴露出的导体层250，形成第一沟槽121。参照图52、图57、图58，第一沟槽121将存储单元区Z1的导体层250划分成沿第一方向D1独立设置在第一沟槽121两侧的两段，参照图55所示，第一区域A1中，位于第一沟槽121左侧的导体层250作为后续形成的存储单元SU中单元晶体管MCT的第一源/漏极181，位于第一沟槽121右侧的导体层250作为后续形成的存储单元SU中单元晶体管MCT的第二源/漏极182，可以看出，第一源/漏极181和电容器600相连，第二源/漏极182和位线相连。
如图50所示，基于第五沟槽521刻蚀位线区Z2，去除被第五沟槽521暴露出的导电金属材料层，形成第四沟槽421。参照图52、图57、图58，第四沟槽421将位线区Z2的导电金属材料层划分成沿第二方向D2独立设置在第四沟槽421两侧的两段，其中，远离选择线SL的部分作为后续形成的选择晶体管ST的第三源/漏极281，靠近选择区Z3的部分作为后续形成的选择晶体管ST的第四源/漏极282，可以看出，第三源/漏极281和位线BL相连，第四源/漏极282和选择线SL相连。
步骤S390：于第一沟槽中形成第一半导体沟道和第一栅介质层，第一半导体沟道覆盖第一沟槽的槽壁，第一栅介质层覆盖第一半导体沟道，同时，于第四沟槽中形成第二半导体沟道和第二栅介质层，第二半导体沟道覆盖第四沟槽的槽壁，第二栅介质层覆盖第二半导体沟道。
步骤S400：形成第一字线，同时形成第二字线。
参照图51、图52、图53所示，一些实施例中的步骤S390、步骤S400和上述实施例中的步骤S270、步骤S280的实施方法相同，在此不再赘述。
本实施例的存储器的制作方法，可以基于氧化硅和氮化硅层形成的叠层结构形成三维架构的存储器，也可以基于氧化硅和半导体掺杂层形成的叠层结构形成三维架构的存储器，存储器的制作方法适用范围广泛。
根据一示例性实施例，提供了一种存储器，参照图52、图55、图56、图57、图58，并参照图33、图53，存储器包括衬底100、至少一条第一字线WL1、以及至少一列存储单元列SUC；第一字线WL1包括第一竖直部VP1以及至少一个第一水平部HS1，第一竖直部VP1垂直设置在衬底100上，至少一个第一水平部HS1沿垂直于衬底100的方向间隔排列并与第一竖直部VP1连接；至少一列存储单元列SUC，存储单元列SUC包括沿垂直于衬底100的方向间隔排列的至少一个存储单元SU；存储单元SU包括单元晶体管MCT，第一水平部HS1作为单元晶体管MCT的栅极G1，单元晶体管MCT包括沿远离第一水平 部HS1的方向依次设置的第一栅介质层171和第一半导体沟道161，单元晶体管MCT还包括沿第一方向D1相对设置在第一半导体沟道161两侧的第一源/漏极181和第二源/漏极182，第一方向D1平行于衬底100。存储器中没有在制程中残留的导电膜层，没有寄生器件，能够提高半导体结构的响应速度、避免响应延迟，提高半导体结构的良率和电性能。
第一字线WL1包括第一竖直部VP1以及至少一个第一水平部HS1，第一水平部HS1作为单元晶体管MCT的栅极G1，第一水平部HS不受第一字线WL1的第一竖直部VP1的长度限制，第一水平部HS可以增加单元晶体管MCT的栅极G1的长度，从而增强单元晶体管MCT的栅极G1的控制能力；另外，第一水平部HS1位置的第一半导体沟道161可以得到保护，避免去除寄生沟道时损伤第一水平部HS1位置的第一半导体沟道161。
在一些实施例中，参照图52、图53，在平行于第一方向D1且垂直于衬底100的平面中，第一半导体沟道161环绕第一水平部HS1，如此设置可以增强单元晶体管MCT的栅极G1的控制能力。
在一些实施例中，参照图52、图53，第一半导体沟道161包括连接沟道1611，连接沟道1611位于第一水平部HS1在第二方向D2的一侧，第二方向D2平行于衬底100且与第一方向D1相交，如此设置使得第一半导体沟道161进一步包覆第一水平部HS1，进一步增强单元晶体管MCT的栅极G1的控制能力。
在一些实施例中，参照图52、图53，并参照图33、图53，第一半导体沟道161为杯状，第一半导体沟道161套设在第一水平部HS1上。
第一水平部HS1的一侧和第一竖直部VP1相连，第一水平部HS1除和第一竖直部VP1相连的区域以外，第一水平部HS1的全部外周面均被第一半导体沟道161覆盖，比如，参照图52、图53所示，在一些实施例中，第一水平部HS1沿平行于衬底100的方向的截面图为正方形或长方形，第一水平部HS1的一侧的侧面和第一竖直部VP1相连，第一水平部HS1的其余五面均被第一半导体沟道161覆盖，第一半导体沟道161对第一水平部HS1覆盖面积较大，单元晶体管MCT的栅极G1的控制能力较大。
在一些实施例中，如图55、图56所示，存储单元SU还包括半导体掺杂层220a，半导体掺杂层220a包括沿第一方向D1相对设置在第一半导体沟道161的两侧的两段，第一源/漏极181和第二源/漏极182分别设置在第一半导体沟道161的两侧的半导体掺杂层220a中。
在一些实施例中，如图57、图58所示，存储单元SU还包括导体层250，导体层250包括沿第一方向D1相对设置在第一半导体沟道161的两侧的两段，第一源/漏极181和第二源/漏极182分别设置在第一半导体沟道161的两侧的导体层250中。
在一些实施例中，存储单元SU还包括用于存储数据的记忆体件，用于存储数据的记忆体件可以为电容器600或磁性隧道结或相变组件。
在一些实施例中，参照图52、图55、图56、图57、图58，存储单元SU还包括电容器600，沿第一方向D1，电容器600设置在单元晶体管MCT的一侧，电容器600和单元晶体管MCT的第一源/漏极181相连。
在一些实施例中，参照图52、图55、图56、图57、图58，电容器600包括下电极630、介电层610和上电极620，下电极630与第一源/漏极181相连，介电层610设置在上电极620和下电极630之间。介电层610覆盖在下电极630上，上电极620覆盖在介电层610上。
在一些实施例中，参照图52、图55、图56、图57、图58，电容器600的下电极630设置在半导体掺杂层220a中，电容器600的下电极630和第一源/漏极181同侧设置，第一源/漏极181靠近第一半导体沟道161设置，电容器600的下电极630远离第一半导体沟道161设置。
在一些实施例中，参照图52、图55、图56、图57、图58，电容器600的下电极630设置在导体层250中，同样的，电容器600的下电极630和第一源/漏极181同侧设置，第一源/漏极181靠近第一半导体沟道161设置，电容器600的下电极630远离第一半导体沟道161设置。
在一些实施例中，参照图52、图55、图56、图57、图58，在平行于衬底100的平面中，多个电容器600的上电极620相互连接，形成封闭图形，如此设置可以增加上电极620、下电极630的相对面积，增大电容。
在一些实施例中，参照图52、图55、图56、图57、图58，在封闭图形内具有共用上极板640，共用上极板640与上电极620连接，如此设置可以增加存储器中电容器600的体积占比，增加存储器的存储电容。
在一些实施例中，参照图52、图55、图56、图57、图58，存储器还包括至少一条位线BL，位线BL沿垂直于衬底100的方向间隔排列，位线BL沿第二方向D2延伸，位线BL和沿第二方向D2排列的多个单元晶体管MCT的第二源/漏极相连，第二方向D2平行于衬底100且与第一方向D1相交，位线BL用于在单元晶体管MCT导通时，对单元晶体管MCT所在的存储单元SU执行读取或写入操作。
在一些实施例中，参照图52、图55、图56、图57、图58，存储器还包括第二字线WL2，第二字线WL2包括第二竖直部VP2以及至少一个第二水平部HS2，第二竖直部VP2垂直设置在衬底100上，至少一个第二水平部HS2沿垂直于衬底100的方向间隔排列并与第二竖直部VP2连接。
参照图52、图55、图56、图57、图58，存储器还包括至少一个选择晶体管ST，至少一个选择晶体管ST沿垂直于衬底100的方向间隔排列，第二水平部HS2作为选择晶体管ST的栅极G2，选择晶体管ST包括沿远离第二水平部HS2的方向依次设置的第二栅介质层271和第二半导体沟道261，选择晶体管ST还包括沿第二方向D2相对设置在第二半导体沟道261两侧的第三源/漏极281和第四源/漏极282；选择晶体管ST的第三源/漏极281和位线BL一一对应连接。
参照图52、图55、图56、图57、图58，存储器还包括至少一条选择线SL，至少一条选择线SL沿垂直于衬底100的方向间隔排列，选择线SL沿第一方向D1延伸，且选择线SL和选择晶体管ST的第四源/漏极282一一对应连接。选择线SL用于向选择晶体管ST提供电压，并通过电压控制选择晶体管ST的导通或截止，进而通过位线BL控制与其相连的存储单元SU。
根据一示例性实施例，提供了一种电子设备，电子设备包括上述实施例中的存储器。电子设备可以为存储设备、手机、电脑、平板电脑、电视、人工智能设备等。
以上所述实施例的各技术特征可以进行任意的组合，为使描述简洁，未对上述实施例各个技术特征所有可能的组合都进行描述，然而，只要这些技术特征的组合不存在矛盾，都应当认为是本说明书记载的范围。
以上所述实施例仅表达了本公开的几种实施方式，其描述较为具体和详细，但并不能因此而理解为对申请专利范围的限制。应当指出的是，对于本领域的普通技术人员来说，在不脱离本公开构思的前提下，还可以做出若干变形和改进，这些都属于本公开的保护范围。因此，本公开专利的保护范围应以所附权利要求为准。

Claims (27)

  1. 一种存储器的制作方法，包括以下步骤：
    提供衬底，在所述衬底上形成叠层结构，所述叠层结构包括交替堆叠的第一子层和第二子层，在所述叠层结构定义存储单元区和位线区；
    形成隔离沟槽，所述隔离沟槽沿垂直于所述衬底的方向贯穿所述叠层结构，所述隔离沟槽沿第一方向延伸、将所述存储单元区的所述叠层结构划分成至少一个沿所述第一方向延伸的条形结构，所述第一方向平行于所述衬底；
    刻蚀所述条形结构的中间区域，去除部分所述条形结构，沿垂直于所述衬底的方向，在相邻的所述第一子层之间形成第一沟槽；
    于所述第一沟槽中形成第一半导体沟道和第一栅介质层，所述第一半导体沟道覆盖所述第一沟槽的槽壁，所述第一栅介质层覆盖所述第一半导体沟道；
    形成第一字线，所述第一字线包括形成在所述第一沟槽中的第一水平部以及形成在所述隔离沟槽中的第一竖直部，所述第一水平部覆盖所述第一栅介质层，所述第一竖直部垂直设置在所述衬底上，所述第一水平部和所述第一竖直部相连。
  2. 根据权利要求1所述的存储器的制作方法，其中，在相邻的所述第一子层之间形成第一沟槽，包括：
    于所述隔离沟槽中形成隔离层；
    在所述隔离层中形成第二沟槽，所述第二沟槽的一侧壁暴露出所述条形结构的中间区域的部分表面；
    刻蚀去除所述第二沟槽暴露出的所述条形结构，形成所述第一沟槽，所述中间区域的所述第一沟槽和所述第一子层沿垂直于所述衬底的方向交替设置。
  3. 根据权利要求2所述的存储器的制作方法，其中，于所述第一沟槽中形成第一半导体沟道和第一栅介质层，包括：
    形成半导体材料层，所述半导体材料层覆盖所述第一沟槽的槽壁和所述第二沟槽的槽壁；
    形成栅介质材料层，所述栅介质材料层覆盖所述半导体材料层；
    去除所述第二沟槽中的所述半导体材料层和所述栅介质材料层，所述第一沟槽中的所述半导体材料层形成所述第一半导体沟道，所述第一沟槽中的所述栅介质材料层形成所述第一栅介质层。
  4. 根据权利要求3所述的存储器的制作方法，其中，形成第一字线，包括：
    于所述第一沟槽中形成所述第一水平部，所述第一水平部覆盖所述第一栅介质层并填充所述第一沟槽，所述第二沟槽的一侧壁暴露出所述第一水平部的部分表面；
    形成所述第一竖直部，所述第一竖直部接触所述第一水平部的暴露的表面并填充所述第二沟槽。
  5. 根据权利要求4所述的存储器的制作方法，其中，于所述第一沟槽中形成所述第一水平部，包括：
    形成栅介质材料层之后，形成第一栅导电层，所述第一栅导电层覆盖所述栅介质材料层并填充所述第一沟槽和所述第二沟槽；
    刻蚀去除所述第二沟槽中的所述第一栅导电层，保留所述第一沟槽中的所述第一栅导电层，形成所述第一水平部。
  6. 根据权利要求5所述的存储器的制作方法，其中，所述制作方法，包括：
    依次刻蚀去除所述第二沟槽中的所述第一栅导电层、所述栅介质材料层和所述半导体材料层，暴露出所述第二沟槽。
  7. 根据权利要求5所述的存储器的制作方法，其中，所述制作方法，包括：
    刻蚀去除所述第二沟槽的周围的部分所述隔离层，形成第三沟槽，所述第三沟槽暴露出位于所述第二沟槽中的所述半导体材料层；
    基于所述第三沟槽刻蚀去除所述第二沟槽中的所述半导体材料层、所述栅介质材料层和所述第一栅导电层。
  8. 根据权利要求4所述的存储器的制作方法，其中，形成所述第一竖直部，包括：
    形成第二栅导电层，所述第二栅导电层至少填充所述第二沟槽，形成所述第一竖直部。
  9. 根据权利要求1-8中任一项所述的存储器的制作方法，其中，沿所述第一方向，所述第一沟槽和所述位线区间隔预设距离。
  10. 根据权利要求1-8中任一项所述的存储器的制作方法，其中，在所述叠层结构定义选择区，所述存储单元区和所述位线区沿所述第一方向排列，所述选择区沿第二方向在所述位线区的一端，所述第二方向平行于所述衬底且与所述第一方向相交；所述制作方法，还包括：
    刻蚀所述位线区，去除所述位线区的部分所述叠层结构，沿垂直于所述衬底的方向，在所述位线区中相邻的所述第一子层之间形成第四沟槽，所述第四沟槽靠近所述选择区设置。
  11. 根据权利要求10所述的存储器的制作方法，其中，所述制作方法，还包括：
    于所述第一沟槽中形成所述第一半导体沟道和所述第一栅介质层的同时，于所述第四沟槽中形成第二半导体沟道和第二栅介质层，所述第二半导体沟道覆盖所述第四沟槽的槽壁，所述第二栅介质层覆盖所述第二半导体沟道；
    形成所述第一字线的同时，形成第二字线，所述第二字线包括形成在所述第四沟槽的第二水平部以及形成在所述隔离沟槽的第二竖直部，所述第二水平部覆盖所述第二栅介质层并填充所述第四沟槽，所述第二竖直部垂直设置在所述衬底上，所述第二水平部和所述第二竖直部相连。
  12. 根据权利要求1所述的存储器的制作方法，其中，所述第一子层为氧化硅层，所述第二子层为半导体掺杂层，形成所述隔离沟槽之后，所述位线区的所述半导体掺杂层形成沿第二方向延伸的位线，所述第二方向平行于所述衬底且与所述第一方向相交。
  13. 根据权利要求12所述的存储器的制作方法，其中，所述制作方法，还包括：
    刻蚀去除远离所述位线区的一端的部分所述第一子层，暴露出所述半导体掺杂层远离所述位线区的一端的部分表面；
    形成介电层，所述介电层覆盖所述半导体掺杂层的暴露的表面；
    形成上电极，所述上电极覆盖所述介电层。
  14. 根据权利要求1所述的存储器的制作方法，其中，所述第一子层为氧化硅层，所述第二子层为氮化硅层；于所述存储单元区形成隔离沟槽之后，所述制作方法包括：
    刻蚀去除全部的所述第二子层，在所述第二子层被去除的区域形成空气层；
    于所述位线区的所述空气层中形成位线，所述位线沿第二方向延伸，所述第二方向平行于所述衬底且与所述第一方向相交；
    形成导体层，所述导体层填充所述空气层未被填充的区域。
  15. 根据权利要求14所述的存储器的制作方法，其中，所述制作方法，还包括：
    刻蚀去除远离所述位线区的一端的部分所述第一子层，暴露出所述导体层远离所述位线区的一端的部分表面；
    形成介电层，所述介电层覆盖所述导体层的暴露的表面；
    形成上电极，所述上电极覆盖所述介电层。
  16. 一种存储器，所述存储器包括：
    衬底；
    至少一条第一字线，所述第一字线包括第一竖直部以及至少一个第一水平部，所述第一竖直部垂直设置在所述衬底上，至少一个所述第一水平部沿垂直于所述衬底的方向间隔排列并与所述第一竖直部连接；
    至少一列存储单元列，所述存储单元列包括沿垂直于所述衬底的方向间隔排列的至少一个存储单元；
    所述存储单元包括单元晶体管，所述第一水平部作为所述单元晶体管的栅极，所述单元晶体管包括沿远离所述第一水平部的方向依次设置的第一栅介质层和第一半导体沟道，所述单元晶体管还包括沿第一方向相对设置在所述第一半导体沟道两侧的第一源/漏极和第二源/漏极，所述第一方向平行于所述衬底。
  17. 根据权利要求16所述的存储器，其中，在平行于所述第一方向且垂直于所述衬底的平面中，所述第一半导体沟道环绕所述第一水平部。
  18. 根据权利要求17所述的存储器，其中，所述第一半导体沟道包括连接沟道，连接沟道位于所述第一水平部在第二方向的一侧，所述第二方向平行于所述衬底且与所述第一方向相交。
  19. 根据权利要求17所述的存储器，其中，所述第一半导体沟道为杯状，所述第一半导体沟道套设在所述第一水平部上。
  20. 根据权利要求16所述的存储器，其中，所述存储单元还包括电容器，沿所述第一方向，所述电容器设置在所述单元晶体管的一侧，所述电容器和所述单元晶体管的所述第一源/漏极相连。
  21. 根据权利要求20所述的存储器，其中，所述电容器包括下电极、介电层和上电极，所述下电极与所述第一源/漏极相连，所述介电层设置在所述上电极和所述下电极之间。
  22. 根据权利要求21所述的存储器，其中，在平行于所述衬底的平面中，多个所述电容器的所述上电极相互连接，形成封闭图形。
  23. 根据权利要求22所述的存储器，其中，在所述封闭图形内具有共用上极板，共用上极板与所述上电极连接。
  24. 根据权利要求16所述的存储器，其中，所述存储器还包括：
    至少一条位线，至少一条所述位线沿垂直于所述衬底的方向间隔排列，所述位线沿第二方向延伸，所述位线和沿所述第二方向排列的多个所述单元晶体管的所述第二源/漏极相连，所述第二方向平行于所述衬底且与所述第一方向相交。
  25. 根据权利要求24所述的存储器，其中，所述存储器还包括：
    第二字线，所述第二字线包括第二竖直部以及至少一个第二水平部，所述第二竖直部垂直设置在所述衬底上，至少一个所述第二水平部沿垂直于所述衬底的方向间隔排列并与所述第二竖直部连接；
    至少一个选择晶体管，至少一个所述选择晶体管沿垂直于所述衬底的方向间隔排列，所述第二水平部作为所述选择晶体管的栅极，所述选择晶体管包括沿远离所述第二水平部的方向依次设置的第二栅介质层和第二半导体沟道，所述选择晶体管还包括沿所述第二方向相对设置在所述第二半导体沟道两侧的第三源/漏极和第四源/漏极；所述选择晶体管的所述第三源/漏极和所述位线一一对应连接。
  26. 根据权利要求25所述的存储器，其中，所述存储器还包括：
    至少一条选择线，至少一条所述选择线沿垂直于所述衬底的方向间隔排列，所述选择线沿所述第一方向延伸，且所述选择线和所述选择晶体管的所述第四源/漏极一一对应连接。
  27. 一种电子设备，包括如权利要求16至26中任一项所述的存储器。
PCT/CN2024/113355 2023-12-01 2024-08-20 存储器的制作方法及存储器、电子设备 Pending WO2025112686A1 (zh)

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CN115867026A (zh) * 2023-02-23 2023-03-28 北京超弦存储器研究院 半导体结构、存储器及其制造方法、电子设备

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