WO2025112668A1 - 移位寄存器单元、显示基板和显示装置 - Google Patents

移位寄存器单元、显示基板和显示装置 Download PDF

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Publication number
WO2025112668A1
WO2025112668A1 PCT/CN2024/112607 CN2024112607W WO2025112668A1 WO 2025112668 A1 WO2025112668 A1 WO 2025112668A1 CN 2024112607 W CN2024112607 W CN 2024112607W WO 2025112668 A1 WO2025112668 A1 WO 2025112668A1
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WIPO (PCT)
Prior art keywords
transistor
input terminal
signal input
control
coupled
Prior art date
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PCT/CN2024/112607
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English (en)
French (fr)
Inventor
黄耀
都蒙蒙
李光明
董向丹
胡明
邱海军
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Beijing BOE Technology Development Co Ltd
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Publication of WO2025112668A1 publication Critical patent/WO2025112668A1/zh
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/287—Organisation of a multiplicity of shift registers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register unit, a display substrate and a display device.
  • GOA Gate On Array
  • the gate drive circuit generally includes a plurality of cascaded shift register units, each of which includes a plurality of thin film transistors.
  • the characteristics of the thin film transistors have a certain influence on the stability of the gate drive signal output by the shift register unit, thereby affecting the display quality of the display product.
  • the object of the present disclosure is to provide a shift register unit, a display substrate and a display device.
  • a first aspect of the present disclosure provides a shift register unit, comprising a first output transistor, a gate drive signal output terminal, a first output control node, a control signal input terminal and a first signal input terminal;
  • the first output transistor includes a dual-gate structure, a first gate of the first output transistor is coupled to the first output control node, and a second gate of the first output transistor is coupled to the control signal
  • the first electrode of the first output transistor is coupled to the first signal input terminal, and the second electrode of the first output transistor is coupled to the gate drive signal output terminal.
  • the shift register unit further includes a second output transistor, a second output control node and a first level signal input terminal, a gate of the second output transistor is coupled to the second output control node, a first electrode of the second output transistor is coupled to the first level signal input terminal, and a second electrode of the second output transistor is coupled to the gate drive signal output terminal;
  • the first signal input terminal includes a first clock signal input terminal;
  • the shift register unit also includes a second level signal input terminal, a third level signal input terminal and a control signal debugging unit, and the control signal debugging unit includes a first debugging sub-unit and a second debugging sub-unit;
  • the first debugging sub-unit is coupled to the first clock signal input terminal, the second output control node, the second level signal input terminal and the control signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the second level signal input terminal and the control signal input terminal under the control of the first clock signal input terminal and the second output control node;
  • the second debugging subunit is coupled to the first output control node, the third level signal input terminal and the control signal input terminal respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the control signal input terminal under the control of the first output control node.
  • the first debugging sub-unit includes a first debugging transistor and a second debugging transistor;
  • the second debugging sub-unit includes a third debugging transistor;
  • the gate of the first debugging transistor is coupled to the first clock signal input terminal, the first electrode of the first debugging transistor is coupled to the second electrode of the second debugging transistor, and the second electrode of the first debugging transistor is coupled to the control signal input terminal;
  • the gate of the second debugging transistor is coupled to the second output control node, and the first electrode of the second debugging transistor is coupled to the second level signal input terminal;
  • a gate of the third debugging transistor is coupled to the first output control node, a first electrode of the third debugging transistor is coupled to the third level signal input terminal, and a second electrode of the third debugging transistor is coupled to the control signal input terminal.
  • the shift register unit further includes: a first node control unit, a second node control unit, a second clock signal input terminal and a start signal input terminal;
  • the first node control unit is coupled to the second clock signal input terminal, the first output control node and the start signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the initial signal input terminal and the first output control node under the control of the second clock signal input terminal;
  • the second node control unit is coupled to the first clock signal input terminal, the second clock signal input terminal, the first level signal input terminal, the third level signal input terminal and the second output control node respectively, and is used to control the electrical connection between the first level signal input terminal and the second output control node under the control of the first clock signal input terminal, and is used to control the electrical connection between the third level signal input terminal and the second output control node under the control of the second clock signal input terminal; or, the second node control unit is coupled to the second clock signal input terminal, the first output control node, the second output control node and the third level signal input terminal respectively, and is used to control the electrical connection between the third level signal input terminal and the second output control node under the control of the second clock signal input terminal; and is used to control the electrical connection between the second clock signal input terminal and the second output control node under the control of the first output control node.
  • the first node control unit is also coupled to the first clock signal input terminal, the second output control node, and the first level signal input terminal, respectively; and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the first output control node under the control of the first clock signal input terminal and the second output control node.
  • the first signal input terminal includes a first level signal input terminal
  • the control signal input terminal includes a second level signal input terminal
  • the second level signal input terminal is used to input a DC second level signal
  • the shift register unit also includes: a second output transistor, a second output control node and a third level signal input terminal, the gate of the second output transistor is coupled to the second output control node, the first electrode of the second output transistor is coupled to the third level signal input terminal, and the second electrode of the second output transistor is coupled to the gate drive signal output terminal.
  • the shift register unit further includes a first node control unit, the first node control unit is respectively coupled to the second output control node, the first level signal input terminal and the first output control node, and is used to control the conduction or disconnection under the control of the second output control node.
  • the electrical connection between the first level signal input terminal and the first output control node is opened.
  • the first node control unit is also coupled to the second level signal input terminal;
  • the first node control unit includes: a first control transistor, the first control transistor includes a dual-gate structure, the first gate of the first control transistor is coupled to the second output control node, the second gate of the first control transistor is coupled to the second level signal input terminal, the first electrode of the first control transistor is coupled to the first level signal input terminal, and the second electrode of the first control transistor is coupled to the first output control node.
  • the shift register unit also includes a second node control unit, a third clock signal input terminal and a start signal input terminal; the second node control unit is respectively coupled to the third clock signal input terminal, the start signal input terminal and the second output control node, and is used to control the conduction or disconnection of the electrical connection between the start signal input terminal and the second output control node under the control of the third clock signal input terminal.
  • the second node control unit is further coupled to the third level signal input terminal;
  • the second node control unit includes: a second control transistor, a third control transistor and a fourth control transistor;
  • the gate of the second control transistor is coupled to the third clock signal input terminal, the first electrode of the second control transistor is coupled to the start signal input terminal, and the second electrode of the second control transistor is coupled to the first electrode of the third control transistor;
  • a gate of the third control transistor is coupled to the third clock signal input terminal, and a second electrode of the third control transistor is coupled to the second output control node.
  • the gate of the fourth control transistor is coupled to the second output control node, the first electrode of the fourth control transistor is coupled to the third level signal input terminal, and the second electrode of the fourth control transistor is coupled to the first electrode of the third control transistor.
  • the first node control unit is also coupled to the first level signal input terminal, the third level signal input terminal and the start signal input terminal respectively; and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the first output control node under the control of the first level signal input terminal and the start signal input terminal.
  • the second aspect of the present disclosure provides a display substrate, including the above shift register unit, wherein the display substrate includes a display area and a display region located in the display area.
  • the shift register unit is located in the display area and/or the peripheral area.
  • the shift register unit includes a control signal debugging unit, the control signal debugging unit includes a first debugging sub-unit and a second debugging sub-unit, the first debugging sub-unit includes a first debugging transistor and a second debugging transistor; the second debugging sub-unit includes a third debugging transistor; the shift register unit also includes a first output transistor and a second output transistor;
  • the first output transistor and the second output transistor are arranged along a first direction; at least a portion of the third debug transistor, the first debug transistor and the second debug transistor are arranged along the first direction; the first output transistor is located between the display area and the first debug transistor.
  • the second debug transistor and the second output transistor both include a dual-gate structure, a first gate of the second debug transistor and a first gate of the second output transistor form an integral structure, and a second gate of the second debug transistor and a second gate of the second output transistor form an integral structure.
  • the gate of the third debugging transistor and the first gate of the first output transistor form an integrated structure.
  • the display substrate further includes a second level signal line, and the second level signal line is coupled to the second debugging transistor as a second level signal input terminal;
  • the first debug transistor includes a first debug active layer
  • the second debug transistor includes a second debug active layer
  • the third debug transistor includes a third debug active layer
  • the orthographic projection of the second-level signal line on the substrate substrate of the display substrate at least partially overlaps with the orthographic projection of the first debugging active layer on the substrate substrate of the display substrate; and/or, the orthographic projection of the second-level signal line on the substrate substrate of the display substrate at least partially overlaps with the orthographic projection of the second debugging active layer on the substrate substrate of the display substrate; and/or, the orthographic projection of the second-level signal line on the substrate substrate of the display substrate at least partially overlaps with the orthographic projection of the third debugging active layer on the substrate substrate of the display substrate.
  • the display substrate further includes a first level signal line and a third level signal line; the first level signal line is coupled to the second output transistor as a first level signal input terminal; the third level signal line is coupled to the third debugging transistor as a third level signal input terminal;
  • an orthographic projection of the third level signal line on the base substrate, an orthographic projection of the first level signal line on the base substrate, and an orthographic projection of the second level signal line on the base substrate are arranged in sequence.
  • the display substrate further includes a first clock signal line, a second clock signal line and a start signal line, the first clock signal line being coupled to the first debug transistor as a first clock signal input terminal;
  • the shift register unit further includes a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor;
  • the gate of the fifth transistor is coupled to the second clock signal line, the first electrode of the fifth transistor is coupled to the third level signal line, and the second electrode of the fifth transistor is coupled to the gate of the second output transistor;
  • the gate of the sixth transistor is coupled to the first clock signal line, the first electrode of the sixth transistor is coupled to the first level signal line, and the second electrode of the sixth transistor is coupled to the gate of the second output transistor;
  • the gate of the seventh transistor is coupled to the second clock signal line, the first electrode of the seventh transistor is coupled to the start signal line, the second electrode of the seventh transistor is coupled to the first electrode of the eighth transistor, the second electrode of the eighth transistor is coupled to the gate of the first output transistor, and the gate of the eighth transistor is coupled to the third level signal line;
  • the seventh transistor, the eighth transistor, the sixth transistor and the fifth transistor are arranged in sequence along the first direction; the orthographic projection of the seventh transistor on the substrate, the orthographic projection of the eighth transistor on the substrate, the orthographic projection of the sixth transistor on the substrate, and the orthographic projection of the fifth transistor on the substrate are all located between the orthographic projection of the third-level signal line on the substrate and the orthographic projection of the first-level signal line on the substrate.
  • the start signal line, the second clock signal line, the first clock signal line and the third level signal line are arranged in sequence.
  • a third aspect of the present disclosure provides a display device, comprising the above-mentioned display substrate.
  • FIG1 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure
  • FIG2 is a timing diagram corresponding to the circuit structure of FIG1 ;
  • FIG3 is a waveform diagram of a gate driving signal corresponding to different voltage values of the threshold voltage offset corresponding to the circuit structure of FIG1 ;
  • FIG4 is a schematic diagram of the structure of a dual-gate transistor provided by an embodiment of the present disclosure.
  • FIG5 is a schematic diagram of characteristic curves corresponding to different bottom gate voltages provided by an embodiment of the present disclosure.
  • FIG6 is a schematic diagram of the structure of a dual-gate transistor provided in an embodiment of the present disclosure.
  • FIG7 is a schematic diagram of waveforms corresponding to the top gate and the bottom gate provided in an embodiment of the present disclosure
  • FIG. 8 is a schematic diagram of a voltage change at a control signal input terminal corresponding to a voltage change of a second level signal provided by an embodiment of the present disclosure
  • FIG9 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure.
  • FIG10 is a timing diagram corresponding to FIG9 ;
  • FIG11 is a waveform diagram of a gate driving signal corresponding to different voltage values of the threshold voltage offset of the circuit structure of FIG9 ;
  • FIG12 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure.
  • FIG13 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure.
  • FIG14 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure.
  • FIG15 is a waveform diagram of a gate driving signal corresponding to different voltage values of the threshold voltage offset of the circuit structure of FIG14 ;
  • FIG16 is a schematic diagram of a circuit structure of a shift register unit provided in an embodiment of the present disclosure.
  • FIG17 is a waveform diagram of a gate driving signal corresponding to different voltage values of the threshold voltage offset of the circuit structure of FIG16 ;
  • FIG18 is a schematic diagram of the layout of the first gate metal layer of the shift register unit provided in an embodiment of the present disclosure
  • FIG19 is a schematic diagram of a layout in which a second gate metal layer is added on the basis of FIG18;
  • FIG20 is a schematic diagram of the layout of the second gate metal layer added in FIG19;
  • FIG21 is a schematic diagram of a layout in which an oxide active layer is added based on FIG19;
  • FIG22 is a schematic diagram of the layout of the oxide active layer added in FIG21;
  • FIG23 is a schematic diagram of a layout in which a third gate metal layer is added on the basis of FIG21;
  • FIG24 is a schematic diagram of the layout of the third gate metal layer added in FIG23;
  • FIG25 is a schematic diagram of a layout in which a first source/drain metal layer is added on the basis of FIG23;
  • FIG26 is a schematic diagram of the layout of the first source-drain metal layer added in FIG25;
  • FIG. 27 is a schematic diagram of the layout of adding a second source-drain metal layer based on FIG. 25 .
  • the embodiment of the present disclosure provides a shift register unit, including a first output transistor Ts1 , a gate drive signal output terminal OUT, a first output control node N1 , a control signal input terminal K0 and a first signal input terminal X0 ;
  • the first output transistor Ts1 includes a dual-gate structure, a first gate of the first output transistor Ts1 is coupled to the first output control node N1, a second gate of the first output transistor Ts1 is coupled to the control signal input terminal K0, a first electrode of the first output transistor Ts1 is coupled to the first signal input terminal X0, and a second electrode of the first output transistor Ts1 is coupled to the gate drive signal output terminal OUT.
  • the shift register unit is applied to a gate driving circuit, and the gate driving circuit includes a plurality of cascaded shift register units.
  • the shift register unit includes a gate control shift register unit (Gate GOA) and an emission control shift register unit (EM GOA), but is not limited thereto.
  • the display device includes a display area and a peripheral area located around the display area, the display area includes a plurality of sub-pixels distributed in an array, and a plurality of sub-pixel driving circuits included in the plurality of sub-pixels are divided into a plurality of rows of sub-pixel driving circuits.
  • the display device further includes a plurality of gate lines, which are respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits, and are used to provide gate signals to each sub-pixel driving circuit.
  • the compensation transistor and/or data writing transistor included in the sub-pixel driving circuit may be coupled to the gate line, but is not limited thereto.
  • the gate drive circuit includes a gate control gate drive circuit, the gate control gate drive circuit includes a plurality of cascaded Gate GOAs, and the gate drive signal output terminal OUT of each Gate GOA is coupled to the corresponding gate line.
  • the display device further includes a plurality of light-emitting control signal lines, and the light-emitting control signal lines are respectively coupled to each sub-pixel driving circuit in a corresponding row of sub-pixel driving circuits, and are used to provide a light-emitting control signal to each sub-pixel driving circuit.
  • the power control transistor and the light-emitting control transistor included in the sub-pixel driving circuit can be coupled to the light-emitting control signal line, but is not limited to this.
  • the gate driving circuit includes a light-emitting control gate driving circuit, and the light-emitting control gate driving circuit includes a plurality of cascaded EM GOAs, and the gate driving signal output terminal OUT of each EM GOA is coupled to the corresponding light-emitting control signal line.
  • the shift register unit includes a plurality of transistors, and the transistors include oxide transistors, but are not limited thereto.
  • the first electrode includes a source electrode, and the second electrode includes a drain electrode; or, the first electrode includes a drain electrode, and the second electrode includes a source electrode.
  • the first gate of the first output transistor Ts1 is coupled to the first output control node N1
  • the second gate of the first output transistor Ts1 is coupled to the control signal input terminal K0
  • the first output transistor Ts1 is used to realize the electrical connection between the first signal input terminal X0 and the gate drive signal output terminal OUT under the joint control of the first output control node N1 and the control signal input terminal K0.
  • FIG. 1 and FIG. 2 it is a schematic diagram of abnormal output waveforms of each node and the gate drive signal output terminal OUT after a threshold voltage shift (VTH Shift) occurs in the first output transistor Ts1 in the shift register unit, such as after negative bias.
  • VTH Shift threshold voltage shift
  • the main reason for the abnormality is that the negative bias leakage causes the first output transistor Ts1 to turn on, and the increase in parasitic capacitance causes the first clock signal input terminal GCB to couple and leak with the gate drive signal output terminal OUT, resulting in glitches in the signal waveform, which in turn causes screen Mura after VTH Shift negative bias.
  • the main transistor negative bias point is the first output transistor Ts1.
  • N3 in FIG. 2 represents a node located between the seventh transistor T7 and the eighth transistor T8 in FIG. 1 .
  • the first gate of the first output transistor Ts1 is defined as a top gate TG
  • the second gate of the first output transistor Ts1 is defined as a bottom gate BG.
  • the threshold voltage of the first output transistor Ts1 can be regulated by regulating the voltage of the bottom gate BG.
  • the effect of the bottom gate BG potential on the transistor characteristics is illustrated.
  • the horizontal axis in the figure represents V GS1 , that is, the voltage difference between the top gate TG and the source of the transistor, and the vertical axis in the figure represents Ids, that is, the current between the source and drain of the transistor.
  • the figure illustrates the effect on the characteristic curve when the voltage of the bottom gate BG is set to 0V, 2V, 4V, 6V, -2V, -4V, and -6V respectively. Therefore, the characteristic curve of the transistor can be regulated by adjusting the voltage of the bottom gate BG, so that even if the transistor is negatively biased, it can be adjusted back through the control of the bottom gate BG.
  • a connection mode of the first output transistor Ts1 is illustrated, wherein the first electrode of the first output transistor Ts1 is coupled to the first clock signal input terminal GCB, and the second electrode of the first output transistor Ts1 is coupled to the gate drive signal output terminal OUT.
  • V GS1 of the first output transistor Ts1 is the voltage difference between the top gate TG and the source of the first output transistor Ts1
  • V GS2 of the first output transistor Ts1 is the voltage difference between the bottom gate BG and the source of the first output transistor Ts1.
  • the signal waveform of the bottom gate BG will change with the signal waveform of the top gate TG, and can also be controlled by the control signal input terminal K0.
  • the first dark area in FIG7 illustrates V GS2 >0
  • the third dark area illustrates V GS2 ⁇ 0. Setting such a waveform of V GS2 can adjust the characteristic of the first output transistor Ts1 to be positive biased.
  • the waveform of the gate drive signal output when the VTH Shift of the first output transistor Ts1 is biased from -5V to +5V is illustrated. It can be seen that when the bias is between -5V and -2V, the output gate drive signal fluctuates.
  • the waveform of the gate drive signal output when the VTH Shift of the first output transistor Ts1 is biased from -5V to +5V is illustrated. It can be seen that when the bias is between -5V and +5V, the output gate drive signal does not fluctuate.
  • the first output transistor Ts1 is configured to include a double-gate structure.
  • the first gate of the body transistor Ts1 is coupled to the first output control node N1
  • the second gate of the first output transistor Ts1 is coupled to the control signal input terminal K0
  • the first electrode of the first output transistor Ts1 is coupled to the first signal input terminal X0
  • the second electrode of the first output transistor Ts1 is coupled to the gate drive signal output terminal OUT.
  • the first gate and the second gate can control the conduction or cutoff of the first output transistor Ts1 to ensure the normal operation of the shift register unit.
  • the characteristic curve of the first output transistor Ts1 can be adjusted, thereby effectively improving the negative bias of the first output transistor Ts1 and improving the fluctuation of the output gate drive signal.
  • the shift register unit provided in the embodiment of the present disclosure, by setting the first output transistor Ts1 to include a dual-gate structure, by adjusting the voltage of the second gate of the first output transistor Ts1, it is achieved to control the characteristic curve of the first output transistor Ts1, so that even if the first output transistor Ts1 has a negative bias, it can be adjusted back through the control of the bottom gate BG.
  • the process margin of the first output transistor Ts1 is improved, so that the first output transistor Ts1 has the ability to be compatible with a wider range of negative bias, thereby ensuring the stability of the output gate drive signal.
  • the shift register unit further includes a second output transistor Ts2, a second output control node N2 and a first level signal input terminal VGL, a gate of the second output transistor Ts2 is coupled to the second output control node N2, a first electrode of the second output transistor Ts2 is coupled to the first level signal input terminal VGL, and a second electrode of the second output transistor Ts2 is coupled to the gate drive signal output terminal OUT;
  • the first signal input terminal X0 includes a first clock signal input terminal GCB;
  • the shift register unit also includes a second level signal input terminal VGL2, a third level signal input terminal VGH and a control signal debugging unit, and the control signal debugging unit includes a first debugging sub-unit 11 and a second debugging sub-unit 12;
  • the first debugging subunit 11 is coupled to the first clock signal input terminal GCB, the second output control node N2, the second level signal input terminal VGL2 and the control signal input terminal K0 respectively, and is used to control the first clock signal input terminal GCB and the second output control node N2. Under control, controlling to turn on or off the electrical connection between the second level signal input terminal VGL2 and the control signal input terminal K0;
  • the second debugging sub-unit 12 is coupled to the first output control node N1, the third level signal input terminal VGH and the control signal input terminal K0 respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the control signal input terminal K0 under the control of the first output control node N1.
  • the first debugging sub-unit 11 includes a first debugging transistor T01 and a second debugging transistor T02;
  • the second debugging sub-unit 12 includes a third debugging transistor T03;
  • the gate of the first debugging transistor T01 is coupled to the first clock signal input terminal GCB, the first electrode of the first debugging transistor T01 is coupled to the second electrode of the second debugging transistor T02, and the second electrode of the first debugging transistor T01 is coupled to the control signal input terminal K0;
  • the gate of the second debugging transistor T02 is coupled to the second output control node N2, and the first electrode of the second debugging transistor T02 is coupled to the second level signal input terminal VGL2;
  • the gate of the third debugging transistor T03 is coupled to the first output control node N1, the first electrode of the third debugging transistor T03 is coupled to the third level signal input terminal VGH, and the second electrode of the third debugging transistor T03 is coupled to the control signal input terminal K0.
  • the second debugging subunit 12 under the control of the first output control node N1, controls to disconnect the electrical connection between the third level signal input terminal VGH and the control signal input terminal K0, that is, the third debugging transistor T03 is turned off.
  • the first debugging subunit 11 When the signal transmitted by the first clock signal input terminal GCB and the signal transmitted by the second output control node N2 are at an active level, the first debugging subunit 11, under the control of the first clock signal input terminal GCB and the second output control node N2, controls to connect the electrical connection between the second level signal input terminal VGL2 and the control signal input terminal K0, that is, the first debugging transistor T01 and the second debugging transistor T02 are both turned on, so that the potential of the control signal input terminal K0 is controlled by the second level signal input terminal VGL2.
  • the signal transmitted at the first clock signal input terminal GCB and the signal transmitted at the second output terminal GCB When the signal transmitted by the control node N2 is at an inactive level, the first debugging subunit 11, under the control of the first clock signal input terminal GCB and the second output control node N2, controls to disconnect the electrical connection between the second level signal input terminal VGL2 and the control signal input terminal K0, that is, the first debugging transistor T01 and the second debugging transistor T02 are both turned off.
  • the second debugging subunit 12 Under the control of the first output control node N1, controls to connect the electrical connection between the third level signal input terminal VGH and the control signal input terminal K0, that is, the third debugging transistor T03 is turned on, so that the potential of the control signal input terminal K0 is controlled by the third level signal input terminal VGH.
  • the control signal debugging unit can adaptively adjust the potential of the control signal input terminal K0 according to different working stages, that is, the different working states of the first output transistor Ts1, so that the potential of the second gate of the first output transistor Ts1 can be adaptively adjusted in different working stages. Therefore, the shift register unit provided in the above embodiment can adaptively adjust its characteristic curve according to the different working states of the first output transistor Ts1, and while effectively improving the negative bias problem of the first output transistor Ts1, it can further improve the output stability of the gate drive signal and reduce the power consumption of the transistor.
  • the shift register unit further includes: a first node control unit 21 , a second node control unit 22 , a second clock signal input terminal GCK and a start signal input terminal STV;
  • the first node control unit 21 is coupled to the second clock signal input terminal GCK, the first output control node N1 and the start signal input terminal STV respectively; and is used to control the electrical connection between the initial signal input terminal and the first output control node N1 to be turned on or off under the control of the second clock signal input terminal GCK;
  • the second node control unit 22 is respectively coupled to the first clock signal input terminal GCB, the second clock signal input terminal GCK, the first level signal input terminal VGL, the third level signal input terminal VGH and the second output control node N2, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGL and the second output control node N2 under the control of the first clock signal input terminal GCB, and to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the second output control node N2 under the control of the second clock signal input terminal GCK; or, as shown in FIGS.
  • the second node control unit 22 is respectively coupled to the second clock signal input terminal GCK, the first output control node N1, the second output control node N2 and the third level signal input terminal VGH, and is used for controlling the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the second output control node N2 under the control of the second clock signal input terminal GCK; and is used for controlling the conduction or disconnection of the electrical connection between the second clock signal input terminal GCK and the second output control node N2 under the control of the first output control node N1.
  • the first node control unit 21 includes a seventh transistor T7, a gate of the seventh transistor T7 is coupled to the second clock signal input terminal GCK, a first electrode of the seventh transistor T7 is coupled to the start signal input terminal STV, and a second electrode of the seventh transistor T7 is coupled to the first output control node N1.
  • the second node control unit 22 includes a fifth transistor T5 and a sixth transistor T6, the gate of the fifth transistor T5 is coupled to the second clock signal input terminal GCK, the first electrode of the fifth transistor T5 is coupled to the third level signal input terminal VGH, and the second electrode of the fifth transistor T5 is coupled to the second output control node N2.
  • the gate of the sixth transistor T6 is coupled to the first clock signal input terminal GCB, the first electrode of the sixth transistor T6 is coupled to the first level signal input terminal VGL, and the second electrode of the sixth transistor T6 is coupled to the second output control node N2.
  • the V GS voltage of each transistor when it is working can be calculated.
  • the second node control unit 22 includes the fifth transistor T5 and the ninth transistor T9, the gate of the ninth transistor T9 is coupled to the first output control node N1, the first electrode of the ninth transistor T9 is coupled to the second clock signal input terminal GCK, and the second electrode of the ninth transistor T9 is coupled to the second output control node N2.
  • the shift register unit further includes an eighth transistor T8, the gate of the eighth transistor T8 is coupled to the third level signal input terminal VGH, the first electrode of the eighth transistor T8 is coupled to the second electrode of the seventh transistor T7, and the second electrode of the eighth transistor T8 is coupled to the first output terminal VGH.
  • the shift register unit further includes a fourth capacitor C4, a first plate of the fourth capacitor C4 is coupled to the first output control node N1, and a second plate of the fourth capacitor C4 is coupled to the gate drive signal output terminal OUT.
  • the shift register unit also includes an eighth transistor T8, the second electrode of the seventh transistor T7, the gate of the ninth transistor T9, and the second electrode of the eleventh transistor T11 are all coupled to the first output control node N1 through the eighth transistor T8.
  • the first node control unit 21 is also coupled to the first clock signal input terminal GCB, the second output control node N2, and the first level signal input terminal VGL, respectively; and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGL and the first output control node N1 under the control of the first clock signal input terminal GCB and the second output control node N2.
  • the first node control unit 21 further includes a tenth transistor T10 and an eleventh transistor T11.
  • the gate of the tenth transistor T10 is coupled to the second output control node N2
  • the first electrode of the tenth transistor T10 is coupled to the first level signal input terminal VGL
  • the second electrode of the tenth transistor T10 is coupled to the first electrode of the eleventh transistor T11
  • the second electrode of the eleventh transistor T11 is coupled to the first output control node N1
  • the gate of the eleventh transistor T11 is coupled to the first clock signal input terminal GCB.
  • the first signal input terminal X0 includes a first level signal input terminal VGL
  • the control signal input terminal K0 includes a second level signal input terminal VGL2
  • the second level signal input terminal VGL2 is used to input a DC second level signal
  • the shift register unit also includes: a second output transistor Ts2, a second output control node N2 and a third level signal input terminal VGH, the gate of the second output transistor Ts2 is coupled to the second output control node N2, the first electrode of the second output transistor Ts2 is coupled to the third level signal input terminal VGH, and the second electrode of the second output transistor Ts2 is coupled to the gate drive signal output terminal OUT.
  • the above scheme is limited to the source of the first output transistor Ts1 being a fixed potential, and the source voltage cannot be changed at will, otherwise V GS2 will also change, causing characteristic changes.
  • the above setting of the first signal input terminal X0 including the first level signal input terminal VGL makes the first output transistor
  • the source of the transistor Ts1 has a fixed potential that is the same as the first level signal.
  • the control signal input terminal K0 By setting the control signal input terminal K0 to include the second level signal input terminal VGL2, the voltage of the second gate can adjust the characteristic curve of the first output transistor Ts1, thereby effectively improving the negative bias of the first output transistor Ts1 and improving the fluctuation of the output gate drive signal.
  • the shift register unit also includes a first node control unit 21, which is respectively coupled to the second output control node N2, the first level signal input terminal VGL and the first output control node N1, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal VGL and the first output control node N1 under the control of the second output control node N2.
  • the first node control unit 21 is also coupled to the second level signal input terminal VGL2; the first node control unit 21 includes: a first control transistor Tk1, the first control transistor Tk1 includes a dual-gate structure, the first gate of the first control transistor Tk1 is coupled to the second output control node N2, the second gate of the first control transistor Tk1 is coupled to the second level signal input terminal VGL2, the first electrode of the first control transistor Tk1 is coupled to the first level signal input terminal VGL, and the second electrode of the first control transistor Tk1 is coupled to the first output control node N1.
  • the above-mentioned setting of the first control transistor Tk1 includes a dual-gate structure, so that the characteristic curve of the first control transistor Tk1 can be adjusted by the voltage of the second gate of the first control transistor Tk1, thereby effectively improving the negative bias of the first control transistor Tk1 and improving the fluctuation of the output gate drive signal.
  • the waveform of the gate drive signal output when the VTH shift of the first control transistor Tk1 is biased from -5V to +5V is illustrated. It can be seen that when the bias is between -3V and +3V, there is no fluctuation in the output gate drive signal.
  • the shift register unit also includes a second node control unit 22, a third clock signal input terminal CK and a start signal input terminal STV; the second node control unit 22 is coupled to the third clock signal input terminal CK, the start signal input terminal STV and the second output control node N2, respectively, and is used to control the conduction or disconnection of the electrical connection between the start signal input terminal STV and the second output control node N2 under the control of the third clock signal input terminal CK.
  • the second node control unit 22 includes a fourteenth transistor T14, a gate of the fourteenth transistor T14 is coupled to the third clock signal input terminal CK, a first electrode of the fourteenth transistor T14 is coupled to the start signal input terminal STV, and a second electrode of the fourteenth transistor T14 is coupled to the second output control node N2.
  • the second node control unit 22 is further coupled to the third level signal input terminal VGH; the second node control unit 22 includes: a second control transistor Tk2, a third control transistor Tk3 and a fourth control transistor Tk4;
  • the gate of the second control transistor Tk2 is coupled to the third clock signal input terminal CK, the first electrode of the second control transistor Tk2 is coupled to the start signal input terminal STV, and the second electrode of the second control transistor Tk2 is coupled to the first electrode of the third control transistor Tk3;
  • a gate of the third control transistor Tk3 is coupled to the third clock signal input terminal CK, and a second electrode of the third control transistor Tk3 is coupled to the second output control node N2.
  • a gate of the fourth control transistor Tk4 is coupled to the second output control node N2, a first electrode of the fourth control transistor Tk4 is coupled to the third level signal input terminal VGH, and a second electrode of the fourth control transistor Tk4 is coupled to a first electrode of the third control transistor Tk3.
  • the channel width-to-length ratio of the fourth control transistor Tk4 is greater than the channel width-to-length ratio of the second control transistor Tk2; and/or the channel width-to-length ratio of the fourth control transistor Tk4 is greater than the channel width-to-length ratio of the third control transistor Tk3.
  • the second node control unit 22 when the second node control unit 22 is set to include: a second control transistor Tk2, a third control transistor Tk3 and a fourth control transistor Tk4, when the VTH shift of the second control transistor Tk2 and the third control transistor Tk3 is biased from -5V to +5V, the waveform of the output gate drive signal is illustrated. It can be seen that when the bias voltage is between -4V and 2V, the fourth control transistor Tk4 can absorb the leakage current well and output a stable gate drive signal.
  • the second node control unit 22 by setting the second node control unit 22 to include: the second control transistor Tk2, the third control transistor Tk3 and the fourth control transistor Tk4, it is possible to ensure that the signal is transmitted through the second control transistor Tk2 and the third control transistor Tk3, and the fourth control transistor Tk4 with a larger channel width-to-length ratio can also absorb the signal generated by the transistor characteristics.
  • the leakage current signal generated by the offset can ensure that the shift register unit normally outputs the gate drive signal even when the second control transistor Tk2 and the third control transistor Tk3 have characteristic offsets. Therefore, in the shift register unit provided by the above embodiment, the problem of unstable output gate drive signal caused by increased leakage current due to transistor characteristic offset is effectively improved, and the normal drive of the display area is ensured, thereby ensuring the display quality of the display product.
  • the above-mentioned simultaneous setting of the first output transistor Ts1 and the first control transistor Tk1 to adopt a dual-gate structure makes it possible to control the characteristics of the transistor by adjusting the second level signal received by the second gate of the transistor, so that even if the transistor is negatively biased, the potential of the second gate can be changed to optimize the VTH Margin, thereby ensuring the output of a stable gate drive signal.
  • the first node control unit 21 is also coupled to the first level signal input terminal VGL, the third level signal input terminal VGH and the start signal input terminal STV, respectively; and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal VGH and the first output control node N1 under the control of the first level signal input terminal VGL and the start signal input terminal STV.
  • the first node control unit 21 includes a first transistor T1, a second transistor T2 and a first capacitor C1.
  • the gate of the first transistor T1 is coupled to the second electrode of the second transistor T2, the first electrode of the first transistor T1 is coupled to the third level signal input terminal VGH, and the second electrode of the first transistor T1 is coupled to the first output control node N1.
  • the gate of the second transistor T2 is coupled to the start signal input terminal STV, and the first electrode of the second transistor T2 is coupled to the first level signal input terminal VGL.
  • the first plate of the first capacitor C1 is coupled to the third clock signal input terminal CK, and the second plate of the first capacitor C1 is coupled to the gate of the first transistor T1.
  • the shift register unit further includes a fourth transistor T4, the gate of the fourth transistor T4 is coupled to the third level signal input terminal VGH, the first electrode of the fourth transistor T4 is coupled to the second electrode of the first transistor T1, and the second electrode of the fourth transistor T4 is coupled to the first output control node N1.
  • the shift register unit further includes a second capacitor C2 and a third capacitor C3, the first plate of the second capacitor C2 is coupled to the first output control node N1, and the second plate of the second capacitor C2 is coupled to the gate drive signal output terminal OUT.
  • the first plate of the third capacitor C3 is coupled to the gate drive signal output terminal OUT, and the second plate of the third capacitor C3 is coupled to the gate of the second output transistor Ts2.
  • an embodiment of the present disclosure also provides a display substrate, including the shift register unit provided in the above embodiment, the display substrate includes a display area and a peripheral area located around the display area, and the shift register unit is located in the display area and/or the peripheral area.
  • the peripheral area surrounds the display area, but is not limited thereto.
  • the peripheral area includes a left frame area and a right frame area
  • the display area is located between the left frame area and the right frame area.
  • the shift register unit can be arranged in the left frame area and/or the right frame area.
  • the shift register unit can also be arranged in the display area.
  • the first gate and the second gate can control the conduction or cutoff of the first output transistor Ts1 to ensure the normal operation of the shift register unit.
  • the characteristic curve of the first output transistor Ts1 can be adjusted, thereby effectively improving the negative bias of the first output transistor Ts1 and improving the fluctuation of the output gate drive signal.
  • the shift register unit by setting the first output transistor Ts1 to include a double-gate structure, by adjusting the voltage of the second gate Ts1-g2 of the first output transistor Ts1, the characteristic curve of the first output transistor Ts1 is regulated, so that even if the first output transistor Ts1 has a negative bias, it can be adjusted back through the control of the bottom gate BG.
  • the process Margin of the first output transistor Ts1 is improved, so that the first output transistor Ts1 has the ability to be compatible with a wider range of negative biases, ensuring the stability of the output gate drive signal.
  • the display substrate provided by the embodiment of the present disclosure also has the above-mentioned beneficial effects when including the shift register unit provided by the above-mentioned embodiment.
  • the display substrate can achieve higher display quality when driven by a stable gate driving signal.
  • the shift register unit includes a control signal debugging unit
  • the control signal debugging unit includes a first debugging sub-unit 11 and a second debugging sub-unit 12
  • the first debugging sub-unit 11 includes a first debugging transistor T01 and a second debugging transistor T02
  • the second debugging sub-unit 12 includes a third debugging transistor T03
  • the shift register unit also includes a first output transistor Ts1 and a second output transistor Ts2;
  • the first output transistor Ts1 and the second output transistor Ts2 are arranged along a first direction; At least part of the third debugging transistor T03 , the first debugging transistor T01 and the second debugging transistor T02 are arranged along the first direction; and the first output transistor Ts1 is located between the display area and the first debugging transistor T01 .
  • the third debug transistor T03 and the first output transistor Ts1 are arranged along the second direction
  • the first debug transistor T01 and the first output transistor Ts1 are arranged along the second direction
  • the second debug transistor T02 and the first output transistor Ts1 are arranged along the second direction.
  • the first direction intersects with the second direction.
  • the first direction includes the longitudinal direction
  • the second direction includes the transverse direction.
  • the first output transistor Ts1 and the second output transistor Ts2 are arranged along the first direction, and at least part of the third debug transistor T03, the first debug transistor T01 and the second debug transistor T02 are arranged along the first direction; the width of the layout space occupied by the first output transistor Ts1, the second output transistor Ts2, the first debug transistor T01, the second debug transistor T02 and the third debug transistor T03 in the second direction is reduced, thereby effectively reducing the border width of the display substrate.
  • the above setting of the first output transistor Ts1 being located between the display area and the first debugging transistor T01 better plans the limited layout space and reduces the layout difficulty of the shift register unit in the limited layout space.
  • the second debugging transistor T02 and the second output transistor Ts2 both include a dual-gate structure, the first gate T02-g1 of the second debugging transistor T02 and the first gate Ts2-g1 of the second output transistor Ts2 form an integrated structure, and the second gate T02-g2 of the second debugging transistor T02 and the second gate of the second output transistor Ts2 form an integrated structure.
  • the above-mentioned configuration of the second debugging transistor T02 and the second output transistor Ts2 both include a dual-gate structure, which better improves the performance of the second debugging transistor T02 and the second output transistor Ts2.
  • forming the above-mentioned structure in an integrated structure not only ensures the coupling performance between the structures, but also helps to simplify the manufacturing process and reduce the manufacturing cost.
  • the gate T03 - g of the third debugging transistor T03 and the first gate Ts1 - g1 of the first output transistor Ts1 are formed into an integrated structure.
  • Forming the above structure in an integrated manner not only ensures the coupling performance between the structures, It is also beneficial to simplify the production process and reduce production costs.
  • the display substrate further includes a second level signal line VGL2′, and the second level signal line VGL2′ is coupled to the second debugging transistor T02 as a second level signal input terminal VGL2;
  • the first debug transistor T01 includes a first debug active layer 501
  • the second debug transistor T02 includes a second debug active layer 502
  • the third debug transistor T03 includes a third debug active layer 503 ;
  • the orthographic projection of the second-level signal line VGL2’ on the substrate substrate of the display substrate at least partially overlaps with the orthographic projection of the first debugging active layer 501 on the substrate substrate of the display substrate; and/or, the orthographic projection of the second-level signal line VGL2’ on the substrate substrate of the display substrate at least partially overlaps with the orthographic projection of the second debugging active layer 502 on the substrate substrate of the display substrate; and/or, the orthographic projection of the second-level signal line VGL2’ on the substrate substrate of the display substrate at least partially overlaps with the orthographic projection of the third debugging active layer 503 on the substrate substrate of the display substrate.
  • the first debugging active layer 501 , the second debugging active layer 502 and the third debugging active layer 503 all include oxide active layers, such as IGZO active layers, but not limited thereto.
  • the second level signal line VGL2' includes at least a portion extending along the first direction.
  • the first debugging active layer 501 and the second debugging active layer 502 both extend along the first direction
  • the third debugging active layer 503 includes a portion extending along the first direction and a portion extending along the second direction.
  • the orthographic projection of the first debugging active layer 501 on the base substrate is located inside the orthographic projection of the second level signal line VGL2' on the base substrate.
  • the orthographic projection of the second debugging active layer 502 on the base substrate is located inside the orthographic projection of the second level signal line VGL2' on the base substrate.
  • the orthographic projection of the third debugging active layer 503 on the base substrate of the display substrate partially overlaps with the orthographic projection of the second level signal line VGL2' on the base substrate of the display substrate.
  • the second debugging active layer 502 and the first debugging active layer 501 form an integrated structure.
  • the above arrangement is conducive to reducing the layout space independently occupied by the second level signal line VGL2', and is conducive to narrowing the frame of the display substrate.
  • the display substrate further includes a first level signal line VGL’ and a third level signal line VGH’; the first level signal line VGL’ is coupled to the second output transistor Ts2 as a first level signal input terminal VGL; the third level signal line VGH’ is coupled to the third debugging transistor T03 as a third level signal input terminal VGH;
  • the orthographic projection of the third level signal line VGH’ on the base substrate, the orthographic projection of the first level signal line VGL’ on the base substrate, and the orthographic projection of the second level signal line VGL2’ on the base substrate are arranged in sequence.
  • the first level signal line VGL' includes at least a portion extending along the first direction.
  • the third level signal line VGH' includes at least a portion extending along the first direction.
  • the display substrate further includes a first clock signal line GCB’, a second clock signal line GCK’ and a start signal line STV’, wherein the first clock signal line GCB’ is coupled to the first debug transistor T01 as a first clock signal input terminal GCB;
  • the shift register unit further includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8;
  • the gate of the fifth transistor T5 is coupled to the second clock signal line GCK', the first electrode of the fifth transistor T5 is coupled to the third level signal line VGH', and the second electrode of the fifth transistor T5 is coupled to the gate of the second output transistor Ts2;
  • the gate of the sixth transistor T6 is coupled to the first clock signal line GCB', the first electrode of the sixth transistor T6 is coupled to the first level signal line VGL', and the second electrode of the sixth transistor T6 is coupled to the gate of the second output transistor Ts2;
  • the gate of the seventh transistor T7 is coupled to the second clock signal line GCK', the first electrode of the seventh transistor T7 is coupled to the start signal line STV', the second electrode of the seventh transistor T7 is coupled to the first electrode of the eighth transistor T8, the second electrode of the eighth transistor T8 is coupled to the gate of the first output transistor Ts1, and the gate of the eighth transistor T8 is coupled to the third level signal line VGH'; it should be noted that, in the case where the display substrate includes a plurality of cascaded shift register units, the first electrode of the seventh transistor T7 in the first-stage shift register unit is directly coupled to the start signal line STV', and the first electrodes of the seventh transistors T7 in the remaining stages of the shift register units are all coupled to the start signal line STV'.
  • the gate driving signal output terminals OUT of the adjacent previous stage shift register units are coupled.
  • the seventh transistor T7, the eighth transistor T8, the sixth transistor T6 and the fifth transistor T5 are arranged in sequence along the first direction; the orthographic projection of the seventh transistor T7 on the substrate, the orthographic projection of the eighth transistor T8 on the substrate, the orthographic projection of the sixth transistor T6 on the substrate, and the orthographic projection of the fifth transistor T5 on the substrate are all located between the orthographic projection of the third level signal line VGH’ on the substrate and the orthographic projection of the first level signal line VGL’ on the substrate.
  • the start signal line STV’, the second clock signal line GCK’, the first clock signal line GCB’ and the third level signal line VGH’ are arranged in sequence.
  • the above-mentioned arrangement of the seventh transistor T7, the eighth transistor T8, the sixth transistor T6 and the fifth transistor T5 in sequence along the first direction reduces the width of the layout space occupied by the seventh transistor T7, the eighth transistor T8, the sixth transistor T6 and the fifth transistor T5 in the second direction, thereby effectively reducing the border width of the display substrate.
  • the orthographic projection of the eighth transistor T8 on the substrate, the orthographic projection of the sixth transistor T6 on the substrate, and the orthographic projection of the fifth transistor T5 on the substrate are all located between the orthographic projection of the third level signal line VGH’ on the substrate and the orthographic projection of the first level signal line VGL’ on the substrate, so as to better plan the limited layout space, simplify the layout complexity, and reduce the layout difficulty of the shift register unit in the limited layout space while ensuring the coupling performance between the transistor and the signal line.
  • the stacking design of each transistor in the shift register unit is optimized, thereby achieving efficient driving of the shift register unit.
  • the second plate C42 of the fourth capacitor C4 and the second plate C52 of the fifth capacitor C5 are illustrated.
  • the fourth capacitor C4 and the fifth capacitor C5 are illustrated.
  • the first plate C41 of the fourth capacitor C4 and the first plate C51 of the fifth capacitor C5 are illustrated.
  • the first output active layer 5s1 included in the first output transistor Ts1, the second output active layer 5s2 included in the second output transistor Ts2, the first debugging active layer 501 included in the first debugging transistor T01, and the second debugging active layer 502 included in the second debugging transistor T02 are schematically shown.
  • the gate T01 - g of the first debugging transistor T01 As shown in FIG. 24 , the gate T01 - g of the first debugging transistor T01 , the gate T5 - g of the fifth transistor T5 , the gate T6 - g of the sixth transistor T6 , the gate T7 - g of the seventh transistor T7 , and the gate T8 - g of the eighth transistor T8 are illustrated.
  • the black dots in FIG25 represent the connection holes between the first source-drain metal layer and the film layer therebelow.
  • the black square holes in FIG27 are used to connect the second level signal line VGL2 ′ and the seventh conductive connection portion 67 .
  • the first conductive connection portion 61 is coupled to the first electrode of the seventh transistor T7.
  • the second conductive connection portion 62 is respectively coupled to an electrode of the third debugging transistor T03 and the gate of the eighth transistor T8, and the gate of the eighth transistor T8 is coupled to the third level signal line VGH'.
  • the third conductive connection portion 63 is respectively coupled to the other electrode of the third debugging transistor T03 , the second gate Ts1 - g2 of the first output transistor Ts1 , and one electrode of the first debugging transistor T01 .
  • the fourth conductive connection portion 64 is respectively coupled to one electrode of the eighth transistor T8 and the first gate Ts1 - g1 of the first output transistor Ts1 .
  • the fifth conductive connection portion 65 is respectively coupled to one electrode of the sixth transistor T6 , the first electrode plate C51 of the fifth capacitor C5 , and one electrode of the fifth transistor T5 .
  • the sixth conductive connection portion 66 is respectively coupled to the first plate C51 of the fifth capacitor C5 and the first gate Ts2 - g1 of the second output transistor Ts2 .
  • the seventh conductive connection portion 67 is coupled to one electrode of the second debugging transistor T02 and the second level signal line VGL2 ′ respectively.
  • a portion of the eighth conductive connection portion 68 and the ninth conductive connection portion 69 may serve as an electrode of the first output transistor Ts1 , and another portion of the ninth conductive connection portion 69 may serve as an electrode of the second output transistor Ts2 .
  • the display substrate provided in the above embodiment includes the shift register unit structure shown in FIG. 9 , but is not limited thereto.
  • An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.
  • the display device may be: a television, a monitor, a digital photo frame, a mobile phone, Any product or component with display function, such as a tablet computer, wherein the display device also includes a flexible unit board, a printed unit board, a backplane, etc.
  • the display substrate provided in the above embodiment can achieve good display effects when including the above shift register unit.
  • the display device provided in the embodiment of the present disclosure also has the above beneficial effects when including the above display substrate, which will not be described in detail here.
  • the signal line extends along the X direction means that the signal line includes a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along the X direction, and the length of the main part extending along the X direction is greater than the length of the secondary part extending along other directions.
  • the "same layer" in the embodiment of the present disclosure may refer to a film layer on the same structural layer.
  • a film layer on the same layer may be a film layer for forming a specific pattern formed by the same film forming process, and then the film layer is patterned by the same mask through a single composition process to form a layer structure.
  • a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.
  • each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments.
  • the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

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Abstract

本公开提供一种移位寄存器单元、显示基板和显示装置。所述移位寄存器单元包括第一输出晶体管，栅极驱动信号输出端，第一输出控制节点，控制信号输入端和第一信号输入端；所述第一输出晶体管包括双栅结构，所述第一输出晶体管的第一栅极与所述第一输出控制节点耦接，所述第一输出晶体管的第二栅极与所述控制信号输入端耦接，所述第一输出晶体管的第一极与所述第一信号输入端耦接，所述第一输出晶体管的第二极与所述栅极驱动信号输出端耦接。

Description

移位寄存器单元、显示基板和显示装置
相关申请的交叉引用
本申请主张在2023年11月30日在中国提交的中国专利申请号No.202311621298.3的优先权，其全部内容通过引用包含于此。
技术领域
本公开涉及显示技术领域，尤其涉及一种移位寄存器单元、显示基板和显示装置。
背景技术
随着显示技术的不断发展，显示产品的应用领域越来越广泛，人们对显示产品的显示质量要求也越来越高。为了进一步缩窄显示装置的边框宽度，提升显示产品的驱动性能，一般采用GOA(Gate On Array)技术，这种GOA技术是将栅极驱动电路集成在显示产品中阵列基板的周边区域，这样在外接电路仅提供几路控制信号的基础上，采用与薄膜晶体管同样制程的工艺制作出该栅极驱动电路，即可实现逐行扫描驱动功能。
栅极驱动电路一般包括多个级联的移位寄存器单元，移位寄存器单元中包括多个薄膜晶体管。相关技术中，薄膜晶体管的特性对移位寄存器单元输出的栅极驱动信号的稳定性具有一定的影响，从而影响了显示产品的显示质量。
发明内容
本公开的目的在于提供一种移位寄存器单元、显示基板和显示装置。
为了实现上述目的，本公开提供如下技术方案：
本公开的第一方面提供一种移位寄存器单元，包括第一输出晶体管，栅极驱动信号输出端，第一输出控制节点，控制信号输入端和第一信号输入端；
所述第一输出晶体管包括双栅结构，所述第一输出晶体管的第一栅极与所述第一输出控制节点耦接，所述第一输出晶体管的第二栅极与所述控制信 号输入端耦接，所述第一输出晶体管的第一极与所述第一信号输入端耦接，所述第一输出晶体管的第二极与所述栅极驱动信号输出端耦接。
可选的，所述移位寄存器单元还包括第二输出晶体管，第二输出控制节点和第一电平信号输入端，所述第二输出晶体管的栅极与所述第二输出控制节点耦接，所述第二输出晶体管的第一极与所述第一电平信号输入端耦接，所述第二输出晶体管的第二极与所述栅极驱动信号输出端耦接；
所述第一信号输入端包括第一时钟信号输入端；所述移位寄存器单元还包括第二电平信号输入端，第三电平信号输入端和控制信号调试单元，所述控制信号调试单元包括第一调试子单元和第二调试子单元；
所述第一调试子单元分别与所述第一时钟信号输入端，所述第二输出控制节点，所述第二电平信号输入端和所述控制信号输入端耦接，用于在所述第一时钟信号输入端和所述第二输出控制节点的控制下，控制导通或断开所述第二电平信号输入端和所述控制信号输入端之间的电连接；
所述第二调试子单元分别与所述第一输出控制节点，第三电平信号输入端和所述控制信号输入端耦接，用于在所述第一输出控制节点的控制下，控制导通或断开所述第三电平信号输入端与所述控制信号输入端之间的电连接。
可选的，所述第一调试子单元包括第一调试晶体管和第二调试晶体管；所述第二调试子单元包括第三调试晶体管；
所述第一调试晶体管的栅极与所述第一时钟信号输入端耦接，所述第一调试晶体管的第一极与所述第二调试晶体管的第二极耦接，所述第一调试晶体管的第二极与所述控制信号输入端耦接；
所述第二调试晶体管的栅极与所述第二输出控制节点耦接，所述第二调试晶体管的第一极与所述第二电平信号输入端耦接；
所述第三调试晶体管的栅极与所述第一输出控制节点耦接，所述第三调试晶体管的第一极与所述第三电平信号输入端耦接，所述第三调试晶体管的第二极与所述控制信号输入端耦接。
可选的，所述移位寄存器单元还包括：第一节点控制单元，第二节点控制单元，第二时钟信号输入端和起始信号输入端；
所述第一节点控制单元分别与所述第二时钟信号输入端，所述第一输出控制节点和所述起始信号输入端耦接；用于在所述第二时钟信号输入端的控制下，控制导通或断开所述初始信号输入端与所述第一输出控制节点之间的电连接；
所述第二节点控制单元分别与所述第一时钟信号输入端，所述第二时钟信号输入端，第一电平信号输入端，第三电平信号输入端和第二输出控制节点耦接，用于在所述第一时钟信号输入端的控制下，控制导通或断开所述第一电平信号输入端和所述第二输出控制节点之间的电连接，以及用于在所述第二时钟信号输入端的控制下，控制导通或断开所述第三电平信号输入端和所述第二输出控制节点之间的电连接；或者，所述第二节点控制单元分别与所述第二时钟信号输入端，所述第一输出控制节点，所述第二输出控制节点和所述第三电平信号输入端耦接，用于在所述第二时钟信号输入端的控制下，控制导通或断开所述第三电平信号输入端与所述第二输出控制节点之间的电连接；以及用于在所述第一输出控制节点的控制下，控制导通或断开所述第二时钟信号输入端与所述第二输出控制节点之间的电连接。
可选的，所述第一节点控制单元还分别与所述第一时钟信号输入端，所述第二输出控制节点，所述第一电平信号输入端耦接；用于在所述第一时钟信号输入端和所述第二输出控制节点的控制下，控制导通或断开所述第一电平信号输入端与所述第一输出控制节点之间的电连接。
可选的，所述第一信号输入端包括第一电平信号输入端，所述控制信号输入端包括第二电平信号输入端，所述第二电平信号输入端用于输入直流的第二电平信号；
所述移位寄存器单元还包括：第二输出晶体管，第二输出控制节点和第三电平信号输入端，所述第二输出晶体管的栅极与所述第二输出控制节点耦接，所述第二输出晶体管的第一极与所述第三电平信号输入端耦接，所述第二输出晶体管的第二极与所述栅极驱动信号输出端耦接。
可选的，所述移位寄存器单元还包括第一节点控制单元，所述第一节点控制单元分别与所述第二输出控制节点，所述第一电平信号输入端和所述第一输出控制节点耦接，用于在所述第二输出控制节点的控制下控制导通或断 开所述第一电平信号输入端和所述第一输出控制节点之间的电连接。
可选的，所述第一节点控制单元还与所述第二电平信号输入端耦接；所述第一节点控制单元包括：第一控制晶体管，所述第一控制晶体管包括双栅结构，所述第一控制晶体管的第一栅极与所述第二输出控制节点耦接，所述第一控制晶体管的第二栅极与所述第二电平信号输入端耦接，所述第一控制晶体管的第一极与所述第一电平信号输入端耦接，所述第一控制晶体管的第二极与所述第一输出控制节点耦接。
可选的，所述移位寄存器单元还包括第二节点控制单元，第三时钟信号输入端和起始信号输入端；所述第二节点控制单元分别与所述第三时钟信号输入端，所述起始信号输入端和所述第二输出控制节点耦接，用于在所述第三时钟信号输入端的控制下，控制导通或断开所述起始信号输入端和所述第二输出控制节点之间的电连接。
可选的，所述第二节点控制单元还与所述第三电平信号输入端耦接；所述第二节点控制单元包括：第二控制晶体管，第三控制晶体管和第四控制晶体管；
所述第二控制晶体管的栅极与所述第三时钟信号输入端耦接，所述第二控制晶体管的第一极与所述起始信号输入端耦接，所述第二控制晶体管的第二极与所述第三控制晶体管的第一极耦接；
所述第三控制晶体管的栅极与所述第三时钟信号输入端耦接，所述第三控制晶体管的第二极与所述第二输出控制节点耦接。
所述第四控制晶体管的栅极与所述第二输出控制节点耦接，所述第四控制晶体管的第一极与所述第三电平信号输入端耦接，所述第四控制晶体管的第二极与所述第三控制晶体管的第一极耦接。
可选的，所述第一节点控制单元还分别与第一电平信号输入端，第三电平信号输入端和起始信号输入端耦接；用于在所述第一电平信号输入端和所述起始信号输入端的控制下，控制导通或断开所述第三电平信号输入端与所述第一输出控制节点之间的电连接。
基于上述移位寄存器单元的技术方案，本公开的第二方面提供一种显示基板，包括上述移位寄存器单元，所述显示基板包括显示区域和位于所述显 示区域周边的周边区域，所述移位寄存器单元位于所述显示区域和/或所述周边区域。
可选的，所述移位寄存器单元包括控制信号调试单元，所述控制信号调试单元包括第一调试子单元和第二调试子单元，所述第一调试子单元包括第一调试晶体管和第二调试晶体管；所述第二调试子单元包括第三调试晶体管；所述移位寄存器单元还包括第一输出晶体管和第二输出晶体管；
所述第一输出晶体管和所述第二输出晶体管沿第一方向排列；所述第三调试晶体管的至少部分，所述第一调试晶体管和所述第二调试晶体管沿所述第一方向排列；所述第一输出晶体管位于所述显示区域和所述第一调试晶体管之间。
可选的，所述第二调试晶体管和所述第二输出晶体管均包括双栅结构，所述第二调试晶体管的第一栅极与所述第二输出晶体管的第一栅极形成为一体结构，所述第二调试晶体管的第二栅极与所述第二输出晶体管的第二栅极形成为一体结构。
可选的，所述第三调试晶体管的栅极与所述第一输出晶体管的第一栅极形成为一体结构。
可选的，所述显示基板还包括第二电平信号线，所述第二电平信号线作为第二电平信号输入端与所述第二调试晶体管耦接；
所述第一调试晶体管包括第一调试有源层，所述第二调试晶体管包括第二调试有源层，所述第三调试晶体管包括第三调试有源层；
所述第二电平信号线在所述显示基板的衬底基板上的正投影，与所述第一调试有源层在所述显示基板的衬底基板上的正投影至少部分交叠；和/或，所述第二电平信号线在所述显示基板的衬底基板上的正投影，与所述第二调试有源层在所述显示基板的衬底基板上的正投影至少部分交叠；和/或，所述第二电平信号线在所述显示基板的衬底基板上的正投影，与所述第三调试有源层在所述显示基板的衬底基板上的正投影至少部分交叠。
可选的，所述显示基板还包括第一电平信号线和第三电平信号线；所述第一电平信号线作为第一电平信号输入端与第二输出晶体管耦接；所述第三电平信号线作为第三电平信号输入端与所述第三调试晶体管耦接；
沿靠近所述显示区域的方向，所述第三电平信号线在所述衬底基板上的正投影，所述第一电平信号线在所述衬底基板上的正投影，以及所述第二电平信号线在所述衬底基板上的正投影依次排列。
可选的，所述显示基板还包括第一时钟信号线，第二时钟信号线和起始信号线，所述第一时钟信号线作为第一时钟信号输入端与所述第一调试晶体管耦接；所述移位寄存器单元还包括第五晶体管，第六晶体管，第七晶体管和第八晶体管；
所述第五晶体管的栅极与所述第二时钟信号线耦接，所述第五晶体管的第一极与所述第三电平信号线耦接，所述第五晶体管的第二极与所述第二输出晶体管的栅极耦接；
所述第六晶体管的栅极与所述第一时钟信号线耦接，所述第六晶体管的第一极与所述第一电平信号线耦接，所述第六晶体管的第二极与所述第二输出晶体管的栅极耦接；
所述第七晶体管的栅极与所述第二时钟信号线耦接，所述第七晶体管的第一极与起始信号线耦接，所述第七晶体管的第二极与第八晶体管的第一极耦接，所述第八晶体管的第二极与所述第一输出晶体管的栅极耦接，所述第八晶体管的栅极与所述第三电平信号线耦接；
所述第七晶体管，所述第八晶体管，所述第六晶体管和所述第五晶体管沿所述第一方向依次排列；所述第七晶体管在所述衬底基板上的正投影，所述第八晶体管在所述衬底基板上的正投影，所述第六晶体管在所述衬底基板上的正投影，以及所述第五晶体管在所述衬底基板上的正投影，均位于所述第三电平信号线在所述衬底基板上的正投影和所述第一电平信号线在所述衬底基板上的正投影之间。
可选的，沿靠近所述显示区域的方向，所述起始信号线，所述第二时钟信号线，所述第一时钟信号线和所述第三电平信号线依次排列。
基于上述显示基板的技术方案，本公开的第三方面提供一种显示装置，包括上述显示基板。
附图说明
此处所说明的附图用来提供对本公开的进一步理解，构成本公开的一部 分，本公开的示意性实施例及其说明用于解释本公开，并不构成对本公开的不当限定。在附图中：
图1为本公开实施例提供的移位寄存器单元的一种电路结构示意图；
图2为对应图1电路结构的时序图；
图3为对应图1电路结构的阈值电压偏移不同电压值对应的栅极驱动信号的波形图；
图4为本公开实施例提供的一种双栅晶体管的结构示意图；
图5为本公开实施例提供的不同底栅电压对应的特性曲线示意图；
图6为本公开实施例提供的一种双栅晶体管的结构示意图；
图7为本公开实施例提供的顶栅和底栅对应的波形示意图；
图8为本公开实施例提供的第二电平信号的电压值变化对应的控制信号输入端电压变化示意图；
图9本公开实施例提供的移位寄存器单元的一种电路结构示意图；
图10为图9对应的时序图；
图11为对应图9电路结构的阈值电压偏移不同电压值对应的栅极驱动信号的波形图；
图12本公开实施例提供的移位寄存器单元的一种电路结构示意图；
图13本公开实施例提供的移位寄存器单元的一种电路结构示意图；
图14本公开实施例提供的移位寄存器单元的一种电路结构示意图；
图15为对应图14电路结构的阈值电压偏移不同电压值对应的栅极驱动信号的波形图；
图16本公开实施例提供的移位寄存器单元的一种电路结构示意图；
图17为对应图16电路结构的阈值电压偏移不同电压值对应的栅极驱动信号的波形图；
图18本公开实施例提供的移位寄存器单元的第一栅金属层的布局示意图；
图19为在图18的基础上增加第二栅金属层的布局示意图；
图20为图19中增加的第二栅金属层的布局示意图；
图21为在图19的基础上增加氧化物有源层的布局示意图；
图22为图21中增加的氧化物有源层的布局示意图；
图23为在图21的基础上增加第三栅金属层的布局示意图；
图24为图23中增加的第三栅金属层的布局示意图；
图25为在图23的基础上增加第一源漏金属层的布局示意图；
图26为图25中增加的第一源漏金属层的布局示意图；
图27为在图25的基础上增加第二源漏金属层的布局示意图。
具体实施方式
为了进一步说明本公开实施例提供的移位寄存器单元、显示基板和显示装置，下面结合说明书附图进行详细描述。
请参阅图9至图14，本公开实施例提供了一种移位寄存器单元，包括第一输出晶体管Ts1，栅极驱动信号输出端OUT，第一输出控制节点N1，控制信号输入端K0和第一信号输入端X0；
所述第一输出晶体管Ts1包括双栅结构，所述第一输出晶体管Ts1的第一栅极与所述第一输出控制节点N1耦接，所述第一输出晶体管Ts1的第二栅极与所述控制信号输入端K0耦接，所述第一输出晶体管Ts1的第一极与所述第一信号输入端X0耦接，所述第一输出晶体管Ts1的第二极与所述栅极驱动信号输出端OUT耦接。
示例性的，所述移位寄存器单元应用于栅极驱动电路，所述栅极驱动电路包括级联的多个移位寄存器单元。例如：所述移位寄存器单元包括栅极控制移位寄存器单元(Gate GOA)和发光控制移位寄存器单元(EM GOA)等，但不仅限于此。
示例性的，显示装置包括显示区域和位于所述显示区域周边的周边区域，所述显示区域包括阵列分布的多个子像素，所述多个子像素包括的多个子像素驱动电路划分为多行子像素驱动电路行。
示例性的，所述显示装置还包括多条栅线，所述栅线与对应的一行子像素驱动电路行中的各子像素驱动电路分别耦接，用于为各子像素驱动电路提供栅极信号。以子像素驱动电路采用7T1C(即包括7个晶体管和1个电容)电路结构为例，该子像素驱动电路中包括的补偿晶体管和/或数据写入晶体管 可以与所述栅线耦接，但不仅限于此。示例性的，在所述周边区域，所述栅极驱动电路包括栅极控制栅极驱动电路，该栅极控制栅极驱动电路包括级联的多个Gate GOA，每个Gate GOA的栅极驱动信号输出端OUT与对应的所述栅线耦接。
示例性的，所述显示装置还包括多条发光控制信号线，所述发光控制信号线与对应的一行子像素驱动电路行中的各子像素驱动电路分别耦接，用于为各子像素驱动电路提供发光控制信号。以子像素驱动电路采用7T1C电路结构为例，该子像素驱动电路中包括的电源控制晶体管和发光控制晶体管可以与所述发光控制信号线耦接，但不仅限于此。示例性的，在所述周边区域，所述栅极驱动电路包括发光控制栅极驱动电路，该发光控制栅极驱动电路包括级联的多个EM GOA，每个EM GOA的栅极驱动信号输出端OUT与对应的所述发光控制信号线耦接。
示例性的，所述移位寄存器单元包括多个晶体管，所述晶体管包括氧化物晶体管，但不仅限于此。
示例性的，所述第一极包括源极，所述第二极包括漏极；或者，所述第一极包括漏极，所述第二极包括源极。
示例性的，所述第一输出晶体管Ts1的第一栅极与所述第一输出控制节点N1耦接，所述第一输出晶体管Ts1的第二栅极与所述控制信号输入端K0耦接，所述第一输出晶体管Ts1用于在所述第一输出控制节点N1和所述控制信号输入端K0的共同控制下，实现导通或断开所述第一信号输入端X0与所述栅极驱动信号输出端OUT之间的电连接。
更详细地说，如图1和图2所示，为移位寄存器单元中在第一输出晶体管Ts1出现阈值电压偏移(VTH Shift)后，如：负偏后，各节点和栅极驱动信号输出端OUT输出波形异常的示意图。产生该异常的主要原因为：负偏漏电导致第一输出晶体管Ts1开启，寄生电容增加引起第一时钟信号输入端GCB与栅极驱动信号输出端OUT耦合、漏电，导致信号波形产生毛刺，进而导致在VTH Shift负偏后出现屏幕Mura。通过仿真得到，主要晶体管负偏点为第一输出晶体管Ts1，因此改善第一输出晶体管Ts1结构以及其控制信号，能够改善第一输出晶体管Ts1结构的负偏，进而改善输出的栅极驱动信号。需 要说明的是，图2中的N3代表图1中位于第七晶体管T7和第八晶体管T8之间的节点。
如图4所示，在设置所述第一输出晶体管Ts1采用双栅结构时，定义所述第一输出晶体管Ts1的第一栅极为顶栅TG，所述第一输出晶体管Ts1的第二栅极为底栅BG，通过调控底栅BG的电压能够调控第一输出晶体管Ts1的阈值电压。
如图5所示，示意了底栅BG电位对晶体管特性的影响，图中横坐标代表VGS1，即晶体管的顶栅TG与源极之间的电压差值，图中纵坐标代表Ids，即晶体管的源漏极之间的电流。图中示意了底栅BG的电压分别设置为0V、2V、4V、6V、-2V、-4V、-6V时，对特性曲线的影响。因此，通过调整底栅BG的电压可以对晶体管的特性曲线进行调控，使得晶体管即使出现负偏也能够通过底栅BG的控制调整回来。
如图6所示，示意了第一输出晶体管Ts1的一种连接方式，第一输出晶体管Ts1的第一极耦接第一时钟信号输入端GCB，第一输出晶体管Ts1的第二极耦接栅极驱动信号输出端OUT。如图7所示，所述第一输出晶体管Ts1的VGS1为第一输出晶体管Ts1的顶栅TG与源极之间的电压差值，所述第一输出晶体管Ts1的VGS2为第一输出晶体管Ts1的底栅BG与源极之间的电压差值。底栅BG的信号波形会随着顶栅TG的信号波形进行变化，同时也能受到控制信号输入端K0的控制。图7中的第一个深色区域示意了VGS2＞0，第二个深色区域示意了VGS2＝0，能够第三个深色区域示意了VGS2＜0。设置这种波形的VGS2能够实现调整第一输出晶体管Ts1特性正偏。
如图3所示，示意了对第一输出晶体管Ts1进行改善之前，第一输出晶体管Ts1的VTH Shift从-5V偏压至+5V时，输出的栅极驱动信号的波形。可见偏压在-5V至-2V之间时，输出的栅极驱动信号存在波动。如图11所示，示意了对第一输出晶体管Ts1进行改善之后，第一输出晶体管Ts1的VTH Shift从-5V偏压至+5V时，输出的栅极驱动信号的波形。可见偏压在-5V至+5V之间时，输出的栅极驱动信号均不存在波动。
根据上述移位寄存器单元的具体结构可知，本公开实施例提供的移位寄存器单元中，设置所述第一输出晶体管Ts1包括双栅结构，所述第一输出晶 体管Ts1的第一栅极与所述第一输出控制节点N1耦接，所述第一输出晶体管Ts1的第二栅极与所述控制信号输入端K0耦接，所述第一输出晶体管Ts1的第一极与所述第一信号输入端X0耦接，所述第一输出晶体管Ts1的第二极与所述栅极驱动信号输出端OUT耦接。通过所述第一栅极和所述第二栅极能够控制所述第一输出晶体管Ts1的导通或截止，保证移位寄存器单元的正常工作。通过调整所述第二栅极的电压，能够调节所述第一输出晶体管Ts1的特性曲线，从而有效改善第一输出晶体管Ts1的负偏，改善输出的栅极驱动信号的波动。
需要说明的是，在氧化物显示产品的生产过程中，氧化物晶体管容易发生负偏进而造成移位寄存器单元失效，为了兼顾工艺Margin，需要对氧化物晶体管进行工艺Margin改善。本公开实施例提供的移位寄存器单元中，通过设置所述第一输出晶体管Ts1包括双栅结构，通过调试所述第一输出晶体管Ts1的第二栅极的电压，实现了对第一输出晶体管Ts1的特性曲线进行调控，使得第一输出晶体管Ts1即使出现负偏也能够通过底栅BG的控制调整回来。因此，本公开实施例提供的移位寄存器单元中，实现了对第一输出晶体管Ts1的工艺Margin改善，使得所述第一输出晶体管Ts1具有能够兼容更大范围负偏的能力，保证了输出的栅极驱动信号的稳定性。
如图9至图13所示，在一些实施例中，所述移位寄存器单元还包括第二输出晶体管Ts2，第二输出控制节点N2和第一电平信号输入端VGL，所述第二输出晶体管Ts2的栅极与所述第二输出控制节点N2耦接，所述第二输出晶体管Ts2的第一极与所述第一电平信号输入端VGL耦接，所述第二输出晶体管Ts2的第二极与所述栅极驱动信号输出端OUT耦接；
所述第一信号输入端X0包括第一时钟信号输入端GCB；所述移位寄存器单元还包括第二电平信号输入端VGL2，第三电平信号输入端VGH和控制信号调试单元，所述控制信号调试单元包括第一调试子单元11和第二调试子单元12；
所述第一调试子单元11分别与所述第一时钟信号输入端GCB，所述第二输出控制节点N2，所述第二电平信号输入端VGL2和所述控制信号输入端K0耦接，用于在所述第一时钟信号输入端GCB和所述第二输出控制节点N2的控 制下，控制导通或断开所述第二电平信号输入端VGL2和所述控制信号输入端K0之间的电连接；
所述第二调试子单元12分别与所述第一输出控制节点N1，第三电平信号输入端VGH和所述控制信号输入端K0耦接，用于在所述第一输出控制节点N1的控制下，控制导通或断开所述第三电平信号输入端VGH与所述控制信号输入端K0之间的电连接。
示例性的，所述第一调试子单元11包括第一调试晶体管T01和第二调试晶体管T02；所述第二调试子单元12包括第三调试晶体管T03；所述第一调试晶体管T01的栅极与所述第一时钟信号输入端GCB耦接，所述第一调试晶体管T01的第一极与所述第二调试晶体管T02的第二极耦接，所述第一调试晶体管T01的第二极与所述控制信号输入端K0耦接；所述第二调试晶体管T02的栅极与所述第二输出控制节点N2耦接，所述第二调试晶体管T02的第一极与所述第二电平信号输入端VGL2耦接；所述第三调试晶体管T03的栅极与所述第一输出控制节点N1耦接，所述第三调试晶体管T03的第一极与所述第三电平信号输入端VGH耦接，所述第三调试晶体管T03的第二极与所述控制信号输入端K0耦接。
示例性的，在所述第一输出控制节点N1传输的信号处于非有效电平时，所述第二调试子单元12在所述第一输出控制节点N1的控制下，控制断开所述第三电平信号输入端VGH与所述控制信号输入端K0之间的电连接，即所述第三调试晶体管T03截止。在所述第一时钟信号输入端GCB传输的信号和所述第二输出控制节点N2传输的信号处于有效电平时，所述第一调试子单元11在所述第一时钟信号输入端GCB和所述第二输出控制节点N2的控制下，控制导通所述第二电平信号输入端VGL2和所述控制信号输入端K0之间的电连接，即所述第一调试晶体管T01和所述第二调试晶体管T02均导通，使所述控制信号输入端K0的电位受所述第二电平信号输入端VGL2控制。如图8所示，示意了第二电平信号输入端VGL2输入的第二电平信号的电压值在从-6V变化到-14V的过程中，控制信号输入端K0的电压对应的变化范围在-6V至-12V。
示例性的，在所述第一时钟信号输入端GCB传输的信号和所述第二输出 控制节点N2传输的信号处于非有效电平时，所述第一调试子单元11在所述第一时钟信号输入端GCB和所述第二输出控制节点N2的控制下，控制断开所述第二电平信号输入端VGL2和所述控制信号输入端K0之间的电连接，即所述第一调试晶体管T01和所述第二调试晶体管T02均截止。在所述第一输出控制节点N1传输的信号处于有效电平时，所述第二调试子单元12在所述第一输出控制节点N1的控制下，控制导通所述第三电平信号输入端VGH与所述控制信号输入端K0之间的电连接，即所述第三调试晶体管T03导通，使所述控制信号输入端K0的电位受所述第三电平信号输入端VGH控制。
上述实施例提供的移位寄存器单元中，所述控制信号调试单元可以针对不同的工作阶段，即所述第一输出晶体管Ts1所处的不同工作状态，适应性的调整所述控制信号输入端K0的电位，从而使得所述第一输出晶体管Ts1的第二栅极的电位能够在不同的工作阶段适应性的调整，因此，上述实施例提供的移位寄存器单元能够根据第一输出晶体管Ts1的不同工作状态，适应性调整其特性曲线，在有效改善第一输出晶体管Ts1的负偏问题的同时，能够进一步提升栅极驱动信号的输出稳定性，降低晶体管的功耗。
如图9，图12和图13所示，在一些实施例中，所述移位寄存器单元还包括：第一节点控制单元21，第二节点控制单元22，第二时钟信号输入端GCK和起始信号输入端STV；
所述第一节点控制单元21分别与所述第二时钟信号输入端GCK，所述第一输出控制节点N1和所述起始信号输入端STV耦接；用于在所述第二时钟信号输入端GCK的控制下，控制导通或断开所述初始信号输入端与所述第一输出控制节点N1之间的电连接；
如图9所示，所述第二节点控制单元22分别与所述第一时钟信号输入端GCB，所述第二时钟信号输入端GCK，第一电平信号输入端VGL，第三电平信号输入端VGH和第二输出控制节点N2耦接，用于在所述第一时钟信号输入端GCB的控制下，控制导通或断开所述第一电平信号输入端VGL和所述第二输出控制节点N2之间的电连接，以及用于在所述第二时钟信号输入端GCK的控制下，控制导通或断开所述第三电平信号输入端VGH和所述第二输出控制节点N2之间的电连接；或者，如图12和图13所示，所述第二节点控制单元 22分别与所述第二时钟信号输入端GCK，所述第一输出控制节点N1，所述第二输出控制节点N2和所述第三电平信号输入端VGH耦接，用于在所述第二时钟信号输入端GCK的控制下，控制导通或断开所述第三电平信号输入端VGH与所述第二输出控制节点N2之间的电连接；以及用于在所述第一输出控制节点N1的控制下，控制导通或断开所述第二时钟信号输入端GCK与所述第二输出控制节点N2之间的电连接。
示例性的，所述第一节点控制单元21包括第七晶体管T7，所述第七晶体管T7的栅极与所述第二时钟信号输入端GCK耦接，所述第七晶体管T7的第一极与所述起始信号输入端STV耦接，所述第七晶体管T7的第二极与所述第一输出控制节点N1耦接。
示例性的，如图9所示，所述第二节点控制单元22包括第五晶体管T5和第六晶体管T6，所述第五晶体管T5的栅极与所述第二时钟信号输入端GCK耦接，所述第五晶体管T5的第一极与第三电平信号输入端VGH耦接，所述第五晶体管T5的第二极与第二输出控制节点N2耦接。所述第六晶体管T6的栅极与所述第一时钟信号输入端GCB耦接，所述第六晶体管T6的第一极与第一电平信号输入端VGL耦接，所述第六晶体管T6的第二极与第二输出控制节点N2耦接。
如图10所示，在P1阶段，N2＝高电平，N3＝高电平，N1＝高电平，OUT＝低电平；在P2阶段，N2＝低电平，N3＝高电平，N1＝高电平，OUT＝高电平；在P3阶段，N2＝高电平，N3＝低电平，N1＝低电平，OUT＝低电平，在P4阶段，N2＝高电平，N3＝低电平，N1＝低电平，OUT＝低电平。基于上述节点的电位情况能够计算可以得到每个晶体管工作时的VGS电压。
示例性的，如图12和图13所示，所述第二节点控制单元22包括所述第五晶体管T5和第九晶体管T9，第九晶体管T9的栅极与所述第一输出控制节点N1耦接，第九晶体管T9的第一极与所述第二时钟信号输入端GCK耦接，第九晶体管T9的第二极与第二输出控制节点N2耦接。
示例性的，所述移位寄存器单元还包括第八晶体管T8，所述第八晶体管T8的栅极与第三电平信号输入端VGH耦接，所述第八晶体管T8的第一极与第七晶体管T7的第二极耦接，所述第八晶体管T8的第二极与所述第一输出 控制节点N1耦接。所述移位寄存器单元还包括第四电容C4，所述第四电容C4的第一极板与所述第一输出控制节点N1耦接，所述第四电容C4的第二极板与栅极驱动信号输出端OUT耦接。
需要说明的是，如图13所示，在所述移位寄存器单元还包括第八晶体管T8的情况下，第七晶体管T7的第二极，第九晶体管T9的栅极，以及第十一晶体管T11的第二极均通过第八晶体管T8实现与所述第一输出控制节点N1耦接。
如图13所示，在一些实施例中，所述第一节点控制单元21还分别与所述第一时钟信号输入端GCB，所述第二输出控制节点N2，所述第一电平信号输入端VGL耦接；用于在所述第一时钟信号输入端GCB和所述第二输出控制节点N2的控制下，控制导通或断开所述第一电平信号输入端VGL与所述第一输出控制节点N1之间的电连接。
示例性的，所述第一节点控制单元21还包括第十晶体管T10和第十一晶体管T11。第十晶体管T10的栅极与所述第二输出控制节点N2耦接，第十晶体管T10的第一极与所述第一电平信号输入端VGL耦接，第十晶体管T10的第二极与第十一晶体管T11的第一极耦接，第十一晶体管T11的第二极与所述第一输出控制节点N1耦接，第十一晶体管T11的栅极与所述第一时钟信号输入端GCB耦接。
如图14至图17所示，在一些实施例中，所述第一信号输入端X0包括第一电平信号输入端VGL，所述控制信号输入端K0包括第二电平信号输入端VGL2，所述第二电平信号输入端VGL2用于输入直流的第二电平信号；
所述移位寄存器单元还包括：第二输出晶体管Ts2，第二输出控制节点N2和第三电平信号输入端VGH，所述第二输出晶体管Ts2的栅极与所述第二输出控制节点N2耦接，所述第二输出晶体管Ts2的第一极与所述第三电平信号输入端VGH耦接，所述第二输出晶体管Ts2的第二极与所述栅极驱动信号输出端OUT耦接。
需要说明，上述方案仅限于所述第一输出晶体管Ts1的源极为固定电位，源极电压不能随意变换，否则VGS2也会随着变化，造成特性变化。上述设置所述第一信号输入端X0包括第一电平信号输入端VGL，使得所述第一输出晶体 管Ts1的源极具有与第一电平信号相同的固定电位，通过设置所述控制信号输入端K0包括第二电平信号输入端VGL2，使得通过所述第二栅极的电压，能够调节所述第一输出晶体管Ts1的特性曲线，从而有效改善第一输出晶体管Ts1的负偏，改善输出的栅极驱动信号的波动。
在一些实施例中，所述移位寄存器单元还包括第一节点控制单元21，所述第一节点控制单元21分别与所述第二输出控制节点N2，所述第一电平信号输入端VGL和所述第一输出控制节点N1耦接，用于在所述第二输出控制节点N2的控制下控制导通或断开所述第一电平信号输入端VGL和所述第一输出控制节点N1之间的电连接。
如图16和图17所示，在一些实施例中，所述第一节点控制单元21还与所述第二电平信号输入端VGL2耦接；所述第一节点控制单元21包括：第一控制晶体管Tk1，所述第一控制晶体管Tk1包括双栅结构，所述第一控制晶体管Tk1的第一栅极与所述第二输出控制节点N2耦接，所述第一控制晶体管Tk1的第二栅极与所述第二电平信号输入端VGL2耦接，所述第一控制晶体管Tk1的第一极与所述第一电平信号输入端VGL耦接，所述第一控制晶体管Tk1的第二极与所述第一输出控制节点N1耦接。
上述设置所述第一控制晶体管Tk1包括双栅结构，使得通过所述第一控制晶体管Tk1的第二栅极的电压，能够调节所述第一控制晶体管Tk1的特性曲线，从而有效改善第一控制晶体管Tk1的负偏，改善输出的栅极驱动信号的波动。
更详细地说，如图17所示，示意了对第一控制晶体管Tk1进行改善之后，第一控制晶体管Tk1的VTH Shift从-5V偏压至+5V时，输出的栅极驱动信号的波形。可见偏压在-3V至+3V之间时，输出的栅极驱动信号均不存在波动。
如图16所示，在一些实施例中，所述移位寄存器单元还包括第二节点控制单元22，第三时钟信号输入端CK和起始信号输入端STV；所述第二节点控制单元22分别与所述第三时钟信号输入端CK，所述起始信号输入端STV和所述第二输出控制节点N2耦接，用于在所述第三时钟信号输入端CK的控制下，控制导通或断开所述起始信号输入端STV和所述第二输出控制节点N2之间的电连接。
示例性的，所述第二节点控制单元22包括第十四晶体管T14，第十四晶体管T14的栅极与第三时钟信号输入端CK耦接，第十四晶体管T14的第一极与起始信号输入端STV耦接，第十四晶体管T14的第二极与第二输出控制节点N2耦接。
如图14和图15所示，在一些实施例中，所述第二节点控制单元22还与所述第三电平信号输入端VGH耦接；所述第二节点控制单元22包括：第二控制晶体管Tk2，第三控制晶体管Tk3和第四控制晶体管Tk4；
所述第二控制晶体管Tk2的栅极与所述第三时钟信号输入端CK耦接，所述第二控制晶体管Tk2的第一极与所述起始信号输入端STV耦接，所述第二控制晶体管Tk2的第二极与所述第三控制晶体管Tk3的第一极耦接；
所述第三控制晶体管Tk3的栅极与所述第三时钟信号输入端CK耦接，所述第三控制晶体管Tk3的第二极与所述第二输出控制节点N2耦接。
所述第四控制晶体管Tk4的栅极与所述第二输出控制节点N2耦接，所述第四控制晶体管Tk4的第一极与所述第三电平信号输入端VGH耦接，所述第四控制晶体管Tk4的第二极与所述第三控制晶体管Tk3的第一极耦接。
示例性的，所述第四控制晶体管Tk4的沟道宽长比大于所述第二控制晶体管Tk2的沟道宽长比；和/或，所述第四控制晶体管Tk4的沟道宽长比大于所述第三控制晶体管Tk3的沟道宽长比。
更详细地说，所述第四控制晶体管Tk4的沟道宽长比越大，沟道电阻越小，更有利于漏电流向所述第四控制晶体管Tk4传输，实现对漏电流的吸收。
如图15所示，示意了在设置所述第二节点控制单元22包括：第二控制晶体管Tk2，第三控制晶体管Tk3和第四控制晶体管Tk4时，在第二控制晶体管Tk2和第三控制晶体管Tk3的VTH Shift从-5V偏压至+5V时，输出的栅极驱动信号的波形。可见偏压在-4V至2V之间时，第四控制晶体管Tk4均能够很好的吸收漏电流，实现输出稳定的栅极驱动信号。
上述实施例提供的移位寄存器单元中，通过设置所述第二节点控制单元22包括：第二控制晶体管Tk2，第三控制晶体管Tk3和第四控制晶体管Tk4，不仅能够保证信号通过第二控制晶体管Tk2和第三控制晶体管Tk3实现传输，还能够通过沟道宽长比更大的第四控制晶体管Tk4吸收由于晶体管发生特性 偏移而产生的漏电流信号，这样即使在第二控制晶体管Tk2和第三控制晶体管Tk3发生特性偏移的情况下，也能够保证移位寄存器单元正常输出栅极驱动信号。因此，上述实施例提供的移位寄存器单元中，有效改善了由于晶体管特性偏移，漏电流增大，导致的输出栅极驱动信号不稳定的问题，保证了对显示区域的正常驱动，从而保证了显示产品的显示质量。
上述同时设置所述第一输出晶体管Ts1和所述第一控制晶体管Tk1采用双栅结构，使得可以通过调整晶体管第二栅极接收的第二电平信号，对晶体管的特性进行调控，使得即使晶体管出现负偏，也能够通过第二栅极的电位改变，优化VTH Margin，从而保证输出稳定的栅极驱动信号。
如图14和图16所示，在一些实施例中，所述第一节点控制单元21还分别与第一电平信号输入端VGL，第三电平信号输入端VGH和起始信号输入端STV耦接；用于在所述第一电平信号输入端VGL和所述起始信号输入端STV的控制下，控制导通或断开所述第三电平信号输入端VGH与所述第一输出控制节点N1之间的电连接。
示例性的，所述第一节点控制单元21包括第一晶体管T1，第二晶体管T2和第一电容C1。所述第一晶体管T1的栅极与所述第二晶体管T2的第二极耦接，所述第一晶体管T1的第一极与所述第三电平信号输入端VGH耦接，所述第一晶体管T1的第二极与第一输出控制节点N1耦接。所述第二晶体管T2的栅极与起始信号输入端STV耦接，所述第二晶体管T2的第一极与第一电平信号输入端VGL耦接。所述第一电容C1的第一极板与第三时钟信号输入端CK耦接，所述第一电容C1的第二极板与所述第一晶体管T1的栅极耦接。
示例性的，所述移位寄存器单元还包括第四晶体管T4，所述第四晶体管T4的栅极与所述第三电平信号输入端VGH耦接，所述第四晶体管T4的第一极与所述第一晶体管T1的第二极耦接，所述第四晶体管T4的第二极与第一输出控制节点N1耦接。所述移位寄存器单元还包括第二电容C2和第三电容C3，第二电容C2的第一极板与第一输出控制节点N1耦接，第二电容C2的第二极板与栅极驱动信号输出端OUT耦接。第三电容C3的第一极板与栅极驱动信号输出端OUT耦接，第三电容C3的第二极板与所述第二输出晶体管Ts2的栅极耦接。
如图18至图27所示，本公开实施例还提供了一种显示基板，包括上述实施例提供的移位寄存器单元，所述显示基板包括显示区域和位于所述显示区域周边的周边区域，所述移位寄存器单元位于所述显示区域和/或所述周边区域。
示例性的，所述周边区域包围所述显示区域，但不仅限于此。
示例性的，所述周边区域包括左边框区域和右边框区域，所述显示区域位于所述左边框区域和所述右边框区域之间。所述移位寄存器单元可以设置于所述左边框区域和/或所述右边框区域。所述移位寄存器单元也可以设置于所述显示区域。
上述实施例提供的移位寄存器单元中，通过所述第一栅极和所述第二栅极能够控制所述第一输出晶体管Ts1的导通或截止，保证移位寄存器单元的正常工作。通过调整所述第二栅极的电压，能够调节所述第一输出晶体管Ts1的特性曲线，从而有效改善第一输出晶体管Ts1的负偏，改善输出的栅极驱动信号的波动。上述实施例提供的移位寄存器单元中，通过设置所述第一输出晶体管Ts1包括双栅结构，通过调试所述第一输出晶体管Ts1的第二栅极Ts1-g2的电压，实现了对第一输出晶体管Ts1的特性曲线进行调控，使得第一输出晶体管Ts1即使出现负偏也能够通过底栅BG的控制调整回来。上述实施例提供的移位寄存器单元中，实现了对第一输出晶体管Ts1的工艺Margin改善，使得所述第一输出晶体管Ts1具有能够兼容更大范围负偏的能力，保证了输出的栅极驱动信号的稳定性。
本公开实施例提供的显示基板在包括上述实施例提供的移位寄存器单元时，同样具有上述有益效果，所述显示基板在稳定的栅极驱动信号的驱动下，能够实现较高的显示质量。
如图18至图27所示，在一些实施例中，所述移位寄存器单元包括控制信号调试单元，所述控制信号调试单元包括第一调试子单元11和第二调试子单元12，所述第一调试子单元11包括第一调试晶体管T01和第二调试晶体管T02；所述第二调试子单元12包括第三调试晶体管T03；所述移位寄存器单元还包括第一输出晶体管Ts1和第二输出晶体管Ts2；
所述第一输出晶体管Ts1和所述第二输出晶体管Ts2沿第一方向排列； 所述第三调试晶体管T03的至少部分，所述第一调试晶体管T01和所述第二调试晶体管T02沿所述第一方向排列；所述第一输出晶体管Ts1位于所述显示区域和所述第一调试晶体管T01之间。
示例性的，所述第三调试晶体管T03与所述第一输出晶体管Ts1沿第二方向排列，所述第一调试晶体管T01与所述第一输出晶体管Ts1沿第二方向排列，所述第二调试晶体管T02与所述第一输出晶体管Ts1沿第二方向排列。
示例性的，所述第一方向与所述第二方向相交。例如：所述第一方向包括纵向，所述第二方向包括横向。
上述设置所述第一输出晶体管Ts1和所述第二输出晶体管Ts2沿第一方向排列，以及所述第三调试晶体管T03的至少部分，所述第一调试晶体管T01和所述第二调试晶体管T02沿所述第一方向排列；缩小了所述第一输出晶体管Ts1，所述第二输出晶体管Ts2，所述第一调试晶体管T01，所述第二调试晶体管T02和所述第三调试晶体管T03占用的布局空间在第二方向上的宽度，从而有效缩小显示基板的边框宽度。
上述设置所述第一输出晶体管Ts1位于所述显示区域和所述第一调试晶体管T01之间，更好的规划了有限的布局空间，降低了移位寄存器单元在有限布局空间内的布局难度。
如图20和图24所示，在一些实施例中，所述第二调试晶体管T02和所述第二输出晶体管Ts2均包括双栅结构，所述第二调试晶体管T02的第一栅极T02-g1与所述第二输出晶体管Ts2的第一栅极Ts2-g1形成为一体结构，所述第二调试晶体管T02的第二栅极T02-g2与所述第二输出晶体管Ts2的第二栅极形成为一体结构。
上述设置所述第二调试晶体管T02和所述第二输出晶体管Ts2均包括双栅结构，更好的提升了所述第二调试晶体管T02和所述第二输出晶体管Ts2性能。同时按照一体结构的方式形成上述结构，不仅保证了结构之间的耦接性能，还有利于简化制作工艺流程，降低制作成本。
如图24所示，在一些实施例中，所述第三调试晶体管T03的栅极T03-g与所述第一输出晶体管Ts1的第一栅极Ts1-g1形成为一体结构。
按照一体结构的方式形成上述结构，不仅保证了结构之间的耦接性能， 还有利于简化制作工艺流程，降低制作成本。
如图22和图27所示，在一些实施例中，所述显示基板还包括第二电平信号线VGL2’，所述第二电平信号线VGL2’作为第二电平信号输入端VGL2与所述第二调试晶体管T02耦接；
所述第一调试晶体管T01包括第一调试有源层501，所述第二调试晶体管T02包括第二调试有源层502，所述第三调试晶体管T03包括第三调试有源层503；
所述第二电平信号线VGL2’在所述显示基板的衬底基板上的正投影，与所述第一调试有源层501在所述显示基板的衬底基板上的正投影至少部分交叠；和/或，所述第二电平信号线VGL2’在所述显示基板的衬底基板上的正投影，与所述第二调试有源层502在所述显示基板的衬底基板上的正投影至少部分交叠；和/或，所述第二电平信号线VGL2’在所述显示基板的衬底基板上的正投影，与所述第三调试有源层503在所述显示基板的衬底基板上的正投影至少部分交叠。
示例性的，所述第一调试有源层501，所述第二调试有源层502和所述第三调试有源层503均包括氧化物有源层，例如：IGZO有源层，但不仅限于此。
示例性的，所述第二电平信号线VGL2’包括沿所述第一方向延伸的至少部分。所述第一调试有源层501和所述第二调试有源层502均沿所述第一方向延伸，所述第三调试有源层503包括沿所述第一方向延伸的部分和沿第二方向延伸的部分。
示例性的，所述第一调试有源层501在所述衬底基板上的正投影，位于所述第二电平信号线VGL2’在所述衬底基板上的正投影的内部。所述第二调试有源层502在所述衬底基板上的正投影，位于所述第二电平信号线VGL2’在所述衬底基板上的正投影的内部。所述第三调试有源层503在所述显示基板的衬底基板上的正投影与所述第二电平信号线VGL2’在所述显示基板的衬底基板上的正投影部分交叠。
示例性的，所述第二调试有源层502与所述第一调试有源层501形成为一体结构。
上述设置方式有利于减小所述第二电平信号线VGL2’独立占用的布局空间，有利于显示基板的窄边框化。
如图18至图27所示，在一些实施例中，所述显示基板还包括第一电平信号线VGL’和第三电平信号线VGH’；所述第一电平信号线VGL’作为第一电平信号输入端VGL与第二输出晶体管Ts2耦接；所述第三电平信号线VGH’作为第三电平信号输入端VGH与所述第三调试晶体管T03耦接；
沿靠近所述显示区域的方向，所述第三电平信号线VGH’在所述衬底基板上的正投影，所述第一电平信号线VGL’在所述衬底基板上的正投影，以及所述第二电平信号线VGL2’在所述衬底基板上的正投影依次排列。
示例性的，所述第一电平信号线VGL’包括沿所述第一方向延伸的至少部分。所述第三电平信号线VGH’包括沿所述第一方向延伸的至少部分。
如图18至图27所示，在一些实施例中，所述显示基板还包括第一时钟信号线GCB’，第二时钟信号线GCK’和起始信号线STV’，所述第一时钟信号线GCB’作为第一时钟信号输入端GCB与所述第一调试晶体管T01耦接；所述移位寄存器单元还包括第五晶体管T5，第六晶体管T6，第七晶体管T7和第八晶体管T8；
所述第五晶体管T5的栅极与所述第二时钟信号线GCK’耦接，所述第五晶体管T5的第一极与所述第三电平信号线VGH’耦接，所述第五晶体管T5的第二极与所述第二输出晶体管Ts2的栅极耦接；
所述第六晶体管T6的栅极与所述第一时钟信号线GCB’耦接，所述第六晶体管T6的第一极与所述第一电平信号线VGL’耦接，所述第六晶体管T6的第二极与所述第二输出晶体管Ts2的栅极耦接；
所述第七晶体管T7的栅极与所述第二时钟信号线GCK’耦接，所述第七晶体管T7的第一极与起始信号线STV’耦接，所述第七晶体管T7的第二极与第八晶体管T8的第一极耦接，所述第八晶体管T8的第二极与所述第一输出晶体管Ts1的栅极耦接，所述第八晶体管T8的栅极与所述第三电平信号线VGH’耦接；需要说明的是，在所述显示基板包括级联的多个移位寄存器单元的情况下，首级移位寄存器单元中的第七晶体管T7的第一极直接与起始信号线STV’耦接，其余各级移位寄存器单元中的第七晶体管T7的第一极均与其 相邻上一级移位寄存器单元的栅极驱动信号输出端OUT耦接。
所述第七晶体管T7，所述第八晶体管T8，所述第六晶体管T6和所述第五晶体管T5沿所述第一方向依次排列；所述第七晶体管T7在所述衬底基板上的正投影，所述第八晶体管T8在所述衬底基板上的正投影，所述第六晶体管T6在所述衬底基板上的正投影，以及所述第五晶体管T5在所述衬底基板上的正投影，均位于所述第三电平信号线VGH’在所述衬底基板上的正投影和所述第一电平信号线VGL’在所述衬底基板上的正投影之间。
示例性的，沿靠近所述显示区域的方向，所述起始信号线STV’，所述第二时钟信号线GCK’，所述第一时钟信号线GCB’和所述第三电平信号线VGH’依次排列。
上述设置所述第七晶体管T7，所述第八晶体管T8，所述第六晶体管T6和所述第五晶体管T5沿所述第一方向依次排列，缩小了所述第七晶体管T7，所述第八晶体管T8，所述第六晶体管T6和所述第五晶体管T5占用的布局空间在第二方向上的宽度，从而有效缩小显示基板的边框宽度。
而且，设置所述第八晶体管T8在所述衬底基板上的正投影，所述第六晶体管T6在所述衬底基板上的正投影，以及所述第五晶体管T5在所述衬底基板上的正投影，均位于所述第三电平信号线VGH’在所述衬底基板上的正投影和所述第一电平信号线VGL’在所述衬底基板上的正投影之间，更好的规划了有限的布局空间，简化了布局复杂度，在保证晶体管与信号线之间的耦接性能的同时，降低了移位寄存器单元在有限布局空间内的布局难度。
此外，上述实施例提供的显示基板中，优化了移位寄存器单元中各晶体管的叠层设计，实现了移位寄存器单元的高效驱动。
更详细地说，如图18所示，示意了第四电容C4的第二极板C42和第五电容C5的第二极板C52。如图19所示，示意了第四电容C4和第五电容C5。如图20所示，示意了第四电容C4的第一极板C41和第五电容C5的第一极板C51。
如图21和图22所示，示意了第一输出晶体管Ts1包括的第一输出有源层5s1，第二输出晶体管Ts2包括的第二输出有源层5s2，第一调试晶体管T01包括的第一调试有源层501，第二调试晶体管T02包括的第二调试有源层 502，第三调试晶体管T03包括的第三调试有源层503，第五晶体管T5包括的第五有源层55，第六晶体管T6包括的第六有源层56，第七晶体管T7包括的第七有源层57，第八晶体管T8包括的第八有源层58。
如图24所示，示意了第一调试晶体管T01的栅极T01-g，第五晶体管T5的栅极T5-g，第六晶体管T6的栅极T6-g，第七晶体管T7的栅极T7-g，第八晶体管T8的栅极T8-g。
需要说明的是，图25中的黑色圆点代表第一源漏金属层与其下方的膜层之间的连接孔。图27中的黑色方形孔用于连接第二电平信号线VGL2'和第七导电连接部67。
如图18至图27所示，第一导电连接部61与第七晶体管T7的第一极耦接。第二导电连接部62分别与第三调试晶体管T03的一极和第八晶体管T8的栅极耦接，第八晶体管T8的栅极与第三电平信号线VGH'耦接。
第三导电连接部63分别与第三调试晶体管T03的另一极，第一输出晶体管Ts1的第二栅极Ts1-g2，以及第一调试晶体管T01的一极耦接。
第四导电连接部64分别与第八晶体管T8的一极和第一输出晶体管Ts1的第一栅极Ts1-g1耦接。
第五导电连接部65分别与第六晶体管T6的一极，第五电容C5的第一极板C51，以及第五晶体管T5的一极耦接。
第六导电连接部66分别第五电容C5的第一极板C51和第二输出晶体管Ts2的第一栅极Ts2-g1耦接。
第七导电连接部67分别与第二调试晶体管T02的一极和第二电平信号线VGL2'耦接。
第八导电连接部68和第九导电连接部69的一部分可以作为第一输出晶体管Ts1的电极。第九导电连接部69的另一部分可以作为第二输出晶体管Ts2的电极。
需要说明的，上述实施例提供的显示基板包括如图9所示的移位寄存器单元结构，但不仅限于此。
本公开实施例还提供了一种显示装置，包括上述实施例提供的显示基板。
需要说明的是，所述显示装置可以为：电视、显示器、数码相框、手机、 平板电脑等任何具有显示功能的产品或部件，其中，所述显示装置还包括柔性单元板、印刷单元板和背板等。
上述实施例提供的显示基板在包括上述移位寄存器单元时，能够实现良好的显示效果，本公开实施例提供的显示装置在包括上述显示基板时，同样具有上述有益效果，此处不再赘述。
需要说明，信号线沿X方向延伸是指：信号线包括主要部分和与所述主要部分连接的次要部分，所述主要部分是线、线段或条形状体，所述主要部分沿X方向延展，且所述主要部分沿X方向延展的长度大于次要部分沿其它方向伸展的长度。
需要说明的是，本公开实施例的“同层”可以指的是处于相同结构层上的膜层。或者例如，处于同层的膜层可以是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。这些特定图形还可能处于不同的高度或者具有不同的厚度。
在本公开各方法实施例中，所述各步骤的序号并不能用于限定各步骤的先后顺序，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，对各步骤的先后变化也在本公开的保护范围之内。
需要说明，本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分互相参见即可，每个实施例重点说明的都是与其他实施例的不同之处。尤其，对于方法实施例而言，由于其基本相似于产品实施例，所以描述得比较简单，相关之处参见产品实施例的部分说明即可。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”、“耦接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。 “上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
在上述实施方式的描述中，具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (20)

  1. 一种移位寄存器单元，包括第一输出晶体管，栅极驱动信号输出端，第一输出控制节点，控制信号输入端和第一信号输入端；
    所述第一输出晶体管包括双栅结构，所述第一输出晶体管的第一栅极与所述第一输出控制节点耦接，所述第一输出晶体管的第二栅极与所述控制信号输入端耦接，所述第一输出晶体管的第一极与所述第一信号输入端耦接，所述第一输出晶体管的第二极与所述栅极驱动信号输出端耦接。
  2. 根据权利要求1所述的移位寄存器单元，其中，所述移位寄存器单元还包括第二输出晶体管，第二输出控制节点和第一电平信号输入端，所述第二输出晶体管的栅极与所述第二输出控制节点耦接，所述第二输出晶体管的第一极与所述第一电平信号输入端耦接，所述第二输出晶体管的第二极与所述栅极驱动信号输出端耦接；
    所述第一信号输入端包括第一时钟信号输入端；所述移位寄存器单元还包括第二电平信号输入端，第三电平信号输入端和控制信号调试单元，所述控制信号调试单元包括第一调试子单元和第二调试子单元；
    所述第一调试子单元分别与所述第一时钟信号输入端，所述第二输出控制节点，所述第二电平信号输入端和所述控制信号输入端耦接，用于在所述第一时钟信号输入端和所述第二输出控制节点的控制下，控制导通或断开所述第二电平信号输入端和所述控制信号输入端之间的电连接；
    所述第二调试子单元分别与所述第一输出控制节点，第三电平信号输入端和所述控制信号输入端耦接，用于在所述第一输出控制节点的控制下，控制导通或断开所述第三电平信号输入端与所述控制信号输入端之间的电连接。
  3. 根据权利要求2所述的移位寄存器单元，其中，所述第一调试子单元包括第一调试晶体管和第二调试晶体管；所述第二调试子单元包括第三调试晶体管；
    所述第一调试晶体管的栅极与所述第一时钟信号输入端耦接，所述第一调试晶体管的第一极与所述第二调试晶体管的第二极耦接，所述第一调试晶 体管的第二极与所述控制信号输入端耦接；
    所述第二调试晶体管的栅极与所述第二输出控制节点耦接，所述第二调试晶体管的第一极与所述第二电平信号输入端耦接；
    所述第三调试晶体管的栅极与所述第一输出控制节点耦接，所述第三调试晶体管的第一极与所述第三电平信号输入端耦接，所述第三调试晶体管的第二极与所述控制信号输入端耦接。
  4. 根据权利要求2或3所述的移位寄存器单元，其中，所述移位寄存器单元还包括：第一节点控制单元，第二节点控制单元，第二时钟信号输入端和起始信号输入端；
    所述第一节点控制单元分别与所述第二时钟信号输入端，所述第一输出控制节点和所述起始信号输入端耦接；用于在所述第二时钟信号输入端的控制下，控制导通或断开所述初始信号输入端与所述第一输出控制节点之间的电连接；
    所述第二节点控制单元分别与所述第一时钟信号输入端，所述第二时钟信号输入端，第一电平信号输入端，第三电平信号输入端和第二输出控制节点耦接，用于在所述第一时钟信号输入端的控制下，控制导通或断开所述第一电平信号输入端和所述第二输出控制节点之间的电连接，以及用于在所述第二时钟信号输入端的控制下，控制导通或断开所述第三电平信号输入端和所述第二输出控制节点之间的电连接；或者，所述第二节点控制单元分别与所述第二时钟信号输入端，所述第一输出控制节点，所述第二输出控制节点和所述第三电平信号输入端耦接，用于在所述第二时钟信号输入端的控制下，控制导通或断开所述第三电平信号输入端与所述第二输出控制节点之间的电连接；以及用于在所述第一输出控制节点的控制下，控制导通或断开所述第二时钟信号输入端与所述第二输出控制节点之间的电连接。
  5. 根据权利要求4所述的移位寄存器单元，其中，所述第一节点控制单元还分别与所述第一时钟信号输入端，所述第二输出控制节点，所述第一电平信号输入端耦接；用于在所述第一时钟信号输入端和所述第二输出控制节点的控制下，控制导通或断开所述第一电平信号输入端与所述第一输出控制节点之间的电连接。
  6. 根据权利要求1所述的移位寄存器单元，其中，所述第一信号输入端包括第一电平信号输入端，所述控制信号输入端包括第二电平信号输入端，所述第二电平信号输入端用于输入直流的第二电平信号；
    所述移位寄存器单元还包括：第二输出晶体管，第二输出控制节点和第三电平信号输入端，所述第二输出晶体管的栅极与所述第二输出控制节点耦接，所述第二输出晶体管的第一极与所述第三电平信号输入端耦接，所述第二输出晶体管的第二极与所述栅极驱动信号输出端耦接。
  7. 根据权利要求6所述的移位寄存器单元，其中，所述移位寄存器单元还包括第一节点控制单元，所述第一节点控制单元分别与所述第二输出控制节点，所述第一电平信号输入端和所述第一输出控制节点耦接，用于在所述第二输出控制节点的控制下控制导通或断开所述第一电平信号输入端和所述第一输出控制节点之间的电连接。
  8. 根据权利要求7所述的移位寄存器单元，其中，所述第一节点控制单元还与所述第二电平信号输入端耦接；所述第一节点控制单元包括：第一控制晶体管，所述第一控制晶体管包括双栅结构，所述第一控制晶体管的第一栅极与所述第二输出控制节点耦接，所述第一控制晶体管的第二栅极与所述第二电平信号输入端耦接，所述第一控制晶体管的第一极与所述第一电平信号输入端耦接，所述第一控制晶体管的第二极与所述第一输出控制节点耦接。
  9. 根据权利要求6所述的移位寄存器单元，其中，所述移位寄存器单元还包括第二节点控制单元，第三时钟信号输入端和起始信号输入端；所述第二节点控制单元分别与所述第三时钟信号输入端，所述起始信号输入端和所述第二输出控制节点耦接，用于在所述第三时钟信号输入端的控制下，控制导通或断开所述起始信号输入端和所述第二输出控制节点之间的电连接。
  10. 根据权利要求9所述的移位寄存器单元，其中，所述第二节点控制单元还与所述第三电平信号输入端耦接；所述第二节点控制单元包括：第二控制晶体管，第三控制晶体管和第四控制晶体管；
    所述第二控制晶体管的栅极与所述第三时钟信号输入端耦接，所述第二控制晶体管的第一极与所述起始信号输入端耦接，所述第二控制晶体管的第二极与所述第三控制晶体管的第一极耦接；
    所述第三控制晶体管的栅极与所述第三时钟信号输入端耦接，所述第三控制晶体管的第二极与所述第二输出控制节点耦接。
    所述第四控制晶体管的栅极与所述第二输出控制节点耦接，所述第四控制晶体管的第一极与所述第三电平信号输入端耦接，所述第四控制晶体管的第二极与所述第三控制晶体管的第一极耦接。
  11. 根据权利要求7～10中任一项所述的移位寄存器单元，其中，所述第一节点控制单元还分别与第一电平信号输入端，第三电平信号输入端和起始信号输入端耦接；用于在所述第一电平信号输入端和所述起始信号输入端的控制下，控制导通或断开所述第三电平信号输入端与所述第一输出控制节点之间的电连接。
  12. 一种显示基板，包括如权利要求1～11中任一项所述的移位寄存器单元，所述显示基板包括显示区域和位于所述显示区域周边的周边区域，所述移位寄存器单元位于所述显示区域和/或所述周边区域。
  13. 根据权利要求12所述的显示基板，其中，所述移位寄存器单元包括控制信号调试单元，所述控制信号调试单元包括第一调试子单元和第二调试子单元，所述第一调试子单元包括第一调试晶体管和第二调试晶体管；所述第二调试子单元包括第三调试晶体管；所述移位寄存器单元还包括第一输出晶体管和第二输出晶体管；
    所述第一输出晶体管和所述第二输出晶体管沿第一方向排列；所述第三调试晶体管的至少部分，所述第一调试晶体管和所述第二调试晶体管沿所述第一方向排列；所述第一输出晶体管位于所述显示区域和所述第一调试晶体管之间。
  14. 根据权利要求13所述的显示基板，其中，所述第二调试晶体管和所述第二输出晶体管均包括双栅结构，所述第二调试晶体管的第一栅极与所述第二输出晶体管的第一栅极形成为一体结构，所述第二调试晶体管的第二栅极与所述第二输出晶体管的第二栅极形成为一体结构。
  15. 根据权利要求13所述的显示基板，其中，所述第三调试晶体管的栅极与所述第一输出晶体管的第一栅极形成为一体结构。
  16. 根据权利要求12～15中任一项所述的显示基板，其中，所述显示基 板还包括第二电平信号线，所述第二电平信号线作为第二电平信号输入端与所述第二调试晶体管耦接；
    所述第一调试晶体管包括第一调试有源层，所述第二调试晶体管包括第二调试有源层，所述第三调试晶体管包括第三调试有源层；
    所述第二电平信号线在所述显示基板的衬底基板上的正投影，与所述第一调试有源层在所述显示基板的衬底基板上的正投影至少部分交叠；和/或，所述第二电平信号线在所述显示基板的衬底基板上的正投影，与所述第二调试有源层在所述显示基板的衬底基板上的正投影至少部分交叠；和/或，所述第二电平信号线在所述显示基板的衬底基板上的正投影，与所述第三调试有源层在所述显示基板的衬底基板上的正投影至少部分交叠。
  17. 根据权利要求16所述的显示基板，其中，所述显示基板还包括第一电平信号线和第三电平信号线；所述第一电平信号线作为第一电平信号输入端与第二输出晶体管耦接；所述第三电平信号线作为第三电平信号输入端与所述第三调试晶体管耦接；
    沿靠近所述显示区域的方向，所述第三电平信号线在所述衬底基板上的正投影，所述第一电平信号线在所述衬底基板上的正投影，以及所述第二电平信号线在所述衬底基板上的正投影依次排列。
  18. 根据权利要求17所述的显示基板，其中，所述显示基板还包括第一时钟信号线，第二时钟信号线和起始信号线，所述第一时钟信号线作为第一时钟信号输入端与所述第一调试晶体管耦接；所述移位寄存器单元还包括第五晶体管，第六晶体管，第七晶体管和第八晶体管；
    所述第五晶体管的栅极与所述第二时钟信号线耦接，所述第五晶体管的第一极与所述第三电平信号线耦接，所述第五晶体管的第二极与所述第二输出晶体管的栅极耦接；
    所述第六晶体管的栅极与所述第一时钟信号线耦接，所述第六晶体管的第一极与所述第一电平信号线耦接，所述第六晶体管的第二极与所述第二输出晶体管的栅极耦接；
    所述第七晶体管的栅极与所述第二时钟信号线耦接，所述第七晶体管的第一极与起始信号线耦接，所述第七晶体管的第二极与第八晶体管的第一极 耦接，所述第八晶体管的第二极与所述第一输出晶体管的栅极耦接，所述第八晶体管的栅极与所述第三电平信号线耦接；
    所述第七晶体管，所述第八晶体管，所述第六晶体管和所述第五晶体管沿所述第一方向依次排列；所述第七晶体管在所述衬底基板上的正投影，所述第八晶体管在所述衬底基板上的正投影，所述第六晶体管在所述衬底基板上的正投影，以及所述第五晶体管在所述衬底基板上的正投影，均位于所述第三电平信号线在所述衬底基板上的正投影和所述第一电平信号线在所述衬底基板上的正投影之间。
  19. 根据权利要求18所述的显示基板，其中，沿靠近所述显示区域的方向，所述起始信号线，所述第二时钟信号线，所述第一时钟信号线和所述第三电平信号线依次排列。
  20. 一种显示装置，包括如权利要求13～19中任一项所述的显示基板。
PCT/CN2024/112607 2023-11-30 2024-08-16 移位寄存器单元、显示基板和显示装置 Pending WO2025112668A1 (zh)

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