WO2025112112A1 - 一种显示面板 - Google Patents

一种显示面板 Download PDF

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Publication number
WO2025112112A1
WO2025112112A1 PCT/CN2023/138412 CN2023138412W WO2025112112A1 WO 2025112112 A1 WO2025112112 A1 WO 2025112112A1 CN 2023138412 W CN2023138412 W CN 2023138412W WO 2025112112 A1 WO2025112112 A1 WO 2025112112A1
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WIPO (PCT)
Prior art keywords
display panel
insulating layer
gate
thin film
film transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
PCT/CN2023/138412
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English (en)
French (fr)
Inventor
李治福
袁剑峰
艾飞
宋德伟
罗成志
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Wuhan China Star Optoelectronics Technology Co Ltd
Original Assignee
Wuhan China Star Optoelectronics Technology Co Ltd
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Publication of WO2025112112A1 publication Critical patent/WO2025112112A1/zh
Anticipated expiration legal-status Critical
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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel.
  • VR/AR display devices are near-eye display devices, which have high requirements for the aperture ratio and display quality of the display panel, and need to reduce the production cost as much as possible.
  • the display panel includes a pixel electrode and a thin film transistor (full name in English: Thin Film Transistor, abbreviated as: TFT) electrically connected to the pixel electrode.
  • the thin film transistor is a switching element that controls the pixel electrode to obtain the pixel voltage.
  • the connection method between the thin film transistor and the pixel electrode and the structure of the thin film transistor directly affect the aperture ratio, display quality and production cost of the display panel.
  • the present application provides a display panel that can effectively solve the problem that the display panel cannot take into account both display quality and production cost while achieving a high aperture ratio.
  • the present application provides a display panel, which has a display area, and the display panel includes: a substrate; a first thin film transistor, which is arranged on one side of the substrate and located in the display area; a pixel electrode, which is arranged on a side of the first thin film transistor away from the substrate and located in the display area; wherein the first thin film transistor includes: a first active layer, including a first channel and a first drain ohmic contact portion arranged on one side of the first channel; an isolation portion, which is arranged on a surface of the first channel away from the substrate and covers the first channel; a first drain, including a transparent first part and a transparent second part, wherein the first part is arranged on a surface of the isolation portion away from the first active layer, and the second part is arranged on a surface of the first drain ohmic contact portion away from the substrate; wherein the pixel electrode is electrically connected to the first part through a first via hole arranged on a side of the first part away from the isolation portion.
  • FIG. 1 is a schematic plan view of a display panel in the related art.
  • FIG. 2 is a cross-sectional schematic diagram of a display panel in the related art.
  • FIG. 3 is a plan view of a display panel provided in some embodiments of the present application.
  • FIG. 4 is a cross-sectional schematic diagram of a display panel provided in some embodiments of the present application.
  • FIG5 a is a schematic cross-sectional view of an isolation portion when the angle between the side wall of the isolation portion and the bottom surface of the isolation portion is 90° according to some embodiments of the present application.
  • FIG5 b is a schematic cross-sectional view of the isolation portion when the angle between the side wall of the isolation portion and the bottom surface of the isolation portion is 30° according to some embodiments of the present application.
  • FIG. 6 a is a schematic structural diagram of a display panel corresponding to step S01 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6 b is a schematic structural diagram of a display panel corresponding to step S02 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6 c is a schematic structural diagram of a display panel corresponding to step S03 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6 d is a schematic structural diagram of a display panel corresponding to step S04 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6 e is a schematic structural diagram of a display panel corresponding to step S05 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6f is a schematic structural diagram of a display panel corresponding to step S06 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6g is a schematic structural diagram of a display panel corresponding to step S07 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6h is a schematic structural diagram of a display panel corresponding to step S08 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6i is a schematic structural diagram of a display panel corresponding to step S09 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6 j is a schematic structural diagram of a display panel corresponding to step S10 in the method for preparing a display panel provided in an embodiment of the present application.
  • FIG. 6k is a schematic structural diagram of a display panel corresponding to step S11 in the method for preparing a display panel provided in an embodiment of the present application.
  • the present application provides a display panel, which has a display area, and the display panel includes: a substrate; a first thin film transistor, which is arranged on one side of the substrate and located in the display area; a pixel electrode, which is arranged on a side of the first thin film transistor away from the substrate and located in the display area; wherein the first thin film transistor includes: a first active layer, including a first channel and a first drain ohmic contact portion arranged on one side of the first channel; an isolation portion, which is arranged on a surface of the first channel away from the substrate and covers the first channel; a first drain, including a transparent first part and a transparent second part, wherein the first part is arranged on a surface of the isolation portion away from the first active layer, and the second part is arranged on a surface of the first drain ohmic contact portion away from the substrate; wherein the pixel electrode is electrically connected to the first part through a first via hole arranged on a side of the first part away from the isolation portion.
  • the second portion covers the first drain ohmic contact.
  • the second portion covers the side wall of the isolation portion, and an angle between the side wall of the isolation portion and the bottom surface of the isolation portion is a, and 30° ⁇ a ⁇ 90°.
  • an edge of the isolation portion protrudes beyond an edge of the first portion.
  • the first active layer also includes a first source ohmic contact portion arranged on the other side of the first channel, wherein the first thin film transistor also includes a first source electrode formed integrally with the first drain electrode, and the first source electrode is arranged on a surface of the first source ohmic contact portion on a side away from the substrate and covers the first source ohmic contact portion.
  • the display panel also includes a first gate insulating layer, which is arranged on a side of the first active layer away from the isolation portion, wherein the first gate insulating layer includes a first sub-insulating layer, the first sub-insulating layer is in contact with the first active layer, and the first sub-insulating layer is made of the same material as the isolation portion.
  • the display panel also includes a second thin film transistor, which is arranged on the side of the substrate facing the first thin film transistor, wherein the second thin film transistor includes a second active layer, which is arranged on the side of the first active layer away from the isolation portion, and the second active layer includes a second channel, and the material of the second channel is different from the material of the first channel.
  • the second thin film transistor includes a second active layer, which is arranged on the side of the first active layer away from the isolation portion, and the second active layer includes a second channel, and the material of the second channel is different from the material of the first channel.
  • the first gate insulating layer also includes a second sub-insulating layer, which is arranged on a side of the first sub-insulating layer away from the first active layer, and the second sub-insulating layer and the first sub-insulating layer are made of different materials;
  • the first thin film transistor includes a first gate, which is arranged on a side of the second sub-insulating layer away from the first sub-insulating layer;
  • the second thin film transistor also includes a second gate, which is arranged on a side of the second active layer away from the substrate; wherein the first gate and the second gate are arranged on the same layer, and the first gate and the second gate are respectively in contact with the second sub-insulating layer.
  • the display panel also includes a second gate insulating layer, which is arranged on a side of the second active layer facing the second gate, wherein the first gate insulating layer arranged between the first active layer and the first gate has a first thickness, the second gate insulating layer arranged between the second active layer and the second gate has a second thickness, and a ratio of the first thickness to the second thickness is less than or equal to 3.
  • the second thin film transistor further includes a second source and a second drain
  • the first thin film transistor further includes a first source conductive connection portion, the first source conductive connection portion is arranged in the same layer as the second source and the second drain, and the first source conductive connection portion is electrically connected to the first source through a second via.
  • the present application provides a display panel, the display panel having a display area, the display panel comprising: a substrate; a first thin film transistor, arranged on one side of the substrate and located in the display area; a pixel electrode, arranged on the side of the first thin film transistor away from the substrate and located in the display area; the first thin film transistor comprises a first active layer, an isolation portion and a first drain electrode, wherein the first active layer comprises a first channel and a first drain electrode ohmic contact portion arranged on one side of the first channel; the isolation portion is arranged on the surface of the first channel away from the substrate and covers the first channel; the first drain electrode comprises a transparent first part and a transparent second part, the first part is arranged on the surface of the isolation portion away from the first active layer, and the second part is arranged on the surface of the first drain electrode ohmic contact portion away from the substrate; wherein the pixel electrode is electrically connected to the first part through a first via hole arranged on the side of the first part away from the isolation portion.
  • FIG. 1 is a schematic plan view of a display panel in the related art
  • FIG. 2 is a schematic cross-sectional view of a display panel in the related art.
  • a display panel 100 ⁇ in the related art has a display area AA ⁇ and a non-display area NAA ⁇
  • the display panel 100 ⁇ includes a substrate 10 ⁇ , a thin film transistor 20 ⁇ arranged on one side of the substrate 10 ⁇ , and a pixel electrode 30 ⁇ arranged on a side of the thin film transistor 20 ⁇ away from the substrate 10 ⁇
  • the thin film transistor 20 ⁇ and the pixel electrode 30 ⁇ are both located in the display area AA ⁇ of the display panel 100 ⁇
  • the thin film transistor 20 ⁇ includes an active layer 21 ⁇ , a first gate 22 ⁇ , a second gate 23 ⁇ , a source 24 ⁇ and a drain 25 ⁇
  • the active layer 21 ⁇ includes a channel 211 ⁇ and a drain ohmic contact portion 212 ⁇ located on one side of the channel 211 ⁇
  • the drain 25 ⁇ is overlapped with the drain o
  • the drain electrode 25' is made of a transparent conductive material, so that the area where the drain electrode 25' overlaps with the drain ohmic contact portion 212' can have high light transmittance, so as to be used for performing the display function, thereby improving the aperture ratio of the display panel 100'.
  • the via structure of the first via hole 40' is prone to uneven display in the area where the first via hole 40' is located when performing the display function, which reduces the display quality of the display panel 100', and the first via hole 40' and the second via hole 50' increase the process steps of the display panel 100', thereby increasing the production cost of the display panel 100'.
  • the present application provides a display panel and a method for preparing the same.
  • FIG3 is a schematic plan view of a display panel provided by some embodiments of the present application
  • FIG4 is a schematic cross-sectional view of a display panel provided by some embodiments of the present application.
  • an embodiment of the present application provides a display panel, wherein the display panel has a display area AA and a non-display area NAA, wherein the non-display area NAA surrounds the display area AA, and the display area AA array is provided with a plurality of display pixels.
  • the display panel includes a substrate 10, a first thin film transistor 20, and a pixel electrode 30, wherein the first thin film transistor 20 is disposed on one side of the substrate 10 and is located in the display area AA; the pixel electrode 30 is disposed on a side of the first thin film transistor 20 away from the substrate 10 and is located in the display area AA.
  • the first thin film transistor 20 includes a first active layer 21, an isolation portion 22 and a first drain 23, wherein the first active layer 21 includes a first channel 211 and a first drain ohmic contact portion 212 arranged on one side of the first channel 211; the isolation portion 22 is arranged on a surface of the first channel 211 on a side away from the substrate 10 and covers the first channel 211; the first drain 23 includes a transparent first portion 231 and a transparent second portion 232, the first portion 231 is arranged on a surface of the isolation portion 22 on a side away from the first active layer 21, and the second portion 232 is arranged on a surface of the first drain ohmic contact portion 212 on a side away from the substrate 10; wherein the pixel electrode 30 is electrically connected to the first portion 231 through a first via 40 arranged on a side of the first portion 231 away from the isolation portion 22.
  • the area where the first drain ohmic contact portion 212 is located can have high light transmittance for performing the display function, thereby improving the aperture ratio of the display panel.
  • the pixel electrode 30 is electrically connected to the first part 231 through the first via hole 40 arranged on the side of the first part 231 away from the isolation part 22, and the first part 231 is arranged on the isolation part 22 corresponding to the first channel 211, that is, in the direction perpendicular to the substrate 10, the first via hole 40 and the first drain ohmic contact part 212 are staggered, the first via hole 40 will not affect the display function of the area where the first drain ohmic contact part 212 is located.
  • first part 231 is arranged on the surface of the isolation part 22 on the side away from the first active layer 21, and the second part 232 is arranged on the surface of the first drain ohmic contact part 212 on the side away from the substrate 10, that is, in the direction perpendicular to the substrate 10, the first part 231 and the second part 232 are separated by only one isolation part 22.
  • the first part 231 and the second part 232 do not need to be connected by a via structure when they are formed as one piece, so that there is no need to set a via structure above the second part 232, so that the area where the first drain ohmic contact part 212 is located has a consistent display effect with other display areas AA, thereby improving the display uniformity of the display panel and the display quality of the display panel.
  • a vertical projection of the first via hole 40 on the first active layer 21 overlaps with the first channel 211 .
  • a channel region of the thin film transistor is often provided with an opaque gate, that is, the display panel does not have a display function in the channel region of the thin film transistor.
  • the present application overlaps the vertical projection of the first via hole 40 on the first active layer 21 with the first channel 211, so that the first via hole 40 does not occupy the area with display function in the display area AA, thereby further improving the aperture ratio of the display panel.
  • the first thin film transistor 20 is a metal oxide thin film transistor
  • the material of the first channel 211 is a metal oxide semiconductor
  • the first drain ohmic contact portion 212 is a transparent conductive structure formed by the metal oxide semiconductor material after being subjected to a conductor treatment.
  • the display panel can have the advantages of low leakage current, low refresh rate, and high light transmittance.
  • the second portion 232 covers the drain ohmic contact portion.
  • the edge of the second portion 232 protrudes from the edge of the drain ohmic contact portion by 0.5-1 micrometer.
  • the second part 232 since the second part 232 covers the first drain ohmic contact portion 212, the second part 232 can protect the first drain ohmic contact portion 212 to avoid damage to the first drain ohmic contact portion 212 during the patterning process of the film layer where the first drain 23 is located.
  • the second portion 232 covers the side wall 221 of the isolation portion 22 , and an angle between the side wall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 is a, and 30° ⁇ a ⁇ 90°.
  • the end of the second part 232 close to the first part 231 covers the side wall 221 of the isolation part 22 and is connected to the first part 231. Therefore, the junction of the first part 231 and the second part 232 forms a step structure corresponding to the shape of the side wall 221 of the isolation part 22.
  • the present application controls the angle between the side wall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 within the range of 30° to 90°, thereby reducing the risk of fracture at the junction of the first portion 231 and the second portion 232, while allowing the top surface of the isolation portion 22 and the first portion 231 to have a larger area, thereby improving the electrical connection stability between the first drain 23 and the pixel electrode 30 and reducing the design difficulty of the first via 40.
  • FIG5a is a cross-sectional schematic diagram of an isolation portion provided in some embodiments of the present application when the angle between the side wall of the isolation portion and the bottom surface of the isolation portion is 90°.
  • the angle between the side wall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 is 90°, which can reduce the risk of fracture at the junction of the first portion 231 and the second portion 232 and reduce the area of the bottom surface of the isolation portion 22, while increasing the area of the top surface of the isolation portion 22 and the area of the first portion 231 as much as possible, thereby reducing the design difficulty of the first via 40.
  • FIG5b is a cross-sectional schematic diagram of the isolation portion when the angle between the side wall of the isolation portion and the bottom surface of the isolation portion is 30° according to some embodiments of the present application.
  • the angle between the side wall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 is 30°, which can reduce the risk of fracture at the junction of the first portion 231 and the second portion 232 as much as possible while taking into account the area of the top surface of the isolation portion 22 and the area requirements of the first portion 231, and the electrical connection stability between the first drain 23 and the pixel electrode 30, thereby improving the stability of the first drain 23 electrically connecting the pixel electrode 30 and the first drain ohmic contact portion 212.
  • the edge 223 of the isolation portion 22 protrudes from the edge 2311 of the first portion 231.
  • the edge 223 of the isolation portion 22 protrudes from the edge 23111 of the first portion 231 by 1-2 micrometers.
  • the edge 223 of the isolation portion 22 protrudes from the edge 2311 of the first portion 231 in the direction in which the isolation portion 22 moves away from the second portion 232, it is possible to ensure that the first portion 231 does not go over the edge 223 of the isolation portion 22, thereby avoiding a short circuit between the first portion 231 and other structures (such as the first source 24 of the first thin film transistor 20), thereby improving the stability of the first thin film transistor 20.
  • the first active layer 21 further includes a first source ohmic contact 213 disposed on the other side of the first channel 211, wherein the first thin film transistor 20 further includes a first source 24 formed integrally with the first drain 23, and the first source 24 is disposed on a surface of the first source ohmic contact 213 on a side away from the substrate 10, and covers the first source ohmic contact 213.
  • an edge of the first source 24 protrudes from an edge of the first source ohmic contact 213 by 0.5-1 micrometers.
  • the first source electrode 24 and the first drain electrode 23 are formed integrally, the production process of the first thin film transistor 20 can be simplified.
  • the first source electrode 24 is arranged on the surface of the first source ohmic contact portion 213 on the side away from the substrate 10 and covers the first source ohmic contact portion 213, the first source electrode 24 can protect the first source ohmic contact portion 213 to avoid damage to the first source ohmic contact portion 213 during the patterning process of the film layer where the first source electrode 24 is located.
  • the display panel also includes a first gate insulating layer 50, which is arranged on the side of the first active layer 21 away from the isolation portion 22, wherein the first gate insulating layer 50 includes a first sub-insulating layer 51, the first sub-insulating layer 51 is in contact with the first active layer 21, and the first sub-insulating layer 51 and the isolation portion 22 are made of the same material.
  • the isolation portion 22 covering the first channel 211 can protect the first channel 211. Since the first sub-insulating layer 51 is in contact with the first active layer 21, and the first sub-insulating layer 51 and the isolation portion 22 are made of the same material, the first gate insulating layer 50 can provide good protection for the first channel 211 while reducing material costs.
  • the first insulating layer and the isolation portion 22 are both made of silicon oxide, and the hydrogen content in the silicon oxide film layer is lower than the hydrogen content in the silicon nitride film layer.
  • the display panel also includes a second thin film transistor 60, which is arranged on the side of the substrate 10 facing the first thin film transistor 20, wherein the second thin film transistor 60 includes a second active layer 61, and the second active layer 61 is arranged on the side of the first active layer 21 away from the isolation portion 22, and the second active layer 61 includes a second channel, and the material of the second channel is different from the material of the first channel 211.
  • the type of the second thin film transistor 60 is different from the type of the first thin film transistor 20, so that the display panel can have two types of thin film transistors, thereby further improving the display performance of the display panel.
  • the second thin film transistor 60 is arranged in the non-display area NAA of the display panel, for example, it can be arranged in the gate drive circuit of the non-display area NAA, the material of the second channel is low-temperature polysilicon, and the type of the second thin film transistor 60 is a low-temperature polysilicon thin film transistor, so that the display panel can have advantages such as high mobility and high response speed.
  • the type of the second thin film transistor 60 is a low-temperature polysilicon thin film transistor with high mobility and high response speed, the driving ability of the gate drive circuit is stronger, so that the display panel including the second thin film transistor 60 can drive more pixels, so that the display panel can have a higher resolution and be applied to VR/AR display devices with higher requirements for resolution.
  • the number of various types of wiring (such as data lines, scan lines) will increase, resulting in a decrease in the aperture ratio of the display area AA of the display panel.
  • the present application sets the second thin film transistor 60 in the non-display area NAA of the display panel and sets the first thin film transistor 20 in the display area AA, so that the aperture ratio of the display area AA of the display panel can be improved while ensuring high resolution.
  • the second thin film transistor 60 can be arranged in the non-display area NAA and/or the display area AA of the display panel.
  • the type of the display panel can be a liquid crystal display panel; when at least part of the second thin film transistor 60 is arranged in the display area AA, the type of the display panel can be an organic light emitting diode display panel.
  • the first gate insulating layer 50 also includes a second sub-insulating layer 52, which is arranged on a side of the first sub-insulating layer 51 away from the first active layer 21, and the second sub-insulating layer 52 and the first sub-insulating layer 51 are made of different materials;
  • the first thin film transistor 20 includes a first gate 25, which is arranged on a side of the second sub-insulating layer 52 away from the first sub-insulating layer 51;
  • the second thin film transistor 60 also includes a second gate 62, which is arranged on a side of the second active layer 61 away from the substrate 10; wherein the first gate 25 and the second gate 62 are arranged on the same layer, and the first gate 25 and the second gate 62 are respectively in contact with the second sub-insulating layer 52.
  • the number of film layers of the display panel can be reduced, thereby reducing the production cost.
  • the second sub-insulating layer 52 can be set to a silicon nitride film layer with a higher hydrogen content, which is beneficial to improving the performance of the second thin film transistor 60.
  • the display panel also includes a second gate insulating layer 90, which is arranged on the side of the second active layer 61 facing the second gate 62, wherein the first gate insulating layer 50 arranged between the first active layer 21 and the first gate 25 has a first thickness, the second gate insulating layer 90 arranged between the second active layer 61 and the second gate 62 has a second thickness, and the ratio of the first thickness to the second thickness is less than or equal to 3.
  • the first thin film transistor 20 is a metal oxide thin film transistor, and therefore, compared with the second thin film transistor 60 which is a low-temperature polycrystalline silicon thin film transistor, the mobility is relatively low.
  • another gate can be provided on the side of the first channel 211 away from the first gate 25, thereby forming a double-gate structure to improve the performance of the first thin film transistor 20.
  • the isolation layer, the first drain 23 and the first via 40 are provided on the side of the first channel 211 away from the first gate 25 of the present application, a double-gate structure cannot be formed.
  • the present application makes the thickness of the first gate insulating layer 50 arranged between the first active layer 21 and the first gate 25 less than three times the thickness of the second gate insulating layer 90 arranged between the second active layer 61 and the second gate 62.
  • the thickness of the first gate insulating layer 50 arranged between the first active layer 21 and the first gate 25 is more than five times the thickness of the second gate insulating layer 90 arranged between the second active layer 61 and the second gate 62, the device performance of the first thin film transistor 20 can be significantly improved.
  • the second thin film transistor 60 also includes a second source 63 and a second drain 64
  • the first thin film transistor 20 also includes a first source conductive portion 70
  • the first source conductive portion 70 is arranged in the same layer as the second source 63 and the second drain 64, and the first source conductive portion 70 is electrically connected to the first source 24 through a second via 80.
  • the first source conductive portion 70 electrically connected to the first source 24 is arranged on the same layer as the second source 63 and the second drain 64, it is possible to facilitate signal introduction of the first thin film transistor 20 without increasing the number of film layers of the display panel, which is beneficial to reducing production costs.
  • the display panel further includes: at least one of a composite functional layer 100 , an interlayer dielectric layer 110 , a first planar layer 120 , a passivation layer 130 , a second planar layer 140 and a common electrode 150 .
  • the composite functional layer 100 is arranged between the second active layer 61 and the substrate 10, and the composite functional layer 100 includes at least one of a buffer layer and a light shielding layer;
  • the interlayer dielectric layer 110 is arranged on the side of the first drain 23 away from the substrate 10;
  • the first flat layer 120 is arranged on the side of the second source 63, the second drain 64, and the first source conductive portion 70 away from the substrate 10
  • the pixel electrode 30 is arranged on the side of the first flat layer 120 away from the substrate 10, and the first via 40 passes through the interlayer dielectric layer 110 and the first flat layer 120;
  • the passivation layer 130 is arranged on the side of the pixel electrode 30 away from the substrate 10;
  • the second flat layer 140 is arranged on the side of the passivation layer 130 away from the substrate 10;
  • the common electrode 150 is arranged on the side of the second flat layer 140 away from the substrate 10.
  • the present application provides a method for preparing a display panel, the method for preparing a display panel comprising step S01, step S02, step S03, step S04, step S05, step S06, step S07, step S08, step S09, step S10, and step S11.
  • FIG6a is a schematic diagram of the structure of a display panel corresponding to step S01 in the method for preparing a display panel provided in an embodiment of the present application.
  • step S01 includes: providing a substrate 10.
  • step S01 also includes forming a composite functional layer 100 on the substrate 10, wherein the composite functional layer 100 includes at least one of a buffer layer and a light shielding layer.
  • Fig. 6b is a schematic diagram of the structure of the display panel corresponding to step S02 in the method for manufacturing a display panel provided in an embodiment of the present application.
  • step S02 includes: forming a second active layer 61 of a second thin film transistor on one side of the substrate 10, the second active layer 61 including a second channel and a second source region and a second drain region located on both sides of the second channel.
  • FIG6c is a schematic diagram of the structure of the display panel corresponding to step S03 in the method for manufacturing a display panel provided in an embodiment of the present application.
  • step S03 includes: forming a second gate insulating layer 90 on a side of the second active layer 61 away from the substrate 10, and forming a second gate 62 of the second thin film transistor 60 and a first gate 25 of the first thin film transistor on a side of the second gate insulating layer 90 away from the substrate 10.
  • FIG6d is a schematic diagram of the structure of the display panel corresponding to step S04 in the method for preparing a display panel provided in an embodiment of the present application.
  • step S04 includes: forming a first gate insulating layer 50 on the side of the second gate insulating layer 90 away from the substrate 10, and covering the first gate 25 and the second gate 62, the first gate insulating layer 50 includes a first sub-insulating layer 51 and a second sub-insulating layer 52, the first sub-insulating layer 51 is arranged on the side of the second sub-insulating layer 52 away from the substrate 10, the hydrogen content of the first sub-insulating layer 51 is lower than the hydrogen content of the second sub-insulating layer 52, and the second channel is hydrogen activated, and then, forming the first active layer 21 of the first thin film transistor 20 on the side of the first gate insulating layer 50 away from the substrate 10, the first active layer 21 includes a first channel 211 and a first source ohmic contact portion and a first drain ohmic contact
  • FIG6e is a schematic diagram of the structure of the display panel corresponding to step S05 in the method for preparing a display panel provided in an embodiment of the present application.
  • step S05 includes: forming an isolation layer on the side of the first channel 211 away from the substrate 10, the isolation layer being made of the same material as the first sub-insulating layer 51, such as silicon oxide, and then, through exposure, development and etching, the isolation layer is processed to form an isolation portion 22 corresponding to the first channel 211, the thickness of the isolation portion 22 is 50-250nm, and the sidewall 221 of the isolation portion 22 and the bottom surface 222 of the isolation portion 22 are substantially the same as the first sub-insulating layer 51.
  • the angle is a, 30° ⁇ a ⁇ 90°, and a photoresist is formed on the side of the isolation portion 22 away from the first channel 211. Then, the isolation portion 22 and the photoresist are used as masks to perform conductorization on the exposed first source ohmic contact portion and the first drain ohmic contact portion that have not been conductorized.
  • the conductorization process includes boron ion doping or argon plasma treatment, thereby forming a first source ohmic contact portion 213 and a first drain ohmic contact portion 212, and then the photoresist is stripped off.
  • FIG6f is a schematic diagram of the structure of the display panel corresponding to step S06 in the method for preparing the display panel provided in the embodiment of the present application.
  • step S06 includes: forming a transparent conductive layer on the side of the isolation portion 22 away from the substrate 10, patterning the transparent conductive layer to form a first source 24 and a first drain 23, wherein the first source 24 covers the first source ohmic contact portion 213, and the edge of the first source 24 exceeds the edge of the first source ohmic contact portion 213 by 0.5-1 micrometer; the first drain 23 includes a first portion 231 and a second portion 232, wherein the second portion 232 of the first drain 23 covers the first drain ohmic contact portion 212, and the edge of the second portion 232 exceeds the edge of the first drain ohmic contact portion 212 by 0.5-1 micrometer, and the edge 223 of the isolation portion 22 protrudes from the edge 2311 of the first portion 231 of the first drain 23 by 1-2 micrometers.
  • FIG6g is a schematic diagram of the structure of the display panel corresponding to step S07 in the method for preparing the display panel provided in an embodiment of the present application.
  • step S07 includes: forming an interlayer dielectric layer 110 on the side of the transparent conductive layer away from the substrate 10, the interlayer dielectric layer 110 being a silicon nitride film layer, a silicon oxide film layer, or a stack of a silicon nitride film layer and a silicon oxide film layer, and performing an opening process on the interlayer dielectric layer 110 to form a plurality of openings exposing the second source region, the second drain region, and the first source 24, wherein the opening exposing the first source 24 is a second via 80.
  • FIG6h is a schematic diagram of the structure of the display panel corresponding to step S08 in the method for preparing the display panel provided in an embodiment of the present application.
  • step S08 includes: forming a source-drain metal layer on the side of the interlayer dielectric layer 110 away from the substrate 10, the source-drain metal layer may be Ti, Al, Mo or their alloys and stacks, and patterning the source-drain metal layer to form a second source 63, a second drain 64 and a first source conductive portion 70, the second source 63 is electrically connected to the second source region through an opening exposing the second source region, the second drain 64 is electrically connected to the second drain region through an opening exposing the second drain region, and the first source conductive portion 70 is electrically connected to the first source 24 through an opening (second via 80) exposing the first source 24.
  • FIG6i is a schematic diagram of the structure of the display panel corresponding to step S09 in the method for preparing the display panel provided in an embodiment of the present application.
  • step S09 includes: using a coating exposure and development process, a patterned first flat layer 120 including a via hole corresponding to the first portion 231 is formed on the side of the second source electrode 63, the second drain electrode 64, and the first source conductive portion 70 away from the substrate 10, and then, the interlayer dielectric layer 110 is etched using the first flat layer 120 as a mask, and a via hole penetrating the interlayer dielectric layer 110 is formed at a position of the interlayer dielectric layer 110 corresponding to the first portion 231, and the via hole penetrating the interlayer dielectric layer 110 and the via hole in the first flat layer 120 together constitute a first via hole 40.
  • the first via hole 40 penetrating the first flat layer 120 and the interlayer dielectric layer 110 can also be formed by forming a photoresist mask on the first flat layer 120 through
  • FIG6j is a schematic diagram of the structure of the display panel corresponding to step S10 in the method for preparing a display panel provided in an embodiment of the present application.
  • step S10 includes: forming a pixel electrode 30 on a side of the first planar layer 120 away from the substrate 10, and the pixel electrode 30 is electrically connected to the first portion 231 of the first drain electrode 23 through the first via hole 40.
  • FIG6k is a schematic diagram of the structure of the display panel corresponding to step S11 in the method for preparing a display panel provided in an embodiment of the present application.
  • step S11 includes: forming a passivation layer 130, a common electrode 150, and a second planarization layer 140 in sequence on a side of the pixel electrode 30 away from the substrate 10, and the second planarization layer 140 fills the groove formed by the pixel electrode 30 at the first via hole 40.
  • the present application provides a display panel, the display panel having a display area, the display panel comprising: a substrate; a first thin film transistor, arranged on one side of the substrate and located in the display area; a pixel electrode, arranged on the side of the first thin film transistor away from the substrate and located in the display area;
  • the first thin film transistor comprises a first active layer, an isolation portion and a first drain electrode, wherein the first active layer comprises a first channel and a first drain electrode ohmic contact portion arranged on one side of the first channel;
  • the isolation portion is arranged on the surface of the first channel away from the substrate and covers the first channel;
  • the first drain electrode comprises a transparent first part and a transparent second part, the first part is arranged on the surface of the isolation portion away from the first active layer, and the second part is arranged on the surface of the first drain electrode ohmic contact portion away from the substrate; wherein the pixel electrode is electrically connected to the first part through a first via hole arranged on the side of the first part

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Abstract

本申请提供一种显示面板，第一有源层包括第一沟道和第一漏极欧姆接触部；隔离部覆盖第一沟道；第一漏极包括透明的第一部分和透明的第二部分，第一部分设置在隔离部背离第一有源层的一侧的表面上，第二部分设置在第一漏极欧姆接触部之上；像素电极通过设置在第一部分背离隔离部的一侧的第一过孔与第一部分电性连接。

Description

一种显示面板 技术领域
本申请涉及显示技术领域，具体涉及一种显示面板。
 背景技术
随着显示技术的发展，手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机、虚拟现实（英文全称：Virtual Reality，简称：VR）显示设备、增强现实（英文全称：Augmented Reality，简称：AR）显示设备等依赖于显示面板的显示功能的消费性电子产品层出不穷。而“元宇宙”概念的兴起，也使得VR/AR显示设备受到了消费者的广泛关注，具有广阔的市场应用前景。
VR/AR显示设备为近眼显示设备，对其中的显示面板的开口率和显示画质具有较高的要求，且需要尽可能地降低生产制造成本。显示面板包括像素电极和与所述像素电极电性连接的薄膜晶体管（英文全称：Thin Film Transistor，简称：TFT），该薄膜晶体管是控制该像素电极获取像素电压的开关元件，该薄膜晶体管与该像素电极的连接方式及该薄膜晶体管的结构直接影响显示面板的开口率、显示画质和生产制造成本。
因此，如何设置与像素电极电性连接的薄膜晶体管的结构，以及该薄膜晶体管与该像素电极的连接方式，以使显示面板兼具高开口率、高显示画质和低生产制造成本，是本领域技术人员亟需解决的问题。
 发明概述
本申请提供一种显示面板，能够有效解决显示面板存在的在实现高开口率的同时无法兼顾显示画质和生产制造成本的问题。
本申请提供一种显示面板，所述显示面板具有显示区，所述显示面板包括：衬底；第一薄膜晶体管，设置在所述衬底的一侧，并位于所述显示区；像素电极，设置在所述第一薄膜晶体管背离所述衬底的一侧，并位于所述显示区；其中，所述第一薄膜晶体管包括：第一有源层，包括第一沟道和设置在所述第一沟道的一侧的第一漏极欧姆接触部；隔离部，设置在所述第一沟道背离所述衬底的一侧的表面上，并覆盖所述第一沟道；第一漏极，包括透明的第一部分和透明的第二部分，所述第一部分设置在所述隔离部背离所述第一有源层的一侧的表面上，所述第二部分设置在所述第一漏极欧姆接触部背离所述衬底的一侧的表面上；其中，所述像素电极通过设置在所述第一部分背离所述隔离部的一侧的第一过孔与所述第一部分电性连接。
 附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为相关技术中的一种显示面板的平面示意图。
图2为相关技术中的一种显示面板的剖面示意图。
图3为本申请一些实施例提供的一种显示面板的平面示意图。
图4为本申请一些实施例提供的一种显示面板的剖面示意图。
图5a为本申请一些实施例提供的隔离部的侧壁与隔离部的底面所呈的夹角为90°时的隔离部的剖面示意图。
图5b为本申请一些实施例提供的隔离部的侧壁与隔离部的底面所呈的夹角为30°时的隔离部的剖面示意图。
图6a为本申请实施例提供的显示面板的制备方法中与步骤S01对应的显示面板的结构示意图。
图6b为本申请实施例提供的显示面板的制备方法中与步骤S02对应的显示面板的结构示意图。
图6c为本申请实施例提供的显示面板的制备方法中与步骤S03对应的显示面板的结构示意图。
图6d为本申请实施例提供的显示面板的制备方法中与步骤S04对应的显示面板的结构示意图。
图6e为本申请实施例提供的显示面板的制备方法中与步骤S05对应的显示面板的结构示意图。
图6f为本申请实施例提供的显示面板的制备方法中与步骤S06对应的显示面板的结构示意图。
图6g为本申请实施例提供的显示面板的制备方法中与步骤S07对应的显示面板的结构示意图。
图6h为本申请实施例提供的显示面板的制备方法中与步骤S08对应的显示面板的结构示意图。
图6i为本申请实施例提供的显示面板的制备方法中与步骤S09对应的显示面板的结构示意图。
图6j为本申请实施例提供的显示面板的制备方法中与步骤S10对应的显示面板的结构示意图。
图6k为本申请实施例提供的显示面板的制备方法中与步骤S11对应的显示面板的结构示意图。
附图标记说明：
显示区AA`；非显示区NAA`；衬底10`；薄膜晶体管20`；有源层21`；沟道211`；漏极欧姆接触部212`；第一栅极22`；第二栅极23`；源极24`；漏极25`；像素电极30`；第一过孔40`；第二过孔50`；
显示区AA；非显示区NAA；衬底10；第一薄膜晶体管20；第一有源层21；第一沟道211；第一漏极欧姆接触部212；第一源极欧姆接触部213；隔离部22；隔离部的侧壁221；隔离部的底面222；隔离部的边缘223；第一漏极23；第一部分231；第一部分的边缘2311；第二部分232；第一源极24；第一栅极25；像素电极30；第一过孔40；第一栅极绝缘层50；第一子绝缘层51；第二子绝缘层52；第二薄膜晶体管60；第二有源层61；第二栅极62；第二源极63；第二漏极64；第一源极导接部70；第二过孔80；第二栅极绝缘层90；复合功能层100；层间介质层110；第一平坦层120；钝化层130；第二平坦层140；公共电极150；
 本发明的实施方式
本申请提供一种显示面板，所述显示面板具有显示区，所述显示面板包括：衬底；第一薄膜晶体管，设置在所述衬底的一侧，并位于所述显示区；像素电极，设置在所述第一薄膜晶体管背离所述衬底的一侧，并位于所述显示区；其中，所述第一薄膜晶体管包括：第一有源层，包括第一沟道和设置在所述第一沟道的一侧的第一漏极欧姆接触部；隔离部，设置在所述第一沟道背离所述衬底的一侧的表面上，并覆盖所述第一沟道；第一漏极，包括透明的第一部分和透明的第二部分，所述第一部分设置在所述隔离部背离所述第一有源层的一侧的表面上，所述第二部分设置在所述第一漏极欧姆接触部背离所述衬底的一侧的表面上；其中，所述像素电极通过设置在所述第一部分背离所述隔离部的一侧的第一过孔与所述第一部分电性连接。
可选的，所述第二部分覆盖所述第一漏极欧姆接触部。
可选的，所述第二部分覆盖所述隔离部的侧壁，且所述隔离部的侧壁与所述隔离部的底面所呈的夹角为a，30°≤a≤90°。
可选的，在所述隔离部远离所述第二部分的方向上，所述隔离部的边缘凸出于所述第一部分的边缘。
可选的，所述第一有源层还包括设置在所述第一沟道的另一侧的第一源极欧姆接触部，其中，所述第一薄膜晶体管还包括与所述第一漏极一体形成的第一源极，所述第一源极设置在所述第一源极欧姆接触部背离所述衬底的一侧的表面上，并覆盖所述第一源极欧姆接触部。
可选的，所述显示面板还包括第一栅极绝缘层，所述第一栅极绝缘层设置在所述第一有源层背离所述隔离部的一侧，其中，所述第一栅极绝缘层包括第一子绝缘层，所述第一子绝缘层与所述第一有源层相接触，且所述第一子绝缘层与所述隔离部的材质相同。
可选的，所述显示面板还包括第二薄膜晶体管，所述第二薄膜晶体管设置在所述衬底朝向所述第一薄膜晶体管的一侧，其中，所述第二薄膜晶体管包括第二有源层，所述第二有源层设置在所述第一有源层背离所述隔离部的一侧，所述第二有源层包括第二沟道，所述第二沟道的材质与所述第一沟道的材质不同。
可选的，所述第一栅极绝缘层还包括第二子绝缘层，所述第二子绝缘层设置在所述第一子绝缘层背离所述第一有源层的一侧，且所述第二子绝缘层与所述第一子绝缘层的材质不同；所述第一薄膜晶体管包括第一栅极，所述第一栅极设置在所述第二子绝缘层背离所述第一子绝缘层的一侧；所述第二薄膜晶体管还包括第二栅极，所述第二栅极设置在所述第二有源层背离所述衬底的一侧；其中，所述第一栅极与所述第二栅极同层设置，且所述第一栅极、所述第二栅极分别与所述第二子绝缘层相接触。
可选的，所述显示面板还包括第二栅极绝缘层，所述第二栅极绝缘层设置在所述第二有源层朝向所述第二栅极的一侧，其中，设置在所述第一有源层和所述第一栅极之间的所述第一栅极绝缘层具有第一厚度，设置在所述第二有源层和所述第二栅极之间的所述第二栅极绝缘层具有第二厚度，且所述第一厚度与所述第二厚度的比值小于或等于3。
可选的，第二薄膜晶体管还包括第二源极和第二漏极，所述第一薄膜晶体管还包括第一源极导接部，所述第一源极导接部与所述第二源极和所述第二漏极同层设置，所述第一源极导接部通过第二过孔与所述第一源极电性连接。
本申请提供一种显示面板，所述显示面板具有显示区，所述显示面板包括：衬底；第一薄膜晶体管，设置在所述衬底的一侧，并位于所述显示区；像素电极，设置在所述第一薄膜晶体管背离所述衬底的一侧，并位于所述显示区；所述第一薄膜晶体管包括第一有源层、隔离部和第一漏极，其中，所述第一有源层包括第一沟道和设置在所述第一沟道的一侧的第一漏极欧姆接触部；所述隔离部设置在所述第一沟道背离所述衬底的一侧的表面上，并覆盖所述第一沟道；所述第一漏极包括透明的第一部分和透明的第二部分，所述第一部分设置在所述隔离部背离所述第一有源层的一侧的表面上，所述第二部分设置在所述第一漏极欧姆接触部背离所述衬底的一侧的表面上；其中，所述像素电极通过设置在所述第一部分背离所述隔离部的一侧的第一过孔与所述第一部分电性连接。本申请提供的显示面板能够在实现高开口率的同时，提高显示面板的显示画质，降低显示面板的生产制造成本。
下面结合附图对以上技术方案的具体实施进行详细说明。
图1为相关技术中的一种显示面板的平面示意图；图2为相关技术中的一种显示面板的剖面示意图。参照图1和图2所示，相关技术中的一种显示面板100`具有显示区AA`和非显示区NAA`，所述显示面板100`包括衬底10`、设置在所述衬底10`的一侧的薄膜晶体管20`、设置在所述薄膜晶体管20`背离所述衬底10`的一侧的像素电极30`，所述薄膜晶体管20`与所述像素电极30`均位于所述显示面板100`的显示区AA`，其中，所述薄膜晶体管20`包括有源层21`、第一栅极22`、第二栅极23`、源极24`和漏极25`，所述有源层21`包括沟道211`和位于沟道211`的一侧的漏极欧姆接触部212`，所述漏极25`通过第一过孔40`与所述漏极欧姆接触部212`搭接，所述像素电极30`通过第二过孔50`与所述漏极25`搭接。其中，所述漏极25`由透明导电材料制成，因此，能够使所述漏极25`与所述漏极欧姆接触部212`搭接的区域具有高透光性，以用于执行显示功能，进而提高显示面板100`的开口率。但由于所述漏极25`与所述漏极欧姆接触部212`搭接的区域存在第一过孔40`，第一过孔40`这种的过孔结构，其所在区域在执行显示功能时，容易出现显示不均的现象，使得显示面板100`的显示质量降低，且第一过孔40`和第二过孔50`会增加显示面板100`的制程工艺步骤，进而增加显示面板100`的生产制造成本。
为了使显示面板能够在实现高开口率的同时，提高显示画质和降低生产制造成本，本申请提供一种显示面板及其制备方法。
图3为本申请一些实施例提供的一种显示面板的平面示意图；图4为本申请一些实施例提供的一种显示面板的剖面示意图。参照图3和图4所示，第一方面，本申请实施例提供一种显示面板，所述显示面板具有显示区AA和非显示区NAA，所述非显示区NAA围绕所述显示区AA，所述显示区AA阵列设置有多个显示像素。所述显示面板包括衬底10、第一薄膜晶体管20和像素电极30，其中，所述第一薄膜晶体管20设置在所述衬底10的一侧，并位于所述显示区AA；所述像素电极30设置在所述第一薄膜晶体管20背离所述衬底10的一侧，并位于所述显示区AA。
在本申请的一些实施例中，所述第一薄膜晶体管20包括第一有源层21、隔离部22和第一漏极23，其中，所述第一有源层21包括第一沟道211和设置在所述第一沟道211的一侧的第一漏极欧姆接触部212；所述隔离部22设置在所述第一沟道211背离所述衬底10的一侧的表面上，并覆盖所述第一沟道211；所述第一漏极23包括透明的第一部分231和透明的第二部分232，所述第一部分231设置在所述隔离部22背离所述第一有源层21的一侧的表面上，所述第二部分232设置在所述第一漏极欧姆接触部212背离所述衬底10的一侧的表面上；其中，所述像素电极30通过设置在所述第一部分231背离所述隔离部22的一侧的第一过孔40与所述第一部分231电性连接。
本申请提供的所述显示面板中，由于设置在所述第一漏极欧姆接触部212背离所述衬底10的一侧的表面上的所述第二部分232是透明的，因此，能够使所述第一漏极欧姆接触部212所在的区域具有高透光性，以用于执行显示功能，进而提高显示面板的开口率。
并且，由于所述像素电极30通过设置在所述第一部分231背离所述隔离部22的一侧的第一过孔40与所述第一部分231电性连接，而所述第一部分231设置在与所述第一沟道211对应的所述隔离部22之上，也即，在垂直于所述衬底10的方向上，所述第一过孔40与所述第一漏极欧姆接触部212错位设置，因此，所述第一过孔40不会对所述第一漏极欧姆接触部212所在的区域的显示功能造成影响。
另外，由于所述第一部分231设置在所述隔离部22背离所述第一有源层21的一侧的表面上，所述第二部分232设置在所述第一漏极欧姆接触部212背离所述衬底10的一侧的表面上，也即，在垂直于所述衬底10的方向上，所述第一部分231和所述第二部分232之间仅间隔一个所述隔离部22，因此，所述第一部分231和所述第二部分232在一体形成时无需通过过孔结构相连，从而能够使所述第二部分232的上方无需设置过孔结构，使得所述第一漏极欧姆接触部212所在的区域与其他显示区AA域具有一致的显示效果，提高了显示面板的显示均一性，改善了显示面板的显示质量。
在本申请的一些实施例中，所述第一过孔40在所述第一有源层21上的垂直投影与所述第一沟道211相重叠。
本申请提供的所述显示面板中，薄膜晶体管的沟道区域往往对应设置有不透光的栅极，也即，显示面板在薄膜晶体管的沟道区域不具有显示功能，本申请通过将所述第一过孔40在所述第一有源层21上的垂直投影与所述第一沟道211相重叠，从而能够使所述第一过孔40不占据显示区AA中具有显示功能的区域，从而能够进一布提高所述显示面板的开口率。
在本申请的一些实施例中，所述第一薄膜晶体管20为金属氧化物薄膜晶体管，所述第一沟道211的材质为金属氧化物半导体，所述第一漏极欧姆接触部212为金属氧化物半导体材料经导体化处理后形成的透明导电结构。从而能够使所述显示面板具有低漏电流、低刷新率、高透光率的优势。
在本申请的一些实施例中，所述第二部分232覆盖所述漏极欧姆接触部。可选的，所述第二部分232的边缘凸出于所述漏极欧姆接触部的边缘0.5-1微米。
本申请提供的所述显示面板中，由于所述第二部分232覆盖所述第一漏极欧姆接触部212，因此，所述第二部分232能够对所述第一漏极欧姆接触部212进行保护，避免在所述第一漏极23所在膜层的图案化过程中，对所述第一漏极欧姆接触部212造成损伤。
在本申请的一些实施例中，所述第二部分232覆盖所述隔离部22的侧壁221，且所述隔离部22的侧壁221与所述隔离部22的底面222所呈的夹角为a，30°≤a≤90°。
本申请提供的所述显示面板中，所述第二部分232靠近所述第一部分231的一端覆盖所述隔离部22的侧壁221，并与所述第一部分231相连接，因此，所述第一部分231和所述第二部分232的交界处会形成与所述隔离部22的侧壁221的形状相对应的台阶结构。当所述隔离部22的侧壁221与所述隔离部22的底面222所呈的夹角过大时，如钝角，会在所述隔离部22的侧壁221与所述第一有源层21之间形成底切结构，大大增加所述第一部分231和所述第二部分232的交界处的断裂风险；当所述隔离部22的侧壁221与所述隔离部22的底面222所呈的夹角过小时，如小于30°的情况下，则会减小所述隔离部22的顶面的面积，进而减小所述第一部分231的面积，影响所述第一漏极23和所述像素电极30的电性连接稳定性。本申请通过使所述隔离部22的侧壁221与所述隔离部22的底面222所呈的夹角控制在30°至90°的范围内，能够在降低所述第一部分231和所述第二部分232的交界处的断裂风险的同时，使所述隔离部22的顶面和第一部分231具有较大的面积，进而提高所述第一漏极23和所述像素电极30的电性连接稳定性，降低所述第一过孔40的设计难度。
图5a为本申请一些实施例提供的隔离部的侧壁与隔离部的底面所呈的夹角为90°时的隔离部的剖面示意图。结合图4和图5a所示，所述隔离部22的侧壁221与所述隔离部22的底面222所呈的夹角为90°，能够在降低所述第一部分231和所述第二部分232的交界处的断裂风险和缩减所述隔离部22的底面的面积的同时，尽可能地增大使所述隔离部22的顶面的面积和所述第一部分231的面积，降低所述第一过孔40的设计难度。
图5b为本申请一些实施例提供的隔离部的侧壁与隔离部的底面所呈的夹角为30°时的隔离部的剖面示意图。结合图4和图5b所示，所述隔离部22的侧壁221与所述隔离部22的底面222所呈的夹角为30°，能够在兼顾所述隔离部22的顶面的面积和所述第一部分231的面积需求、所述第一漏极23和所述像素电极30的电性连接稳定性的情况下，尽可能地降低所述第一部分231和所述第二部分232的交界处的断裂风险，进而提高所述第一漏极23电性连接所述像素电极30、所述第一漏极欧姆接触部212的稳定性。
在本申请的一些实施例中，在所述隔离部22远离所述第二部分232的方向上，所述隔离部22的边缘223凸出于所述第一部分231的边缘2311。可选的，所述隔离部22的边缘223凸出于所述第一部分231的边缘23111-2微米。
本申请提供的所述显示面板中，由于在所述隔离部22远离所述第二部分232的方向上，所述隔离部22的边缘223凸出于所述第一部分231的边缘2311，因此，能够保证所述第一部分231不会越过所述所述隔离部22的边缘223，从而避免所述第一部分231与其他结构（如第一薄膜晶体管20的第一源极24）发生短接，提高所述第一薄膜晶体管20的稳定性。
在本申请的一些实施例中，所述第一有源层21还包括设置在所述第一沟道211的另一侧的第一源极欧姆接触部213，其中，所述第一薄膜晶体管20还包括与所述第一漏极23一体形成的第一源极24，所述第一源极24设置在所述第一源极欧姆接触部213背离所述衬底10的一侧的表面上，并覆盖所述第一源极欧姆接触部213。可选的，所述第一源极24的边缘凸出于所述第一源极欧姆接触部213的边缘0.5-1微米。
本申请提供的所述显示面板中，由于所述第一源极24与所述第一漏极23一体形成，因此，能够简化所述第一薄膜晶体管20的生产制备工艺。并且，由于所述第一源极24设置在所述第一源极欧姆接触部213背离所述衬底10的一侧的表面上，并覆盖所述第一源极欧姆接触部213，因此，所述第一源极24能够对所述第一源极欧姆接触部213进行保护，避免在所述第一源极24所在膜层的图案化过程中，对所述第一源极欧姆接触部213造成损伤。
在本申请的一些实施例中，所述显示面板还包括第一栅极绝缘层50，所述第一栅极绝缘层50设置在所述第一有源层21背离所述隔离部22的一侧，其中，所述第一栅极绝缘层50包括第一子绝缘层51，所述第一子绝缘层51与所述第一有源层21相接触，且所述第一子绝缘层51与所述隔离部22的材质相同。
本申请提供的所述显示面板中，覆盖所述第一沟道211的所述隔离部22能够对所述第一沟道211进行保护，由于所述第一子绝缘层51与所述第一有源层21相接触，且所述第一子绝缘层51与所述隔离部22的材质相同，因此，能够在降低物料成本的同时，使所述第一栅极绝缘层50对所述第一沟道211具有良好的保护作用。
可选的，所述一子绝缘层和所述隔离部22的材质均为氧化硅，所述氧化硅膜层中的氢含量低于氮化硅膜层中的氢含量。
在本申请的一些实施例中，所述显示面板还包括第二薄膜晶体管60，所述第二薄膜晶体管60设置在所述衬底10朝向所述第一薄膜晶体管20的一侧，其中，所述第二薄膜晶体管60包括第二有源层61，所述第二有源层61设置在所述第一有源层21背离所述隔离部22的一侧，所述第二有源层61包括第二沟道，所述第二沟道的材质与所述第一沟道211的材质不同。
本申请提供的所述显示面板中，由于所述第二沟道的材质与所述第一沟道211的材质不同，因此，所述第二薄膜晶体管60的类型与所述第一薄膜晶体管20的类型不同，从而能够使所述显示面板具有两种类型的薄膜晶体管，从而使所述显示面板的显示性能进一步提高。
在本申请的一些实施例中，所述第二薄膜晶体管60设置在显示面板的非显示区NAA，例如可以设置在所述非显示区NAA的栅极驱动电路中，所述第二沟道的材质为低温多晶硅，所述第二薄膜晶体管60的类型为低温多晶硅薄膜晶体管，从而能够使所述显示面板具有高迁移率、高反应速度等优势。另外，由于所述第二薄膜晶体管60的类型为具有高迁移率、高反应速度的低温多晶硅薄膜晶体管，因此，所述栅极驱动电路的驱动能力更强，从而能够使包括所述第二薄膜晶体管60的显示面板具有能够驱动更多像素的能力，使所述显示面板能够具有更高的分辨率，并应用在对分辨率具有更高要求的VR/AR显示设备。与此同时，由于显示面板的分辨率提高，因此，会使得各类布线（如数据线、扫描线）的数量增多，造成显示面板的显示区AA的开口率下降，本申请通过使所述显示面板在非显示区NAA设置所述第二薄膜晶体管60的同时，在显示区AA设置所述第一薄膜晶体管20，从而能够在保证高分辨率的情况下，提高显示面板的显示区AA的开口率。
需要说明的是，所述第二薄膜晶体管60可以设置在显示面板的非显示区NAA和/或显示区AA。其中，当所述第二薄膜晶体管60设置在非显示区NAA时，所述显示面板的类型可以是液晶显示面板；当至少部分所述第二薄膜晶体管60设置在显示区AA时，所述显示面板的类型可以是有机发光二极管显示面板。
在本申请的一些实施例中，所述第一栅极绝缘层50还包括第二子绝缘层52，所述第二子绝缘层52设置在所述第一子绝缘层51背离所述第一有源层21的一侧，且所述第二子绝缘层52与所述第一子绝缘层51的材质不同；所述第一薄膜晶体管20包括第一栅极25，所述第一栅极25设置在所述第二子绝缘层52背离所述第一子绝缘层51的一侧；所述第二薄膜晶体管60还包括第二栅极62，所述第二栅极62设置在所述第二有源层61背离所述衬底10的一侧；其中，所述第一栅极25与所述第二栅极62同层设置，且所述第一栅极25、所述第二栅极62分别与所述第二子绝缘层52相接触。
本申请提供的所述显示面板中，由于所述第一栅极25与所述第二栅极62同层设置，因此，能够减少所述显示面板的膜层数量，降低生产制造成本。
并且，由于所述第一栅极25、所述第二栅极62分别与所述第二子绝缘层52相接触，且所述第二子绝缘层52与所述第一子绝缘层51的材质不同，因此，可以将所述第二子绝缘层52设置成具有更高氢含量的氮化硅膜层，从而有利于提高所述第二薄膜晶体管60的性能。
在本申请的一些实施例中，所述显示面板还包括第二栅极绝缘层90，所述第二栅极绝缘层90设置在所述第二有源层61朝向所述第二栅极62的一侧，其中，设置在所述第一有源层21和所述第一栅极25之间的所述第一栅极绝缘层50具有第一厚度，设置在所述第二有源层61和所述第二栅极62之间的所述第二栅极绝缘层90具有第二厚度，且所述第一厚度与所述第二厚度的比值小于或等于3。
本申请提供的所述显示面板中，所述第一薄膜晶体管20为金属氧化物薄膜晶体管，因此，相较于类型为低温多晶硅薄膜晶体管的第二薄膜晶体管60而言，迁移率相对较低，相关技术中，可以通过在所述第一沟道211背离所述第一栅极25的一侧设置另一栅极，从而通过形成双栅结构，提高所述第一薄膜晶体管20的性能，但由于本申请的所述第一沟道211背离所述第一栅极25的一侧设置有所述隔离层、所述第一漏极23和所述第一过孔40，因此无法形成双栅结构。为了能够使所述第一薄膜晶体管20在不具有双栅结构的情况下，依旧具有较高的迁移率，本申请通过使设置在所述第一有源层21和所述第一栅极25之间的所述第一栅极绝缘层50的厚度为设置在所述第二有源层61和所述第二栅极62之间的所述第二栅极绝缘层90的厚度的三倍以下，从而能够相较于相关技术中，设置在所述第一有源层21和所述第一栅极25之间的所述第一栅极绝缘层50的厚度为设置在所述第二有源层61和所述第二栅极62之间的所述第二栅极绝缘层90的厚度为五倍以上的薄膜晶体管架构而言，显著提高所述第一薄膜晶体管20的器件性能。
在本申请的一些实施例中，第二薄膜晶体管60还包括第二源极63和第二漏极64，所述第一薄膜晶体管20还包括第一源极导接部70，所述第一源极导接部70与所述第二源极63和所述第二漏极64同层设置，所述第一源极导接部70通过第二过孔80与所述第一源极24电性连接。
本申请提供的所述显示面板中，由于与所述第一源极24电性连接的所述第一源极导接部70与所述第二源极63和所述第二漏极64同层设置，因此，能够使所述第一薄膜晶体管20的信号导入更为方便，且不会增加所述显示面板的膜层数量，有利于降低生产制造成本。
在本申请的一些实施例中，所述显示面板还包括：复合功能层100、层间介质层110、第一平坦层120、钝化层130、第二平坦层140和公共电极150中的至少一种。其中，所述复合功能层100设置在所述第二有源层61和所述衬底10之间，所述复合功能层100包括缓冲层、遮光层中的至少一种；所述层间介质层110设置在所述第一漏极23背离所述衬底10的一侧；所述第一平坦层120设置在所述第二源极63、第二漏极64、第一源极导接部70背离所述衬底10的一侧，所述像素电极30设置在所述第一平坦层120背离所述衬底10的一侧，且所述第一过孔40贯穿所述层间介质层110和所述第一平坦层120；所述钝化层130设置在所述像素电极30背离所述衬底10的一侧；所述第二平坦层140设置在所述钝化层130背离所述衬底10的一侧；所述公共电极150设置在所述第二平坦层140背离所述衬底10的一侧。
第二方面，本申请提供一种显示面板的制备方法，所述显示面板的制备方法包括步骤S01、步骤S02、步骤S03、步骤S04、步骤S05、步骤S06、步骤S07、步骤S08、步骤S09、步骤S10、步骤S11。
图6a为本申请实施例提供的显示面板的制备方法中与步骤S01对应的显示面板的结构示意图。参照图6a所示，步骤S01包括：提供一衬底10。可选的，步骤S01还包括在所述衬底10上形成复合功能层100，所述复合功能层100包括缓冲层、遮光层中的至少一种。
图6b为本申请实施例提供的显示面板的制备方法中与步骤S02对应的显示面板的结构示意图。参照图6b所示，步骤S02包括：在所述衬底10的一侧形成第二薄膜晶体管的第二有源层61，所述第二有源层61包括第二沟道和位于第二沟道两侧的第二源极区和第二漏极区。
图6c为本申请实施例提供的显示面板的制备方法中与步骤S03对应的显示面板的结构示意图。参照图6c所示，步骤S03包括：在第二有源层61背离所述衬底10的一侧形成第二栅极绝缘层90，并在第二栅极绝缘层90背离所述衬底10的一侧形成所述第二薄膜晶体管60的第二栅极62和第一薄膜晶体管的第一栅极25。
图6d为本申请实施例提供的显示面板的制备方法中与步骤S04对应的显示面板的结构示意图。参照图6d所示，步骤S04包括：在所述第二栅极绝缘层90背离所述衬底10的一侧形成第一栅极绝缘层50，并覆盖所述第一栅极25和所述第二栅极62，所述第一栅极绝缘层50包括第一子绝缘层51和第二子绝缘层52，所述第一子绝缘层51设置在所述第二子绝缘层52背离所述衬底10的一侧，所述第一子绝缘层51的氢含量低于所述第二子绝缘层52的氢含量，并对所述第二沟道进行氢活化，之后，在所述第一栅极绝缘层50背离所述衬底10的一侧形成所述第一薄膜晶体管20的第一有源层21，所述第一有源层21包括第一沟道211和位于所述第一沟道211两侧的未经导体化处理的第一源极欧姆接触部和第一漏极欧姆接触部。
图6e为本申请实施例提供的显示面板的制备方法中与步骤S05对应的显示面板的结构示意图。参照图6e所示，步骤S05包括：在所述第一沟道211背离所述衬底10的一侧形成隔离层，所述隔离层与所述第一子绝缘层51的材质相同，例如为氧化硅，之后，通过曝光显影和刻蚀处理，将所述隔离层处理形成为与所述第一沟道211对应设置的隔离部22，所述隔离部22的厚度为50-250nm，所述隔离部22的侧壁221与所述隔离部22的底面222所呈的夹角为a，30°≤a≤90°，所述隔离部22背离所述第一沟道211的一侧形成有光阻，之后，以所述隔离部22和所述光阻为掩膜版，对暴露的未经导体化处理的第一源极欧姆接触部和第一漏极欧姆接触部进行导体化处理，导体化处理工艺包括硼离子掺杂或氩等离子处理，从而形成第一源极欧姆接触部213和第一漏极欧姆接触部212，之后，剥离所述光阻。
图6f为本申请实施例提供的显示面板的制备方法中与步骤S06对应的显示面板的结构示意图。参照图6f所示，步骤S06包括：在所述隔离部22背离所述衬底10的一侧形成透明导电层，对所述透明导电层进行图案化，形成第一源极24和第一漏极23，所述第一源极24覆盖所述第一源极欧姆接触部213，且所述第一源极24的边缘超出所述第一源极欧姆接触部213的边缘0.5-1微米；所述第一漏极23包括第一部分231和第二部分232，所述第一漏极23的第二部分232覆盖所述第一漏极欧姆接触部212，且所述第二部分232的边缘超出所述第一漏极欧姆接触部212的边缘的距离为0.5-1微米，所述隔离部22的边缘223凸出于所述第一漏极23的第一部分231的边缘2311的距离为1-2微米。
图6g为本申请实施例提供的显示面板的制备方法中与步骤S07对应的显示面板的结构示意图。参照图6g所示，步骤S07包括：在所述透明导电层背离所述衬底10的一侧形成层间介质层110，所述层间介质层110为氮化硅膜层、氧化硅膜层或氮化硅膜层和氧化硅膜层的叠层，并对所述层间介质层110进行开孔处理，形成暴露所述第二源极区、所述第二漏极区和所述第一源极24的多个开孔，其中，暴露所述第一源极24的开孔为第二过孔80。
图6h为本申请实施例提供的显示面板的制备方法中与步骤S08对应的显示面板的结构示意图。参照图6h所示，步骤S08包括：在所述层间介质层110背离所述衬底10的一侧形成源漏极金属层，所述源漏极金属层可以为Ti、Al、Mo或其合金及叠层，并对所述源漏极金属层进行图案化，形成第二源极63、第二漏极64和第一源极导接部70，所述第二源极63通过暴露所述第二源极区的开孔与所述第二源极区电性连接，所述第二漏极64通过暴露所述第二漏极区的开孔与所述第二漏极区电性连接，所述第一源极导接部70通过暴露所述第一源极24的开孔（第二过孔80）与所述第一源极24电性连接。
图6i为本申请实施例提供的显示面板的制备方法中与步骤S09对应的显示面板的结构示意图。参照图6i所示，步骤S09包括：利用涂布曝光显影工艺，在所述第二源极63、第二漏极64、第一源极导接部70背离所述衬底10的一侧形成图案化的、包括与所述第一部分231相对应的过孔的第一平坦层120，之后，以所述第一平坦层120为掩膜版，对所述层间介质层110进行刻蚀，在层间介质层110对应所述第一部分231的位置形成贯穿所述层间介质层110的过孔，贯穿所述层间介质层110的过孔与第一平坦层120中的所述过孔共同组成第一过孔40。当然，也可以通过在所述第一平坦层120上形成光阻掩膜板的方式，经过一次蚀刻形成贯穿所述第一平坦层120和所述层间介质层110的所述第一过孔40。
图6j为本申请实施例提供的显示面板的制备方法中与步骤S10对应的显示面板的结构示意图。参照图6j所示，步骤S10包括：在所述第一平坦层120背离所述衬底10的一侧形成像素电极30，所述像素电极30通过所述第一过孔40与所述第一漏极23的所述第一部分231电性连接。
图6k为本申请实施例提供的显示面板的制备方法中与步骤S11对应的显示面板的结构示意图。参照图6k所示，步骤S11包括：在所述像素电极30背离所述衬底10的一侧依次形成钝化层130、公共电极150和第二平坦层140，所述第二平坦层140填充所述像素电极30在所述第一过孔40处形成的凹槽。
综上所述，本申请提供一种显示面板，所述显示面板具有显示区，所述显示面板包括：衬底；第一薄膜晶体管，设置在所述衬底的一侧，并位于所述显示区；像素电极，设置在所述第一薄膜晶体管背离所述衬底的一侧，并位于所述显示区；所述第一薄膜晶体管包括第一有源层、隔离部和第一漏极，其中，所述第一有源层包括第一沟道和设置在所述第一沟道的一侧的第一漏极欧姆接触部；所述隔离部设置在所述第一沟道背离所述衬底的一侧的表面上，并覆盖所述第一沟道；所述第一漏极包括透明的第一部分和透明的第二部分，所述第一部分设置在所述隔离部背离所述第一有源层的一侧的表面上，所述第二部分设置在所述第一漏极欧姆接触部背离所述衬底的一侧的表面上；其中，所述像素电极通过设置在所述第一部分背离所述隔离部的一侧的第一过孔与所述第一部分电性连接。本申请提供的显示面板能够在实现高开口率的同时，提高显示面板的显示画质，降低显示面板的生产制造成本。
以上对本申请实施例所提供的一种显示面板进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (20)

  1. 一种显示面板，其中，所述显示面板具有显示区，所述显示面板包括：
    衬底；
    第一薄膜晶体管，设置在所述衬底的一侧，并位于所述显示区；
    像素电极，设置在所述第一薄膜晶体管背离所述衬底的一侧，并位于所述显示区；
    其中，所述第一薄膜晶体管包括：
    第一有源层，包括第一沟道和设置在所述第一沟道的一侧的第一漏极欧姆接触部；
    隔离部，设置在所述第一沟道背离所述衬底的一侧的表面上，并覆盖所述第一沟道；
    第一漏极，包括透明的第一部分和透明的第二部分，所述第一部分设置在所述隔离部背离所述第一有源层的一侧的表面上，所述第二部分设置在所述第一漏极欧姆接触部背离所述衬底的一侧的表面上；
    其中，所述像素电极通过设置在所述第一部分背离所述隔离部的一侧的第一过孔与所述第一部分电性连接。
  2. 根据权利要求1所述的显示面板，其中，所述第二部分覆盖所述第一漏极欧姆接触部。
  3. 根据权利要求2所述的显示面板，其中，所述第二部分覆盖所述隔离部的侧壁，且所述隔离部的侧壁与所述隔离部的底面所呈的夹角为a，30°≤a≤90°。
  4. 根据权利要求2所述的显示面板，其中，在所述隔离部远离所述第二部分的方向上，所述隔离部的边缘凸出于所述第一部分的边缘。
  5. 根据权利要求4所述的显示面板，其中，所述第一有源层还包括设置在所述第一沟道的另一侧的第一源极欧姆接触部，
    其中，所述第一薄膜晶体管还包括与所述第一漏极一体形成的第一源极，所述第一源极设置在所述第一源极欧姆接触部背离所述衬底的一侧的表面上，并覆盖所述第一源极欧姆接触部。
  6. 根据权利要求5所述的显示面板，其中，所述显示面板还包括第一栅极绝缘层，所述第一栅极绝缘层设置在所述第一有源层背离所述隔离部的一侧，其中，所述第一栅极绝缘层包括第一子绝缘层，所述第一子绝缘层与所述第一有源层相接触，且所述第一子绝缘层与所述隔离部的材质相同。
  7. 根据权利要求6所述的显示面板，其中，所述显示面板还包括第二薄膜晶体管，所述第二薄膜晶体管设置在所述衬底朝向所述第一薄膜晶体管的一侧，
    其中，所述第二薄膜晶体管包括第二有源层，所述第二有源层设置在所述第一有源层背离所述隔离部的一侧，所述第二有源层包括第二沟道，所述第二沟道的材质与所述第一沟道的材质不同。
  8. 根据权利要求7所述的显示面板，其中，所述第一栅极绝缘层还包括第二子绝缘层，所述第二子绝缘层设置在所述第一子绝缘层背离所述第一有源层的一侧，且所述第二子绝缘层与所述第一子绝缘层的材质不同；
    所述第一薄膜晶体管包括第一栅极，所述第一栅极设置在所述第二子绝缘层背离所述第一子绝缘层的一侧；所述第二薄膜晶体管还包括第二栅极，所述第二栅极设置在所述第二有源层背离所述衬底的一侧；
    其中，所述第一栅极与所述第二栅极同层设置，且所述第一栅极、所述第二栅极分别与所述第二子绝缘层相接触。
  9. 根据权利要求8所述的显示面板，其中，所述显示面板还包括第二栅极绝缘层，所述第二栅极绝缘层设置在所述第二有源层朝向所述第二栅极的一侧，其中，设置在所述第一有源层和所述第一栅极之间的所述第一栅极绝缘层具有第一厚度，设置在所述第二有源层和所述第二栅极之间的所述第二栅极绝缘层具有第二厚度，且所述第一厚度与所述第二厚度的比值小于或等于3。
  10. 根据权利要求7所述的显示面板，其中，第二薄膜晶体管还包括第二源极和第二漏极，所述显示面板还包括第一源极导接部，所述第一源极导接部与所述第二源极和所述第二漏极同层设置，所述第一源极导接部通过第二过孔与所述第一源极电性连接。
  11. 根据权利要求1所述的显示面板，其中，所述第一过孔在所述第一有源层上的垂直投影与所述第一沟道相重叠。
  12. 根据权利要求11所述的显示面板，其中，所述第二部分覆盖所述第一漏极欧姆接触部。
  13. 根据权利要求12所述的显示面板，其中，所述第二部分覆盖所述隔离部的侧壁，且所述隔离部的侧壁与所述隔离部的底面所呈的夹角为a，30°≤a≤90°。
  14. 根据权利要求12所述的显示面板，其中，在所述隔离部远离所述第二部分的方向上，所述隔离部的边缘凸出于所述第一部分的边缘。
  15. 根据权利要求14所述的显示面板，其中，所述第一有源层还包括设置在所述第一沟道的另一侧的第一源极欧姆接触部，
    其中，所述第一薄膜晶体管还包括与所述第一漏极一体形成的第一源极，所述第一源极设置在所述第一源极欧姆接触部背离所述衬底的一侧的表面上，并覆盖所述第一源极欧姆接触部。
  16. 根据权利要求15所述的显示面板，其中，所述显示面板还包括第一栅极绝缘层，所述第一栅极绝缘层设置在所述第一有源层背离所述隔离部的一侧，其中，所述第一栅极绝缘层包括第一子绝缘层，所述第一子绝缘层与所述第一有源层相接触，且所述第一子绝缘层与所述隔离部的材质相同。
  17. 根据权利要求16所述的显示面板，其中，所述显示面板还包括第二薄膜晶体管，所述第二薄膜晶体管设置在所述衬底朝向所述第一薄膜晶体管的一侧，
    其中，所述第二薄膜晶体管包括第二有源层，所述第二有源层设置在所述第一有源层背离所述隔离部的一侧，所述第二有源层包括第二沟道，所述第二沟道的材质与所述第一沟道的材质不同。
  18. 根据权利要求17所述的显示面板，其中，所述第一栅极绝缘层还包括第二子绝缘层，所述第二子绝缘层设置在所述第一子绝缘层背离所述第一有源层的一侧，且所述第二子绝缘层与所述第一子绝缘层的材质不同；
    所述第一薄膜晶体管包括第一栅极，所述第一栅极设置在所述第二子绝缘层背离所述第一子绝缘层的一侧；所述第二薄膜晶体管还包括第二栅极，所述第二栅极设置在所述第二有源层背离所述衬底的一侧；
    其中，所述第一栅极与所述第二栅极同层设置，且所述第一栅极、所述第二栅极分别与所述第二子绝缘层相接触。
  19. 根据权利要求18所述的显示面板，其中，所述显示面板还包括第二栅极绝缘层，所述第二栅极绝缘层设置在所述第二有源层朝向所述第二栅极的一侧，其中，设置在所述第一有源层和所述第一栅极之间的所述第一栅极绝缘层具有第一厚度，设置在所述第二有源层和所述第二栅极之间的所述第二栅极绝缘层具有第二厚度，且所述第一厚度与所述第二厚度的比值小于或等于3。
  20. 根据权利要求17所述的显示面板，其中，第二薄膜晶体管还包括第二源极和第二漏极，所述显示面板还包括第一源极导接部，所述第一源极导接部与所述第二源极和所述第二漏极同层设置，所述第一源极导接部通过第二过孔与所述第一源极电性连接。
PCT/CN2023/138412 2023-12-01 2023-12-13 一种显示面板 Pending WO2025112112A1 (zh)

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CN113594223A (zh) * 2021-07-30 2021-11-02 Tcl华星光电技术有限公司 有机发光显示装置及制作方法
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CN114883345A (zh) * 2022-05-06 2022-08-09 深圳市华星光电半导体显示技术有限公司 驱动背板及其制备方法、显示面板
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