WO2025033507A1 - 蒸着マスク及び、電子デバイスの製造方法 - Google Patents

蒸着マスク及び、電子デバイスの製造方法 Download PDF

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Publication number
WO2025033507A1
WO2025033507A1 PCT/JP2024/028528 JP2024028528W WO2025033507A1 WO 2025033507 A1 WO2025033507 A1 WO 2025033507A1 JP 2024028528 W JP2024028528 W JP 2024028528W WO 2025033507 A1 WO2025033507 A1 WO 2025033507A1
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Prior art keywords
deposition
deposition mask
opening
less
unevenness
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PCT/JP2024/028528
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English (en)
French (fr)
Japanese (ja)
Inventor
公栄 大塚
数馬 碓氷
浩之 道
涼真 茂木
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Toppan Holdings Inc
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Toppan Holdings Inc
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Priority to JP2024573594A priority Critical patent/JP7708338B2/ja
Priority to KR1020257020407A priority patent/KR20250111176A/ko
Priority to CN202480037903.9A priority patent/CN121263549A/zh
Publication of WO2025033507A1 publication Critical patent/WO2025033507A1/ja
Priority to JP2025112684A priority patent/JP2025129318A/ja
Priority to JP2025179711A priority patent/JP2026002996A/ja
Anticipated expiration legal-status Critical
Pending legal-status Critical Current

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    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • C23C14/042—Coating on selected surface areas, e.g. using masks using masks
    • C—CHEMISTRY; METALLURGY
    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/04—Coating on selected surface areas, e.g. using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/10—Deposition of organic active material
    • H10K71/16—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering
    • H10K71/166—Deposition of organic active material using physical vapour deposition [PVD], e.g. vacuum deposition or sputtering using selective deposition, e.g. using a mask

Definitions

  • the present invention relates to a deposition mask and a method for manufacturing an electronic device.
  • Patent Documents 1 and 2 describe that the sidewall surface of each opening of the deposition mask has an uneven shape. In addition, the surface roughness of the unevenness is specified.
  • the uneven shape of the sidewall of the opening causes deposition material to accumulate on the sidewall, resulting in a deterioration in the pattern dimensions of the deposited film.
  • the present invention aims to provide a deposition mask capable of depositing a deposition film with excellent pattern dimensions, and a method for manufacturing an electronic device using the deposition mask.
  • the deposition mask of this embodiment has a first surface and a second surface opposite to the first surface, and is formed with a plurality of openings penetrating between the first surface and the second surface, and is characterized in that the sidewall surface of the opening is formed with an uneven shape, the opening width is 30 ⁇ m or less, and the unevenness ratio (average unevenness height difference/opening width) R is 0.0001 or more and 0.0420 or less.
  • the present invention by controlling the size of the unevenness formed on the sidewall surface of the opening of the deposition mask in terms of the ratio to the opening width, a deposition film having excellent pattern dimensions can be stably formed.
  • the frequency of cleaning the deposition mask can be reduced, making it easier to control the quality of the deposition mask.
  • the occurrence of clogging of the openings can be reduced, and the life of the deposition mask can be extended.
  • FIG. 2 is a cross-sectional view showing an example of a deposition mask according to the present embodiment.
  • 2 is an enlarged cross-sectional view showing a part of the deposition mask shown in FIG. 1 .
  • 4 is a partially enlarged cross-sectional view showing an enlarged portion of an opening of the deposition mask of the present embodiment.
  • FIG. 1A to 1C are cross-sectional views showing a method for manufacturing an electronic device using the deposition mask of the present embodiment.
  • 1A to 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • 1A to 1C are process diagrams illustrating an example of a method for manufacturing a deposition mask according to an embodiment of the present invention.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • FIG. 11 is a cross-sectional view illustrating an example of a deposition mask according to another embodiment.
  • 1 is an image diagram showing a state in which a deposition material is deposited on a side wall surface of an opening.
  • VR/AR Virtual reality/augmented reality
  • PPI Pixels Per Inch
  • OLED silicon-based organic light-emitting diode
  • Silicon-based OLED microdisplay technology is expected to achieve further miniaturization and high PPI. Furthermore, to effectively prepare for AR and VR as high-value-added industries, it is expected to realize ultra-high resolution displays of, for example, 1000 ppi or more. As a result, there is a growing need for deposition masks for RGB color separation used in the manufacturing process of OLED microdisplays.
  • the deposition mask has multiple openings that correspond to the deposited film, and the accuracy of the openings in the deposition mask is important for improving the pattern dimensions of the deposited film.
  • the deposition mask is placed between the substrate and the deposition source, and the deposition material travels from the deposition source through the openings in the deposition mask to reach the surface of the substrate. If the deposition material accumulates on the sidewall of the opening, the opening width becomes narrower than the actual width, making it difficult to form a deposition film with excellent pattern dimensions.
  • Patent Document 1 aims to form an opening that stabilizes the deposition of deposition material, addressing the problem of deposition material depositing on the sidewall surface becoming foreign matter and dropping off, resulting in pixel defects.
  • Patent Document 1 specifies the opening width to be 100 ⁇ m (0.1 mm) or more.
  • the opening width is made smaller than 100 ⁇ m (specifically, 30 ⁇ m or less), assuming that the size of the unevenness on the sidewall surface of the opening is constant, the smaller the opening width, the greater the effect of deposition material accumulation, and the lower the pattern dimensions of the deposited film. For this reason, excellent pattern dimensions cannot be obtained simply by adjusting the size of the unevenness, and it was necessary to determine the range in which a deposited film with excellent pattern dimensions could be formed, taking into account the relationship with the opening width.
  • the inventors focused on the ratio of the height difference between the projections and recesses on the sidewall surface to the opening width, and developed a deposition mask that can increase the pattern dimensions of the deposited film.
  • Fig. 1 is a cross-sectional view of a deposition mask 1 in the present embodiment.
  • Fig. 2 is a cross-sectional view showing an enlarged portion of the deposition mask shown in Fig. 1.
  • Fig. 3 is a partially enlarged cross-sectional view showing an enlarged portion of an opening of the deposition mask in the present embodiment.
  • Fig. 4 is a cross-sectional view showing a method for manufacturing an electronic device using the deposition mask in the present embodiment.
  • the deposition mask 1 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4, and is preferably constructed from an SOI (Silicon on Insulator) substrate 9.
  • SOI Silicon on Insulator
  • the semiconductor layer 2 is preferably a silicon single crystal layer, and is also called an active layer or membrane. There is no limitation on the thickness of the semiconductor layer 2, but it is about 1 ⁇ m to 300 ⁇ m.
  • the deposition mask 1 has multiple opening regions 15 and surrounding regions 16 located around the opening regions 15, and the surrounding regions 16 have a structure in which a semiconductor layer 2, an insulating layer 3, and a support substrate 4 are stacked.
  • the semiconductor layer 2 is disposed in the opening regions 15, that is, the insulating layer 3 and the support substrate 4 have been removed, and furthermore, multiple minute openings 5 are formed in each opening region 15.
  • FIG. 2 is an enlarged view of one of the opening regions 15 shown in FIG. 2, the semiconductor layer 2 has a first surface 2a and a second surface 2b that face each other in the thickness direction.
  • An insulating layer 3 and a support substrate 4 are provided on the second surface 2b side.
  • the first surface 2 a is a front surface facing a deposition target substrate 10
  • the second surface 2 b is a rear surface facing a deposition source 11 .
  • the semiconductor layer 2 has a plurality of openings 5 formed between the first surface 2a and the second surface 2b.
  • the opening width of each opening 5 gradually narrows from the second surface 2b to the first surface 2a.
  • the sidewall surface 6 of the opening 5 is inclined.
  • the opening width W1 is defined by the width dimension in the planar direction along the first surface 2a.
  • the opening width W1 is illustrated at the point where the width dimension is the narrowest.
  • the reference numerals for the opening width W1 and the sidewall surface 6 are illustrated for only one opening 5, but they apply to the other openings 5 in the same way. Note that the shape of the sidewall surface 6 of the opening 5 will be described in detail later.
  • the planar pattern of the openings 5 (the shape seen from directly above the semiconductor layer 2 toward the first surface 2a) is not limited, and examples thereof include a rectangle (including a square), a polygon other than a rectangle, a circle, and an ellipse. All the openings 5 may have the same planar pattern, or some of them may be different.
  • the openings 5 may be regularly arranged, irregularly arranged, or a mixture of regular and irregular arrangements. Although there are no limitations on the distance between adjacent openings 5, the distance is about 1 ⁇ m to 20 ⁇ m when viewed from the first surface 2a side.
  • the outer peripheral shape of the semiconductor layer 2 is preferably a rectangular or disk-shaped wafer, and although there are no limitations on the diameter (the length of one side if rectangular), it is preferable for it to be approximately 100 mm to 500 mm. In this way, even if the diameter of the semiconductor layer 2 is large, each opening 5 can be formed uniformly.
  • the insulating layer 3 may be an oxide layer or a nitride layer, but is preferably an oxide layer, and more specifically, is preferably a silicon oxide (SiO 2 ) layer.
  • the insulating layer 3 is also called a BOX layer (Buried Oxide Layer).
  • the thickness of the insulating layer 3 is not limited, but is, for example, about 100 nm to 20 ⁇ m.
  • the support substrate 4 can function as the pillars 16a and the peripheral frame 16b surrounding the peripheral region 16 of the opening region 15 on the second surface 2b of the semiconductor layer 2. Therefore, the semiconductor layer 2 can be kept in a taut state by the support substrate 4, making tensioning unnecessary, and the deposition mask 1 of this embodiment can be attached to the deposition substrate 10 using an electrostatic chuck that utilizes electrostatic force.
  • the pillars 16a are located inside the peripheral frame 16b, and they all have the same length (height), but for example, the height of the pillars 16a may be lower than the peripheral frame. However, by making the heights uniform, strength can be maintained.
  • ⁇ Detailed Description of the Openings 5 of the Deposition Mask 1 in the Present Embodiment> 3 is a partially enlarged cross-sectional view showing one opening 5 formed in the deposition mask 1, and shows an extracted intermediate portion in the height direction (thickness direction of the semiconductor layer 2) of the opening 5. Note that, although reference numerals are mainly attached only to the side wall surface 6 of the opening 5 on the left side in the figure, the cross-sectional shape is symmetrical, and the side wall surface 6 on the right side in the figure has the same configuration.
  • the side wall surface 6 of the opening 5 is formed in an uneven shape. That is, on the side wall surface 6, a plurality of convex portions 7 protruding inwardly of the opening 5 and concave portions 8 located between the convex portions 7 are repeatedly formed continuously along the height direction of the opening 5.
  • the unevenness height difference and the like of the opening 5 are calculated as follows.
  • the pitch concept described above it is also possible to measure the height at, for example, five points in the center of the thickness using an SEM image.
  • the points with height can be regarded as convex portions, and the areas between them as concave portions.
  • an approximate straight line T1 was drawn connecting the lowest positions (bottom A) of each recess 8a, 8b within the measurement range.
  • Bottom A is, for example, the farthest position when viewed from the center line O in the width direction of the opening 5.
  • the approximate straight line T1 can be found using the least squares method. Note that if an irregular recess 8 is formed within the measurement range (for example, bottom A is extremely lower than top B), the approximate straight line T1 can be drawn excluding that recess 8.
  • the highest position (apex) B of the convex portion 7a was determined in the first half pitch P1.
  • the apex B is the closest position when viewed from the center line O in the width direction of the opening 5.
  • a straight line S1 was drawn perpendicular to the approximated straight line T1 so as to intersect with the apex B.
  • the length of the straight line S1 from the approximated straight line T1 to the apex B was determined.
  • the length of this straight line S1 was defined as the unevenness height difference D1 in the first half pitch P1.
  • the unevenness height difference can be calculated in the same way as for the first half pitch P1. That is, the length of a straight line perpendicular to the approximate straight line T1 to the top B of each convex portion is calculated, and this straight line length is used as the unevenness height difference for each pitch.
  • Figure 3 shows the unevenness height difference D2 for the second half pitch P2.
  • fine irregularities may be formed on the surface of each recess 8a, 8b (or the bottom of the protruding portions 7a, 7b), but these fine irregularities can be ignored. For example, fine irregularities on the order of a few nm in wavelength or smaller can be cut off, and a waviness curve can be created to determine the difference in unevenness height.
  • the opening width W1 As shown in Fig. 2, the opening 5 gradually narrows from the second surface 2b toward the first surface 2a, and the opening width varies depending on the measurement location. For this reason, as shown in Fig. 2, the opening width W1 was obtained as the dimension in the planar direction along the first surface 2a where the opening width is narrowest.
  • the opening width W1 can be determined from an SEM image obtained using eCD-2 manufactured by KLA-Tencor.
  • the unevenness ratio R was calculated from the average value Ave of the unevenness height difference Dn and the opening width W1 measured above. That is, the unevenness ratio R was calculated by (average value Ave of the unevenness height difference Dn/opening width W1).
  • a small unevenness ratio R means that if the average value Ave of the unevenness height difference Dn is constant, the opening width W1 is large, or if the opening width W1 is constant, the average value Ave of the unevenness height difference Dn is small.
  • a large unevenness ratio R means that if the average value Ave of the unevenness height difference Dn is constant, the opening width W1 is small, or if the opening width W1 is constant, the average value Ave of the unevenness height difference Dn is large. In this way, in this embodiment, the average value Ave of the unevenness height difference Dn and the opening width W1 can be adjusted, or both, to control the unevenness ratio R to fall within a predetermined range.
  • the taper angle ⁇ 1 of the opening 5 is determined as follows. That is, as shown in Fig. 2, a straight line is connected between an end of the opening width W1 in the surface direction along the first surface 2a and an end of the opening width W2 in the surface direction along the second surface 2b, and the inclination angle between the straight line and the first surface 2a can be set as the taper angle ⁇ 1 of the opening 5.
  • the taper angle ⁇ 1 was determined by measuring the length of an SEM image obtained using a Hitachi High-Technologies Regulus 8220.
  • the inclination angle ⁇ 4 of the side wall surface 6 can be determined from the inclination angle between the approximate straight line T1 shown in FIG. 3 and the first surface 2a.
  • the taper angle ⁇ 1 and the inclination angle ⁇ 4 are the same or approximate, but depending on, for example, the state of the uneven shape of the side wall surface 6 and the pitch, the inclination of the approximate straight line T1 may change, and the taper angle ⁇ 1 and the inclination angle ⁇ 4 may deviate from each other. Therefore, the inclination of the side wall surface 6 is determined by measuring the taper angle ⁇ 1 of the opening 5.
  • the unevenness angle ⁇ 2 can be determined as the angle between a straight line L1 connecting the top B of the convex portion 7a and the lowest (farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8a located on the deposition substrate 10 side (upper side in the figure) as viewed from the convex portion 7a, and an approximated straight line T1. Also, as shown in Fig. 3, the unevenness angle ⁇ 2 can be determined as the angle between a straight line L1 connecting the top B of the convex portion 7a and the lowest (farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8a located on the deposition substrate 10 side (upper side in the figure) as viewed from the convex portion 7a, and an approximated straight line T1. Also, as shown in Fig.
  • the unevenness angle ⁇ 3 can be determined as the angle between a straight line L2 connecting the top B of the convex portion 7a and the lowest (farthest from the center line O in the width direction of the opening 5) bottom A of the concave portion 8b located on the deposition source 11 side (lower side in the figure, see Fig. 4) as viewed from the convex portion 7a, and an approximated straight line T1.
  • a small concave-convex angle ⁇ 2, ⁇ 3 means that the height of the convex portion 7 is low (the depth of the concave portion 8 is shallow) and the waviness of the side wall surface 6 is small.
  • the deposition mask 1 in this embodiment is (1)
  • the opening width W1 is 30 ⁇ m or less;
  • the unevenness ratio R average value Ave of unevenness height difference Dn/opening width W1 is 0.0001 or more and 0.0420 or less.
  • the opening width W1 is in the range of 30 ⁇ m or less. This satisfies the needs of the deposition mask 1 having the semiconductor layer 2, and in particular, it is necessary to make the opening width W1 even smaller as a deposition mask for RGB color separation used in the manufacturing process of OLED microdisplays.
  • the opening width W1 is preferably 20 ⁇ m or less, and more preferably 10 ⁇ m or less.
  • the opening width W1 is preferably 1 ⁇ m or more, more preferably 2 ⁇ m or more, and even more preferably 3 ⁇ m or more.
  • the opening width W1 is preferably 1 ⁇ m or more and 30 ⁇ m or less, more preferably 2 ⁇ m or more and 20 ⁇ m or less, and even more preferably 3 ⁇ m or more and 10 ⁇ m or less.
  • the opening width W1 is preferably set as the width dimension in the planar direction along the first surface 2a that faces the deposition substrate 10.
  • the concave-convex ratio R is set to 0.0001 or more and 0.0420 or less. By adjusting the concave-convex ratio R within this range, it is possible to make the pattern width of the deposition film formed using the deposition mask 1 80% or more of the opening width W1 of the deposition mask 1.
  • FIG. 4 is a cross-sectional view of the deposition mask 1 of this embodiment, positioned between a deposition substrate 10 and a deposition source 11, showing one step in the method for manufacturing an electronic device.
  • the deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 of the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, where a deposition film 13 is formed.
  • the pattern width W3 of the deposition film 13 is measured and the ratio to the opening width W1 is calculated, if the unevenness ratio R is such that the pattern width ratio ((pattern width W3/opening width W1) ⁇ 100(%)) is 80% or more, this is the present embodiment, and an unevenness ratio R of less than 80% is a comparative example.
  • the lower limit of the unevenness ratio R, 0.0001 is almost the manufacturing limit, and therefore it is set to 0.0001 or more. It is also known that when the upper limit of the unevenness ratio R, 0.0420, is exceeded, the unevenness ratio R to the opening width W1 increases exponentially. In particular, when the unevenness ratio R exceeds 0.0425, the exponential increase becomes significant, and the effect on deposition becomes rapidly large. That is, for example, even if the average value Ave of the unevenness height difference Dn is the same, in the range where the unevenness ratio R exceeds 0.0420, even if the opening width W1 is shifted slightly in the direction of decreasing, the unevenness ratio R fluctuates in the direction of increasing significantly, and the pattern width ratio of the deposition film 13 deteriorates.
  • the unevenness ratio R is set to 0.0420 or less so that a pattern width ratio of 80% or more can be stably obtained.
  • the reason why the required pattern width ratio is set to 80% or more is that if it is less than 80%, the deviation from the desired pattern width W3 of the deposition film 13 will be too large, leading to a decrease in yield, and also because it will lead to a decrease in the area that should emit light at the designed position, such as coordinate position accuracy, leading to a decrease in the brightness of the light-emitting element itself, or because it is a value required for product quality assurance.
  • the pattern width ratio is set to 85% or more, preferably 90% or more, and more preferably 95% or more.
  • the concave-convex ratio R is preferably 0.0380 or less, more preferably 0.0350 or less, and even more preferably 0.0300 or less.
  • the lower limit of the unevenness ratio R can be set to approximately 0.0003 or 0.0005.
  • the unevenness ratio R can be set to 0.0015 or more, or 0.0020 or more.
  • the average value Ave of the unevenness height difference Dn is preferably 0.200 ⁇ m or less, more preferably 0.180 ⁇ m or less, even more preferably 0.175 or less, and most preferably 0.170 ⁇ m or less.
  • the average value Ave of the unevenness height difference Dn is preferably 0.003 ⁇ m or more, more preferably 0.005 ⁇ m or more, and even more preferably 0.008 ⁇ m or more.
  • the maximum value of the unevenness height difference Dn is preferably 0.500 ⁇ m or less, more preferably 0.450 ⁇ m or less, even more preferably 0.400 ⁇ m or less, even more preferably 0.350 ⁇ m or less, and most preferably 0.300 ⁇ m or less.
  • the maximum value of the unevenness height difference Dn is preferably 0.300 ⁇ m or less, more preferably 0.250 ⁇ m or less, even more preferably 0.200 ⁇ m or less, and most preferably 0.100 ⁇ m or less.
  • the maximum value of the unevenness height difference Dn is about 0.005 ⁇ m or more.
  • the unevenness angles ⁇ 2 and ⁇ 3 described in FIG. 3 are within the range of about 0.5° to 50°, and are preferably 45° or less, more preferably 40° or less, even more preferably 30° or less, even more preferably 20° or less, and even more preferably 10° or less.
  • the most preferable range of the unevenness angles ⁇ 2 and ⁇ 3 is about 0.5° to 2°.
  • the unevenness angle ⁇ 3 shown in FIG. 3 is preferably smaller than the unevenness angle ⁇ 2. This makes it possible to prevent the deposition material 12 from depositing on the side wall surface 6.
  • the opening width of the opening 5 gradually narrows from the second surface 2b side toward the first surface 2a side. That is, as shown in FIG. 4, the opening width W1 on the side facing the deposition substrate 10 in the deposition mask 1 is narrow, and the side wall surface 6 of the opening 5 is formed by an inclined surface. This makes it easier to stably form the deposition film 13 having the desired pattern width W3.
  • the side wall surface 6 of the opening 5 is inclined, making it easier to form the side wall surface 6.
  • the taper angle ⁇ 1 of the opening 5 is preferably 60° or more, more preferably 70° or more.
  • the taper angle ⁇ 1 is preferably smaller than 90°, more preferably 85° or less, and even more preferably 80° or less. Therefore, the taper angle ⁇ 1 is most preferably 70° or more and 80° or less. If the taper angle ⁇ 1 is less than 60°, the amount of deposition material 12 deposited on the sidewall surface 6 increases, and the pattern width ratio of the deposition film tends to be smaller than 80%.
  • the taper angle ⁇ 1 can be set to about 90°, i.e., the sidewall surface 6 can be formed almost vertically.
  • the influence of the unevenness height difference Dn of the sidewall surface 6 during deposition is considered to be large, and it is necessary to make the average value Ave and maximum value of the unevenness height difference Dn as small as possible, especially as the opening width W1 becomes narrower.
  • the taper angle ⁇ 1 is controlled to be smaller than 90°, preferably 85° or less, more preferably 80° or less.
  • 5A and 5B are process diagrams showing a first manufacturing method of the deposition mask 1 of the present embodiment.
  • the deposition mask 1 in the manufacturing process shown in FIG. 5 and FIG. 6 described later shows only one opening region 15 and its vicinity, as in FIG. 2, but actually, the multiple opening regions 15 shown in FIG. 1 are formed simultaneously.
  • FIG. 5A an SOI substrate 9 is prepared.
  • the SOI substrate 9 has a laminated structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4. The materials and thicknesses of each layer have been explained in FIG. 1, so please refer to that.
  • the diameter is not limited, but in this embodiment, it can accommodate up to about 500 mm.
  • a mask layer 14 is patterned on the surface of the semiconductor layer 2.
  • the mask layer 14 is preferably a resist, and can be patterned by exposure and development.
  • a plurality of through holes 14a are formed in the mask layer 14. These through holes 14a are an opening pattern for forming the openings 5 in the semiconductor layer 2, and the width dimension W4 of the through holes 14a is formed to be small, less than or equal to 30 ⁇ m.
  • the semiconductor layer 2 exposed from the through hole 14a of the mask layer 14 is dry etched.
  • the semiconductor layer 2 is deep etched. It is preferable to use a method in which, for example, etching of Si with SF6 and generation of a polymer film with C4F8 are repeated to deeply dig silicon, and sidewall protection and bottom etching proceed alternately, by the so-called Bosch process.
  • Bosch process the sidewall surface 6 of the opening 5 formed in the semiconductor layer 2 has an uneven shape.
  • the composition of the etching gas, the flow rate, the pressure inside the etching chamber, the power of the high frequency power source, etc. are appropriately adjusted so as to form an inverse tapered surface. Furthermore, by adjusting these, it is possible to control the inclination angle of the inverse tapered surface (taper angle ⁇ 1 of opening 5) and the unevenness height difference Dn.
  • the Bosch process was carried out in a dry etching apparatus by alternately using SF6 gas and C4F8 gas.
  • Anisotropic dry etching using fluorine ions was carried out by applying a bias to the substrate to be etched using the same gas as that used in the mode in which isotropic dry etching using fluorine radicals was carried out using SF6 gas.
  • the processing conditions were SF6 gas at 0 to 500 sccm, C4F8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • multiple openings 5 can be deeply formed in the semiconductor layer 2, and the taper angle ⁇ 1 and height difference between the protrusions and recesses of the openings 5 can be adjusted appropriately.
  • the mask layer 14 is removed, thereby completing the SOI substrate 9 having the plurality of openings 5 formed in the semiconductor layer 2.
  • a protective layer 20 is formed on the surface of the semiconductor layer 2. This allows the entire surface of the semiconductor layer 2 to be appropriately protected.
  • the protective layer 20 is, for example, a resist film.
  • a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9.
  • the mask layer 21 is a resist pattern.
  • the mask layer 21 is not formed in the opening region 15 that faces the opening 5 formed in the semiconductor layer 2 in the thickness direction, but is provided only in the surrounding region 16 (see also FIG. 1).
  • the mask layer 21 may be formed together with the mask layer 14 during the process shown in FIG. 5(b).
  • the support substrate 4 that is not covered with the mask layer 21 is removed by dry etching, and in the step shown in Fig. 4(h), the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching. At this time, the semiconductor layer 2 is not affected by the wet etching and maintains the shape having the multiple openings 5. 5I, the protective layer 20 and the mask layer 21 are removed, thereby completing the deposition mask 1.
  • FIG. 6 is a process diagram showing a second manufacturing method of the deposition mask 1 of this embodiment.
  • an SOI substrate 9 is prepared.
  • the SOI substrate 9 has a layered structure of a semiconductor layer 2, an insulating layer 3, and a support substrate 4.
  • the materials and thicknesses of each layer are explained in FIG. 1, so please refer to that.
  • the diameter of the SOI substrate 9 there is no limit to the diameter of the SOI substrate 9, but in this embodiment, it can accommodate a diameter of up to approximately 500 mm.
  • a mask layer 21 is formed on the surface of the support substrate 4, which corresponds to the back surface of the SOI substrate 9.
  • the mask layer 21 is a resist pattern.
  • the mask layer 21 is provided only in the peripheral region of the SOI substrate 9.
  • the support substrate 4 that is not covered by the mask layer 21 is removed by dry etching
  • the insulating layer 3 that is revealed by removing the support substrate 4 is removed by wet etching.
  • a mask layer 22 is formed on the back surface of the semiconductor layer 2.
  • the mask layer 22 can be formed from a resist pattern.
  • a pattern of multiple openings 22a is formed in the mask layer 22 by exposure and development.
  • the semiconductor layer 2 exposed from the opening 22a is etched.
  • This etching is dry etching, and although not limited thereto, it is preferable to use an etching gas that contains a fluorine compound and oxygen, and optionally a rare gas.
  • the fluorine compound may be, for example, one or more selected from CF 4 , SF 6 , NF 3 , BF 3 , PF 5 , and F 2
  • the rare gas may be, for example, one or more selected from helium and argon.
  • etching was performed using CF4 gas, O2 gas, and Ar gas in a dry etching apparatus.
  • the processing conditions were CF4 gas at 10 to 100 sccm, O2 gas at 0 to 100 sccm, Ar gas at 0 to 200 sccm, IPC power at 200 to 1000 W, RIE power at 0 to 1000 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • an opening 5 is formed in the semiconductor layer 2, the width of which gradually decreases as it moves away from the mask layer 22 (towards the first surface 2a of the semiconductor layer 2). This allows the sidewall surface 6 of the opening 5 to be formed as an inclined surface. Then, in the step of FIG. 6(g), the mask layer 22 is removed. This completes the deposition mask 1.
  • a plurality of openings 5 can be formed in the semiconductor layer 2, and the sidewall surface 6 of the openings 5 can be formed as an inclined surface such that the opening width gradually narrows from the back surface (second surface 2b) of the semiconductor layer 2 facing the deposition source 11 toward the front surface (first surface 2a) facing the deposition substrate 10.
  • the opening width W1 and taper angle ⁇ 1 can be adjusted by the various gas flow rates, chamber pressure, and power of the plasma generation source, etc.
  • the semiconductor layer 2 is deeply etched to form the opening 5, and the unevenness height difference Dn of the sidewall surface 6 is larger than in the dry etching process described in FIG. 6.
  • the unevenness height difference Dn of the opening 5 formed in the semiconductor layer 2 is about 0.040 ⁇ m to 0.300 ⁇ m.
  • the unevenness height difference Dn of the opening 5 formed in the semiconductor layer 2 is about 0.003 ⁇ m to 0.020 ⁇ m. For this reason, it is preferable to apply the manufacturing method shown in FIG.
  • the opening width W1 becomes narrower (for example, the opening width W1 is 5 ⁇ m or less), and to apply the manufacturing method shown in FIG. 5 when the opening width W1 is 5 ⁇ m or more.
  • the manufacturing method shown in FIG. 5 it is possible to reduce the unevenness height difference by laser hydrogen annealing treatment, etc., as described above.
  • the deposition mask 1 is disposed between a deposition substrate 10 and a deposition source 11. At this time, the first surface 2a of the semiconductor layer 2 of the deposition mask 1 faces the deposition substrate 10, and the second surface 2b of the semiconductor layer 2 faces the deposition source 11. A plurality of openings 5 are formed in the semiconductor layer 2, and the opening width is narrower on the first surface side than on the second surface side.
  • the deposition mask 1 is placed in a holder (not shown) of the deposition device, and the deposition mask 1 and the deposition substrate 10 can be fixed with an electrostatic chuck.
  • the deposition mask 1 and the deposition substrate 10 are rotated around the axial center of the holder as the rotation axis.
  • the deposition material (deposition particles) 12 from the deposition source 11 passes through the openings 5 in the deposition mask 1 and reaches the surface 10a of the deposition substrate 10, forming a deposition film 13.
  • examples of electronic devices include OLED microdisplay panels, liquid crystal panels, solar cells, etc.
  • the present invention is particularly suitable for a manufacturing method for an OLED microdisplay panel as an organic electronic device.
  • the pattern width W3 of the deposition film 13 can be ensured to be 80% or more of the opening width W1, preferably 85% or more, and more preferably 90% or more. In this way, a deposition film 13 with excellent pattern dimensions can be formed.
  • the opening width W1 is set to a range of 30 ⁇ m or less, and the unevenness ratio R is set to 0.0001 or more and 0.0420 or less, so that a deposition film 13 having excellent pattern dimensions can be stably formed.
  • the unevenness of the sidewall surface of an opening was uniformly regulated based on the roughness at which deposition material would not easily accumulate.
  • the allowable size of unevenness varies depending on the opening width. Therefore, with conventional control methods, it is not possible to stably form a deposition film 13 with high pattern dimensions, regardless of the opening width.
  • a new factor called the unevenness ratio R is introduced, and by adjusting the average value Ave of the unevenness height difference Dn so that the unevenness ratio R is 0.0001 or more and 0.0420 or less, regardless of the size of the opening width W1, as long as the opening width W1 is in the range of 30 ⁇ m or less, a deposition film 13 having a pattern width W3 with a pattern width ratio of 80% or more can be stably formed.
  • the present invention is not limited to the above-mentioned embodiments and modifications, and may be modified, substituted, or altered in various ways without departing from the spirit of the technical idea. Furthermore, if the technical idea can be realized in a different way due to technological advances or derived other technologies, it may be implemented using that method. Therefore, the scope of the claims covers all embodiments that may fall within the scope of the technical idea.
  • a membrane 31 made of SiN, SiO2, or the like may be formed on the surface of a frame-shaped silicon substrate 30, and a plurality of openings 32 may be formed in the membrane 31 in the central region from which the silicon substrate 30 has been removed, or a single-layer structure may be formed in which a plurality of openings are formed in a semiconductor substrate (preferably a silicon substrate).
  • the membrane is formed by CVD, but it is preferable to use SiN from the viewpoint of easy stress control.
  • an SOI substrate 9 is used as in Figure 1, but in Figure 8, a SiN layer 33 is formed on the back side (support substrate 4 side, facing deposition source 11) of the SOI substrate 9, in Figure 9, a SiN layer 33 is formed on the front side (semiconductor layer 2 side, facing deposition substrate 10) of the SOI substrate 9, and in Figure 10, a SiN layer 33 is formed on both the back side and front side of the SOI substrate 9.
  • a SiN layer 33 is formed on the front side (semiconductor layer 2 side) of the SOI substrate 9
  • an opening 5 is formed in contiguous with the semiconductor layer 2 as shown in Figures 9 and 10.
  • the SiN layer 33 By providing the SiN layer 33, it becomes easier to control the stress of the deposition mask, and distortion and the like can be suppressed. Moreover, it is preferable that the SiN layer 33 formed on the front side of the SOI substrate 9 is thinner than the SiN layer 33 formed on the back side of the SOI substrate 9. Although not limited thereto, the thickness of the SiN layer 33 formed on the front side of the SOI substrate 9 is about 0.05 ⁇ m to 0.5 ⁇ m, and the thickness of the SiN layer 33 formed on the back side of the SOI substrate 9 is about 0.05 ⁇ m to 3 ⁇ m.
  • the SiN layer 33 formed on the front side of the SOI substrate 9 is formed thinner than the SiN layer 33 formed on the back side of the SOI substrate 9 in order to control the stress in a well-balanced manner between the front side and the back side.
  • the SOI substrate used had a support substrate (625 ⁇ m)/insulating layer (0.5 ⁇ m)/semiconductor layer (15 ⁇ m or 5 ⁇ m).
  • the parentheses indicate the thickness.
  • the support substrate was a Si substrate
  • the semiconductor layer was a Si layer
  • the insulating layer was a SiO2 layer.
  • the outer diameter of the SOI substrate was 200 mm.
  • two types of SOI substrates were prepared, one with a semiconductor layer thickness of 15 ⁇ m and the other with a thickness of 5 ⁇ m.
  • step (b) shown in FIG. 5 and step (e) shown in FIG. 6 an opening pattern is formed in the mask layer (resist layer) by i-line exposure, and the opening width of the master plate used in forming this opening pattern was adjusted within the range of 2.0 ⁇ m to 30 ⁇ m.
  • the deposition mask 1 was formed using the manufacturing method shown in FIG. 5 and FIG. 6.
  • the opening width W1 was changed depending on the master plate used.
  • the opening width W1 and taper angle ⁇ 1 formed in the semiconductor layer 2 were adjusted by adjusting the flow rates of various gases, the chamber pressure, and the power of the plasma generation source.
  • anisotropic dry etching using fluorine ions was performed by applying a bias to the substrate to be etched using the same gas as that used in the mode in which isotropic dry etching using fluorine radicals is performed using SF 6 gas.
  • the processing conditions were SF 6 gas at 0 to 500 sccm, C 4 F 8 gas at 0 to 300 sccm, Platen LF at 0 to 1500 W, Coil RF at 300 to 1500 W, and chamber pressure at 1 to 10 Pa, and various conditions were adjusted.
  • the opening width W1 was defined as the width dimension in the surface direction along the first surface 2a of the semiconductor layer 2.
  • the opening width W1 can be obtained from an SEM image obtained using eCD-2 manufactured by KLA-Tencor.
  • the unevenness height difference Dn and taper angle ⁇ 1 were obtained by the method described in Figure 2 from SEM images obtained using Hitachi High-Tech's Regulus 8220. As described in Figure 2, the unevenness height difference Dn and taper angle ⁇ 1 were obtained by observing five pitches in the center of the thickness of the uneven shape formed on the side wall surface 6 at the middle point of the opening height.
  • the unevenness height difference Dn and taper angle ⁇ 1 please refer to the explanations in Figures 1 and 2. Note that the experimental examples obtained as pitch are limited to those with odd numbers in Tables 1 and 2.
  • the pattern width W3 of the evaporated film was measured using a laser microscope (model number VK-X210 (Keyence)) to determine the pattern width ratio of the evaporated film to the opening width W1 of the evaporation mask ((W3/W1) x 100 (%)).
  • Experimental examples with a pattern width ratio of less than 70% were marked with an X, experimental examples with a pattern width ratio of 70% to 80% with a ⁇ , experimental examples with a pattern width ratio of 80% to 90% with an ⁇ , and experimental examples with a pattern width ratio of over 90% with an ⁇ .
  • Table 1 shows the experimental results when the semiconductor layer thickness was 15 ⁇ m
  • Table 2 shows the experimental results when the semiconductor layer thickness was 5 ⁇ m.
  • the opening width W1 is set to 30 ⁇ m or less, preferably 20 ⁇ m or less, so as to be preferably used as a deposition mask for RGB color separation used in the manufacturing process of an OLED microdisplay. Furthermore, based on the experimental example, the opening width W1 is set to an even more preferable range of 3 ⁇ m or more and 20 ⁇ m.
  • the unevenness ratio R is preferably set to 0.0400 or less, and more preferably set to 0.0380 or less.
  • the average value Ave of the unevenness height difference Dn is preferably 0.200 ⁇ m or less, more preferably 0.18 ⁇ m or less, and even more preferably 0.170 ⁇ m or less.
  • the lower limit of the average value Ave of the unevenness height difference Dn is set to 0.001 ⁇ m or more, or 0.003 ⁇ m or more.
  • the maximum unevenness height difference Dn is preferably 0.500 ⁇ m or less, more preferably 0.450 ⁇ m or less, even more preferably 0.400 ⁇ m or less, even more preferably 0.350 ⁇ m or less, and most preferably 0.300 ⁇ m or less.
  • the taper angle is preferably 60° or more, and more preferably 70° or more.
  • the lower limit of the taper angle can be less than 90°, or 85° or less, or 80° or less.
  • Experimental examples show that the taper angle can be set in the range of 60° or more and 80° or less. An error of about ⁇ 3° is permitted for the taper angle.
  • the concave-convex angles ⁇ 2 and ⁇ 3 described in FIG. 2 were approximately 11° to 41° in the odd-numbered experimental examples.
  • the concave-convex angles ⁇ 2 and ⁇ 3 were approximately 1.0° to 1.5° in the even-numbered experimental examples.
  • the unevenness angles ⁇ 2 and ⁇ 3 can be set within a range of approximately 0.5° to 50°, and when the opening width W1 is 5 ⁇ m or less, it is desirable to make the unevenness angles ⁇ 2 and ⁇ 3 as small as possible, setting them to 10° or less, with the most preferable range being approximately 0.5° to 2°. It has also been found that the unevenness angle ⁇ 3 is smaller than the unevenness angle ⁇ 2, which results in a form that can suppress the deposition of the deposition material.
  • FIG. 11(a) is an image of deposition of deposition material 19 when the thickness of semiconductor layer 2 is about 3 to 5 ⁇ m
  • FIG. 11(b) is an image of deposition of deposition material 19 when the thickness of semiconductor layer 2 is about 15 to 20 ⁇ m. From the top to the bottom, FIG. 11(a) and (b) show how deposition material 19 is deposited on the lower sidewall of opening 5. As shown in FIG. 11(a) and (b), even if the thickness of semiconductor layer 2 is different, the range where deposition material 19 is deposited on sidewall surface 6 of opening 5 is almost the same, and it is considered that the deposition result is almost the same.
  • the deposition result is not very different when the thickness of semiconductor layer 2 is within the range of 2 to 20 ⁇ m. Therefore, although the above is an example of an experiment when the thickness of semiconductor layer is 15 ⁇ m and 5 ⁇ m, it can be estimated that even with other thicknesses, the pattern width ratio can be made 80% or more by adjusting the unevenness ratio R in the range of 0.0001 to 0.0420.
  • the thickness of the semiconductor layer is about 3 to 5 ⁇ m before the deposition material is deposited on the sidewall surface of the opening, a pattern width ratio of more than 90% can be reliably obtained.

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PCT/JP2024/028528 2023-08-10 2024-08-08 蒸着マスク及び、電子デバイスの製造方法 Pending WO2025033507A1 (ja)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008189990A (ja) * 2007-02-05 2008-08-21 Seiko Epson Corp 蒸着用マスクおよび蒸着用マスクの製造方法
US20200044010A1 (en) * 2017-04-14 2020-02-06 Shanghai Seeo Optronics Technology Co., Ltd Shadow mask for oled evaporation and manufacturing method therefor, and oled panel manufacturing method
JP2020158807A (ja) * 2019-03-25 2020-10-01 大日本印刷株式会社 マスク
JP2022184708A (ja) * 2021-05-31 2022-12-13 キヤノン株式会社 蒸着マスク、及び有機電子デバイスの製造方法
WO2023145951A1 (ja) * 2022-01-31 2023-08-03 大日本印刷株式会社 蒸着マスク、フレーム付き蒸着マスク、蒸着マスクの製造方法、有機デバイスの製造方法及びフレーム付き蒸着マスクの製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008189990A (ja) * 2007-02-05 2008-08-21 Seiko Epson Corp 蒸着用マスクおよび蒸着用マスクの製造方法
US20200044010A1 (en) * 2017-04-14 2020-02-06 Shanghai Seeo Optronics Technology Co., Ltd Shadow mask for oled evaporation and manufacturing method therefor, and oled panel manufacturing method
JP2020158807A (ja) * 2019-03-25 2020-10-01 大日本印刷株式会社 マスク
JP2022184708A (ja) * 2021-05-31 2022-12-13 キヤノン株式会社 蒸着マスク、及び有機電子デバイスの製造方法
WO2023145951A1 (ja) * 2022-01-31 2023-08-03 大日本印刷株式会社 蒸着マスク、フレーム付き蒸着マスク、蒸着マスクの製造方法、有機デバイスの製造方法及びフレーム付き蒸着マスクの製造方法

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