WO2025001706A1 - 阵列基板、显示面板和显示装置 - Google Patents

阵列基板、显示面板和显示装置 Download PDF

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Publication number
WO2025001706A1
WO2025001706A1 PCT/CN2024/095889 CN2024095889W WO2025001706A1 WO 2025001706 A1 WO2025001706 A1 WO 2025001706A1 CN 2024095889 W CN2024095889 W CN 2024095889W WO 2025001706 A1 WO2025001706 A1 WO 2025001706A1
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WIPO (PCT)
Prior art keywords
base substrate
orthographic projection
light
substrate
branch portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/095889
Other languages
English (en)
French (fr)
Inventor
张永强
徐敬义
李伟
尹晓峰
丁爱宇
侯靖威
霍培荣
李峰
李志�
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Beijing BOE Technology Development Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Ordos Yuansheng Optoelectronics Co Ltd
Beijing BOE Technology Development Co Ltd
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Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Ordos Yuansheng Optoelectronics Co Ltd, Beijing BOE Technology Development Co Ltd filed Critical BOE Technology Group Co Ltd
Publication of WO2025001706A1 publication Critical patent/WO2025001706A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136209—Light shielding layers, e.g. black matrix, incorporated in the active matrix substrate, e.g. structurally associated with the switching element
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

Definitions

  • At least one embodiment of the present disclosure provides an array substrate, a display panel and a display device.
  • the orthographic projection of the light-shielding layer on the base substrate at least covers the orthographic projections of the first channel region and the first via structure on the base substrate.
  • the array substrate can reduce the leakage current of the subsequently formed display panel by adjusting the design of the light-shielding layer to enhance the retention capacity of the pixel capacitor, thereby improving the problem of flickering at low frequencies and ensuring the aperture ratio of the subsequently formed display panel.
  • the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the light shielding layer on the base substrate.
  • the array substrate provided in at least one embodiment of the present disclosure, there is a gap between the light shielding layer and the connecting portion in the first direction.
  • the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light-shielding portion on the base substrate, and the orthographic projection of the second via structure on the base substrate is located outside the orthographic projection of the second sub-light-shielding portion on the base substrate.
  • At least one embodiment of the present disclosure also provides a display panel, which includes a first substrate and a second substrate arranged opposite to each other, wherein the first substrate includes a base substrate and a semiconductor layer and a light-shielding layer stacked on the base substrate; the second substrate includes a black matrix; the semiconductor layer includes a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, a first via structure is provided on a side of the first branch portion away from the base substrate, and the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the end of the first branch portion away from the connecting portion on the base substrate; the orthographic projection of the light-shielding layer on the base substrate is located within the orthographic projection of the black matrix on the base substrate, and at least covers the orthographic projection of the first channel region and the first via structure on the base substrate.
  • the end of the second branch portion away from the connecting portion corresponds to a second via structure, and the second via structure is farther away from the connecting portion than the first via structure.
  • the material of the light-shielding layer includes a conductive metal
  • the orthographic projection of the black matrix on the base substrate covers the orthographic projection of the second via structure on the base substrate
  • the orthographic projection of the second via structure on the base substrate is outside the orthographic projection of the light-shielding layer on the base substrate.
  • a plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure.
  • the first branch portion and the second branch portion both extend along a first direction
  • the connecting portion extends along a second direction intersecting the first direction
  • the first branch portion, the second branch portion and the connecting portion are arranged to form an opening area
  • the light-shielding layer covers at least part of the opening area.
  • the first substrate further includes a first metal layer disposed on a side of the semiconductor layer away from the base substrate, and the first metal layer
  • the layer includes a gate line extending in the second direction, the gate line includes a first gate and a second gate, the orthographic projection of the first gate on the base substrate overlaps with the orthographic projection of the first channel region on the base substrate, and the orthographic projection of the second gate on the base substrate overlaps with the orthographic projection of the second channel region on the base substrate.
  • the orthographic projection of the first gate on the base substrate is within the orthographic projection of the black matrix on the base substrate
  • the orthographic projection of the second gate on the base substrate is within the orthographic projection of the black matrix on the base substrate.
  • the display panel provided in at least one embodiment of the present disclosure, there is a gap between the light shielding layer and the connecting portion in the first direction.
  • the orthographic projection of the edge of the portion of the light-shielding layer corresponding to the first branch portion close to the connecting portion on the base substrate overlaps with the orthographic projection of the edge of the portion of the black matrix corresponding to the first branch portion close to the connecting portion on the base substrate.
  • the orthographic projection of the edge of the light-shielding layer away from the connecting portion on the base substrate includes a first part located on the side of the first via structure away from the connecting portion and a second part located on the side of the second via structure away from the connecting portion, and the orthographic projection of the second part on the base substrate is located within the orthographic projection of the edge of the black matrix farthest from the second via structure on the base substrate.
  • the orthographic projection of the first via structure on the base substrate is located within the orthographic projection of the first sub-light shielding portion on the base substrate
  • the orthographic projection of the second via structure on the base substrate is located within the orthographic projection of the second sub-light shielding portion on the base substrate. Outside the orthographic projection on the substrate.
  • the end of the second branch portion away from the connecting portion corresponds to a second via structure
  • the maximum distance between the second via structure and the connecting portion is equal to the maximum distance between the first via structure and the connecting portion.
  • the material of the light-shielding layer includes a non-conductive light-shielding material
  • the orthographic projection of the black matrix on the base substrate and the orthographic projection of the light-shielding layer on the base substrate both cover the orthographic projection of the second via structure on the base substrate.
  • a plurality of thin film transistors are arranged on the first substrate, portions of the light-shielding layer corresponding to different thin film transistors are spaced apart from each other, and portions of the light-shielding layer corresponding to the first channel region and the second channel region of the same thin film transistor are an integral structure or a structure spaced apart from each other.
  • At least one embodiment of the present disclosure further provides a display device, which includes the array substrate described in any of the above embodiments, or the display panel described in any of the above embodiments.
  • FIG1 is a schematic diagram of a planar structure of a thin film transistor
  • FIG2 is a schematic diagram of a cross-sectional structure of an array substrate
  • FIG3 is a schematic diagram of a cross-sectional structure of the thin film transistor in FIG1 ;
  • FIG5 is a schematic diagram of a stacked structure of an array substrate provided by at least one embodiment of the present disclosure.
  • FIG6 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG7 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG8 is a schematic diagram of a cross-sectional structure of the array substrate in FIG7 ;
  • FIG9 is a schematic diagram of a planar structure of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG10 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG9 ;
  • FIG11 is a schematic diagram of a planar structure of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG12 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG11;
  • FIG13 is a schematic diagram of a planar structure of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG14 is a schematic diagram of a cross-sectional structure of the array substrate shown in FIG13 ;
  • FIG15 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG16 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG17 is a schematic diagram of a stacked structure of another array substrate provided by at least one embodiment of the present disclosure.
  • FIG18 is a schematic diagram of a cross-sectional structure of a display panel provided by at least one embodiment of the present disclosure.
  • FIG19 is a schematic diagram of a planar structure of a display panel provided by at least one embodiment of the present disclosure.
  • FIG20 is a schematic diagram of a cross-sectional structure of a first substrate provided by at least one embodiment of the present disclosure
  • FIG21 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure.
  • FIG22 is a schematic diagram of the cross-sectional structure of the first substrate in FIG21;
  • FIG23 is a schematic diagram of a planar structure of yet another display panel provided by at least one embodiment of the present disclosure.
  • FIG24 is a schematic diagram of the cross-sectional structure of the first substrate in FIG23;
  • FIG25 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure.
  • FIG26 is a schematic diagram of the cross-sectional structure of the first substrate in FIG25;
  • FIG27 is a schematic diagram of a planar structure of yet another display panel provided by at least one embodiment of the present disclosure.
  • FIG28 is a schematic diagram of the cross-sectional structure of the first substrate in FIG27;
  • FIG29 is a schematic diagram of a planar structure of yet another display panel provided by at least one embodiment of the present disclosure.
  • FIG30 is a schematic diagram of the cross-sectional structure of the first substrate shown in FIG29;
  • FIG31 is a schematic diagram of a planar structure of yet another display panel provided by at least one embodiment of the present disclosure.
  • FIG32 is a schematic diagram of the cross-sectional structure of the first substrate shown in FIG31;
  • FIG33 is a schematic diagram of a planar structure of yet another display panel provided by at least one embodiment of the present disclosure.
  • FIG. 36 is a block diagram of a display device provided by at least one embodiment of the present disclosure.
  • the array substrate 21 also includes a first metal layer 214 arranged on a side of the semiconductor layer 212 away from the base substrate 211, the first metal layer 214 includes a gate line 2128 extending in the second direction Y, the gate line 2128 is in a long strip shape, the gate line 2128 includes a first gate 2128a and a second gate 2128b, the orthographic projection of the first gate 2128a on the base substrate 211 overlaps with the orthographic projection of the first channel region 2124 on the base substrate 211, and the orthographic projection of the second gate 2128b on the base substrate 211 overlaps with the orthographic projection of the second channel region 2125 on the base substrate 211.
  • the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure
  • the first gate 2128a and the second gate 2128b are part of the gate line 2128
  • the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124
  • the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.
  • a first insulating layer 219 is provided between the light-shielding layer 213 and the semiconductor layer 212 , a gate insulating layer 217 is provided between the first insulating layer 219 and the first metal layer 214 , and an interlayer insulating layer 218 is provided on the side of the first metal layer 214 away from the base substrate 211 .
  • the orthographic projection of the side of the first sub-light shielding portion 213a away from the connection portion 2123 on the base substrate 211 includes a first portion 213c located on the side of the first via structure 2126 away from the connection portion 2123
  • the orthographic projection of the side of the second sub-light shielding portion 213b away from the connection portion 2123 on the base substrate 211 includes a second portion 213d located on the side of the second via structure 2127 away from the connection portion 2123, that is, the plane shapes of the first sub-light shielding portion 213a and the second sub-light shielding portion 213b are both long strips, and the length of the first sub-light shielding portion 213a is equal to the length of the second sub-light shielding portion 213b.
  • the distance between the first portion 213c and the connection portion 2123 is equal to the distance between the second portion 213d and the connection portion 2123.
  • the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the light shielding layer 213 on the base substrate 211.
  • the material of the light-shielding layer 213 is a non-conductive light-shielding material. Even if the interlayer insulating layer 218 is etched to over-etch the light-shielding layer 213, the first source-drain electrode and the second source-drain electrode of the thin-film transistor will not be short-circuited.
  • the sub-light shielding portion 213a and the second sub-light shielding portion 213b are spaced from each other, the orthographic projection of the first channel region 2124 on the substrate 211 is completely located within the orthographic projection of the first sub-light shielding portion 213a on the substrate 211, and the orthographic projection of the second channel region 2125 on the substrate 211 is completely located within the orthographic projection of the second sub-light shielding portion 213b on the substrate 211.
  • Figure 13 is a schematic diagram of the planar structure of another array substrate provided by at least one embodiment of the present disclosure
  • Figure 14 is a schematic diagram of the cross-sectional structure of the array substrate shown in Figure 13.
  • the array substrate 21 includes a base substrate 211 and a light-shielding layer 213 and a semiconductor layer 212 stacked on the base substrate 211.
  • the semiconductor layer 212 includes a first branch portion 2121 and a second branch portion 2122 that are arranged opposite to each other, and a connecting portion 2123 connecting the first branch portion 2121 and the second branch portion 2122.
  • the first branch portion 2121 includes a first channel region 2124
  • the second branch portion 2122 includes a second channel region 2125.
  • the end of the first branch portion 2121 away from the connecting portion 2123 corresponds to the first via structure 2126, that is, the side of the first branch portion 2121 away from the substrate 211 has the first via structure 2126, and the orthographic projection of the first via structure 2126 on the substrate 211 is located within the orthographic projection of the end of the first branch portion 2121 away from the connecting portion 2123 on the substrate 211.
  • the end of the second branch portion 2122 away from the connection portion 2123 corresponds to the second via structure 2127, that is, the side of the second branch portion 2122 away from the base substrate 211 has the second via structure 2127, and the orthographic projection of the second via structure 2127 on the base substrate 211 is located within the orthographic projection of the end of the second branch portion 2122 away from the connection portion 2123 on the base substrate 211.
  • the orthographic projection of the light shielding layer 213 on the base substrate 211 covers the orthographic projections of the first channel region 2124, the second channel region 2125 and the first via structure 2126 on the base substrate 311.
  • the array substrate 21 can reduce the leakage current phenomenon and improve the retention capacity of the pixel capacitance by setting the light shielding layer 213 to cover the entire area of the first channel region 2124, the second channel region 2125 and the first via structure 2126, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel formed subsequently.
  • the distance between the second via structure 2127 and the connecting portion 2123 is equal to the distance between the first via structure 2124 and the connecting portion 2123, that is, in the plan view shown in FIG. 13 , the first branch portion 2121 and the second branch portion 2122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is equal to the length of the first branch portion 2121 in the first direction X, so that the second branch portion 2122 is The second via structure 2127 at the end portion and the first via structure 2124 corresponding to the end portion of the first branch portion 2121 are flush.
  • the first gate 2128a, the second gate 2128b and the gate line 2128 are an integrated linear structure
  • the first gate 2128a and the second gate 2128b are part of the gate line 2128
  • the first gate 2128a is the part of the gate line 2128 corresponding to the first channel region 2124
  • the second gate 2128b is the part of the gate line 2128 corresponding to the second channel region 2125.
  • a first insulating layer 219 is arranged between the light-shielding layer 213 and the semiconductor layer 212, a gate insulating layer 217 is arranged between the first insulating layer 219 and the first metal layer 214, and an interlayer insulating layer 218 is arranged on the side of the first metal layer 214 away from the base substrate 211.
  • the material of the light-shielding layer 213 includes a non-conductive light-shielding material or a conductive light-shielding material
  • the orthographic projection of the first via structure 2126 on the base substrate 211 is located within the orthographic projection of the light-shielding layer 213 on the base substrate 211.
  • the light-shielding layer 213 is an integral structure, and the orthographic projection of the light-shielding layer 213 on the base substrate 211 covers the orthographic projection of the first channel region 2124 on the base substrate 211, the orthographic projection of the second channel region 2125 on the base substrate 211, and the orthographic projection of the first via structure 2126 on the base substrate 211, as well as covers the gap between the first channel region 2124 and the second channel region 2125, and the planar shape of the light-shielding layer 213 is stepped.
  • Figure 15 is a schematic diagram of the stacked structure of another array substrate provided by at least one embodiment of the present disclosure.
  • a plurality of thin film transistors are arranged on the base substrate 211, and the portions of the light-shielding layer 213 corresponding to different thin film transistors are spaced apart from each other, and the light-shielding layer 213 only corresponds to the first channel region 2124 of the same thin film transistor, that is, the orthographic projection of the light-shielding layer 213 on the base substrate 211 only covers the orthographic projection of the first channel region 2124 on the base substrate 211, and does not cover the orthographic projection of the second channel region 2125 on the base substrate 211.
  • the end of the second branch portion 2122 away from the connecting portion 2123 corresponds to the second via structure 2127, and the second via structure 2127 is further away from the first via structure 2126.
  • the connecting portion 2123 that is, in the plan view shown in Figure 15, the first branch portion 2121 and the second branch portion 2122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 2122 in the first direction X is greater than the length of the first branch portion 2121 in the first direction X, that is, in the first direction X, the distance between the second via structure 2127 and the connecting portion 2123 is greater than the distance between the first via structure 2126 and the connecting portion 2123, so that the second via structure 2127 corresponding to the end of the second branch portion 2122 and the first via structure 2126 corresponding to the end of the first branch portion 2121 are not flush.
  • the array substrate 21 can reduce leakage current and enhance the pixel capacitance retention capability by designing the light-shielding layer 213 to cover the positive projection of the first channel region 2124 and the first via structure 2126 on the base substrate 211, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel to be subsequently formed.
  • FIG16 is a schematic diagram of a laminated structure of another array substrate provided by at least one embodiment of the present disclosure.
  • the difference between the array substrate shown in FIG16 and the array substrate shown in FIG5 is that a touch signal line 220 extending along the first direction X is provided between the first branch portion 2121 and the second branch portion 2122.
  • This design can save space for placing the wiring, making the array substrate thinner and lighter.
  • the structure of the array substrate shown in FIG16 can refer to the relevant description of the array substrate shown in FIG5, and will not be repeated here.
  • FIG17 is a schematic diagram of a laminated structure of another array substrate provided by at least one embodiment of the present disclosure.
  • the difference between the array substrate shown in FIG17 and the array substrate shown in FIG11 is that a touch signal line 220 extending along the first direction X is provided between the first branch portion 2121 and the second branch portion 2122.
  • This design can save space for wiring placement and make the array substrate thinner and lighter.
  • the structure of the array substrate shown in FIG17 can refer to the relevant description of the array substrate shown in FIG11, and will not be repeated here.
  • a black matrix can be further arranged on an opposing substrate arranged opposite to the array substrate, and the length of the light-shielding layer that blocks the spacing area on the lower side of the gate line in the first direction X can be reduced, so that the edges of the light-shielding layer are all shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.
  • At least one embodiment of the present disclosure provides a display panel, which includes a first substrate and a second substrate arranged opposite to each other, wherein the first substrate includes a base substrate and a semiconductor layer and a light shielding layer stacked on the base substrate; the second substrate includes a black matrix; the semiconductor layer includes a first branch portion and a second branch portion arranged opposite to each other, and a connecting portion connecting the first branch portion and the second branch portion, the first branch portion includes a first channel region, the second branch portion includes a second channel region, and a portion of the first branch portion away from the base substrate includes a second channel region.
  • One side has a first via structure
  • the orthographic projection of the first via structure on the substrate is located within the orthographic projection of the end of the first branch portion away from the connecting portion on the substrate;
  • the orthographic projection of the light shielding layer on the substrate is located within the orthographic projection of the black matrix on the substrate, and at least covers the first channel region and the orthographic projection of the first via structure on the substrate.
  • the display panel can reduce the leakage current of the display panel formed subsequently by adjusting the design of the light shielding layer to improve the retention capacity of the pixel capacitor, thereby improving the problem of flickering at low frequency, and can also ensure the aperture ratio of the display panel formed subsequently, and make the edges of the light shielding layer shrink to the area covered by the black matrix, so that the aperture ratio of the display panel can be further improved.
  • Figure 18 is a schematic diagram of the cross-sectional structure of a display panel provided by at least one embodiment of the present disclosure
  • Figure 19 is a schematic diagram of the planar structure of a display panel provided by at least one embodiment of the present disclosure
  • Figure 20 is a schematic diagram of the cross-sectional structure of a first substrate provided by at least one embodiment of the present disclosure.
  • the display panel 30 includes a first substrate 31 and a second substrate 32 relatively arranged, and the first substrate 31 includes a base substrate 311 and a light-shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311.
  • the second substrate 32 includes a black matrix 321
  • the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 that are arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122
  • the first branch portion 3121 includes a first channel region 3121a
  • the second branch portion 3122 includes a second channel region 3122a
  • an end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first branch portion 3121 has a first via structure 314 on a side away from the base substrate 311, and an orthographic projection of the first via structure 314 on the base substrate 311 is located at an end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311.
  • the orthographic projection of the shading layer 313 on the substrate 311 is within the orthographic projection of the black matrix 321 on the substrate 311, and at least covers the orthographic projections of the first channel region 3121a, the second channel region 3122a and the first via structure 314 on the substrate 311.
  • the display panel 30 sets the black matrix 321 to cover the entire area of the shading layer 313, and sets the shading layer 313 to cover the entire area of the first channel region 3121a, the second channel region 3122a and the first via structure 314. This can reduce the leakage current phenomenon of the display panel formed subsequently, enhance the retention capacity of the pixel capacitance, thereby improving the flicker problem under low frequency, and can also ensure the aperture ratio of the display panel.
  • the semiconductor layer is a state in the process of making the display panel. There are other processes to make part of the semiconductor area conductive, that is, after forming the gate and gate line mentioned later, there is a heavy doping step to make the part of the semiconductor layer outside the area covered by the gate conductive, so that the gate can block the channel area. Therefore, the semiconductor layer corresponding to the gate is located below the gate. Channel area.
  • the light shielding layer 313 covers the second channel region 3122 a , in other examples, the light shielding layer 313 may not cover the second channel region 3122 a .
  • the first substrate 31 is an array substrate
  • the second substrate 32 is an opposing substrate arranged opposite to the array substrate
  • the opposing substrate is, for example, a color filter substrate.
  • Other structures on the color filter substrate can refer to conventional designs and will not be described here.
  • the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the second via structure 315 is farther away from the connecting portion 3123 than the first via structure 314, that is, in the plan view shown in Figure 19, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the minimum distance between the second via structure 315 and the connecting portion 3123 is greater than the minimum distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.
  • the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate line 3161 extending in the second direction Y, the gate line 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.
  • the orthographic projection of the first gate 3161a on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311
  • the orthographic projection of the second gate 3161b on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, so that the black matrix 321 completely covers the first gate 3161a and the second gate 3161b.
  • the black matrix 321 covers an entire gate line 3161.
  • the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122 on one side, so that the left side of the black matrix has two protrusions.
  • the black matrix 321 also covers the data line.
  • the black matrix also covers the touch signal line.
  • a first insulating layer 319 is arranged between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is arranged between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is arranged on the side of the first metal layer 316 away from the base substrate 311.
  • the material of the light-shielding layer 313 includes a conductive metal with light-shielding properties
  • the orthographic projection of the black matrix 321 on the base substrate 311 and the orthographic projection of the light-shielding layer 313 on the base substrate 311 both cover the orthographic projection of the first via structure 314 on the base substrate 311
  • the orthographic projection of the second via structure 315 on the base substrate 311 is located outside the orthographic projection of the light-shielding layer 313 on the base substrate 311.
  • the second via structure 315 is blocked by the light-shielding layer 313, the light-shielding layer 313 needs to be blocked by the black matrix 321.
  • the alignment fluctuations of the multi-layer structure will lead to the need to design a wider black matrix, thereby sacrificing the pixel aperture ratio of the subsequently formed display panel.
  • the yield of the display panel there is a risk of over-etching the light-shielding layer 313 when etching the interlayer insulating layer 318.
  • the material of the light-shielding layer 313 is a conductive metal with light-shielding properties
  • over-etching the interlayer insulating layer 318 will cause a short circuit between the first source-drain electrode and the second source-drain electrode of the thin-film transistor, thereby causing the thin-film transistor to lose its switching function.
  • the light-shielding layer 313 when the material of the light-shielding layer 313 is not a conductive material with light-shielding properties, that is, when the material of the light-shielding layer 313 is an insulating material with light-shielding properties, the light-shielding layer 313 can also cover the second via structure 315, so that even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, there will be no short circuit problem between the first source-drain electrode and the second source-drain electrode of the thin-film transistor.
  • the light shielding layer 313 covers the first via structure 314, which has a significant effect on reducing the leakage current I off of the thin film transistor.
  • the blocking area of the light shielding layer 313 on the first channel region 3121a changes, the corresponding data of the leakage current I off of the thin film transistor of the display panel is as follows: Taking the conventional design as the benchmark (100%), the data obtained by the experimental item is compared with the data obtained by the conventional design.
  • the blocking area of the light shielding layer 313 on the first channel region 3121a is increased, the improvement effect on the leakage current I off of the thin film transistor of the display panel is obvious, but the adjustment of the blocking area of the light shielding layer 313 on the second channel region 3122a has little effect on the characteristics of the thin film transistor. Therefore, under the premise of not affecting the size of the aperture ratio of the display panel to be formed subsequently, the blocking area of the light shielding layer 313 on the first channel region 3121a is increased as much as possible, and the light shielding layer 313 on the second channel region 3122a is increased as much as possible.
  • a via structure 314 is used for shielding, and the shielding area of the second channel region 3122 a by the light shielding layer 313 is reduced, so as to reduce the influence on the aperture ratio of the display panel formed subsequently.
  • the black matrix 321 in order to ensure that the first via structure 314 does not leak light, the black matrix 321 needs to completely cover the first via structure 314, and make the distance between the first via structure 314 and the edge of the black matrix 321 adjacent to the first via structure 314 in the first direction X be 1.15 microns. Therefore, in order to ensure that the light-shielding layer 313 does not affect the aperture ratio of the display panel formed subsequently, in the first direction X, the upper edge of the right side portion of the light-shielding layer 313 corresponding to the first via structure is flush with the upper edge of the first via structure 314.
  • the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns
  • the light shielding layer 313 completely shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314.
  • the light shielding layer 313 shields the first branch portion 3121 by 6.15 microns.
  • the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 1.4 microns.
  • the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 to the gate line 3161 is 1.4 microns.
  • the length of the light shielding layer 313 is longer, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns.
  • the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the portion above the gate line 3161.
  • the light transmittance is 34% under 6500 nit illumination; and the light transmittance is 31% under 20000 nit illumination.
  • 10 sets of experimental data on low-frequency flicker are made, which are: -35.82, -33.53, -36.55, -36.45, -35.78, -38.12, -36.21, -36.45, -35.72 and -37.41, so that the average flicker value can be obtained to be -36.204.
  • the distance from the upper edge of the first via structure 314 to the gate line 3161 is 5.5 microns
  • the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, and on the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 5.5 microns.
  • the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 1.4 microns.
  • the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 to the gate line 3161 is 1.4 microns.
  • the length of the light shielding layer 313 is longer, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns.
  • the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the gap above the gate line 3161.
  • the light transmittance is 49% under 6500 nit illumination; and the light transmittance is 41% under 20000 nit illumination.
  • the distance from the upper edge of the first via structure 314 to the gate line 3161 is 5 microns
  • the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, and on the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 5 microns.
  • the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 1.4 microns.
  • the lower edge of the portion of the light shielding layer 313 corresponding to one side of the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121, and the distance from the lower edge of the light shielding layer 313 to the gate line 3161 is 1.4 microns.
  • the length of the light shielding layer 313 is relatively long, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns.
  • the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 blocks the gap between the first branch portion 3121 and the second branch portion 3122.
  • the light transmittance is 57% under 6500nit illumination, and 48% under 20000nit illumination.
  • the distance from the upper edge of the first via structure 314 to the gate line 3161 is 4.5 microns
  • the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, so on the upper side of the gate line 3161, the length of the light shielding layer 313 shielding the first branch portion 3121 is 4.5 microns.
  • the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 1.4 microns.
  • the lower edge of the portion of the light shielding layer 313 corresponding to one side of the first branch portion 3121 is designed to be flush with the lower edge of the black matrix 321, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to one side of the first branch portion 3121 to the gate line 3161 is 1.4 microns.
  • the length of the light shielding layer 313 is relatively long, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns.
  • the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the gap above the gate line 3161.
  • the light transmittance is 64% under 6500nit illumination; and the light transmittance is 61% under 20000nit illumination.
  • the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns
  • the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, and on the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 6.15 microns.
  • the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 0.7 microns.
  • the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 to the gate line 3161 is 0.7 microns.
  • the length of the light shielding layer 313 is longer, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 microns, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 microns.
  • the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 is not too large.
  • the light layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the portion above the gate line 3161.
  • the light transmittance is 36% under 6500nit illumination; and the light transmittance is 35% under 20000nit illumination.
  • the distance from the upper edge of the first via structure 314 to the gate line 3161 is 6.15 microns
  • the light shielding layer 313 shields the first via structure 314, and the upper edge of the light shielding layer 313 is flush with the upper edge of the first via structure 314, and on the upper side of the gate line 3161, the length of the first branch portion 3121 shielded by the light shielding layer 313 is 6.15 microns.
  • the length of the portion of the black matrix 321 corresponding to one side of the first branch portion 3121 is 0 microns.
  • the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 is designed to be flush with the lower edge of the portion of the black matrix 321 corresponding to the first branch portion 3121, and the distance from the lower edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 to the gate line 3161 is 0 micrometers.
  • the length of the light shielding layer 313 is longer, and the minimum distance between the right edge of the light shielding layer 313 and the right edge of the first branch portion 3121 is 2.0 micrometers, and the minimum distance between the left edge of the light shielding layer 313 and the left edge of the second branch portion 3122 is 2.0 micrometers.
  • the light shielding layer 313 is designed as a whole block, and the light shielding layer 313 completely blocks the gap between the first branch portion 3121 and the second branch portion 3122, that is, the light shielding layer 313 fully blocks the portion above the gate line 3161.
  • the light transmittance is 39% under 6500 nit illumination; and the light transmittance is 32% under 20000 nit illumination.
  • the channel region corresponding to the two gates of the thin film transistor is shielded by a whole shading layer or a shading layer with a larger area and spaced apart, and the shading layer increases the shielding area on one side of the first source and drain electrode connected to the pixel electrode, that is, when the first via structure in the above interlayer insulating layer is blocked, the leakage current of the thin film transistor included in the display panel can be reduced, and the length of the shading layer on the lower side of the gate line in the first direction X that shields the spacing area is reduced, so that the edges of the shading layer are all shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.
  • a plurality of thin film transistors may be disposed on the first substrate 31, and portions of the light shielding layer 313 corresponding to different thin film transistors are spaced apart from each other.
  • portions of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are an integral structure.
  • the light shielding layer 313 is designed as an integral structure so that the portions of the first channel region 3121a and the second channel region 3122a covered by the light shielding layer 313 are spaced apart from each other.
  • the area of one side of the hole structure 314 is increased, thereby reducing the leakage current of the thin film transistor.
  • the first branch portion 3121 and the second branch portion 3122 both extend along a first direction X
  • the connecting portion 3123 extends along a second direction Y intersecting the first direction X.
  • the first branch portion 3121, the second branch portion 3122 and the connecting portion 3123 are arranged to form an opening area, and the shading layer 313 covers at least part of the opening area, so that the shading layer 313 can be arranged to cover the entire area of the first channel region 3121a, the second channel region 3122a and the first via structure 314, so as to reduce the leakage current of the thin film transistor, enhance the retention capacity of the pixel capacitance, improve the flicker problem at low frequency, and in addition, ensure the aperture ratio of the display panel.
  • the first direction X and the second direction Y are perpendicular.
  • the orthographic projections of the two side edges of the gate line 3161 in the second direction Y on the substrate substrate 311 and the orthographic projections of the corresponding two side edges of the black matrix 321 in the second direction Y on the substrate substrate 311 overlap respectively, that is, the orthographic projections of the edge lines on both sides of the gate line 3161 in the second direction Y on the substrate substrate 311 and the orthographic projections of the edge lines on both sides of the black matrix 321 in the second direction Y on the substrate substrate 311 coincide with each other, so that the gate line 3161 can be shrunk into the area covered by the black matrix 321, thereby further improving the aperture ratio of the display panel.
  • the orthographic projection of the edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 close to the connection portion 3123 on the substrate substrate 311 overlaps with the orthographic projection of the edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 close to the connection portion 3123 on the substrate substrate 311, that is, the orthographic projection of the edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 close to the connection portion 3123 on the substrate substrate 311 and the orthographic projection of the edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 on the substrate substrate 311 overlaps with the orthographic projection of the edge of the portion of the light shielding layer 313 corresponding to the first branch portion 3121 on the substrate substrate 311.
  • the orthographic projection of the edge of the portion of the light shading layer 313 corresponding to the first branch portion 3121 close to the connecting portion 3123 on the substrate 311 coincides with the orthographic projection of the edge of the portion of the black matrix 321 corresponding to the first branch portion 3121 close to the connecting portion 3123 on the substrate 311, so that the edge of the light shading layer 313 can be completely retracted into the area covered by the black matrix 321 to ensure the aperture ratio of the display panel.
  • the leftmost edge of the light shielding layer 313 may also coincide with the leftmost edge of the black matrix 321 or be located between the leftmost edge of the black matrix 321 and the leftmost edge of the black matrix 321.
  • the rightmost edge of the light shielding layer 313 may also coincide with the leftmost edge of the black matrix 321 or be located within the orthographic projection of the rightmost edge of the black matrix 321 on the base substrate 311 .
  • FIG. 21 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure
  • FIG. 22 is a schematic diagram of a cross-sectional structure of the first substrate in FIG. 21.
  • the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311.
  • the second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122.
  • the first branch portion 3121 includes a first channel region 3121a
  • the second branch portion 3122 includes a second channel region 3122a.
  • the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first
  • the side of the branch portion 3121 away from the base substrate 311 has a first via structure 314, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311, and the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, that is, the side of the second branch portion 3122 away from the base substrate 311 has the second via structure 315, and
  • the orthographic projection of the second via structure 315 on the substrate substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connecting portion 3123 on the substrate substrate 311, the orthographic projection of the light shielding layer 313
  • the display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the black matrix 321 to cover the entire area of the light shielding layer 313, and setting the light shielding layer 313 to cover the entire area of the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel.
  • the second via structure 315 is further away from the connecting portion 3123 than the first via structure 314, that is, in the plan view shown in FIG. 21 , the first branch portion 3121
  • Both the second branch portion 3122 are in the shape of elongated strips and extend in the first direction X.
  • the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is greater than the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.
  • the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate line 3161 extending in the second direction Y, the gate line 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.
  • the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122 on one side, so that the left side of the black matrix has two protrusions, and, although the data line is not shown in FIG19, in the actual product, the black matrix 321 also covers the data line.
  • the black matrix also covers the touch signal line.
  • a first insulating layer 319 is arranged between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is arranged between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is arranged on the side of the first metal layer 316 away from the base substrate 311.
  • the orthographic projection of the edge of the light shielding layer 313 away from the connection portion 3123 on the base substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connection portion 3123 and a second portion 313d located on the side of the second via structure 315 away from the connection portion 3123.
  • the upper edge of the first portion 313c and the upper edge of the second portion 313d are not on the same straight line, that is, the planar shape of the light shielding layer 313 is stepped, and the planar shape of the black matrix 321 is grid-shaped.
  • the planar shape of the light shielding layer 313 corresponding to the black matrix 321 is also stepped, and in the first direction X, the distance between the first portion 313c and the connection portion 3123 is less than the distance between the second portion 313d and the connection portion 3123.
  • the second portion 313d and the edge of the black matrix 321 located on the upper side of the second via structure 315 on the base substrate 311 are not aligned with each other.
  • the orthographic projections overlap, that is, the orthographic projections of the upper edge of the second portion 313d and the portion of the left side of the black matrix 321 corresponding to the second via structure 315 on the substrate substrate 311 coincide with each other, and the orthographic projections of the first portion 313c and the edge of the black matrix 321 located on the upper side of the first via structure 314 on the substrate substrate 311 are spaced apart.
  • the orthographic projection of the black matrix 321 on the substrate substrate 311 and the orthographic projection of the light shielding layer 313 on the substrate substrate 311 both cover the orthographic projection of the second via structure 315 on the substrate substrate 311, that is, the orthographic projection of the second via structure 315 on the substrate substrate 311 is located within the orthographic projection of the light shielding layer 313 on the substrate substrate 311.
  • the material of the light-shielding layer 313 is a non-conductive light-shielding material.
  • the material of the light-shielding layer 313 is a non-conductive light-shielding material, even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, the first source-drain electrode and the second source-drain electrode of the thin-film transistor will not be short-circuited.
  • FIG. 23 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure
  • FIG. 24 is a schematic diagram of a cross-sectional structure of the first substrate in FIG. 23.
  • the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311.
  • the second substrate 32 includes a black matrix 321
  • the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122
  • the first branch portion 3121 includes a first channel region 3121a
  • the second branch portion 3122 includes a second channel region 3122a
  • the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314
  • the orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311.
  • the portions of the light shielding layer 313 corresponding to different thin film transistors are spaced apart from each other, and the portions of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light shielding portion 313a and the second sub-light shielding portion 313b, and the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are spaced apart from each other.
  • the first sub-light shielding portion 313a covers the orthographic projection of the first channel region 3121a and the first via structure 314 on the base substrate 311, and the second sub-light shielding portion 313b covers the orthographic projection of the second channel region 3122a on the base substrate 311, but does not cover the orthographic projection of the second via structure 315 on the base substrate 311.
  • the display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the black matrix 321 to cover the entire area of the light-shielding layer 313 and the area between the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and designing the first sub-light-shielding portion 313a to cover the orthographic projection of the first channel region 3121a and the first via structure 314 on the base substrate 311, and designing the second sub-light-shielding portion 313b to cover the orthographic projection of the second channel region 3122a on the base substrate 311, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel.
  • the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the second via structure 315 is farther away from the connecting portion 3123 than the first via structure 314, that is, in the plan view shown in Figure 23, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is greater than the length of the first branch portion 3121 in the first direction X, that is, in the first direction X, the distance between the second via structure 315 and the connecting portion 3123 is greater than the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are not flush.
  • the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate 3161 extending in the second direction Y, the gate 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.
  • the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122, so that the left side of the black matrix has two protrusions, and, although the data line is not shown in FIG19, in the actual product, the black matrix 321 also covers the data line.
  • the black matrix also covers the touch signal line.
  • a first insulating layer 319 is arranged between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is arranged between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is arranged on the side of the first metal layer 316 away from the base substrate 311.
  • the orthographic projection of the edge of the first sub-light shielding portion 313a away from the connection portion 3123 on the substrate substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connection portion 3123
  • the orthographic projection of the edge of the second sub-light shielding portion 313b away from the connection portion 3123 on the substrate substrate 311 includes a second portion 313d located on the side of the second via structure 315 away from the connection portion 3123, that is, the planar shapes of the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are both long strips, and the length of the first sub-light shielding portion 313a is less than the length of the second sub-light shielding portion 313b.
  • the distance between the first portion 313c and the connection portion 3123 is less than the distance between the second portion 313d. and the distance between the connecting portion 3123.
  • the orthographic projection of the black matrix 321 on the substrate substrate 311 covers the orthographic projection of the second via structure 315 on the substrate substrate 311, and the orthographic projection of the light shielding layer 313 on the substrate substrate 311 does not cover the orthographic projection of the second via structure 315 on the substrate substrate 311, that is, the orthographic projection of the second via structure 315 on the substrate substrate 311 is outside the orthographic projection of the light shielding layer 313 on the substrate substrate 311.
  • the material of the light-shielding layer 313 is a non-conductive light-shielding material or a light-shielding conductive material. Even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, there will be no short circuit problem between the first source-drain electrode and the second source-drain electrode of the thin-film transistor.
  • a plurality of thin film transistors are arranged on the first substrate 31, and portions of the light-shielding layer 313 corresponding to different thin film transistors are spaced apart from each other.
  • portions of the light-shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b are spaced apart from each other, and the orthographic projection of the first channel region 3121a on the base substrate 311 is completely located within the orthographic projection of the first sub-light-shielding portion 313a on the base substrate 311, and the orthographic projection of the second channel region 3122a on the base substrate 311 is completely located within the orthographic projection of the second sub-light-shielding portion 313b on the
  • the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the first sub-light shielding portion 313a on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located outside the orthographic projection of the second sub-light shielding portion 313b on the base substrate 311.
  • the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, and the maximum distance between the second via structure 315 and the connecting portion 3123 is greater than the maximum distance between the first via structure 314 and the connecting portion 3123.
  • FIG. 25 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure
  • FIG. 26 is a schematic diagram of a cross-sectional structure of the first substrate in FIG. 25.
  • the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311.
  • the second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 that are arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122.
  • the first branch portion 3121 includes a first channel region 3121a
  • the second branch portion 3122 includes a second channel region 3122 a .
  • the end of the first branch portion 3121 away from the connection portion 3123 corresponds to the first via structure 314 .
  • the end of the second branch portion 3122 away from the connection portion 3123 corresponds to the second via structure 315 .
  • the orthographic projection of the light-shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311, and covers the orthographic projections of the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315 on the base substrate 311.
  • the display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the black matrix 321 to cover the entire area of the light-shielding layer 313, and setting the light-shielding layer 313 to cover the entire area of the first channel region 3121a, the second channel region 3122a, the first via structure 314 and the second via structure 315, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel.
  • the orthographic projection of the light-shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311, and the orthographic projection area of the light-shielding layer 313 on the base substrate 311 is smaller than the orthographic projection area of the black matrix 321 on the base substrate 311.
  • the embodiments of the present disclosure are not limited to this, and the portion of the black matrix covering the lower left corner of the connecting portion 3123 is not considered.
  • the planar shape of the light-shielding layer 313 and the planar shape of the portion of the black matrix 321 corresponding to the light-shielding layer may also be the same.
  • the second via structure 315 corresponds to the end of the second branch portion 3122 away from the connecting portion 3123.
  • the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123, that is, in the plan view shown in Figure 25, the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are flush.
  • the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate 3161 extending in the second direction Y, the gate 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projections of the first gate 3161a and the second gate 3161b on the base substrate 311 are within the orthographic projection of the black matrix 321 on the base substrate 311.
  • the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122 on one side, so that the left side of the black matrix has two protrusions, and, although the data line is not shown in FIG. 19 , in an actual product, the black matrix 321 also covers the data line.
  • the black matrix also covers the touch signal line.
  • a first insulating layer 319 is arranged between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is arranged between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is arranged on the side of the first metal layer 316 away from the base substrate 311.
  • the material of the light-shielding layer 313 includes a non-conductive light-shielding material
  • the orthographic projection of the black matrix 321 on the base substrate 311 covers the orthographic projections of the first via structure 314 and the second via structure 315 on the base substrate 311
  • the orthographic projections of the first via structure 314 and the second via structure 315 on the base substrate 311 are both located within the orthographic projection of the light-shielding layer 313 on the base substrate 311.
  • the light-shielding layer 313 is an integral structure, and the orthographic projection of the light-shielding layer 313 on the substrate substrate 311 covers the orthographic projection of the first channel region 3121a on the substrate substrate 311, the orthographic projection of the second channel region 3122a on the substrate substrate 311, the orthographic projection of the first via structure 314 on the substrate substrate 311, and the orthographic projection of the second via structure 315 on the substrate substrate 311, as well as covers the gap between the first channel region 3121a and the second channel region 3122a, and covers the gap between the first via structure 314 and the second via structure 315.
  • Figure 27 is a schematic diagram of the planar structure of another display panel provided by at least one embodiment of the present disclosure
  • Figure 28 is a schematic diagram of the cross-sectional structure of the first substrate in Figure 27.
  • the first substrate 31 includes a base substrate 311 and a light-shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311.
  • the second substrate 32 includes a black matrix 321
  • the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 that are arranged opposite to each other, and a connecting portion 3123 that connects the first branch portion 3121 and the second branch portion 3122
  • the first branch portion 3121 includes a first channel region 3121a
  • the second branch portion 3122 includes a second channel region 3122a
  • the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first via structure 314 is provided on the side of the first branch portion 3121 away from the base substrate 311
  • the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311, and the orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311.
  • the parts of the light shielding layer 313 corresponding to different thin film transistors are spaced apart from each other,
  • the portions of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light shielding portion 313a and the second sub-light shielding portion 313b, and the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are spaced from each other.
  • the first sub-light shielding portion 313a covers the orthographic projection of the first channel region 3121a and the first via structure 314 on the base substrate 311
  • the second sub-light shielding portion 313b covers the orthographic projection of the second channel region 3122a and the second via structure 315 on the base substrate 311.
  • the display panel 30 sets the black matrix 321 to cover the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, but does not cover the area between the first sub-light-shielding portion 313a and the second sub-light-shielding portion 313b, and designs the first sub-light-shielding portion 313a so that the orthographic projection of the first sub-light-shielding portion 313a on the substrate 311 covers the orthographic projection of the first channel region 3121a and the first via structure 314 on the substrate 311, and designs the second sub-light-shielding portion 313b so that the orthographic projection of the second sub-light-shielding portion 313b on the substrate 311 covers the orthographic projection of the second channel region 3122a and the second via structure 315 on the substrate 311.
  • This design can reduce leakage current and improve the retention capacity of pixel capacitance, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel
  • the second via structure 315 corresponds to the end of the second branch portion 3122 away from the connecting portion 3123
  • the minimum distance between the second via structure 315 and the connecting portion 3123 is equal to the minimum distance between the first via structure 314 and the connecting portion 3123, that is, in the plan view shown in Figure 27
  • the first branch portion 3121 and the second branch portion 3122 are both long strips and extend in the first direction X
  • the length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, that is, in the first direction X
  • the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123, so that the second via structure 315 corresponding to the end of the second branch portion 3122 and the first via structure 314 corresponding to the end of the first branch portion 3121 are flush.
  • the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate 3161 extending in the second direction Y, the gate 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311, and the orthographic projection of the gate line 3161 on the base substrate 311 is within the orthographic projection of the black matrix 321 on the base substrate 311, that is, the gate line 3161 is also contracted to within the range defined by the black matrix 321, thereby not reducing the aperture ratio of the display panel.
  • the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122 on one side, so that the left side of the black matrix has two protrusions, and, although the data line is not shown in FIG19 , in the actual product, the black matrix 321 also covers the data line.
  • the black matrix also covers the touch signal line.
  • a first insulating layer 319 is arranged between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is arranged between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is arranged on the side of the first metal layer 316 away from the base substrate 311.
  • the orthographic projection of the side of the first sub-light shielding portion 313a away from the connection portion 3123 on the base substrate 311 includes a first portion 313c located on the side of the first via structure 314 away from the connection portion 3123
  • the orthographic projection of the side of the second sub-light shielding portion 313b away from the connection portion 3123 on the base substrate 311 includes a second portion 313d located on the side of the second via structure 315 away from the connection portion 3123
  • the upper edge of the first portion 313c and the upper edge of the second portion 313d are on the same straight line, that is, the plane shapes of the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are both long strips
  • the length of the first sub-light shielding portion 313a in the first direction X is equal to the length of the second sub-light shielding portion 313b in the first direction X.
  • the distance between the first portion 313c and the connection portion 3123 is equal to the distance between the second portion 313d and the connection portion 3123.
  • the second portion 313d overlaps with the orthographic projection of the upper edge of the black matrix 321 located on the upper side of the second via structure 315 on the substrate 311, that is, the second portion 313d coincides with the orthographic projection of the upper edge of the black matrix 321 located on the upper side of the second via structure 315 on the substrate 311, and the first portion 313c coincides with the orthographic projection of the upper edge of the black matrix 321 located on the upper side of the first via structure 314 on the substrate 311.
  • the orthographic projection of the black matrix 321 on the substrate 311 and the orthographic projection of the light shielding layer 313 on the substrate 311 both cover the orthographic projection of the second via structure 315 on the substrate 311, that is, the orthographic projection of the second via structure 315 on the substrate 311 is located within the orthographic projection of the light shielding layer 313 on the substrate 311.
  • the material of the light-shielding layer 313 is a non-conductive light-shielding material. Even if the interlayer insulating layer 318 is etched to over-etch the light-shielding layer 313, the first source-drain electrode and the second source-drain electrode of the thin-film transistor will not be short-circuited.
  • a plurality of thin film transistors are disposed on the first substrate 31, and portions of the light shielding layer 313 corresponding to different thin film transistors are spaced apart from each other.
  • portions of the light shielding layer 313 corresponding to the first channel region 3121a and the second channel region 3122a of the same thin film transistor are respectively the first sub-light shielding portion 313a and the second sub-light shielding portion 313b, and the first sub-light shielding portion 313a and the second sub-light shielding portion 313b are spaced apart from each other.
  • the light portions 313b are spaced from each other, the orthographic projection of the first channel region 3121a on the base substrate 311 is completely located within the orthographic projection of the first sub-light shielding portion 313a on the base substrate 311, and the orthographic projection of the second channel region 3122a on the base substrate 311 is completely located within the orthographic projection of the second sub-light shielding portion 313b on the base substrate 311.
  • the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the first sub-light shielding portion 313a on the base substrate 311, and the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the second sub-light shielding portion 313b on the base substrate 311.
  • FIG29 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure
  • FIG30 is a schematic diagram of a cross-sectional structure of the first substrate shown in FIG29.
  • the first substrate 31 includes a base substrate 311 and a light shielding layer 313 and a semiconductor layer 312 stacked on the base substrate 311.
  • the second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, the first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a.
  • the end of the first branch portion 3121 away from the connection portion 3123 corresponds to the first via structure 314, that is, the first via structure 314 is provided on the side of the first branch portion 3121 away from the substrate 311, and the orthographic projection of the first via structure 314 on the substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connection portion 3123 on the substrate 311.
  • the end of the second branch portion 3122 away from the connection portion 3123 corresponds to the second via structure 315, that is, the second branch portion 3122 is provided on the side away from the substrate 311, and the orthographic projection of the second via structure 315 on the substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connection portion 3123 on the substrate 311.
  • the orthographic projection of the light shielding layer 313 on the substrate 311 is located within the orthographic projection of the black matrix 321 on the substrate 311.
  • the orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projections of the first channel region 3121a, the second channel region 3122a and the first via structure 2126 on the base substrate 311.
  • the display panel 30 can reduce leakage current and enhance the retention capacity of pixel capacitance by setting the light-shielding layer 213 to cover the entire area of the first channel region 3121a, the second channel region 3122a and the first via structure 314, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel to be formed subsequently.
  • the distance between the second via structure 315 and the connecting portion 3123 is equal to the distance between the first via structure 314 and the connecting portion 3123, that is, in the plan view shown in FIG. 29 , the first branch portion 3121 and the second branch portion 3122 are both in the shape of long strips and extend in the first direction X, and the length of the second branch portion 3122 in the first direction X is equal to the length of the first branch portion 3121 in the first direction X, so that the second branch portion 3122 is The second via structure 315 at the end portion and the first via structure 2124 corresponding to the end portion of the first branch portion 3121 are flush.
  • the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate line 3161 extending in the second direction Y, the gate line 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.
  • the first gate 3161a, the second gate 3161b and the gate line 3161 are an integrated linear structure
  • the first gate 3161a and the second gate 3161b are part of the gate line 3161
  • the first gate 3161a is the part of the gate line 3161 corresponding to the first channel region 3121a
  • the second gate 3161b is the part of the gate line 3161 corresponding to the second channel region 3122a.
  • the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122 on one side, so that the left side of the black matrix has two protrusions, and, although the data line is not shown in FIG19, in the actual product, the black matrix 321 also covers the data line.
  • the black matrix also covers the touch signal line.
  • a first insulating layer 319 is arranged between the light-shielding layer 313 and the semiconductor layer 312, a gate insulating layer 317 is arranged between the first insulating layer 319 and the first metal layer 316, and an interlayer insulating layer 318 is arranged on the side of the first metal layer 316 away from the base substrate 311.
  • the material of the light-shielding layer 313 includes a non-conductive light-shielding material or a conductive light-shielding material
  • the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the light-shielding layer 313 on the base substrate 311.
  • the light-shielding layer 313 is an integral structure, and the orthographic projection of the light-shielding layer 313 on the substrate substrate 311 covers the orthographic projection of the first channel region 3121a on the substrate substrate 311, the orthographic projection of the second channel region 3122a on the substrate substrate 311, and the orthographic projection of the first via structure 314 on the substrate substrate 311, as well as covers the gap between the first channel region 3121a and the second channel region 3122a, and the planar shape of the light-shielding layer 313 is stepped.
  • FIG. 31 is a schematic diagram of a planar structure of another display panel provided in at least one embodiment of the present disclosure
  • FIG. 32 is a schematic diagram of a cross-sectional structure of the first substrate shown in FIG. 31.
  • the first substrate 31 includes a base substrate 311 and a shielding layer stacked on the base substrate 311.
  • the second substrate 32 includes a black matrix 321, and the semiconductor layer 312 includes a first branch portion 3121 and a second branch portion 3122 that are arranged opposite to each other, and a connecting portion 3123 connecting the first branch portion 3121 and the second branch portion 3122, wherein the first branch portion 3121 includes a first channel region 3121a, and the second branch portion 3122 includes a second channel region 3122a.
  • the end of the first branch portion 3121 away from the connecting portion 3123 corresponds to the first via structure 314, that is, the first via structure 314 is provided on the side of the first branch portion 3121 away from the base substrate 311, and the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the end of the first branch portion 3121 away from the connecting portion 3123 on the base substrate 311.
  • the end of the second branch portion 3122 away from the connecting portion 3123 corresponds to the second via structure 315, that is, the side of the second branch portion 3122 away from the base substrate 311 has the second via structure 315, and the orthographic projection of the second via structure 315 on the base substrate 311 is located within the orthographic projection of the end of the second branch portion 3122 away from the connecting portion 3123 on the base substrate 311.
  • the orthographic projection of the light shielding layer 313 on the base substrate 311 is located within the orthographic projection of the black matrix 321 on the base substrate 311.
  • the orthographic projection of the light-shielding layer 313 on the base substrate 311 covers the orthographic projections of the first channel region 3121a and the first via structure 2126 on the base substrate 311.
  • the display panel 30 can reduce leakage current and enhance the retention capacity of the pixel capacitor by setting the light-shielding layer 213 to cover the entire area of the first channel region 3121a and the first via structure 314, but not covering the orthographic projection of the second channel region 3122a on the base substrate 311, thereby improving the flicker problem at low frequency and ensuring the aperture ratio of the display panel to be formed subsequently.
  • the distance between the second via structure 315 and the connection portion 3123 is greater than the distance between the first via structure 314 and the connection portion 3123 .
  • the first substrate 31 also includes a first metal layer 316 arranged on a side of the semiconductor layer 312 away from the base substrate 311, the first metal layer 316 includes a gate line 3161 extending in the second direction Y, the gate line 3161 is in a long strip shape, the gate line 3161 includes a first gate 3161a and a second gate 3161b, the orthographic projection of the first gate 3161a on the base substrate 311 overlaps with the orthographic projection of the first channel region 3121a on the base substrate 311, and the orthographic projection of the second gate 3161b on the base substrate 311 overlaps with the orthographic projection of the second channel region 3122a on the base substrate 311.
  • the black matrix 321 covers the lower left corner of the connecting portion 3123, that is, the black matrix 321 covers the portion of the connecting portion 3123 corresponding to the second branch portion 3122 on one side, so that the left side of the black matrix has two protrusions, and, although the data line is not shown in FIG19 , in the actual product, the black matrix 321 also covers the data line.
  • the black matrix also covers the touch signal line.
  • a first insulating layer is provided between the light shielding layer 313 and the semiconductor layer 312.
  • a gate insulating layer 317 is disposed between the first insulating layer 319 and the first metal layer 316
  • an interlayer insulating layer 318 is disposed on a side of the first metal layer 316 away from the substrate 311 .
  • the material of the light-shielding layer 313 includes a non-conductive light-shielding material or a conductive light-shielding material
  • the orthographic projection of the first via structure 314 on the base substrate 311 is located within the orthographic projection of the light-shielding layer 313 on the base substrate 311.
  • FIG33 is a schematic diagram of a planar structure of another display panel provided by at least one embodiment of the present disclosure.
  • the difference between the display panel shown in FIG33 and the display panel shown in FIG19 is that a touch signal line 320 extending along the first direction X is provided between the first branch portion 3121 and the second branch portion 3122, which can save space for wiring placement and make the display panel thinner and lighter.
  • the structure of the display panel shown in FIG33 can refer to the relevant description of the display panel shown in FIG19, and will not be repeated here.
  • the black matrix 321 also covers the touch signal line 320 .
  • FIG34 is a schematic diagram of a laminated structure of another display panel provided by at least one embodiment of the present disclosure.
  • the difference between the display panel shown in FIG34 and the display panel shown in FIG27 is that a touch signal line 320 extending along the first direction X is provided between the first branch portion 3121 and the second branch portion 3122, which can save space for wiring placement and make the display panel thinner and lighter.
  • the structure of the display panel shown in FIG34 can refer to the relevant description of the display panel shown in FIG27, and will not be repeated here.
  • the black matrix 321 also covers the touch signal line 320 .
  • FIG35 is a block diagram of a display panel provided by at least one embodiment of the present disclosure.
  • the display panel 30 includes the array substrate 21 in any of the above embodiments, that is, the first substrate 31.
  • the display panel 30 also includes a liquid crystal layer sandwiched between the first substrate 31 and the second substrate 32.
  • Other circuit structures included in the display panel can refer to conventional designs, and the embodiments of the present disclosure are not limited thereto.
  • FIG36 is a block diagram of a display device provided by at least one embodiment of the present disclosure.
  • the display device 500 includes the display panel 30 described in any one of the above items, and the display panel 30 includes the array substrate provided by any one of the above embodiments.
  • the display device 500 may be a display device with a display function.
  • the display device 500 may be a display, an OLED display panel, an OLED TV, a liquid crystal display panel, a liquid crystal display TV, a QLED display panel, a QLED TV, an electronic paper, a mobile phone, a tablet computer, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function and a touch function.
  • At least one embodiment of the present disclosure provides an array substrate, a display panel, and a display device having At least one of the following beneficial technical effects:
  • the array substrate provided in at least one embodiment of the present disclosure can reduce the leakage current of the display panel by adjusting the design of the light-shielding layer.
  • the light-shielding layer is designed to shield the first via structure, thereby improving the retention capacity of the pixel capacitor, thereby improving the flicker problem at low frequencies and ensuring the aperture ratio of the display panel.
  • the light-shielding layer is designed as an integral piece, and the light-shielding layer completely blocks the gap between the first branch portion and the second branch portion, that is, the light-shielding layer fully blocks the gap above the gate line, thereby reducing the leakage current of the thin film transistor without affecting the aperture ratio.
  • the edges of the light shielding layer are shrunk into the area covered by the black matrix, which can further improve the aperture ratio of the display panel.

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Abstract

本公开至少一实施例提供一种阵列基板、显示面板和显示装置，该阵列基板包括：层叠设置在衬底基板上的半导体层和遮光层，半导体层包括相对设置的第一分支部和第二分支部，连接第一分支部和第二分支部的连接部，第一分支部包括第一沟道区，第二分支部包括第二沟道区，在第一分支部的远离衬底基板的一侧具有第一过孔结构，第一过孔结构在衬底基板上的正投影位于第一分支部的远离连接部的端部在衬底基板上的正投影之内；遮光层在衬底基板上的正投影至少覆盖第一沟道区和第一过孔结构在衬底基板上的正投影，该阵列基板通过调整遮光层的设计可以减少漏电流现象，以提升像素电容的保持能力，并改善低频下闪烁的问题，还可以保证显示面板的开口率。

Description

阵列基板、显示面板和显示装置
本申请要求于2023年06月30日递交的中国专利申请第202310796827.7号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种阵列基板、显示面板和显示装置。
背景技术
低温多晶硅薄膜晶体管(Low-Temperature Polycrystalline Silicon Thin Film Transistor,LTPS TFT)技术已经日渐成熟，相比于非晶硅薄膜晶体管和金属氧化物薄膜晶体管，低温多晶硅薄膜晶体管具有更高的载流子迁移率，能够增强采用该低温多晶硅薄膜晶体管的显示器件的驱动能力，以降低功耗。目前的低温多晶硅薄膜晶体管的结构为顶栅结构(top gate structure)，在将低温多晶硅薄膜晶体管用于液晶显示面板时，需要设计遮光层对沟道区进行完全覆盖，否则低温多晶硅的沟道区会产生漏光的现象。
发明内容
本公开至少一实施例提供一种阵列基板、显示面板和显示装置，在该阵列基板中，遮光层在衬底基板上的正投影至少覆盖第一沟道区和第一过孔结构在衬底基板上的正投影，该阵列基板通过调整遮光层的设计可以减少后续形成的显示面板的漏电流，以提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
本公开至少一实施例提供一种阵列基板，该阵列基板包括衬底基板和层叠设置在所述衬底基板上的半导体层和遮光层，所述半导体层包括相对设置的第一分支部和第二分支部，以及连接所述第一分支部和所述第二分支部的连接部，所述第一分支部包括第一沟道区，所述第二分支部包括第二沟道区，在所述第一分支部的远离所述衬底基板的一侧具有第一过孔结构，且所述第一过孔结构在所述衬底基板上的正投影位于所述第一分支部的远离所述连接 部的端部在所述衬底基板上的正投影之内；所述遮光层在所述衬底基板上的正投影至少覆盖所述第一沟道区和所述第一过孔结构在所述衬底基板上的正投影。
例如，在本公开至少一实施例提供的阵列基板中，所述第二分支部的远离所述衬底基板的一侧具有第二过孔结构，且所述第二过孔结构在所述衬底基板上的正投影位于所述第二分支部的远离所述连接部的端部在所述衬底基板上的正投影之内，所述第二过孔结构与所述连接部之间的最小距离大于或者等于所述第一过孔结构与所述连接部之间的最小距离。
例如，在本公开至少一实施例提供的阵列基板中，所述第二过孔结构在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影之外。
例如，在本公开至少一实施例提供的阵列基板中，所述衬底基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分为一个整体结构。
例如，在本公开至少一实施例提供的阵列基板中，所述第一分支部和所述第二分支部均沿第一方向延伸，所述连接部沿与所述第一方向交叉的第二方向延伸，所述第一分支部、所述第二分支部和所述连接部围设形成开口区域，所述遮光层覆盖至少部分所述开口区域。
例如，本公开至少一实施例提供的阵列基板还包括设置在所述半导体层的远离所述衬底基板的一侧的第一金属层，所述第一金属层包括在所述第二方向上延伸的栅线，所述栅线包括第一栅极和第二栅极，所述第一栅极在所述衬底基板上的正投影和所述第一沟道区在所述衬底基板上的正投影交叠，所述第二栅极在所述衬底基板上的正投影和所述第二沟道区在所述衬底基板上的正投影交叠。
例如，在本公开至少一实施例提供的阵列基板中，在所述第一方向上所述遮光层和所述连接部之间具有间隙。
例如，在本公开至少一实施例提供的阵列基板中，所述衬底基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分分别为第一子遮光部和第二子遮光部，且所述第一子遮光部和所述第二子遮光部相互间隔。
例如，在本公开至少一实施例提供的阵列基板中，所述第一过孔结构在所述衬底基板上的正投影位于所述第一子遮光部在所述衬底基板上的正投影内，所述第二过孔结构在所述衬底基板上的正投影位于所述第二子遮光部在所述衬底基板上的正投影之外。
本公开至少一实施例还提供一种显示面板，该显示面板包括相对设置的第一基板和第二基板，其中，所述第一基板包括衬底基板和层叠设置在所述衬底基板上的半导体层和遮光层；所述第二基板包括黑矩阵；所述半导体层包括相对设置的第一分支部和第二分支部，以及连接所述第一分支部和所述第二分支部的连接部，所述第一分支部包括第一沟道区，所述第二分支部包括第二沟道区，在所述第一分支部的远离所述衬底基板的一侧具有第一过孔结构，且所述第一过孔结构在所述衬底基板上的正投影位于所述第一分支部的远离所述连接部的端部在所述衬底基板上的正投影之内；所述遮光层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影之内，且至少覆盖所述第一沟道区和所述第一过孔结构在所述衬底基板上的正投影。
例如，在本公开至少一实施例提供的显示面板中，所述第二分支部的远离所述连接部的端部对应第二过孔结构，所述第二过孔结构相对于所述第一过孔结构更远离所述连接部。
例如，在本公开至少一实施例提供的显示面板中，所述遮光层的材料包括导电金属，所述黑矩阵在所述衬底基板上的正投影覆盖所述第二过孔结构在所述衬底基板上的正投影，且所述第二过孔结构在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影之外。
例如，在本公开至少一实施例提供的显示面板中，所述第一基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分为一个整体结构。
例如，在本公开至少一实施例提供的显示面板中，所述第一分支部和所述第二分支部均沿第一方向延伸，所述连接部沿与所述第一方向交叉的第二方向延伸，所述第一分支部、所述第二分支部和所述连接部围设形成开口区域，所述遮光层覆盖至少部分所述开口区域。
例如，在本公开至少一实施例提供的显示面板中，所述第一基板还包括设置在所述半导体层的远离所述衬底基板的一侧的第一金属层，所述第一金属 层包括在所述第二方向上延伸的栅线，所述栅线包括第一栅极和第二栅极，所述第一栅极在所述衬底基板上的正投影和所述第一沟道区在所述衬底基板上的正投影交叠，所述第二栅极在所述衬底基板上的正投影和所述第二沟道区在所述衬底基板上的正投影交叠。
例如，在本公开至少一实施例提供的显示面板中，所述第一栅极在所述衬底基板上的正投影在所述黑矩阵在所述衬底基板上的正投影之内，所述第二栅极在所述衬底基板上的正投影在所述黑矩阵在所述衬底基板上的正投影之内。
例如，在本公开至少一实施例提供的显示面板中，在所述第一方向上所述遮光层和所述连接部之间具有间隙。
例如，在本公开至少一实施例提供的显示面板中，所述遮光层的对应所述第一分支部的部分的靠近所述连接部的边缘在所述衬底基板上的正投影与所述黑矩阵的对应所述第一分支部的部分的靠近所述连接部的边缘在所述衬底基板上的正投影交叠。
例如，在本公开至少一实施例提供的显示面板中，所述遮光层的对应所述第一分支部的部分的最远离所述连接部的边缘在所述衬底基板上的正投影和所述黑矩阵的对应所述第一分支部的部分的最远离所述连接部的边缘在所述衬底基板上的正投影相交叠。
例如，在本公开至少一实施例提供的显示面板中，所述遮光层的远离所述连接部的边在所述衬底基板上的正投影包括位于所述第一过孔结构的远离所述连接部的一侧的第一部分和位于所述第二过孔结构的远离所述连接部的一侧的第二部分，所述第二部分在所述衬底基板上的正投影位于所述黑矩阵的最远离所述第二过孔结构的边在所述衬底基板上的正投影之内。
例如，在本公开至少一实施例提供的显示面板中，所述第一基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分分别为第一子遮光部和第二子遮光部，且所述第一子遮光部和所述第二子遮光部相互间隔。
例如，在本公开至少一实施例提供的显示面板中，所述第一过孔结构在所述衬底基板上的正投影位于所述第一子遮光部在所述衬底基板上的正投影内，所述第二过孔结构在所述衬底基板上的正投影位于所述第二子遮光部在所述 衬底基板上的正投影之外。
例如，在本公开至少一实施例提供的显示面板中，所述第二分支部的远离所述连接部的端部对应第二过孔结构，所述第二过孔结构和所述连接部之间的最大距离等于所述第一过孔结构和所述连接部之间的最大距离。
例如，在本公开至少一实施例提供的显示面板中，所述遮光层的材料包括非导电遮光材料，所述黑矩阵在所述衬底基板上的正投影和所述遮光层在所述衬底基板上的正投影均覆盖所述第二过孔结构在所述衬底基板上的正投影。
例如，在本公开至少一实施例提供的显示面板中，所述第一基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分为整体结构或者为相互间隔的结构。
本公开至少一实施例还提供一种显示装置，该显示装置包括上述任一实施例所述的阵列基板，或者如上任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1为一种薄膜晶体管的平面结构示意图；
图2为一种阵列基板的截面结构示意图；
图3为图1中的薄膜晶体管的截面结构示意图；
图4为本公开至少一实施例提供的一种阵列基板和黑矩阵的平面结构示意图；
图5为本公开至少一实施例提供的一种阵列基板的叠层结构示意图；
图6为本公开至少一实施例提供的再一种阵列基板的叠层结构示意图；
图7为本公开至少一实施例提供的又一种阵列基板的叠层结构示意图；
图8为图7中阵列基板的截面结构示意图；
图9为本公开至少一实施例提供的又一种阵列基板的平面结构示意图；
图10为图9所示阵列基板的截面结构示意图；
图11为本公开至少一实施例提供的又一种阵列基板的平面结构示意图；
图12为图11所示阵列基板的截面结构示意图；
图13为本公开至少一实施例提供的又一种阵列基板的平面结构示意图；
图14为图13所示阵列基板的截面结构示意图；
图15为本公开至少一实施例提供的又一种阵列基板的叠层结构示意图；
图16为本公开至少一实施例提供的又一种阵列基板的叠层结构示意图；
图17为本公开至少一实施例提供的又一种阵列基板的叠层结构示意图；
图18为本公开至少一实施例提供的一种显示面板的截面结构示意图；
图19为本公开至少一实施例提供的一种显示面板的平面结构示意图；
图20为本公开至少一实施例提供的一种第一基板的截面结构示意图；
图21为本公开至少一实施例提供的另一种显示面板的平面结构示意图；
图22为图21中第一基板的截面结构示意图；
图23为本公开至少一实施例提供的又一种显示面板的平面结构示意图；
图24为图23中第一基板的截面结构示意图；
图25为本公开至少一实施例提供的又一种显示面板的平面结构示意图；
图26为图25中第一基板的截面结构示意图；
图27为本公开至少一实施例提供的又一种显示面板的平面结构示意图；
图28为图27中第一基板的截面结构示意图；
图29为本公开至少一实施例提供的又一种显示面板的平面结构示意图；
图30为图29所示第一基板的截面结构示意图；
图31为本公开至少一实施例提供的又一种显示面板的平面结构示意图；
图32为图31所示第一基板的截面结构示意图；
图33为本公开至少一实施例提供的又一种显示面板的平面结构示意图；
图34为本公开至少一实施例提供的又一种显示面板的叠层结构示意图；
图35为本公开至少一实施例提供的一种显示面板的框图；以及
图36为本公开至少一实施例提供的一种显示装置的框图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
除非另外定义，本发明实施例中使用的“平行”、“垂直”和“相同”等特征均包括严格意义上的“平行”、“垂直”、“相同”等情况，以及“大致平行”、“大致垂直”、“大致相同”等包含一定误差的情况。例如，上述的“大致”可表示所比较的对象的差值为所比较的对象的平均值的10％，或者5％之内。在本发明实施例的下文中没有特别指出一个部件或元件的数量时，意味着该部件或元件可以是一个也可以是多个，或可理解为至少一个。“至少一个”指一个或多个，“多个”指至少两个。本发明实施例中的“同层设置”指同一材料在经过同一步骤(例如，一步图案化工艺)后形成的多个膜层之间的关系。这里的“同层”并不总是指多个膜层的厚度相同或者多个膜层在截面图中的高度相同。
目前，手机、平板电脑和笔记本电脑等移动设备对低功耗的要求越来越高，降低显示面板的刷新频率成为降低显示面板的功耗的主要方法。在显示面板进行低刷新频率时，像素电容的保持时间加长，当薄膜晶体管的漏电流(简称Ioff)较大时，像素电容的保持能力下降，像素电极与公共电极之间的电压差会下降，从而会造成显示面板的亮度衰减，进而导致像素的闪烁问题加重，同时残像等光学效果也会因为漏电流问题的加重而变差。
例如，图1为一种薄膜晶体管的平面结构示意图，图2为一种阵列基板的截面结构示意图，结合图1和图2，在像素电极11和薄膜晶体管的第一源漏电极12之间设置有层间绝缘层13，在该层间绝缘层13中设置有第一过孔结构14，为了防止第一过孔结构14漏光，需要将黑矩阵15(图2中未示出)设置成遮挡第一过孔结构14，这样在第一方向X上，在黑矩阵15的对应第一过孔结构14的右侧部分，黑矩阵15对沟道区16的上侧(栅线17覆盖区 域的上侧)的遮挡部分的长度L1大于对沟道区16的下侧(栅线17覆盖区域的下侧)的遮挡部分的长度L2，所以黑矩阵15对于沟道区16在第一方向X的两侧的遮挡范围不一致，黑矩阵15对沟道区16的上侧部分的遮挡面积大于对沟道区16下侧部分的遮挡面积。背光从低温多晶硅薄膜晶体管所在侧入射，在一定的光照条件下，沟道区16中会激发光生载流子，从而导致光照条件下薄膜晶体管的漏电流(Ioff)增大，即光照强度和薄膜晶体管的漏电流Ioff呈正相关。在沟道区16的靠近衬底基板10的一侧设置有遮光层18，遮光层18可以降低沟道区16接收到的光照，从而可以降低光照条件下的漏电流，在遮光层18和沟道区16之间设置有第一绝缘层22，在第一绝缘层22和第一源漏电极12之间设置有钝化层23。第二源漏电极21和第一源漏电极12相对设置，且在第二源漏电极21和第一源漏电极12之间的空隙中形成栅极和栅绝缘层20，显示面板通过行扫描的方式进行显示，像素在一帧的时间内只有几微秒的时间在充电，其余时间均处于电压的保持阶段。在理想的条件下，像素电压始终保持着设定的电压，但由于薄膜晶体管中漏电流的存在，电压保持阶段会有电压的衰减，电压的衰减程度和薄膜晶体管的漏电流Ioff以及电压保持时间呈正相关，且漏电流压降的公式为△V＝Ioff*Thold/Cst。在显示面板进行低频显示的情况下，在一帧时间加长(刷新频率为60Hz时，1帧时间为16.7ms；刷新频率为15Hz时，1帧时间为66.7ms)，像素电压的保持时间加长，且漏电流速度相同的前提下，低刷新频率下漏电流导致的电压衰减会增加，像素的亮度衰减也会增加，从而闪烁的问题会加重。
例如，图3为图1中的薄膜晶体管的截面结构示意图，如图3所示，两个间隔设置的遮光层18对两个沟道区16分别进行遮挡，每个遮光层18对对应的沟道区16的整体进行遮挡，且相邻的两个遮光层18对称设计。例如，如图1所示，在一个示例中，在第一方向X上，遮光层18在栅线17的上侧的遮挡长度L3为2.05微米，在栅线17的下侧的遮挡长度L4也为2.05微米，这样在栅线17的下侧一部分遮光层18已经超出了黑矩阵15的遮挡范围，进入了开口区，会导致后续形成的显示面板的像素的开口率降低，例如，相对于遮光层18没有进入开口区的情形，像素的开口率会下降0.8％。遮光层18对双栅结构的薄膜晶体管的两个栅极也分开进行遮挡，这样遮光层18对两个沟道区16之间的间隔区域没有进行遮挡，对于每个沟道区16，在与第一方向X垂直的第二方向Y上遮光层18遮挡沟道区16之外的间隔区域的距离L5较 小，例如，在一个示例中，该距离L5的大小只有1.5微米，在第一方向X上在栅线17的上侧遮光层18对间隔区域遮挡的长度L3为2.05微米，该长度L3也较小，从而导致薄膜晶体管的漏电流(Ioff)较大，这样在低刷新频率下对闪烁等光效的影响较大。
需要说明的是，在图3所示的截面结构中，第三方向Z垂直于第一方向X和第二方向Y所在的平面，即第三方向Z为垂直于衬底基板10的主表面的方向。
本公开的发明人注意到，可以将薄膜晶体管的对应两个栅极的沟道区通过一整块遮光层或者较大面积的间隔设置的遮光层进行遮挡，并且将与像素电极连接的第一源漏电极的一侧的遮光层的遮挡面积增大，即采用遮光层将上述层间绝缘层中的第一过孔结构进行遮挡，可以减少后续形成的显示面板的漏电流现象。
本公开至少一实施例提供一种阵列基板，该阵列基板包括衬底基板和层叠设置在衬底基板上的半导体层和遮光层，半导体层包括相对设置的第一分支部和第二分支部，以及连接第一分支部和第二分支部的连接部，第一分支部包括第一沟道区，第二分支部包括第二沟道区，在第一分支部的远离衬底基板的一侧具有第一过孔结构，且第一过孔结构在衬底基板上的正投影位于第一分支部的远离连接部的端部在衬底基板上的正投影之内；遮光层在衬底基板上的正投影至少覆盖第一沟道区和第一过孔结构在衬底基板上的正投影，该阵列基板通过调整遮光层的设计可以减少后续形成的显示面板的漏电流，以提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，图4为本公开至少一实施例提供的一种阵列基板和黑矩阵的平面结构示意图，如图4所示，该阵列基板21包括衬底基板211和层叠设置在衬底基板211上的半导体层212和遮光层213，半导体层212包括相对设置的第一分支部2121和第二分支部2122，以及连接第一分支部2121和第二分支部2122的连接部2123，第一分支部2121包括第一沟道区2124，第二分支部2122包括第二沟道区2125，在第一分支部2121的远离衬底基板211的一侧具有第一过孔结构2126，且第一过孔结构2126在衬底基板211上的正投影位于第一分支部2121的远离连接部2123的端部在衬底基板211上的正投影之内；遮光层213在衬底基板211上的正投影至少覆盖第一沟道区2124和第一过孔结 构2126在衬底基板211上的正投影，该阵列基板21通过调整遮光层213的设计可以减少后续形成的显示面板的漏电流，以提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
需要说明的是，半导体层是在制作阵列基板的过程中的一种状态，后续还有其他工艺把部分半导体区域进行了导体化，也就是在形成后续提及的栅极和栅线之后具有重掺杂的步骤，把半导体层的被栅极覆盖区域之外的部分变成导体，使得栅极能够遮挡沟道区，因此，位于栅线下方的是半导体层对应的沟道区，被导体化的部分对应第一源漏电极和第二源漏电极。
例如，如图4所示，在该阵列基板21中示出了第一沟道区2124和第二沟道区2125这两个沟道区。第一分支部2121的对应第一过孔结构2126的端部(第一源漏电极)通过第一过孔结构2126和像素电极222电连接，第二分支部2122的端部(第二源漏电极)和数据线221连接，该数据线221和栅线2128相交限定像素区域，在像素区域中设置有像素电极222。
需要说明的是，为了体现阵列基板上遮光层和半导体层等与黑矩阵的位置关系，在图4中也示出了黑矩阵223，该黑矩阵223在衬底基板211上的正投影覆盖数据线221、栅线2128、遮光层213、第一分支部2121、第二分支部2122和连接部2123的右下角部分在衬底基板211上的正投影，但在描述阵列基板时没有提及黑矩阵223。
例如，如图4所示，该阵列基板21还包括触控信号线224，该触控信号线224包括和数据线221平行设置的第一部分224a和第二部分224b，该黑矩阵223在衬底基板211上的正投影也覆盖该触控信号线224在衬底基板211上的正投影。
例如，图5为本公开至少一实施例提供的一种阵列基板的叠层结构示意图，如图5所示，该阵列基板21包括衬底基板211和层叠设置在衬底基板211上的半导体层212和遮光层213，半导体层212包括相对设置的第一分支部2121和第二分支部2122，以及连接第一分支部2121和第二分支部2122的连接部2123，第一分支部2121包括第一沟道区2124，第二分支部2122包括第二沟道区2125，在第一分支部2121的远离衬底基板211的一侧具有第一过孔结构2126，且第一过孔结构2126在衬底基板211上的正投影位于第一分支部2121的远离连接部2123的端部在衬底基板211上的正投影之内；遮光层213 在衬底基板211上的正投影至少覆盖第一沟道区2124和第一过孔结构2126在衬底基板211上的正投影，该阵列基板21通过调整遮光层213的设计可以减少后续形成的显示面板的漏电流，以提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，如图5所示，第二分支部2122的远离衬底基板211的一侧具有第二过孔结构2127，且第二过孔结构2127在衬底基板211上的正投影位于第二分支部2122的远离连接部2123的端部在衬底基板211上的正投影之内，第二过孔结构2127与连接部2123之间的最小距离大于第一过孔结构2126与连接部2123之间的最小距离，即第二过孔结构2127相对于第一过孔结构2126更远离连接部2123。在其他的示例中，也可以是第二过孔结构2127与连接部2123之间的最小距离等于第一过孔结构2126与连接部2123之间的最小距离。
例如，如图5所示，该第二过孔结构2127在衬底基板211上的正投影位于遮光层213在衬底基板211上的正投影之外，即遮光层213没有对第二过孔结构2127进行覆盖。
例如，在一个示例中，衬底基板211上设置有多个薄膜晶体管，遮光层213的对应于不同的薄膜晶体管的部分相互间隔，遮光层213的对应于同一个薄膜晶体管的第一沟道区2124和第二沟道区2125的部分为一个整体结构，即遮光层213除了覆盖第一沟道区2124和第二沟道区2125之外，还覆盖第一沟道区2124和第二沟道区2125之间的部分。
例如，如图5所示，第一分支部2121和第二分支部2122均沿第一方向X延伸，连接部2123沿与第一方向X交叉的第二方向Y延伸，第一分支部2121、第二分支部2122和连接部2123围设形成开口区域，遮光层213覆盖至少部分该开口区域。
例如，在一个示例中，该第一方向X和第二方向Y垂直。
例如，如图5所示，该阵列基板21还包括设置在半导体层212的远离衬底基板211的一侧的第一金属层214，第一金属层214包括在第二方向Y上延伸的栅线2128，栅线2128在衬底基板211上的正投影和第一沟道区2124在衬底基板211上的正投影以及第二沟道区2125在衬底基板211上的正投影均交叠。
例如，如图5所示，在第一方向X上遮光层213和连接部2123之间具有间隙，即遮光层213的下边缘位于连接部2123的上边缘之上。
例如，图6为本公开至少一实施例提供的再一种阵列基板的叠层结构示意图，在一个示例中，该衬底基板211上设置有多个薄膜晶体管，遮光层213的对应于不同的薄膜晶体管的部分相互间隔，遮光层213的对应于同一个薄膜晶体管的第一沟道区2124和第二沟道区2125的部分分别为第一子遮光部213a和第二子遮光部213b，且第一子遮光部213a和第二子遮光部213b相互间隔。从图6中可以看出，第二子遮光部213b的最远离连接部2123的边与连接部2123之间的距离大于第一子遮光部213a的最远离连接部2123的边与连接部2123之间的距离。
例如，如图6所示，在第二分支部2122的远离连接部2123的端部对应第二过孔结构2127，该第二过孔结构2127相对于第一过孔结构2126更远离连接部2123，即在图6所示的平面图中，第一分支部2121和第二分支部2122均呈长条形，且均在第一方向X上延伸，而且第二分支部2122在第一方向X上的长度大于第一分支部2121在第一方向X上的长度，即在第一方向X上，第二过孔结构2127与连接部2123之间的距离大于第一过孔结构2126与连接部2123之间的距离，从而使得对应于第二分支部2122的端部的第二过孔结构2127和对应于第一分支部2121的端部的第一过孔结构2126不是平齐的。
例如，如图6所示，该第一子遮光部213a覆盖第一沟道区2124和第一过孔结构2126在衬底基板211上的正投影，第二子遮光部213b覆盖第二沟道区2125在衬底基板211上的正投影，但没有覆盖第二过孔结构2127在衬底基板211上的正投影。该阵列基板21通过将第一子遮光部213a设计成覆盖第一沟道区2124和第一过孔结构2126在衬底基板211上的正投影，将第二子遮光部213b设计成覆盖第二沟道区2125在衬底基板211上的正投影，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，如图6所示，第一过孔结构2126在衬底基板211上的正投影位于第一子遮光部213a在衬底基板211上的正投影内，第二过孔结构2127在衬底基板211上的正投影位于第二子遮光部213b在衬底基板211上的正投影之外。
例如，图7为本公开至少一实施例提供的又一种阵列基板的叠层结构示意图，图8为图7中阵列基板的截面结构示意图，例如，结合图7和图8，该阵列基板21包括衬底基板211和层叠设置在衬底基板211上的遮光层213和 半导体层212。半导体层212包括相对设置的第一分支部2121和第二分支部2122，以及连接第一分支部2121和第二分支部2122的连接部2123，该第一分支部2121包括第一沟道区2124，第二分支部2122包括第二沟道区2125，第一分支部2121的远离连接部2123的端部对应第一过孔结构2126，即第一分支部2121的远离衬底基板211的一侧具有第一过孔结构2126，且第一过孔结构2126在衬底基板211上的正投影位于第一分支部2121的远离连接部2123的端部在衬底基板211上的正投影之内。第二分支部2122的远离连接部2123的端部对应第二过孔结构2127，即第二分支部2122的远离衬底基板211的一侧具有第二过孔结构2127，且第二过孔结构2127在衬底基板211上的正投影位于第二分支部2122的远离连接部2123的端部在衬底基板211上的正投影之内。遮光层213在衬底基板211上的正投影覆盖第一沟道区2124、第二沟道区2125、第一过孔结构2126和第二过孔结构2127在衬底基板211上的正投影，该阵列基板21通过将遮光层213设置成覆盖第一沟道区2124、第二沟道区2125、第一过孔结构2126和第二过孔结构2127的全部区域，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，结合图7，在第一方向X上，该第二过孔结构2127相对于第一过孔结构2126更远离连接部2123，即在图7所示的平面图中，第一分支部2121和第二分支部2122均呈长条形，且均在第一方向X上延伸，而且第二分支部2122在第一方向X上的长度大于第一分支部2121在第一方向X上的长度，即在第一方向X上，第二过孔结构2127与连接部2123之间的距离大于第一过孔结构2126与连接部2123之间的距离，从而使得对应于第二分支部2122的端部的第二过孔结构2127和对应于第一分支部2121的端部的第一过孔结构2126不是平齐的。
例如，结合图7和图8，该阵列基板21还包括设置在半导体层212的远离衬底基板211的一侧的第一金属层214，第一金属层214包括在第二方向Y上延伸的栅线2128，栅线2128呈长条形，栅线2128包括第一栅极2128a和第二栅极2128b，第一栅极2128a在衬底基板211上的正投影和第一沟道区2124在衬底基板211上的正投影交叠，第二栅极2128b在衬底基板211上的正投影和第二沟道区2125在衬底基板211上的正投影交叠。
例如，第一栅极2128a、第二栅极2128b和栅线2128是一体的直线型结 构，第一栅极2128a和第二栅极2128b是栅线2128的一部分，第一栅极2128a为栅线2128的对应第一沟道区2124的部分，第二栅极2128b为栅线2128的对应第二沟道区2125的部分。
例如，如图8所示，在遮光层213和半导体层212之间设置有第一绝缘层219，在第一绝缘层219和第一金属层214之间设置有栅绝缘层217，在第一金属层214的远离衬底基板211的一侧设置有层间绝缘层218。
例如，如图7和图8所示，该遮光层213的远离连接部2123的边在衬底基板211上的正投影包括位于第一过孔结构2124的远离连接部2123的一侧的第一部分213c和位于第二过孔结构2127的远离连接部2123的一侧的第二部分213d，第一部分213c的上边缘和第二部分213d的上边缘不在同一条直线上，即该遮光层213的平面形状为台阶状。在第一方向X上，第一部分213c和连接部2123之间的距离大于第二部分213d和连接部2123之间的距离。第二过孔结构2127在衬底基板211上的正投影位于遮光层213在衬底基板211上的正投影之内。需要说明的是，在该示例中，该遮光层213的材料为非导电遮光材料，当该遮光层213的材料为非导电遮光材料时，即使出现对层间绝缘层218进行刻蚀过刻到遮光层213的现象时，也不会出现薄膜晶体管的第一源漏电极和第二源漏电极短路的问题。
例如，图9为本公开至少一实施例提供的又一种阵列基板的平面结构示意图，图10为图9所示阵列基板的截面结构示意图，例如，结合图9和图10，该阵列基板21包括衬底基板211和层叠设置在衬底基板211上的遮光层213和半导体层212。半导体层212包括相对设置的第一分支部2121和第二分支部2122，以及连接第一分支部2121和第二分支部2122的连接部2123，该第一分支部2121包括第一沟道区2124，第二分支部2122包括第二沟道区2125，第一分支部2121的远离连接部2123的端部对应第一过孔结构2126，即第一分支部2121的远离衬底基板211的一侧具有第一过孔结构2126，且第一过孔结构2126在衬底基板211上的正投影位于第一分支部2121的远离连接部2123的端部在衬底基板211上的正投影之内。第二分支部2122的远离连接部2123的端部对应第二过孔结构2127，即第二分支部2122的远离衬底基板211的一侧具有第二过孔结构2127，且第二过孔结构2127在衬底基板211上的正投影位于第二分支部2122的远离连接部2123的端部在衬底基板211上的正投影之内。遮光层213在衬底基板211上的正投影覆盖第一沟道区2124、第 二沟道区2125、第一过孔结构2126和第二过孔结构2127在衬底基板211上的正投影，该阵列基板21通过将遮光层213设置成覆盖第一沟道区2124、第二沟道区2125、第一过孔结构2126和第二过孔结构2127的全部区域，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，结合图9，在第二分支部2122的远离连接部2123的端部对应第二过孔结构2127，在第一方向X上，该第二过孔结构2127和连接部2123之间的距离等于第一过孔结构2124和连接部2123之间的距离，即在图9所示的平面图中，第一分支部2121和第二分支部2122均呈长条形，且均在第一方向X上延伸，而且第二分支部2122在第一方向X上的长度等于第一分支部2121在第一方向X上的长度，从而使得对应于第二分支部2122的端部的第二过孔结构2127和对应于第一分支部2121的端部的第一过孔结构2124是平齐的。
例如，结合图9和图10，该阵列基板21还包括设置在半导体层212的远离衬底基板211的一侧的第一金属层214，第一金属层214包括在第二方向Y上延伸的栅线2128，栅线2128呈长条形，栅线2128包括第一栅极2128a和第二栅极2128b，第一栅极2128a在衬底基板211上的正投影和第一沟道区2124在衬底基板211上的正投影交叠，第二栅极2128b在衬底基板211上的正投影和第二沟道区2125在衬底基板211上的正投影交叠。例如，第一栅极2128a、第二栅极2128b和栅线2128是一体的直线型结构，第一栅极2128a和第二栅极2128b是栅线2128的一部分，第一栅极2128a为栅线2128的对应第一沟道区2124的部分，第二栅极2128b为栅线2128的对应第二沟道区2125的部分。
例如，如图10所示，在遮光层213和半导体层212之间设置有第一绝缘层219，在第一绝缘层219和第一金属层214之间设置有栅绝缘层217，在第一金属层214的远离衬底基板211的一侧设置有层间绝缘层218。
例如，结合图9和图10，在一个示例中，该遮光层213的材料包括非导电遮光材料，第一过孔结构2126和第二过孔结构2127在衬底基板211上的正投影均位于遮光层213在衬底基板211上的正投影之内。
例如，结合图9和图10，该遮光层213为一个整体结构，且该遮光层213在衬底基板211上的正投影覆盖第一沟道区2124在衬底基板211上的正投 影、第二沟道区2125在衬底基板211上的正投影、第一过孔结构2126在衬底基板211上的正投影和第二过孔结构2127在衬底基板211上的正投影，以及覆盖第一沟道区2124和第二沟道区2125之间的间隙，并且覆盖第一过孔结构2126和第二过孔结构2127之间的间隙。
例如，图11为本公开至少一实施例提供的又一种阵列基板的平面结构示意图，图12为图11所示阵列基板的截面结构示意图，例如，结合图11和图12，该阵列基板21包括衬底基板211和层叠设置在衬底基板211上的遮光层213和半导体层212。半导体层212包括相对设置的第一分支部2121和第二分支部2122，以及连接第一分支部2121和第二分支部2122的连接部2123，该第一分支部2121包括第一沟道区2124，第二分支部2122包括第二沟道区2125，第一分支部2121的远离连接部2123的端部对应第一过孔结构2126，即第一分支部2121的远离衬底基板211的一侧具有第一过孔结构2126，且第一过孔结构2126在衬底基板211上的正投影位于第一分支部2121的远离连接部2123的端部在衬底基板211上的正投影之内。遮光层213的对应于不同的薄膜晶体管的部分相互间隔，该遮光层213的对应于同一个薄膜晶体管的第一沟道区2124和第二沟道区2125的部分分别为第一子遮光部213a和第二子遮光部213b，且该第一子遮光部213a和第二子遮光部213b相互间隔。该第一子遮光部213a覆盖第一沟道区2124和第一过孔结构2126在衬底基板211上的正投影，第二子遮光部213b覆盖第二沟道区2125和第二过孔结构2127在衬底基板211上的正投影。该阵列基板21通过将第一子遮光部213a设计成第一子遮光部213a在衬底基板211上的正投影覆盖第一沟道区2124和第一过孔结构2126在衬底基板211上的正投影，将第二子遮光部213b设计成第二子遮光部213b在衬底基板211上的正投影覆盖第二沟道区2125和第二过孔结构2127在衬底基板211上的正投影，该种设计可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，结合图11，在第二分支部2122的远离连接部2123的端部对应第二过孔结构2127，该第二过孔结构2127相对于第一过孔结构2126更远离连接部2123，即在图11所示的平面图中，第一分支部2121和第二分支部2122均呈长条形，且均在第一方向X上延伸，第二分支部2122在第一方向X上的长度等于第一分支部2121在第一方向X上的长度，即在第一方向X上， 第二过孔结构2127与连接部2123之间的距离等于第一过孔结构2126与连接部2123之间的距离，从而使得对应于第二分支部2122的端部的第二过孔结构2127和对应于第一分支部2121的端部的第一过孔结构2126是平齐的。
例如，结合图11和图12，该阵列基板21还包括设置在半导体层212的远离衬底基板211的一侧的第一金属层214，第一金属层214包括在第二方向Y上延伸的栅线2128，栅线2128呈长条形，栅线2128包括第一栅极2128a和第二栅极2128b，第一栅极2128a在衬底基板211上的正投影和第一沟道区2124在衬底基板211上的正投影交叠，第二栅极2128b在衬底基板211上的正投影和第二沟道区2125在衬底基板211上的正投影交叠。
例如，第一栅极2128a、第二栅极2128b和栅线2128是一体的直线型结构，第一栅极2128a和第二栅极2128b是栅线2128的一部分，第一栅极2128a为栅线2128的对应第一沟道区2124的部分，第二栅极2128b为栅线2128的对应第二沟道区2125的部分。
例如，如图12所示，在遮光层213和半导体层212之间设置有第一绝缘层219，在第一绝缘层219和第一金属层214之间设置有栅绝缘层217，在第一金属层214的远离衬底基板211的一侧设置有层间绝缘层218。
例如，如图11和图12所示，该第一子遮光部213a的远离连接部2123的边在衬底基板211上的正投影包括位于第一过孔结构2126的远离连接部2123的一侧的第一部分213c，第二子遮光部213b的远离连接部2123的边在衬底基板211上的正投影包括位于第二过孔结构2127的远离连接部2123的一侧的第二部分213d，即该第一子遮光部213a和第二子遮光部213b的平面形状均为长条形，且第一子遮光部213a的长度等于第二子遮光部213b的长度。在第一方向X上，第一部分213c和连接部2123之间的距离等于第二部分213d和连接部2123之间的距离。第二过孔结构2127在衬底基板211上的正投影位于遮光层213在衬底基板211上的正投影之内。需要说明的是，在该示例中，该遮光层213的材料为非导电遮光材料，即使出现对层间绝缘层218进行刻蚀过刻到遮光层213的现象时，也不会出现薄膜晶体管的第一源漏电极和第二源漏电极短路的问题。
例如，该阵列基板21上设置有多个薄膜晶体管，遮光层213的对应于不同的薄膜晶体管的部分相互间隔，结合图11和图12，该遮光层213的对应于同一个薄膜晶体管的第一沟道区2124和第二沟道区2125的部分分别为第一 子遮光部213a和第二子遮光部213b，且该第一子遮光部213a和第二子遮光部213b相互间隔，第一沟道区2124在衬底基板211上的正投影完全位于第一子遮光部213a在衬底基板211上的正投影之内，第二沟道区2125在衬底基板211上的正投影完全位于第二子遮光部213b在衬底基板211上的正投影之内。该第一过孔结构2126在衬底基板211上的正投影位于第一子遮光部213a在衬底基板211上的正投影内，且第二过孔结构2127在衬底基板211上的正投影位于第二子遮光部213b在衬底基板211上的正投影之内。
例如，图13为本公开至少一实施例提供的又一种阵列基板的平面结构示意图，图14为图13所示阵列基板的截面结构示意图，如图13所示，该阵列基板21包括衬底基板211和层叠设置在衬底基板211上的遮光层213和半导体层212。半导体层212包括相对设置的第一分支部2121和第二分支部2122，以及连接第一分支部2121和第二分支部2122的连接部2123，该第一分支部2121包括第一沟道区2124，第二分支部2122包括第二沟道区2125，第一分支部2121的远离连接部2123的端部对应第一过孔结构2126，即第一分支部2121的远离衬底基板211的一侧具有第一过孔结构2126，且第一过孔结构2126在衬底基板211上的正投影位于第一分支部2121的远离连接部2123的端部在衬底基板211上的正投影之内。第二分支部2122的远离连接部2123的端部对应第二过孔结构2127，即第二分支部2122的远离衬底基板211的一侧具有第二过孔结构2127，且第二过孔结构2127在衬底基板211上的正投影位于第二分支部2122的远离连接部2123的端部在衬底基板211上的正投影之内。遮光层213在衬底基板211上的正投影覆盖第一沟道区2124、第二沟道区2125和第一过孔结构2126在衬底基板311上的正投影，该阵列基板21通过将遮光层213设置成覆盖第一沟道区2124、第二沟道区2125和第一过孔结构2126的全部区域，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，如图13所示，在第一方向X上，该第二过孔结构2127和连接部2123之间的距离等于第一过孔结构2124和连接部2123之间的距离，即在图13所示的平面图中，第一分支部2121和第二分支部2122均呈长条形，且均在第一方向X上延伸，而且第二分支部2122在第一方向X上的长度等于第一分支部2121在第一方向X上的长度，从而使得对应于第二分支部2122的 端部的第二过孔结构2127和对应于第一分支部2121的端部的第一过孔结构2124是平齐的。
例如，如图13所示，该阵列基板21还包括设置在半导体层212的远离衬底基板211的一侧的第一金属层214，第一金属层214包括在第二方向Y上延伸的栅线2128，栅线2128呈长条形，栅线2128包括第一栅极2128a和第二栅极2128b，第一栅极2128a在衬底基板211上的正投影和第一沟道区2124在衬底基板211上的正投影交叠，第二栅极2128b在衬底基板211上的正投影和第二沟道区2125在衬底基板211上的正投影交叠。
例如，第一栅极2128a、第二栅极2128b和栅线2128是一体的直线型结构，第一栅极2128a和第二栅极2128b是栅线2128的一部分，第一栅极2128a为栅线2128的对应第一沟道区2124的部分，第二栅极2128b为栅线2128的对应第二沟道区2125的部分。
例如，如图14所示，在遮光层213和半导体层212之间设置有第一绝缘层219，在第一绝缘层219和第一金属层214之间设置有栅绝缘层217，在第一金属层214的远离衬底基板211的一侧设置有层间绝缘层218。
例如，结合图13和图14，在一个示例中，该遮光层213的材料包括非导电遮光材料或者导电遮光材料，第一过孔结构2126在衬底基板211上的正投影位于遮光层213在衬底基板211上的正投影之内。
例如，结合图13和图14，该遮光层213为一个整体结构，且该遮光层213在衬底基板211上的正投影覆盖第一沟道区2124在衬底基板211上的正投影、第二沟道区2125在衬底基板211上的正投影和第一过孔结构2126在衬底基板211上的正投影，以及覆盖第一沟道区2124和第二沟道区2125之间的间隙，该遮光层213的平面形状为台阶状。
例如，图15为本公开至少一实施例提供的又一种阵列基板的叠层结构示意图，在一个示例中，该衬底基板211上设置有多个薄膜晶体管，遮光层213的对应于不同的薄膜晶体管的部分相互间隔，且遮光层213仅对应于同一个薄膜晶体管的第一沟道区2124，即遮光层213在衬底基板211上的正投影仅覆盖第一沟道区2124在衬底基板211上的正投影，没有覆盖第二沟道区2125在衬底基板211上的正投影。
例如，如图15所示，在第二分支部2122的远离连接部2123的端部对应第二过孔结构2127，该第二过孔结构2127相对于第一过孔结构2126更远离 连接部2123，即在图15所示的平面图中，第一分支部2121和第二分支部2122均呈长条形，且均在第一方向X上延伸，而且第二分支部2122在第一方向X上的长度大于第一分支部2121在第一方向X上的长度，即在第一方向X上，第二过孔结构2127与连接部2123之间的距离大于第一过孔结构2126与连接部2123之间的距离，从而使得对应于第二分支部2122的端部的第二过孔结构2127和对应于第一分支部2121的端部的第一过孔结构2126不是平齐的。
例如，如图15所示，该阵列基板21通过将遮光层213设计成覆盖第一沟道区2124和第一过孔结构2126在衬底基板211上的正投影，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，图16为本公开至少一实施例提供的又一种阵列基板的叠层结构示意图，图16所示的阵列基板和图5所示的阵列基板的不同之处仅在于在第一分支部2121和第二分支部2122之间设置有沿着第一方向X延伸的触控信号线220，该种设计可以节省放置走线的空间，使得阵列基板更加轻薄化。图16所示的阵列基板的结构可以参见图5所示阵列基板的相关描述，在此不再赘述。
例如，图17为本公开至少一实施例提供的又一种阵列基板的叠层结构示意图，图17所示的阵列基板和图11所示的阵列基板的不同之处仅在于在第一分支部2121和第二分支部2122之间设置有沿着第一方向X延伸的触控信号线220，该种设计可以节省走线放置的空间，使得阵列基板更加轻薄化。图17所示的阵列基板的结构可以参见图11所示阵列基板的相关描述，在此不再赘述。
例如，对于显示面板，在和阵列基板相对设置的对置基板上还可以设置黑矩阵，而且还可以将遮光层的在第一方向X上在栅线的下侧的部分对间隔区域遮挡的长度减小，使得遮光层的边缘均收缩到黑矩阵覆盖的区域之内，这样可以进一步提升显示面板的开口率。
本公开至少一实施例提供一种显示面板，该显示面板包括相对设置的第一基板和第二基板，其中，第一基板包括衬底基板和层叠设置在衬底基板上的半导体层和遮光层；第二基板包括黑矩阵；半导体层包括相对设置的第一分支部和第二分支部，以及连接第一分支部和第二分支部的连接部，第一分支部包括第一沟道区，第二分支部包括第二沟道区，在第一分支部的远离衬底基板的 一侧具有第一过孔结构，且第一过孔结构在衬底基板上的正投影位于第一分支部的远离连接部的端部在衬底基板上的正投影之内；遮光层在衬底基板上的正投影位于黑矩阵在衬底基板上的正投影之内，且至少覆盖第一沟道区和第一过孔结构在衬底基板上的正投影。该显示面板通过调整遮光层的设计可以减少后续形成的显示面板的漏电流，以提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率，而且使得遮光层的边缘均收缩到黑矩阵覆盖的区域之内，这样可以进一步提升显示面板的开口率。
例如，图18为本公开至少一实施例提供的一种显示面板的截面结构示意图，图19为本公开至少一实施例提供的一种显示面板的平面结构示意图，图20为本公开至少一实施例提供的一种第一基板的截面结构示意图，结合图18、图19和图20所示，该显示面板30包括相对设置的第一基板31和第二基板32，该第一基板31包括衬底基板311和层叠设置在衬底基板311上的遮光层313和半导体层312。该第二基板32包括黑矩阵321，半导体层312包括相对设置的第一分支部3121和第二分支部3122，以及连接第一分支部3121和第二分支部3122的连接部3123，该第一分支部3121包括第一沟道区3121a，第二分支部3122包括第二沟道区3122a，第一分支部3121的远离连接部3123的端部对应第一过孔结构314，即第一分支部3121的远离衬底基板311的一侧具有第一过孔结构314，且第一过孔结构314在衬底基板311上的正投影位于第一分支部3121的远离连接部3123的端部在衬底基板311上的正投影之内，遮光层313在衬底基板311上的正投影位于黑矩阵321在衬底基板311上的正投影之内，且至少覆盖第一沟道区3121a、第二沟道区3122a和第一过孔结构314在衬底基板311上的正投影，该显示面板30通过将黑矩阵321设置成覆盖遮光层313的全部区域，并且将遮光层313设置成覆盖第一沟道区3121a、第二沟道区3122a和第一过孔结构314的全部区域，可以减少后续形成的显示面板的漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证显示面板的开口率。
需要说明的是，半导体层是在制作显示面板的过程中的一种状态，后续还有其他工艺把部分半导体区域进行了导体化，也就是在形成后续提及的栅极和栅线之后具有重掺杂的步骤，把半导体层的被栅极覆盖区域之外的部分变成导体，使得栅极能够遮挡沟道区，因此，位于栅极下方的是半导体层对应的 沟道区。
还需要说明的是，尽管在图19所示的实施例中，遮光层313覆盖了第二沟道区3122a，但是在其他的示例中，也可以是遮光层313对第二沟道区3122a不进行覆盖。
例如，在一个示例中，该第一基板31为阵列基板，该第二基板32为与阵列基板相对设置的对置基板，该对置基板例如为彩膜基板。该彩膜基板上的其他结构可以参见常规的设计，在此不再赘述。
例如，结合图19，在第二分支部3122的远离连接部3123的端部对应第二过孔结构315，该第二过孔结构315相对于第一过孔结构314更远离连接部3123，即在图19所示的平面图中，第一分支部3121和第二分支部3122均呈长条形，且均在第一方向X上延伸，而且第二分支部3122在第一方向X上的长度大于第一分支部3121在第一方向X上的长度，即在第一方向X上，第二过孔结构315与连接部3123之间的最小距离大于第一过孔结构314与连接部3123之间的最小距离，从而使得对应于第二分支部3122的端部的第二过孔结构315和对应于第一分支部3121的端部的第一过孔结构314不是平齐的。
例如，结合图19和图20，该第一基板31还包括设置在半导体层312的远离衬底基板311的一侧的第一金属层316，第一金属层316包括在第二方向Y上延伸的栅线3161，栅线3161呈长条形，栅线3161包括第一栅极3161a和第二栅极3161b，第一栅极3161a在衬底基板311上的正投影和第一沟道区3121a在衬底基板311上的正投影交叠，第二栅极3161b在衬底基板311上的正投影和第二沟道区3122a在衬底基板311上的正投影交叠。
例如，结合图19和图20，第一栅极3161a在衬底基板311上的正投影在黑矩阵321在衬底基板311上的正投影之内，第二栅极3161b在衬底基板311上的正投影在黑矩阵321在衬底基板311上的正投影之内，从而使得黑矩阵321对第一栅极3161a和第二栅极3161b进行完全覆盖。而且黑矩阵321对栅线3161的一整条都进行覆盖。
需要说明的是，在图19所示的实施例中，该黑矩阵321覆盖连接部3123的左下角的部分，即黑矩阵321覆盖连接部3123的对应第二分支部3122的一侧的部分，从而使得黑矩阵的左侧部分具有两个凸起部，而且，尽管在图19中未示出数据线，在实际的产品中，黑矩阵321还覆盖数据线。当显示面板上 还设置有触控信号线时，该黑矩阵也覆盖触控信号线的。
例如，如图20所示，在遮光层313和半导体层312之间设置有第一绝缘层319，在第一绝缘层319和第一金属层316之间设置有栅绝缘层317，在第一金属层316的远离衬底基板311的一侧设置有层间绝缘层318。
例如，结合图19和图20，在一个示例中，该遮光层313的材料包括具有遮光性能的导电金属，该黑矩阵321在衬底基板311上的正投影和遮光层313在衬底基板311上的正投影均覆盖第一过孔结构314在衬底基板311上的正投影，且第二过孔结构315在衬底基板311上的正投影位于遮光层313在衬底基板311上的正投影之外。
需要说明的是，如果用遮光层313遮挡第二过孔结构315，需要用黑矩阵321再将遮光层313进行遮挡，考虑到工艺过程中存在对位波动，当此处增加遮光层313时，多层结构的对位波动对会导致需要设计更宽的黑矩阵，从而会牺牲后续形成的显示面板的像素的开口率，基于显示面板的良率的考量，对层间绝缘层318进行刻蚀时会存在过刻到遮光层313的风险，而且当遮光层313的材料为具有遮光性能的导电金属时，对层间绝缘层318进行过刻会导致薄膜晶体管的第一源漏电极和第二源漏电极出现短路的问题，从而会使得薄膜晶体管失去开关的功能。
还需要说明的是，当遮光层313的材料不是具有遮光性能的导电材料时，即遮光层313的材料是具有遮光性能的绝缘材料时，遮光层313也可以覆盖第二过孔结构315，这样即使出现对层间绝缘层318进行刻蚀过刻到遮光层313的现象时，也不会出现薄膜晶体管的第一源漏电极和第二源漏电极出现短路的问题。
例如，在本公开的一个示例中，结合图19和图20，遮光层313对第一过孔结构314进行覆盖对于降低薄膜晶体管的漏电流Ioff的效果比较显著，遮光层313对第一沟道区3121a的遮挡面积变化时对应的显示面板的薄膜晶体管的漏电流Ioff的数据如下：以常规设计为基准(100％)，实验项得到的数据和常规设计得到的数据做比值，可以得出当增大遮光层313对第一沟道区3121a的遮挡面积时，对于显示面板的薄膜晶体管的漏电流Ioff的改善效果明显，但是遮光层313对第二沟道区3122a的遮挡面积的调整对于薄膜晶体管的特性的影响较小，因此，在不影响后续形成的显示面板的开口率的大小的前提下，尽量增大遮光层313对第一沟道区3121a的遮挡面积，并且遮光层313对第 一过孔结构314进行遮挡，且缩小遮光层313对第二沟道区3122a的遮挡面积，可以减小对后续形成的显示面板的开口率的影响。
例如，在本公开的一个示例中，为了保证第一过孔结构314不漏光，黑矩阵321需要完全遮挡第一过孔结构314，并且使得在第一方向X上，第一过孔结构314和黑矩阵321的与第一过孔结构314邻近的边的距离为1.15微米，所以为了保证遮光层313不影响后续形成的显示面板的开口率，在第一方向X上，遮光层313的对应第一过孔结构的右侧部分的上边缘与第一过孔结构314的上边缘平齐。
例如，如图19所示，在第一方向X上，第一过孔结构314的上边缘到栅线3161的距离为6.15微米，遮光层313将第一过孔结构314进行完全遮挡，且遮光层313的上边缘和第一过孔结构314的上边缘平齐，在栅线3161的上侧，遮光层313遮挡第一分支部3121的长度为6.15微米。在第一方向X上，在栅线3161的下侧，黑矩阵321的对应第一分支部3121的一侧的部分的长度为1.4微米。为了不影响后续形成的显示面板的开口率，在第一方向X上，将遮光层313的对应第一分支部3121的一侧的部分的下边缘设计成与黑矩阵321的对应第一分支部3121的一侧的部分的下边缘平齐，遮光层313的对应第一分支部3121的一侧的部分的下边缘到栅线3161的距离为1.4微米。在第二方向Y上，遮光层313的长度较长，遮光层313的右侧边缘与第一分支部3121的右侧边缘之间的最小距离为2.0微米，遮光层313的左侧边缘与第二分支部3122的左侧边缘之间的最小距离为2.0微米。此外，遮光层313进行整块设计，遮光层313对第一分支部3121和第二分支部3122之间的间隙部分进行完全遮挡，即实现遮光层313对栅线3161之上的部分进行充分遮挡。例如，基于上述数值大小对显示面板进行设计时，在6500nit光照的情况下，光线的透过率为34％；在20000nit光照的情况下，光线的透过率为31％。
例如，基于上述图19和图20所示实施例中的数值大小对显示面板进行设计时，做出10组关于低频闪烁的实验数据，分别是：-35.82、-33.53、-36.55、-36.45、-35.78、-38.12、-36.21、-36.45、-35.72以及-37.41，从而可以得出闪烁的平均数值为-36.204。对应的，基于图1中的常规设计的数值大小对显示面板进行设计时，做出10组关于低频闪烁的实验数据，分别是：-28.12、-26.58、-26.09、-28.22、-27.35、-29.2、-27.63、-28.54、-27.86以及-29.51，从而可以得出闪烁的平均数值为-27.91。从上述实验数据可以得出，通过对遮光层313 的优化设计，可以有效改善显示面板的显示画面的闪烁程度，以满足对显示面板的管控基准。
例如，在另一个示例中，在第一方向X上，第一过孔结构314的上边缘到栅线3161的距离为5.5微米，遮光层313对第一过孔结构314进行遮挡，且遮光层313的上边缘和第一过孔结构314的上边缘平齐，在栅线3161的上侧，遮光层313遮挡第一分支部3121的长度为5.5微米。在第一方向X上，在栅线3161的下侧，黑矩阵321的对应第一分支部3121的一侧的部分的长度为1.4微米。为了不影响后续形成的显示面板的开口率，在第一方向X上，将遮光层313的对应第一分支部3121的一侧的部分的下边缘设计成与黑矩阵321的对应第一分支部3121的一侧的部分的下边缘平齐，遮光层313的对应第一分支部3121的一侧的部分的下边缘到栅线3161的距离为1.4微米。在第二方向Y上，遮光层313的长度较长，遮光层313的右侧边缘与第一分支部3121的右侧边缘之间的最小距离为2.0微米，遮光层313的左侧边缘与第二分支部3122的左侧边缘之间的最小距离为2.0微米。此外，遮光层313进行整块设计，遮光层313对第一分支部3121和第二分支部3122之间的间隙部分进行完全遮挡，即实现遮光层313对栅线3161之上的间隙部分进行充分遮挡。例如，基于上述数值大小对显示面板进行设计时，在6500nit光照的情况下，光线的透过率为49％；在20000nit光照的情况下，光线的透过率为41％。
例如，在另一个示例中，在第一方向X上，第一过孔结构314的上边缘到栅线3161的距离为5微米，遮光层313对第一过孔结构314进行遮挡，且遮光层313的上边缘和第一过孔结构314的上边缘平齐，在栅线3161的上侧，遮光层313遮挡第一分支部3121的长度为5微米。在第一方向X上，在栅线3161的下侧，黑矩阵321的对应第一分支部3121的一侧的部分的长度为1.4微米。为了不影响显示面板的开口率，在第一方向X上，将遮光层313的对应第一分支部3121的一侧的部分的下边缘设计成与黑矩阵321的对应第一分支部3121的一侧的部分的下边缘平齐，遮光层313的下边缘到栅线3161的距离为1.4微米。在第二方向Y上，遮光层313的长度较长，遮光层313的右侧边缘与第一分支部3121的右侧边缘之间的最小距离为2.0微米，遮光层313的左侧边缘与第二分支部3122的左侧边缘之间的最小距离为2.0微米。此外，遮光层313进行整块设计，遮光层313对第一分支部3121和第二分支部3122之间的间隙部分进行完全遮挡，即实现遮光层313对栅线3161之上 的间隙部分进行充分遮挡。例如，基于上述数值大小对显示面板进行设计时，在6500nit光照的情况下，光线的透过率为57％；在20000nit光照的情况下，光线的透过率为48％。
例如，在另一个示例中，在第一方向X上，第一过孔结构314的上边缘到栅线3161的距离为4.5微米，遮光层313对第一过孔结构314进行遮挡，且遮光层313的上边缘和第一过孔结构314的上边缘平齐，故在栅线3161的上侧，遮光层313遮挡第一分支部3121的长度为4.5微米。在第一方向X上，在栅线3161的下侧，黑矩阵321的对应第一分支部3121的一侧的部分的长度为1.4微米。为了不影响显示面板的开口率，在第一方向X上，将遮光层313的对应第一分支部3121的一侧的部分的下边缘设计成与黑矩阵321的下边缘平齐，遮光层313的对应第一分支部3121的一侧的部分的下边缘到栅线3161的距离为1.4微米。在第二方向Y上，遮光层313的长度较长，遮光层313的右侧边缘与第一分支部3121的右侧边缘之间的最小距离为2.0微米，遮光层313的左侧边缘与第二分支部3122的左侧边缘之间的最小距离为2.0微米。此外，遮光层313进行整块设计，遮光层313对第一分支部3121和第二分支部3122之间的间隙部分进行完全遮挡，即实现遮光层313对栅线3161之上的间隙部分进行充分遮挡。例如，基于上述数值大小对显示面板进行设计时，在6500nit光照的情况下，光线的透过率为64％；在20000nit光照的情况下，光线的透过率为61％。
例如，在另一个示例中，在第一方向X上，第一过孔结构314的上边缘到栅线3161的距离为6.15微米，遮光层313将第一过孔结构314进行遮挡，且遮光层313的上边缘和第一过孔结构314的上边缘平齐，在栅线3161的上侧，遮光层313遮挡第一分支部3121的长度为6.15微米。在第一方向X上，在栅线3161的下侧，黑矩阵321的对应第一分支部3121的一侧的部分的长度为0.7微米。为了不影响显示面板的开口率，在第一方向X上，将遮光层313的对应第一分支部3121的一侧的部分的下边缘设计成与黑矩阵321的对应第一分支部3121的一侧的部分的下边缘平齐，遮光层313的对应第一分支部3121的一侧的部分的下边缘到栅线3161的距离为0.7微米。在第二方向Y上，遮光层313的长度较长，遮光层313的右侧边缘与第一分支部3121的右侧边缘之间的最小距离为2.0微米，遮光层313的左侧边缘与第二分支部3122的左侧边缘之间的最小距离为2.0微米。此外，遮光层313进行整块设计，遮 光层313对第一分支部3121和第二分支部3122之间的间隙部分进行完全遮挡，即实现遮光层313对栅线3161之上的部分进行充分遮挡。例如，基于上述数值大小对显示面板进行设计时，在6500nit光照的情况下，光线的透过率为36％；在20000nit光照的情况下，光线的透过率为35％。
例如，在另一个示例中，在第一方向X上，第一过孔结构314的上边缘到栅线3161的距离为6.15微米，遮光层313将第一过孔结构314进行遮挡，且遮光层313的上边缘和第一过孔结构314的上边缘平齐，在栅线3161的上侧，遮光层313遮挡第一分支部3121的长度为6.15微米。在第一方向X上，在栅线3161的下侧，黑矩阵321的对应第一分支部3121的一侧的部分的长度为0微米。为了不影响显示面板的开口率，在第一方向X上，将遮光层313的对应第一分支部3121的一侧的部分的下边缘设计成与黑矩阵321的对应第一分支部3121的一侧的部分的下边缘平齐，遮光层313的对应第一分支部3121的一侧的部分的下边缘到栅线3161的距离为0微米。在第二方向Y上，遮光层313的长度较长，遮光层313的右侧边缘与第一分支部3121的右侧边缘之间的最小距离为2.0微米，遮光层313的左侧边缘与第二分支部3122的左侧边缘之间的最小距离为2.0微米。此外，遮光层313进行整块设计，遮光层313对第一分支部3121和第二分支部3122之间的间隙部分进行完全遮挡，即实现遮光层313对栅线3161之上的部分进行充分遮挡。例如，基于上述数值大小对显示面板进行设计时，在6500nit光照的情况下，光线的透过率为39％；在20000nit光照的情况下，光线的透过率为32％。
基于对上述实验数据的分析，可以得出将薄膜晶体管的对应两个栅极的沟道区通过一整块遮光层或者较大面积的间隔设置的遮光层进行遮挡，并且遮光层将与像素电极连接的第一源漏电极的一侧的遮挡面积增大，即将上述层间绝缘层中的第一过孔结构进行遮挡时，可以减少显示面板包括的薄膜晶体管的漏电流的现象，而且将遮光层的在第一方向X上在栅线的下侧的遮光层对间隔区域进行遮挡的长度减小，以使得遮光层的边缘均收缩到黑矩阵覆盖的区域内，可以进一步提升显示面板的开口率。
例如，在第一基板31上可以设置有多个薄膜晶体管，遮光层313的对应于不同的薄膜晶体管的部分相互间隔，例如，如图19所示，遮光层313的对应于同一个薄膜晶体管的第一沟道区3121a和第二沟道区3122a的部分为一个整体结构。遮光层313设计成整体结构使得遮光层313覆盖的位于第一过 孔结构314一侧的面积增大，从而可以减少薄膜晶体管的漏电流。
例如，如图19所示，该第一分支部3121和第二分支部3122均沿第一方向X延伸，连接部3123沿与第一方向X交叉的第二方向Y延伸，该第一分支部3121、第二分支部3122和连接部3123围设形成开口区域，遮光层313覆盖至少部分开口区域，从而可以使得遮光层313设置成覆盖第一沟道区3121a、第二沟道区3122a和第一过孔结构314的全部区域，以减少薄膜晶体管的漏电流现象，并提升像素电容的保持能力，改善低频下闪烁的问题，此外，还可以保证显示面板的开口率。
例如，在一个示例中，该第一方向X和第二方向Y垂直。
例如，如图19所示，栅线3161在第二方向Y上的两侧边缘在衬底基板311上的正投影和黑矩阵321的在第二方向Y上对应的两侧边缘在衬底基板311上的正投影分别交叠，即栅线3161在第二方向Y上的两侧的边缘线在衬底基板311上的正投影和黑矩阵321的在第二方向Y上对应的两侧的边缘线在衬底基板311上的正投影重合，这样可以保证栅线3161可以收缩到黑矩阵321覆盖的区域内，从而可以进一步提升显示面板的开口率。
例如，如图19所示，在一个示例中，在第一方向X上，在遮光层313和连接部3123之间具有间隙，也即在黑矩阵321和连接部3123之间具有间隙，这样在减少显示面板包括的薄膜晶体管的漏电流的前提下，还可以改善低频下显示面板的闪烁问题，以及提高显示面板的开口率。
例如，如图19所示，在一个示例中，遮光层313的对应第一分支部3121的部分的靠近连接部3123的边缘在衬底基板311上的正投影与黑矩阵321的对应第一分支部3121的部分的靠近连接部3123的边缘在衬底基板311上的正投影交叠，也即遮光层313的对应第一分支部3121的部分的靠近连接部3123的边缘在衬底基板311上的正投影和黑矩阵321的对应第一分支部3121的部分的靠近连接部3123的边缘在衬底基板311上的正投影是平齐的，也即遮光层313的对应第一分支部3121的部分的靠近连接部3123的边线在衬底基板311上的正投影与黑矩阵321的对应第一分支部3121的部分的靠近连接部3123的边线在衬底基板311上的正投影重合，这样可以保证遮光层313的边缘可以完全收缩至黑矩阵321覆盖的区域之内，以保证显示面板的开口率。
例如，在其他的示例中，在第二方向Y上，遮光层313的最左侧边缘也可以是和黑矩阵321的最左侧边缘重合或者位于黑矩阵321的最左侧边缘在 衬底基板311上的正投影之内；遮光层313的最右侧边缘也可以是和黑矩阵321的最左侧边缘重合或者位于黑矩阵321的最右侧边缘在衬底基板311上的正投影之内。
例如，如图19所示，在第一方向X上位于栅线3161下侧的对应第一分支部3121的部分遮光层313的最下边缘和在第一方向X上位于栅线3161下侧的对应第一分支部3121的部分黑矩阵321的最靠近连接部3123的边缘在衬底基板311上的正投影相交叠，即黑矩阵321的至少部分和遮光层313的边也平齐。
例如，图21为本公开至少一实施例提供的另一种显示面板的平面结构示意图，图22为图21中第一基板的截面结构示意图，例如，结合图18、图21和图22，该第一基板31包括衬底基板311和层叠设置在衬底基板311上的遮光层313和半导体层312。该第二基板32包括黑矩阵321，半导体层312包括相对设置的第一分支部3121和第二分支部3122，以及连接第一分支部3121和第二分支部3122的连接部3123，该第一分支部3121包括第一沟道区3121a，第二分支部3122包括第二沟道区3122a，第一分支部3121的远离连接部3123的端部对应第一过孔结构314，即第一分支部3121的远离衬底基板311的一侧具有第一过孔结构314，且第一过孔结构314在衬底基板311上的正投影位于第一分支部3121的远离连接部3123的端部在衬底基板311上的正投影之内，第二分支部3122的远离连接部3123的端部对应第二过孔结构315，即第二分支部3122的远离衬底基板311的一侧具有第二过孔结构315，且第二过孔结构315在衬底基板311上的正投影位于第二分支部3122的远离连接部3123的端部在衬底基板311上的正投影之内，遮光层313在衬底基板311上的正投影位于黑矩阵321在衬底基板311上的正投影之内，且遮光层313在衬底基板311上的正投影覆盖第一沟道区3121a、第二沟道区3122a、第一过孔结构314和第二过孔结构315在衬底基板311上的正投影，该显示面板30通过将黑矩阵321设置成覆盖遮光层313的全部区域，并且将遮光层313设置成覆盖第一沟道区3121a、第二沟道区3122a、第一过孔结构314和第二过孔结构315的全部区域，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证显示面板的开口率。
例如，结合图21，在第一方向X上，该第二过孔结构315相对于第一过孔结构314更远离连接部3123，即在图21所示的平面图中，第一分支部3121 和第二分支部3122均呈长条形，且均在第一方向X上延伸，而且第二分支部3122在第一方向X上的长度大于第一分支部3121在第一方向X上的长度，即在第一方向X上，第二过孔结构315与连接部3123之间的距离大于第一过孔结构314与连接部3123之间的距离，从而使得对应于第二分支部3122的端部的第二过孔结构315和对应于第一分支部3121的端部的第一过孔结构314不是平齐的。
例如，结合图21和图22，该第一基板31还包括设置在半导体层312的远离衬底基板311的一侧的第一金属层316，第一金属层316包括在第二方向Y上延伸的栅线3161，栅线3161呈长条形，栅线3161包括第一栅极3161a和第二栅极3161b，第一栅极3161a在衬底基板311上的正投影和第一沟道区3121a在衬底基板311上的正投影交叠，第二栅极3161b在衬底基板311上的正投影和第二沟道区3122a在衬底基板311上的正投影交叠，且第一栅极3161a和第二栅极3161b在衬底基板311上的正投影在黑矩阵321在衬底基板311上的正投影之内。
需要说明的是，在图21所示的实施例中，该黑矩阵321覆盖连接部3123的左下角的部分，即黑矩阵321覆盖连接部3123的对应第二分支部3122的一侧的部分，从而使得黑矩阵的左侧部分具有两个凸起部，而且，尽管在图19中未示出数据线，在实际的产品中，黑矩阵321还覆盖数据线。当显示面板上还设置有触控信号线时，该黑矩阵也覆盖触控信号线的。
例如，如图22所示，在遮光层313和半导体层312之间设置有第一绝缘层319，在第一绝缘层319和第一金属层316之间设置有栅绝缘层317，在第一金属层316的远离衬底基板311的一侧设置有层间绝缘层318。
例如，如图21和图22所示，该遮光层313的远离连接部3123的边在衬底基板311上的正投影包括位于第一过孔结构314的远离连接部3123的一侧的第一部分313c和位于第二过孔结构315的远离连接部3123的一侧的第二部分313d，第一部分313c的上边缘和第二部分313d的上边缘不在同一条直线上，即该遮光层313的平面形状为台阶状，黑矩阵321的平面形状为网格状。尽管图21所示的黑矩阵321的平面形状为矩形，黑矩阵321的对应遮光层313的平面形状也为台阶状，且在第一方向X上，第一部分313c和连接部3123之间的距离小于第二部分313d和连接部3123之间的距离。第二部分313d和黑矩阵321的位于第二过孔结构315上侧的边缘在衬底基板311上的 正投影相交叠，即第二部分313d和黑矩阵321的左侧对应于第二过孔结构315的部分的上边缘在衬底基板311上的正投影相重合，第一部分313c和黑矩阵321的位于第一过孔结构314上侧的边缘在衬底基板311上的正投影相间隔。该黑矩阵321在衬底基板311上的正投影和遮光层313在衬底基板311上的正投影均覆盖第二过孔结构315在衬底基板311上的正投影，即第二过孔结构315在衬底基板311上的正投影位于遮光层313在衬底基板311上的正投影之内。需要说明的是，在该示例中，该遮光层313的材料为非导电遮光材料，当该遮光层313的材料为非导电遮光材料时，即使出现对层间绝缘层318进行刻蚀过刻到遮光层313的现象时，也不会出现薄膜晶体管的第一源漏电极和第二源漏电极短路的问题。
例如，图23为本公开至少一实施例提供的又一种显示面板的平面结构示意图，图24为图23中第一基板的截面结构示意图，例如，结合图18、图23和图24，该第一基板31包括衬底基板311和层叠设置在衬底基板311上的遮光层313和半导体层312。该第二基板32包括黑矩阵321，半导体层312包括相对设置的第一分支部3121和第二分支部3122，以及连接第一分支部3121和第二分支部3122的连接部3123，该第一分支部3121包括第一沟道区3121a，第二分支部3122包括第二沟道区3122a，第一分支部3121的远离连接部3123的端部对应第一过孔结构314，遮光层313在衬底基板311上的正投影位于黑矩阵321在衬底基板311上的正投影之内。遮光层313的对应于不同的薄膜晶体管的部分相互间隔，该遮光层313的对应于同一个薄膜晶体管的第一沟道区3121a和第二沟道区3122a的部分分别为第一子遮光部313a和第二子遮光部313b，且该第一子遮光部313a和第二子遮光部313b相互间隔。该第一子遮光部313a覆盖第一沟道区3121a和第一过孔结构314在衬底基板311上的正投影，第二子遮光部313b覆盖第二沟道区3122a在衬底基板311上的正投影，但没有覆盖第二过孔结构315在衬底基板311上的正投影。该显示面板30通过将黑矩阵321设置成覆盖遮光层313的全部区域，以及第一子遮光部313a和第二子遮光部313b之间的区域，并且将第一子遮光部313a设计成覆盖第一沟道区3121a和第一过孔结构314在衬底基板311上的正投影，将第二子遮光部313b设计成覆盖第二沟道区3122a在衬底基板311上的正投影，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证显示面板的开口率。
例如，结合图23，在第二分支部3122的远离连接部3123的端部对应第二过孔结构315，该第二过孔结构315相对于第一过孔结构314更远离连接部3123，即在图23所示的平面图中，第一分支部3121和第二分支部3122均呈长条形，且均在第一方向X上延伸，而且第二分支部3122在第一方向X上的长度大于第一分支部3121在第一方向X上的长度，即在第一方向X上，第二过孔结构315与连接部3123之间的距离大于第一过孔结构314与连接部3123之间的距离，从而使得对应于第二分支部3122的端部的第二过孔结构315和对应于第一分支部3121的端部的第一过孔结构314不是平齐的。
例如，结合图23和图24，该第一基板31还包括设置在半导体层312的远离衬底基板311的一侧的第一金属层316，第一金属层316包括在第二方向Y上延伸的栅极3161，栅极3161呈长条形，栅线3161包括第一栅极3161a和第二栅极3161b，第一栅极3161a在衬底基板311上的正投影和第一沟道区3121a在衬底基板311上的正投影交叠，第二栅极3161b在衬底基板311上的正投影和第二沟道区3122a在衬底基板311上的正投影交叠，且第一栅极3161a和第二栅极3161b在衬底基板311上的正投影在黑矩阵321在衬底基板311上的正投影之内。
需要说明的是，在图23所示的实施例中，该黑矩阵321覆盖连接部3123的左下角的部分，即黑矩阵321覆盖连接部3123的对应第二分支部3122的一侧的部分，从而使得黑矩阵的左侧部分具有两个凸起部，而且，尽管在图19中未示出数据线，在实际的产品中，黑矩阵321还覆盖数据线。当显示面板上还设置有触控信号线时，该黑矩阵也覆盖触控信号线的。
例如，如图23所示，在遮光层313和半导体层312之间设置有第一绝缘层319，在第一绝缘层319和第一金属层316之间设置有栅绝缘层317，在第一金属层316的远离衬底基板311的一侧设置有层间绝缘层318。
例如，如图23和图24所示，该第一子遮光部313a的远离连接部3123的边在衬底基板311上的正投影包括位于第一过孔结构314的远离连接部3123的一侧的第一部分313c，第二子遮光部313b的远离连接部3123的边在衬底基板311上的正投影包括位于第二过孔结构315的远离连接部3123的一侧的第二部分313d，即该第一子遮光部313a和第二子遮光部313b的平面形状均为长条形，且第一子遮光部313a的长度小于第二子遮光部313b的长度。在第一方向X上，第一部分313c和连接部3123之间的距离小于第二部分313d 和连接部3123之间的距离。第二部分313d和黑矩阵321的位于第二过孔结构315的上侧的部分的边缘在衬底基板311上的正投影相交叠，即第二部分313d和黑矩阵321的位于第二过孔结构315的上侧的部分的边缘在衬底基板311上的正投影相重合，第一部分313c和黑矩阵321的位于第一过孔结构314的上侧的部分的边缘在衬底基板311上的正投影相间隔。该黑矩阵321在衬底基板311上的正投影覆盖第二过孔结构315在衬底基板311上的正投影，遮光层313在衬底基板311上的正投影未覆盖第二过孔结构315在衬底基板311上的正投影，即第二过孔结构315在衬底基板311上的正投影位于遮光层313在衬底基板311上的正投影之外。需要说明的是，在该示例中，该遮光层313的材料为非导电遮光材料或者遮光导电材料，即使出现对层间绝缘层318进行刻蚀过刻到遮光层313的现象时，也不会出现薄膜晶体管的第一源漏电极和第二源漏电极之间短路的问题。
例如，该第一基板31上设置有多个薄膜晶体管，遮光层313的对应于不同的薄膜晶体管的部分相互间隔，结合图23和图24，该遮光层313的对应于同一个薄膜晶体管的第一沟道区3121a和第二沟道区3122a的部分分别为第一子遮光部313a和第二子遮光部313b，且该第一子遮光部313a和第二子遮光部313b相互间隔，第一沟道区3121a在衬底基板311上的正投影完全位于第一子遮光部313a在衬底基板311上的正投影之内，第二沟道区3122a在衬底基板311上的正投影完全位于第二子遮光部313b在衬底基板311上的正投影之内。该第一过孔结构314在衬底基板311上的正投影位于第一子遮光部313a在衬底基板311上的正投影内，且第二过孔结构315在衬底基板311上的正投影位于第二子遮光部313b在衬底基板311上的正投影之外。
例如，如图23和图24所示，该第二分支部3122的远离连接部3123的端部对应第二过孔结构315，第二过孔结构315和连接部3123之间的最大距离大于第一过孔结构314和连接部3123之间的最大距离。
例如，图25为本公开至少一实施例提供的又一种显示面板的平面结构示意图，图26为图25中第一基板的截面结构示意图，例如，结合图18、图25和图26，该第一基板31包括衬底基板311和层叠设置在衬底基板311上的遮光层313和半导体层312。该第二基板32包括黑矩阵321，半导体层312包括相对设置的第一分支部3121和第二分支部3122，以及连接第一分支部3121和第二分支部3122的连接部3123，该第一分支部3121包括第一沟道区3121a， 第二分支部3122包括第二沟道区3122a，第一分支部3121的远离连接部3123的端部对应第一过孔结构314，第二分支部3122的远离连接部3123的端部对应第二过孔结构315。遮光层313在衬底基板311上的正投影位于黑矩阵321在衬底基板311上的正投影之内，且覆盖第一沟道区3121a、第二沟道区3122a、第一过孔结构314和第二过孔结构315在衬底基板311上的正投影，该显示面板30通过将黑矩阵321设置成覆盖遮光层313的全部区域，并且将遮光层313设置成覆盖第一沟道区3121a、第二沟道区3122a、第一过孔结构314和第二过孔结构315的全部区域，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证显示面板的开口率。
例如，在图25所示的平面结构示意图中，该遮光层313在衬底基板311上的正投影位于黑矩阵321在衬底基板311上的正投影之内，且遮光层313在衬底基板311上的正投影面积小于黑矩阵321在衬底基板311上的正投影的面积，当然，本公开的实施例不限于此，不考虑黑矩阵的对连接部3123的左下角部分进行覆盖的部分，还可以是遮光层313的平面形状和对应于遮光层的黑矩阵321的部分的平面形状相同。
例如，结合图25，在第二分支部3122的远离连接部3123的端部对应第二过孔结构315，在第一方向X上，该第二过孔结构315和连接部3123之间的距离等于第一过孔结构314和连接部3123之间的距离，即在图25所示的平面图中，第一分支部3121和第二分支部3122均呈长条形，且均在第一方向X上延伸，而且第二分支部3122在第一方向X上的长度等于第一分支部3121在第一方向X上的长度，从而使得对应于第二分支部3122的端部的第二过孔结构315和对应于第一分支部3121的端部的第一过孔结构314是平齐的。
例如，结合图25和图26，该第一基板31还包括设置在半导体层312的远离衬底基板311的一侧的第一金属层316，第一金属层316包括在第二方向Y上延伸的栅极3161，栅极3161呈长条形，栅线3161包括第一栅极3161a和第二栅极3161b，第一栅极3161a在衬底基板311上的正投影和第一沟道区3121a在衬底基板311上的正投影交叠，第二栅极3161b在衬底基板311上的正投影和第二沟道区3122a在衬底基板311上的正投影交叠，且第一栅极3161a和第二栅极3161b在衬底基板311上的正投影在黑矩阵321在衬底基板311上的正投影之内。
需要说明的是，在图25所示的实施例中，该黑矩阵321覆盖连接部3123的左下角的部分，即黑矩阵321覆盖连接部3123的对应第二分支部3122的一侧的部分，从而使得黑矩阵的左侧部分具有两个凸起部，而且，尽管在图19中未示出数据线，在实际的产品中，黑矩阵321还覆盖数据线。当显示面板上还设置有触控信号线时，该黑矩阵也覆盖触控信号线的。
例如，如图26所示，在遮光层313和半导体层312之间设置有第一绝缘层319，在第一绝缘层319和第一金属层316之间设置有栅绝缘层317，在第一金属层316的远离衬底基板311的一侧设置有层间绝缘层318。
例如，结合图25和图26，在一个示例中，该遮光层313的材料包括非导电遮光材料，该黑矩阵321在衬底基板311上的正投影覆盖第一过孔结构314和第二过孔结构315在衬底基板311上的正投影，且第一过孔结构314和第二过孔结构315在衬底基板311上的正投影均位于遮光层313在衬底基板311上的正投影之内。
例如，结合图25和图26，该遮光层313为一个整体结构，且该遮光层313在衬底基板311上的正投影覆盖第一沟道区3121a在衬底基板311上的正投影、第二沟道区3122a在衬底基板311上的正投影、第一过孔结构314在衬底基板311上的正投影和第二过孔结构315在衬底基板311上的正投影，以及覆盖第一沟道区3121a和第二沟道区3122a之间的间隙，并且覆盖第一过孔结构314和第二过孔结构315之间的间隙。
例如，图27为本公开至少一实施例提供的又一种显示面板的平面结构示意图，图28为图27中第一基板的截面结构示意图，例如，结合图18、图27和图28，该第一基板31包括衬底基板311和层叠设置在衬底基板311上的遮光层313和半导体层312。该第二基板32包括黑矩阵321，半导体层312包括相对设置的第一分支部3121和第二分支部3122，以及连接第一分支部3121和第二分支部3122的连接部3123，该第一分支部3121包括第一沟道区3121a，第二分支部3122包括第二沟道区3122a，第一分支部3121的远离连接部3123的端部对应第一过孔结构314，即在第一分支部3121的远离衬底基板311的一侧具有第一过孔结构314，且第一过孔结构314在衬底基板311上的正投影位于第一分支部3121的远离连接部3123的端部在衬底基板311上的正投影之内，遮光层313在衬底基板311上的正投影位于黑矩阵321在衬底基板311上的正投影之内。遮光层313的对应于不同的薄膜晶体管的部分相互间隔， 该遮光层313的对应于同一个薄膜晶体管的第一沟道区3121a和第二沟道区3122a的部分分别为第一子遮光部313a和第二子遮光部313b，且该第一子遮光部313a和第二子遮光部313b相互间隔。该第一子遮光部313a覆盖第一沟道区3121a和第一过孔结构314在衬底基板311上的正投影，第二子遮光部313b覆盖第二沟道区3122a和第二过孔结构315在衬底基板311上的正投影。该显示面板30通过将黑矩阵321设置成覆盖第一子遮光部313a和第二子遮光部313b，但没有覆盖第一子遮光部313a和第二子遮光部313b之间的区域，并且将第一子遮光部313a设计成第一子遮光部313a在衬底基板311上的正投影覆盖第一沟道区3121a和第一过孔结构314在衬底基板311上的正投影，将第二子遮光部313b设计成第二子遮光部313b在衬底基板311上的正投影覆盖第二沟道区3122a和第二过孔结构315在衬底基板311上的正投影，该种设计可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证显示面板的开口率。
例如，结合图27，在第二分支部3122的远离连接部3123的端部对应第二过孔结构315，该第二过孔结构315和连接部3123之间的最小距离等于第一过孔结构314和连接部3123之间的最小距离，即在图27所示的平面图中，第一分支部3121和第二分支部3122均呈长条形，且均在第一方向X上延伸，第二分支部3122在第一方向X上的长度等于第一分支部3121在第一方向X上的长度，即在第一方向X上，第二过孔结构315与连接部3123之间的距离等于第一过孔结构314与连接部3123之间的距离，从而使得对应于第二分支部3122的端部的第二过孔结构315和对应于第一分支部3121的端部的第一过孔结构314是平齐的。
例如，结合图27和图28，该第一基板31还包括设置在半导体层312的远离衬底基板311的一侧的第一金属层316，第一金属层316包括在第二方向Y上延伸的栅极3161，栅极3161呈长条形，栅线3161包括第一栅极3161a和第二栅极3161b，第一栅极3161a在衬底基板311上的正投影和第一沟道区3121a在衬底基板311上的正投影交叠，第二栅极3161b在衬底基板311上的正投影和第二沟道区3122a在衬底基板311上的正投影交叠，且栅线3161在衬底基板311上的正投影在黑矩阵321在衬底基板311上的正投影之内，即栅线3161也收缩至黑矩阵321限定的范围之内，从而不会减小显示面板的开口率。
需要说明的是，在图27所示的实施例中，该黑矩阵321覆盖连接部3123的左下角的部分，即黑矩阵321覆盖连接部3123的对应第二分支部3122的一侧的部分，从而使得黑矩阵的左侧部分具有两个凸起部，而且，尽管在图19中未示出数据线，在实际的产品中，黑矩阵321还覆盖数据线。当显示面板上还设置有触控信号线时，该黑矩阵也覆盖触控信号线的。
例如，如图28所示，在遮光层313和半导体层312之间设置有第一绝缘层319，在第一绝缘层319和第一金属层316之间设置有栅绝缘层317，在第一金属层316的远离衬底基板311的一侧设置有层间绝缘层318。
例如，如图27和图28所示，该第一子遮光部313a的远离连接部3123的边在衬底基板311上的正投影包括位于第一过孔结构314的远离连接部3123的一侧的第一部分313c，第二子遮光部313b的远离连接部3123的边在衬底基板311上的正投影包括位于第二过孔结构315的远离连接部3123的一侧的第二部分313d，第一部分313c的上边缘和第二部分313d的上边缘在同一条直线上，即该第一子遮光部313a和第二子遮光部313b的平面形状均为长条形，且第一子遮光部313a在第一方向X上的长度等于第二子遮光部313b在第一方向X上的长度。在第一方向X上，第一部分313c和连接部3123之间的距离等于第二部分313d和连接部3123之间的距离。第二部分313d和位于第二过孔结构315上侧的黑矩阵321的上边缘在衬底基板311上的正投影相交叠，即第二部分313d和位于第二过孔结构315上侧的黑矩阵321的上边缘在衬底基板311上的正投影相重合，第一部分313c和位于第一过孔结构314上侧的黑矩阵321的上边缘在衬底基板311上的正投影相重合。该黑矩阵321在衬底基板311上的正投影和遮光层313在衬底基板311上的正投影均覆盖第二过孔结构315在衬底基板311上的正投影，即第二过孔结构315在衬底基板311上的正投影位于遮光层313在衬底基板311上的正投影之内。需要说明的是，在该示例中，该遮光层313的材料为非导电遮光材料，即使出现对层间绝缘层318进行刻蚀过刻到遮光层313的现象时，也不会出现薄膜晶体管的第一源漏电极和第二源漏电极短路的问题。
例如，该第一基板31上设置有多个薄膜晶体管，遮光层313的对应于不同的薄膜晶体管的部分相互间隔，结合图27和图28，该遮光层313的对应于同一个薄膜晶体管的第一沟道区3121a和第二沟道区3122a的部分分别为第一子遮光部313a和第二子遮光部313b，且该第一子遮光部313a和第二子遮 光部313b相互间隔，第一沟道区3121a在衬底基板311上的正投影完全位于第一子遮光部313a在衬底基板311上的正投影之内，第二沟道区3122a在衬底基板311上的正投影完全位于第二子遮光部313b在衬底基板311上的正投影之内。该第一过孔结构314在衬底基板311上的正投影位于第一子遮光部313a在衬底基板311上的正投影内，且第二过孔结构315在衬底基板311上的正投影位于第二子遮光部313b在衬底基板311上的正投影之内。
例如，图29为本公开至少一实施例提供的又一种显示面板的平面结构示意图，图30为图29所示第一基板的截面结构示意图，结合图18、图29和图30所示，该第一基板31包括衬底基板311和层叠设置在衬底基板311上的遮光层313和半导体层312。该第二基板32包括黑矩阵321，半导体层312包括相对设置的第一分支部3121和第二分支部3122，以及连接第一分支部3121和第二分支部3122的连接部3123，该第一分支部3121包括第一沟道区3121a，第二分支部3122包括第二沟道区3122a。第一分支部3121的远离连接部3123的端部对应第一过孔结构314，即在第一分支部3121的远离衬底基板311的一侧具有第一过孔结构314，且第一过孔结构314在衬底基板311上的正投影位于第一分支部3121的远离连接部3123的端部在衬底基板311上的正投影之内。第二分支部3122的远离连接部3123的端部对应第二过孔结构315，即第二分支部3122的远离衬底基板311的一侧具有第二过孔结构315，且第二过孔结构315在衬底基板311上的正投影位于第二分支部3122的远离连接部3123的端部在衬底基板311上的正投影之内。遮光层313在衬底基板311上的正投影位于黑矩阵321在衬底基板311上的正投影之内。遮光层313在衬底基板311上的正投影覆盖第一沟道区3121a、第二沟道区3122a和第一过孔结构2126在衬底基板311上的正投影，该显示面板30通过将遮光层213设置成覆盖第一沟道区3121a、第二沟道区3122a和第一过孔结构314的全部区域，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，如图29所示，在第一方向X上，该第二过孔结构315和连接部3123之间的距离等于第一过孔结构314和连接部3123之间的距离，即在图29所示的平面图中，第一分支部3121和第二分支部3122均呈长条形，且均在第一方向X上延伸，而且第二分支部3122在第一方向X上的长度等于第一分支部3121在第一方向X上的长度，从而使得对应于第二分支部3122的 端部的第二过孔结构315和对应于第一分支部3121的端部的第一过孔结构2124是平齐的。
例如，如图29和30所示，该第一基板31还包括设置在半导体层312的远离衬底基板311的一侧的第一金属层316，第一金属层316包括在第二方向Y上延伸的栅线3161，栅线3161呈长条形，栅线3161包括第一栅极3161a和第二栅极3161b，第一栅极3161a在衬底基板311上的正投影和第一沟道区3121a在衬底基板311上的正投影交叠，第二栅极3161b在衬底基板311上的正投影和第二沟道区3122a在衬底基板311上的正投影交叠。
例如，第一栅极3161a、第二栅极3161b和栅线3161是一体的直线型结构，第一栅极3161a和第二栅极3161b是栅线3161的一部分，第一栅极3161a为栅线3161的对应第一沟道区3121a的部分，第二栅极3161b为栅线3161的对应第二沟道区3122a的部分。
需要说明的是，在图29所示的实施例中，该黑矩阵321覆盖连接部3123的左下角的部分，即黑矩阵321覆盖连接部3123的对应第二分支部3122的一侧的部分，从而使得黑矩阵的左侧部分具有两个凸起部，而且，尽管在图19中未示出数据线，在实际的产品中，黑矩阵321还覆盖数据线。当显示面板上还设置有触控信号线时，该黑矩阵也覆盖触控信号线的。
例如，如图30所示，在遮光层313和半导体层312之间设置有第一绝缘层319，在第一绝缘层319和第一金属层316之间设置有栅绝缘层317，在第一金属层316的远离衬底基板311的一侧设置有层间绝缘层318。
例如，结合图29和图30，在一个示例中，该遮光层313的材料包括非导电遮光材料或者导电遮光材料，第一过孔结构314在衬底基板311上的正投影位于遮光层313在衬底基板311上的正投影之内。
例如，结合图29和图30，该遮光层313为一个整体结构，且该遮光层313在衬底基板311上的正投影覆盖第一沟道区3121a在衬底基板311上的正投影、第二沟道区3122a在衬底基板311上的正投影和第一过孔结构314在衬底基板311上的正投影，以及覆盖第一沟道区3121a和第二沟道区3122a之间的间隙，该遮光层313的平面形状为台阶状。
例如，图31为本公开至少一实施例提供的又一种显示面板的平面结构示意图，图32为图31所示第一基板的截面结构示意图，结合图18、图31和图32所示，该第一基板31包括衬底基板311和层叠设置在衬底基板311上的遮 光层313和半导体层312。该第二基板32包括黑矩阵321，半导体层312包括相对设置的第一分支部3121和第二分支部3122，以及连接第一分支部3121和第二分支部3122的连接部3123，该第一分支部3121包括第一沟道区3121a，第二分支部3122包括第二沟道区3122a。第一分支部3121的远离连接部3123的端部对应第一过孔结构314，即在第一分支部3121的远离衬底基板311的一侧具有第一过孔结构314，且第一过孔结构314在衬底基板311上的正投影位于第一分支部3121的远离连接部3123的端部在衬底基板311上的正投影之内。第二分支部3122的远离连接部3123的端部对应第二过孔结构315，即第二分支部3122的远离衬底基板311的一侧具有第二过孔结构315，且第二过孔结构315在衬底基板311上的正投影位于第二分支部3122的远离连接部3123的端部在衬底基板311上的正投影之内。遮光层313在衬底基板311上的正投影位于黑矩阵321在衬底基板311上的正投影之内。遮光层313在衬底基板311上的正投影覆盖第一沟道区3121a和第一过孔结构2126在衬底基板311上的正投影，该显示面板30通过将遮光层213设置成覆盖第一沟道区3121a和第一过孔结构314的全部区域，但没有覆盖第二沟道区3122a在衬底基板311上的正投影，可以减少漏电流现象，提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证后续形成的显示面板的开口率。
例如，如图31所示，在第一方向X上，该第二过孔结构315和连接部3123之间的距离大于第一过孔结构314和连接部3123之间的距离。
例如，如图31和32所示，该第一基板31还包括设置在半导体层312的远离衬底基板311的一侧的第一金属层316，第一金属层316包括在第二方向Y上延伸的栅线3161，栅线3161呈长条形，栅线3161包括第一栅极3161a和第二栅极3161b，第一栅极3161a在衬底基板311上的正投影和第一沟道区3121a在衬底基板311上的正投影交叠，第二栅极3161b在衬底基板311上的正投影和第二沟道区3122a在衬底基板311上的正投影交叠。
需要说明的是，在图31所示的实施例中，该黑矩阵321覆盖连接部3123的左下角的部分，即黑矩阵321覆盖连接部3123的对应第二分支部3122的一侧的部分，从而使得黑矩阵的左侧部分具有两个凸起部，而且，尽管在图19中未示出数据线，在实际的产品中，黑矩阵321还覆盖数据线。当显示面板上还设置有触控信号线时，该黑矩阵也覆盖触控信号线的。
例如，如图32所示，在遮光层313和半导体层312之间设置有第一绝缘 层319，在第一绝缘层319和第一金属层316之间设置有栅绝缘层317，在第一金属层316的远离衬底基板311的一侧设置有层间绝缘层318。
例如，结合图31和图32，在一个示例中，该遮光层313的材料包括非导电遮光材料或者导电遮光材料，第一过孔结构314在衬底基板311上的正投影位于遮光层313在衬底基板311上的正投影之内。
例如，图33为本公开至少一实施例提供的又一种显示面板的平面结构示意图，图33所示的显示面板和图19所示的显示面板的不同之处仅在于在第一分支部3121和第二分支部3122之间设置有沿着第一方向X延伸的触控信号线320，可以节省走线放置的空间，使得显示面板更加轻薄化。图33所示的显示面板的结构可以参见图19所示显示面板的相关描述，在此不再赘述。
例如，在图33所示的结构中，黑矩阵321也覆盖了触控信号线320。
例如，图34为本公开至少一实施例提供的又一种显示面板的叠层结构示意图，图34所示的显示面板和图27所示的显示面板的不同之处仅在于在第一分支部3121和第二分支部3122之间设置有沿着第一方向X延伸的触控信号线320，可以节省走线放置的空间，使得显示面板更加轻薄化。图34所示的显示面板的结构可以参见图27所示显示面板的相关描述，在此不再赘述。
例如，在图34所示的结构中，黑矩阵321也覆盖了触控信号线320。
例如，图35为本公开至少一实施例提供的一种显示面板的框图，如图35所示，该显示面板30包括上述任一实施例中的阵列基板21，也即第一基板31。在一个示例中，该显示面板30还包括夹设在第一基板31和第二基板32之间的液晶层，该显示面板包括的其他电路结构可以参见常规的设计，本公开的实施例对此不作限定。
本公开至少一实施例还提供一种显示装置，例如，图36为本公开至少一实施例提供的一种显示装置的框图，如图36所示，该显示装置500包括上述任一项所述显示面板30，该显示面板30包括上述任一实施例提供的阵列基板。
例如，该显示装置500可以为具有显示功能的显示设备。例如，该显示装置500可以为显示器、OLED显示面板、OLED电视、液晶显示面板、液晶显示电视、QLED显示面板、QLED电视、电子纸、手机、平板电脑、笔记本电脑、数码相框、导航仪等任何具有显示功能和触控功能的产品或者部件。
本公开至少一实施例提供的阵列基板、显示面板和显示装置，具有 以下至少一项有益技术效果：
(1)本公开至少一实施例提供的阵列基板，通过调整遮光层的设计，将遮光层设计成遮挡第一过孔结构，可以减少显示面板的漏电流，以提升像素电容的保持能力，从而可以改善低频下闪烁的问题，而且还可以保证显示面板的开口率。
(2)本公开至少一实施例提供的显示面板，遮光层进行整块设计，遮光层对第一分支部和第二分支部之间的间隙部分进行完全遮挡，即实现遮光层对栅线之上的间隙部分进行充分遮挡，可以在不影响开口率的情况下减少薄膜晶体管的漏电流。
(3)本公开至少一实施例提供的显示面板，将遮光层的边缘均收缩到黑矩阵覆盖的区域之内，可以进一步提升显示面板的开口率。
有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本公开的实施例的附图中，层或区域的厚度被放大或缩小，即这些附图并非按照实际的比例绘制。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (26)

  1. 一种阵列基板，包括衬底基板和层叠设置在所述衬底基板上的半导体层和遮光层，所述半导体层包括相对设置的第一分支部和第二分支部，以及连接所述第一分支部和所述第二分支部的连接部，所述第一分支部包括第一沟道区，所述第二分支部包括第二沟道区，在所述第一分支部的远离所述衬底基板的一侧具有第一过孔结构，且所述第一过孔结构在所述衬底基板上的正投影位于所述第一分支部的远离所述连接部的端部在所述衬底基板上的正投影之内；所述遮光层在所述衬底基板上的正投影至少覆盖所述第一沟道区和所述第一过孔结构在所述衬底基板上的正投影。
  2. 根据权利要求1所述的阵列基板，其中，所述第二分支部的远离所述衬底基板的一侧具有第二过孔结构，且所述第二过孔结构在所述衬底基板上的正投影位于所述第二分支部的远离所述连接部的端部在所述衬底基板上的正投影之内，所述第二过孔结构与所述连接部之间的最小距离大于或者等于所述第一过孔结构与所述连接部之间的最小距离。
  3. 根据权利要求2所述的阵列基板，其中，所述第二过孔结构在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影之外。
  4. 根据权利要求1～3中任一项所述的阵列基板，其中，所述衬底基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分为一个整体结构。
  5. 根据权利要求4所述的阵列基板，其中，所述第一分支部和所述第二分支部均沿第一方向延伸，所述连接部沿与所述第一方向交叉的第二方向延伸，所述第一分支部、所述第二分支部和所述连接部围设形成开口区域，所述遮光层覆盖至少部分所述开口区域。
  6. 根据权利要求1～5中任一项所述的阵列基板，还包括设置在所述半导体层的远离所述衬底基板的一侧的第一金属层，所述第一金属层包括在所述第二方向上延伸的栅线，所述栅线包括第一栅极和第二栅极，所述第一栅极在所述衬底基板上的正投影和所述第一沟道区在所述衬底基板上的正投影交叠，所述第二栅极在所述衬底基板上的正投影和所述第二沟道区在所述衬底基板上的正投影交叠。
  7. 根据权利要求5所述的阵列基板，其中，在所述第一方向上所述遮光层和所述连接部之间具有间隙。
  8. 根据权利要求1～3中任一项所述的阵列基板，其中，所述衬底基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分分别为第一子遮光部和第二子遮光部，且所述第一子遮光部和所述第二子遮光部相互间隔。
  9. 根据权利要求8所述的阵列基板，其中，所述第一过孔结构在所述衬底基板上的正投影位于所述第一子遮光部在所述衬底基板上的正投影内，所述第二过孔结构在所述衬底基板上的正投影位于所述第二子遮光部在所述衬底基板上的正投影之外。
  10. 一种显示面板，包括相对设置的第一基板和第二基板，其中，
    所述第一基板包括衬底基板和层叠设置在所述衬底基板上的半导体层和遮光层；
    所述第二基板包括黑矩阵；
    所述半导体层包括相对设置的第一分支部和第二分支部，以及连接所述第一分支部和所述第二分支部的连接部，所述第一分支部包括第一沟道区，所述第二分支部包括第二沟道区，在所述第一分支部的远离所述衬底基板的一侧具有第一过孔结构，且所述第一过孔结构在所述衬底基板上的正投影位于所述第一分支部的远离所述连接部的端部在所述衬底基板上的正投影之内；
    所述遮光层在所述衬底基板上的正投影位于所述黑矩阵在所述衬底基板上的正投影之内，且至少覆盖所述第一沟道区和所述第一过孔结构在所述衬底基板上的正投影。
  11. 根据权利要求10所述的显示面板，其中，所述第二分支部的远离所述连接部的端部对应第二过孔结构，所述第二过孔结构相对于所述第一过孔结构更远离所述连接部。
  12. 根据权利要求11所述的显示面板，其中，所述遮光层的材料包括导电金属，所述黑矩阵在所述衬底基板上的正投影覆盖所述第二过孔结构在所述衬底基板上的正投影，且所述第二过孔结构在所述衬底基板上的正投影位于所述遮光层在所述衬底基板上的正投影之外。
  13. 根据权利要求10～12中任一项所述的显示面板，其中，所述第一基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分为一个整体结构。
  14. 根据权利要求13所述的显示面板，其中，所述第一分支部和所述第二分支部均沿第一方向延伸，所述连接部沿与所述第一方向交叉的第二方向延伸，所述第一分支部、所述第二分支部和所述连接部围设形成开口区域，所述遮光层覆盖至少部分所述开口区域。
  15. 根据权利要求10～14中任一项所述的显示面板，其中，所述第一基板还包括设置在所述半导体层的远离所述衬底基板的一侧的第一金属层，所述第一金属层包括在所述第二方向上延伸的栅线，所述栅线包括第一栅极和第二栅极，所述第一栅极在所述衬底基板上的正投影和所述第一沟道区在所述衬底基板上的正投影交叠，所述第二栅极在所述衬底基板上的正投影和所述第二沟道区在所述衬底基板上的正投影交叠。
  16. 根据权利要求15所述的显示面板，其中，所述第一栅极在所述衬底基板上的正投影在所述黑矩阵在所述衬底基板上的正投影之内，所述第二栅极在所述衬底基板上的正投影在所述黑矩阵在所述衬底基板上的正投影之内。
  17. 根据权利要求16所述的显示面板，其中，在所述第一方向上所述遮光层和所述连接部之间具有间隙。
  18. 根据权利要求14～17中任一项所述的显示面板，其中，所述遮光层的对应所述第一分支部的部分的靠近所述连接部的边缘在所述衬底基板上的正投影与所述黑矩阵的对应所述第一分支部的部分的靠近所述连接部的边缘在所述衬底基板上的正投影交叠。
  19. 根据权利要求11所述的显示面板，其中，所述遮光层的对应所述第一分支部的部分的最远离所述连接部的边缘在所述衬底基板上的正投影和所述黑矩阵的对应所述第一分支部的部分的最远离所述连接部的边缘在所述衬底基板上的正投影相交叠。
  20. 根据权利要求19所述的显示面板，其中，所述遮光层的远离所述连接部的边在所述衬底基板上的正投影包括位于所述第一过孔结构的远离所述连接部的一侧的第一部分和位于所述第二过孔结构的远离所述连接部的一侧的第二部分，所述第二部分在所述衬底基板上的正投影位于所述黑矩阵的最 远离所述第二过孔结构的边在所述衬底基板上的正投影之内。
  21. 根据权利要求19或20所述的显示面板，其中，所述第一基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分分别为第一子遮光部和第二子遮光部，且所述第一子遮光部和所述第二子遮光部相互间隔。
  22. 根据权利要求21所述的显示面板，其中，所述第一过孔结构在所述衬底基板上的正投影位于所述第一子遮光部在所述衬底基板上的正投影内，所述第二过孔结构在所述衬底基板上的正投影位于所述第二子遮光部在所述衬底基板上的正投影之外。
  23. 根据权利要求10所述的显示面板，其中，所述第二分支部的远离所述连接部的端部对应第二过孔结构，所述第二过孔结构和所述连接部之间的最大距离等于所述第一过孔结构和所述连接部之间的最大距离。
  24. 根据权利要求23所述的显示面板，其中，所述遮光层的材料包括非导电遮光材料，所述黑矩阵在所述衬底基板上的正投影和所述遮光层在所述衬底基板上的正投影均覆盖所述第二过孔结构在所述衬底基板上的正投影。
  25. 根据权利要求23或24所述的显示面板，其中，所述第一基板上设置有多个薄膜晶体管，所述遮光层的对应于不同的所述薄膜晶体管的部分相互间隔，所述遮光层的对应于同一个所述薄膜晶体管的所述第一沟道区和所述第二沟道区的部分为整体结构或者为相互间隔的结构。
  26. 一种显示装置，包括如权利要求1～9中任一项所述的阵列基板，或者如权利要求10～25中任一项所述的显示面板。
PCT/CN2024/095889 2023-06-30 2024-05-29 阵列基板、显示面板和显示装置 Ceased WO2025001706A1 (zh)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140204303A1 (en) * 2013-01-21 2014-07-24 Japan Display Inc. Liquid crystal display panel
CN107256872A (zh) * 2017-07-10 2017-10-17 厦门天马微电子有限公司 一种阵列基板及其制作方法、显示面板、显示装置
CN115373188A (zh) * 2021-05-20 2022-11-22 京东方科技集团股份有限公司 一种阵列基板、显示面板

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20140204303A1 (en) * 2013-01-21 2014-07-24 Japan Display Inc. Liquid crystal display panel
CN107256872A (zh) * 2017-07-10 2017-10-17 厦门天马微电子有限公司 一种阵列基板及其制作方法、显示面板、显示装置
CN115373188A (zh) * 2021-05-20 2022-11-22 京东方科技集团股份有限公司 一种阵列基板、显示面板

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