WO2025001587A1 - 像素电路及其驱动方法、显示面板、显示装置 - Google Patents

像素电路及其驱动方法、显示面板、显示装置 Download PDF

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Publication number
WO2025001587A1
WO2025001587A1 PCT/CN2024/093251 CN2024093251W WO2025001587A1 WO 2025001587 A1 WO2025001587 A1 WO 2025001587A1 CN 2024093251 W CN2024093251 W CN 2024093251W WO 2025001587 A1 WO2025001587 A1 WO 2025001587A1
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Prior art keywords
node
signal
voltage
reset
subcircuit
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2024/093251
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English (en)
French (fr)
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WO2025001587A9 (zh
Inventor
胡明
高文辉
郭永林
于子阳
张跳梅
王苗
谷泉泳
王世龙
张竞文
李健
吴建鹏
承天一
蒋志亮
宋江
郑海
青海刚
董向丹
张毅
汪锐
谢涛峰
邱海军
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to DE112024002785.7T priority Critical patent/DE112024002785T5/de
Priority to GB2515109.3A priority patent/GB2643358A/en
Priority to US18/993,122 priority patent/US12555539B2/en
Publication of WO2025001587A1 publication Critical patent/WO2025001587A1/zh
Publication of WO2025001587A9 publication Critical patent/WO2025001587A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0804—Sub-multiplexed active matrix panel, i.e. wherein one active driving circuit is used at pixel level for multiple image producing elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0257—Reduction of after-image effects

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, a display panel, and a display device.
  • OLED organic light emitting diodes
  • a pixel circuit comprising a driving subcircuit, a compensation subcircuit, a reset subcircuit and a storage subcircuit.
  • the driving subcircuit is coupled to the first node, the second node and the third node, and is configured to control the conduction and cutoff of the circuit between the second node and the third node under the control of the voltage of the first node.
  • the compensation subcircuit is coupled to the first scan signal terminal, the first node and the third node, and is configured to control the conduction and cutoff of the circuit between the first node and the third node in response to the first scan signal received at the first scan signal terminal.
  • the reset subcircuit is coupled to the first initialization signal terminal, the reset signal terminal and the first node.
  • the reset subcircuit is configured to transmit the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal received at the reset signal terminal.
  • the storage subcircuit is coupled to the first voltage signal terminal, the first node and the second node.
  • the storage subcircuit is configured to store voltages of the first node and the second node.
  • the storage subcircuit includes a first storage capacitor and a second storage capacitor, wherein a first plate of the first storage capacitor is connected to the first voltage signal terminal, and a second plate of the first storage capacitor is connected to the first node. A first plate of the second storage capacitor is connected to the first voltage signal terminal, and a second plate of the second storage capacitor is connected to the second node.
  • the compensation sub-circuit includes a first sub-transistor and a second sub-transistor connected in series, the first end of the first sub-transistor is connected to the first node, the second end of the first sub-transistor and/or the first end of the second sub-transistor is connected to a fourth node, the second end of the second sub-transistor is connected to the third node, and the first The control electrodes of the sub-transistor and the second sub-transistor are connected to the first scanning signal terminal.
  • the pixel circuit also includes a leakage prevention sub-circuit, which is coupled to the control signal terminal, the constant voltage terminal and the fourth node. The leakage prevention sub-circuit is configured to transmit the constant voltage signal received at the constant voltage terminal to the fourth node in response to the operating voltage of the control signal received at the control signal terminal.
  • the pixel circuit further includes a light emitting control subcircuit, the light emitting control subcircuit is coupled to the first voltage signal terminal, the enable signal terminal, the second node, the third node and the fifth node.
  • the fifth node is connected to the anode of the light emitting device.
  • the light emitting control subcircuit is configured to control the conduction and cutoff of the circuit between the first voltage signal terminal and the second node in response to the enable signal received at the enable signal terminal; and control the conduction and cutoff of the circuit between the third node and the fifth node; wherein the signals received at the enable signal terminal and the control signal terminal are the same.
  • the pixel circuit further includes a data writing subcircuit, the data writing subcircuit is coupled to the data signal terminal, the second scanning signal terminal and the second node.
  • the data writing subcircuit is configured to transmit the data signal received at the data signal terminal to the second node in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal; and transmit the data refresh signal received at the data signal terminal to the second node in response to the second operating voltage of the second scanning signal received at the second scanning signal terminal; the data refresh signal is the data signal received by the pixel circuits of other rows.
  • the cut-off time of the first working voltage of the second scanning signal is before the cut-off time of the working voltage of the first scanning signal.
  • the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is greater than or equal to one row scanning period.
  • the row scanning period is the duration of one working voltage of the second scanning signal.
  • the start time of the first working voltage of the second scanning signal is after the end time of the working voltage of the reset signal.
  • the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is greater than or equal to one row scanning period.
  • the row scanning period is the duration of one working voltage of the second scanning signal.
  • the transistor included in the compensation subcircuit is a P-type transistor.
  • the duration of the operating voltage of the first scanning signal is greater than or equal to 4 row scanning periods.
  • the voltage of the first row scanning period after the first scanning signal works is greater than the voltage of the second row scanning period after the first scanning signal works.
  • the row scanning period is the duration of an operating voltage of the second scanning signal.
  • the time of the first operating voltage of the second scanning signal coincides with the 2Nth row scanning period of the operating voltage of the first scanning signal, N ⁇ 2, and N is an integer.
  • the start and end time of the second operating voltage of the second scanning signal is between the end time of the operating voltage of the first scanning signal and the start time of the operating voltage of the enable signal. Moreover, the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period. The time interval between the start time of the working voltage of the second scanning signal is greater than or equal to one of the row scanning periods. The row scanning period is the duration of one working voltage of the second scanning signal.
  • the data writing sub-circuit is further configured to transmit the data holding signal received at the data signal terminal to the second node in response to a third operating voltage of the second scan signal received at the second scan signal terminal.
  • the reset subcircuit is further coupled to the second initialization signal terminal, the third scan signal terminal and the fifth node.
  • the reset subcircuit is further configured to transmit the second initialization signal received at the second initialization signal terminal to the fifth node under the control of the operating voltage of the third scan signal received at the third scan signal terminal.
  • the start time of the working voltage of the reset signal is before the start time of the working voltage of the first scanning signal. Moreover, the time interval between the start time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 3 row scanning periods. And/or; the end time of the working voltage of the reset signal is after the start time of the working voltage of the first scanning signal; and the time interval between the end time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 2 row scanning periods.
  • a method for driving a pixel circuit is provided.
  • the method for driving a pixel circuit is used to drive the pixel circuit as described in any of the above embodiments.
  • a display frame includes a refresh frame, and the refresh frame includes a first reset phase and a second reset phase.
  • the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal at the reset signal terminal. And, the storage subcircuit stores the voltage of the second node after the end of the previous frame.
  • the reset subcircuit transmits the first initialization signal received at the first initialization signal terminal to the first node in response to the operating voltage of the reset signal at the reset signal terminal.
  • the compensation subcircuit transmits the voltage of the first node to the third node in response to the operating voltage of the first scan signal received at the first scan signal terminal.
  • the driving subcircuit transmits the voltage of the third node to the second node under the control of the voltage of the first node.
  • the pixel circuit further includes a data writing subcircuit
  • the refresh frame further includes a first data writing phase and a second data writing phase.
  • the data writing subcircuit transmits the data signal received at the data signal terminal to the second node in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal, and writes the data signal into the storage subcircuit.
  • the driving subcircuit transmits the voltage of the second node to the third node under the control of the voltage of the first node.
  • the compensation subcircuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scanning signal received at the first scanning signal terminal.
  • the storage subcircuit discharges and transmits the stored data signal to the second node.
  • the driving subcircuit transmits the voltage of the second node to the third node under the control of the voltage of the first node.
  • the compensation sub-circuit transmits the voltage of the third node to the first node in response to the operating voltage of the first scan signal received at the first scan signal terminal.
  • the transistor included in the compensation subcircuit is a P-type transistor; the second reset phase includes at least 3 row scanning periods. In the second reset phase, the voltage of the first row scanning period after the first scanning signal works is greater than the voltage of the second row scanning period after the first scanning signal works.
  • the first data writing phase is located after the second reset phase and coincides with the 2Nth row scanning period after the start time of the second reset phase, N ⁇ 2, and N is an integer.
  • the pixel circuit includes a data writing subcircuit
  • the refresh frame further includes a third reset phase and a first light emitting phase
  • the third reset phase is located between the second data writing phase and the first light emitting phase.
  • the data writing subcircuit transmits the data refresh signal received at the data signal terminal to the second node in response to the second operating voltage of the second scan signal received at the second scan signal terminal.
  • the difference between the start time of the third reset phase and the end time of the second data writing phase is greater than or equal to one row scanning period. And/or, the difference between the end time of the third reset phase and the start time of the first light emitting phase is greater than or equal to one row scanning period.
  • the difference between the start time of the first reset phase and the start time of a frame in which the first reset phase is located is greater than or equal to two row scanning periods.
  • the pixel circuit includes a data writing subcircuit, a leakage prevention subcircuit, and a light emitting control subcircuit.
  • the pixel circuit has a first refresh frequency and a second refresh frequency, and the second refresh frequency is less than the first refresh frequency.
  • a display frame includes a refresh frame;
  • a display frame includes a refresh frame and at least one holding frame.
  • the holding frame includes a black insertion stage, a fourth reset stage, and a second light emitting stage.
  • the light emitting control subcircuit is configured to control the circuit transmitting the driving current signal to be cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal.
  • the data writing sub-circuit transmits the data holding signal received at the data signal terminal to the second node in response to the third operating voltage of the second scan signal received at the second scan signal terminal.
  • the light-emitting control subcircuit transmits the first voltage signal received at the first voltage signal terminal to the second node in response to the operating voltage of the enable signal received at the enable signal terminal; the driving subcircuit generates a driving current signal according to the voltage of the first node and the voltage of the second node; and the light-emitting control subcircuit transmits the driving current signal to the light-emitting device in response to the operating voltage of the enable signal received at the enable signal terminal; the leakage prevention subcircuit transmits the constant voltage signal received at the constant voltage terminal to the fourth node in response to the operating voltage of the control signal received at the control signal terminal.
  • the difference between the end time of the fourth resetting stage and the start time of the second light emitting stage is greater than or equal to one row scanning period.
  • a display panel in another aspect, includes a plurality of pixel circuits as described in any of the above embodiments.
  • the plurality of pixel circuits are arranged in M rows and N columns, each row includes N pixel circuits arranged along a first direction, each column includes M pixel circuits arranged along a second direction, M>1, N>1, and M and N are both integers.
  • the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.
  • the display panel further includes a first gate driving circuit, which includes M+Q cascaded first shift registers, from the first stage first shift register to the last stage first shift register, the M+Q first shift registers are respectively the 1st to the M+Qth first shift registers; each of the first shift registers includes a first signal output terminal.
  • the first scanning signal terminal of the P-th row pixel circuit is connected to the first signal output terminal of the P+Qth first shift register; the reset signal terminal of the P-th row pixel circuit is connected to the first output terminal of the Pth first shift register; P ⁇ M, Q>0, and P and Q are both integers.
  • the M rows of pixel circuits are respectively the 1st to the Mth rows of pixel circuits.
  • the display panel also includes a second gate driving circuit and a third gate driving circuit.
  • the second gate driving circuit includes M cascaded second shift registers, from the first stage second shift register to the last stage second shift register, and the M second shift registers are respectively the 1st to the Mth second shift registers.
  • Each of the second shift registers includes a second signal output terminal. Among them, the first scanning signal terminal of the Pth row pixel circuit is connected to the second signal output terminal of the Pth second shift register, P ⁇ M, and P is an integer;
  • the third gate driving circuit includes M cascaded third shift registers, from the first stage third shift register to the last stage third shift register, the M third shift registers are respectively the 1st to the Mth third shift registers.
  • Each of the third shift registers includes a third signal output terminal.
  • the reset signal terminal of the Pth row pixel circuit is connected to the third signal output terminal of the Pth third shift register, P ⁇ M, and P is an integer.
  • a display device comprising the display panel as described in any one of the above embodiments.
  • FIG1 is a structural diagram of a display device according to some embodiments.
  • FIG2 is a structural diagram of another display device according to some embodiments.
  • FIG3 is a cross-sectional view along the section line A-A' in FIG1;
  • FIG4 is a structural diagram of a display panel according to some embodiments.
  • FIG5 is a cross-sectional view along the section line C-C' in FIG4;
  • FIG6 is a structural block diagram of a pixel circuit according to some embodiments.
  • FIG7 is a circuit diagram of the pixel circuit shown in FIG6 ;
  • FIG8A is a block diagram of another pixel circuit according to some embodiments.
  • FIG8B is a structural block diagram of yet another pixel circuit according to some embodiments.
  • FIG9A is a circuit diagram of the pixel circuit shown in FIG8A ;
  • FIG9B is a circuit diagram of the pixel circuit shown in FIG8B ;
  • FIG10 is a structural diagram of a gate driving circuit of a display panel according to some embodiments.
  • FIG11 is a structural diagram of another gate driving circuit of a display panel according to some embodiments.
  • FIG12 is a structural diagram of a gate driving circuit of another display panel according to some embodiments.
  • FIG13 is a timing diagram of a pixel circuit according to some embodiments.
  • FIG. 14 is another timing diagram of a pixel circuit according to some embodiments.
  • FIG. 15 is yet another timing diagram of a pixel circuit according to some embodiments.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • Coupled and “connected” and their derivatives may be used.
  • the term “connected” should be understood in a broad sense.
  • “connected” can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • the term “coupled” means, for example, that two or more components are connected. There is direct physical contact or electrical contact.
  • the term “coupled” or “communicatively coupled” may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that” or “if [a stated condition or event] is detected” are optionally interpreted to mean “upon determining that” or “in response to determining that” or “upon detecting [a stated condition or event]” or “in response to detecting [a stated condition or event],” depending on the context.
  • “about,” “approximately,” or “substantially” includes the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurement in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ⁇ 30%, ⁇ 20%, ⁇ 10%, ⁇ 5% of the stated value.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and the area of regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be construed as being limited to the drawings shown herein.
  • the shapes of the regions are not limited to the shapes of the devices, but include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the example embodiments.
  • first element may be directly or indirectly opposed to the second element.
  • first element and the second element may be understood to be indirectly opposed to each other although still opposed to each other.
  • the transistors used may be thin film transistors (TFT), field effect transistors (MOS) or other switching devices with the same characteristics.
  • TFT thin film transistors
  • MOS field effect transistors
  • the embodiments of the present disclosure are described using thin film transistors as examples.
  • the control electrode of each thin film transistor used is the gate of the transistor, the first electrode is one of the source and drain of the thin film transistor, and the second electrode is the other of the source and drain of the thin film transistor. Since the source and drain of the thin film transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the thin film transistor in the embodiments of the present disclosure can be structurally indistinguishable.
  • the first electrode of the transistor is the source and the second electrode is the drain; exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.
  • the capacitor may be a capacitor device manufactured separately through a process, for example, a capacitor device is realized by manufacturing a special capacitor electrode, and each capacitor electrode of the capacitor may be realized by a metal layer, a semiconductor layer (for example, doped polysilicon), etc.
  • the capacitor may also be a parasitic capacitor between transistors, or realized by the transistor itself and other devices and circuits, or realized by utilizing the parasitic capacitor between the circuits of the circuit itself.
  • the first node, the second node, the first control node, the second control node and other nodes do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.
  • operating voltage refers to a voltage that can turn on the operated transistor included therein; correspondingly, “non-operating voltage” refers to a voltage that cannot turn on the operated transistor included therein.
  • low level refers to a voltage that can turn on the operated P-type transistor included therein, but cannot turn on the operated N-type transistor included therein (i.e., the N-type transistor is turned off);
  • high level refers to a voltage that can turn on the operated N-type transistor included therein, but cannot turn on the operated P-type transistor included therein (ie, the P-type transistor is turned off).
  • a display device 1000 which may be any device that displays an image, whether in motion (eg, video) or fixed (eg, still image), and whether text or text.
  • the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.
  • a display function such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a wearable device, a virtual reality (VR) device, etc.
  • PDA personal digital assistant
  • VR virtual reality
  • the display device 1000 may be a portable display product; for example, the display device 1000 may be the mobile phone shown in Fig. 1.
  • the display device 1000 may be a wearable device; for example, the display device 1000 may be the watch shown in Fig. 2.
  • the following takes the display device 1000 as the mobile phone shown in FIG. 1 as an example to schematically illustrate some embodiments of the present disclosure, but the implementation of the present disclosure is not limited thereto.
  • a display device 1000 includes a display panel 100 .
  • the display panel 100 includes a light-emitting side and a non-light-emitting side that are arranged opposite to each other.
  • the light-emitting side is a side of the display panel 100 used for display, that is, the upper side in FIG. 3 .
  • the display device 1000 may further include a housing 200 , a cover plate 300 , a circuit board 400 and other electronic components.
  • the cover plate 300 may be a single-layer glass cover plate, or may include a stack of multiple layers of sub-cover plates, which is not specifically limited in the embodiment of the present disclosure.
  • the longitudinal section of the housing 200 may be, for example, U-shaped, the display panel 100 and the circuit board 400 are disposed in the housing 200, and the cover plate 300 is disposed at the opening of the housing 200.
  • the circuit board 400 is disposed on a side of the display panel 100 away from the cover plate 300, and the circuit board 400 is connected to the display panel 100 to provide the display panel 100 with the required display signal.
  • the display panel 100 may be of various types and may be selected according to actual needs.
  • the display panel 100 may be an organic light emitting diode (OLED) display panel, a quantum dot light emitting diode (QLED) display panel, etc., which is not specifically limited in the embodiments of the present disclosure.
  • OLED organic light emitting diode
  • QLED quantum dot light emitting diode
  • the display panel 100 includes a display substrate 110 and an encapsulation layer 120 for encapsulating the display substrate 110 .
  • the encapsulation layer 120 may be an encapsulation film or an encapsulation substrate. The present disclosure will not specifically describe the encapsulation layer 120 in detail. limited.
  • the display panel 100 has a display area A, where the display area A is a region for displaying an image and is configured to provide a plurality of sub-pixels P.
  • the display panel 100 includes a substrate 11 and a plurality of sub-pixels P disposed on one side of the substrate 11 and located in a display area A. As shown in FIG. 4
  • the substrate 11 There are many types of the substrate 11, which can be selected according to actual needs.
  • the substrate 11 may be a rigid substrate.
  • the rigid substrate may be a glass substrate or a polymethyl methacrylate (PMMA) substrate.
  • the substrate 11 may be a flexible substrate.
  • the flexible substrate may be a polyethylene terephthalate (PET) substrate, a polyethylene naphthalate (PEN) substrate, or a polyimide (PI) substrate.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PI polyimide
  • each sub-pixel P includes a light emitting device 10 and a pixel circuit 20 .
  • the pixel circuit 20 includes a plurality of thin film transistors 30 .
  • the thin film transistor 30 includes a semiconductor channel 31 , a source electrode 32 , a drain electrode 33 , and a gate electrode 34 .
  • the source electrode 32 and the drain electrode 33 are both in contact with the semiconductor channel 31 .
  • the light-emitting device 10 includes a first electrode 11, a light-emitting functional layer 12 and a second electrode 13.
  • the first electrode 11 is electrically connected to a source 32 or a drain 33 of a thin-film transistor 30.
  • FIG5 illustrates the electrical connection between the first electrode 11 and the drain 33 of the thin-film transistor 30 as an example.
  • the above-mentioned light-emitting functional layer 12 may include only a light-emitting layer, or, in addition to the light-emitting layer, may also include at least one of an electron transport layer (ETL), an electron injection layer (EIL), a hole transport layer (HTL) and a hole injection layer (HIL).
  • ETL electron transport layer
  • EIL electron injection layer
  • HTL hole transport layer
  • HIL hole injection layer
  • display devices use display panels with variable refresh rates to meet users' needs for low power consumption and high refresh rates.
  • the frame rate of the display panel is reduced, making the human eye more sensitive to the flicker of the display panel, causing the human eye to perceive flickering on the display screen.
  • the hysteresis effect refers to an uncertainty in the electrical characteristics of the driving transistor under a certain bias voltage, that is, the magnitude of the current of the driving transistor is not only related to the current bias voltage, but also to the bias state in the previous period.
  • some embodiments of the present disclosure provide a pixel circuit 20, including a driving subcircuit 21, a compensation subcircuit 22, and a The compensation sub-circuit 22, the reset sub-circuit 23 and the storage sub-circuit 24.
  • the driving subcircuit 21 is coupled to the first node N1, the second node N2, and the third node N3.
  • the driving subcircuit 21 is configured to control the conduction and cutoff of the circuit between the second node N2 and the third node N3 under the control of the voltage of the first node N1; and generate a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.
  • the driving subcircuit 21 includes an eighth transistor T8 (i.e., the driving transistor mentioned above), a first electrode of the eighth transistor T8 is connected to the second node N2, a second electrode of the eighth transistor T8 is connected to the third node N3, and a control electrode of the eighth transistor T8 is connected to the first node N1.
  • an eighth transistor T8 i.e., the driving transistor mentioned above
  • a first electrode of the eighth transistor T8 is connected to the second node N2
  • a second electrode of the eighth transistor T8 is connected to the third node N3
  • a control electrode of the eighth transistor T8 is connected to the first node N1.
  • the compensation sub-circuit 22 is coupled to the first scan signal terminal GATE1, the first node N1 and the third node N3.
  • the compensation sub-circuit 22 is configured to control the conduction and cutoff of the circuit between the first node N1 and the third node N3 in response to the first scan signal received at the first scan signal terminal GATE1.
  • the compensation sub-circuit 22 includes a first sub-transistor T1-1 and a second sub-transistor T1-2 connected in series, the first end of the first sub-transistor T1-1 is connected to the first node N1, the second end of the first sub-transistor T1-1 and/or the first end of the second sub-transistor T1-2 is connected to the fourth node N4, the second end of the second sub-transistor is connected to the third node N3, and the control electrodes of the first sub-transistor T1-1 and the second sub-transistor T1-2 are connected to the first scan signal terminal GATE1.
  • the compensation sub-circuit 22 may also include three, four or more transistors connected in series, which is not specifically limited in the embodiment of the present disclosure.
  • the compensation sub-circuit 22 including the first sub-transistor T1-1 and the second sub-transistor T1-2 connected in series as an example, but the implementation of the present disclosure is not limited to this, and it can also be considered that the compensation sub-circuit 22 includes three, four or more transistors connected in series, as long as the same technical concept is applied.
  • the reset sub-circuit 23 is coupled to the first initialization signal terminal VINIT1, the reset signal terminal RESET, and the first node N1.
  • the reset sub-circuit 23 is configured to transmit the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 in response to the operating voltage of the reset signal received at the reset signal terminal RESET to reset the voltage of the first node N1.
  • the reset subcircuit 23 includes a plurality of fifth transistors T5 connected in series, one end of the plurality of fifth transistors T5 is connected to the first initialization signal terminal VINIT1, the other end is connected to the first node N1, and the control electrode of each fifth transistor T5 is connected to the reset signal terminal RESET.
  • the reset sub-circuit 23 includes two fifth transistors T5 connected in series, and the two fifth transistors T5 form a double-gate transistor to reduce leakage current.
  • the start time of the working voltage of the reset signal is before the start time of the working voltage of the first scanning signal; and the time interval between the start time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 3 row scanning periods.
  • the time interval between the start time of the voltage and the start time of the working voltage of the first scanning signal is 8 row scanning periods for illustration.
  • the cut-off time of the working voltage of the reset signal is after the start time of the working voltage of the first scanning signal.
  • the time interval between the cut-off time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is greater than or equal to 2 row scanning periods.
  • FIG. 13 takes the cut-off time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal as an example for illustration, that is, the time interval between the cut-off time of the working voltage of the reset signal and the start time of the working voltage of the first scanning signal is 3 row scanning periods.
  • the storage sub-circuit 24 is coupled to the first voltage signal terminal VDD, the first node N1 and the second node N2.
  • the storage sub-circuit 24 is configured to store the voltages of the first node N1 and the second node N2.
  • the storage subcircuit 24 includes a first storage capacitor C1 and a second storage capacitor C2, wherein a first plate of the first storage capacitor C1 is connected to the first voltage signal terminal VDD, and a second plate of the first storage capacitor C1 is connected to the first node N1.
  • a first plate of the second storage capacitor C2 is connected to the first voltage signal terminal VDD, and a second plate of the second storage capacitor C2 is connected to the second node N2.
  • the storage subcircuit 24 can store the voltage at the second node N2 after the previous frame of display ends, so that the second node N2 maintains a relatively stable potential corresponding to the first voltage signal, thereby causing the first node N1 and the third node N3 of the driving subcircuit 21 to generate a stable and large bias voltage, thereby improving the hysteresis characteristics of the driving subcircuit 21, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of the human eye being able to perceive flickering in the display screen.
  • the second storage capacitor C2 can store the voltage at the second node N2 (i.e., the first electrode of the eighth transistor T8) after the previous frame of display ends, so that the second node N2 maintains a relatively stable potential corresponding to the first voltage signal, thereby causing the first electrode (second node N2) and the control electrode (third node N3) of the eighth transistor T8 to generate a stable and large bias voltage, thereby improving the hysteresis characteristics of the eighth transistor T8, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem of flickering in the display screen that can be perceived by the human eye.
  • the pixel circuit 20 further includes a leakage prevention sub-circuit 25 .
  • the leakage prevention sub-circuit 25 is coupled to the control signal terminal K, the constant voltage terminal VC and the fourth node N4.
  • the leakage prevention sub-circuit 25 is configured to transmit the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.
  • the voltage of the constant voltage signal is -7V to 7V.
  • the voltage of the constant voltage signal is any one of -7V, -6V, -5V, -4V, -3V, -2V, -1V, 0V, 1V, 2V, 3V, 4V, 5V, 6V and 7V.
  • a voltage value with a better anti-leakage effect can be obtained as the actual voltage value of the constant voltage signal, which is not specifically limited in the embodiments of the present disclosure.
  • the leakage prevention sub-circuit 25 includes a second transistor T2, a first electrode of the second transistor T2 is connected to the constant voltage terminal VC, a second electrode of the second transistor T2 is connected to the fourth node N4, and the second transistor T2 The control electrode is connected to the control signal terminal K.
  • the anti-leakage sub-circuit 25 can respond to the operating voltage of the control signal received at the control signal terminal K, and transmit the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, so as to reduce the voltage difference between the fourth node N4 and the first node N1, and reduce the risk of leakage of the first node N1, thereby reducing the flicker value of the display panel 100 and improving the problem that the human eye can perceive flickering in the display screen.
  • the pixel circuit 20 further includes a light emission control subcircuit 26 .
  • the light emitting control subcircuit 26 is coupled to the first voltage signal terminal VDD, the enable signal terminal EM, the second node N2, the third node N3, and the fifth node N5.
  • the light emitting control subcircuit 26 is configured to control the conduction and cutoff of the circuit between the first voltage signal terminal VDD and the second node N2 in response to the enable signal received at the enable signal terminal EM; and control the conduction and cutoff of the circuit between the third node N3 and the fifth node N5.
  • the first voltage signal may be a signal of the positive electrode of a DC power supply.
  • the first voltage signal may be 5V.
  • the fifth node N5 is connected to the anode of the light emitting device 10 so that the driving current signal can be transmitted to the light emitting device 10 .
  • the light emitting control subcircuit 26 includes a third transistor T3 and a fourth transistor T4.
  • a first electrode of the third transistor T3 is connected to the first voltage signal terminal VDD
  • a second electrode of the third transistor T3 is connected to the second node N2
  • a control electrode of the third transistor T3 is connected to the enable signal terminal EM.
  • a first electrode of the fourth transistor T4 is connected to the third node N3, a second electrode of the fourth transistor T4 is connected to the fifth node N5, and a control electrode of the fourth transistor T4 is connected to the enable signal terminal EM.
  • the signals received at the enable signal terminal EM and the control signal terminal K are the same.
  • the enable signal terminal EM and the control signal terminal K can be connected to the same signal line, such as a gate line mentioned below, to simplify the circuit structure.
  • the anti-leakage subcircuit 25 responds to the operating voltage of the control signal received at the enable signal terminal EM, and transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4, so as to reduce the voltage difference between the fourth node N4 and the first node N1, reduce the risk of leakage of the first node N1, thereby reducing the flicker value of the display panel 100, and improving the problem that the human eye can perceive flickering on the display screen.
  • the pixel circuit 20 further includes a data writing subcircuit 27 .
  • the data writing subcircuit 27 is coupled to the data signal terminal DATA, the second scanning signal terminal GATE2, and the second node N2.
  • the data writing subcircuit 27 is configured to transmit the data signal received at the data signal terminal DATA to the second node N2 in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal GATE2; and transmit the data refresh signal received at the data signal terminal DATA to the second node N2 in response to the second operating voltage of the second scanning signal received at the second scanning signal terminal GATE2.
  • the data refresh signal is a data signal received by the pixel circuit 20 of other rows, for example, a data signal received by the pixel circuit 20 of the next adjacent row.
  • first operating voltage and the second operating voltage of the second scanning signal may be the same.
  • the timings of the first working voltage and the second working voltage are different.
  • the cut-off time of the first working voltage of the second scanning signal is before the cut-off time of the working voltage of the first scanning signal. Moreover, the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is greater than or equal to one row scanning period H.
  • the row scanning period H is the duration of a working voltage of the second scanning signal.
  • the time interval between the cut-off time of the first working voltage of the second scanning signal and the cut-off time of the working voltage of the first scanning signal is 5 row scanning periods H.
  • the start time of the first working voltage of the second scanning signal is after the end time of the working voltage of the reset signal.
  • the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is greater than or equal to one row scanning period H.
  • the time interval between the start time of the first working voltage of the second scanning signal and the end time of the working voltage of the reset signal is 2 row scanning periods H.
  • the transistor included in the compensation subcircuit 22 is a P-type transistor.
  • the duration of the working voltage of the first scanning signal is greater than or equal to 4 row scanning periods H.
  • the voltage of the first row scanning period H after the first scanning signal works is greater than the voltage of the second row scanning period H after the first scanning signal works.
  • the row scanning period H is the duration of a working voltage of the second scanning signal. In other words, the stability of the first scanning signal output in the even-numbered row scanning period H is greater than the stability of the odd-numbered row scanning period H.
  • the voltage of the first row scanning period H after the first scanning signal is working can be understood as the first period after the effective level of the first scanning signal begins to be input, that is, the first row scanning period H after the first falling edge of the first scanning signal terminal GATE1 in Figure 13, that is, the first row scanning period H counted from left to right in the second reset stage P12; or, it can be understood as the first period after the level used to turn on the first sub-transistor T1-1 in Figure 9A is input.
  • the voltage of the second row scanning period H after the first scanning signal works can be understood as the second period after the effective level of the first scanning signal starts to be input, that is, the second row scanning period H after the first falling edge of the first scanning signal terminal GATE1 in Figure 13, that is, the second row scanning period H counted from left to right in the second reset stage P12; or, it can be understood as the second period after the level used to turn on the first sub-transistor T1-1 in Figure 9A is input.
  • the time of the first working voltage of the second scanning signal coincides with the 2Nth row scanning period H of the working voltage of the first scanning signal, N ⁇ 2, and N is an integer.
  • the start and end time of the second operating voltage of the second scan signal is located between the end time of the operating voltage of the first scan signal and the start time of the operating voltage of the enable signal.
  • the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is greater than or equal to one row scanning period H.
  • the time interval between the end time of the second operating voltage of the second scanning signal and the start time of the operating voltage of the enable signal is greater than or equal to one row scanning period H.
  • the time interval between the start time of the second operating voltage of the second scanning signal and the end time of the operating voltage of the first scanning signal is 2 row scanning periods H.
  • the time interval between the end time of the second operating voltage of the second scanning signal and the start time of the operating voltage of the enable signal is 1 row scanning period H.
  • the data writing subcircuit 27 is further configured to transmit the data holding signal received at the data signal terminal DATA to the second node N2 in response to the third operating voltage of the second scan signal received at the second scan signal terminal GATE2.
  • the voltage range of the data holding signal is 0V to V GMP , where V GMP refers to the black state voltage of the sub-pixel P.
  • V GMP refers to the black state voltage of the sub-pixel P.
  • the black state voltage is when the target gray scale of a sub-pixel P is 0, the black state voltage is directly used as the driving voltage corresponding to the sub-pixel P, so that the corresponding sub-pixel does not emit light.
  • the voltage of the data hold signal ranges from 0V to 7V, for example, the voltage of the data hold signal is any one of 0V, 1V, 2V, 3V, 4V, 5V, 6V and 7V.
  • the voltage value of the data hold signal can be determined based on experimental tests, and a voltage value with a lower flicker value can be used as the actual voltage value of the data hold signal, which is not specifically limited in the embodiments of the present disclosure.
  • first operating voltage, the second operating voltage and the third operating voltage of the second scanning signal may be the same in magnitude, but the timings of the first operating voltage, the second operating voltage and the third operating voltage are different.
  • the data writing sub-circuit 27 includes a seventh transistor T7 , a first electrode of the seventh transistor T7 is connected to the data signal terminal DATA, a second electrode of the seventh transistor T7 is connected to the second node N2 , and a control electrode of the seventh transistor T7 is connected to the second scan signal terminal GATE2 .
  • the reset subcircuit 23 is also coupled to the second initialization signal terminal VININT2, the third scan signal terminal GATE3 and the fifth node N5.
  • the reset subcircuit 23 is also configured to, under the control of the operating voltage of the third scan signal received at the third scan signal terminal GATE3, transmit the second initialization signal received at the second initialization signal terminal VINIT to the fifth node N5 to reset the anode (fifth node N5) of the light emitting device 10.
  • the reset subcircuit 23 further includes a sixth transistor T6, a first electrode of the sixth transistor T6 is connected to the second initialization signal terminal VINIT2, a second electrode of the sixth transistor VINIT2 is connected to the fifth node N5, and a control electrode of the sixth transistor T6 is connected to the third scan signal terminal GATE3.
  • control electrode of the sixth transistor T6 that resets the anode (fifth node N5) of the light-emitting device 10 can be controlled by the third scan signal terminal GATE3, so that the anode (fifth node N5) of the light-emitting device 10 can be reset to improve the light-emitting efficiency.
  • the third scan signal terminal GATE3 can be connected to the same signal line as the second scan signal terminal GATE2, that is, the signals received at the third scan signal terminal GATE3 and the second scan signal terminal GATE2 can be the same.
  • the scan signal terminal GATE3 may also be called the second scan signal terminal GATE2.
  • the reset sub-circuit 23 is coupled to the second initialization signal terminal VININT2, the second scan signal terminal GATE2 and the fifth node N5.
  • the reset sub-circuit 23 is configured to, under the control of the operating voltage of the third scan signal received at the second scan signal terminal GATE2, transmit the second initialization signal received at the second initialization signal terminal VINIT to the fifth node N5 to reset the anode (fifth node N5) of the light emitting device 10.
  • the reset subcircuit 23 further includes a sixth transistor T6 , a first electrode of the sixth transistor T6 is connected to the second initialization signal terminal VINIT2 , a second electrode of the sixth transistor VINIT2 is connected to the fifth node N5 , and a control electrode of the sixth transistor T6 is connected to the second scan signal terminal GATE2 .
  • control electrode of the sixth transistor T6 for resetting the anode (fifth node N5) of the light-emitting device 10 and the control electrode of the seventh transistor T7 can both be controlled by the second scanning signal terminal GATE2, so that during the data writing process, the anode (fifth node N5) of the light-emitting device 10 can be reset at the same time, simplifying the circuit structure.
  • all pixel circuits 20 are arranged in multiple rows and columns, each row includes multiple pixel circuits 20 arranged along a first direction X, and each column includes multiple pixel circuits 20 arranged along a second direction Y.
  • the first direction X is substantially perpendicular to the second direction Y.
  • first direction X may be, for example, a row direction in which the plurality of pixel circuits 20 are arranged
  • second direction Y may be, for example, a column direction in which the plurality of pixel circuits 20 are arranged.
  • a plurality of pixel circuits 20 arranged along a first direction X is referred to as a row of pixel circuits 20, and a plurality of pixel circuits 20 arranged along a second direction Y is referred to as a column of pixel circuits 20.
  • the display panel 100 further includes a plurality of gate lines GL, a plurality of data lines DL, a plurality of first power lines VDL, a plurality of first initialization signal lines VL1, a plurality of second initialization signal lines VL2, and a plurality of constant voltage signal lines VCL.
  • each gate line GL extends substantially along the first direction X, and is configured to transmit any one of a first scan signal, a second scan signal, a reset signal, and an enable signal (control signal).
  • One gate line GL for example, can be connected to any one of a first scan signal terminal GATE1, a second scan signal terminal GATE2, a reset signal terminal RESET, and an enable signal terminal EN (control signal terminal K) of a row of pixel circuits 20.
  • the data line DL substantially extends along the second direction Y and is configured to transmit a data signal.
  • one data line DL may be connected to a data signal terminal DATA of a column of pixel circuits 20 .
  • the first power line VDL extends substantially along the second direction Y and is configured to transmit a first power voltage signal.
  • one first power line VDL may be connected to the first voltage signal terminal VDD of a column of pixel circuits 20 .
  • the first initialization signal line VL1 extends substantially along the first direction X and is configured to transmit a first Initialization signal:
  • a first initialization signal line VL1 may be connected to a first initialization signal terminal VINIT1 of a row of pixel circuits 20, for example.
  • the second initialization signal line VL2 extends substantially along the first direction X and is configured to transmit a second initialization signal.
  • One second initialization signal line VL2 may be connected to the second initialization signal terminal VINIT2 of a row of pixel circuits 20 , for example.
  • the constant voltage signal line VCL extends substantially along the second direction Y and is configured to transmit a constant voltage signal.
  • one constant voltage signal line VCL may be connected to the constant voltage signal terminal VC of a row of pixel circuits 20 .
  • the display panel 100 includes a substrate 11, a semiconductor layer ACT, a first gate insulating layer GI1, a first gate conductive layer GT1, a second gate insulating layer GI2, a second gate conductive layer GT2, an interlayer insulating layer ILD, a first source and drain conductive layer SD1, a first planar layer PLN1, a second source and drain conductive layer SD2 and a second planar layer PLN2.
  • the semiconductor channel 31 of the transistor may be located, for example, in the semiconductor layer ACT, and the gate line GL, the gate 34 of the transistor and the first plate of the capacitor (the first capacitor C1 and the second capacitor C2) may be located, for example, in the first gate conductive layer GT1.
  • the second plate of the capacitor (the first capacitor C1 and the second capacitor C2), the first initialization signal line VL1 and the second initialization signal line may be located, for example, in the second gate conductive layer GT2.
  • the source 32, the drain 33, the first power line VDL and the constant voltage signal line VCL of the transistor may be located, for example, in the first source-drain conductive layer SD1.
  • the data line DL may be located, for example, in the second source-drain conductive layer SD2.
  • the display panel 100 further includes a pixel defining layer PDL, the pixel defining layer PDL is provided with a plurality of openings, and one light emitting device 10 is located in one opening.
  • the display panel 100 further includes a spacer PS, which can be disposed between the pixel defining layer PDL and the first electrode 11 of the light-emitting device 10 to support the mask during the process so that the gap between the mask and the pixel defining layer PDL is uniform.
  • a spacer PS which can be disposed between the pixel defining layer PDL and the first electrode 11 of the light-emitting device 10 to support the mask during the process so that the gap between the mask and the pixel defining layer PDL is uniform.
  • the display panel 100 further has a peripheral area B, and the peripheral area B is disposed on at least one side of the display area A.
  • FIG. 4 takes the example that the peripheral area B is disposed around the display area A.
  • the peripheral area B includes a first border area B1, a second border area B2, a third border area B3 and a fourth border area B4.
  • first border area B1 and the second border area B2 are located on two opposite sides of the display area A
  • second direction Y the third border area B3 and the fourth border area B4 are located on the other opposite sides of the display area A.
  • the peripheral area B is a region where no image is displayed and is configured to set up a gate driving circuit 130 and a source driving circuit 140 and the like.
  • the gate driving circuit 130 includes a first gate driving circuit 131, and the first gate driving circuit 131 includes a plurality of cascaded first shift registers RS1, each of which includes a first signal output terminal, and the first signal output terminal of each first shift register RS1 is connected to at least one row of pixel circuits 20
  • the first scan signal terminal GATE1 and/or the reset signal terminal RESET are connected.
  • a plurality of pixel circuits 20 are arranged in M rows and N columns, each row includes N pixel circuits 20 arranged along the first direction X, and each column includes M pixel circuits 20 arranged along the second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20.
  • FIG10 takes 2480 rows of pixel circuits 20 as an example for illustration.
  • the first gate driving circuit 131 includes M+Q cascaded first shift registers RS1, from the first stage first shift register RS1 to the last stage first shift register RS1, the M+Q first shift registers RS1 are respectively the 1st to the M+Qth first shift registers RS1.
  • FIG10 takes Q equal to 8 as an example for illustration.
  • the first scanning signal terminal GATE1 of the P-th row pixel circuit 20 is connected to the first signal output terminal of the P+Q-th first shift register RS1.
  • the reset signal terminal RESET of the P-th row pixel circuit 20 is connected to the first signal output terminal of the P-th first shift register RS1.
  • P ⁇ M, Q>0, and P and Q are both integers.
  • the first gate driving circuit 131 can provide the first scanning signal and the reset signal to the first scanning signal terminal GATE1 and the reset signal terminal RESET of all the pixel circuits 20.
  • the first scanning signal terminal GATE1 and the reset signal terminal RESET of one pixel circuit 20 can share one gate driving circuit 130, which is beneficial to the narrow frame design of the display device 1000 (see FIG. 1).
  • the first gate driving circuit 131 is disposed on one side of the display area A (see FIG. 4 ), and drives each row of pixel circuits 20 row by row in sequence from a single side of the display area A (see FIG. 4 ), i.e., single-sided driving.
  • first gate driving circuits 131 are arranged on opposite sides of the display area A (see FIG4 ), and through the two first gate driving circuits 131, each row of pixel circuits 20 is driven row by row from opposite sides of the display area A (see FIG4 ) at the same time, i.e., double-sided driving.
  • the gate driving circuit 130 includes a second gate driving circuit 132 and a third gate driving circuit 133 .
  • the second gate driving circuit 132 includes a plurality of cascaded second shift registers RS2 , each second shift register RS2 includes a second signal output terminal, and the second signal output terminal of each second shift register RS2 is connected to the first scanning signal terminal GATE1 of at least one row of pixel circuits 20 .
  • a plurality of pixel circuits 20 are arranged in M rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20.
  • FIG12 takes 2480 rows of pixel circuits 20 as an example for illustration.
  • the second gate drive circuit 132 includes M cascaded second shift registers RS2, from the first stage second shift register The M second shift registers RS2 are respectively the 1st to the Mth second shift registers RS2. Each second shift register RS2 includes a second signal output terminal.
  • the first scanning signal terminal GATE1 of the pixel circuit 20 in the P-th row is connected to the second signal output terminal of the P-th second shift register RS2, P ⁇ M, and P is an integer.
  • the third gate driving circuit 133 includes a plurality of cascaded third shift registers RS3, each of which includes a third signal output terminal, and the third signal output terminal of each third shift register RS3 is connected to the reset signal terminal RESET of at least one row of pixel circuits 20.
  • a plurality of pixel circuits 20 are arranged in M rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20.
  • FIG12 takes 2480 rows of pixel circuits 20 as an example for illustration.
  • the third gate driving circuit 133 includes M cascaded third shift registers RS3, from the first stage third shift register RS3 to the last stage third shift register RS3, the M third shift registers RS3 are respectively the first to the Mth third shift registers RS3.
  • Each third shift register RS3 includes a third signal output terminal.
  • the reset signal terminal RESET of the pixel circuit in the Pth row is connected to the third signal output terminal of the Pth third shift register RS3, P ⁇ M, and P is an integer.
  • the second gate driving circuit 132 can provide the first scanning signal to the first scanning signal terminal GATE1 of all the pixel circuits 20, and the third gate driving circuit 133 can provide the reset signal to the reset signal terminal RESET of all the pixel circuits 20.
  • the ratio of the duration of the first scanning signal received by the first scanning signal terminal GATE1 of the pixel circuit 20 and the duration of the reset signal received by the reset signal terminal RESET can be adjusted arbitrarily, which is conducive to improving the afterimage performance, reducing flicker, and thus improving the display quality.
  • the second gate driving circuit 132 and the third gate driving circuit 133 are respectively arranged on opposite sides of the display area A (see FIG4 ), that is, the second gate driving circuit 132 and the third gate driving circuit 133 are respectively arranged in the first border area B1 (see FIG4 ) and the second border area B2 (see FIG4 ), and each row of pixel circuits 20 are driven row by row from a single side of the display area A (see FIG4 ), which is beneficial to reducing the border of the display device 1000 (see FIG1 ) and improving the screen-to-body ratio.
  • the gate driving circuit 130 further includes a fourth gate driving circuit 134 .
  • the fourth gate driving circuit 134 includes a plurality of cascaded fourth shift registers RS4 , each of which includes a fourth signal output terminal , and the fourth signal output terminal of each fourth shift register RS4 is connected to the enable signal terminal EM of at least one row of pixel circuits 20 .
  • a plurality of pixel circuits 20 are arranged in M rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, And M and N are both integers. And, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the first to Mth rows of pixel circuits 20.
  • FIG10 takes 2480 rows of pixel circuits 20 as an example for illustration.
  • the fourth gate driving circuit 134 includes M cascaded fourth shift registers RS4, from the first stage fourth shift register RS4 to the last stage fourth shift register RS4, the M fourth shift registers RS4 are respectively the first to the Mth fourth shift registers RS4.
  • Each of the fourth shift registers RS4 includes a fourth signal output terminal.
  • the enable signal terminal EM of the P-th row pixel circuit 20 is connected to the fourth signal output terminal of the P-th fourth shift register RS4 of the fourth gate driving circuit 134, P ⁇ M, and P is an integer.
  • the first gate driving circuit 131 and the fourth gate driving circuit 134 are respectively arranged in the first border area B1 (see Figure 4) and the second border area B2 (see Figure 4), which is conducive to the narrow border design of the display device 1000 (see Figure 1).
  • the odd-numbered fourth shift register RS4 and the even-numbered fourth shift register RS4 can be respectively arranged in the first border area B1 and the second border area B2 to form a cross drive, so as to make full use of the areas of the first border area B1 and the second border area B2 and improve the uniformity of the picture display.
  • the odd-numbered fourth shift register RS4 and the even-numbered fourth shift register RS4 are respectively arranged in the first border area B1 and the second border area B2 to form a cross drive to fully utilize the areas of the first border area B1 and the second border area B2 to improve the uniformity of the picture display.
  • the gate driving circuit 130 further includes a fifth gate driving circuit 135 .
  • the fifth gate driving circuit 135 includes a plurality of cascaded fifth shift registers RS5 , each fifth shift register RS5 includes a fifth signal output terminal , and the fifth signal output terminal of each fifth shift register RS5 is connected to the second scanning signal terminal GATE2 of at least one row of pixel circuits 20 .
  • a plurality of pixel circuits 20 are arranged in M rows and N columns, each row includes N pixel circuits 20 arranged along a first direction X, and each column includes M pixel circuits 20 arranged along a second direction Y, M>1, N>1, and M and N are both integers. Also, along the second direction Y, from the first row of pixel circuits 20 to the last row of pixel circuits 20, the M rows of pixel circuits 20 are respectively the 1st to the Mth rows of pixel circuits 20.
  • FIG12 takes 2480 rows of pixel circuits 20 as an example for illustration.
  • the fifth gate driving circuit 135 includes M cascaded fifth shift registers RS5, from the first stage fifth shift register RS5 to the last stage fifth shift register RS5, the M fifth shift registers RS5 are respectively the first to the Mth fifth shift registers RS5.
  • Each fifth shift register RS5 includes a fifth signal output terminal.
  • the enable signal terminal EM of the pixel circuit 20 in the Pth row is connected to the fourth signal output terminal of the Pth fifth shift register RS5 of the fourth gate driving circuit 134, P ⁇ M, and P is an integer.
  • the display panel 100 includes two fifth gate drive circuits 135, and the two fifth gate drive circuits 135 are respectively arranged in the first border area B1 (see FIG. 4 ) and the second border area B2 (see FIG. 4 ). That is, the second scan signal terminal GATE2 of the P-th row pixel circuit 20 is connected to the fifth signal output terminal of the P-th fifth shift register RS5 of the two fifth gate drive circuits 135 to form a double-sided drive, P ⁇ M, and P is an integer. In this way, the influence of the voltage drop on the second scan signal can be reduced, thereby improving the brightness uniformity of the display screen.
  • Some embodiments of the present disclosure further provide a driving method of a pixel circuit 20 , which is used to drive the pixel circuit 20 as in any of the above embodiments.
  • a display frame F includes a refresh frame F1 , and the refresh frame F1 includes a first reset phase P11 and a second reset phase P12 .
  • the reset subcircuit 23 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 in response to the working voltage of the reset signal of the reset signal terminal RESET, so as to reset the first node N1.
  • the storage subcircuit 24 stores the voltage of the second node N2 after the previous frame ends, so that the second node N2 can form a relatively stable potential (the voltage of the second voltage signal).
  • the fifth transistor T5 is turned on under the control of the reset signal received at the reset signal terminal RESET, and transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 .
  • the second storage capacitor C2 stores the voltage of the second node N2 after the previous frame ends.
  • a large bias voltage can be formed between the second node N2 and the first node N1, so that a stable and large bias voltage is generated between the source terminal and the control terminal of the eighth transistor T8, thereby improving the hysteresis characteristic of the eighth transistor T8, thereby improving the afterimage performance of the sub-pixel P, reducing the flicker value of the display panel 100, and improving the problem that the human eye can perceive flickering in the display screen.
  • the difference between the start time of the first reset stage P11 and the start time of a frame F in which the first reset stage P11 is located is greater than or equal to two row scanning periods H, so as to avoid the rising and falling edges of various signals of the first reset stage P11 being interlaced at the end of the previous frame F, thereby affecting the first reset stage P11.
  • the reset sub-circuit 23 transmits the first initialization signal received at the first initialization signal terminal VINIT1 to the first node N1 in response to the operating voltage of the reset signal at the reset signal terminal RESET.
  • the compensation sub-circuit 22 transmits the voltage of the first node N1 to the third node N3 in response to the operating voltage of the first scan signal received at the first scan signal terminal GATE1.
  • the driving sub-circuit 21 transmits the voltage of the third node N3 to the second node N2 under the control of the voltage of the first node N1, so as to reset the third node N3 and the second node N2 in sequence.
  • the first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the first scan signal received at the first scan signal terminal GATE1, and the voltage of the first node N1 is transmitted to the third node N3. Furthermore, the eighth transistor T8 is turned on under the control of the voltage of the first node N1, and the voltage of the third node N3 is transmitted to the second node N2.
  • the second node N2 and the third node N3 may be reset to reduce the influence of the residual voltage of the previous frame on the data writing of this frame, thereby improving the brightness uniformity of the display screen.
  • the refresh frame F1 further includes a first data writing phase P21 and a second data writing phase P22 .
  • the data writing sub-circuit 27 transmits the data signal received at the data signal terminal DATA to the second node N2 in response to the first operating voltage of the second scanning signal received at the second scanning signal terminal GATE2, and writes the data signal into the storage sub-circuit 24.
  • the driving sub-circuit 21 transmits the voltage of the second node N2 to the third node N3 under the control of the voltage of the first node N1.
  • the compensation sub-circuit 22 transmits the voltage of the third node N3 to the first node N1 in response to the operating voltage of the first scanning signal received at the first scanning signal terminal GATE1.
  • the seventh transistor T7 is turned on under the control of the first working voltage of the second scan signal received at the second scan signal terminal GATE2, and transmits the data signal received at the data signal terminal DATA to the second node N2.
  • the second storage capacitor C2 stores the voltage of the data signal written to the second node N2.
  • the eighth transistor T8 is turned on under the control of the voltage of the first node N1, and transmits the voltage of the third node N3 to the second node N2.
  • the first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the operating voltage of the first scan signal received at the first scan signal terminal GATE1, and transmit the voltage of the third node N3 to the first node N1.
  • the data signal may be written into the first node N1 and the second storage capacitor C2.
  • the storage sub-circuit 24 discharges and transmits the stored data signal to the second node N2.
  • the driving sub-circuit 21 transmits the voltage of the second node N2 to the third node N3 under the control of the voltage of the first node N1.
  • the compensation sub-circuit 22 transmits the voltage of the third node N3 to the first node N1 in response to the working voltage of the first scan signal received at the first scan signal terminal GATE1.
  • the second storage capacitor C2 is discharged, and the data signal written in the first data writing phase P21 is transmitted to the second node N2.
  • the eighth transistor T8 is turned on under the control of the voltage of the first node N1, and the voltage of the third node N3 is transmitted to the second node N2.
  • the first sub-transistor T1-1 and the second sub-transistor T1-2 are turned on under the control of the operating voltage of the first scan signal received at the first scan signal terminal GATE1, and the voltage of the third node N3 is transmitted to the first node N1.
  • the second storage capacitor C2 can be continuously discharged to continuously write the data signal to the first node N1, thereby increasing the data writing time, which is beneficial to improving the brightness uniformity of the display screen and enhancing the display effect.
  • the transistors included in the compensation sub-circuit 22 are P-type transistors.
  • the second reset phase P12 includes at least three row scanning periods H.
  • the voltage of the first row scanning period H after the first scanning signal is on is greater than the voltage of the second row scanning period H after the first scanning signal is on.
  • the stability of the scanning signal H is greater than the stability of H in the odd-numbered row scanning periods.
  • the first scanning signal of the first signal output terminal of the first shift register RS1 is output by the clock signal line, and in the first row scanning period H of the second reset phase P12, the first signal output terminal outputs a high level signal of the clock signal line. In the second row scanning period H of the second reset phase P12, the first signal output terminal outputs a low level signal of the clock signal line.
  • the first signal output terminal is in a floating state.
  • the first signal output terminal is a low-level signal of the output clock signal line. At this time, the stability of the first scanning signal output in the even-numbered row scanning period H is greater than the stability in the odd-numbered row scanning period H.
  • the first data writing phase P21 is located after the second resetting phase P12 and coincides with the 2Nth row scanning period H after the start time of the second resetting phase P12, N ⁇ 2, and N is an integer.
  • the first data writing phase P21 is performed in the even-numbered row scanning period H when the stability of the first scanning signal is relatively high, which can improve the accuracy of data signal writing, thereby improving the brightness uniformity of the display screen.
  • the display panel 100 includes the first gate driving circuit 131, the risk of the last few rows of sub-pixels P being illuminated compared to other sub-pixels P can be reduced, thereby improving the brightness uniformity of the display screen.
  • the second reset phase P12 includes three row scanning periods H.
  • the first data writing phase P21 coincides with the sixth row scanning period H after the start time of the second reset phase P12, that is, the sixth row scanning period H when the stability of the first scanning signal is relatively high is performed.
  • the falling edge of the second scanning signal and the rising edge of the reset signal can be staggered by two row scanning periods H, so as to avoid the influence of the second reset stage P12 on data writing, and the brightness uniformity of the display screen is higher.
  • the refresh frame F further includes a first light emitting phase P3 .
  • the light-emitting control subcircuit 26 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the operating voltage of the enable signal received at the enable signal terminal EM.
  • the driving subcircuit 21 generates a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.
  • the light emitting control subcircuit 26 transmits the driving current signal to the light emitting device 10 in response to the operating voltage of the enable signal received at the enable signal terminal EM.
  • the leakage prevention subcircuit 25 transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.
  • the third transistor T3 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2.
  • the eighth transistor T8 generates a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.
  • the third transistor T3 and the fourth transistor T4 are both turned on under the control of the enable signal received at the enable signal terminal EM, and transmit the drive current signal to the light emitting device 10 to drive the light emitting device 10 to emit light.
  • the second transistor T2 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the constant voltage received at the constant voltage terminal VC to the constant voltage terminal VC.
  • the signal is transmitted to the fourth node N4 to reduce the leakage current of the first node N1, thereby improving the brightness uniformity of the display picture.
  • the refresh frame F may further include a third reset phase P13 , and the third reset phase P13 is located between the second data writing phase P22 and the first light emitting phase P3 .
  • the data writing sub-circuit 27 transmits the data refresh signal received at the data signal terminal DATA to the second node N2 in response to the second operating voltage of the second scan signal received at the second scan signal terminal GATE2 .
  • the seventh transistor T7 is turned on under the control of the second scan signal received at the second scan signal terminal GATE2, and the data refresh signal received at the data signal terminal DATA is transmitted to the second node N2, so that the data signal received by the pixel circuit 20 of other rows can be reused, and the second node N2 and the fourth node N4 are reset again to improve the brightness uniformity of the display screen without changing the circuit structure, and the structure is simple.
  • the difference between the start time of the third reset phase P13 and the end time of the second data writing phase P22 is greater than or equal to one row scanning period H, so as to reduce the risk of the rising edge and the falling edge of each signal in the third reset phase P13 and the second data writing phase P22 being interlaced, thereby affecting data writing or resetting.
  • the difference between the start time of the third reset stage P13 and the end time of the second data writing stage P22 is 2 row scanning periods H, so as to avoid the rising edge and falling edge of each signal in the third reset stage P13 and the second data writing stage P22 from interlacing, which will affect data writing or resetting.
  • the difference between the end time of the third reset stage P13 and the start time of the first light-emitting stage P3 is greater than or equal to a row scanning period H, so as to avoid the rising edge and falling edge of each signal in the third reset stage P13 and the first light-emitting stage P3 from interlacing, thereby affecting data writing or light emission.
  • the difference between the start time of the third reset stage P13 and the end time of the second data writing stage P22 is 1 row scanning period H, so as to avoid the rising edge and falling edge of each signal in the third reset stage P13 and the second data writing stage P22 from interlacing, which will affect data writing or resetting.
  • the pixel circuit 20 has a first refresh frequency and a second refresh frequency, and the second refresh frequency is less than the first refresh frequency.
  • a display frame F includes a refresh frame F1.
  • a display frame F includes a refresh frame F1 and at least one hold frame F2.
  • the display panel 100 can display high and low frequency conversion at 30 Hz, 40 Hz, 60 Hz and 120 Hz, or high and low frequency conversion at 40 Hz, 55 Hz, 82 Hz and 165 Hz, for example, but the embodiments of the present disclosure are not limited thereto.
  • the holding frame F2 includes a black insertion phase P4 , a fourth resetting phase P5 , and a second light emitting phase P6 .
  • the light emitting control subcircuit 26 is configured to control the circuit transmitting the driving current signal to be cut off in response to the non-operating voltage of the enable signal received at the enable signal terminal EM.
  • the third transistor T3 and the fourth transistor T4 receive the enable signal terminal EM.
  • the circuit that transmits the driving current signal is cut off under the control of the enable signal.
  • a black screen can be inserted to provide a rest time for the light-emitting device 10, thereby avoiding abnormal light emission of the light-emitting device 10 caused by long-term bias, improving the image display effect and extending the service life of the light-emitting device 10.
  • the data writing sub-circuit 27 transmits the data holding signal received at the data signal terminal DATA to the second node N2 in response to the third operating voltage of the second scan signal received at the second scan signal terminal GATE2 .
  • the voltage range of the data hold signal is 0V ⁇ V GMP .
  • V GMP refers to the black state voltage of the sub-pixel P.
  • the black state voltage means that when the target grayscale of a sub-pixel P is 0, the black state voltage is directly used as the driving voltage corresponding to the sub-pixel P, so that the corresponding sub-pixel does not emit light.
  • the voltage range of the data hold signal is 0V ⁇ 7V, such as the voltage of the data hold signal is any one of 0V, 1V, 2V, 3V, 4V, 5V, 6V and 7V.
  • the voltage value of the data hold signal can be specifically based on experimental tests, and the voltage value with a lower flicker value can be used as the actual voltage value of the data hold signal, and the embodiments of the present disclosure are not specifically limited here.
  • the seventh transistor T7 is turned on under the control of the second scan signal received at the second scan signal terminal GATE2 , and transmits the data holding signal received at the data signal terminal DATA to the second node N2 to reset the second node N2 .
  • the light-emitting control subcircuit 26 transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2 in response to the operating voltage of the enable signal received at the enable signal terminal EM.
  • the driving subcircuit 21 generates a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.
  • the light emitting control subcircuit 26 transmits the driving current signal to the light emitting device 10 in response to the operating voltage of the enable signal received at the enable signal terminal EM.
  • the leakage prevention subcircuit 25 transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 in response to the operating voltage of the control signal received at the control signal terminal K.
  • the third transistor T3 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the first voltage signal received at the first voltage signal terminal VDD to the second node N2.
  • the eighth transistor T8 generates a driving current signal according to the voltage of the first node N1 and the voltage of the second node N2.
  • the third transistor T3 and the fourth transistor T4 are both turned on under the control of the enable signal received at the enable signal terminal EM, and transmit the driving current signal to the light emitting device 10 to drive the light emitting device 10 to emit light.
  • the second transistor T2 is turned on under the control of the enable signal received at the enable signal terminal EM, and transmits the constant voltage signal received at the constant voltage terminal VC to the fourth node N4 to reduce the leakage current of the first node N1, thereby improving the brightness uniformity of the display screen.
  • the difference between the end time of the fourth reset stage P5 and the start time of the second light-emitting stage P6 is greater than or equal to a row scanning period H, so as to avoid the rising edge and falling edge of each signal in the fourth reset stage P5 and the second light-emitting stage P6 from interlacing, thereby affecting the reset or light-emitting.
  • the end time of the fourth reset phase P5 and the start time of the second light-emitting phase P6 The difference is a row scanning period H, so as to avoid the rising edge and the falling edge of each signal in the fourth resetting stage P5 and the second light-emitting stage P6 from being staggered, thereby affecting the resetting or light-emitting.

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Abstract

一种像素电路，包括驱动子电路、补偿子电路、复位子电路和存储子电路。驱动子电路被配置为，在第一节点的电压的控制下，控制第二节点和第三节点之间的电路的导通和截止。补偿子电路被配置为，响应于第一扫描信号端处接收的第一扫描信号，控制第一节点和第三节点之间的电路的导通和截止。复位子电路被配置为，响应于复位信号端处接收的复位信号，将第一初始化信号端处接收的第一初始化信号传输至第一节点。存储子电路与第一电压信号端、第一节点和第二节点耦接。存储子电路被配置为，存储第一节点和第二节点的电压。

Description

像素电路及其驱动方法、显示面板、显示装置
本申请要求于2023年06月30日提交的、申请号为202310799140.9的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、显示面板、显示装置。
背景技术
随着显示技术的飞速发展，显示装置已经逐渐遍及在人们的生活中。其中，有机发光二极管(Organic Light Emitting Diode，简称OLED)由于具有自发光、低功耗、宽视角、响应速度快、高对比度以及柔性显示等优点，因而被广泛的应用于手机、电视、笔记本电脑等智能产品中。
发明内容
一方面，提供一种像素电路。所述像素电路包括驱动子电路、补偿子电路、复位子电路和存储子电路。
所述驱动子电路与第一节点、第二节点和第三节点耦接。所述驱动子电路被配置为，在所述第一节点的电压的控制下，控制所述第二节点和所述第三节点之间的电路的导通和截止。
所述补偿子电路与第一扫描信号端、所述第一节点和所述第三节点耦接。所述补偿子电路被配置为，响应于所述第一扫描信号端处接收的第一扫描信号，控制所述第一节点和所述第三节点之间的电路的导通和截止。
所述复位子电路与第一初始化信号端、复位信号端和所述第一节点耦接。所述复位子电路被配置为，响应于所述复位信号端处接收的复位信号的工作电压，将所述第一初始化信号端处接收的第一初始化信号传输至所述第一节点。
所述存储子电路与第一电压信号端、所述第一节点和所述第二节点耦接。所述存储子电路被配置为，存储所述第一节点和所述第二节点的电压。
在一些实施例中，所述存储子电路包括第一存储电容器和第二存储电容器，所述第一存储电容器的第一极板与所述第一电压信号端连接，所述第一存储电容器的第二极板与所述第一节点连接。所述第二存储电容器的第一极板与所述第一电压信号端连接，所述第二存储电容器的第二极板与所述第二节点连接。
在一些实施例中，所述补偿子电路包括串联的第一子晶体管和第二子晶体管，所述第一子晶体管的第一端与所述第一节点连接，所述第一子晶体管的第二端和/或所述第二子晶体管第一端连接第四节点，所述第二子晶体管的第二端与所述第三节点连接，且所述第一 子晶体管和所述第二子晶体管的控制极与所述第一扫描信号端连接。所述像素电路还包括防漏子电路，所述防漏子电路与控制信号端、恒定电压端和所述第四节点耦接。所述防漏子电路被配置为，响应于所述控制信号端处接收的控制信号的工作电压，将所述恒定电压端处接收的恒定电压信号传输至所述第四节点。
在一些实施例中，所述像素电路还包括发光控制子电路，所述发光控制子电路与第一电压信号端、使能信号端、所述第二节点、所述第三节点和第五节点耦接。所述第五节点与发光器件的阳极连接。所述发光控制子电路被配置为，响应于所述使能信号端处接收的使能信号，控制所述第一电压信号端和所述第二节点之间的电路导通与截止；以及，控制所述第三节点和所述第五节点之间的电路导通与截止；其中，所述使能信号端和所述控制信号端处接收的信号相同。
在一些实施例中，所述的像素电路还包括数据写入子电路，所述数据写入子电路与数据信号端、第二扫描信号端和所述第二节点耦接。所述数据写入子电路被配置为，响应于所述第二扫描信号端处接收的第二扫描信号的第一工作电压，将所述数据信号端处接收的数据信号传输至所述第二节点；以及，响应于所述第二扫描信号端处接收的第二扫描信号的第二工作电压，将所述数据信号端处接收的数据刷新信号传输至所述第二节点；所述数据刷新信号为其他行像素电路接收的数据信号。
在一些实施例中，所述第二扫描信号的第一工作电压的截止时间，位于所述第一扫描信号的工作电压的截止时间之前。且，所述第二扫描信号的第一工作电压的截止时间，与所述第一扫描信号的工作电压的截止时间的时间间隔大于或等于一个行扫描时段。所述行扫描时段为所述第二扫描信号的一个工作电压的持续时长。
在一些实施例中，所述第二扫描信号的第一工作电压的开始时间，位于所述复位信号的工作电压的截止时间之后。且，所述第二扫描信号的第一工作电压的开始时间，与所述复位信号的工作电压的截止时间的时间间隔大于或等于1个行扫描时段。所述行扫描时段为所述第二扫描信号的一个工作电压的持续时长。
在一些实施例中，所述补偿子电路包括晶体管为P型晶体管。所述第一扫描信号的工作电压的持续时长大于或等于4个行扫描时段。所述第一扫描信号工作后的第一个行扫描时段的电压，大于所述第一扫描信号工作后的第二个行扫描时段的电压。所述行扫描时段为所述第二扫描信号的一个工作电压的持续时长。所述第二扫描信号的第一工作电压的时间，与所述第一扫描信号的工作电压的第2N个行扫描时段重合，N≥2，且N为整数。
在一些实施例中，所述第二扫描信号的第二工作电压的起止时间，位于所述第一扫描信号的工作电压的截止时间和使能信号的工作电压的开始时间之间。且，所述第二扫描信号的第二工作电压的开始时间，与所述第一扫描信号的工作电压的截止时间的时间间隔大于或等于一个行扫描时段。所述第二扫描信号的第二工作电压的截止时间与所述使能信号 的工作电压的开始时间的时间间隔大于或等于一个所述行扫描时段。所述行扫描时段为所述第二扫描信号的一个工作电压的持续时长。
在一些实施例中，所述数据写入子电路还被配置为，响应于所述第二扫描信号端处接收的第二扫描信号的第三工作电压，将所述数据信号端处接收的数据保持信号传输至所述第二节点。
在一些实施例中，所述复位子电路还与第二初始化信号端、第三扫描信号端和第五节点耦接。所述复位子电路还被配置为，在所述第三扫描信号端处接收的第三扫描信号的工作电压的控制下，将所述第二初始化信号端处接收的第二初始化信号传输至所述第五节点。
在一些实施例中，所述复位信号的工作电压的开始时间，位于所述第一扫描信号的工作电压的开始时间之前。且，所述复位信号的工作电压的开始时间，与所述第一扫描信号的工作电压的开始时间的时间间隔大于或等于3个行扫描时段。和/或；所述复位信号的工作电压的截止时间，位于所述第一扫描信号的工作电压的开始时间之后；且，所述复位信号的工作电压的截止时间，与所述第一扫描信号的工作电压的开始时间的时间间隔大于或等于2个行扫描时段。
另一方面，提供一种像素电路的驱动方法。所述像素电路的驱动方法用于驱动如上述任一实施例所述的像素电路。一个显示帧包括一个刷新帧，所述刷新帧包括第一复位阶段和第二复位阶段。
在所述第一复位阶段，复位子电路响应于复位信号端的复位信号的工作电压，将第一初始化信号端处接收的第一初始化信号传输至第一节点。且，存储子电路存储第二节点在上一帧结束后的电压。在所述第二复位阶段，复位子电路响应于复位信号端的复位信号的工作电压，将第一初始化信号端处接收的第一初始化信号传输至第一节点。补偿子电路响应于第一扫描信号端处接收的第一扫描信号的工作电压，将所述第一节点的电压传输至所述第三节点。以及，驱动子电路在所述第一节点的电压的控制下，将所述第三节点的电压传输至所述第二节点。
在一些实施例中，所述像素电路还包括数据写入子电路，所述刷新帧还包括第一数据写入阶段和在第二数据写入阶段。
在所述第一数据写入阶段，所述数据写入子电路响应于第二扫描信号端处接收的第二扫描信号的第一工作电压，将数据信号端处接收的数据信号传输至所述第二节点，并写入所述存储子电路。所述驱动子电路在所述第一节点的电压的控制下，将所述第二节点的电压传输至所述第三节点。所述补偿子电路响应于第一扫描信号端处接收的第一扫描信号的工作电压，将所述第三节点的电压传输至所述第一节点。
在第二数据写入阶段，所述存储子电路放电，将存储的数据信号传输至所述第二节点。所述驱动子电路在所述第一节点的电压的控制下，将所述第二节点的电压传输至所述第三 节点。所述补偿子电路响应于第一扫描信号端处接收的第一扫描信号的工作电压，将所述第三节点的电压传输至所述第一节点。
在一些实施例中，所述补偿子电路包括晶体管为P型晶体管；所述第二复位阶段包括至少3个行扫描时段。在所述第二复位阶段，所述第一扫描信号工作后的第一个行扫描时段的电压，大于所述第一扫描信号工作后的第二个行扫描时段的电压。所述第一数据写入阶段位于所述第二复位阶段之后，且与所述第二复位阶段的开始时间后的第2N个行扫描时段重合，N≥2，且N为整数。
在一些实施例中，所述像素电路包括数据写入子电路，所述刷新帧还包括第三复位阶段和第一发光阶段，所述第三复位阶段位于所述第二数据写入阶段和所述第一发光阶段之间。在所述第三复位阶段，所述数据写入子电路响应于所述第二扫描信号端处接收的第二扫描信号的第二工作电压，将所述数据信号端处接收的数据刷新信号传输至所述第二节点。
在一些实施例中，所述第三复位阶段的开始时间，与所述第二数据写入阶段的截止时间的差值大于或等于一个行扫描时段。和/或，所述第三复位阶段的截止时间，与所述第一发光阶段的开始时间的差值大于或等于一个行扫描时段。
在一些实施例中，所述第一复位阶段的开始时间，与所述第一复位阶段所在的一帧的开始时间的差值大于或等于两个行扫描时段。
在一些实施例中，所述像素电路包括数据写入子电路、防漏子电路和发光控制子电路。所述像素电路具有第一刷新频率和第二刷新频率，所述第二刷新频率小于所述第一刷新频率。在所述第一刷新频率，一个显示帧包括一个刷新帧；在所述第二刷新频率，一个显示帧包括一个刷新帧和至少一个保持帧。所述保持帧包括插黑阶段、第四复位阶段和第二发光阶段。
在所述插黑阶段，所述发光控制子电路被配置为，响应于所述使能信号端处接收的使能信号的非工作电压，控制传输所述驱动电流信号的电路截止。
在所述第四复位阶段，所述数据写入子电路响应于所述第二扫描信号端处接收的第二扫描信号的第三工作电压，将所述数据信号端处接收的数据保持信号传输至所述第二节点。
在所述第二发光阶段，所述发光控制子电路响应于所述使能信号端处接收的使能信号的工作电压，将所述第一电压信号端处接收的第一电压信号，传输至所述第二节点；所述驱动子电路根据所述第一节点的电压和所述第二节点的电压，生成驱动电流信号；且，所述发光控制子电路响应于所述使能信号端处接收的使能信号的工作电压，将所述驱动电流信号传输至发光器件；所述防漏子电路响应于控制信号端处接收的控制信号的工作电压，将恒定电压端处接收的恒定电压信号传输至第四节点。
在一些实施例中，所述第四复位阶段的截止时间，与所述第二发光阶段的开始时间的差值大于或等于一个行扫描时段。
再一方面，提供一种显示面板。所述显示装置包括多个如上述任一实施例所述的像素电路。多个像素电路排列为M行N列，每行包括沿第一方向排列的N个像素电路，每列包括沿第二方向排列的M个像素电路，M＞1，N＞1，且M、N均为整数。
在一些实施例中，沿所述第二方向，从第一行像素电路到最后一行像素电路，M行像素电路分别为第1～第M行像素电路。
所述显示面板还包括第一栅极驱动电路，所述第一栅极驱动电路包括M+Q个级联的第一移位寄存器，从第一级第一移位寄存器到最后一级第一移位寄存器，M+Q个第一移位寄存器分别为第1～第M+Q个第一移位寄存器；每个所述第一移位寄存器包括第一信号输出端。其中，第P行像素电路的第一扫描信号端与第P+Q个第一移位寄存器的第一信号输出端连接；第P行像素电路的复位信号端与第P个第一移位寄存器的第一输出端连接；P≤M，Q＞0，且P、Q均为整数。
在一些实施例中，沿所述第二方向，从第一行像素电路到最后一行像素电路，M行像素电路分别为第1～第M行像素电路。
所述显示面板还包括第二栅极驱动电路和第三栅极驱动电路。所述第二栅极驱动电路包括M个级联的第二移位寄存器，从第一级第二移位寄存器到最后一级第二移位寄存器，M个第二移位寄存器分别为第1～第M个第二移位寄存器。每个所述第二移位寄存器包括第二信号输出端。其中，第P行像素电路的第一扫描信号端与第P个第二移位寄存器的第二信号输出端连接，P≤M，且P为整数；
所述第三栅极驱动电路包括M个级联的第三移位寄存器，从第一级第三移位寄存器到最后一级第三移位寄存器，M个第三移位寄存器分别为第1～第M个第三移位寄存器。每个所述第三移位寄存器包括第三信号输出端。其中，第P行像素电路的复位信号端与第P个第三移位寄存器的第三信号输出端连接，P≤M，且P为整数。
又一方面，提供一种显示装置。所述显示装置包括如上述任一实施例所述的显示面板。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的一种显示装置的结构图；
图2为根据一些实施例的另一种显示装置的结构图；
图3为图1中沿剖面线A-A＇处的一种剖视图；
图4为根据一些实施例的显示面板的结构图；
图5为图4中沿剖面线C-C＇处的一种剖视图；
图6为根据一些实施例的一种像素电路的结构框图；
图7为图6所示的像素电路的电路图；
图8A为根据一些实施例的另一种像素电路的结构框图；
图8B为根据一些实施例的又一种像素电路的结构框图；
图9A为图8A所示的像素电路的电路图；
图9B为图8B所示的像素电路的电路图；
图10为根据一些实施例的一种显示面板的栅极驱动电路的结构图；
图11为根据一些实施例的另一种显示面板的栅极驱动电路的结构图；
图12为根据一些实施例的又一种显示面板的栅极驱动电路的结构图；
图13为根据一些实施例的像素电路的一种时序图；
图14为根据一些实施例的像素电路的另一种时序图；
图15为根据一些实施例的像素电路的又一种时序图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。术语“耦接”例如表明两个或两个以上部件 有直接物理接触或电接触。术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
考虑到所讨论的测量和与特定数量的测量相关联的误差(即，测量系统的限制)，如本文中所使用的“约”、“近似”或“大致”包括所陈述的值并且意味着在如由本领域普通技术人员所确定的针对特定值的可接受偏差范围内。例如，“约”可意味着在一个或多个标准偏差内，或在所陈述的值的±30％、±20％、±10％、±5％内。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的 区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本说明书中，除非另有定义，否则这里使用的所有术语(包括技术术语和科学术语)具有与本发明所属领域的普通技术人员所通常理解的意思相同的意思。将进一步理解，除非这里明确定义，否则术语(例如在通用的字典中定义的术语)应该被解释为具有与它们在相关领域的背景中的意思一致的意思，并且不应解释为理想的或过于形式化的意思。
在本公开中，诸如“下”、“下方”、“上方”和“上”等类似词的术语用于解释附图中所示的部件的关系关联。术语可为相对概念并且基于附图中表示的方向来描述，也可以基于工艺步骤形成的先后顺序来描述，但是不限于此。
术语“相对”意味着第一元件可与第二元件直接或间接相对。在第三元件介于第一元件和第二元件之间的情况下，尽管仍然彼此相对，但是第一元件和第二元件可被理解为彼此间接相对。
在本公开的实施例中，所采用的晶体管可以为薄膜晶体管(Thin Film Transistor，简称TFT)、场效应晶体管(metal oxide semiconductor，简称MOS)或其他特性相同的开关器件，本公开的实施例中均以薄膜晶体管为例进行说明。
在本公开的实施例中，所采用的各薄膜晶体管的控制极为晶体管的栅极，第一极为薄膜晶体管的源极和漏极中一者，第二极为薄膜晶体管的源极和漏极中另一者。由于薄膜晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的薄膜晶体管的第一极和第二极在结构上可以是没有区别的。示例性地，在晶体管为P型晶体管的情况下，晶体管的第一极为源极，第二极为漏极；示例性地，在晶体管为N型晶体管的情况下，晶体管的第一极为漏极，第二极为源极。
在本公开的实施例中，电容器可以是通过工艺制程单独制作的电容器件，例如通过制作专门的电容电极来实现电容器件，该电容器的各个电容电极可以通过金属层、半导体层(例如掺杂多晶硅)等实现。电容器也可以是晶体管之间的寄生电容，或者通过晶体管本身与其他器件、线路来实现，又或者利用电路自身线路之间的寄生电容来实现。
本公开的实施例中，第一节点、第二节点、第一控制节点、第二控制节点等节点并非表示实际存在的部件，而是表示电路图中相关电连接的汇合点，也就是说，这些节点是由电路图中相关电连接的汇合点等效而成的节点。
本公开的实施例中，“工作电压”指的是能够使得其包括的被操作晶体管被导通的电压；相应地，“非工作电压”指的是不能使得其包括的被操作晶体管被导通的电压。
本公开的实施例中，“低电平”指的是能够使得其包括的被操作P型晶体管被导通的电压，并不能使得其包括的被操作N型晶体管被导通(即，该N型晶体管被截止)的电压； 相应地，“高电平”指的是能够使得其包括的被操作N型晶体管被导通的电压，并不能使得其包括的被操作P型晶体管被导通(即，该P型晶体管被截止)的电压。
如图1和图2所示，本公开的一些实施例提供了一种显示装置1000，显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的且不论文字还是的图像的任何装置。
示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、个人数字助理(Personal Digital Assistant，简称PDA)、导航仪、可穿戴设备、虚拟现实(Virtual Reality，简称VR)设备等任何具有显示功能的产品或者部件。
例如，如图1所示，该显示装置1000可以为便携式显示产品；如，该显示装置1000可以为图1所示的手机。又例如，参阅图2，该显示装置1000可以为可穿戴设备；如，该显示装置1000可以为图2中所示的手表。
下面以上述显示装置1000为图1所示的手机为例，对本公开的一些实施例进行示意性说明，但是本公开的实施方式不限于此。
在一些实施例中，参阅图3，显示装置1000包括显示面板100。
其中，显示面板100包括相对设置的出光侧和非出光侧。出光侧为显示面板100用于显示的一侧，即图3中的上侧。
示例性地，如图3所示，上述显示装置1000还可以包括壳体200、盖板300和电路板400以及其他电子配件。
参阅图3，盖板300可以为单层的玻璃盖板，也可以包括多层子盖板堆叠，本公开实施例在此不做具体限定。
如图3所示，壳体200的纵截面例如可以呈U型，显示面板100和电路板400设置于壳体200内，盖板300设置于壳体200的开口处。其中，电路板400设置于显示面板100远离盖板300的一侧，且电路板400与显示面板100连接，以向显示面板100提供所需的显示信号。
上述显示面板100的类型包括多种，可以根据实际需要选择设置。
示例性地，上述显示面板100可以为：有机发光二极管(Organic Light Emitting Diode，简称OLED)显示面板、量子点发光二极管(Quantum Dot Light Emitting Diode，简称QLED)显示面板等，本公开实施例在此不做具体限定。
下面以上述显示面板100为OLED显示面板为例，对本公开的一些实施例进行示意性的说明。
在一些实施例中，参阅图5，显示面板100包括显示基板110和用于封装显示基板110的封装层120。
其中，封装层120可以为封装薄膜，也可以为封装基板，本公开实施例在此不做具体 限定。
在一些实施例中，参阅图4，显示面板100具有显示区A，显示区A为显示图像的区域，被配置为设置多个子像素P。
示例性地，参阅图4，显示面板100包括衬底11和设置在衬底11的一侧，且位于显示区A的多个子像素P。
上述衬底11的类型包括多种，可以根据实际需要选择设置。
例如，衬底11可以为刚性衬底。例如，该刚性衬底可以为玻璃衬底或聚甲基丙烯酸甲酯(Polymethyl Methacrylate，简称PMMA)衬底等。
又例如，衬底11可以为柔性衬底。例如，该柔性衬底可以为聚对苯二甲酸乙二醇酯(Polyethylene Terephthalate，简称PET)衬底、聚萘二甲酸乙二醇酯(Polyethylene Naphthalate Two Formic Acid Glycol Ester，简称PEN)衬底或聚酰亚胺(Polyimide，简称PI)衬底等。
其中，参阅图4和图5，每个子像素P包括发光器件10和像素电路20。像素电路20包括多个薄膜晶体管30。
如图5所示，薄膜晶体管30包括半导体沟道31、源极32、漏极33和栅极34，源极32和漏极33均与半导体沟道31接触。
如图5所示，发光器件10包括第一电极11、发光功能层12以及第二电极13，第一电极11和一个薄膜晶体管30的源极32或漏极33电连接，图5中以第一电极11和薄膜晶体管30的漏极33电连接为例进行示意。
需要说明的是，上述发光功能层12可以仅包括发光层，也可以除包括发光层外，还包括电子传输层(Election Transporting Layer，简称ETL)、电子注入层(Election Injection Layer，简称EIL)、空穴传输层(Hole Transporting Layer，简称HTL)和空穴注入层(Hole Injection Layer，简称HIL)中的至少一者。
目前，显示装置采用可变刷新率的显示面板，以满足用户低功耗和高刷新率的需求。然而，在低频率显示时，显示面板的帧频降低，使得人眼对显示面板的闪烁的感知更加敏感，导致人眼能够感知到显示画面出现闪烁。
经研究发现，像素电路中的驱动晶体管的沟道本身因缺陷态多，而显现出明显的迟滞效应，导致上一时刻(前一个帧周期)的图像往往会保留在下一时刻的图像显示中，从而导致显示画面产生闪烁的显示问题。
需要说明的是，迟滞效应指的是在一定的偏压下，驱动晶体管的电特性所表现出来的一种不确定性，即驱动晶体管的电流的大小不仅与当前的偏压有关，还与前一时段的偏压状态相关。
基于此，参阅图6，本公开的一些实施例提供的像素电路20，包括驱动子电路21、补 偿子电路22、复位子电路23和存储子电路24。
在一些示例中，如图6所示，驱动子电路21与第一节点N1、第二节点N2和第三节点N3耦接。驱动子电路21被配置为，在第一节点N1的电压的控制下，控制第二节点N2和第三节点N3之间的电路的导通和截止；以及，根据第一节点N1的电压和第二节点N2的电压，生成驱动电流信号。
示例性地，如图7所示，驱动子电路21包括第八晶体管T8(即上面提到的驱动晶体管)，第八晶体管T8的第一极与第二节点N2连接，第八晶体管T8的第二极与第三节点N3连接，第八晶体管T8的控制极与第一节点N1连接。
在一些示例中，如图6所示，补偿子电路22与第一扫描信号端GATE1、第一节点N1和第三节点N3耦接。补偿子电路22被配置为，响应于第一扫描信号端GATE1处接收的第一扫描信号，控制第一节点N1和第三节点N3之间的电路的导通和截止。
示例性地，参阅图7，补偿子电路22包括串联的第一子晶体管T1-1和第二子晶体管T1-2，第一子晶体管T1-1的第一端与第一节点N1连接，第一子晶体管T1-1的第二端和/或第二子晶体管T1-2第一端连接第四节点N4，第二子晶体管的第二端与第三节点N3连接，且第一子晶体管T1-1和第二子晶体管T1-2的控制极与第一扫描信号端GATE1连接。
需要说明的是，第一子晶体管T1-1和第二子晶体管T1-2之间，还可以有其他串联的晶体管，即补偿子电路22还可以包括串联的三个、四个或更多个晶体管，本公开实施例在此不作具体限定。
下面以补偿子电路22包括串联的第一子晶体管T1-1和第二子晶体管T1-2为例，对本公开的一些实施例进行示意性说明，但是本公开的实施方式不限于此，并且也可以考虑补偿子电路22包括串联的三个、四个或更多个晶体管，只要应用相同的技术思想即可。
在一些示例中，如图6所示，复位子电路23与第一初始化信号端VINIT1、复位信号端RESET和第一节点N1耦接。复位子电路23被配置为，响应于复位信号端RESET处接收的复位信号的工作电压，将第一初始化信号端VINIT1处接收的第一初始化信号传输至第一节点N1，以对第一节点N1的电压进行复位。
示例性地，参阅图7，复位子电路23包括串联的多个第五晶体管T5，多个第五晶体管T5的一端与第一初始化信号端VINIT1连接，另一端与第一节点N1连接，且每个第五晶体管T5的控制极与复位信号端RESET连接。
例如，如图7所示，复位子电路23包括串联的两个第五晶体管T5，两个第五晶体管T5形成双栅晶体管，以减小漏电流。
其中，参阅图13、图14和图15，复位信号的工作电压的开始时间，位于第一扫描信号的工作电压的开始时间之前；且，复位信号的工作电压的开始时间，与第一扫描信号的工作电压的开始时间的时间间隔大于或等于3个行扫描时段。图13中以复位信号的工作 电压的开始时间，与第一扫描信号的工作电压的开始时间的时间间隔为8个行扫描时段为例进行示意。
此外，参阅图13、图14和图15，复位信号的工作电压的截止时间，位于第一扫描信号的工作电压的开始时间之后。且，复位信号的工作电压的截止时间，与第一扫描信号的工作电压的开始时间的时间间隔大于或等于2个行扫描时段。图13中以复位信号的工作电压的截止时间，与第一扫描信号的工作电压的开始时间的时间间隔为3个行扫描时段为例进行示意。
在一些示例中，如图6所示，存储子电路24与第一电压信号端VDD、第一节点N1和第二节点N2耦接。存储子电路24被配置为，存储第一节点N1和第二节点N2的电压。
示例性地，如图7所示，存储子电路24包括第一存储电容器C1和第二存储电容器C2，第一存储电容器C1的第一极板与第一电压信号端VDD连接，第一存储电容器C1的第二极板与第一节点N1连接。第二存储电容器C2的第一极板与第一电压信号端VDD连接，第二存储电容器C2的第二极板与第二节点N2连接。
在这种情况下，在一帧显示开始后，存储子电路24可以存储上一帧显示结束后在第二节点N2的电压，使得第二节点N2保持一个较为稳定的第一电压信号对应的电势，从而使得驱动子电路21的第一节点N1和第三节点N3产生稳定的较大的偏压，改善驱动子电路21的迟滞特性，从而改善子像素P的残像表现，降低显示面板100的闪烁值，改善人眼能够感知到显示画面出现闪烁的问题。
也就是说，在一帧显示开始后，第二存储电容器C2可以存储上一帧显示结束后在第二节点N2(即第八晶体管T8的第一极)的电压，使得第二节点N2保持一个较为稳定的第一电压信号对应的电势，从而使得第八晶体管T8的第一极(第二节点N2)和控制极(第三节点N3)产生稳定的较大的偏压，改善第八晶体管T8的迟滞特性，从而改善子像素P的残像表现，降低显示面板100的闪烁值，改善人眼能够感知到显示画面出现闪烁的问题。
在一些实施例中，如图8A所示，像素电路20还包括防漏子电路25。
在一些示例中，如图8A和图9B所示，防漏子电路25与控制信号端K、恒定电压端VC和第四节点N4耦接。防漏子电路25被配置为，响应于控制信号端K处接收的控制信号的工作电压，将恒定电压端VC处接收的恒定电压信号传输至第四节点N4。
其中，恒定电压信号的电压为-7V～7V。如，恒定电压信号的电压为-7V、-6V、-5V、-4V、-3V、-2V、-1V、0V、1V、2V、3V、4V、5V、6V和7V中的任一者，具体可以根据实验测试，获取防漏电效果较好的电压值作为恒定电压信号的实际电压值，本公开实施例在此不做具体限定。
示例性地，如图9B所示，防漏子电路25包括第二晶体管T2，第二晶体管T2的第一极与恒定电压端VC连接，第二晶体管T2的第二极与第四节点N4连接，第二晶体管T2 的控制极与控制信号端K连接。
在这种情况下，在发光阶段，防漏子电路25可以响应于控制信号端K处接收的控制信号的工作电压，将恒定电压端VC处接收的恒定电压信号传输至第四节点N4，以减小第四节点N4与第一节点N1之间的压差，降低第一节点N1漏电的风险，从而降低显示面板100的闪烁值，改善人眼能够感知到显示画面出现闪烁的问题。
在一些实施例中，如图8A所示，像素电路20还包括发光控制子电路26。
在一些示例中，如图8A所示，发光控制子电路26与第一电压信号端VDD、使能信号端EM、第二节点N2、第三节点N3和第五节点N5耦接。发光控制子电路26被配置为，响应于使能信号端EM处接收的使能信号，控制第一电压信号端VDD和第二节点N2之间的电路导通与截止；以及，控制第三节点N3和第五节点N5之间的电路导通与截止。
此处，第一电压信号可以为直流电源的正极的信号，例如，第一电压信号可以为5V。
需要说明的是，第五节点N5与发光器件10的阳极连接，以使得驱动电流信号可以传输至发光器件10。
示例性地，如图9B所示，发光控制子电路26包括第三晶体管T3和第四晶体管T4。第三晶体管T3的第一极与第一电压信号端VDD连接，第三晶体管T3的第二极与第二节点N2连接，第三晶体管T3的控制极与使能信号端EM连接。第四晶体管T4的第一极与第三节点N3连接，第四晶体管T4的第二极与第五节点N5连接，第四晶体管T4的控制极与使能信号端EM连接。
在此基础上，如图9B所示，使能信号端EM和控制信号端K处接收的信号相同。这样的话，使能信号端EM和控制信号端K可以连接同一条信号线，例如下面提到的一条栅线，以简化电路结构。即，在发光阶段，防漏子电路25响应于使能信号端EM处接收的控制信号的工作电压，将恒定电压端VC处接收的恒定电压信号传输至第四节点N4，以减小第四节点N4与第一节点N1之间的压差，降低第一节点N1漏电的风险，从而降低显示面板100的闪烁值，改善人眼能够感知到显示画面出现闪烁的问题。
在一些实施例中，如图8A所示，像素电路20还包括数据写入子电路27。
在一些示例中，如图8A所示，数据写入子电路27与数据信号端DATA、第二扫描信号端GATE2和第二节点N2耦接。数据写入子电路27被配置为，响应于第二扫描信号端GATE2处接收的第二扫描信号的第一工作电压，将数据信号端DATA处接收的数据信号传输至第二节点N2；以及，响应于第二扫描信号端GATE2处接收的第二扫描信号的第二工作电压，将数据信号端DATA处接收的数据刷新信号传输至第二节点N2。该数据刷新信号为其他行像素电路20接收的数据信号，例如相邻的下一行的像素电路20接收的数据信号。
需要说明的是，第二扫描信号的第一工作电压和第二工作电压的大小可以相同，但第 一工作电压和第二工作电压的时序并不相同。
示例性地，参阅图13、图14和图15，第二扫描信号的第一工作电压的截止时间，位于第一扫描信号的工作电压的截止时间之前。且，第二扫描信号的第一工作电压的截止时间，与第一扫描信号的工作电压的截止时间的时间间隔大于或等于一个行扫描时段H。
需要说明的是，行扫描时段H为第二扫描信号的一个工作电压的持续时长。
例如，如图13所示，第二扫描信号的第一工作电压的截止时间，与第一扫描信号的工作电压的截止时间的时间间隔为5个行扫描时段H。
示例性地，参阅图13、图14和图15，第二扫描信号的第一工作电压的开始时间，位于复位信号的工作电压的截止时间之后。且，第二扫描信号的第一工作电压的开始时间，与复位信号的工作电压的截止时间的时间间隔大于或等于1个行扫描时段H。
例如，如图13所示，第二扫描信号的第一工作电压的开始时间，与复位信号的工作电压的截止时间的时间间隔为2个行扫描时段H。
在一些实施例中，参阅图9B，上述补偿子电路22包括晶体管为P型晶体管。且，结合图13、图14和图15，第一扫描信号的工作电压的持续时长大于或等于4个行扫描时段H。第一扫描信号工作后的第一个行扫描时段H的电压，大于第一扫描信号工作后的第二个行扫描时段H的电压。该行扫描时段H为第二扫描信号的一个工作电压的持续时长。也就是说，第偶数个行扫描时段H输出的第一扫描信号的稳定性，大于第奇数个行扫描时段H的稳定性。
在本公开中，第一扫描信号工作后的第一个行扫描时段H的电压，可以理解为第一扫描信号的有效电平开始输入后的第一个时段，即图13中第一扫描信号端GATE1的第一下降沿后的第一个行扫描时段H，也即第二复位阶段P12的从左向右数的第一个行扫描时段H；或者，理解为用于将图9A中的第一子晶体管T1-1开启的电平输入后的第一个时段。
在本公开中，第一扫描信号工作后的第二个行扫描时段H的电压，可以理解为第一扫描信号的有效电平开始输入后的第二个时段，即图13中第一扫描信号端GATE1的第一下降沿后的第二个行扫描时段H，也即第二复位阶段P12的从左向右数的第二个行扫描时段H；或者，理解为用于将图9A中的第一子晶体管T1-1开启的电平输入后的第二个时段。
在此基础上，第二扫描信号的第一工作电压的时间，与第一扫描信号的工作电压的第2N个行扫描时段H重合，N≥2，且N为整数。
示例性地，如图13所示，第一扫描信号的工作电压的持续时长为11个行扫描时段H，第二扫描信号的第一工作电压的时间，与第一扫描信号的工作电压的第6个行扫描时段H重合，即N＝3。
此外，参阅图13、图14和图15，第二扫描信号的第二工作电压的起止时间，位于第一扫描信号的工作电压的截止时间和使能信号的工作电压的开始时间之间。
且，第二扫描信号的第二工作电压的开始时间，与第一扫描信号的工作电压的截止时间的时间间隔大于或等于一个行扫描时段H。第二扫描信号的第二工作电压的截止时间与使能信号的工作电压的开始时间的时间间隔大于或等于一个行扫描时段H。
示例性地，如图13所示，第二扫描信号的第二工作电压的开始时间，与第一扫描信号的工作电压的截止时间的时间间隔为2个行扫描时段H。第二扫描信号的第二工作电压的截止时间与使能信号的工作电压的开始时间的时间间隔为1个行扫描时段H。
在一些实施例中，如图所示，数据写入子电路27还被配置为，响应于第二扫描信号端GATE2处接收的第二扫描信号的第三工作电压，将数据信号端DATA处接收的数据保持信号传输至第二节点N2。
此处，数据保持信号的电压的范围为0V～VGMP。其中，VGMP指的是子像素P的黑态电压，黑态电压即当一个子像素P的目标灰阶为0时，直接将黑态电压作为该子像素P对应的驱动电压，使得对应的子像素不发光。
示例性地，数据保持信号的电压的范围为0V～7V，如，数据保持信号的电压为0V、1V、2V、3V、4V、5V、6V和7V中的任一者。这里，数据保持信号的电压值具体可以根据实验测试，将闪烁值较低的电压值作为数据保持信号的实际电压值，本公开实施例在此不做具体限定。
需要说明的是，第二扫描信号的第一工作电压、第二工作电压和第三工作电压的大小可以相同，但第一工作电压、第二工作电压和第三工作电压的时序并不相同。
在一些实施例中，如图9B所示，数据写入子电路27包括第七晶体管T7，第七晶体管T7的第一极与数据信号端DATA连接，第七晶体管T7的第二极与第二节点N2连接，第七晶体管T7的控制极与第二扫描信号端GATE2连接。
在一些实施例中，如图8A所示，复位子电路23还与第二初始化信号端VININT2、第三扫描信号端GATE3和第五节点N5耦接。复位子电路23还被配置为，在第三扫描信号端GATE3处接收的第三扫描信号的工作电压的控制下，将第二初始化信号端VINIT处接收的第二初始化信号传输至第五节点N5，以对发光器件10的阳极(第五节点N5)复位。
示例性地，如图9A所示，复位子电路23还包括第六晶体管T6，第六晶体管T6的第一极与第二初始化信号端VINIT2连接，第六晶体管VINIT2的第二极与第五节点N5连接，第六晶体管T6的控制极与第三扫描信号端GATE3连接。
在这种情况下，对发光器件10的阳极(第五节点N5)复位的第六晶体管T6的控制极，可以通过第三扫描信号端GATE3控制，可以对发光器件10的阳极(第五节点N5)复位，提升发光效率。
此外，上述第三扫描信号端GATE3可以与第二扫描信号端GATE2连接同一信号线，即第三扫描信号端GATE3和第二扫描信号端GATE2处接收的信号可以相同，第三扫描信 号端GATE3也可以称为第二扫描信号端GATE2。
此时，如图8B所示，复位子电路23与第二初始化信号端VININT2、第二扫描信号端GATE2和第五节点N5耦接。复位子电路23被配置为，在第二扫描信号端GATE2处接收的第三扫描信号的工作电压的控制下，将第二初始化信号端VINIT处接收的第二初始化信号传输至第五节点N5，以对发光器件10的阳极(第五节点N5)复位。
例如，如图9B所示，复位子电路23还包括第六晶体管T6，第六晶体管T6的第一极与第二初始化信号端VINIT2连接，第六晶体管VINIT2的第二极与第五节点N5连接，第六晶体管T6的控制极与第二扫描信号端GATE2连接。
在这种情况下，对发光器件10的阳极(第五节点N5)复位的第六晶体管T6的控制极，与第七晶体管T7的控制极，可以均通过第二扫描信号端GATE2控制，从而在数据写入的过程中，同时对发光器件10的阳极(第五节点N5)复位，简化电路结构。
下面以第三扫描信号端GATE3与第二扫描信号端GATE2连接同一信号线为例，对本公开的一些实施例进行示意性说明，但是本公开的实施方式不限于此。
在一些实施例中，如图4所示，所有的像素电路20排列为多行多列，每行包括沿第一方向X排列的多个像素电路20，每列包括沿第二方向Y排列的多个像素电路20。其中，第一方向X与第二方向Y大致垂直。
需要说明的是，第一方向X例如可以为多个像素电路20排列的行方向，第二方向Y例如可以为多个像素电路20排列的列方向。
下面以所有的像素电路20排列为多行多列为例，对本公开的一些实施例进行示例性的说明，但是本公开的实施方式不限于此。并且，将沿第一方向X排列的多个像素电路20称为一行像素电路20，沿第二方向Y排列的多个像素电路20称为一列像素电路20。
在此基础上，显示面板100还包括多条栅线GL、多条数据线DL、多条第一电源线VDL和多条第一初始化信号线VL1、多条第二初始化信号线VL2和多条恒定电压信号线VCL。
如图4所示，每条栅线GL大致沿第一方向X延伸，且被配置为传输第一扫描信号、第二扫描信号、复位信号和使能信号(控制信号)中的任一者。其中，一条栅线GL例如可以与一行像素电路20的第一扫描信号端GATE1、第二扫描信号端GATE2、复位信号端RESET和使能信号端EN(控制信号端K)中的任一者连接。
如图4所示，数据线DL大致沿第二方向Y延伸，且被配置为传输数据信号。一条数据线DL例如可以与一列像素电路20的数据信号端DATA连接。
如图4所示，第一电源线VDL大致沿第二方向Y延伸，且被配置为传输第一电源电压信号。一条第一电源线VDL例如可以与一列像素电路20的第一电压信号端VDD连接。
如图4所示，第一初始化信号线VL1大致沿第一方向X延伸，且被配置为传输第一 初始化信号。一条第一初始化信号线VL1例如可以与一行像素电路20的第一初始化信号端VINIT1连接。
如图4所示，第二初始化信号线VL2大致沿第一方向X延伸，且被配置为传输第二初始化信号。一条第二初始化信号线VL2例如可以与一行像素电路20的第二初始化信号端VINIT2连接。
如图4所示，恒定电压信号线VCL大致沿第二方向Y延伸，且被配置为传输恒定电压信号。一条恒定电压信号线VCL例如可以与一行像素电路20的恒定电压信号端VC连接。
如图5所示，沿垂直于衬底11，且远离衬底11的方向，显示面板100包括衬底11、半导体层ACT、第一栅绝缘层GI1、第一栅导电层GT1、第二栅绝缘层GI2、第二栅导电层GT2、层间绝缘层ILD、第一源漏导电层SD1、第一平坦层PLN1、第二源漏导电层SD2和第二平坦层PLN2。
在此基础上，参阅图4和图5，晶体管的半导体沟道31例如可以位于半导体层ACT，栅线GL、晶体管的栅极34和电容器(第一电容器C1和第二电容器C2)的第一极板例如可以位于第一栅导电层GT1。电容器(第一电容器C1和第二电容器C2)的第二极板、第一初始化信号线VL1和第二初始化信号线例如可以位于第二栅导电层GT2。晶体管的源极32、漏极33、第一电源线VDL和恒定电压信号线VCL例如可以位于第一源漏导电层SD1。数据线DL例如可以位于第二源漏导电层SD2。
在一些实施例中，如图5所示，显示面板100还包括像素界定层PDL，像素界定层PDL设有多个开口，一个发光器件10位于一个开口内。
在一些实施例中，如图5所示，显示面板100还包括隔垫物PS，隔垫物PS可以设置于像素界定层PDL和发光器件10的第一电极11之间，以支撑工艺过程中的掩膜版，使得掩膜版与像素界定层PDL之间的间隙均匀。
在一些实施例中，参阅图4，显示面板100还具有周边区B，周边区B设置在显示区A的至少一侧。图4中以周边区B围绕显示区A设置为例进行示意。
如图4所示，周边区B包括第一边框区B1、第二边框区B2、第三边框区B3和第四边框区B4，沿第一方向X，第一边框区B1和第二边框区B2位于显示区A的相对两侧，沿第二方向Y，第三边框区B3和第四边框区B4位于显示区A的另外相对两侧。
其中，周边区B为不显示图像的区域，被配置为设置栅极驱动电路130和源极驱动电路140等。
在一些实施例中，参阅图9B和图10，栅极驱动电路130包括第一栅极驱动电路131，第一栅极驱动电路131包括多个级联的第一移位寄存器RS1，每个第一移位寄存器RS1包括第一信号输出端，每个第一移位寄存器RS1的第一信号输出端与至少一行像素电路20 的第一扫描信号端GATE1和/或复位信号端RESET连接。
示例性地，如图9B和图10所示，多个像素电路20排列为M行N列，每行包括沿第一方向X排列的N个像素电路20，每列包括沿第二方向Y排列的M个像素电路20，M＞1，N＞1，且M、N均为整数。且，沿第二方向Y，从第一行像素电路20到最后一行像素电路20，M行像素电路20分别为第1～第M行像素电路20。图10中以2480行像素电路20为例进行示意。
其中，第一栅极驱动电路131包括M+Q个级联的第一移位寄存器RS1，从第一级第一移位寄存器RS1到最后一级第一移位寄存器RS1，M+Q个第一移位寄存器RS1分别为第1～第M+Q个第一移位寄存器RS1。图10中以Q等于8为例进行示意。
在此基础上，第P行像素电路20的第一扫描信号端GATE1与第P+Q个第一移位寄存器RS1的第一信号输出端连接。第P行像素电路20的复位信号端RESET与第P个第一移位寄存器RS1的第一信号输出端连接。且，P≤M，Q＞0，且P、Q均为整数。
在这种情况下，第一栅极驱动电路131可以向所有的像素电路20的第一扫描信号端GATE1和复位信号端RESET分别提供第一扫描信号和复位信号。也就是说，一个像素电路20的第一扫描信号端GATE1和复位信号端RESET可以共用一个栅极驱动电路130，有利于显示装置1000(参见图1)的窄边框设计。
在一些示例中，如图10所示，沿第一方向X，第一栅极驱动电路131设置于在显示区A(参见图4)的一侧，且从显示区A(参见图4)的单侧逐行依次驱动各行像素电路20，即单侧驱动。
在另一些示例中，如图11所示，沿第一方向X，两个第一栅极驱动电路131设置于显示区A(参见图4)的相对两侧，且通过两个第一栅极驱动电路131，同时从显示区A(参见图4)的相对两侧逐行依次驱动各行像素电路20，即双侧驱动。
在另一些实施例中，参阅图12，栅极驱动电路130包括第二栅极驱动电路132和第三栅极驱动电路133。
其中，如图9B和图12所示，第二栅极驱动电路132包括多个级联的第二移位寄存器RS2，每个第二移位寄存器RS2包括第二信号输出端，每个第二移位寄存器RS2的第二信号输出端与至少一行像素电路20的第一扫描信号端GATE1连接。
示例性地，如图12所示，多个像素电路20排列为M行N列，每行包括沿第一方向X排列的N个像素电路20，每列包括沿第二方向Y排列的M个像素电路20，M＞1，N＞1，且M、N均为整数。且，沿第二方向Y，从第一行像素电路20到最后一行像素电路20，M行像素电路20分别为第1～第M行像素电路20。图12中以2480行像素电路20为例进行示意。
其中，第二栅极驱动电路132包括M个级联的第二移位寄存器RS2，从第一级第二移 位寄存器RS2到最后一级第二移位寄存器RS2，M个第二移位寄存器RS2分别为第1～第M个第二移位寄存器RS2。每个第二移位寄存器RS2包括第二信号输出端。
在此基础上，第P行像素电路20的第一扫描信号端GATE1与第P个第二移位寄存器RS2的第二信号输出端连接，P≤M，且P为整数。
此外，如图9B和图12所示，第三栅极驱动电路133包括多个级联的第三移位寄存器RS3，每个第三移位寄存器RS3包括第三信号输出端，每个第三移位寄存器RS3的第三信号输出端与至少一行像素电路20的复位信号端RESET连接。
示例性地，如图12所示，多个像素电路20排列为M行N列，每行包括沿第一方向X排列的N个像素电路20，每列包括沿第二方向Y排列的M个像素电路20，M＞1，N＞1，且M、N均为整数。且，沿第二方向Y，从第一行像素电路20到最后一行像素电路20，M行像素电路20分别为第1～第M行像素电路20。图12中以2480行像素电路20为例进行示意。
其中，第三栅极驱动电路133包括M个级联的第三移位寄存器RS3，从第一级第三移位寄存器RS3到最后一级第三移位寄存器RS3，M个第三移位寄存器RS3分别为第1～第M个第三移位寄存器RS3。每个第三移位寄存器RS3包括第三信号输出端。
在此基础上，第P行像素电路的复位信号端RESET与第P个第三移位寄存器RS3的第三信号输出端连接，P≤M，且P为整数。
在这种情况下，第二栅极驱动电路132可以向所有的像素电路20的第一扫描信号端GATE1提供第一扫描信号，第三栅极驱动电路133可以向所有的像素电路20的复位信号端RESET提供复位信号。在这种情况下，像素电路20的第一扫描信号端GATE1接收的第一扫描信号的时长，和复位信号端RESET接收的复位信号的时长的比例，可以任意调节，有利于改善残像表现，降低闪烁，从而提高显示画质。
在一些示例中，如图12所示，沿第一方向X，第二栅极驱动电路132和第三栅极驱动电路133分别设置于显示区A(参见图4)的相对两侧，即，第二栅极驱动电路132和第三栅极驱动电路133分别设置于第一边框区B1(参见图4)和第二边框区B2(参见图4)，且从分别从显示区A(参见图4)的单侧逐行依次驱动各行像素电路20，有利于缩减显示装置1000(参见图1)的边框，提高屏占比。
在一些实施例中，参阅图10～图12，栅极驱动电路130还包括第四栅极驱动电路134。
其中，如图9B和图10所示，第四栅极驱动电路134包括多个级联的第四移位寄存器RS4，每个第四移位寄存器RS4包括第四信号输出端，每个第四移位寄存器RS4的第四信号输出端与至少一行像素电路20的使能信号端EM连接。
示例性地，如图10所示，多个像素电路20排列为M行N列，每行包括沿第一方向X排列的N个像素电路20，每列包括沿第二方向Y排列的M个像素电路20，M＞1，N＞1， 且M、N均为整数。且，沿第二方向Y，从第一行像素电路20到最后一行像素电路20，M行像素电路20分别为第1～第M行像素电路20。图10中以2480行像素电路20为例进行示意。
其中，第四栅极驱动电路134包括M个级联的第四移位寄存器RS4，从第一级第四移位寄存器RS4到最后一级第四移位寄存器RS4，M个第四移位寄存器RS4分别为第1～第M个第四移位寄存器RS4。每个所述第四移位寄存器RS4包括第四信号输出端。
在此基础上，第P行像素电路20的使能信号端EM，与第四栅极驱动电路134的第P个第四移位寄存器RS4的第四信号输出端连接，P≤M，且P为整数。
如图10所示，在显示面板100包括一个第一栅极驱动电路131的情况下，第一栅极驱动电路131和第四栅极驱动电路134分别设置于第一边框区B1(参见图4)和第二边框区B2(参见图4)，这样有利于显示装置1000(参见图1)的窄边框设计。
如图11所示，在显示面板100包括两个第一栅极驱动电路131，且两个第一栅极驱动电路131分别设置于第一边框区B1和第二边框区B2的情况下，第奇数个第四移位寄存器RS4和第偶数个第四移位寄存器RS4可以分别设置于第一边框区B1和第二边框区B2，形成交叉驱动，以充分利用第一边框区B1和第二边框区B2的区域，提高画面显示的均一性。
如图12所示，在显示面板100包括第二栅极驱动电路132和第三栅极驱动电路133的情况下，第奇数个第四移位寄存器RS4和第偶数个第四移位寄存器RS4分别设置于第一边框区B1和第二边框区B2，形成交叉驱动，以充分利用第一边框区B1和第二边框区B2的区域，提高画面显示的均一性。
在一些实施例中，参阅图10～图12，栅极驱动电路130还包括第五栅极驱动电路135。
其中，如图9B和图12所示，第五栅极驱动电路135包括多个级联的第五移位寄存器RS5，每个第五移位寄存器RS5包括第五信号输出端，每个第五移位寄存器RS5的第五信号输出端与至少一行像素电路20的第二扫描信号端GATE2连接。
示例性地，如图12所示，多个像素电路20排列为M行N列，每行包括沿第一方向X排列的N个像素电路20，每列包括沿第二方向Y排列的M个像素电路20，M＞1，N＞1，且M、N均为整数。且，沿第二方向Y，从第一行像素电路20到最后一行像素电路20，M行像素电路20分别为第1～第M行像素电路20。图12中以2480行像素电路20为例进行示意。
其中，第五栅极驱动电路135包括M个级联的第五移位寄存器RS5，从第一级第五移位寄存器RS5到最后一级第五移位寄存器RS5，M个第五移位寄存器RS5分别为第1～第M个第五移位寄存器RS5。每个第五移位寄存器RS5包括第五信号输出端。
在此基础上，第P行像素电路20的使能信号端EM，与第四栅极驱动电路134的第P个第五移位寄存器RS5的第四信号输出端连接，P≤M，且P为整数。
在一些示例中，如图10～图12所示，显示面板100包括两个第五栅极驱动电路135，两个第五栅极驱动电路135分别设置于第一边框区B1(参见图4)和第二边框区B2(参见图4)。即，第P行像素电路20的第二扫描信号端GATE2，与两个第五栅极驱动电路135的第P个第五移位寄存器RS5的第五信号输出端连接，形成双侧驱动，P≤M，且P为整数。以这种方式设置，可以减小压降对第二扫描信号的影响，从而提高显示画面的亮度均一性。
本公开的一些实施例还提供一种像素电路20的驱动方法，用于驱动如上述任一实施例的像素电路20。
其中，如图13所示，一个显示帧F包括一个刷新帧F1，刷新帧F1包括第一复位阶段P11和第二复位阶段P12。
在第一复位阶段P11，复位子电路23响应于复位信号端RESET的复位信号的工作电压，将第一初始化信号端VINIT1处接收的第一初始化信号传输至第一节点N1，以对第一节点N1进行复位。且，存储子电路24存储第二节点N2在上一帧结束后的电压，以使得第二节点N2可以形成较为稳定的电势(第二电压信号的电压)。
也就是说，如图9B所示，第五晶体管T5在复位信号端RESET处接收的复位信号的控制下导通，将第一初始化信号端VINIT1处接收的第一初始化信号传输至第一节点N1。且，第二存储电容器C2存储第二节点N2在上一帧结束后的电压。
此时，在第一复位阶段P11，第二节点N2和第一节点N1之间可以形成较大的偏压，即使得第八晶体管T8的源端和控制端之间，产生稳定的较大的偏压，改善第八晶体管T8的迟滞特性，从而改善子像素P的残像表现，降低显示面板100的闪烁值，改善人眼能够感知到显示画面出现闪烁的问题。
需要说明的是，第一复位阶段P11的开始时间，与第一复位阶段P11所在的一帧F的开始时间的差值大于或等于两个行扫描时段H，以避免上一帧F结束时与第一复位阶段P11的各个信号的上升沿与下降沿产生交错，对第一复位阶段P11造成影响。
在第二复位阶段P12，复位子电路23响应于复位信号端RESET的复位信号的工作电压，将第一初始化信号端VINIT1处接收的第一初始化信号传输至第一节点N1。补偿子电路22响应于第一扫描信号端GATE1处接收的第一扫描信号的工作电压，将第一节点N1的电压传输至第三节点N3。以及，驱动子电路21在第一节点N1的电压的控制下，将第三节点N3的电压传输至第二节点N2，以对第三节点N3和第二节点N2依次进行复位。
也就是说，如图9B所示，第一子晶体管T1-1和第二子晶体管T1-2在第一扫描信号端GATE1处接收的第一扫描信号的控制下导通，将第一节点N1的电压传输至第三节点N3。且，第八晶体管T8在第一节点N1的电压的控制下导通，将第三节点N3的电压传输至第二节点N2。
此时，在第二复位阶段P12，可以对第二节点N2和第三节点N3进行复位，以降低上一帧的残留电压对这一帧的数据写入造成影响，从而提高显示画面的亮度均一性。
在一些实施例中，如图13所示，刷新帧F1还包括第一数据写入阶段P21和在第二数据写入阶段P22。
在第一数据写入阶段P21，数据写入子电路27响应于第二扫描信号端GATE2处接收的第二扫描信号的第一工作电压，将在数据信号端DATA处接收的数据信号传输至第二节点N2，并写入存储子电路24。驱动子电路21在第一节点N1的电压的控制下，将第二节点N2的电压传输至第三节点N3。补偿子电路22响应于第一扫描信号端GATE1处接收的第一扫描信号的工作电压，将第三节点N3的电压传输至第一节点N1。
也就是说，如图9B所示，第七晶体管T7在第二扫描信号端GATE2处接收的第二扫描信号的第一工作电压的控制下导通，将在数据信号端DATA处接收的数据信号传输至第二节点N2。第二存储电容器C2存储第二节点N2写入的数据信号的电压。
且，第八晶体管T8在第一节点N1的电压的控制下导通，将第三节点N3的电压传输至第二节点N2。第一子晶体管T1-1和第二子晶体管T1-2在第一扫描信号端GATE1处接收的第一扫描信号的工作电压的控制下导通，将第三节点N3的电压传输至第一节点N1。
此时，在第一数据写入阶段P21，可以将数据信号写入第一节点N1以及第二存储电容器C2。
在第二数据写入阶段P22，存储子电路24放电将存储的数据信号传输至第二节点N2。驱动子电路21在第一节点N1的电压的控制下，将第二节点N2的电压传输至第三节点N3。补偿子电路22响应于第一扫描信号端GATE1处接收的第一扫描信号的工作电压，将第三节点N3的电压传输至第一节点N1。
也就是说，如图9B所示，第二存储电容器C2放电，将第一数据写入阶段P21写入的数据信号，传输至第二节点N2。第八晶体管T8在第一节点N1的电压的控制下导通，将第三节点N3的电压传输至第二节点N2。第一子晶体管T1-1和第二子晶体管T1-2在第一扫描信号端GATE1处接收的第一扫描信号的工作电压的控制下导通，将第三节点N3的电压传输至第一节点N1。
此时，在第二数据写入阶段P22，第二存储电容器C2可以持续放电，以将数据信号持续写入至第一节点N1，增加数据写入时间，有利于提高显示画面的亮度均一性，提升显示效果。
在一些实施例中，如图9B和图13所示，补偿子电路22包括晶体管为P型晶体管。且，第二复位阶段P12包括至少3个行扫描时段H。
在第二复位阶段P12，第一扫描信号工作后的第一个行扫描时段H的电压，大于第一扫描信号工作后的第二个行扫描时段H的电压。即，第偶数个行扫描时段H输出的第一扫 描信号H的稳定性，大于第奇数个行扫描时段H的稳定性。
示例性地，第一移位寄存器RS1的第一信号输出端的第一扫描信号由时钟信号线输出，在第二复位阶段P12的第一个行扫描时段H，第一信号输出端输出时钟信号线的高电平信号。在第二复位阶段P12的第二个行扫描时段H，第一信号输出端输出时钟信号线的低电平信号。
且，在第二复位阶段P12中的其他的第奇数个行扫描时段H，第一信号输出端为浮空状态。在第二复位阶段P12中的其他的第偶数个行扫描时段H，第一信号输出端为输出时钟信号线的低电平信号。此时，第偶数个行扫描时段H输出的第一扫描信号的稳定性，大于第奇数个行扫描时段H的稳定性。
在此基础上，第一数据写入阶段P21位于第二复位阶段P12之后，且与第二复位阶段P12的开始时间后的第2N个行扫描时段H重合，N≥2，且N为整数。
在这种情况下，在第一数据写入阶段P21在第一扫描信号的稳定性较高的第偶数个行扫描时段H进行，可以提高数据信号写入的准确度，从而提高显示画面的亮度均一性。尤其是，在显示面板100包括第一栅极驱动电路131的情况下，可以降低最后几行子像素P相较于其他子像素P发亮的风险，提高显示画面的亮度均一性。
例如，如图13所示，第二复位阶段P12包括3个行扫描时段H。此时，在第一数据写入阶段P21与第二复位阶段P12的开始时间后的第6个行扫描时段H重合，即在第一扫描信号的稳定性较高的第六数个行扫描时段H进行。
且，第二扫描信号的下降沿与复位信号的上升沿可以错开两个行扫描时段H，避免第二复位阶段P12对数据写入造成影响，且显示画面的亮度均一性较高。
在一些实施例中，如图13所示，刷新帧F还包括第一发光阶段P3。
在第一发光阶段P3，发光控制子电路26响应于使能信号端EM处接收的使能信号的工作电压，将第一电压信号端VDD处接收的第一电压信号，传输至第二节点N2。驱动子电路21根据第一节点N1的电压和第二节点N2的电压，生成驱动电流信号。
且，发光控制子电路26响应于使能信号端EM处接收的使能信号的工作电压，将驱动电流信号传输至发光器件10。防漏子电路25响应于控制信号端K处接收的控制信号的工作电压，将恒定电压端VC处接收的恒定电压信号传输至第四节点N4。
也就是说，如图9B所示，第三晶体管T3在使能信号端EM处接收的使能信号的控制下导通，将第一电压信号端VDD处接收的第一电压信号，传输至第二节点N2。第八晶体管T8根据第一节点N1的电压和第二节点N2的电压，生成驱动电流信号。
且，第三晶体管T3和第四晶体管T4，均在使能信号端EM处接收的使能信号的控制下导通，将驱动电流信号传输至发光器件10，以驱动发光器件10发光。第二晶体管T2在使能信号端EM处接收的使能信号的控制下导通，将恒定电压端VC处接收的恒定电压 信号传输至第四节点N4，以减小第一节点N1的漏电流，从而提高显示画面的亮度均一性。
在此基础上，如图13所示，刷新帧F还可以包括第三复位阶段P13，第三复位阶段P13位于第二数据写入阶段P22和第一发光阶段P3之间。
在第三复位阶段P13，数据写入子电路27响应于第二扫描信号端GATE2处接收的第二扫描信号的第二工作电压，将数据信号端DATA处接收的数据刷新信号传输至第二节点N2。
也就是说，如图9B所示，第七晶体管T7在第二扫描信号端GATE2处接收的第二扫描信号的控制下导通，将数据信号端DATA处接收的数据刷新信号传输至第二节点N2，这样可以复用其它行的像素电路20接收的数据信号，对第二节点N2和第四节点N4再次进行复位，以提高显示画面的亮度均一性，无需更改电路结构，结构简单。
在一些示例中，参阅图13、图14和图15，第三复位阶段P13的开始时间，与第二数据写入阶段P22的截止时间的差值大于或等于1个行扫描时段H，以降低第三复位阶段P13与第二数据写入阶段P22中各个信号的上升沿与下降沿产生交错的风险，从而对数据写入或复位造成影响。
例如，如图13所示，第三复位阶段P13的开始时间，与第二数据写入阶段P22的截止时间的差值为2个行扫描时段H，以避免第三复位阶段P13与第二数据写入阶段P22中各个信号的上升沿与下降沿产生交错，对数据写入或复位造成影响。
在一些示例中，参阅图13、图14和图15，第三复位阶段P13的截止时间，与第一发光阶段P3的开始时间的差值大于或等于一个行扫描时段H，以避免第三复位阶段P13与第一发光阶段P3中各个信号的上升沿与下降沿产生交错，对数据写入或发光造成影响。
例如，如图13所示，第三复位阶段P13的开始时间，与第二数据写入阶段P22的截止时间的差值为1个行扫描时段H，以避免第三复位阶段P13与第二数据写入阶段P22中各个信号的上升沿与下降沿产生交错，对数据写入或复位造成影响。
在一些实施例中，参阅图9B和图13，像素电路20具有第一刷新频率和第二刷新频率，第二刷新频率小于第一刷新频率。在第一刷新频率，一个显示帧F包括一个刷新帧F1。在第二刷新频率，一个显示帧F包括一个刷新帧F1和至少一个保持帧F2。
此时，该显示面板100例如可以30Hz、40Hz、60Hz和120Hz的高低变频显示，或，40Hz、55Hz、82Hz和165Hz的高低变频显示，本公开实施例不限于此。
其中，如图13所示，保持帧F2包括插黑阶段P4、第四复位阶段P5和第二发光阶段P6。
在插黑阶段P4，发光控制子电路26被配置为，响应于使能信号端EM处接收的使能信号的非工作电压，控制传输驱动电流信号的电路截止。
也就是说，如图9B所示，第三晶体管T3和第四晶体管T4在使能信号端EM处接收 的使能信号的控制下截止，从而控制传输驱动电流信号的电路截止。
此时，在刷新帧F1的第一发光阶段P3之后，可以插入黑画面，为发光器件10提供休息时间，避免长时间的偏压造成发光器件10发光异常，提高图像显示效果和延长发光器件10使用寿命。
在第四复位阶段P5，数据写入子电路27响应于第二扫描信号端GATE2处接收的第二扫描信号的第三工作电压，将数据信号端DATA处接收的数据保持信号传输至第二节点N2。
需要说明的是，数据保持信号的电压的范围为0V～VGMP。其中，VGMP指的是子像素P的黑态电压，黑态电压即当一个子像素P的目标灰阶为0时，直接将黑态电压作为该子像素P对应的驱动电压，使得对应的子像素不发光。示例性地，数据保持信号的电压的范围为0V～7V，如，数据保持信号的电压为0V、1V、2V、3V、4V、5V、6V和7V中的任一者。这里，数据保持信号的电压值具体可以根据实验测试，将闪烁值较低的电压值作为数据保持信号的实际电压值，本公开实施例在此不做具体限定。
也就是说，如图9B所示，第七晶体管T7在第二扫描信号端GATE2处接收的第二扫描信号的控制下导通，将数据信号端DATA处接收的数据保持信号传输至第二节点N2，以对第二节点N2进行复位。
在第二发光阶段P6，发光控制子电路26响应于使能信号端EM处接收的使能信号的工作电压，将第一电压信号端VDD处接收的第一电压信号，传输至第二节点N2。驱动子电路21根据第一节点N1的电压和第二节点N2的电压，生成驱动电流信号。
且，发光控制子电路26响应于使能信号端EM处接收的使能信号的工作电压，将驱动电流信号传输至发光器件10。防漏子电路25响应于控制信号端K处接收的控制信号的工作电压，将恒定电压端VC处接收的恒定电压信号传输至第四节点N4。
也就是说，如图9B所示，第三晶体管T3在使能信号端EM处接收的使能信号的控制下导通，将第一电压信号端VDD处接收的第一电压信号，传输至第二节点N2。第八晶体管T8根据第一节点N1的电压和第二节点N2的电压，生成驱动电流信号。
且，第三晶体管T3和第四晶体管T4，均在使能信号端EM处接收的使能信号的控制下导通，将驱动电流信号传输至发光器件10，以驱动发光器件10发光。第二晶体管T2在使能信号端EM处接收的使能信号的控制下导通，将恒定电压端VC处接收的恒定电压信号传输至第四节点N4，以减小第一节点N1的漏电流，从而提高显示画面的亮度均一性。
在一些示例中，参阅图13、图14和图15，第四复位阶段P5的截止时间，与第二发光阶段P6的开始时间的差值大于或等于一个行扫描时段H，以避免第四复位阶段P5与第二发光阶段P6中各个信号的上升沿与下降沿产生交错，对复位或发光造成影响。
例如，如图13所示，第四复位阶段P5的截止时间，与第二发光阶段P6的开始时间 的差值为一个行扫描时段H，以避免第四复位阶段P5与第二发光阶段P6中各个信号的上升沿与下降沿产生交错，对复位或发光造成影响。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种像素电路，包括：
    驱动子电路，与第一节点、第二节点和第三节点耦接；所述驱动子电路被配置为，在所述第一节点的电压的控制下，控制所述第二节点和所述第三节点之间的电路的导通和截止；
    补偿子电路，与第一扫描信号端、所述第一节点和所述第三节点耦接；所述补偿子电路被配置为，响应于所述第一扫描信号端处接收的第一扫描信号，控制所述第一节点和所述第三节点之间的电路的导通和截止；
    复位子电路，与第一初始化信号端、复位信号端和所述第一节点耦接；所述复位子电路被配置为，响应于所述复位信号端处接收的复位信号的工作电压，将所述第一初始化信号端处接收的第一初始化信号传输至所述第一节点；
    存储子电路，与第一电压信号端、所述第一节点和所述第二节点耦接；所述存储子电路被配置为，存储所述第一节点和所述第二节点的电压。
  2. 根据权利要求1所述的像素电路，其中，所述存储子电路包括：
    第一存储电容器，所述第一存储电容器的第一极板与所述第一电压信号端连接，所述第一存储电容器的第二极板与所述第一节点连接；
    第二存储电容器，所述第二存储电容器的第一极板与所述第一电压信号端连接，所述第二存储电容器的第二极板与所述第二节点连接。
  3. 根据权利要求1或2所述的像素电路，其中，所述补偿子电路包括：
    串联的第一子晶体管和第二子晶体管，所述第一子晶体管的第一端与所述第一节点连接，所述第一子晶体管的第二端和/或所述第二子晶体管第一端连接第四节点，所述第二子晶体管的第二端与所述第三节点连接，且所述第一子晶体管和所述第二子晶体管的控制极与所述第一扫描信号端连接；
    所述像素电路还包括：
    防漏子电路，与控制信号端、恒定电压端和所述第四节点耦接；所述防漏子电路被配置为，响应于所述控制信号端处接收的控制信号的工作电压，将所述恒定电压端处接收的恒定电压信号传输至所述第四节点。
  4. 根据权利要求3所述的像素电路，还包括：
    发光控制子电路，与第一电压信号端、使能信号端、所述第二节点、所述第三节点和第五节点耦接；所述第五节点与发光器件的阳极连接；所述发光控制子电路被配置为，响应于所述使能信号端处接收的使能信号，控制所述第一电压信号端和所述第二节点之间的电路导通与截止；以及，控制所述第三节点和所述第五节点之间的电路导通与截止；其中，所述使能信号端和所述控制信号端处接收的信号相同。
  5. 根据权利要求1～4中任一项所述的像素电路，还包括：
    数据写入子电路，与数据信号端、第二扫描信号端和所述第二节点耦接；所述数据写入子电路被配置为，响应于所述第二扫描信号端处接收的第二扫描信号的第一工作电压，将所述数据信号端处接收的数据信号传输至所述第二节点；以及，响应于所述第二扫描信号端处接收的第二扫描信号的第二工作电压，将所述数据信号端处接收的数据刷新信号传输至所述第二节点；所述数据刷新信号为其他行像素电路接收的数据信号。
  6. 根据权利要求5所述的像素电路，其中，所述第二扫描信号的第一工作电压的截止时间，位于所述第一扫描信号的工作电压的截止时间之前；
    且，所述第二扫描信号的第一工作电压的截止时间，与所述第一扫描信号的工作电压的截止时间的时间间隔大于或等于一个行扫描时段；所述行扫描时段为所述第二扫描信号的一个工作电压的持续时长。
  7. 根据权利要求5或6所述的像素电路，其中，所述第二扫描信号的第一工作电压的开始时间，位于所述复位信号的工作电压的截止时间之后；
    且，所述第二扫描信号的第一工作电压的开始时间，与所述复位信号的工作电压的截止时间的时间间隔大于或等于1个行扫描时段；所述行扫描时段为所述第二扫描信号的一个工作电压的持续时长。
  8. 根据权利要求5～7中任一项所述的像素电路，其中，所述补偿子电路包括晶体管为P型晶体管；
    所述第一扫描信号的工作电压的持续时长大于或等于4个行扫描时段；所述第一扫描信号工作后的第一个行扫描时段的电压，大于所述第一扫描信号工作后的第二个行扫描时段的电压；所述行扫描时段为所述第二扫描信号的一个工作电压的持续时长；
    所述第二扫描信号的第一工作电压的时间，与所述第一扫描信号的工作电压的第2N个行扫描时段重合，N≥2，且N为整数。
  9. 根据权利要求5～8中任一种所述的像素电路，其中，所述第二扫描信号的第二工作电压的起止时间，位于所述第一扫描信号的工作电压的截止时间和使能信号的工作电压的开始时间之间；
    且，所述第二扫描信号的第二工作电压的开始时间，与所述第一扫描信号的工作电压的截止时间的时间间隔大于或等于一个行扫描时段；所述第二扫描信号的第二工作电压的截止时间与所述使能信号的工作电压的开始时间的时间间隔大于或等于一个所述行扫描时段；所述行扫描时段为所述第二扫描信号的一个工作电压的持续时长。
  10. 根据权利要求5～7中任一项所述的像素电路，其中，所述数据写入子电路还被配置为，响应于所述第二扫描信号端处接收的第二扫描信号的第三工作电压，将所述数据信号端处接收的数据保持信号传输至所述第二节点。
  11. 根据权利要求5～8中任一项所述的像素电路，其中，所述复位子电路还与第二初 始化信号端、第三扫描信号端和第五节点耦接；所述复位子电路还被配置为，在所述第三扫描信号端处接收的第三扫描信号的工作电压的控制下，将所述第二初始化信号端处接收的第二初始化信号传输至所述第五节点。
  12. 根据权利要求1～11中任一项所述的像素电路，其中，所述复位信号的工作电压的开始时间，位于所述第一扫描信号的工作电压的开始时间之前；且，所述复位信号的工作电压的开始时间，与所述第一扫描信号的工作电压的开始时间的时间间隔大于或等于3个行扫描时段；
    和/或；
    所述复位信号的工作电压的截止时间，位于所述第一扫描信号的工作电压的开始时间之后；且，所述复位信号的工作电压的截止时间，与所述第一扫描信号的工作电压的开始时间的时间间隔大于或等于2个行扫描时段。
  13. 一种像素电路的驱动方法，用于驱动如权利要求1～12中任一项所述的像素电路，一个显示帧包括一个刷新帧，所述刷新帧包括第一复位阶段和第二复位阶段；
    在所述第一复位阶段，复位子电路响应于复位信号端的复位信号的工作电压，将第一初始化信号端处接收的第一初始化信号传输至第一节点；且，存储子电路存储第二节点在上一帧结束后的电压；
    在所述第二复位阶段，复位子电路响应于复位信号端的复位信号的工作电压，将第一初始化信号端处接收的第一初始化信号传输至第一节点；补偿子电路响应于第一扫描信号端处接收的第一扫描信号的工作电压，将所述第一节点的电压传输至所述第三节点；以及，驱动子电路在所述第一节点的电压的控制下，将所述第三节点的电压传输至所述第二节点。
  14. 根据权利要求13所述的驱动方法，其中，所述像素电路还包括数据写入子电路，所述刷新帧还包括第一数据写入阶段和在第二数据写入阶段；
    在所述第一数据写入阶段，所述数据写入子电路响应于第二扫描信号端处接收的第二扫描信号的第一工作电压，将数据信号端处接收的数据信号传输至所述第二节点，并写入所述存储子电路；所述驱动子电路在所述第一节点的电压的控制下，将所述第二节点的电压传输至所述第三节点；所述补偿子电路响应于第一扫描信号端处接收的第一扫描信号的工作电压，将所述第三节点的电压传输至所述第一节点；
    在第二数据写入阶段，所述存储子电路放电，将存储的数据信号传输至所述第二节点；所述驱动子电路在所述第一节点的电压的控制下，将所述第二节点的电压传输至所述第三节点；所述补偿子电路响应于第一扫描信号端处接收的第一扫描信号的工作电压，将所述第三节点的电压传输至所述第一节点。
  15. 根据权利要求14所述的驱动方法，其中，所述补偿子电路包括晶体管为P型晶体管；所述第二复位阶段包括至少3个行扫描时段；
    在所述第二复位阶段，所述第一扫描信号工作后的第一个行扫描时段的电压，大于所述第一扫描信号工作后的第二个行扫描时段的电压；
    所述第一数据写入阶段位于所述第二复位阶段之后，且与所述第二复位阶段的开始时间后的第2N个行扫描时段重合，N≥2，且N为整数。
  16. 根据权利要求13～15中任一项所述的驱动方法，其中，所述像素电路包括数据写入子电路，所述刷新帧还包括第三复位阶段和第一发光阶段，所述第三复位阶段位于所述第二数据写入阶段和所述第一发光阶段之间；
    在所述第三复位阶段，所述数据写入子电路响应于所述第二扫描信号端处接收的第二扫描信号的第二工作电压，将所述数据信号端处接收的数据刷新信号传输至所述第二节点。
  17. 根据权利要求16所述的驱动方法，其中，所述第三复位阶段的开始时间，与所述第二数据写入阶段的截止时间的差值大于或等于一个行扫描时段；和/或，所述第三复位阶段的截止时间，与所述第一发光阶段的开始时间的差值大于或等于一个行扫描时段。
  18. 根据权利要求13～17中任一项所述的驱动方法，其中，所述像素电路包括数据写入子电路、防漏子电路和发光控制子电路；所述像素电路具有第一刷新频率和第二刷新频率，所述第二刷新频率小于所述第一刷新频率；在所述第一刷新频率，一个显示帧包括一个刷新帧；在所述第二刷新频率，一个显示帧包括一个刷新帧和至少一个保持帧；所述保持帧包括插黑阶段、第四复位阶段和第二发光阶段；
    在所述插黑阶段，所述发光控制子电路被配置为，响应于所述使能信号端处接收的使能信号的非工作电压，控制传输驱动电流信号的电路截止；
    在所述第四复位阶段，所述数据写入子电路响应于所述第二扫描信号端处接收的第二扫描信号的第三工作电压，将所述数据信号端处接收的数据保持信号传输至所述第二节点；
    在所述第二发光阶段，所述发光控制子电路响应于所述使能信号端处接收的使能信号的工作电压，将所述第一电压信号端处接收的第一电压信号，传输至所述第二节点；所述驱动子电路根据所述第一节点的电压和所述第二节点的电压，生成所述驱动电流信号；且，所述发光控制子电路响应于所述使能信号端处接收的使能信号的工作电压，将所述驱动电流信号传输至发光器件；所述防漏子电路响应于控制信号端处接收的控制信号的工作电压，将恒定电压端处接收的恒定电压信号传输至第四节点。
  19. 根据权利要求18所述的驱动方法，其中，所述第四复位阶段的截止时间，与所述第二发光阶段的开始时间的差值大于或等于一个行扫描时段。
  20. 一种显示面板，包括：
    多个如权利要求1～12中任一项所述的像素电路，多个像素电路排列为M行N列，每行包括沿第一方向排列的N个像素电路，每列包括沿第二方向排列的M个像素电路，M＞1，N＞1，且M、N均为整数。
  21. 根据权利要求20所述的显示面板，其中，沿所述第二方向，从第一行像素电路到最后一行像素电路，M行像素电路分别为第1～第M行像素电路；
    所述显示面板还包括：
    第一栅极驱动电路，包括M+Q个级联的第一移位寄存器，从第一级第一移位寄存器到最后一级第一移位寄存器，M+Q个第一移位寄存器分别为第1～第M+Q个第一移位寄存器；每个所述第一移位寄存器包括第一信号输出端；
    其中，第P行像素电路的第一扫描信号端与第P+Q个第一移位寄存器的第一信号输出端连接；第P行像素电路的复位信号端与第P个第一移位寄存器的第一信号输出端连接；P≤M，Q＞0，且P、Q均为整数。
  22. 根据权利要求20所述的显示面板，其中，沿所述第二方向，从第一行像素电路到最后一行像素电路，M行像素电路分别为第1～第M行像素电路；
    所述显示面板还包括：
    第二栅极驱动电路，包括M个级联的第二移位寄存器，从第一级第二移位寄存器到最后一级第二移位寄存器，M个第二移位寄存器分别为第1～第M个第二移位寄存器；每个所述第二移位寄存器包括第二信号输出端；其中，第P行像素电路的第一扫描信号端与第P个第二移位寄存器的第二信号输出端连接，P≤M，且P为整数；
    第三栅极驱动电路，包括M个级联的第三移位寄存器，从第一级第三移位寄存器到最后一级第三移位寄存器，M个第三移位寄存器分别为第1～第M个第三移位寄存器；每个所述第三移位寄存器包括第三信号输出端；其中，第P行像素电路的复位信号端与第P个第三移位寄存器的第三信号输出端连接，P≤M，且P为整数。
  23. 一种显示装置，包括：
    如权利要求20～22中任一项所述的显示面板。
PCT/CN2024/093251 2023-06-30 2024-05-15 像素电路及其驱动方法、显示面板、显示装置 Ceased WO2025001587A1 (zh)

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