WO2025001586A1 - 显示基板及显示装置 - Google Patents

显示基板及显示装置 Download PDF

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Publication number
WO2025001586A1
WO2025001586A1 PCT/CN2024/093233 CN2024093233W WO2025001586A1 WO 2025001586 A1 WO2025001586 A1 WO 2025001586A1 CN 2024093233 W CN2024093233 W CN 2024093233W WO 2025001586 A1 WO2025001586 A1 WO 2025001586A1
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WO
WIPO (PCT)
Prior art keywords
fan
voltage signal
line
pixel
signal line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2024/093233
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English (en)
French (fr)
Other versions
WO2025001586A9 (zh
Inventor
张跳梅
吴建鹏
高文辉
刘烺
马鸿博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Publication of WO2025001586A1 publication Critical patent/WO2025001586A1/zh
Publication of WO2025001586A9 publication Critical patent/WO2025001586A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H10K59/1315—Interconnections, e.g. wiring lines or terminals comprising structures specially adapted for lowering the resistance
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate and a display device.
  • OLED display devices have gradually become one of the mainstream products in the display field due to their excellent performance such as self-luminescence, high contrast, wide viewing angle, fast response speed, application in flexible panels, wide operating temperature range, simple structure and process.
  • OLED display substrates can be widely used in terminal products such as smartphones, tablets, TVs and wearable devices (such as watches). Among them, high pixel density (Pixels Per Inch, PPI) and narrow frame are currently an important development direction of OLED display devices.
  • a display substrate has a display area and a binding area, and the binding area is located on one side of the display area along a second direction.
  • the display substrate includes: a plurality of pixel circuits, a plurality of data lines, and a first fan-out line and a second fan-out line arranged in the display area. At least one of the plurality of data lines is a set data line, and the second fan-out line is closer to the midline of the binding area along the second direction than the set data line.
  • a plurality of pixel circuits are arranged in a plurality of rows and columns, a row of pixel circuits is arranged along a first direction, a column of pixel circuits is arranged along a second direction, and the first direction and the second direction intersect.
  • a data line extends along the second direction, and a column of pixel circuits is electrically connected to a data line.
  • a first fan-out line extends along the first direction, and a second fan-out line extends along the second direction. One end of the first fan-out line is electrically connected to a set data line, and the other end is electrically connected to the second fan-out line.
  • the display substrate includes a plurality of pixels, each pixel includes at least three sub-pixels, and each sub-pixel includes a pixel circuit; at least one of the plurality of pixels is a setting pixel, and one setting pixel is correspondingly provided with at least one second fan-out line, and the second fan-out line passes between the pixel circuits of two adjacent sub-pixels in the corresponding setting pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding setting pixel, and extends to the binding area.
  • the display substrate further includes: a first voltage signal line extending along the second direction.
  • a set pixel is correspondingly provided with at least one first voltage signal line, and the first voltage signal line passes between pixel circuits of two adjacent sub-pixels in the corresponding set pixel, or passes from the outside of the pixel circuit located on the outside of the corresponding set pixel.
  • a second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels, and a first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels.
  • a pixel includes three sub-pixels.
  • a second fan-out line and a first voltage signal line are set corresponding to the pixel, and the second fan-out line passes between pixel circuits of a pair of adjacent sub-pixels in the three sub-pixels.
  • the first voltage signal line passes between pixel circuits of another pair of adjacent sub-pixels among the three sub-pixels.
  • one first voltage signal line and one second fan-out line pass between pixel circuits of the same pair of adjacent sub-pixels.
  • a pixel includes three sub-pixels.
  • a second fan-out line and a first voltage signal line are set corresponding to the pixel, and the second fan-out line and the first voltage signal line pass between pixel circuits of the same pair of adjacent sub-pixels in the three sub-pixels.
  • the second fan-out line is provided with a second break, and the second break divides the second fan-out line into an effective part and a redundant part.
  • One end of the effective part of the second fan-out line is electrically connected to the first fan-out line, and the other end extends to the binding area.
  • the display substrate also includes: a first connection portion, and the first voltage signal line and the redundant part of the second fan-out line are electrically connected through the first connection portion.
  • the first voltage signal line and the second fan-out line passing through the pixel circuits of the same pair of adjacent sub-pixels are arranged adjacent to each other, and the first voltage signal line, the second fan-out line and the first connecting portion are arranged in the same layer and are integrally formed.
  • the first fan-out line is provided with a first break, and the first break divides the first fan-out line into an effective part and a redundant part.
  • One end of the effective part of the first fan-out line is electrically connected to the set data line, and the other end is electrically connected to the effective part of the second fan-out line.
  • the display substrate also includes: a second connection part, one end of the second connection part is electrically connected to the redundant part of the first fan-out line; along the thickness direction of the display substrate, a via is provided between the second connection part and the redundant part of the second fan-out line, and the other end of the second connection part is electrically connected to the redundant part of the second fan-out line through the via.
  • the second connection portion and the redundant portion of the first fan-out line are disposed in the same layer and are integrally formed.
  • the display substrate further includes: a plurality of reference voltage signal lines extending along the second direction, and a column of pixel circuits is electrically connected to a reference voltage signal line.
  • a column of pixel circuits is electrically connected to a reference voltage signal line.
  • the reference voltage signal line connected to one column of pixel circuits and the data line connected to the other column of pixel circuits are arranged close to each other.
  • the second fan-out line is arranged between the reference voltage signal line and the data line that are arranged close to each other.
  • the first voltage signal line of the display substrate is disposed between the reference voltage signal line and the data line which are disposed close to each other.
  • the display substrate further comprises: a substrate, a semiconductor layer disposed on the substrate, and a plurality of auxiliary reference voltage signal lines disposed on a side of the semiconductor layer away from the substrate.
  • the auxiliary reference voltage signal lines extend along a first direction and are electrically connected to the reference voltage signal lines.
  • the first fan-out line is disposed on a side of the auxiliary reference voltage signal line away from the substrate; in an orthographic projection onto the substrate, the first fan-out line overlaps with the auxiliary reference voltage signal line and partially overlaps with the semiconductor layer.
  • the display substrate further includes: a plurality of second voltage signal lines extending along the second direction, and a column of pixel circuits is electrically connected to a second voltage signal line.
  • the film layer where the plurality of second voltage signal lines are located is located on a side of the film layer where the first fan-out line is located away from the substrate, and in an orthographic projection onto the substrate, the second voltage signal line covers the first break of the first fan-out line.
  • the display substrate further comprises: a plurality of source-drain conductive layers.
  • a pair of adjacent source-drain conductive layers in the plurality of source-drain conductive layers are respectively a first set source-drain conductive layer and a second set source-drain conductive layer, wherein the first set source-drain conductive layer is The source-drain conductive layer is set close to the substrate, wherein the first fan-out line is set in the first set source-drain conductive layer, and the data line and the second fan-out line are set in the second set source-drain conductive layer.
  • the display substrate further includes: a gate signal line, an enable signal line, an auxiliary first voltage signal line, and an auxiliary second voltage signal line, all extending along the first direction.
  • the pixel circuit is electrically connected to the gate signal line and the enable signal line; the auxiliary first voltage signal line is electrically connected to the first voltage signal line, and the auxiliary second voltage signal line is electrically connected to the second voltage signal line.
  • the first set source-drain conductive layer is provided with at least one of a gate signal line, an enable signal line, an auxiliary first voltage signal line, and an auxiliary second voltage signal line.
  • at least one of the gate signal line, the enable signal line, the auxiliary first voltage signal line, and the auxiliary second voltage signal line covers the second break of the second fan-out line.
  • the first voltage signal line, the second voltage signal line and the reference voltage signal line of the display substrate are all disposed in the second set source-drain conductive layer.
  • the display substrate further includes: a first gate layer and a second gate layer.
  • the semiconductor layer, the first gate layer and the second gate layer of the display substrate are sequentially arranged in a direction away from the substrate and are located between the substrate and the multi-layer source and drain conductive layer.
  • the auxiliary reference voltage signal line of the display substrate is arranged on the second gate layer.
  • the multi-layer source-drain conductive layer includes a first source-drain conductive layer and a second source-drain conductive layer, the first source-drain conductive layer is a first set source-drain conductive layer, and the second source-drain conductive layer is a second set source-drain conductive layer.
  • the multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the first source-drain conductive layer is a first set source-drain conductive layer, and the second source-drain conductive layer is a second set source-drain conductive layer.
  • the multi-layer source-drain conductive layer includes a first source-drain conductive layer, a second source-drain conductive layer and a third source-drain conductive layer, the second source-drain conductive layer is a first set source-drain conductive layer, and the third source-drain conductive layer is a second set source-drain conductive layer.
  • the set data line is further away from the center line of the binding area along the second direction than other data lines in the plurality of data lines.
  • the set data line is entirely located in the display area, and ends of other data lines extend to the binding area.
  • a display device comprising: a display substrate as described in any of the above embodiments, and a circuit board, the circuit board being electrically connected to the display substrate.
  • FIG1 is a structural diagram of a display device according to some embodiments.
  • FIG2 is another structural diagram of a display device according to some embodiments.
  • FIG3 is a structural diagram of a pixel circuit according to some embodiments.
  • FIG4 is a structural diagram of a pixel circuit according to some other embodiments.
  • FIG5 is a partial enlarged structural diagram of a display area AA of a display substrate according to some embodiments.
  • FIG6 is an enlarged structural diagram of area D in FIG5 ;
  • FIG7 is an enlarged structural diagram of area F in FIG5 ;
  • FIG. 8 is a structural diagram of a first source-drain conductive layer to a second source-drain conductive layer of a display substrate according to some embodiments;
  • FIG. 9 is an enlarged structural diagram of a first source-drain conductive layer of a display substrate according to some embodiments according to region E in FIG. 8 ;
  • FIG. 10 is an enlarged structural diagram of a second source-drain conductive layer of a display substrate according to some embodiments according to region E in FIG. 8 ;
  • FIG11 is an equivalent circuit diagram of a pixel circuit according to some embodiments.
  • FIG12 is a cross-sectional structural diagram of a display substrate according to some embodiments.
  • FIG13 is a structural diagram of a semiconductor layer of a display substrate according to some embodiments.
  • FIG14 is a structural diagram of a display substrate from a semiconductor layer to a second gate layer according to some embodiments.
  • FIG. 15 is a structural diagram of a display substrate from a semiconductor layer to a first source-drain conductive layer according to some embodiments.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • Coupled When describing some embodiments, the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” should be understood in a broad sense. For example, “connected” can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium.
  • the term “coupled” indicates, for example, that two or more components are in direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also refer to two or more components being in direct physical or electrical contact with each other. There is no direct contact between them, but they still cooperate or interact with each other.
  • the embodiments disclosed here are not necessarily limited to the contents of this article.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • the term “if” is optionally interpreted to mean “when” or “upon” or “in response to determining” or “in response to detecting,” depending on the context.
  • the phrases “if it is determined that” or “if [a stated condition or event] is detected” are optionally interpreted to mean “upon determining that” or “in response to determining that” or “upon detecting [a stated condition or event]” or “in response to detecting [a stated condition or event],” depending on the context.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism may be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity may also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality may be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of the layers and the area of the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing.
  • an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • FIG. 1 and FIG. 2 are planar structural diagrams of a display device 1000.
  • FIG. 2 shows the circuit board 200 in the display area of the display substrate 100.
  • the circuit board 200 is bent to the other side.
  • FIG3 and FIG4 only show the structural diagram of a part of the pixel circuit 10 of the display substrate 100.
  • the number of pixel circuits 10 included in the actual display substrate 100 is not limited to that shown in the figure, and the film layer structure included in the display substrate 100 includes but is not limited to the film layer structure shown in the figure.
  • FIG5 shows a partial enlarged view in the display area AA.
  • the direction indicated by the vertical arrow in FIG5 is the transmission path of the data signal transmitted through the second fan-out line FIP2 in the binding area BB.
  • the direction indicated by the horizontal arrow in FIG5 is the transmission path of the data signal transmitted from the second fan-out line FIP2 to the first fan-out line FIP1.
  • FIG5 identifies the transmission paths of the data signals of the three setting data lines DL1.
  • FIG6 is an enlarged structural diagram of area D in FIG5, and
  • FIG7 is an enlarged structural diagram of area F in FIG5.
  • Figure 9 is an enlarged structural diagram of the first source-drain conductive layer according to the area E in Figure 8
  • Figure 10 is an enlarged structural diagram of the second source-drain conductive layer according to the area E in Figure 8.
  • Fig. 11 is an equivalent circuit diagram of a pixel circuit according to some embodiments.
  • Fig. 12 is a cross-sectional structural diagram of a display substrate according to some embodiments.
  • Figure 13 is a planar structural diagram of a semiconductor layer of a display substrate according to some embodiments.
  • Figure 14 is a structural diagram of a display substrate from a semiconductor layer to a second gate layer according to some embodiments.
  • Figure 15 is a structural diagram of a display substrate from a semiconductor layer to a first source-drain conductive layer according to some embodiments.
  • Figures 3 to 10 and Figures 13 to 15 only show enlarged structural schematic diagrams of partial areas corresponding to some sub-pixels in each film layer structure of the display substrate.
  • the actual film layer structure of the display substrate 100 may also include other film layer structures, and the patterned design of each film layer structure includes but is not limited to that shown in the figure, and may also include other designs.
  • the insulating dielectric layer ILD and the first planarization layer 61 shown in Figures 3, 4, 6 to 8, 14 and 15 are vias on the insulating dielectric layer ILD and the first planarization layer 61.
  • the insulating dielectric layer ILD and the first planarization layer 61 are the film layers that entirely cover the display substrate 100, and vias are set on the insulating dielectric layer ILD and the first planarization layer 61 at the positions shown in the figures, so that the parts that need to be electrically connected between the second gate layer 32 and the first source-drain conductive layer 41, and between the first source-drain conductive layer 41 and the second source-drain conductive layer 42 can be connected correspondingly through the vias.
  • the display device 1000 may be any device that displays a moving (e.g., video) or fixed (e.g., still image), and a text or image. More specifically, it is expected that the embodiments may be implemented in or associated with a variety of electronic devices, the multiple electronic devices
  • the electronic devices include, but are not limited to, televisions, mobile phones, wearable devices, PDAs (Personal Digital Assistants), AR (Augmented Reality) devices, VR (Virtual Reality) devices, handheld or portable computers, GPS receivers/navigators, cameras, MP4 video players, video cameras, game consoles, clocks, calculators, television monitors, flat panel displays, computer monitors, vehicle displays (e.g., odometer displays, etc.), navigators, cockpit controllers and/or displays, displays of camera views (e.g., displays of rear-view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures
  • the display device 1000 may be an OLED (Organic Light-Emitting Diode, or Organic Electroluminescence Display, organic light-emitting semiconductor) display device, a QLED (Quantum Dot Light Emitting Diodes, quantum dot electroluminescent diode) display device, an MLED (Mini Light Emitting Diodes, or Micro Light Emitting Diodes, micro light-emitting diode) display device, etc.
  • the display device 1000 may be a flat display device, a curved display device, or a foldable display device, etc.
  • the display device 1000 may be a rectangular or circular display, etc. There is no limitation on this, and an adaptive design can be performed according to actual needs.
  • Some embodiments of the present disclosure are schematically described below using a rectangular and planar organic light emitting diode display device as an example, but the implementation methods of the present disclosure include but are not limited to this, and any other display device may also be considered as long as the same technical concept is applied.
  • the display device 1000 includes a display substrate 100 and a circuit board 200.
  • the circuit board 200 is electrically connected to the display substrate 100.
  • the circuit board 200 is configured to transmit a driving signal to the display substrate 100 to drive the display substrate 100 to realize image display.
  • the circuit board 200 may include a TCON (Timing Controller), a power management chip DC/DC, and an adjustable resistor divider circuit (generating Vcom) and other driving circuits.
  • the circuit board 200 may also include other circuit structures, which are not listed here one by one.
  • the display device 1000 may further include an under-screen camera and an under-screen fingerprint sensor, so that the display device 1000 can realize various functions such as taking photos, recording videos, fingerprint recognition or face recognition, etc. There is no limitation to this, and an adaptive design can be performed according to actual needs.
  • the display substrate 100 has a display area AA and a peripheral area AN at least located on one side of the display area AA along the second direction Y.
  • the display substrate 100 includes a plurality of pixels P disposed in the display area AA, each pixel P including at least three sub-pixels P(x).
  • the plurality of pixels P are arranged in a plurality of rows and columns.
  • the display area AA is an area on the display substrate 100 for displaying images
  • the sub-pixel P(x) is a minimum light-emitting unit on the display substrate 100
  • the sub-pixel P(x) is used to display images.
  • the display substrate 100 may further include a color filter layer disposed on the light-emitting side of the multiple sub-pixels P(x), that is, the display substrate 100 adopts a COE (CF On Encapsulation) structure.
  • COE CF On Encapsulation
  • multiple sub-pixels P(x) all emit light of colors such as white light, red light, green light or blue light.
  • the colored light emitted by the sub-pixel P(x) remains the same color light after passing through the color filter layer, or is converted into other color light for emission. Therefore, when multiple sub-pixels P(x) emit the same color light, the display substrate 100 can achieve multi-color light output.
  • multiple sub-pixels P(x) emit light of different colors.
  • multiple sub-pixels P(x) include red sub-pixels that emit red light, green sub-pixels that emit green light, and blue sub-pixels that emit blue light, thereby realizing multi-color light output of the display substrate 100.
  • each pixel P includes at least three sub-pixels P(x), that is, each pixel P may include three, four or more sub-pixels P(x), and the multiple sub-pixels P(x) included in each pixel P may be a row, a column or a group of sub-pixels P(x), and a group of sub-pixels P(x) may be a plurality of sub-pixels P(x) adjacent to each other, and the adjacent plurality of sub-pixels P(x) are arranged in a row, a column, an L-shape, a rectangle or a diamond, etc.
  • the light emitting areas of the multiple sub-pixels P(x) included in each pixel P may be the same or different.
  • the above is only an exemplary description and is not intended to limit the present disclosure.
  • the specific adaptive design can be carried out according to actual needs.
  • the peripheral area AN is disposed around the display area AA, and a gate driving circuit (e.g., Gate on Array, GOA for short), control signal lines (e.g., clock signal lines, power supply voltage signal lines, etc.) and a binding driver chip (e.g., Source Driver IC, source driver chip) may be disposed in the peripheral area AN.
  • a gate driving circuit e.g., Gate on Array, GOA for short
  • control signal lines e.g., clock signal lines, power supply voltage signal lines, etc.
  • a binding driver chip e.g., Source Driver IC, source driver chip
  • the peripheral area AN includes a binding area BB, and the binding area BB is located on one side of the display area AA along the second direction Y.
  • the binding area BB is adjacent to one side edge of the display area AA, and the binding area BB is adjacent to the lower side edge of the display area AA, for example.
  • the display substrate 100 is connected to an external driver in the binding area BB.
  • the binding area BB is configured to lead out the signal lines (such as the data line DL, the first voltage signal line VSS and the reference voltage signal line VRef1, etc.) and bind them to the driving circuit board (such as the circuit board 200) or the driving chip. That is, the binding area BB is located on the side of the display substrate 100 for binding the driving circuit board or the driving chip.
  • the signal lines such as the data line DL, the first voltage signal line VSS and the reference voltage signal line VRef1, etc.
  • the display substrate 100 includes: a plurality of pixel circuits 10 and a plurality of light-emitting devices 20.
  • the plurality of pixel circuits 10 are arranged in a plurality of rows and columns, a row of pixel circuits 10 is arranged along a first direction X, and each row of pixel circuits 10 includes a plurality of pixel circuits 10 arranged at intervals along the first direction X; a column of pixel circuits 10 is arranged along a second direction Y, and each column of pixel circuits 10 includes a plurality of pixel circuits 10 arranged at intervals along the second direction Y.
  • the first direction X is the row direction in which the plurality of pixel circuits 10 are arranged
  • the second direction Y is the column direction in which the plurality of pixel circuits 10 are arranged.
  • the first direction X and the second direction Y intersect.
  • the first direction X is perpendicular to the second direction Y.
  • each pixel circuit 10 is connected to a light emitting device 20 , and the pixel circuit 10 is configured to drive the light emitting device 20 connected thereto to emit light.
  • the light-emitting device 20 includes but is not limited to OLED (Organic Light-Emitting Diode), Mini LED (Mini Light-Emitting Diode), Micro LED (Micro Light-Emitting Diode), etc.
  • OLED Organic Light-Emitting Diode
  • Mini LED Mini Light-Emitting Diode
  • Micro LED Micro Light-Emitting Diode
  • the display substrate 100 further includes: a plurality of data lines DL, a first fan-out line FIP1, and a second fan-out line FIP2.
  • the data lines DL extend along the second direction Y, and a column of pixel circuits 10 is electrically connected to one data line DL.
  • At least one of the plurality of data lines DL is a set data line DL1, and the second fan-out line FIP2 is closer to the center line of the binding area BB along the second direction Y than the set data line DL1.
  • the first fan-out line FIP1 and the second fan-out line FIP2 are provided in the display area AA, the first fan-out line FIP1 extends along the first direction X, and the second fan-out line FIP2 extends along the second direction Y.
  • One end of the first fan-out line FIP1 is electrically connected to the setting data line DL1 , and the other end is electrically connected to the second fan-out line FIP2 .
  • At least one of the plurality of pixels P is a setting pixel PP, and one setting pixel PP is correspondingly provided with at least one second fan-out line FIP2.
  • the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP, or passes from the outside of the pixel circuit 10 located on the outside of the corresponding setting pixel PP, and extends to the binding area BB.
  • the set data line DL1 is further away from the center line of the binding area BB along the second direction Y.
  • the set data line DL1 is entirely located in the display area AA, and the ends of other data lines DL extend to the binding area BB.
  • the data line DL may include a first data line DL1 and a second data line DL2, wherein the first data line DL1 is a setting data line DL1.
  • the setting data line DL1 is located in the display area AA and does not extend to the binding area BB; the second fan-out line FIP2 and the second data line DL2 extend to the binding area BB.
  • the setting data line DL1, the first fan-out line FIP1 and the second fan-out line FIP2 are connected in sequence, and each first fan-out line FIP1 is electrically connected to a setting data line DL1 and a second fan-out line FIP2, respectively.
  • the second data line DL2 is directly extended to the binding area BB, and the data line DL1 is set as the data line DL in the display substrate 100 that needs to be led out to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2 in sequence.
  • This setting method can be called FIP (Fanout In Pixel).
  • the width of the frame of the display substrate 100 on one side for binding the driver for example, the width of the portion of the peripheral area AN shown in FIG2 located below the display area AA is d1, and the size of the binding area BB along the second direction Y is d2, d1 ⁇ d2.
  • the size d1 of the side of the peripheral area AN where the binding area BB is set can be reduced, which is conducive to realizing a narrow frame of the display device 1000.
  • the set data line DL1 is led out to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2, thereby increasing the display area AA for transmitting data signals.
  • the number of signal lines is increased, and the density of signal lines for transmitting data signals is increased, so that the overall resistance of the signal lines for transmitting data signals is reduced, which is conducive to achieving the transmission stability and reliability of data signals.
  • the newly added second fan-out lines FIP2 are respectively inserted between adjacent pixel circuits 10, which ensures the uniformity of the film structure of the display substrate 100, thereby ensuring the display effect of the display substrate 100.
  • the set pixel PP includes, for example, three sub-pixels P(x) arranged in sequence along the first direction X, for example, from the left side to the right side in FIG. 2 , they are the first sub-pixel PP(1), the second sub-pixel PP(2) and the third sub-pixel PP(3).
  • a second fan-out line FIP2 is correspondingly provided for a setting pixel PP in the display substrate 100 , and the second fan-out line FIP2 passes through the outer side of the pixel circuit 10 located on the outer side of the corresponding setting pixel PP and extends to the binding area BB.
  • the second fan-out line FIP2 passes through a side of the pixel circuit 10 of the first sub-pixel PP( 1 ) away from the pixel circuit 10 of the second sub-pixel PP( 2 ) and extends to the bonding area BB.
  • the second fan-out line FIP2 passes through a side of the pixel circuit 10 of the third sub-pixel PP(3) away from the pixel circuit 10 of the second sub-pixel PP(2), and extends to the bonding area BB.
  • a second fan-out line FIP2 is correspondingly provided for a setting pixel PP in the display substrate 100 , and the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP and extends to the binding area BB.
  • the second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the binding area BB; or, as shown in FIG. 3 , the second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the binding area BB.
  • two second fan-out lines FIP2 are correspondingly arranged for one setting pixel PP in the display substrate 100 .
  • the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP and extends to the binding area BB.
  • one second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the binding area BB; another second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the binding area BB.
  • a setting pixel PP in the display substrate 100 is correspondingly provided with three setting data lines DL1 and a second fan-out line FIP2, and the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP and extends to the binding area BB.
  • a second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the binding area BB; another second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the binding area BB; another second fan-out line FIP2 passes from the outside of the pixel circuit 10 located on the outside in the corresponding set pixel PP, and extends to the binding area BB.
  • four second fan-out lines FIP2 are correspondingly arranged for a set pixel PP in the display substrate 100, wherein, along the first direction X, the first second fan-out line FIP2 passes from the side of the pixel circuit 10 of the first sub-pixel PP(1) away from the second sub-pixel PP(2), and extends to the binding area BB; the second second fan-out line FIP2 passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2), and extends to the binding area BB; the third second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3), and extends to the binding area BB; the fourth second fan-out line FIP2 passes from the side of the pixel circuit 10 of the third sub-pixel PP(3) away from the second sub-pixel PP(2), and extends to the binding area BB.
  • the setting pixel PP includes three sub-pixels P(x), and both sides of the setting pixel PP along the first direction X are adjacent to other pixels P, one or two second fan-out lines FIP2 may be included between two adjacent pixels P (one of which is the setting pixel PP).
  • any one of the second fan-out lines FIP2 corresponding to the second setting pixel PP may be located between the two setting pixels PP, or between the sub-pixels P(x) in the second setting pixel PP, or on the side of the second setting pixel PP away from the first setting pixel PP.
  • the data line DL corresponding to at least a part of the multiple sub-pixels P(x) included in the pixel PP is led out from the display area AA to the binding area BB through the second fan-out line FIP2 instead of being led out from the peripheral area AN to the binding area BB, thereby reducing the wiring area of the data line DL in the peripheral area AN and reducing the dimension d1 of the side of the peripheral area AN where the binding area BB is set along the second direction Y, thereby achieving a narrow frame of the display device 1000.
  • the outer side of the pixel circuit 10 located on the outer side of the setting pixel PP refers to between the setting pixel PP and another pixel P adjacent to the setting pixel PP, and the other pixel P may also be the setting pixel PP.
  • Each set pixel PP may also include four, five or more sub-pixels P(x).
  • the number of second fan-out lines FIP2 corresponding to each set pixel PP is less than or equal to the number of sub-pixels P(x) included therein, and the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding set pixel PP, or passes from the outside of the pixel circuit 10 located on the outside of the corresponding set pixel PP, and extends to the binding area BB.
  • the number of second fan-out lines FIP2 corresponding to each set pixel PP is greater than the number of sub-pixels P(x) included therein, and a portion of the second fan-out line FIP2 passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding set pixel PP, and another portion passes from the outside of the pixel circuit 10 located on the outside of the corresponding set pixel PP, and extends to the binding area BB.
  • the data line DL needs to extend to the binding area BB and be bound and connected to a driver (eg, a driver circuit board or a driver chip, etc.) in the binding area BB.
  • the driver transmits a data signal to the data line DL so that the pixel circuit 10 can drive the light-emitting device 20 to emit light.
  • the size of the binding area BB is, for example, smaller than the size of the display area AA, and along the second direction Y, the binding area BB may be arranged opposite to the middle area of the display area AA.
  • the data lines DL located at both side edges of the display area AA along the first direction X are set data lines DL1 (first data lines DL1), and the data lines DL located in the middle area of the display area AA along the first direction X are second data lines DL2.
  • the display substrate does not include the first fan-out line FIP1 and the second fan-out line FIP2, and the end of the data line DL1 close to the binding area BB is set to extend toward the peripheral area AN and converge toward the binding area BB.
  • the size of the binding area BB is smaller than the size of the display area AA, so that the portion of the data line DL1 located in the peripheral area AN and extending into the binding area BB will occupy the space in the peripheral area AN, so that the portion of the peripheral area AN on the side where the binding area BB is set is larger in size along the second direction Y, and the border width of the side of the display substrate 100 for binding the driver is larger.
  • the second data line DL2 is arranged opposite to the binding area BB, and the set data line DL1 is located on both sides of the second data line DL2 along the first direction X.
  • the first data line DL1 located on both sides of the binding area BB is led out to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2, and the second data line DL2 arranged opposite to the binding area BB is directly led out to the binding area BB.
  • a plurality of data lines DL (set data line DL1 and second data line DL2) are led out from the display area AA to the binding area BB.
  • the data lines DL do not occupy the space in the peripheral area AN, which is beneficial for reducing the dimension d2 of the portion of the peripheral area AN on one side where the binding area BB is set along the second direction Y, thereby achieving a narrow frame of the display device 1000.
  • the number of binding areas BB can be multiple.
  • the display substrate 100 may include multiple binding areas BB, and the data lines DL arranged relative to the binding areas BB along the second direction Y can be considered as the second data lines DL2, and the remaining data lines DL can be considered as the first data lines DL1 (set data lines DL1).
  • the way of distinguishing the first data lines DL1 and the second data lines DL2 is not limited to this, and the first data lines DL1 and the second data lines DL2 can also be arranged in different areas as needed.
  • the display substrate 100 further includes: a first voltage signal line VSS extending along the second direction Y. At least one first voltage signal line VSS is correspondingly provided for one setting pixel PP, and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP, or passes from the outside of the pixel circuit 10 located on the outside of the corresponding setting pixel PP.
  • the pixel PP includes a first sub-pixel PP(1), a second sub-pixel PP(2) and a third sub-pixel PP(3) sequentially arranged along the first direction X as an example.
  • a first voltage signal line VSS is correspondingly disposed to a setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes through the outside of the pixel circuit 10 located outside of the corresponding setting pixel PP.
  • the first voltage signal line VSS passes through a side of the pixel circuit 10 of the first sub-pixel PP( 1 ) away from the pixel circuit 10 of the second sub-pixel PP( 2 ).
  • the first voltage signal line VSS passes through a side of the pixel circuit 10 of the third sub-pixel PP( 3 ) away from the pixel circuit 10 of the second sub-pixel PP( 2 ).
  • a setting pixel PP in the display substrate 100 is correspondingly provided with a first voltage signal line VSS, and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.
  • the first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); or, the first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3).
  • two first voltage signal lines VSS are correspondingly provided to one setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.
  • a first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); another first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3).
  • three first voltage signal lines VSS are correspondingly provided for one setting pixel PP in the display substrate 100 , and the first voltage signal line VSS passes between the pixel circuits 10 of two adjacent sub-pixels P(x) in the corresponding setting pixel PP.
  • a first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); another first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3); and another first voltage signal line VSS passes from the outside of the pixel circuit 10 located on the outside in the corresponding set pixel PP.
  • first voltage signal lines VSS are correspondingly arranged for a set pixel PP in the display substrate 100, wherein, along the first direction X, the first first voltage signal line VSS passes from a side of the pixel circuit 10 of the first sub-pixel PP(1) away from the second sub-pixel PP(2); the second first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel PP(1) and the second sub-pixel PP(2); the third first voltage signal line VSS passes between the pixel circuits 10 of the second sub-pixel PP(2) and the third sub-pixel PP(3); and the fourth first voltage signal line VSS passes from a side of the pixel circuit 10 of the third sub-pixel PP(3) away from the second sub-pixel PP(2).
  • the setting pixel PP includes three sub-pixels P(x), and the setting pixel PP is adjacent to other pixels P on both sides along the first direction X, one or two first voltage signal lines VSS may be included between two adjacent pixels P (one of which is the setting pixel PP).
  • any one of the first voltage signal lines VSS corresponding to the second setting pixel PP may be located between the two setting pixels PP.
  • the pixel is located between the two setting pixels PP, or between the sub-pixels P(x) in the second setting pixel PP, or on a side of the second setting pixel PP away from the first setting pixel PP.
  • the number of wiring lines of the first voltage signal line VSS in the display area AA is increased, and the density of the first voltage signal line VSS in the display area AA is increased, thereby reducing the overall resistance of the first voltage signal line VSS, which is beneficial to reducing the voltage drop of the first voltage signal line VSS and ensuring the transmission stability and reliability of the first voltage signal.
  • a second fan-out line FIP2 passes between the pixel circuits 10 of a pair of adjacent sub-pixels P(x), and a first voltage signal line VSS passes between the pixel circuits 10 of another pair of adjacent sub-pixels P(x).
  • the density of signal lines for transmitting the first voltage signal and the data signal within the display area AA is increased, thereby reducing the overall resistance of the first voltage signal line VSS and the data line DL, which is beneficial to reducing the voltage drop of the first voltage signal line VSS and the data line DL, and ensuring the transmission stability and reliability of the first voltage signal and the data signal.
  • each pixel P includes three sub-pixels P(x). It is set that the pixel PP is correspondingly provided with a second fan-out line FIP2 and a first voltage signal line VSS, the second fan-out line FIP2 passes between the pixel circuits 10 of a pair of adjacent sub-pixels P(x) among the three sub-pixels P(x), and the first voltage signal line VSS passes between the pixel circuits 10 of another pair of adjacent sub-pixels P(x) among the three sub-pixels P(x).
  • the pixel PP is set to include a first sub-pixel P(1), a second sub-pixel P(2), and a third sub-pixel P(3) sequentially arranged along a first direction X.
  • the first voltage signal line VSS passes between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2)
  • the second fan-out line FIP2 passes between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3), and extends to the binding area BB.
  • the second fan-out line FIP2 may pass between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2) and extend to the binding area BB; the first voltage signal line VSS may pass between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3).
  • one first voltage signal line VSS and one second fan-out line FIP2 pass between the pixel circuits 10 of the same pair of adjacent sub-pixels P(x).
  • the pixel circuit 10 includes, for example, a plurality of transistors TFT (Thin Film Transistor), at least one capacitor and at least one connection node. Among them, some nodes in the connection nodes (such as the fifth node N5 shown in FIG. 11 ) play a key role in the operation of the pixel circuit 10. The specific structure of the pixel circuit 10 is described later and will not be described here.
  • TFT Thin Film Transistor
  • the wiring density of the signal line for transmitting the first voltage signal in the display area AA is increased, the resistance of the signal line for transmitting the first voltage signal in the display area AA is reduced, and the voltage drop of the first voltage signal is reduced.
  • the first voltage signal line VSS serves as a constant voltage signal line, which can play a signal shielding effect, thereby preventing the data signal transmitted by the second fan-out line FIP2 passing through the pixel circuits 10 of adjacent sub-pixels P(x) from generating signal crosstalk with the nodes within the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.
  • the pixel P includes three sub-pixels P(x).
  • the pixel PP is set to be correspondingly provided with a second fan-out line FIP2 and a first voltage signal line VSS, and the second fan-out line FIP2 and the first voltage signal line VSS pass between the pixel circuits 10 of the same pair of adjacent sub-pixels P(x) among the three sub-pixels P(x).
  • the pixel PP is set to include a first sub-pixel P(1), a second sub-pixel P(2), and a third sub-pixel P(3) sequentially arranged along a first direction X.
  • the first voltage signal line VSS and the second fan-out line FIP2 both pass between the pixel circuits 10 of the first sub-pixel P(1) and the second sub-pixel P(2).
  • the first voltage signal line VSS and the second fan-out line FIP2 may also pass between the pixel circuits 10 of the second sub-pixel P(2) and the third sub-pixel P(3).
  • the second fan-out line FIP2 is provided with a second break DK2, and the second break DK2 divides the second fan-out line FIP2 into an effective part FIP21 and a redundant part FIP22.
  • One end of the effective part FIP21 of the second fan-out line FIP2 is electrically connected to the first fan-out line FIP1, and the other end extends to the binding area BB.
  • the second break DK2 divides the second fan-out line FIP2 into an effective part FIP21 and a redundant part FIP22 that are electrically insulated from each other.
  • one end of the effective part FIP21 of the second fan-out line FIP2 extends to the binding area BB, and the other end is connected to the first fan-out line FIP1.
  • the effective part FIP21 of the second fan-out line FIP2 is electrically insulated from the redundant part FIP22 of the second fan-out line FIP2 on one side away from the binding area BB. That is, the first fan-out line FIP1 is electrically connected to the effective part FIP21 of the second fan-out line FIP2, and extends to the binding area BB through the effective part FIP21 of the second fan-out line FIP2.
  • the second fan-out line FIP2 is divided into an effective part FIP21 and a redundant part FIP22 which are electrically insulated from each other through the second break DK2.
  • the data signal is emitted from the driver bound in the binding area BB, and is transmitted to the corresponding sub-pixel P(x) in sequence through the effective part FIP21 of the second fan-out line FIP2, the first fan-out line FIP1 and the set data line DL1.
  • the transmission path of the data signal does not pass through the redundant part FIP22 of the second fan-out line FIP2, which is beneficial to shortening the transmission path of the data signal on the second fan-out line FIP2, thereby reducing the voltage drop of the data signal during the transmission process on the second fan-out line FIP2, preventing signal distortion caused by the voltage drop, and ensuring the accuracy of data signal transmission.
  • redundant part FIP22 of the second fan-out line FIP2 may be configured not to transmit signals, or configured to transmit signals other than data signals.
  • the display substrate 100 further includes a first connection portion LJ1, through which the first voltage signal line VSS and the redundant portion FIP22 of the second fan-out line FIP2 are electrically connected.
  • the redundant portion FIP22 of the second fan-out line FIP2 is configured to transmit a first voltage signal.
  • the redundant part FIP22 of the second fan-out line FIP2 is connected to the first voltage signal line VSS through the first connection part LJ1, thereby increasing the wiring area of the first voltage signal line VSS in the display area AA, so that the density of the first voltage signal line VSS in the display area AA is increased, which is beneficial to reducing the resistance of the first voltage signal line VSS, and further reducing the voltage drop of the first voltage signal line VSS.
  • the first voltage signal line VSS and the second fan-out line FIP2 passing through the pixel circuits 10 of the same pair of adjacent sub-pixels P(x) are arranged adjacent to each other, and the first voltage signal line VSS, the second fan-out line FIP2 and the first connecting portion LJ1 are arranged on the same layer and are integrally formed.
  • a conductive structure layer is first formed by a sputtering process, and then the conductive structure layer is patterned by an etching process, so as to form the connected first voltage signal line VSS, the first connection part LJ1 and the second fan-out line FIP2.
  • the first voltage signal line VSS, the second fan-out line FIP2 and the first connection part LJ1 are formed at the same time in the same preparation step, and the first voltage signal line VSS, the first connection part LJ1 and the second fan-out line FIP2 are connected to each other as an integrated structure, and there is no need to set up other structures to connect the three.
  • adding the first connection part LJ1 and the second fan-out line FIP2 there is no need to increase the preparation process steps of the display substrate 100, which is conducive to reducing production costs.
  • the preparation process of the first voltage signal line VSS, the first connection portion LJ1 and the second fan-out line FIP2 may also adopt other methods, which are only exemplary descriptions and are not intended to limit the present disclosure.
  • the first fan-out line FIP1 is provided with a first break DK1, and the first break DK1 divides the first fan-out line FIP1 into an effective part FIP11 and a redundant part FIP12.
  • One end of the effective part 11 of the first fan-out line FIP1 is electrically connected to the set data line DL1, and the other end is electrically connected to the effective part FIP21 of the second fan-out line FIP2.
  • the first break DK1 divides the first fan-out line FIP1 into an effective part FIP11 and a redundant part FIP12 that are electrically insulated from each other.
  • one end of the effective part FIP11 of the first fan-out line FIP1 extends to the binding area BB, and the other end is connected to the second fan-out line FIP2.
  • the effective part FIP21 of the first fan-out line FIP1 is electrically insulated from the redundant part FIP12 of the first fan-out line FIP1 on one side away from the binding area BB.
  • the effective part FIP11 of the first fan-out line FIP1 is electrically connected to the effective part FIP21 of the second fan-out line FIP2, and extends to the binding area BB through the effective part FIP21 of the second fan-out line FIP2.
  • the first fan-out line FIP1 is divided into an effective part FIP11 and a redundant part FIP12 which are electrically insulated from each other through the first break DK1.
  • the data signal is sent from the driver bound in the binding area BB, and is transmitted to the corresponding sub-pixel P(x) through the effective part FIP21 of the second fan-out line FIP2, the effective part FIP11 of the first fan-out line FIP1 and the set data line DL1 in sequence.
  • the transmission path of the data signal does not pass through the redundant part FIP22 of the second fan-out line FIP2 and the redundant part FIP12 of the first fan-out line FIP1, which is conducive to shortening the transmission path of the data signal on the first fan-out line FIP1 and the second fan-out line FIP2, thereby reducing the voltage drop of the data signal during the transmission process on the first fan-out line FIP1 and then the second fan-out line FIP2, thereby preventing the voltage drop.
  • the signal distortion caused by this is beneficial to ensure the accuracy of data signal transmission.
  • the display substrate 100 further includes: a second connection portion LJ2.
  • a via K is provided between the second connection portion LJ2 and the redundant portion FIP22 of the second fan-out line FIP2 along the thickness direction of the display substrate 100, one end of the second connection portion LJ2 is electrically connected to the redundant portion FIP12 of the first fan-out line FIP1, and the other end of the second connection portion LJ2 is electrically connected to the redundant portion FIP22 of the second fan-out line FIP2 through the via K.
  • the first fan-out line FIP1 and the second fan-out line FIP2 are located in different film layer structures, that is, along the thickness direction of the display substrate 100 , the film layer structures where the first fan-out line FIP1 and the second fan-out line FIP2 are located are at different distances from the display substrate 100 .
  • An insulating spacer layer such as a planarization layer 6, may be further included between the first fan-out line FIP1 and the second fan-out line FIP2.
  • the first fan-out line FIP1 and the second fan-out line FIP2 are electrically insulated from each other.
  • a via K is provided on the planarization layer 6 corresponding to a portion between the redundant portion FIP22 of the second fan-out line FIP2 and one end close to the second connection portion LJ2, so that one end of the second connection portion LJ2 is connected to the redundant portion FIP22 of the second fan-out line FIP2 through the via K.
  • the redundant portion FIP12 of the first fan-out line FIP1 is connected to the redundant portion FIP22 of the second fan-out line FIP2 through the second connection portion LJ2, thereby increasing the wiring area of the first voltage signal line VSS in the display area AA, thereby increasing the density of the first voltage signal line VSS in the display area AA, and the redundant portion FIP12 of the first fan-out line FIP1 is provided in parallel with the redundant portion FIP22 of the second fan-out line FIP2, thereby reducing the resistance of the first voltage signal line VSS, thereby reducing the voltage drop of the first voltage signal line VSS.
  • the second connection portion LJ2 and the redundant portion FIP12 of the first fan-out line FIP1 are disposed in the same layer and are integrally formed.
  • a conductive structure layer is first formed by a sputtering process, and then, for example, the conductive structure layer is patterned by an etching process, so as to form the redundant part FIP12 and the second connection part LJ2 of the first fan-out line FIP1 that are connected.
  • the redundant part FIP12 and the second connection part LJ2 of the first fan-out line FIP1 are formed at the same time in the same preparation step, and the second connection part LJ2 and the redundant part FIP12 of the first fan-out line FIP1 are an integral structure connected to each other, and there is no need to set up other structures to connect the two. While the redundant part FIP12 and the second connection part LJ2 of the first fan-out line FIP1 are added, there is no need to increase the preparation process steps of the display substrate 100, which is conducive to reducing production costs.
  • redundant part FIP12 of the first fan-out line FIP1 and the second connection part LJ2 may also be prepared by other methods, which are only illustrative and not intended to limit the present disclosure.
  • the display substrate 100 further includes: a plurality of reference voltage signal lines VRef1.
  • the reference voltage signal line VRef1 extends along the second direction Y, and a column of pixel circuits 10 is electrically connected to a reference voltage signal line VRef1.
  • the reference voltage signal line VRef1 connected to one column of pixel circuits 10 and the data line DL connected to the other column of pixel circuits 10 are arranged close to each other.
  • the second fan-out line FIP2 is arranged between the reference voltage signal line VRef1 and the data line DL which are arranged close to each other.
  • each column of pixel circuits 10 is respectively connected to a data line DL and a reference voltage line.
  • the signal line VRef1 is electrically connected
  • a column of pixel circuits 10 extends along the second direction Y
  • the data line DL and the reference voltage signal line VRef1 corresponding to the column of pixel circuits 10 are located on both sides of the pixel circuit 10 along the first direction X.
  • a second fan-out line FIP2 is inserted into two adjacent columns of pixel circuits 10 to lead the set data line DL1 from the display area AA to the binding area BB.
  • the first voltage signal line VSS of the display substrate 100 is disposed between the reference voltage signal line VRef1 and the data line DL which are disposed close to each other.
  • the data line DL and the reference voltage signal line VRef1 corresponding to a column of pixel circuits 10 are located on both sides of the pixel circuit 10 along the first direction X.
  • a first voltage signal line VSS is inserted into two adjacent columns of pixel circuits 10, which increases the density of the first voltage signal lines VSS in the display area AA, thereby reducing the overall resistance of the first voltage signal lines VSS, which is beneficial to reducing the voltage drop of the first voltage signal lines VSS, and ensuring the transmission stability and reliability of the first voltage signal.
  • the pixel circuit 10 includes a plurality of transistors TFT and at least one capacitor.
  • the pixel circuit 10 may be a "3T1C” circuit, a “7T1C” circuit, an “8T1C” circuit, or a “9T2C” circuit, etc., wherein “T” refers to a TFT, and the number before “T” refers to the number of TFTs; “C” refers to a capacitor, and the number before “C” refers to the number of capacitors.
  • the pixel circuit 10 is a "9T2C" circuit as an example for schematic description, but the embodiments of the present disclosure are not limited thereto, and any other pixel circuit 10 may also be considered as long as the same technical concept is applied.
  • the pixel circuit 10 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1 and a second capacitor C2, and signal lines electrically connected to the pixel circuit 10 (e.g., a data signal line DL, a first enable signal line EM1, a second enable signal line EM2, an initialization signal line Vinit, a first voltage signal line VSS, a second voltage signal line VDD, etc.).
  • a data signal line DL e.g., a data signal line DL, a first enable signal line EM1, a second enable signal line EM2, an initialization signal line Vinit, a first voltage signal line VSS, a second voltage signal line VDD, etc.
  • each pixel circuit 10 is correspondingly connected to three gate signal lines GL, namely a first gate signal line GL1 , a second gate signal line GL2 , and a third gate signal line GL3 .
  • a gate of the first transistor T1 is electrically connected to the third gate signal line GL3 , a first electrode of the first transistor T1 is electrically connected to the first initialization signal line Vinit1 , and a second electrode of the first transistor T1 is electrically connected to the first node N1 .
  • a gate of the second transistor T2 is electrically connected to the second gate signal line GL2 , a first electrode of the second transistor T2 is electrically connected to the first node N1 , and a second electrode of the second transistor T2 is electrically connected to the third node N3 .
  • a gate of the third transistor T3 is electrically connected to the first node N1 , a first electrode of the third transistor T3 is electrically connected to the second node N2 , and a second electrode of the third transistor T3 is electrically connected to the third node N3 .
  • a gate of the fourth transistor T4 is electrically connected to the first gate signal line GL1 , a first electrode of the fourth transistor T4 is electrically connected to the data signal line DL, and a second electrode of the fourth transistor T4 is electrically connected to the fifth node N5 .
  • a gate of the fifth transistor T5 is electrically connected to the first enable signal line EM1 , a first electrode of the fifth transistor T5 is electrically connected to the second voltage signal line VDD, and a second electrode of the fifth transistor T5 is electrically connected to the second node N2 .
  • a gate of the sixth transistor T6 is electrically connected to the second enable signal line EM2 , a first electrode of the sixth transistor T6 is electrically connected to the third node N3 , and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4 .
  • a gate of the seventh transistor T7 is electrically connected to the scan signal line Scan, a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal line Vinit2, and a second electrode of the seventh transistor T7 is electrically connected to the fourth node N4.
  • a gate of the eighth transistor T8 is electrically connected to the scan signal line Scan, a first electrode of the eighth transistor T8 is electrically connected to the second reference voltage signal line VRef2, and a second electrode of the eighth transistor T8 is electrically connected to the second node N2.
  • a gate of the ninth transistor T9 is electrically connected to the second gate signal line GL2 , a first electrode of the ninth transistor T9 is electrically connected to the first reference voltage signal line VRef1 , and a second electrode of the ninth transistor T9 is electrically connected to the fifth node N5 .
  • the first plate C11 of the first capacitor C1 is electrically connected to the fifth node N5, and the second plate C12 of the first capacitor C1 is electrically connected to the first node N1.
  • the first plate C21 of the second capacitor C2 is electrically connected to the fifth node N5, and the second plate C22 of the second capacitor C2 is electrically connected to the second voltage signal line VDD.
  • the fifth node N5 is electrically connected to the first capacitor C1 and the second capacitor C2, and a voltage change of the fifth node N5 may cause a change in the storage voltages of the first capacitor C1 and the second capacitor C2.
  • the display substrate 100 includes a substrate 1, a semiconductor layer 2, a multi-layer gate layer 3, and a multi-layer source-drain conductive layer 4.
  • the multi-layer source-drain conductive layer 4 can be collectively referred to as a functional film layer in the display substrate 100, each functional film layer has a set conductive pattern, and adjacent functional film layers are separated by an insulating film layer structure.
  • the substrate 1 may be a rigid substrate, the material of which includes but is not limited to glass.
  • the substrate 1 may be a flexible substrate, the material of which includes but is not limited to any one of PI (Polyimide), PC (Polycarbonate) or PVC (Polyvinyl Chloride).
  • the semiconductor layer 2 includes an active layer pattern.
  • the active layer pattern includes an active layer 21 of each transistor TFT.
  • the thin film transistor TFT may be a low temperature polysilicon thin film transistor, that is, the semiconductor layer 2 is made of low temperature polysilicon.
  • the thin film transistor TFT may also be an oxide thin film transistor, that is, the semiconductor layer 2 is made of metal oxide, such as indium gallium zinc oxide or indium gallium tin oxide.
  • the multi-layer gate layer 3 includes a first gate layer 31 and a second gate layer 32 sequentially disposed from one side of the substrate 1 .
  • the first gate layer 31 includes a first gate conductive pattern, the first gate conductive pattern overlaps with the orthographic projection of the active layer pattern on the substrate 1 , and the overlapping portion of the first gate conductive pattern and the active layer pattern serves as the gate of each transistor TFT.
  • the first gate conductive pattern includes a scan signal line Scan extending along the first direction X, and the scan signal line Scan is configured to transmit a scan signal to the transistor TFT.
  • the second gate layer 32 includes a second gate conductive pattern, and the second gate conductive pattern includes an auxiliary reference voltage signal line VRef11 .
  • the auxiliary reference voltage signal line VRef11 extends along the first direction X and is connected to the reference voltage signal line VRef1 .
  • the second gate conductive pattern includes a plurality of signal lines extending along the first direction X, such as an auxiliary reference voltage signal line VRef11, a second reference voltage signal line VRef2, a first initialization signal line Vinit1, a second enable signal line EM2, and a repair signal line Repair.
  • the first initialization signal line Vinit1 is configured to transmit an initialization signal to the transistor TFT.
  • the second enable signal line EM2 is configured to transmit a light emission control signal to the transistor TFT.
  • the display substrate 100 further includes a multi-layer gate insulating layer 5 .
  • the multi-layer gate insulating layer 5 includes a first gate insulating layer 51 disposed between the semiconductor layer 2 and the first gate layer 1 , and a second gate insulating layer 52 disposed between the first gate layer 31 and the second gate layer 32 .
  • the first gate conductive pattern includes a first plate pattern
  • the first plate pattern includes a first plate (e.g., a first plate C11 of the first capacitor C1, and a first plate C21 of the second capacitor C2) of a capacitor (e.g., a first capacitor C1 and a second capacitor C2) of each pixel circuit 10.
  • the second gate layer 32 also includes a second plate pattern, the second plate pattern includes a second plate (e.g., a second plate C12 of the first capacitor C1, and a second plate C22 of the second capacitor C2) of the capacitor of each pixel circuit 10.
  • the first plate pattern and the second plate pattern overlap in their orthographic projections on the substrate 1.
  • the second plate C12 of the first capacitor C1 overlaps with the first plate C11 to form the first capacitor C1
  • the second plate C22 of the second capacitor C2 overlaps with the first plate C21 to form the second capacitor C2.
  • a pair of adjacent source-drain conductive layers 4 in the multi-layer source-drain conductive layer 4 are respectively a first set source-drain conductive layer and a second set source-drain conductive layer, and the first set source-drain conductive layer is closer to the substrate 1 than the second set source-drain conductive layer.
  • the first fan-out line FIP1 is provided in the first set source-drain conductive layer
  • the data line DL and the second fan-out line FIP2 are provided in the second set source-drain conductive layer.
  • an insulating dielectric layer ILD is provided between the second gate layer 32 and the first source-drain conductive layer 41, the second gate layer 32 is electrically insulated from the first source-drain conductive layer 41, a via is provided on the insulating dielectric layer ILD, and the second gate conductive pattern in the second gate layer 32 and the first conductive pattern in the first source-drain conductive layer 41 that need to be connected are electrically connected through the via on the insulating dielectric layer ILD.
  • an insulating spacer layer (e.g., a planarization layer 6) is further provided between the first set source-drain conductive layer and the second set source-drain conductive layer, the first set source-drain conductive layer and the second set source-drain conductive layer are electrically insulated, a via is provided on the insulating spacer layer, and the parts of the first set source-drain conductive layer and the second set source-drain conductive layer that need to be connected can be electrically connected through the via on the insulating spacer layer.
  • One end of the first fan-out line FIP1 is connected to the set data line DL1 through a via, and the other end is connected to the set data line DL1 through another via.
  • the hole is connected to the second fan-out line FIP2.
  • the first set source-drain conductive layer includes a first fan-out line FIP1 extending along a first direction X, and may also include other signal lines extending along the first direction X.
  • the second set source-drain conductive layer includes a second fan-out line FIP2 and a data line DL extending along a second direction Y, and may also include other signal lines extending along the second direction Y.
  • the multiple signal lines included in each source-drain conductive layer may all extend in the same direction, simplifying the structure of the conductive pattern inside, thereby simplifying the preparation process of the source-drain conductive layer.
  • the data lines DL (set data lines DL1) located on both sides of the display area AA along the first direction X can be led out from the display area AA to the binding area BB through the first fan-out line FIP1 and the second fan-out line FIP2, thereby reducing the width of the peripheral area AN of the display substrate 100 on the side of the binding area BB, thereby reducing the border width of the side of the display device 1000 used to bind the driver.
  • the first fan-out line FIP1 is disposed in the first set source-drain conductive layer, and the auxiliary reference voltage signal line VRef11 is located in the second gate layer 32.
  • the auxiliary reference voltage signal line VRef11 is located above the fifth node N5
  • the first fan-out line FIP1 is located above the auxiliary reference voltage signal line VRef11. That is, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1.
  • the auxiliary reference voltage signal line VRef11 is configured to transmit a reference voltage signal, and the auxiliary reference voltage signal is a constant voltage signal. In this way, the auxiliary reference voltage line VRef11 between the fifth node N5 and the first fan-out line FIP1 can play a shielding effect, preventing signal crosstalk between the data signal transmitted on the first fan-out line FIP and the fifth node N5, thereby ensuring the normal operation of the pixel circuit 10.
  • the multilayer source-drain conductive layer 4 includes a first source-drain conductive layer 41 and a second source-drain conductive layer 42 , wherein the first source-drain conductive layer 41 is a first set source-drain conductive layer and the second source-drain conductive layer 42 is a second set source-drain conductive layer.
  • the first fan-out line FIP1 is disposed on the first source-drain conductive layer 41
  • the data line DL and the second fan-out line FIP2 are disposed on the second source-drain conductive layer 42 .
  • the first source-drain conductive layer 41 includes a first source-drain conductive pattern, and the first source-drain conductive pattern includes a source 411 and a drain 412 of each transistor TFT.
  • the source 411 and the drain 412 may be identical in structure, so the source 411 and the drain 412 of the transistor TFT may be interchangeable.
  • the first source-drain conductive pattern further includes a first gate line GL1, a second gate line GL2, a third gate line GL3, a first fan-out line FIP1, an auxiliary second voltage signal line DIP, an auxiliary first voltage signal line SIP, and a first enable signal line EM1 extending along the first direction X.
  • the first enable signal line EM1 is configured to transmit a light emitting control signal to the transistor TFT.
  • an opening is provided on the second electrode plate C22 of the second capacitor C2, and the first source-drain conductive layer 41 also includes a connecting line LX, one end of the connecting line LX is connected to the first electrode plate C21 of the second capacitor C2 through the opening, and the other end is connected to the fifth node N5 in the dotted box in FIG. 14 .
  • the auxiliary reference voltage signal line VRef11 is located above the fifth node N5, and the first fan-out line FIP1 is located above the auxiliary reference voltage signal line VRef11 in the thickness direction of the display substrate 100. That is, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1.
  • the auxiliary reference voltage signal line VRef11 is configured to transmit a reference voltage signal, and the auxiliary reference voltage signal is a constant voltage signal. In this way, the auxiliary reference voltage line VRef11 between the fifth node N5 and the first fan-out line FIP1 can play a shielding effect, preventing signal crosstalk between the data signal transmitted on the first fan-out line FIP and the fifth node N5, thereby ensuring the normal operation of the pixel circuit 10.
  • the display substrate 100 further includes: a multi-layer planarization layer 6, the multi-layer planarization layer 6 includes a first planarization layer 61 and a second planarization layer 62.
  • the first planarization layer 61 is disposed between the first source-drain conductive layer 41 and the second source-drain conductive layer 42
  • the second planarization layer 62 is disposed on a side of the second source-drain conductive layer 42 away from the first source-drain conductive layer 41.
  • the second source-drain conductive layer 42 includes a data line DL extending along a second direction Y, a first voltage signal line VSS, a second voltage signal line VDD, a second fan-out line FIP2 , and a reference voltage signal line VRef1 .
  • a plurality of vias are provided on the first planarization layer 61, and the first voltage signal line VSS is electrically connected to the auxiliary first voltage signal line SIP through the vias on the first planarization layer 61, thereby increasing the number of signal lines for transmitting the first voltage signal in the display area AA without increasing the film layer structure, increasing the wiring density of the signal lines for transmitting the first voltage signal in the display area AA, and reducing the resistance of the first voltage signal line VSS.
  • the second voltage signal line VDD is electrically connected to the auxiliary first voltage signal line DIP through a via on the first planarization layer 61, thereby increasing the number of signal lines for transmitting the second voltage signal in the display area AA without increasing the film layer structure, increasing the wiring density of the signal lines for transmitting the second voltage signal in the display area AA, and reducing the resistance of the second voltage signal line VDD.
  • the multi-layer source-drain conductive layer 4 includes a first source-drain conductive layer 41 , a second source-drain conductive layer 42 and a third source-drain conductive layer 43 , the first source-drain conductive layer 41 is a first set source-drain conductive layer, and the second source-drain conductive layer 42 is a second set source-drain conductive layer.
  • the first fan-out line FIP1 is disposed on the first source-drain conductive layer 41
  • the data line DL and the second fan-out line FIP2 are disposed on the second source-drain conductive layer 42 .
  • the multi-layer planarization layer 6 further includes a third planarization layer 63 , which is disposed on a side of the third source-drain conductive layer 43 away from the second source-drain conductive layer 42 .
  • the multi-layer source-drain conductive layer 4 includes a first source-drain conductive layer 41 , a second source-drain conductive layer 42 and a third source-drain conductive layer 43 , the second source-drain conductive layer 42 is a first set source-drain conductive layer, and the third source-drain conductive layer 43 is a second set source-drain conductive layer.
  • the second source-drain conductive layer 42 is a first set source-drain conductive layer
  • the third source-drain conductive layer 43 is a second set source-drain conductive layer.
  • the first fan-out line FIP1 is provided on the second source-drain conductive layer 42
  • the data line DL and the second fan-out line FIP2 are provided on the The third source-drain conductive layer 43 .
  • the display substrate 100 may include two semiconductor layers, wherein the material of one semiconductor layer includes, for example, low-temperature polysilicon, and the material of the other semiconductor layer includes, for example, metal oxide, and the active layers of the multiple transistors TFT included in the pixel circuit 10 are respectively located in the two semiconductor layers.
  • the multiple transistors TFT included in the pixel circuit 10 include some low-temperature polysilicon thin film transistors and some oxide thin film transistors.
  • the display substrate 100 further includes: a plurality of auxiliary reference voltage signal lines VRef11 disposed on a side of the semiconductor layer 2 away from the substrate 1.
  • the auxiliary reference voltage signal line VRef11 extends along a first direction X and is electrically connected to the reference voltage signal line VRef1.
  • the first fan-out line FIP1 is disposed on a side of the auxiliary reference voltage signal line VRef11 away from the substrate 1. In an orthographic projection onto the substrate 1, the first fan-out line FIP1 overlaps with the auxiliary reference voltage signal line VRef11 and overlaps with part of the semiconductor layer 2.
  • the auxiliary reference voltage signal line VRef11 is located above the fifth node N5, and the first fan-out line FIP1 is located above the auxiliary reference voltage signal line VRef11. That is, the auxiliary reference voltage signal line VRef11 is located between the fifth node N5 and the first fan-out line FIP1, so that the auxiliary reference voltage signal transmitted by the auxiliary reference voltage signal line VRef11 is a constant voltage signal, which can play a shielding effect, prevent the data signal transmitted on the first fan-out line FIP from generating signal crosstalk with the fifth node N5, and ensure the normal operation of the pixel circuit 10.
  • the first fan-out line FIP1 extends along the first direction X, and a shielding structure is provided between the first fan-out line FIP1 and the fifth node N5 of a row of pixel circuits 10 adjacent thereto, so as to prevent signal crosstalk between the data signal transmitted by the first fan-out line FIP1 and the fifth node N5 of the pixel circuit 10.
  • the shielding structure may be an auxiliary reference voltage signal line VRef11 located between the first fan-out line FIP1 and the fifth node N5 along the thickness direction of the display substrate 100, or may be other signal lines that transmit constant voltage signals.
  • the display substrate 100 further includes: a plurality of second voltage signal lines VDD.
  • the second voltage signal lines VDD extend along the second direction Y, and a column of pixel circuits 10 is electrically connected to a second voltage signal line VDD.
  • the film layer where the plurality of second voltage signal lines VDD are located is located on the side of the film layer where the first fan-out line FIP1 is located away from the substrate 1 .
  • the second voltage signal line VDD covers the first break DK1 of the first fan-out line FIP1 .
  • the first fan-out line FIP1 is located at the first source-drain conductive layer 41, and the second voltage signal line VDD is located at the second source-drain conductive layer 42.
  • the orthographic projection of the first break DK1 on the first fan-out line FIP1 on the display substrate 100 falls within the range of the orthographic projection of the second voltage signal line VDD on the display substrate 100, that is, the first break DK1 is blocked by the second voltage signal line VDD, and when ambient light from the side of the substrate 1 away from the first source-drain conductive layer 41 is emitted toward the substrate 1, the portion of the ambient light emitted toward the first fan-out line FIP1 where the break DK1 is not set can be blocked and reflected by the first fan-out line FIP1, and the portion of the ambient light emitted toward the first break DK1 can be blocked and reflected by the second voltage signal line VDD, thereby reducing the difference in light reflectivity between the first source-drain conductive layer 41 at
  • the number of the second breaks DK2 on the second fan-out line FIP2 is greater than or equal to the number of the first breaks DK1 on the first fan-out line FIP1.
  • the number of second breaks DK2 on the second fan-out line FIP2 is half the number of first breaks DK1 on the first fan-out line FIP1.
  • two first breaks DK1 are provided on each first fan-out line FIP1
  • one second break DK2 is provided on each second fan-out line FIP2.
  • each first fan-out line FIP1 is provided with a first break DK1
  • each second fan-out line FIP2 is provided with a second break DK2.
  • the length of the first fan-out line FIP1 along the first direction X is, for example, the same or substantially the same as the length of the display area AA along the first direction X
  • the length of the second fan-out line FIP1 along the second direction Y is, for example, the same or substantially the same as the length of the display area AA along the second direction Y.
  • One end of the effective portion FIP21 of the second fan-out line FIP2 extends to the binding area BB, and the other end extends toward the display area AA along the second direction Y and is connected to one end of the effective portion FIP11 of the first fan-out line FIP1, and the other end of the effective portion FIP11 of the first fan-out line FIP1 is connected to a setting data line DL1.
  • a first break DK1 may be disposed on the first fan-out line FIP1 connected to the setting data line DL1 .
  • two first breaks DK1 may be provided on the first fan-out line FIP1 connected to the setting data line DL1, and the two first breaks DK1 are respectively provided on both sides of the setting data line DL1 along the first direction X.
  • the first fan-out line FIP1 has two redundant parts FIP12, and the two redundant parts FIP12 may be respectively connected to two signal lines (such as the first voltage signal line VSS or the second voltage signal line VDD, etc.), so as to increase the wiring density of the signal lines connected thereto in the display area AA, thereby reducing the resistance of the signal lines connected thereto.
  • the two redundant parts FIP12 may be respectively connected to two signal lines (such as the first voltage signal line VSS or the second voltage signal line VDD, etc.), so as to increase the wiring density of the signal lines connected thereto in the display area AA, thereby reducing the resistance of the signal lines connected thereto.
  • first fan-out line FIP1 and the second fan-out line FIP2 can be adaptively designed according to actual needs, which is only an exemplary description here and is not intended to limit the present disclosure.
  • the display substrate 100 further includes: a gate signal line GL1, an enable signal line EM, an auxiliary first voltage signal line SIP and an auxiliary second voltage signal line DIP, all extending along the first direction X.
  • the pixel circuit 10 is electrically connected to the gate signal line GL1 and the enable signal line EM.
  • the auxiliary first voltage signal line SIP is electrically connected to the first voltage signal line VSS, and the auxiliary second voltage signal line DIP is electrically connected to the second voltage signal line VDD.
  • the first set source-drain conductive layer is provided with at least one of a gate signal line GL1, an enable signal line EM, an auxiliary first voltage signal line SIP, and an auxiliary second voltage signal line DIP. At least one of the signal line EM, the auxiliary first voltage signal line SIP, and the auxiliary second voltage signal line DIP covers the second break DK2 of the second fan-out line FIP2.
  • the enable signal line EM includes a first enable signal line EM1 and a second enable signal line EM2.
  • the pixel circuit 10 is electrically connected to the first enable signal line EM1 and the second enable signal line EM2.
  • the first set source-drain conductive layer is the first source-drain conductive layer 41.
  • the first set source-drain conductive layer is the first source-drain conductive layer 41 or the second source-drain conductive layer 42.
  • the first set source-drain conductive layer is the first source-drain conductive layer 41
  • the second set source-drain conductive layer is the second source-drain conductive layer 42.
  • At least one of the gate signal line GL1, the enable signal line EM, the auxiliary first voltage signal line SIP and the auxiliary second voltage signal line DIP is located in the first set source-drain conductive layer, the second fan-out line FIP2 is located in the second set source-drain conductive layer, and the first set source-drain conductive layer is located between the second set source-drain conductive layer and the substrate 1.
  • the enable signal line EM, the auxiliary first voltage signal line SIP and the auxiliary second voltage signal line DIP in the first set source-drain conductive layer covers the second break DK2 of the second fan-out line FIP2, it can achieve a signal shielding effect, thereby avoiding the data signal transmitted by the second fan-out line FIP2 passing through the pixel circuits 10 of adjacent sub-pixels P(x) from generating signal crosstalk with the nodes in the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.
  • the lateral signal line in the first source-drain conductive layer 41 overlapping the second break DK2 may be at least one of the gate signal line GL1 , the enable signal line EM, the auxiliary first voltage signal line SIP or the auxiliary second voltage signal line DIP.
  • the first voltage signal line VSS, the second voltage signal line VDD, and the reference voltage signal line VRef1 of the display substrate 100 are all disposed in the second set source-drain conductive layer.
  • the first voltage signal line VSS, the second voltage signal line VDD and the reference voltage signal line VRef1 in the second set source-drain conductive layer can block the first break DK1 on the first fan-out line FIP1 in the first set source-drain conductive layer to prevent the data signal transmitted by the first fan-out line FIP1 from generating signal crosstalk between the first break DK1 position and the node in the pixel circuit 10, thereby ensuring the normal operation of the pixel circuit 10.

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Abstract

一种显示基板及显示装置。显示基板具有显示区和位于显示区一侧的绑定区。显示基板包括多个像素电路，多条数据线及设于显示区的第一扇出线和第二扇出线。多条数据线中的至少一条为设定数据线，第二扇出线相比设定数据线靠近绑定区的沿第二方向的中线。多个像素电路排列成多行多列，一列像素电路与一条数据线电连接。第一扇出线的一端与设定数据线电连接，另一端与第二扇出线电连接。显示基板包括多个像素，其中至少一个为设定像素。每个像素包括至少三个子像素，每个子像素包括一个像素电路。第二扇出线从与其对应的设定像素中相邻两个子像素的像素电路之间穿过，或从与其对应的设定像素中位于外侧的像素电路的外侧穿过，并延伸至绑定区。

Description

显示基板及显示装置
本申请要求于2023年06月30日提交的、申请号为202310805085.X的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及显示装置。
背景技术
有机发光二级管(Organic Light-Emitting Diode，简称OLED)显示装置凭借其自发光、对比度高、视角广、反应速度快、可用于挠曲性面板、使用温度范围广、构造及制程较简单等优异性能，逐渐成为显示领域的主流产品之一。OLED显示基板可广泛应用于智能手机、平板电脑、电视和可穿戴设备(比如手表)等终端产品中。其中，高像素密度(Pixels Per Inch，简称PPI)和窄边框化是OLED显示装置当前的一个重要发展方向。
发明内容
一方面，提供一种显示基板。所述显示基板具有显示区和绑定区，绑定区位于显示区的沿第二方向的一侧。显示基板包括：多个像素电路，多条数据线及设于显示区的第一扇出线和第二扇出线。多条数据线中的至少一条为设定数据线，第二扇出线相比设定数据线靠近绑定区的沿第二方向的中线。
多个像素电路排列成多行多列，一行像素电路沿第一方向排列，一列像素电路沿第二方向排列，第一方向和第二方向相交叉。数据线沿第二方向延伸，一列像素电路与一条数据线电连接。第一扇出线沿第一方向延伸，第二扇出线沿第二方向延伸。第一扇出线的一端与设定数据线电连接，另一端与第二扇出线电连接。
其中，显示基板包括多个像素，每个像素包括至少三个子像素，每个子像素包括一个像素电路；多个像素中的至少一个为设定像素，一个设定像素对应设置有至少一条第二扇出线，第二扇出线从对应的设定像素中相邻两个子像素的像素电路之间穿过，或从对应的设定像素中位于外侧的像素电路的外侧穿过，并延伸至绑定区。
在一些实施例中，显示基板还包括：沿第二方向延伸的第一电压信号线。一个设定像素对应设置有至少一条第一电压信号线，第一电压信号线从对应的设定像素中的相邻两个子像素的像素电路之间穿过，或从对应的设定像素中位于外侧的像素电路的外侧穿过。
在一些实施例中，设定像素对应的至少一条第二扇出线和至少一条第一电压信号线中，一条第二扇出线从一对相邻的子像素的像素电路之间穿过，一条第一电压信号线从另外一对相邻的子像素的像素电路之间穿过。
在一些实施例中，一个像素包括三个子像素。设定像素对应设置有一条第二扇出线和一条第一电压信号线，第二扇出线从三个子像素中的一对相邻的子像素的像素电路之间穿过， 第一电压信号线从三个子像素中另外一对相邻的子像素的像素电路之间穿过。
在一些实施例中，设定像素对应的第二扇出线和第一电压信号线中，一条第一电压信号线和一条第二扇出线从同一对相邻的子像素的像素电路之间穿过。
在一些实施例中，一个像素包括三个子像素。设定像素对应设置有一条第二扇出线和一条第一电压信号线，第二扇出线和第一电压信号线从三个子像素中的同一对相邻的子像素的像素电路之间穿过。
在一些实施例中，第二扇出线设有第二断口，第二断口将第二扇出线分成有效部分和冗余部分。第二扇出线的有效部分的一端与第一扇出线电连接，另一端延伸至绑定区。显示基板还包括：第一连接部，第一电压信号线和第二扇出线的冗余部分通过第一连接部电连接。
在一些实施例中，从同一对相邻的子像素的像素电路之间穿过的第一电压信号线和第二扇出线相邻设置，第一电压信号线、第二扇出线和第一连接部同层设置且一体成型。
在一些实施例中，第一扇出线设有第一断口，第一断口将第一扇出线分成有效部分和冗余部分。第一扇出线的有效部分的一端与设定数据线电连接，另一端与第二扇出线的有效部分电连接。显示基板还包括：第二连接部，第二连接部的一端与第一扇出线的冗余部分电连接；沿显示基板的厚度方向，第二连接部与第二扇出线的冗余部分之间设有过孔，第二连接部的另一端通过过孔与第二扇出线的冗余部分电连接。
在一些实施例中，第二连接部和第一扇出线的冗余部分同层设置且一体成型。
在一些实施例中，显示基板，还包括：沿第二方向延伸的多条参考电压信号线，一列像素电路与一条参考电压信号线电连接。相邻两列像素电路中，一列像素电路所连接的参考电压信号线，和另一列像素电路所连接的数据线相靠近设置。其中，第二扇出线设于相靠近设置的参考电压信号线和数据线之间。
在一些实施例中，显示基板的第一电压信号线设于相靠近设置的参考电压信号线和数据线之间。
在一些实施例中，显示基板还包括：衬底，设于衬底上的半导体层，及设于半导体层远离衬底一侧的多条辅助参考电压信号线。辅助参考电压信号线沿第一方向延伸，且与参考电压信号线电连接。其中，第一扇出线设于辅助参考电压信号线远离衬底的一侧；在向衬底的正投影中，第一扇出线与辅助参考电压信号线交叠，且与半导体层的部分交叠。
在一些实施例中，显示基板还包括：沿第二方向延伸的多条第二电压信号线，一列像素电路与一条第二电压信号线电连接。其中，多条第二电压信号线所在的膜层位于第一扇出线所在的膜层远离衬底的一侧，在向衬底的正投影中，第二电压信号线覆盖第一扇出线的第一断口。
在一些实施例中，显示基板还包括：多层源漏导电层。多层源漏导电层中一对相邻的源漏导电层分别为第一设定源漏导电层和第二设定源漏导电层，第一设定源漏导电层相比第二 设定源漏导电层靠近衬底。其中，第一扇出线设于第一设定源漏导电层，数据线和第二扇出线设于第二设定源漏导电层。
在一些实施例中，显示基板还包括：栅极信号线、使能信号线、辅助第一电压信号线和辅助第二电压信号线，均沿第一方向延伸。像素电路与栅极信号线和使能信号线电连接；辅助第一电压信号线与第一电压信号线电连接，辅助第二电压信号线与第二电压信号线电连接。
第一设定源漏导电层中设有栅极信号线、使能信号线、辅助第一电压信号线和辅助第二电压信号线中的至少一者。在向衬底的正投影中，栅极信号线、使能信号线、辅助第一电压信号线和辅助第二电压信号线中的至少一者覆盖第二扇出线的第二断口。
在一些实施例中，显示基板的第一电压信号线、第二电压信号线和参考电压信号线均设于第二设定源漏导电层。
在一些实施例中，显示基板还包括：第一栅极层和第二栅极层。显示基板的半导体层、第一栅极层和第二栅极层沿远离衬底的方向依次设置，且位于衬底和多层源漏导电层之间。显示基板的辅助参考电压信号线设于第二栅极层。
在一些实施例中，多层源漏导电层包括第一源漏导电层和第二源漏导电层，第一源漏导电层为第一设定源漏导电层，第二源漏导电层为第二设定源漏导电层。
在一些实施例中，多层源漏导电层包括第一源漏导电层、第二源漏导电层和第三源漏导电层，第一源漏导电层为第一设定源漏导电层，第二源漏导电层为第二设定源漏导电层。
在一些实施例中，多层源漏导电层包括第一源漏导电层、第二源漏导电层和第三源漏导电层，第二源漏导电层为第一设定源漏导电层，第三源漏导电层为第二设定源漏导电层。
在一些实施例中，相比多条数据线中的其他数据线，设定数据线更远离绑定区的沿第二方向的中线。设定数据线整体位于显示区内，其他数据线的端部延伸至绑定区。
另一方面，提供一种显示装置。所述显示装置包括：如上述任一实施例所述的显示基板，和电路板。电路板与显示基板电连接。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示装置的一种结构图；
图2为根据一些实施例的显示装置的另一种结构图；
图3为根据一些实施例的像素电路的结构图；
图4为根据另一些实施例的像素电路的结构图；
图5为根据一些实施例的显示基板的显示区AA内的局部放大结构图；
图6为根据图5中的区域D的放大结构图；
图7为根据图5中的区域F的放大结构图；
图8为根据一些实施例的显示基板的第一源漏导电层至第二源漏导电层的结构图；
图9为根据一些实施例的显示基板的第一源漏导电层根据图8中的区域E的放大结构图；
图10为根据一些实施例的显示基板的第二源漏导电层根据图8中的区域E的放大结构图；
图11为根据一些实施例的像素电路的等效电路图；
图12为根据一些实施例的显示基板的截面结构图；
图13为根据一些实施例的显示基板的半导体层的结构图；
图14为根据一些实施例的显示基板自半导体层至第二栅极层的结构图；
图15为根据一些实施例的显示基板自半导体层至第一源漏导电层的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。术语“耦接”例如表明两个或两个以上部件有直接物理接触或电接触。术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此 间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
如本文中所使用，根据上下文，术语“如果”任选地被解释为意思是“当……时”或“在……时”或“响应于确定”或“响应于检测到”。类似地，根据上下文，短语“如果确定……”或“如果检测到[所陈述的条件或事件]”任选地被解释为是指“在确定……时”或“响应于确定……”或“在检测到[所陈述的条件或事件]时”或“响应于检测到[所陈述的条件或事件]”。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层的厚度和区域的面积。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
在本公开的实施例中，图1和图2为显示装置1000的平面结构图，为了便于清晰地描述显示基板100与电路板200的连接方式，图2中将电路板200显示于显示基板100的显示区 AA同侧，需要说明的是，最终形成的显示基板100中，电路板200被弯折至另一侧。
为了便于清晰地描述第二扇出线FIP2和第一电压信号线VSS与像素电路10之间的相对位置关系，图3和图4中仅示出了显示基板100的部分像素电路10的结构图。实际的显示基板100中包括的像素电路10的数量不限于图中所示，同时，显示基板100所包括的膜层结构包括但不限于图中所示出的膜层结构。
为了便于清晰地描述数据信号在设定数据线DL1、第一扇出线FIP1和第二扇出线FIP2之间的传输路径，图5中示出了显示区AA内的局部放大图，图5中纵向的箭头所指的方向为绑定区BB内通过第二扇出线FIP2传输的数据信号的传输路径，图5中横向的箭头所指的方向为第二扇出线FIP2向第一扇出线FIP1传输的数据信号的传输路径，图5中标识出了三条设定数据线DL1的数据信号的传输路径。图6为图5中的区域D的放大结构图，图7为图5中的区域F的放大结构图。
为了便于清晰地描述第一扇出线FIP1的冗余部分FIP12，及第二扇出线FIP2的冗余部分FIP22与第一电压信号线VSS的连接方式，图8中仅示出了第一源漏导电层至第二源漏导电层的结构图。图9为第一源漏导电层根据图8中的区域E的放大结构图，图10为第二源漏导电层根据图8中的区域E的放大结构图。
图11为根据一些实施例的像素电路的等效电路图。图12为根据一些实施例的显示基板的截面结构图。
图13为根据一些实施例的显示基板的半导体层的平面结构图。图14为根据一些实施例的显示基板自半导体层至第二栅极层的结构图。图15为根据一些实施例的显示基板自半导体层至第一源漏导电层的结构图。
需要说明的是，为了便于清晰地描述各膜层结构的图案化设计，及各膜层之间的对应关系，图3至图10，及图13至图15中仅示出了显示基板的各膜层结构中对应部分子像素的部分区域的放大结构示意图，显示基板100的实际膜层结构中还可以包括其他膜层结构，且每层膜层结构的图案化设计包括但不限于图中所示，也还可以包括其他设计。
为了便于清晰地描述各功能膜层之间的连接方式，图3、图4、图6至图8、图14和图15中示出的绝缘介质层ILD和第一平坦化层61，为绝缘介质层ILD和第一平坦化层61上的过孔，实际膜层结构中绝缘介质层ILD和第一平坦化层61为整个覆盖显示基板100的膜层，且绝缘介质层ILD和第一平坦化层61上在图中示出的位置设置过孔，以使第二栅极层32和第一源漏导电层41，及第一源漏导电层41和第二源漏导电层42之间需要电连接的部分可以通过过孔对应相连。
如图1所示，本公开的一些实施例提供了一种显示装置1000。显示装置1000可以是显示不论运动的(例如，视频)还是固定的(例如，静止图像)，且不论文字还是图像的任何装置。更明确地说，预期所述实施例可实施在多种电子装置中或与多种电子装置关联，所述多 种电子装置包括但不限于电视、移动电话、可穿戴设备、PDA(Personal Digital Assistant，个人数字助理)、AR(Augmented Reality，增强现实)设备、VR(Virtual Reality，虚拟现实)设备、手持式或便携式计算机、GPS接收器/导航器、相机、MP4视频播放器、摄像机、游戏控制台、时钟、计算器、电视监视器、平板显示器、计算机监视器、车载显示器(例如，里程表显示器等)、导航仪、座舱控制器和/或显示器、相机视图的显示器(例如，车辆中后视相机的显示器)、电子相片、电子广告牌或指示牌、投影仪、建筑结构、包装和美学结构(例如，对于一件珠宝的图像的显示器)等。例如，如图1所示，显示装置1000可以为手机。
从显示装置1000的发光类型上看，上述显示装置1000可以是OLED(Organic Light-Emitting Diode，有机发光二极管，或Organic Electroluminescence Display，有机发光半导体)显示装置、QLED(Quantum Dot Light Emitting Diodes，量子点电致发光二极管)显示装置MLED(Mini Light Emitting Diodes，或Micro Light Emitting Diodes，微型发光二极管)显示装置等。从显示装置1000的形态上看，上述显示装置1000可以是平面显示装置、曲面显示装置或可折叠显示装置等。从显示装1000置的形状上看，上述显示装置1000可以是矩形或圆形等。对此不做限制，可以根据实际需要进行适应性设计。
下面以显示装置为矩形的、且为平面的有机发光二极管显示装置为例，对本公开的一些实施例进行示意性说明，但是本公开的实施方式包括但不限于此，也可以考虑任何其它显示装置，只要应用相同的技术思想即可。
在一些实施例中，如图2所示，显示装置1000包括显示基板100和电路板200。电路板200与显示基板100电连接。
示例性地，电路板200被配置为向显示基板100传输驱动信号，驱动显示基板100实现图像显示。
示例性地，电路板200可以包括TCON(Timing Controller，时序控制器)，电源管理芯片DC/DC和可调电阻分压电路(生成Vcom)等驱动电路。电路板200还可以包括其他电路结构，此处不再一一列举。
在一些实施例中，显示装置1000还可以包括屏下摄像头以及屏下指纹识别传感器等，使得显示装置1000能够实现拍照、录像、指纹识别或人脸识别等多种不同功能。对此不做限制，可以根据实际需要进行适应性设计。
在一些实施例中，如图2所示，显示基板100具有显示区AA和至少位于显示区AA沿第二方向Y的一侧的周边区AN。显示基板100包括设有显示区AA内的多个像素P，每个像素P包括至少三个子像素P(x)。
示例性地，多个像素P排列成多行多列。
示例性地，如图2所示，显示区AA为显示基板100上用于显示图像的区域，子像素P(x)为显示基板100上的最小发光单元，子像素P(x)用于显示图像。
在一些示例中，多个子像素P(x)发射相同颜色的光线，显示基板100还可以包括设置于多个子像素P(x)的出光侧的彩膜层，也就是显示基板100采用了COE(CF On Encapsulation，彩色滤光层在封装膜上)结构。
例如，多个子像素P(x)均发射白光、红光、绿光或蓝光等颜色光，在这种情况下，子像素P(x)发出的颜色光经过彩膜层后保持同色光射出，或转化为其他颜色光射出，从而在多个子像素P(x)发射同色光时，显示基板100可以实现多色出光。
在另一些示例中，多个子像素P(x)发射不同颜色的光线，比如，多个子像素P(x)包括发射红色光线的红光子像素、发射绿色光线的绿光子像素和发射蓝色光线的蓝光子像素，从而实现显示基板100的多色出光。
需要说明的是，每个像素P包括至少三个子像素P(x)，即每个像素P可以包括三个、四个或更多个子像素P(x)，且每个像素P包括的多个子像素P(x)可以是一行，一列或一组子像素P(x)，一组子像素P(x)可以是彼此相邻的多个子像素P(x)，相邻的多个子像素P(x)排成一行、排成一列、排成L型、排成矩形或排成菱形等。
同时，每个像素P包括的多个子像素P(x)的发光面积可以相同或不完全相同。以上仅作为示例性说明，不作为对本公开的限定，具体可以根据实际需要进行适应性设计。
以下以每个像素P包括的多个子像素P(x)沿第一方向X排成一行为例进行说明。
在一些实施例中，如图2所示，周边区AN环绕显示区AA设置，周边区AN内可以设置栅极驱动电路(例如Gate on Array，简称GOA)、控制信号线(例如时钟信号线、电源电压信号线等)及绑定驱动芯片(例如Source Driver IC，源极驱动芯片)等，周边区AN的功能包括但不限于此。
示例性地，如图2所示，周边区AN包括绑定区BB，绑定区BB位于显示区AA的沿第二方向Y上的一侧。绑定区BB与显示区AA的一侧边缘邻接，绑定区BB例如与显示区AA的下侧边缘邻接。显示基板100在绑定区BB内与外部驱动器相连。
例如，绑定区BB被配置将信号线(例如数据线DL、第一电压信号线VSS和参考电压信号线VRef1等)引出，并与驱动电路板(例如电路板200)或驱动芯片进行绑定。即，绑定区BB位于显示基板100的用于绑定驱动电路板或驱动芯片的一侧。
在一些实施例中，如图2所示，显示基板100包括：多个像素电路10和多个发光器件20。多个像素电路10排列成多行多列，一行像素电路10沿第一方向X排列，每行像素电路10包括沿第一方向X间隔排布的多个像素电路10；一列像素电路10沿第二方向Y排列，每列像素电路10包括沿第二方向Y间隔排布的多个像素电路10。也就是说，第一方向X为多个像素电路10排列的行方向，第二方向Y为多个像素电路10排列的列方向。其中，第一方向X和第二方向Y相交叉。
示例性地，第一方向X垂直于第二方向Y。
示例性地，每个像素电路10与一个发光器件20相连，像素电路10被配置为驱动与其相连的发光器件20发光。
示例性地，发光器件20包括但不限于OLED(Organic Light-Emitting Diode，有机发光二极管)、Mini LED(Mini Light-Emitting Diode，迷你发光二极管)、Micro LED(Micro Light-Emitting Diode，微型发光二极管)等。
在一些实施例中，如图2和图3所示，显示基板100还包括：多条数据线DL、第一扇出线FIP1和第二扇出线FIP2。数据线DL沿第二方向Y延伸，一列像素电路10与一条数据线DL电连接。多条数据线DL中的至少一条为设定数据线DL1，第二扇出线FIP2相比设定数据线DL1靠近绑定区BB的沿第二方向Y的中线。
第一扇出线FIP1和第二扇出线FIP2设于显示区AA，第一扇出线FIP1沿第一方向X延伸，第二扇出线FIP2沿第二方向Y延伸。第一扇出线FIP1的一端与设定数据线DL1电连接，另一端与第二扇出线FIP2电连接。
其中，如图2所示，多个像素P中的至少一个为设定像素PP，一个设定像素PP对应设置有至少一条第二扇出线FIP2。第二扇出线FIP2从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过，或从对应的设定像素PP中位于外侧的像素电路10的外侧穿过，并延伸至绑定区BB。
在一些实施例中，如图2所示，相比多条数据线DL中的其他数据线DL，设定数据线DL1更远离绑定区BB的沿第二方向Y的中线。设定数据线DL1整体位于显示区AA内，其他数据线DL的端部延伸至绑定区BB。
示例性地，如图2所示，数据线DL可以包括第一数据线DL1和第二数据线DL2，其中，第一数据线DL1为设定数据线DL1。设定数据线DL1位于显示区AA内，不延伸至绑定区BB；第二扇出线FIP2和第二数据线DL2延伸至绑定区BB。设定数据线DL1、第一扇出线FIP1和第二扇出线FIP2依次相连，每条第一扇出线FIP1分别与一条设定数据线DL1和一条第二扇出线FIP2电连接。
换言之，第二数据线DL2直接延伸至绑定区BB，设定数据线DL1为显示基板100中需要依次通过第一扇出线FIP1和第二扇出线FIP2引出至绑定区BB的数据线DL。这种设置方式可以称为FIP(Fanout In Pixel，像素内扇出)。
如图2所示，显示基板100用于绑定驱动器的一侧的边框宽度，例如图2中示出的周边区AN位于显示区AA的下方的部分的宽度为d1，绑定区BB沿第二方向Y上的尺寸为d2，d1≥d2。采用这样的设计，能够降低周边区AN设置绑定区BB的一侧的尺寸d1，有利于实现显示装置1000的窄边框化。
通过在像素P内或相邻的像素P之间插入第二扇出线FIP2，将设定数据线DL1通过第一扇出线FIP1和第二扇出线FIP2引出至绑定区BB，增加了显示区AA内用于传输数据信号 的信号线的数量，增大了用于传输数据信号的信号线的密度，从而使得传输数据信号的信号线整体的电阻减小，利于实现数据信号的传输稳定性和可靠性。同时，将新增的第二扇出线FIP2分别插入相邻的像素电路10之间，保证了显示基板100的膜层结构的均一性，进而保证显示基板100的显示效果。
示例性地，如图2所示，设定像素PP例如包括沿第一方向X依次排布的三个子像素P(x)，例如，从图2中的左侧指向右侧依次为第一子像素PP(1)、第二子像素PP(2)和第三子像素PP(3)。
在一些示例中，如图2所示，显示基板100中的一个设定像素PP对应设置有一条第二扇出线FIP2，第二扇出线FIP2从对应的设定像素PP中位于外侧的像素电路10的外侧穿过，并延伸至绑定区BB。
例如，第二扇出线FIP2从第一子像素PP(1)的像素电路10远离第二子像素PP(2)的像素电路10的一侧穿过，并延伸至绑定区BB。
又如，第二扇出线FIP2从第三子像素PP(3)的像素电路10远离第二子像素PP(2)的像素电路10的一侧穿过，并延伸至绑定区BB。
在另一些示例中，如图3所示，显示基板100中的一个设定像素PP对应设置有一条第二扇出线FIP2，第二扇出线FIP2从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过，并延伸至绑定区BB。
例如，第二扇出线FIP2从第一子像素PP(1)和第二子像素PP(2)的像素电路10之间穿过，并延伸至绑定区BB；或，如图3所示，第二扇出线FIP2从第二子像素PP(2)和第三子像素PP(3)的像素电路10之间穿过，并延伸至绑定区BB。
在又一些示例中，显示基板100中的一个设定像素PP对应设置有两条第二扇出线FIP2，第二扇出线FIP2从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过，并延伸至绑定区BB。
例如，一条第二扇出线FIP2从第一子像素PP(1)和第二子像素PP(2)的像素电路10之间穿过，并延伸至绑定区BB；另一条第二扇出线FIP2从第二子像素PP(2)和第三子像素PP(3)的像素电路10之间穿过，并延伸至绑定区BB。
在再一些示例中，显示基板100中的一个设定像素PP对应设置有三条设定数据线DL1第二扇出线FIP2，第二扇出线FIP2从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过，并延伸至绑定区BB。
例如，一条第二扇出线FIP2从第一子像素PP(1)和第二子像素PP(2)的像素电路10之间穿过，并延伸至绑定区BB；另一条第二扇出线FIP2从第二子像素PP(2)和第三子像素PP(3)的像素电路10之间穿过，并延伸至绑定区BB；又一条第二扇出线FIP2从对应的设定像素PP中位于外侧的像素电路10的外侧穿过，并延伸至绑定区BB。
在又一些示例中，显示基板100中的一个设定像素PP对应设置有四条第二扇出线FIP2，其中，沿第一方向X，第一条第二扇出线FIP2从第一子像素PP(1)的像素电路10远离第二子像素PP(2)的一侧穿过，并延伸至绑定区BB；第二条第二扇出线FIP2从第一子像素PP(1)和第二子像素PP(2)的像素电路10之间穿过，并延伸至绑定区BB；第三条第二扇出线FIP2从第二子像素PP(2)和第三子像素PP(3)的像素电路10之间穿过，并延伸至绑定区BB；第四条第二扇出线FIP2从第三子像素PP(3)的像素电路10远离第二子像素PP(2)的一侧穿过，并延伸至绑定区BB。
可以理解的是，在设定像素PP包括三个子像素P(x)，且设定像素PP沿第一方向X的两侧均与另外的像素P相邻的情况下，相邻的两个像素P(其中一个为设定像素PP)之间可以包括一条或两条第二扇出线FIP2。在相邻的两个像素P均为设定像素PP，且与一个设定像素PP对应设置的第二扇出线FIP2的数量，小于或者等于该设定像素PP包括的子像素P(x)的数量的情况下，其中，第一个设定像素PP对应的一条第二扇出线FIP2位于这两个设定像素PP之间时，第二个设定像素PP对应的第二扇出线FIP2中的任一条可以是位于这两个设定像素PP之间，或位于第二个设定像素PP内的子像素P(x)之间，或位于第二个设定像素PP远离第一个设定像素PP的一侧。
通过设置第一扇出线FIP和第二扇出线FIP2，将设定像素PP包括的多个子像素P(x)中的至少一部分所对应的数据线DL由从周边区AN引出至绑定区BB，改为通过第二扇出线FIP2从显示区AA内引出至绑定区BB，从而减少了数据线DL在周边区AN内的布线面积，降低了周边区AN设置绑定区BB的一侧沿第二方向Y上的尺寸d1，利用实现显示装置1000的边框窄化。
需要说明的是，设定像素PP中位于外侧的像素电路10的外侧是指，设定像素PP和与设定像素PP相邻的另一个像素P之间，且另一个像素P也可以是设定像素PP。
以上仅为示例性说明，不作为对本公开的限定，每个设定像素PP还可以是包括四个、五个或更多个子像素P(x)。在一些示例中，每个设定像素PP对应设置的第二扇出线FIP2的数量小于或者等于其所包括的子像素P(x)的数量，第二扇出线FIP2从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过，或从对应的设定像素PP中位于外侧的像素电路10的外侧穿过，并延伸至绑定区BB。在另一些示例中，每个设定像素PP对应设置的第二扇出线FIP2的数量大于其所包括的子像素P(x)的数量，第二扇出线FIP2中的一部分从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过，另一部分从对应的设定像素PP中位于外侧的像素电路10的外侧穿过，并延伸至绑定区BB。
示例性地，如图2所示，数据线DL需要延伸至绑定区BB，并在绑定区BB与驱动器(例如驱动电路板或者驱动芯片等)绑定连接，驱动器向数据线DL传输数据信号，使像素电路10能够驱动发光器件20发光。
如图2所示，沿第一方向X，绑定区BB的尺寸例如小于显示区AA的尺寸，且沿第二方向Y，绑定区BB可以是与显示区AA的中部区域相对设置。位于显示区AA沿第一方向X的两侧边缘的数据线DL为设定数据线DL1(第一数据线DL1)，位于显示区AA沿第一方向X的中部区域的数据线DL为第二数据线DL2。
在一些实施例中，显示基板不包括第一扇出线FIP1和第二扇出线FIP2，设定数据线DL1靠近绑定区BB的一端延伸向周边区AN，并向绑定区BB收敛。参见图2，显示基板100中，沿第一方向X，绑定区BB的尺寸小于显示区AA的尺寸，这样，设定数据线DL1位于周边区AN内且向绑定区BB内延伸的部分，会占据周边区AN内的空间，使得周边区AN设置绑定区BB的一侧的部分沿第二方向Y的尺寸较大，显示基板100的用于绑定驱动器的一侧的边框宽度较大。
在另一些实施例中，如图2所示，沿第二方向Y，第二数据线DL2与绑定区BB相对设置，设定数据线DL1位于第二数据线DL2沿第一方向X的两侧。这样，沿第一方向X，位于绑定区BB两侧的第一数据线DL1通过第一扇出线FIP1和第二扇出线FIP2引出至绑定区BB，与绑定区BB相对设置的第二数据线DL2直接引出至绑定区BB。
采用如图2所示的设计，多条数据线DL(设定数据线DL1和第二数据线DL2)均从显示区AA内引出至绑定区BB，数据线DL不会占据周边区AN内的空间，有利于缩小周边区AN设置绑定区BB的一侧的部分沿第二方向Y的尺寸d2，进而实现显示装置1000的窄边框化。
需要说明的是，显示基板100中，绑定区BB的数量可以为多个，比如在大尺寸显示装置中(比如电视或电脑等)，显示基板100可以包括多个绑定区BB，沿第二方向Y与绑定区BB相对设置的数据线DL可以认为是第二数据线DL2，其余数据线DL可以认为是第一数据线DL1(设定数据线DL1)。当然，第一数据线DL1和第二数据线DL2的区分方式不限于此，还可以根据需要，在不同区域设置第一数据线DL1和第二数据线DL2。
在一些实施例中，如图3所示，显示基板100还包括：第一电压信号线VSS，沿第二方向Y延伸。一个设定像素PP对应设置有至少一条第一电压信号线VSS，第一电压信号线VSS从对应的设定像素PP中的相邻两个子像素P(x)的像素电路10之间穿过，或从对应的设定像素PP中位于外侧的像素电路10的外侧穿过。
以设定像素PP包括沿第一方向X依次排列的第一子像素PP(1)、第二子像素PP(2)和第三子像素PP(3)为例进行说明。
在一些示例中，显示基板100中的一个设定像素PP对应设置有一条第一电压信号线VSS，第一电压信号线VSS从对应的设定像素PP中位于外侧的像素电路10的外侧穿过。
例如，第一电压信号线VSS从第一子像素PP(1)的像素电路10远离第二子像素PP(2)的像素电路10的一侧穿过。
又如，第一电压信号线VSS从第三子像素PP(3)的像素电路10远离第二子像素PP(2)的像素电路10的一侧穿过。
在另一些示例中，如图3所示，显示基板100中的一个设定像素PP对应设置有一条第一电压信号线VSS，第一电压信号线VSS从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过。
例如，如图3所示，第一电压信号线VSS从第一子像素PP(1)和第二子像素PP(2)的像素电路10之间穿过；或，第一电压信号线VSS从第二子像素PP(2)和第三子像素PP(3)的像素电路10之间穿过。
在又一些示例中，显示基板100中的一个设定像素PP对应设置有两条第一电压信号线VSS，第一电压信号线VSS从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过。
例如，一条第一电压信号线VSS从第一子像素PP(1)和第二子像素PP(2)的像素电路10之间穿过；另一条第一电压信号线VSS从第二子像素PP(2)和第三子像素PP(3)的像素电路10之间穿过。
在再一些示例中，显示基板100中的一个设定像素PP对应设置有三条第一电压信号线VSS，第一电压信号线VSS从对应的设定像素PP中相邻两个子像素P(x)的像素电路10之间穿过。
例如，一条第一电压信号线VSS从第一子像素PP(1)和第二子像素PP(2)的像素电路10之间穿过；另一条第一电压信号线VSS从第二子像素PP(2)和第三子像素PP(3)的像素电路10之间穿过；又一条第一电压信号线VSS从对应的设定像素PP中位于外侧的像素电路10的外侧穿过。
在又一些示例中，显示基板100中的一个设定像素PP对应设置有四条第一电压信号线VSS，其中，沿第一方向X，第一条第一电压信号线VSS从第一子像素PP(1)的像素电路10远离第二子像素PP(2)的一侧穿过；第二条第一电压信号线VSS从第一子像素PP(1)和第二子像素PP(2)的像素电路10之间穿过；第三条第一电压信号线VSS从第二子像素PP(2)和第三子像素PP(3)的像素电路10之间穿过；第四条第一电压信号线VSS从第三子像素PP(3)的像素电路10远离第二子像素PP(2)的一侧穿过。
可以理解的是，在设定像素PP包括三个子像素P(x)，且设定像素PP沿第一方向X的两侧均与另外的像素P相邻的情况下，相邻的两个像素P(其中一个为设定像素PP)之间可以包括一条或两条第一电压信号线VSS。在相邻的两个像素P均为设定像素PP，且与设定像素PP对应的第一电压信号线VSS的数量，小于或者等于设定像素PP包括的子像素P(x)的数量的情况下，其中，第一个设定像素PP对应的一条第一电压信号线VSS位于这两个设定像素PP之间时，第二个设定像素PP对应的第一电压信号线VSS中的任一条可以是位于 这两个设定像素PP之间，或位于第二个设定像素PP内的子像素P(x)之间，或位于第二个设定像素PP远离第一个设定像素PP的一侧。
通过在设定像素PP内，或在设定像素PP和与其相邻的像素P(也可以是另一个设定像素PP)之间插入第一电压信号线VSS，增加了显示区AA内的第一电压信号线VSS的布线数量，增大了显示区AA内第一电压信号线VSS的密度，从而使得第一电压信号线VSS整体的电阻减小，利于减小第一电压信号线VSS的压降，保证第一电压信号的传输稳定性和可靠性。
在一些实施例中，如图3所示，设定像素PP对应的至少一条第二扇出线FIP2和至少一条第一电压信号线VSS中，一条第二扇出线FIP2从一对相邻的子像素P(x)的像素电路10之间穿过，一条第一电压信号线VSS从另外一对相邻的子像素P(x)的像素电路10之间穿过。
通过在设定像素PP内的相邻的子像素P(x)的像素电路10之间插入第二扇出线FIP2和第一电压信号线VSS，增加了显示区AA内的用于传输第一电压信号和传输数据信号的信号线的密度，从而使得第一电压信号线VSS和数据线DL整体的电阻减小，利于减小第一电压信号线VSS和数据线DL的压降，保证第一电压信号和数据信号的传输稳定性和可靠性。
示例性地，如图3所示，每个像素P包括三个子像素P(x)。设定像素PP对应设置有一条第二扇出线FIP2和一条第一电压信号线VSS，第二扇出线FIP2从三个子像素P(x)中的一对相邻的子像素P(x)的像素电路10之间穿过，第一电压信号线VSS从三个子像素P(x)中另外一对相邻的子像素P(x)的像素电路10之间穿过。
例如，如图3所示，设定像素PP包括沿第一方向X依次排布的第一子像素P(1)、第二子像素P(2)和第三子像素P(3)。其中，第一电压信号线VSS从第一子像素P(1)和第二子像素P(2)的像素电路10之间穿过，第二扇出线FIP2从第二子像素P(2)和第三子像素P(3)的像素电路10之间穿过，并延伸至绑定区BB。
需要说明的是，在每个像素P包括三个子像素P(x)的情况下，也可以是第二扇出线FIP2从第一子像素P(1)和第二子像素P(2)的像素电路10之间穿过，并延伸至绑定区BB；第一电压信号线VSS从第二子像素P(2)和第三子像素P(3)的像素电路10之间穿过。
在一些实施例中，如图4所示，设定像素PP对应的第二扇出线FIP2和第一电压信号线VSS中，一条第一电压信号线VSS和一条第二扇出线FIP2从同一对相邻的子像素P(x)的像素电路10之间穿过。
示例性地，像素电路10例如包括多个晶体管TFT(Thin Film Transistor，薄膜晶体管)、至少一个电容器和至少一个连接节点。其中，连接节点中的部分节点(例如图11中示出的第五节点N5)对像素电路10的工作起到关键作用。像素电路10的具体结构参见后文，在此不多做介绍。
通过将与设定像素PP对应的一条第一电压信号线VSS和一条第二扇出线FIP2设置为从同一对相邻的子像素P(x)的像素电路10之间穿过，增加了显示区AA内用于传输第一电压信号的信号线的布线密度，减小显示区AA内用于传输第一电压信号的信号线的电阻，减小第一电压信号的压降。
同时，第一电压信号线VSS作为恒压信号线，能够起到信号屏蔽效果，避免从相邻的子像素P(x)的像素电路10之间穿过的第二扇出线FIP2传输的数据信号，与像素电路10内的节点之间产生信号串扰，保证像素电路10的正常工作。
示例性地，如图4所示，像素P包括三个子像素P(x)。设定像素PP对应设置有一条第二扇出线FIP2和一条第一电压信号线VSS，第二扇出线FIP2和第一电压信号线VSS从三个子像素P(x)中的同一对相邻的子像素P(x)的像素电路10之间穿过。
例如，如图4所示，设定像素PP包括沿第一方向X依次排布的第一子像素P(1)、第二子像素P(2)和第三子像素P(3)。其中，第一电压信号线VSS和第二扇出线FIP2均从第一子像素P(1)和第二子像素P(2)的像素电路10之间穿过。
需要说明的是，在每个像素P包括三个子像素P(x)的情况下，第一电压信号线VSS和第二扇出线FIP2也可以是均从第二子像素P(2)和第三子像素P(3)的像素电路10之间穿过。
在一些实施例中，如图6所示，第二扇出线FIP2设有第二断口DK2，第二断口DK2将第二扇出线FIP2分成有效部分FIP21和冗余部分FIP22。第二扇出线FIP2的有效部分FIP21的一端与第一扇出线FIP1电连接，另一端延伸至绑定区BB。
示例性地，如图6所示，第二断口DK2将第二扇出线FIP2分割成相互电绝缘的有效部分FIP21和冗余部分FIP22，参见图2和图5，第二扇出线FIP2的有效部分FIP21的一端(例如图2中示出的下端)延伸至绑定区BB，另一端与第一扇出线FIP1相连。第二扇出线FIP2的有效部分FIP21远离绑定区BB的一侧与第二扇出线FIP2的冗余部分FIP22电绝缘。即，第一扇出线FIP1与第二扇出线FIP2的有效部分FIP21电连接，且通过第二扇出线FIP2的有效部分FIP21延伸至绑定区BB。
通过第二断口DK2将第二扇出线FIP2分割形成相互电绝缘的有效部分FIP21和冗余部分FIP22，数据信号自绑定区BB内绑定的驱动器发出，依次经第二扇出线FIP2的有效部分FIP21、第一扇出线FIP1和设定数据线DL1传输至对应的子像素P(x)，这样，数据信号的传输路径不经过第二扇出线FIP2的冗余部分FIP22，有利于缩短数据信号在第二扇出线FIP2上的传输路径，进而降低数据信号在第二扇出线FIP2上传输过程中的压降，防止压降导致的信号失真，利于保证数据信号传输的准确性。
需要说明的是，第二扇出线FIP2的冗余部分FIP22可以被配置为不传输信号，或，被配置为传输出数据信号之外的其他信号。
在一些实施例中，如图8和图10所示，显示基板100还包括第一连接部LJ1，第一电压信号线VSS和第二扇出线FIP2的冗余部分FIP22通过第一连接部LJ1电连接。第二扇出线FIP2的冗余部分FIP22被配置为传输第一电压信号。
通过第一连接部LJ1将第二扇出线FIP2的冗余部分FIP22与第一电压信号线VSS相连，这样，增加了显示区AA内的第一电压信号线VSS的布线面积，使得第一电压信号线VSS在显示区AA内的密度增大，有利于降低第一电压信号线VSS的电阻，进而减小第一电压信号线VSS的压降。
在一些实施例中，如图4、图8和图10所示，从同一对相邻的子像素P(x)的像素电路10之间穿过的第一电压信号线VSS和第二扇出线FIP2相邻设置，第一电压信号线VSS、第二扇出线FIP2和第一连接部LJ1同层设置且一体成型。
示例性地，在显示基板100的制备过程中，例如先通过溅射工艺形成一层导电结构层，接着，例如采用刻蚀工艺对前述导电结构层进行图案化，从而形成相连的第一电压信号线VSS、第一连接部LJ1和第二扇出线FIP2。这样，在同一个制备步骤中同时形成了第一电压信号线VSS、第二扇出线FIP2和第一连接部LJ1，且第一电压信号线VSS、第一连接部LJ1和第二扇出线FIP2彼此相连的一体结构，无需设置其余结构使三者相连，在增加了第一连接部LJ1和第二扇出线FIP2的同时，无需增加显示基板100的制备工艺步骤，利于降低生产成本。
需要说明的是，第一电压信号线VSS、第一连接部LJ1和第二扇出线FIP2的制备工艺也可以采用其他方法，此处为示例性说明，不作为对本公开的限定。
在一些实施例中，如图6所示，第一扇出线FIP1设有第一断口DK1，第一断口DK1将第一扇出线FIP1分成有效部分FIP11和冗余部分FIP12。第一扇出线FIP1的有效部分11的一端与设定数据线DL1电连接，另一端与第二扇出线FIP2的有效部分FIP21电连接。
示例性地，如图6所示，第一断口DK1将第一扇出线FIP1分割成相互电绝缘的有效部分FIP11和冗余部分FIP12，参见图2和图5，第一扇出线FIP1的有效部分FIP11的一端(例如图2中示出的下端)延伸至绑定区BB，另一端与第二扇出线FIP2相连。第一扇出线FIP1的有效部分FIP21远离绑定区BB的一侧与第一扇出线FIP1的冗余部分FIP12电绝缘。即，第一扇出线FIP1的有效部分FIP11与第二扇出线FIP2的有效部分FIP21电连接，且通过第二扇出线FIP2的有效部分FIP21延伸至绑定区BB。
通过第一断口DK1将第一扇出线FIP1分割形成相互电绝缘的有效部分FIP11和冗余部分FIP12，数据信号自绑定区BB内绑定的驱动器发出，依次经第二扇出线FIP2的有效部分FIP21、第一扇出线FIP1的有效部分FIP11和设定数据线DL1传输至对应的子像素P(x)，这样，数据信号的传输路径不经过第二扇出线FIP2的冗余部分FIP22和第一扇出线FIP1的冗余部分FIP12，有利于缩短数据信号在第一扇出线FIP1和第二扇出线FIP2上的传输路径，进而降低数据信号在第一扇出线FIP1进而第二扇出线FIP2上传输过程中的压降，防止压降 导致的信号失真，利于保证数据信号传输的准确性。
在一些实施例中，如图8和图9所示，显示基板100还包括：第二连接部LJ2。沿显示基板100的厚度方向，第二连接部LJ2与第二扇出线FIP2的冗余部分FIP22之间设有过孔K，第二连接部LJ2的一端与第一扇出线FIP1的冗余部分FIP12电连接，第二连接部LJ2的另一端通过过孔K与第二扇出线FIP2的冗余部分FIP22电连接。
示例性地，第一扇出线FIP1和第二扇出线FIP2位于不同的膜层结构中，即沿显示基板100的厚度方向，第一扇出线FIP1和第二扇出线FIP2所在的膜层结构与显示基板100之间的距离不同。
第一扇出线FIP1和第二扇出线FIP2之间可以还包括绝缘间隔层，例如平坦化层6，第一扇出线FIP1和第二扇出线FIP2之间电绝缘，通过在平坦化层6上对应第二扇出线FIP2的冗余部分FIP22与第二连接部LJ2相靠近的一端之间的部分设置过孔K，使第二连接部LJ2的一端通过过孔K与第二扇出线FIP2的冗余部分FIP22相连。这样，第一扇出线FIP1的冗余部分FIP12与第二扇出线FIP2的冗余部分FIP22通过第二连接部LJ2相连，增加了显示区AA内的第一电压信号线VSS的布线面积，使得第一电压信号线VSS在显示区AA内的密度增大，第一扇出线FIP1的冗余部分FIP12与第二扇出线FIP2的冗余部分FIP22并联设置，有利于降低第一电压信号线VSS的电阻，进而减小第一电压信号线VSS的压降。
在一些实施例中，如图9所示，第二连接部LJ2和第一扇出线FIP1的冗余部分FIP12同层设置且一体成型。
示例性地，在显示基板100的制备过程中，例如先通过溅射工艺形成一层导电结构层，接着，例如采用刻蚀工艺对前述导电结构层进行图案化，从而形成相连的第一扇出线FIP1的冗余部分FIP12和第二连接部LJ2。这样，在同一个制备步骤中同时形成了第一扇出线FIP1的冗余部分FIP12和第二连接部LJ2，且第二连接部LJ2和第一扇出线FIP1的冗余部分FIP12为彼此相连的一体结构，无需设置其余结构使二者相连，在增加了第一扇出线FIP1的冗余部分FIP12和第二连接部LJ2的同时，无需增加显示基板100的制备工艺步骤，利于降低生产成本。
需要说明的是，第一扇出线FIP1的冗余部分FIP12和第二连接部LJ2的制备工艺也可以采用其他方法，此处为示例性说明，不作为对本公开的限定。
在一些实施例中，如图3和图4所示，显示基板100还包括：多条参考电压信号线VRef1。参考电压信号线VRef1沿第二方向Y延伸，一列像素电路10与一条参考电压信号线VRef1电连接。相邻两列像素电路10中，一列像素电路10所连接的参考电压信号线VRef1，和另一列像素电路10所连接的数据线DL相靠近设置。其中，第二扇出线FIP2设于相靠近设置的参考电压信号线VRef1和数据线DL之间。
示例性地，如图3和图4所示，每列像素电路10分别与一条数据线DL和一条参考电压 信号线VRef1电连接，一列像素电路10沿第二方向Y延伸，与该列像素电路10对应相连的数据线DL和参考电压信号线VRef1位于该像素电路10沿第一方向X上的两侧。相邻的两列像素电路10中插入一条第二扇出线FIP2，将设定数据线DL1从显示区AA内引出至绑定区BB。
在一些实施例中，如图3和图4所示，显示基板100的第一电压信号线VSS设于相靠近设置的参考电压信号线VRef1和数据线DL之间。
示例性地，如图3和图4所示，与一列像素电路10对应相连的数据线DL和参考电压信号线VRef1位于该像素电路10沿第一方向X上的两侧。相邻的两列像素电路10中插入一条第一电压信号线VSS，增大了显示区AA内第一电压信号线VSS的密度，从而使得第一电压信号线VSS整体的电阻减小，利于减小第一电压信号线VSS的压降，保证第一电压信号的传输稳定性和可靠性。
在一些实施例中，如图11所示，像素电路10包括多个晶体管TFT和至少一个电容器。
示例性地，像素电路10可以为“3T1C”电路、“7T1C”电路、“8T1C”电路或“9T2C”等，其中，“T”是指TFT，“T”前面的数字是指TFT的数量；“C”是指电容器，“C”前面的数字是指电容器的数量。本公开的实施例中，以像素电路10为“9T2C”电路为例进行示意性说明，但是本公开的实施方式不限于此，并且也可以考虑任何其它像素电路10，只要应用相同的技术思想即可。
示例性地，如图11所示，为9T2C模式的像素电路10的等效电路图。在这种情况下，像素电路10可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、第一电容器C1和第二电容器C2，及与像素电路10电连接的信号线(例如数据信号线DL、第一使能信号线EM1、第二使能信号线EM2、初始化信号线Vinit、第一电压信号线VSS和第二电压信号线VDD等)。
例如，如图11所示，每个像素电路10对应连接有三条栅极信号线GL，分别为第一栅极信号线GL1、第二栅极信号线GL2和第三栅极信号线GL3。
第一晶体管T1的栅极与第三栅极信号线GL3电连接，第一晶体管T1的第一极与第一初始化信号线Vinit1，第一晶体管T1的第二极与第一节点N1电连接。
第二晶体管T2的栅极与第二栅极信号线GL2电连接，第二晶体管T2的第一极与第一节点N1电连接，第二晶体管T2的第二极与第三节点N3电连接。
第三晶体管T3的栅极与第一节点N1电连接，第三晶体管T3的第一极与第二节点N2电连接，第三晶体管T3的第二极与第三节点N3电连接。
第四晶体管T4的栅极与第一栅极信号线GL1电连接，第四晶体管T4的第一极与数据信号线DL电连接，第四晶体管T4的第二极与第五节点N5电连接。
第五晶体管T5的栅极与第一使能信号线EM1电连接，第五晶体管T5的第一极与第二电压信号线VDD电连接，第五晶体管T5的第二极与第二节点N2电连接。
第六晶体管T6的栅极与第二使能信号线EM2电连接，第六晶体管T6的第一极与第三节点N3电连接，第六晶体管T6的第二极与第四节点N4电连接。
第七晶体管T7的栅极与扫描信号线Scan电连接，第七晶体管T7的第一极与第二初始化信号线Vinit2电连接，第七晶体管T7的第二极与第四节点N4电连接。
第八晶体管T8的栅极与扫描信号线Scan电连接，第八晶体管T8的第一极与第二参考电压信号线VRef2电连接，第八晶体管T8的第二极与第二节点N2电连接。
第九晶体管T9的栅极与第二栅极信号线GL2电连接，第九晶体管T9的第一极与第一参考电压信号线VRef1电连接，第九晶体管T9的第二极与第五节点N5电连接。
第一电容器C1的第一极板C11与第五节点N5电连接，第一电容器C1的第二极板C12与第一节点N1电连接。
第二电容器C2的第一极板C21与第五节点N5电连接，第二电容器C2的第二极板C22与第二电压信号线VDD电连接。
其中，第五节点N5与第一电容器C1和第二电容器C2电连接，第五节点N5的电压变化会引起第一电容器C1和第二电容器C2的存储电压的变化。
在一些实施例中，如图12所示，显示基板100包括衬底1、半导体层2、多层栅极层3和、多层源漏导电层4。多层源漏导电层4可以统称为显示基板100中的功能膜层，各功能膜层中具有设定导电图案，相邻的功能膜层之间通过绝缘的膜层结构间隔。
示例性地，衬底1可以为刚性衬底，刚性衬底的材料包括但不限于玻璃。或者，衬底1可以为柔性衬底，柔性衬底的材料包括但不限于PI(Polyimide，聚酰亚胺)、PC(Polycarbonate，聚碳酸酯)或者PVC(Polyvinyl Chloride，聚氯乙烯)中的任一种。
示例性地，如图12和图13所示，半导体层2包括有源层图案。如图13所示，有源层图案包括各晶体管TFT的有源层21。
在一些示例中，薄膜晶体管TFT可以是低温多晶硅薄膜晶体管，即半导体层2采用低温多晶硅。
在另一些示例中，薄膜晶体管TFT也可以为氧化物薄膜晶体管，即半导体层2采用金属氧化物，例如，氧化铟镓锌或氧化铟镓锡等。
在一些实施例中，如图12所示，多层栅极层3包括自衬底1一侧依次设置的第一栅极层31和第二栅极层32。
示例性地，如图14所示，第一栅极层31包括第一栅导电图案，第一栅导电图案与有源层图案在衬底1上的正投影有交叠，第一栅导电图案与有源层图案交叠的部分作为各晶体管TFT的栅极。
在一些示例中，如图14所示，第一栅导电图案包括沿第一方向X延伸的扫描信号线Scan，扫描信号线Scan被配置为向晶体管TFT传输扫描信号。
在一些实施例中，如图12和图14所示，第二栅极层32包括第二栅导电图案，第二栅导电图案包括辅助参考电压信号线VRef11。
示例性地，如图14所示，辅助参考电压信号线VRef11沿第一方向X延伸，且与参考电压信号线VRef1相连。
示例性地，如图14所示，第二栅导电图案包括沿第一方向X延伸的多条信号线，例如辅助参考电压信号线VRef11、第二参考电压信号线VRef2、第一初始化信号线Vinit1、第二使能信号线EM2和修复信号线Repair。第一初始化信号线Vinit1被配置为向晶体管TFT传输初始化信号。第二使能信号线EM2被配置为向晶体管TFT传输发光控制信号。
在一些实施例中，如图12所示，显示基板100还包括：多层栅绝缘层5。多层栅绝缘层5包括：设于半导体层2和第一栅极层1之间的第一栅绝缘层51，和设于第一栅极层31和第二栅极层32之间的第二栅绝缘层52。
在一些实施例中，如图14所示，第一栅导电图案包括第一极板图案，第一极板图案包括各像素电路10的电容器(例如第一电容器C1和第二电容器C2)的第一极板(例如第一电容器C1的第一极板C11，和第二电容器C2的第一极板C21)。第二栅极层32还包括第二极板图案，第二极板图案包括各像素电路10的电容器的第二极板(例如第一电容器C1的第二极板C12，和第二电容器C2的第二极板C22)。
如图14所示，第一极板图案和第二极板图案在衬底1上的正投影有交叠。第一电容器C1的第二极板C12与第一极板C11相交叠形成第一电容器C1，第二电容器C2的第二极板C22与第一极板C21相交叠形成第二电容器C2。
在一些实施例中，如图3、图4和图12所示，多层源漏导电层4中一对相邻的源漏导电层4分别为第一设定源漏导电层和第二设定源漏导电层，第一设定源漏导电层相比第二设定源漏导电层靠近衬底1。其中，第一扇出线FIP1设于第一设定源漏导电层，数据线DL和第二扇出线FIP2设于第二设定源漏导电层。
示例性地，如图15所示，第二栅极层32与第一源漏导电层41之间设有绝缘介质层ILD，第二栅极层32与第一源漏导电层41电绝缘，绝缘介质层ILD上设有过孔，第二栅极层32内的第二栅导电图案与第一源漏导电层41内的第一导电图案中需要相连的部分通过绝缘介质层ILD上的过孔电连接。
示例性地，第一设定源漏导电层和第二设定源漏导电层之间还设有绝缘间隔层(例如平坦化层6)，第一设定源漏导电层和第二设定源漏导电层电绝缘，绝缘间隔层上设有过孔，第一设定源漏导电层和第二设定源漏导电层中需要相连的部分可以通过绝缘间隔层上的过孔电连接。第一扇出线FIP1的一端通过一个过孔与设定数据线DL1相连，另一端通过另一个过 孔与第二扇出线FIP2相连。
第一设定源漏导电层包括沿第一方向X延伸的第一扇出线FIP1，还可以包括沿第一方向X延伸的其他信号线，第二设定源漏导电层内包括沿第二方向Y延伸的第二扇出线FIP2和数据线DL，也还可以包括沿第二方向Y延伸的其他信号线。采用这样的设计，每层源漏导电层内包括的多条信号线可以是均沿同一方向延伸，简化了内的导电图案的结构，从而简化了源漏导电层的制备工艺。
同时，通过第一扇出线FIP1和第二扇出线FIP2可以将显示区AA内位于沿第一方向X的两侧的数据线DL(设定数据线DL1)从显示区AA内引出至绑定区BB，从而减小显示基板100的周边区AN在绑定区BB一侧的宽度，进而减小了显示装置1000的用于绑定驱动器的一侧的边框宽度。
如图14和图15所示，第一扇出线FIP1设于第一设定源漏导电层，辅助参考电压信号线VRef11位于第二栅极层32。在沿显示基板100的厚度方向上，辅助参考电压信号线VRef11位于第五节点N5的上方，第一扇出线FIP1位于辅助参考电压信号线VRef11的上方。即，辅助参考电压信号线VRef11位于第五节点N5和第一扇出线FIP1之间。
辅助参考电压信号线VRef11被配置为传输参考电压信号，辅助参考电压信号为恒压信号，这样，第五节点N5和第一扇出线FIP1之间的辅助参考电压线VRef11能够起到屏蔽效果，防止第一扇出线FIP上传输的数据信号与第五节点N5之间产生信号串扰，保证像素电路10的正常工作。
在一些实施例中，如图3和图4所示，多层源漏导电层4包括第一源漏导电层41和第二源漏导电层42，第一源漏导电层41为第一设定源漏导电层，第二源漏导电层42为第二设定源漏导电层。
示例性地，第一扇出线FIP1设于第一源漏导电层41，数据线DL和第二扇出线FIP2设于第二源漏导电层42。
示例性地，如图15所示，第一源漏导电层41包括第一源漏导电图案，第一源漏导电图案包括各晶体管TFT的源极411和漏极412。上述源极411和漏极412在结构上可以是相同的，因此晶体管TFT的源极411和漏极412可以进行互换。
示例性地，如图15所示，第一源漏导电图案还包括沿第一方向X延伸的第一栅极线GL1、第二栅极线GL2、第三栅极线GL3、第一扇出线FIP1、辅助第二电压信号线DIP、辅助第一电压信号线SIP和第一使能信号线EM1。第一使能信号线EM1被配置为向晶体管TFT传输发光控制信号。
参见图14和图15，第二电容器C2的第二极板C22上设有开口，第一源漏导电层41内还包括连接线LX，连接线LX的一端通过开口与第二电容器C2的第一极板C21相连，另一端与图14中的虚线框内第五节点N5相连。
参见图14和图15，在沿显示基板100的厚度方向上，辅助参考电压信号线VRef11位于第五节点N5的上方，第一扇出线FIP1位于辅助参考电压信号线VRef11的上方。即，辅助参考电压信号线VRef11位于第五节点N5和第一扇出线FIP1之间。
辅助参考电压信号线VRef11被配置为传输参考电压信号，辅助参考电压信号为恒压信号，这样，第五节点N5和第一扇出线FIP1之间的辅助参考电压线VRef11能够起到屏蔽效果，防止第一扇出线FIP上传输的数据信号与第五节点N5之间产生信号串扰，保证像素电路10的正常工作。
示例性地，如图12所示，显示基板100还包括：多层平坦化层6，多层平坦化层6包括第一平坦化层61和第二平坦化层62。第一平坦化层61设于第一源漏导电层41和第二源漏导电层42之间，第二平坦化层62设于第二源漏导电层42远离第一源漏导电层41的一侧。
在一些实施例中，如图3和图4所示，第二源漏导电层42包括沿第二方向Y延伸的数据线DL，第一电压信号线VSS、第二电压信号线VDD、第二扇出线FIP2和参考电压信号线VRef1。
示例性地，如图8所示，第一平坦化层61上设有多个过孔，第一电压信号线VSS与辅助第一电压信号线SIP通过第一平坦化层61上的过孔电连接，从而在不增加膜层结构的同时，增加显示区AA内的用于传输第一电压信号的信号线的数量，增加显示区AA内用于传输第一电压信号的信号线的布线密度，减小第一电压信号线VSS的电阻。
示例性地，如图8所示，第二电压信号线VDD与辅助第一电压信号线DIP通过第一平坦化层61上的过孔电连接，从而在不增加膜层结构的同时，增加显示区AA内的用于传输第二电压信号的信号线的数量，增加显示区AA内用于传输第二电压信号的信号线的布线密度，减小第二电压信号线VDD的电阻。
在一些实施例中，多层源漏导电层4包括第一源漏导电层41、第二源漏导电层42和第三源漏导电层43，第一源漏导电层41为第一设定源漏导电层，第二源漏导电层42为第二设定源漏导电层。
示例性地，第一扇出线FIP1设于第一源漏导电层41，数据线DL和第二扇出线FIP2设于第二源漏导电层42。
示例性地，如图12所示，多层平坦化层6还包括第三平坦化层63，设于第三源漏导电层43远离第二源漏导电层42的一侧。
在一些实施例中，多层源漏导电层4包括第一源漏导电层41、第二源漏导电层42和第三源漏导电层43，第二源漏导电层42为第一设定源漏导电层，第三源漏导电层43为第二设定源漏导电层。
示例性地，第二源漏导电层42为第一设定源漏导电层，第三源漏导电层43为第二设定源漏导电层。第一扇出线FIP1设于第二源漏导电层42，数据线DL和第二扇出线FIP2设于 第三源漏导电层43。
需要说明的是，显示基板100可以包括两层半导体层，其中一层半导体层的材料例如包括低温多晶硅，另一层半导体层的材料例如包括金属氧化物，像素电路10包括的多个晶体管TFT的有源层分别位于两层半导体层中，这样，像素电路10包括的多个晶体管TFT包括部分低温多晶硅薄膜晶体管和部分氧化物薄膜晶体管。
在一些实施例中，如图14和图15所示，显示基板100还包括：设于半导体层2远离衬底1一侧的多条辅助参考电压信号线VRef11。辅助参考电压信号线VRef11沿第一方向X延伸，且与参考电压信号线VRef1电连接。其中，第一扇出线FIP1设于辅助参考电压信号线VRef11远离衬底1的一侧。在向衬底1的正投影中，第一扇出线FIP1与辅助参考电压信号线VRef11交叠，且与半导体层2的部分交叠。
在沿显示基板100的厚度方向上，辅助参考电压信号线VRef11位于第五节点N5的上方，第一扇出线FIP1位于辅助参考电压信号线VRef11的上方。即，辅助参考电压信号线VRef11位于第五节点N5和第一扇出线FIP1之间，这样，辅助参考电压信号线VRef11传输的辅助参考电压信号为恒压信号，能够起到屏蔽效果，防止第一扇出线FIP上传输的数据信号与第五节点N5之间产生信号串扰，保证像素电路10的正常工作。
需要说明的是，第一扇出线FIP1沿第一方向X延伸，第一扇出线FIP1和与其相邻的一行像素电路10的第五节点N5之间均设置屏蔽结构，从而防止第一扇出线FIP1传输的数据信号与像素电路10的第五节点N5之间产生信号串扰。屏蔽结构可以是沿显示基板100的厚度方向上，位于第一扇出线FIP1和第五节点N5之间的辅助参考电压信号线VRef11，也可以是其他传输恒压信号的信号线。
在一些实施例中，如图6和图7所示，显示基板100还包括：多条第二电压信号线VDD。第二电压信号线VDD沿第二方向Y延伸，一列像素电路10与一条第二电压信号线VDD电连接。
其中，多条第二电压信号线VDD所在的膜层位于第一扇出线FIP1所在的膜层远离衬底1的一侧，在向衬底1的正投影中，第二电压信号线VDD覆盖第一扇出线FIP1的第一断口DK1。
示例性地，如图6和图7所示，第一扇出线FIP1位于第一源漏导电层41，第二电压信号线VDD位于第二源漏导电层42。第一扇出线FIP1上的第一断口DK1在显示基板100上的正投影落入第二电压信号线VDD在在显示基板100上的正投影的范围内，即，第一断口DK1被第二电压信号线VDD遮挡，自衬底1远离第一源漏导电层41的一侧的环境光射向衬底1时，环境光射向第一扇出线FIP1未设置断口DK1的部分可以被第一扇出线FIP1遮挡并反射，环境光射向第一断口DK1的部分可以被第二电压信号线VDD遮挡并反射，进而降低第一源漏导电层41在第一断口DK1处和未设置第一断口DK1处的光反射率差异，有效弱化 由第一断口DK1导致的息屏mura现象。
示例性地，第二扇出线FIP2上的第二断口DK2的数量大于或等于第一扇出线FIP1上的第一断口DK1的数量。
在一些示例中，如图5、图6和图7所示，设定数据线DL1所对应相连的一条第一扇出线FIP1和一条第二扇出线FIP2中，第二扇出线FIP2上的第二断口DK2的数量是第一扇出线FIP1上的第一断口DK1的数量的一半。例如，每条第一扇出线FIP1上设有两个第一断口DK1，每条第二扇出线FIP2上设有一个第二断口DK2。
在另一些示例中，设定数据线DL1所对应相连的一条第一扇出线FIP1和一条第二扇出线FIP2中，第二扇出线FIP2上的第二断口DK2的数量等于第一扇出线FIP1上的第一断口DK1的数量。例如，每条第一扇出线FIP1上设有一个第一断口DK1，每条第二扇出线FIP2上设有一个第二断口DK2。
可以理解的是，参见图3和图5，第一扇出线FIP1沿第一方向X上的长度例如与显示区AA沿第一方向X上的长度相同或大致相同，第二扇出线FIP1沿第二方向Y上的长度例如与显示区AA沿第二方向Y上的长度相同或大致相同。第二扇出线FIP2的有效部分FIP21的一端延伸至绑定区BB，另一端沿第二方向Y延伸向显示区AA，且与第一扇出线FIP1的有效部分FIP11的一端相连，第一扇出线FIP1的有效部分FIP11的另一端与一条设定数据线DL1相连。
在设定数据线DL1与显示区AA沿第二方向Y延伸的边界之间不设置有其他信号线时，与该设定数据线DL1相连的第一扇出线FIP1上可以设置一个第一断口DK1。
在设定数据线DL1与显示区AA沿第二方向Y延伸的边界之间还设有第一电压线VSS或第二电压线VDD等其他信号线时，与该设定数据线DL1相连的第一扇出线FIP1上可以设置两个第一断口DK1，两个第一断口DK1分设于该设定数据线DL1沿第一方向X上的两侧。这样，该第一扇出线FIP1具有两个冗余部分FIP12，这两个冗余部分FIP12可以分别与两条信号线(例如第一电压信号线VSS或第二电压信号线VDD等)相连，用于增加与其相连的信号线在显示区AA内的布线密度，从而降低其相连的信号线的电阻。
第一扇出线FIP1和第二扇出线FIP2上的断口的具体设计可以根据实际需要进行适应性设计，此处仅做示例性说明，不作为对本公开的限定。
在一些实施例中，如图3、图4和图6所示，显示基板100还包括：栅极信号线GL1、使能信号线EM、辅助第一电压信号线SIP和辅助第二电压信号线DIP，均沿第一方向X延伸。像素电路10与栅极信号线GL1和使能信号线EM电连接。辅助第一电压信号线SIP与第一电压信号线VSS电连接，辅助第二电压信号线DIP与第二电压信号线VDD电连接。
第一设定源漏导电层中设有栅极信号线GL1、使能信号线EM、辅助第一电压信号线SIP和辅助第二电压信号线DIP中的至少一者。在向衬底1的正投影中，栅极信号线GL1、使能 信号线EM、辅助第一电压信号线SIP和辅助第二电压信号线DIP中的至少一者覆盖第二扇出线FIP2的第二断口DK2。
示例性地，使能信号线EM包括第一使能信号线EM1和第二使能信号线EM2。像素电路10与第一使能信号线EM1和第二使能信号线EM2电连接。
在显示基板100包括两层源漏导电层4的情况下，第一设定源漏导电层为第一源漏导电层41。在显示基板100包括三层源漏导电层4的情况下，第一设定源漏导电层为第一源漏导电层41或第二源漏导电层42。以第一设定源漏导电层为第一源漏导电层41，第二设定源漏导电层为第二源漏导电层42为例进行说明。
栅极信号线GL1、使能信号线EM、辅助第一电压信号线SIP和辅助第二电压信号线DIP中的至少一者位于第一设定源漏导电层内，第二扇出线FIP2位于第二设定源漏导电层内，第一设定源漏导电层位于第二设定源漏导电层和衬底1之间，这样，第一设定源漏导电层内的栅极信号线GL1、使能信号线EM、辅助第一电压信号线SIP和辅助第二电压信号线DIP中的至少一者覆盖第二扇出线FIP2的第二断口DK2时，能够起到信号屏蔽效果，避免从相邻的子像素P(x)的像素电路10之间穿过的第二扇出线FIP2传输的数据信号，与像素电路10内的节点之间产生信号串扰，保证像素电路10的正常工作。
如图6所示，第一源漏导电层41内与第二断口DK2交叠的横向的信号线可以为栅极信号线GL1、使能信号线EM、辅助第一电压信号线SIP或辅助第二电压信号线DIP中的至少一者。
在一些实施例中，如图12和图15所示，显示基板100的第一电压信号线VSS、第二电压信号线VDD和参考电压信号线VRef1均设于第二设定源漏导电层。
第二设定源漏导电层内的第一电压信号线VSS、第二电压信号线VDD和参考电压信号线VRef1，可以对第一设定源漏导电层内的第一扇出线FIP1上的第一断口DK1进行遮挡，防止第一扇出线FIP1传输的数据信号在第一断口DK1位置与像素电路10内的节点之间产生信号串扰，保证像素电路10的正常工作。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (21)

  1. 一种显示基板，具有显示区和绑定区，所述绑定区位于所述显示区的沿第二方向的一侧；
    所述显示基板包括：
    多个像素电路，所述多个像素电路排列成多行多列，一行像素电路沿第一方向排列，一列像素电路沿所述第二方向排列，所述第一方向和所述第二方向相交叉；
    多条数据线，所述数据线沿所述第二方向延伸，一列像素电路与一条所述数据线电连接；
    第一扇出线和第二扇出线，设于所述显示区；所述第一扇出线沿所述第一方向延伸，所述第二扇出线沿所述第二方向延伸；所述多条数据线中的至少一条为设定数据线，所述第二扇出线相比所述设定数据线靠近所述绑定区的沿所述第二方向的中线；所述第一扇出线的一端与所述设定数据线电连接，另一端与所述第二扇出线电连接；
    其中，所述显示基板包括多个像素，每个像素包括至少三个子像素，每个子像素包括一个所述像素电路；所述多个像素中的至少一个为设定像素，一个所述设定像素对应设置有至少一条所述第二扇出线，所述第二扇出线从对应的设定像素中相邻两个子像素的像素电路之间穿过，或从对应的设定像素中位于外侧的像素电路的外侧穿过，并延伸至所述绑定区。
  2. 根据权利要求1所述的显示基板，其中，所述显示基板还包括：
    第一电压信号线，沿所述第二方向延伸；一个所述设定像素对应设置有至少一条所述第一电压信号线，所述第一电压信号线从对应的设定像素中的相邻两个子像素的像素电路之间穿过，或从对应的设定像素中位于外侧的像素电路的外侧穿过。
  3. 根据权利要求2所述的显示基板，其中，所述设定像素对应的至少一条所述第二扇出线和至少一条所述第一电压信号线中，一条所述第二扇出线从一对相邻的子像素的像素电路之间穿过，一条所述第一电压信号线从另外一对相邻的子像素的像素电路之间穿过。
  4. 根据权利要求3所述的显示基板，其中，所述像素包括三个子像素；
    所述设定像素对应设置有一条所述第二扇出线和一条所述第一电压信号线，所述第二扇出线从所述三个子像素中的一对相邻的子像素的像素电路之间穿过，所述第一电压信号线从所述三个子像素中另外一对相邻的子像素的像素电路之间穿过。
  5. 根据权利要求2所述的显示基板，其中，所述设定像素对应的所述第二扇出线和所述第一电压信号线中，一条所述第一电压信号线和一条所述第二扇出线从同一对相邻的子像素的像素电路之间穿过。
  6. 根据权利要求5所述的显示基板，其中，所述像素包括三个子像素；
    所述设定像素对应设置有一条所述第二扇出线和一条所述第一电压信号线，所述第二扇出线和所述第一电压信号线从所述三个子像素中的同一对相邻的子像素的像素电路之间穿过。
  7. 根据权利要求5或6所述的显示基板，其中，所述第二扇出线设有第二断口，所述第 二断口将所述第二扇出线分成有效部分和冗余部分；所述第二扇出线的有效部分的一端与所述第一扇出线电连接，另一端延伸至所述绑定区；
    所述显示基板还包括：第一连接部，所述第一电压信号线和所述第二扇出线的冗余部分通过所述第一连接部电连接。
  8. 根据权利要求7所述的显示基板，其中，从同一对相邻的子像素的像素电路之间穿过的所述第一电压信号线和所述第二扇出线相邻设置，所述第一电压信号线、所述第二扇出线和所述第一连接部同层设置且一体成型。
  9. 根据权利要求7或8所述的显示基板，其中，所述第一扇出线设有第一断口，所述第一断口将所述第一扇出线分成有效部分和冗余部分；所述第一扇出线的有效部分的一端与所述设定数据线电连接，另一端与所述第二扇出线的有效部分电连接；
    所述显示基板还包括：第二连接部，所述第二连接部的一端与所述第一扇出线的冗余部分电连接；沿所述显示基板的厚度方向，所述第二连接部与所述第二扇出线的冗余部分之间设有过孔，所述第二连接部的另一端通过所述过孔与所述第二扇出线的冗余部分电连接。
  10. 根据权利要求9所述的显示基板，其中，所述第二连接部和所述第一扇出线的冗余部分同层设置且一体成型。
  11. 根据权利要求1～10中任一项所述的显示基板，其中，所述显示基板还包括：
    多条参考电压信号线，所述参考电压信号线沿所述第二方向延伸，一列像素电路与一条所述参考电压信号线电连接；相邻两列像素电路中，一列像素电路所连接的参考电压信号线，和另一列像素电路所连接的数据线相靠近设置；
    其中，所述第二扇出线设于相靠近设置的所述参考电压信号线和所述数据线之间。
  12. 根据权利要求11所述的显示基板，其中，所述显示基板的第一电压信号线设于相靠近设置的所述参考电压信号线和所述数据线之间。
  13. 根据权利要求11或12所述的显示基板，其中，所述显示基板还包括：
    衬底；
    设于所述衬底上的半导体层；
    设于所述半导体层远离所述衬底一侧的多条辅助参考电压信号线，所述辅助参考电压信号线沿所述第一方向延伸，且与所述参考电压信号线电连接；
    其中，所述第一扇出线设于所述辅助参考电压信号线远离所述衬底的一侧；在向所述衬底的正投影中，所述第一扇出线与所述辅助参考电压信号线交叠，且与半导体层的部分交叠。
  14. 根据权利要求1～13中任一项所述的显示基板，其中，所述显示基板还包括：
    多条第二电压信号线，所述第二电压信号线沿所述第二方向延伸，一列像素电路与一条所述第二电压信号线电连接；
    其中，所述多条第二电压信号线所在的膜层位于所述第一扇出线所在的膜层远离衬底的 一侧，在向所述衬底的正投影中，所述第二电压信号线覆盖所述第一扇出线的第一断口。
  15. 根据权利要求1～14中任一项所述的显示基板，其中，所述显示基板还包括：
    多层源漏导电层，所述多层源漏导电层中一对相邻的源漏导电层分别为第一设定源漏导电层和第二设定源漏导电层，所述第一设定源漏导电层相比所述第二设定源漏导电层靠近衬底；
    其中，所述第一扇出线设于所述第一设定源漏导电层，所述数据线和所述第二扇出线设于所述第二设定源漏导电层。
  16. 根据权利要求15所述的显示基板，其中，所述显示基板还包括：栅极信号线、使能信号线、辅助第一电压信号线和辅助第二电压信号线，均沿所述第一方向延伸；所述像素电路与所述栅极信号线和所述使能信号线电连接；所述辅助第一电压信号线与第一电压信号线电连接，所述辅助第二电压信号线与第二电压信号线电连接；
    所述第一设定源漏导电层中设有所述栅极信号线、所述使能信号线、所述辅助第一电压信号线和所述辅助第二电压信号线中的至少一者；在向所述衬底的正投影中，所述栅极信号线、所述使能信号线、所述辅助第一电压信号线和所述辅助第二电压信号线中的至少一者覆盖所述第二扇出线的第二断口。
  17. 根据权利要求15或16所述的显示基板，其中，所述显示基板的第一电压信号线、第二电压信号线和参考电压信号线均设于所述第二设定源漏导电层。
  18. 根据权利要求15～17中任一项所述的显示基板，其中，所述显示基板还包括：第一栅极层和第二栅极层；所述显示基板的半导体层、所述第一栅极层和所述第二栅极层沿远离衬底的方向依次设置，且位于所述衬底和所述多层源漏导电层之间；
    所述显示基板的辅助参考电压信号线设于所述第二栅极层。
  19. 根据权利要求15～18中任一项所述的显示基板，其中，
    所述多层源漏导电层包括第一源漏导电层和第二源漏导电层，所述第一源漏导电层为所述第一设定源漏导电层，所述第二源漏导电层为所述第二设定源漏导电层；或，
    所述多层源漏导电层包括第一源漏导电层、第二源漏导电层和第三源漏导电层，所述第一源漏导电层为所述第一设定源漏导电层，所述第二源漏导电层为所述第二设定源漏导电层；或，
    所述多层源漏导电层包括第一源漏导电层、第二源漏导电层和第三源漏导电层，所述第二源漏导电层为所述第一设定源漏导电层，所述第三源漏导电层为所述第二设定源漏导电层。
  20. 根据权利要求1～19中任一项所述的显示基板，其中，相比所述多条数据线中的其他数据线，所述设定数据线更远离所述绑定区的沿所述第二方向的中线；所述设定数据线整体位于所述显示区内，所述其他数据线的端部延伸至所述绑定区。
  21. 一种显示装置，包括：
    如权利要求1～20中任一项所述的显示基板；
    电路板，与所述显示基板电连接。
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CN115188792A (zh) * 2022-07-15 2022-10-14 京东方科技集团股份有限公司 显示基板及显示装置
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CN115064108A (zh) * 2022-06-30 2022-09-16 武汉天马微电子有限公司 显示面板及显示装置
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