WO2024262221A1 - 半導体モジュール - Google Patents

半導体モジュール Download PDF

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Publication number
WO2024262221A1
WO2024262221A1 PCT/JP2024/018677 JP2024018677W WO2024262221A1 WO 2024262221 A1 WO2024262221 A1 WO 2024262221A1 JP 2024018677 W JP2024018677 W JP 2024018677W WO 2024262221 A1 WO2024262221 A1 WO 2024262221A1
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WO
WIPO (PCT)
Prior art keywords
chip
semiconductor
tci
inductor
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/JP2024/018677
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English (en)
French (fr)
Japanese (ja)
Inventor
敦丈 小菅
忠広 黒田
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Research Association For Advanced Systems
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Research Association For Advanced Systems
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Publication date
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Priority to JP2025527598A priority Critical patent/JPWO2024262221A1/ja
Publication of WO2024262221A1 publication Critical patent/WO2024262221A1/ja
Priority to US19/406,076 priority patent/US20260101521A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/7295—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors on the rear surface of insulating package substrates, interposers or RDLs, for connection outside of the package, e.g. ball grid array [BGA] bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D80/00—Assemblies of multiple devices comprising at least one device covered by this subclass
    • H10D80/30—Assemblies of multiple devices comprising at least one device covered by this subclass the at least one device being covered by groups H10D84/00 - H10D86/00, e.g. assemblies comprising integrated circuit processor chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/301—Bonding techniques, e.g. hybrid bonding
    • H10W80/314—Bonding techniques, e.g. hybrid bonding characterized by direct bonding of pads or other interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/26—Configurations of stacked chips the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • One embodiment of the present invention relates to a semiconductor module.
  • an electronic computer includes multiple logic chips and multiple memory chips electrically connected to the multiple logic chips.
  • the logic chip is, for example, a semiconductor chip on which a logic circuit is implemented
  • the memory chip is, for example, a semiconductor chip on which a memory circuit is implemented.
  • Data communication in an electronic computer is performed, for example, between the logic chip and the memory chip. For example, stacking the logic chip and the memory chip to implement them in three dimensions to shorten the distance between the logic chip and the memory chip is one effective solution for reducing the power consumption of an electronic computer.
  • Patent documents 1 to 6 disclose, as examples of three-dimensional packaging methods, a semiconductor module in which a structure (vertically stacked memory cube) in which multiple memory chips are stacked is arranged on a substrate or logic chip so that the memory chips are parallel to the substrate or logic chip, or a semiconductor module in which a structure (horizontally stacked memory cube) in which multiple memory chips are stacked is suspended (standing vertically) on a substrate or logic chip so that the memory chips are perpendicular to the substrate or logic chip.
  • the vertically stacked memory cubes disclosed in patent documents 1 to 3 and the substrate or logic chip are electrically connected using, for example, TSVs or microbumps.
  • Patent documents 5 and 6 also disclose technology for non-contact communication between a chip and a substrate.
  • the memory chips, substrates, and logic chips of the semiconductor modules described in Patent Documents 1 to 3 are stacked parallel to the stacking direction, so the thermal resistance of the semiconductor module increases due to, for example, the oxide film contained in the stacked memory chips.
  • the thermal resistance of the semiconductor module increases, the thermal conductivity of the semiconductor module decreases, making it difficult to remove heat from, for example, the logic chip.
  • the temperature of the semiconductor module increases, which may cause the semiconductor module to malfunction due to the temperature increase.
  • the logic chips of the semiconductor modules described in Patent Documents 1 to 3 are connected to external circuits using a redistribution layer.
  • the length of the wiring and the wiring load (capacity) increase, causing delays in signal transmission, degrading calculation performance, and increasing the power consumption of the chip.
  • one embodiment of the present invention aims to provide a semiconductor module that uses inductor communication, which has excellent thermal conduction and heat extraction characteristics, suppresses signal delays, and reduces power consumption.
  • a semiconductor module includes a first semiconductor chip including a first surface parallel to a first direction and a second direction intersecting the first direction, and a second surface parallel to the first surface, and a semiconductor cube including a sub-semiconductor cube in which a second semiconductor chip and a logic chip electrically connected to the second semiconductor chip are stacked in the first direction and arranged on the second surface, the logic chip includes a plurality of first inductors arranged parallel to a third direction perpendicular to the first direction and the second direction, the first semiconductor chip includes a plurality of routers and a plurality of second inductors arranged parallel to the second surface, the plurality of circuits in the first semiconductor chip are electrically connected using the plurality of routers, and the logic chip and the first semiconductor chip are configured to be capable of contactless communication using the plurality of first inductors and the plurality of second inductors.
  • the logic chip may be configured to control the multiple routers via the multiple first inductors and the multiple second inductors, and to be capable of connecting multiple circuits in the first semiconductor chip to the second semiconductor chip.
  • Each of the plurality of routers may include a switch.
  • the logic chip may include a first electrode
  • the second semiconductor chip may include a second electrode that can be joined to the first electrode using fusion bonding.
  • the semiconductor cube may include a plurality of the sub-semiconductor cubes stacked in the first direction, and the sub-semiconductor cubes may be configured to be capable of non-contact communication with each other via the plurality of second inductors using the plurality of first inductors included in each of the sub-semiconductor cubes.
  • the semiconductor cube includes at least one type of memory chip different from the second semiconductor chip, and includes a configuration in which the sub-semiconductor cube and the at least one type of memory chip are stacked in the first direction, and the at least one type of memory chip includes a plurality of third inductors, and at least one second inductor of the plurality of second inductors may be capable of contactless communication with at least one third inductor of the plurality of third inductors.
  • the semiconductor module may include a plurality of the semiconductor cubes, the plurality of semiconductor cubes being spaced apart from one another on the second surface.
  • the plurality of sub-semiconductor cubes may be spaced apart from one another on the second surface.
  • the semiconductor cube includes at least one type of memory chip different from the second semiconductor chip, and includes a configuration in which the sub-semiconductor cube and the at least one type of memory chip are stacked in the first direction, the second semiconductor chip includes a plurality of fourth inductors arranged parallel to the third direction and capable of non-contact communication with each of the plurality of second inductors, and a plurality of fifth inductors different from the plurality of fourth inductors, and the at least one type of memory chip may include a plurality of sixth inductors capable of non-contact communication with each of the plurality of fifth inductors.
  • a semiconductor module using inductor communication that has good thermal conductivity and excellent heat dissipation characteristics, while also suppressing signal delays and reducing power consumption.
  • FIG. 1 is a perspective view showing a configuration of a semiconductor module according to a first embodiment of the present invention
  • 1 is a cross-sectional view showing a configuration of a semiconductor module according to a first embodiment of the present invention.
  • 1A is an oblique view showing a group of inductors included in multiple logic chips according to a first embodiment of the present invention, and a group of inductors included in a magnetic field coupling chip-to-chip interface router chip (Through Chip Interface Router Chip (TCI router chip))
  • FIG. 1B is an oblique view showing the configuration of the inductors on the logic chips and the inductors on the TCI router chip shown in FIG. FIG.
  • 1 is a schematic diagram showing a configuration of a TCI router chip according to a first embodiment of the present invention
  • 1 is a schematic diagram showing a configuration of a logic chip according to a first embodiment of the present invention
  • 1 is a perspective view showing a configuration of a logic chip according to a first embodiment of the present invention
  • 7 is a cross-sectional view showing the cross-sectional structure of the logic chip taken along the line A1-A2 shown in FIG. 6.
  • 1 is a schematic diagram showing the configuration of an SRAM (Static Random Access Memory) chip according to a first embodiment of the present invention.
  • SRAM Static Random Access Memory
  • FIG. 1 is a perspective view showing a configuration of an SRAM chip according to a first embodiment of the present invention
  • 10 is a cross-sectional view showing the cross-sectional structure of the SRAM chip taken along line B1-B2 shown in FIG. 9.
  • 1 is a schematic diagram showing a configuration of a TCI router chip according to a first embodiment of the present invention
  • 1 is a perspective view showing a configuration of a TCI router chip according to a first embodiment of the present invention
  • 13 is a cross-sectional view showing the cross-sectional structure of the TCI router chip taken along line C1-C2 shown in FIG. 12.
  • FIG. 6 is a cross-sectional view showing a configuration of a semiconductor module according to a second embodiment of the present invention.
  • FIG. 10 is a schematic diagram showing the configuration of a semiconductor cube and a TCI router chip according to a second embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a configuration of a semiconductor module according to a third embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing the configuration of multiple semiconductor cubes and a TCI router chip according to a third embodiment of the present invention.
  • FIG. 11 is a cross-sectional view showing a configuration of a semiconductor module according to a fourth embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing the configuration of multiple sub-semiconductor cubes and a TCI router chip according to a fourth embodiment of the present invention.
  • FIG. 13 is a cross-sectional view showing a configuration of a semiconductor module according to a fifth embodiment of the present invention.
  • FIG. 13 is a schematic diagram showing the configuration of a semiconductor cube and a TCI router chip according to a fifth embodiment of the present invention.
  • 13 is a cross-sectional view showing a cross-sectional structure of an SRAM chip according to a fifth embodiment of the present invention.
  • 13 is a cross-sectional view showing a cross-sectional structure of a DRAM chip according to a fifth embodiment of the present invention.
  • a certain component or region when a certain component or region is said to be "above (or below)" another component or region, unless otherwise specified, this includes not only the case where it is directly above (or below) the other component or region, but also the case where it is above (or below) the other component or region, i.e., the case where another component is included between the other component or region and above (or below) the other component or region.
  • the D1 direction intersects with the D2 direction
  • the D3 direction intersects with the D1 and D2 directions (D1D2 plane).
  • the D1 direction is called the first direction
  • the D2 direction is called the second direction
  • the D3 direction is called the third direction.
  • the terms “same” and “match” when the terms “same” and “match” are used, the terms “same” and “match” may include tolerances within the design range. In addition, in one embodiment of the present invention, when tolerances within the design range are included, the terms “approximately same” and “approximately match” may be used.
  • FIG. 1 is a perspective view showing the configuration of the semiconductor module 10.
  • FIG. 2 is a cross-sectional view showing the configuration of the semiconductor module 10.
  • FIG. 3A is a perspective view showing an inductor group 271 included in a plurality of logic chips 200 included in the semiconductor module 10, and an inductor group 371 included in a magnetic field coupling chip-to-chip interface router chip (Through Chip Interface Router Chip (TCI router chip)) 300
  • FIG. 3B is a perspective view showing the configuration of the inductor 272 on the logic chip 200 and the inductor 372 on the TCI router chip 300 shown in FIG. 3A.
  • FIG. 4 is a schematic diagram showing the configuration of the semiconductor cube 100 and the TCI router chip 300 included in the semiconductor module 10.
  • FIG. 5 is a schematic diagram showing the configuration of the TCI router chip 300 included in the semiconductor module 10.
  • the semiconductor module 10 includes a semiconductor cube 100, a TCI router chip 300, and an adhesive layer 400.
  • the stack 20 is composed of the semiconductor cube 100, the TCI router chip 300, and the adhesive layer 400.
  • the semiconductor module 10 may include a bump layer 500, a package substrate 600, and a bump layer 700.
  • the TCI router chip 300 may be referred to as a first semiconductor chip.
  • the semiconductor cube 100 includes a sub-semiconductor cube 101 in which a logic chip 200 and an SRAM chip 110 electrically connected to the logic chip 200 are stacked in the D1 direction.
  • the semiconductor cube 100 includes a configuration in which multiple sub-semiconductor cubes 101 are stacked in the D1 direction.
  • Each of the multiple logic chips 200 has a similar configuration including multiple through electrodes 260 and multiple inductors 272 (first inductors).
  • Each of the multiple SRAM chips 110 has a similar configuration including multiple through electrodes 160.
  • the semiconductor cube 100 includes a first surface 142 parallel to the D2 and D3 directions, and a second surface 144 that is opposite to the first surface 142 with respect to the D1 direction and parallel to the first surface 142.
  • the semiconductor cube 100 also includes a first side 145 perpendicular to the first side 142 and the second side 144, a second side 146 adjacent to the first side 145, a third side 147 adjacent to the second side 146, and a fourth side 148 adjacent to the third side 147 and the first side 145.
  • the second side 146 is in contact with the adhesive layer 400 and faces the second side 304 of the TCI router chip 300, and the semiconductor cube 100 is disposed on the second side 304 of the TCI router chip 300.
  • the SRAM chip 110 may be referred to as a second semiconductor chip.
  • the logic chip 200 includes a first surface 202, which is an exposed surface of the logic chip 200, and a second surface 204, which is an exposed surface of the logic chip 200 opposite to the first surface 202.
  • a plurality of through electrodes 260 are exposed on the first surface 202.
  • a plurality of inductors 272 are arranged at a distance near the second surface 204. The plurality of inductors 272 are arranged parallel to and spaced apart from the second side surface 146, and are arranged side by side in the D2 direction. Details will be described later, but a substrate 273 (see, for example, FIG.
  • the logic chip 200 included in the logic chip 200 is located below (on the first surface 202 side) in the D1 direction, and an N-type transistor 268 and a P-type transistor 269 (see, for example, FIG. 8) are stacked above the substrate 273 in the D1 direction.
  • the first surface 202 of the logic chip 200 is arranged to face the first surface 102 of the SRAM chip 110.
  • the multiple logic chips 200 included in the semiconductor cube 100 include, for example, logic chip 200n (see FIG. 3) and logic chip 200n+1 (see FIG. 3) arranged adjacent to logic chip 200n.
  • the semiconductor cube 100 includes a configuration in which four sub-semiconductor cubes 101 are stacked in the D1 direction. The number of layers of the sub-semiconductor cubes 101 shown in FIG.
  • the number of layers of the sub-semiconductor cubes 101 is not limited to four (four layers) shown in FIG. 1.
  • the number of layers of the sub-semiconductor cubes 101 may be appropriately selected based on the application, specifications, etc. of the semiconductor module 10.
  • the SRAM chip 110 includes a first surface 102, which is the exposed surface of the SRAM chip 110, and a second surface 104, which is the exposed surface of the SRAM chip 110 opposite the first surface 102.
  • the first surface 102 faces and contacts the first surface 202 of the logic chip 200.
  • a plurality of through electrodes 160 are exposed on the first surface 102.
  • a substrate 173 (see, for example, FIG. 11) included in the SRAM chip 110 is located below (on the first surface 102 side) in the D1 direction, and an N-type transistor 168 and a P-type transistor 169 (see, for example, FIG. 11) are stacked above the substrate 173 in the D1 direction.
  • the SRAM chip 110 is also stacked (bonded) with the logic chip 200. At this time, each of the multiple through electrodes 160 is bonded with the corresponding multiple through electrodes 260, and the SRAM chip 110 is electrically connected to the logic chip 200.
  • techniques such as fusion bonding and silicon direct bonding (SDB) can be used. Since welding and silicon direct bonding are well known techniques in the technical field, detailed explanations are omitted here.
  • the multiple through electrodes 160 and the multiple through electrodes 260 are formed using a conductor made of, for example, a metal material.
  • the conductor made of a metal material is, for example, a conductor containing copper.
  • the through electrodes 160 and the through electrodes 260 may be called, for example, a second electrode and a first electrode, respectively.
  • the TCI router chip 300 includes, for example, a transistor layer 330 and an inductor layer 370 laminated on the transistor layer 330.
  • the transistor layer 330 includes a first surface 302, which is the exposed surface of the TCI router chip 300, and a plurality of through electrodes 360.
  • the plurality of through electrodes 360 are exposed on the first surface 302.
  • the inductor layer 370 includes a second surface 304, which is the exposed surface of the TCI router chip 300 opposite the first surface 302, and a plurality of inductors 372.
  • the first surface 302 and the second surface 304 are parallel to the D1 direction and the D2 direction.
  • the substrate 373 (see, for example, FIG. 14) included in the TCI router chip 300 is located downward (on the first surface 302 side) in the D3 direction, and the N-type transistor 368 and the P-type transistor 369 (see, for example, FIG. 14) are stacked above the substrate 373 in the D3 direction. That is, the stacking direction of each layer constituting the TCI router chip 300 is upward in the D3 direction.
  • a mounting structure in which the stacking direction is upward in the D3 direction is called face-up mounting
  • a mounting structure in which the stacking direction is downward in the D3 direction is called face-down mounting.
  • the first surface 302 of the TCI router chip 300 is placed on the package substrate 600, and the TCI router chip 300 is face-up mounted on the package substrate 600.
  • the adhesive layer 400 is disposed between the semiconductor cube 100 and the TCI router chip 300, and bonds the semiconductor cube 100 and the TCI router chip 300.
  • the adhesive layer 400 may be, for example, an adhesive containing an epoxy resin or an acrylic polymer, a die bonding film (DBF) containing an epoxy resin or an acrylic polymer, or an adhesive film such as a die attached film (DAF).
  • the through electrodes 609 are electrically connected to the through electrodes 611, and the through electrodes 611 are electrically connected to the through electrodes 613.
  • the insulating layers alternately stacked with the wiring are omitted.
  • the number of layers in the multilayer wiring structure of the package substrate 600 is not limited to the number of layers (three layers) shown in FIG. 2. The number of layers in the multilayer wiring structure of the package substrate 600 can be changed as appropriate based on the application or specifications of the semiconductor module 10.
  • the package substrate 600 is electrically connected to the laminate 20 via a plurality of bumps 502 included in the bump layer 500 disposed between the laminate 20 and the package substrate 600.
  • the package substrate 600 is also connected to an external substrate and an external circuit via a plurality of bumps 702 included in the bump layer 700.
  • each of the plurality of through electrodes 609 exposed on the first surface 602 is electrically connected to each of the plurality of through electrodes 360 using the bumps 502, and each of the plurality of through electrodes 613 exposed on the second surface 604 is connected to an external substrate and an external circuit using the bumps 702.
  • the semiconductor module 10 includes a semiconductor cube 100 suspended above a TCI router chip 300 in the D3 direction, and has a lower thermal resistance than a configuration including memory chips and logic chips stacked in parallel in the D1 and D2 directions. Therefore, the semiconductor module 10 has high thermal conductivity and excellent heat dissipation characteristics, and can suppress malfunctions caused by temperature increases in the semiconductor module. As a result, the limit on the number of stacked chips in the semiconductor module 10 is relaxed compared to a configuration including memory chips and logic chips stacked in parallel in the D1 and D2 directions. In addition, the semiconductor module 10 has high thermal conductivity and excellent heat dissipation characteristics, and can include a configuration in which logic chips with high power consumption are stacked.
  • the semiconductor module 10 also includes a logic chip 200 and an SRAM chip 110 that are bonded using fusion bonding.
  • the logic chip 200 is tightly coupled to the SRAM chip 110, and the length and wiring load (capacity) of the wiring connecting the logic chip 200 and the SRAM chip 110 are reduced.
  • the semiconductor module 10 can reduce delays in signal transmission that occur between the logic chip 200 and the SRAM chip 110.
  • Logic chip 200n+1 includes an inductor layer 270 (see, for example, Figures 7 and 8).
  • the inductor layer 270 includes multiple inductor groups 271, and each of the multiple inductor groups 271 includes multiple inductors 272.
  • each of the multiple inductors 272 is arranged parallel to the D3 direction perpendicular to the D1 direction and the D2 direction (i.e., the second surface 304).
  • the multiple inductors 272 are arranged in parallel to and spaced apart from the second side surface 146, and are arranged side by side in the D2 direction.
  • Each of the multiple inductors 272 includes terminal A, terminal B, a first portion 272a, a second portion 272b, a third portion 272c, a fourth portion 272d, and a fifth portion 272e.
  • the inductors 272 are electrically connected to the transmission/reception circuit 214 (FIG. 4) using terminal A and terminal B.
  • the fourth portion 272d extends in the D2 direction, one end of the fourth portion 272d is electrically connected to terminal A, and the other end of the fourth portion 272d is electrically connected to one end of the fifth portion 272e.
  • the fifth portion 272e extends in the D3 direction, and the other end of the fifth portion 272e is electrically connected to one end of the first portion 272a.
  • the first portion 272a extends in the D2 direction, and the other end of the first portion 272a is electrically connected to one end of the second portion 272b.
  • the second portion 272b extends in the D3 direction, and the other end of the second portion 272b is electrically connected to one end of the third portion 272c.
  • the third portion 272c extends in the D2 direction, and the other end of the third portion 272c is electrically connected to terminal B.
  • the TCI router chip 300 includes an inductor group 371 including a plurality of inductors 372 arranged parallel to the position where the plurality of inductors 272 are arranged, and parallel to and adjacent to the second surface 304.
  • the TCI router chip 300 includes an inductor layer 370 (see, for example, Figures 10 and 11), which includes a plurality of inductors 372.
  • the plurality of inductors 372 are arranged in a matrix along the D1 direction and the D2 direction.
  • Each of the plurality of inductors 372 includes a terminal C, a terminal D, a first portion 372a, a second portion 372b, a third portion 372c, a fourth portion 372d, and a fifth portion 372e.
  • the inductors 372 are electrically connected to the transmission/reception circuit 314 using the terminals C and D, as will be described in detail later.
  • the fourth portion 372d extends in the D2 direction, one end of the fourth portion 372d is electrically connected to terminal C, and the other end of the fourth portion 372d is electrically connected to one end of the fifth portion 372e.
  • the fifth portion 372e extends in the D1 direction, and the other end of the fifth portion 372e is electrically connected to one end of the first portion 372a.
  • the first portion 372a extends in the D2 direction, and the other end of the first portion 372a is electrically connected to one end of the second portion 372b.
  • the second portion 372b extends in the D1 direction, and the other end of the second portion 372b is electrically connected to one end of the third portion 372c.
  • the third portion 372c extends in the D2 direction, and the other end of the third portion 372c is electrically connected to terminal D.
  • the shape of the inductor 272 when viewed from the D1 direction in a plane parallel to the D2 and D3 directions, and the shape of the inductor 372 when viewed from the D3 direction in a plane parallel to the D1 and D2 directions, are, for example, rectangular. Since the logic chip 200 stands perpendicular to the TCI router chip 300, the inductor 272 is arranged facing the inductor 372 at 90 degrees. Also, when viewed from the D3 direction in a plane parallel to the D1 and D2 directions, the first part 272a of the inductor 272 overlaps the first part 372a of the inductor 372.
  • inductor 272 and inductor 372 that face each other are magnetically coupled, so that the inductors can communicate with each other one-to-one without contact.
  • the communication between the inductors due to magnetic field coupling is called, for example, inductor communication, signal communication, data communication, etc.
  • the shapes of inductor 272 and inductor 372 are not limited to a quadrangle.
  • inductor 272 and inductor 372 may be trapezoidal or pentagonal.
  • the shapes of inductor 272 and inductor 372 may be any shapes that allow inductor communication.
  • inductor 272 and inductor 372 face each other at 90 degrees and can communicate one-to-one by magnetic field coupling. More specifically, effective inductor communication is performed by first portion 272a of inductor 272 and first portion 372a of inductor 372.
  • First portion 272a mainly has the function of performing inductor communication with first portion 372a.
  • second portion 272b, third portion 272c, fourth portion 272d, and fifth portion 272e excluding first portion 272a mainly have the function of supplying current to first portion 272a.
  • second portion 372b, third portion 372c, fourth portion 372d, and fifth portion 372e excluding first portion 372a mainly have the function of supplying current to first portion 372a in inductor 372.
  • Inductor 372 has the same configuration and function as inductor 272. Note that in semiconductor module 10, viewing a surface parallel to the D2 and D3 directions from the D1 direction may be referred to as a front view, and viewing a surface parallel to the D1 and D2 directions from the D3 direction may be referred to as a planar view.
  • Circuit configuration of semiconductor module 10 The circuit configuration of the semiconductor module 10 will be described with reference to Fig. 4 and Fig. 5. As shown in Fig. 4, the semiconductor cube 100 and the TCI router chip 300 are connected based on inductor communication, and the logic chip 200 and the SRAM chip 110 are electrically connected using a signal bus 240. As shown in Fig. 5, each circuit in the TCI router chip 300 is electrically connected using a signal bus 340 via a plurality of network routers (Router(R)) 318 (318a to 318i).
  • Router(R) network routers
  • the semiconductor cube 100 includes, as an example, multiple sub-semiconductor cubes 101.
  • Each of the multiple sub-semiconductor cubes 101 includes a logic chip 200 and an SRAM chip 110.
  • the logic chip 200 is electrically connected to the SRAM chip 110 using a signal bus 240.
  • FIG. 4 the reference numeral 101 of the sub-semiconductor cube 101 has been omitted to clarify the drawing.
  • the logic chip 200 includes a magnetic coupling chip-to-chip interface (Through Chip Interface-IO (TCI-IO)) 212 and multiple logic modules 211.
  • TCI-IO Through Chip Interface-IO
  • the multiple TCI-IOs 212 are electrically connected to the logic module 211.
  • the logic chip 200 includes multiple TCI-IOs 212, in FIG. 4, the number of TCI-IOs 212 is reduced to one for clarity of illustration.
  • the TCI-IO 212 includes an inductor 272, a transmitting/receiving circuit 214, and a parallel-serial conversion circuit 213.
  • the inductor 272 is electrically connected to the transmitting/receiving circuit 214 using terminals A and B.
  • the transmitting/receiving circuit 214 is electrically connected to the parallel-serial conversion circuit 213.
  • the parallel-serial conversion circuit 213 is electrically connected to the logic module 211.
  • the inductor 272 has the function of non-contact inductor communication with the inductor 372 of the TCI router chip 300.
  • the transmitting/receiving circuit 214 has, for example, a function of amplifying the signal (data) received by the inductor 272, and a function of removing noise from the received signal (data).
  • the transmitting/receiving circuit 214 also has a function of transmitting the desired signal (data) converted using the parallel-serial conversion circuit 213 onto a radio wave.
  • the signal received by the inductor 272 includes a large number of parallel signals (parallel signals) from the TCI router chip 300.
  • the desired signal includes a large number of parallel signals (parallel signals) from the logic module 211.
  • the parallel-serial conversion circuit 213 performs parallel-serial conversion on a number of parallel signals from the TCI router chip 300 to convert them into serial signals (serial signals).
  • the serial signals are transferred at high speed using a single signal path (wiring).
  • the parallel-serial conversion circuit 213 performs serial-parallel conversion on the serial signals just before the logic module 211 to return them to a number of parallel signals, and then transmits the number of parallel signals to the logic module 211.
  • the parallel-serial conversion circuit 213 performs, for example, step 1 following step 2.
  • the parallel-serial conversion circuit 213 is called, for example, a SerDes circuit (Serialize and Deserialize Circuit).
  • the logic module 211 has a function for controlling the transmission of signals (data) to the TCI-IO 212, or the reception of signals (data) from the TCI-IO 212.
  • the logic module 211 also has a function for driving the memory module 111 (FIG. 9) in the SRAM chip 110.
  • the logic module 211 transmits a signal for driving the memory module 111 via the TCI-IO 212.
  • the logic module 211 may include an arithmetic circuit such as a CPU (Central Processing Unit).
  • the TCI router chip 300 includes, for example, multiple TCI-IOs 312, multiple Rs 318, a DRAM interface (DRAMIO) 311, a PCIe interface (PCI Express Interface (PCIeIF)) 315, an Ethernet interface (Ethernet Interface (EIF)) 316, and a memory controller 319.
  • DRAMIO DRAM interface
  • PCIeIF PCI Express Interface
  • EIF Ethernet interface
  • TCI-IO312, DRAMIO311, PCIeIF315, EIF316, and memory controller 319 are functional blocks that make up an LSI (Large Scale Integration).
  • the functional blocks that make up an LSI are called, for example, IP (Intellectual Property) cores, IPs, or macros.
  • IP cores include a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), memory, etc.
  • the configuration and functions of the TCI router chip 300 are not limited to the TCI router chip 300 shown in FIG. 4 or FIG. 5.
  • the number of TCI-IOs 312 included in the TCI router chip 300 and the number and types of IP cores are not limited to multiple TCI-IOs 312, DRAMIOs 311, PCIe IFs 315, EIFs 316, and memory controllers 319.
  • the configuration and functions of the TCI router chip 300 are appropriately selected depending on the specifications and applications of the semiconductor module 10, the number of IP cores included in the semiconductor module 10, and the like.
  • the TCI router chip 300 may include multiple DRAMIOs 311, multiple memory controllers 319, and an external IO (not shown).
  • the IP cores such as multiple TCI-IO312, DRAMIO311, PCIeIF315, EIF316, and memory controller 319, include a network interface (NI) 317.
  • NI network interface
  • IP cores such as the multiple TCI-IO312, DRAMIO311, PCIeIF315, EIF316, and memory controller 319 do not include NI317, and NI317 is located outside the multiple TCI-IO312, DRAMIO311, PCIeIF315, EIF316, and memory controller 319, and each of the multiple TCI-IO312, DRAMIO311, PCIeIF315, EIF316, and memory controller 319 may be electrically connected to R318 corresponding to each circuit via NI317.
  • the multiple IP cores such as TCI-IO312, DRAMIO311, PCIeIF315, EIF316, and memory controller 319 are electrically connected to R318 corresponding to the NI317 of each IP core.
  • the multiple IP cores such as TCI-IO312, DRAMIO311, PCIeIF315, EIF316, and memory controller 319 are connected in a network using multiple R318.
  • the multiple R318s are electrically connected using, for example, multiple signal buses 340.
  • the network configuration of the IP core using multiple R318 may be a mesh as shown in FIG. 5.
  • the network configuration of the IP core shown in FIG. 5 is one example, and the network configuration of the IP core is not limited to the configuration shown in FIG. 5.
  • the network configuration of the IP core is appropriately selected depending on the specifications and applications of the semiconductor module 10, the number of IP cores included in the semiconductor module 10, etc.
  • the multiple TCI-IOs 312 include, for example, TCI-IOs 312a, 312b, ... and 312e.
  • TCI-IO312 When the multiple TCI-IOs 312 are not distinguished from one another, the TCI-IO is expressed as TCI-IO312.
  • TCI-IOs 312a, 312b, ... and 312e When the multiple TCI-IOs 312 are distinguished from one another, the multiple TCI-IOs are expressed as TCI-IOs 312a, 312b, ... and 312e, etc.
  • TCI-IO312 includes an inductor 372, a transmitting/receiving circuit 314, a parallel-serial conversion circuit 313, and an NI317.
  • the inductor 372 is electrically connected to the transmitting/receiving circuit 314 using terminals C and D.
  • the transmitting/receiving circuit 314 is electrically connected to the parallel-serial conversion circuit 313.
  • the parallel-serial conversion circuit 313 is electrically connected to NI317.
  • TCI-IO312 (NI317) is electrically connected to R318.
  • the configurations and functions of the inductor 372, the transmission/reception circuit 314, the parallel-serial conversion circuit 313, and the memory controller 319 are similar to those of the inductor 272, the transmission/reception circuit 214, the parallel-serial conversion circuit 213, and the logic module 211. Therefore, a description of the configurations and functions of the inductor 372, the transmission/reception circuit 314, the parallel-serial conversion circuit 313, and the memory controller 319 will be omitted here.
  • NI 317 can convert, for example, data transmitted and received using signal bus 340 into a data format corresponding to an IP core electrically connected to NI 317, and can convert a data format corresponding to an IP core into a data format corresponding to signal bus 340.
  • semiconductor module 10 can transmit and receive both addresses and data using signal bus 340, and therefore can have a smaller bus width than a module including signal buses arranged in a concentrated manner.
  • semiconductor module 10 can transmit and receive data without relying on the data format corresponding to each IP core, and therefore can suppress an increase in the number of signal buses 340.
  • the data transmitted and received using the signal bus 340 includes, for example, an address that can identify an IP core electrically connected to the NI 317.
  • the multiple R318s include, for example, R318a, 318b, ... and 318i.
  • the multiple Rs are expressed as R318.
  • the multiple Rs are expressed as R318a, 318b, ... and 318i, etc.
  • Each of the multiple R318 is electrically connected to the IP core and the signal bus 340.
  • Each of the multiple R318 includes multiple switches, and can control the data transmission/reception path to each IP core connected in a network shape based on the address.
  • the semiconductor module 10 can transmit and receive data to a desired IP core among the IP cores connected in a network shape by controlling the multiple switches of the multiple R318.
  • the semiconductor module 10 can change the placement and address of R318 without depending on the placement of the IP core by controlling the data transmission/reception path to the IP core using R318, so that the data transmission/reception path can be flexibly set.
  • R318 can also function as a repeater (also called a bus buffer) that aggregates multiple signal buses 340 and appropriately divides the routed signal buses 340. Therefore, the semiconductor module 10 can suppress the concentration of multiple signal buses 340. As a result, for example, the degree of freedom in the position of R318 is improved, and restrictions on the placement of IP cores connected to R318 can be relaxed.
  • a repeater also called a bus buffer
  • DRAMIO311 has the function of transmitting and receiving signals between the DRAM chip and the logic chip 200, for example.
  • the PCIeIF 315 is an interface that complies with the serial bus standard used, for example, to connect expansion cards within a computer.
  • the PCIeIF 315 has the ability to transfer data at high speed with, for example, a CPU, memory, and storage connected to an expansion card installed in the computer.
  • the EIF 316 is an interface that has the function of connecting the semiconductor module 10 and all devices (computers, printers, etc.) that communicate via the network to a network medium (cable).
  • the external IO may include, for example, NI317, and may be electrically connected to R318 via NI317.
  • the external IO is electrically connected to the semiconductor cube 100 and an external circuit (not shown, for example, a power supply circuit) via R318, and has the function of transmitting and receiving signals between the external circuit and the semiconductor cube 100.
  • the memory controller 319 includes, for example, NI317.
  • the memory controller 319 is electrically connected to R318 via NI317.
  • the memory controller 319 is also connected to the semiconductor cube 100 via R318, and has the function of controlling the SRAM chip 110.
  • Each of the multiple logic modules 211 has a function for controlling the transmission of signals (data) to the TCI-IO 212, or the reception of signals (data) from the TCI-IO 212. More specifically, it has a function for controlling the transmission of signals (data) to the semiconductor cube 100, the TCI router chip 300, the memory controller 319, the PCIe IF 315, the EIF 214, and the multiple R218, or the reception of signals (data) from the semiconductor cube 100, the TCI router chip 300, the memory controller 319, the PCIe IF 315, the EIF 214, and the multiple R218.
  • the logic module 211 has a function for driving the memory module 111 (FIG. 9) in the SRAM chip 110. For example, the logic module 211 transmits a signal for driving the memory module 111 via the TCI-IO 212.
  • the logic module 211 may include, for example, an arithmetic circuit such as a CPU (Central Processing Unit).
  • each of the multiple logic modules 211 has a function for controlling the transmission of signals (data) to the multiple TCI-IOs 312 and SRAM chips 110 in the semiconductor cube 100, the multiple TCI-IOs 312, DRAMIO 311, PCIe IF 315, EIF 316, memory controller 319, and multiple R318 in the TCI router chip 300, or the reception of signals (data) from the multiple TCI-IOs 312 and SRAM chips 110 in the semiconductor cube 100, the multiple TCI-IOs 312, DRAMIO 311, PCIe IF 315, EIF 316, memory controller 319, and multiple R318 in the TCI router chip 300.
  • each circuit in the TCI router chip 300 is connected in a network via a network router (Router(R)), and each circuit in the semiconductor cube 100 and each circuit in the TCI router chip 300 are connected using inductor communication.
  • the semiconductor module 10 is a so-called network on chip (NoC) in which multiple IP cores are connected in a network, and is a module capable of communication using NoC and inductor communication.
  • NoC network on chip
  • R318h connected to the memory controller 319 is connected to R318g, R318e, and R318i in the TCI router chip 300. That is, the memory controller 319 connected to R318h is electrically connected to the DRAMIO 311 connected to R318g, the TCI-IO 312e connected to R318e, and the EIF 316 connected to R318i via the signal bus 340.
  • the TCI-IO 312e is connected to the logic chip 200 in the semiconductor cube 100 using the inductor 372.
  • the TCI-IO 312e communicates with the TCI-IO 212 via the inductor 372 and the inductor 272, and is connected to the logic chip 200 (logic module 211) and the SRAM chip 110 corresponding to the communicated inductor 272 (TCI-IO 212).
  • the memory controller 319 sends a signal for driving the SRAM chip 110 to the TCI-IO 312e via R318h and R318e, and the TCI-IO 312e communicates with the inductor 272 in the semiconductor cube 100 using the inductor 372, and can send a signal for driving the logic chip 200 (logic module 211) and the SRAM chip 110 corresponding to the communicated inductor 272 (TCI-IO 212) to the logic module 211.
  • the semiconductor module 10 includes a TCI router chip 300 in which routers connected to each of a number of IP cores are connected in a network using a signal bus, and communication is possible using a network-type bus.
  • the semiconductor module 10 is configured by stacking a plurality of sub-semiconductor cubes 101 including a TCI router chip 300 capable of communicating using a network-type bus and a logic chip 200 and an SRAM chip 110 closely joined together, and can connect the semiconductor cube 100 suspended from the TCI router chip 300 using inductor communication.
  • the semiconductor module 10 has excellent heat dissipation characteristics and can reduce power consumption, and can three-dimensionally connect each IP core, logic chip 200, and SRAM chip 110 in the TCI router chip 300, thereby reducing signal transmission delays between each IP core, logic chip 200, and SRAM chip 110 in the TCI router chip 300.
  • Fig. 6 is a schematic diagram showing the configuration of the logic chip 200.
  • Fig. 7 is a perspective view showing the configuration of the logic chip 200.
  • Fig. 8 is a cross-sectional view showing the schematic cross-sectional structure of the logic chip 200 taken along line A1-A2 shown in Fig. 6.
  • Fig. 9 is a schematic diagram showing the configuration of the SRAM chip 110.
  • Fig. 10 is a perspective view showing the configuration of the SRAM chip.
  • Fig. 11 is a cross-sectional view showing the cross-sectional structure of the SRAM chip taken along line B1-B2 shown in Fig. 9. Configurations that are the same as or similar to those in Figs. 1 to 5 will be explained as necessary.
  • the semiconductor cube 100 includes a sub-semiconductor cube 101 in which a logic chip 200 and an SRAM chip 110 electrically connected to the logic chip 200 are stacked in the D1 direction.
  • the second side 146 is in contact with the adhesive layer 400 and faces the second surface 304 of the TCI router chip 300, and the semiconductor cube 100 is disposed on the second surface 304 of the TCI router chip 300.
  • the logic chip 200 includes a plurality of logic modules 211, a plurality of TCI-IOs 212, a power supply wiring 264, and a ground wiring 265.
  • Each of the plurality of TCI-IOs 212 includes a plurality of inductor groups 271, and the inductor groups 271 include a plurality of inductors 272.
  • the multiple logic modules 211 and multiple TCI-IOs 212 are electrically connected to a power supply wiring 264 and a ground wiring 265.
  • the power supply wiring 264 and the ground wiring 265 are electrically connected to, for example, an external circuit (not shown), and are supplied with a power supply voltage VDD and a voltage VSS, etc.
  • the power supply voltage VDD is, for example, 1 V, 3 V, etc.
  • the voltage VSS is, for example, a ground voltage, 0 V, etc.
  • each of the multiple logic chips 200 includes, for example, a transistor layer 230, a wiring layer 250, and an inductor layer 270.
  • Each of the multiple logic chips 200 includes, for example, a logic chip 200n (see FIG. 3(A)) and a logic chip 200n+1 (see FIG. 3(A)) adjacent to the logic chip 200n.
  • logic chip 200 includes a first surface 202 parallel to directions D2 and D3, and a second surface 204 opposite to first surface 202 in direction D1.
  • First surface 202 is the exposed surface of transistor layer 230.
  • Second surface 204 is the exposed surface of inductor layer 270.
  • First surface 202 and second surface 204 are parallel to first surface 142 and second surface 144.
  • the logic chip 200 also includes a first side 205 perpendicular to the first surface 202 and the second surface 204, a second side 206 adjacent to the first side 205, a third side 207 adjacent to the second side 206, and a fourth side 208 adjacent to the third side 207 and the first side 205.
  • the first side 205 is part of the first side 145
  • the second side 206 is part of the second side 146
  • the third side 207 is part of the third side 147
  • the fourth side 208 is part of the fourth side 148.
  • a portion of the power supply wiring 264 and a portion of the ground wiring 265 are exposed, for example, on the first side 205, the second side 206, or the third side 207, and are electrically connected to side wiring that is electrically connected to an external circuit.
  • the power supply voltage VDD and the voltage VSS are supplied to a portion of the power supply wiring 264 and a portion of the ground wiring 265 via the external circuit and the power side wiring.
  • the side wiring can be formed by adopting technology used in the technical field of semiconductor modules.
  • the inductor layer 270 includes a plurality of inductor groups 271.
  • Each of the plurality of inductor groups 271 includes a plurality of inductors 272.
  • the plurality of inductor groups 271 are arranged perpendicular to the D2 direction and the D3 direction (i.e., the first surface 202 and the second surface 204) and parallel to the D3 direction.
  • Each of the plurality of inductor groups 271 is arranged away from the fourth side surface 208 and close to the second side surface 206 (second side surface 146), and is arranged extending in the D2 direction.
  • the number of inductors 272 shown in FIG. 7 is three, the number of inductors 272 shown in FIG. 7 is an example. The number of inductors 272 can be changed as appropriate depending on the specifications and applications of the semiconductor module 10.
  • the multiple inductors 272 include, for example, an inductor having a data communication (data transmission) function and an inductor having a clock communication (clock transmission) function.
  • Each inductor 272 may perform inductor communication with its one-to-one corresponding inductor 372 in response to (synchronized with) a clock received by clock communication, or each inductor 272 may perform inductor communication with its one-to-one corresponding inductor 372 asynchronously with the clock received by clock communication.
  • each inductor 272 may perform inductor communication with its one-to-one corresponding inductor 372 asynchronously with clock communication.
  • the transistor layer 230 includes, for example, a substrate 273, wiring 263, through electrodes 260, through electrodes 294, through electrodes 295, insulating layer 274, fins 267, wiring 266, active regions 284, gate insulating film 275, gate electrodes 276, N-type transistors 268, P-type transistors 269, and insulating layer 277.
  • the substrate 273 is, for example, an N-type Si substrate or an N-type Si-wafer.
  • the logic chip 200 may be formed, for example, by a 2 nm CMOS process and configured using fin-type transistors as shown in FIG. 8, or may be formed by a CMOS process other than 2 nm and configured using transistors other than fin-type transistors.
  • the structure of the transistors of the logic chip 200 may be appropriately selected depending on the specifications and applications of the semiconductor module 10.
  • the through electrodes 260, 294, and 295 are electrically connected to wiring 263, which is a so-called embedded wiring, and a part of the through electrodes 260, 294, and 295 are exposed to the first surface 202. A part of the through electrodes 260, 294, and 295 are electrically connected to the through electrodes 160 exposed to the first surface 102 of the SRAM chip 110. Signals (data), power supply voltage VDD, voltage VSS, etc. are supplied from an external circuit to the through electrodes 360, 394, and 395 via the logic chip 200 (e.g., wiring 280).
  • the wiring layer 250 includes a multi-layer wiring structure in which wiring and insulating layers are alternately stacked.
  • the wiring layer 250 includes, for example, wiring 278, insulating layer 279, wiring 280, and insulating layer 281.
  • the number of layers of the multi-layer wiring in the wiring layer 250 is not limited to the two layers shown in FIG. 8.
  • the number of layers of the multi-layer wiring in the wiring layer 250 may be three or more layers.
  • the number of layers of the multi-layer wiring in the wiring layer 250 can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10.
  • the inductor layer 270 includes, for example, an insulating layer 282 and a plurality of inductors 272.
  • the inductor layer 270 also includes a plurality of inductor groups 271.
  • Wiring 263 is a so-called buried electrode.
  • Wiring 278 and wiring 266 are connected to an external circuit, for example, via the side wiring described above, and signals (data), power supply voltage VDD, voltage VSS, etc. are supplied to wiring 263 via the side wiring, wiring 278, and wiring 266.
  • Wiring 278 and wiring 280 have, for example, a damascene structure, and wiring 266 has, for example, a structure equivalent to a through electrode.
  • Inductor 272 is connected to wiring 280, which is connected to wiring 278.
  • wiring 278 is electrically connected to the source electrode or drain electrode of N-type transistor 268, the source electrode or drain electrode of P-type transistor 269, gate electrode 276, and the like.
  • a signal (data) received by inductor 272 is transmitted to N-type transistor 268, P-type transistor 269, and the like via wiring 280 and wiring 278.
  • a signal (data) including the result of a logical operation is transmitted to inductor 272 via N-type transistor 268, P-type transistor 269, wiring 280, and wiring 278.
  • the SRAM chip 110 includes multiple memory modules 111, power supply wiring 164, and ground wiring 165.
  • Each of the multiple memory modules 111 includes a memory cell array 115.
  • the memory module 111 has functions for controlling, for example, the generation of a large number of signals (data) to be transmitted, the control of a large number of signals (data) received, the storage of signals (data) in the memory cell array 115, the reading of signals (data) from the memory cell array 115, the transmission of signals (data) to the logic chip 200, or the reception of signals (data) from the logic chip 200.
  • the memory cell array 115 includes a plurality of memory cells (not shown). Each of the plurality of memory cell arrays 115 is, for example, an SRAM, and each of the plurality of memory cells is an SRAM cell.
  • the SRAM, the SRAM cell, and the memory module 111 for SRAM can employ technology used in the technical field of SRAM. Therefore, a detailed description is omitted here.
  • the multiple memory modules 111 are electrically connected to power supply wiring 164 and ground wiring 165.
  • the power supply wiring 164 and ground wiring 165 are electrically connected to, for example, an external circuit (not shown), and are supplied with a power supply voltage VDD and a voltage VSS, etc.
  • the power supply voltage VDD is, for example, 1 V, 3 V, etc.
  • the voltage VSS is, for example, a ground voltage, 0 V, etc.
  • each of the multiple SRAM chips 110 includes, for example, a transistor layer 130 and a wiring layer 150.
  • Each of the multiple SRAM chips 110 includes, for example, an SRAM chip 110n (not shown) and an SRAM chip 110n+1 (not shown) adjacent to the SRAM chip 110n.
  • the SRAM chip 110 includes a first surface 102 parallel to the D2 and D3 directions, and a second surface 104 on the opposite side of the first surface 102 in the D1 direction.
  • the first surface 102 is the exposed surface of the transistor layer 130.
  • the second surface 104 is the exposed surface of the wiring layer 150.
  • the first surface 102 and the second surface 104 are parallel to the first surface 142 and the second surface 144.
  • the SRAM chip 110 also includes a first side 105 perpendicular to the first face 102 and the second face 104, a second side 106 adjacent to the first side 105, a third side 107 adjacent to the second side 106, and a fourth side 108 adjacent to the third side 107 and the first side 105.
  • the first side 105 is part of the first side 145
  • the second side 106 is part of the second side 146
  • the third side 107 is part of the third side 147
  • the fourth side 108 is part of the fourth side 148.
  • a portion of the power supply wiring 164 and a portion of the ground wiring 165 are exposed, for example, on the first side 105, the second side 106, or the third side 107, and are electrically connected to side wiring that is electrically connected to an external circuit.
  • the power supply voltage VDD and the voltage VSS are supplied to a portion of the power supply wiring 164 and a portion of the ground wiring 165 via the external circuit and the power side wiring.
  • the side wiring can be formed by adopting technology used in the technical field of semiconductor modules.
  • the transistor layer 130 includes, for example, a substrate 173, a wiring 163, a through electrode 160, an insulating layer 174, a fin 167, a wiring 166, an activation region 184, a gate insulating film 175, a gate electrode 176, an N-type transistor 168, a P-type transistor 169, and an insulating layer 177.
  • the wiring layer 150 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked.
  • the wiring layer 150 includes, for example, a wiring 178, an insulating layer 179, a wiring 180, an insulating layer 181, and an insulating layer 182.
  • substrate 173, wiring 163, through electrode 160, insulating layer 174, fin 167, wiring 166, activation region 184, gate insulating film 175, gate electrode 176, N-type transistor 168, P-type transistor 169, insulating layer 177, wiring 178, insulating layer 179, wiring 180, insulating layer 181, and insulating layer 182 are similar to the respective configurations and functions of substrate 273, wiring 263, through electrode 260, insulating layer 274, fin 267, wiring 266, activation region 284, gate insulating film 275, gate electrode 276, N-type transistor 268, P-type transistor 269, insulating layer 277, wiring 278, insulating layer 279, wiring 280, insulating layer 281, and insulating layer 282 described in the configuration and function of logic chip 200 in "1-2. Overview of semiconductor cube 100". Therefore, each layer and wiring that constitutes the transistor layer 130 and the wiring layer 150 will be described as necessary.
  • the through electrode 160 is electrically connected to the wiring 163, which is a so-called embedded electrode. A part of the through electrode 160 is exposed on the first surface 102. A part of the through electrode 160 is electrically connected to the through electrode 260, the through electrode 294, or the through electrode 295 exposed on the first surface 202 of the logic chip 200.
  • the wiring 178 and the wiring 166 are connected to an external circuit, for example, via the side wiring described above, and signals (data), power supply voltage VDD, voltage VSS, etc. are supplied to the wiring 163 via the side wiring, the wiring 178, and the wiring 166.
  • the wiring 178 and the wiring 180 have, for example, a damascene structure, and the wiring 166 has, for example, a structure equivalent to a through electrode.
  • FIG. 1 is a block diagram showing the configuration of the TCI router chip 300.
  • Figure 13 is a perspective view showing the configuration of the TCI router chip 300.
  • Figure 14 is a cross-sectional view showing an outline of the cross-sectional structure of the TCI router chip 300 taken along line C1-C2 shown in Figure 13. Configurations that are the same as or similar to those in Figures 1 to 11 will be described as necessary.
  • the TCI router chip 300 includes a configuration in which a transistor layer 330, a wiring layer 350, and an inductor layer 370 are stacked in this order in the D3 direction, and includes a first surface 302 parallel to the D1 and D2 directions, and a second surface 304 opposite the first surface 302.
  • the first surface 302 is the exposed surface of the transistor layer 330.
  • the second surface 304 is the exposed surface of the inductor layer 370.
  • the inductor layer 370 includes a plurality of inductor groups 371 (see FIG. 1).
  • the plurality of inductor groups 371 include a plurality of inductors 372.
  • the plurality of inductors 372 are arranged in a matrix in parallel to the D1 direction and the D2 direction (i.e., the first surface 302 and the second surface 304).
  • the transistor layer 330 includes, for example, a substrate 373, a wiring 363, a through electrode 360, a through electrode 394, a through electrode 395, an insulating layer 374, a fin 367, a wiring 366, an activation region 384, a gate insulating film 375, a gate electrode 376, an N-type transistor 368, a P-type transistor 369, and an insulating layer 377.
  • the wiring layer 350 includes a multilayer wiring structure in which wiring and insulating layers are alternately stacked.
  • the wiring layer 350 includes, for example, a wiring 378, an insulating layer 379, a wiring 380, and an insulating layer 381.
  • the inductor layer 370 includes, for example, an insulating layer 382 and a plurality of inductors 372.
  • substrate 373, wiring 363, insulating layer 374, fin 367, wiring 366, active region 384, gate insulating film 375, gate electrode 376, N-type transistor 368, P-type transistor 369, insulating layer 377, wiring 378, insulating layer 379, wiring 380, insulating layer 381, insulating layer 382, and inductor 372 are similar to the respective configurations and functions of substrate 173, wiring 163, insulating layer 174, fin 167, wiring 166, active region 184, gate insulating film 175, gate electrode 176, N-type transistor 168, P-type transistor 169, insulating layer 177, wiring 178, insulating layer 179, wiring 180, insulating layer 181, insulating layer 182, and inductor 172 described in "1-2. Overview of Semiconductor Cube 100". Therefore, the layers and wiring that make up the transistor layer 330, wiring layer 350, and inductor layer 370 will be described as necessary.
  • the through electrodes 360, 394, and 395 are electrically connected to the wiring 363, which is a so-called embedded wiring, and a part of the through electrodes 360, 394, and 395 are exposed to the first surface 302. A part of the through electrodes 360, 394, and 395 are each electrically connected to a through electrode 609 exposed to the first surface 602 of the package substrate 600 via the bump 502 of the bump layer 500. Signals (data), power supply voltage VDD, voltage VSS, etc. are supplied to the through electrodes 360, 394, and 395 from an external circuit via the bump layer 700, the package substrate 600, and the bump layer 500.
  • the TCI router chip 300 includes, for example, a plurality of TCI-IOs 312, a plurality of R318s, a DRAMIO 311, a PCIe IF 315, an EIF 316, and a memory controller 319.
  • the plurality of TCI-IOs 312 include TCI-IOs 312a to 312e and TCI-IO 312j
  • the plurality of R318s include R318a to R318j.
  • Each of the plurality of TCI-IOs 212 includes a plurality of inductor groups 371, and the inductor group 371 includes a plurality of inductors 372.
  • the configuration of the TCI router chip 300 shown in FIG. 12 is an example, and the configuration of the TCI router chip 300 is not limited to the example shown in FIG. 12.
  • the TCI router chip 300 may include IP cores other than those shown in FIG. 12.
  • the power supply wiring 364 is electrically connected to the through electrode 394
  • the ground wiring 365 is electrically connected to the through electrode 395
  • the signal bus 340 is electrically connected to the through electrode 360.
  • the TCI router chip 300 includes, as an example, one through electrode 394 and one through electrode 395, and includes one system of power supply wiring 364 and one system of ground wiring 365.
  • the TCI router chip 300 includes, as an example, two through electrodes 360 and three systems of signal buses 340.
  • the number of through electrodes 394, through electrodes 395, and through electrodes 360 included in the TCI router chip 300, and the number of systems of power supply wiring 364, ground wiring 365, and signal bus 340 are not limited to the example shown in FIG. 14 or FIG. 5.
  • the TCI router chip 300 may include two or more through electrodes 394, 395, and 360, and may include two or more power supply wiring 364, ground wiring 365, and signal bus 340.
  • the number of through electrodes 394, 395, and 360 included in the TCI router chip 300, and the number of power supply wiring 364, ground wiring 365, and signal bus 340 systems can be changed as appropriate depending on the specifications and applications of the semiconductor module 10.
  • the multiple inductors 372 are arranged in a matrix in the D1 and D2 directions on the second surface 304 side.
  • each inductor 372 may perform inductor communication with its one-to-one corresponding inductor 172 in response to (synchronized with) a clock received by clock communication, or may perform inductor communication with its one-to-one corresponding inductor 172 asynchronously (not synchronized with) the clock received by clock communication.
  • the semiconductor module 10 includes the TCI router chip 300.
  • the TCI router chip 300 functions as a router that connects various IP cores, including the logic chip 200 and memory chips (SRAM chip 110, DRAM chip 110A described below, NVM chip 110B, SRAM chip 110C, and DRAM chip 110D), to a network.
  • the semiconductor module 10 including the TCI router chip 300 can package multiple IP cores, which were previously mounted in parallel on a package substrate, into one. As a result, the semiconductor module 10 can suppress signal transmission delays and increases in chip power consumption associated with the length or load (capacity) of the wiring. In other words, the semiconductor module 10 is a module that enables reduction in signal transmission delays and power consumption.
  • each of the multiple logic chips 200 does not need to include an IP core related to a communication interface such as PCIeIF or EIF.
  • a conventional semiconductor module not including the TCI router chip 300 includes four logic chips
  • each of the four logic chips includes an IP core related to a communication interface, which causes a problem that the area of the semiconductor module is large and the manufacturing cost of the semiconductor module is high.
  • the semiconductor module 10 includes four logic chips
  • the four logic chips share the TCI router chip 300, and each of the four logic chips can be selectively connected to a communication interface.
  • the semiconductor module 10 can reduce the area and the manufacturing cost compared to conventional semiconductor modules.
  • Fig. 15 is a cross-sectional view showing an outline of the configuration of the semiconductor module 10A.
  • Fig. 16 is a schematic diagram showing the configurations of the semiconductor cube 100A and the TCI router chip 300A included in the semiconductor module 10A.
  • Fig. 17 is a cross-sectional view showing an outline of the cross-sectional structure of the DRAM chip 110A.
  • Fig. 18 is a cross-sectional view showing an outline of the cross-sectional structure of the NVM chip 110B. Configurations that are the same as or similar to those in Figs. 1 to 14 will be described as necessary.
  • the semiconductor module 10A includes a semiconductor cube 100A, a TCI router chip 300A, and an adhesive layer 400.
  • the stack 20A is composed of the semiconductor cube 100A, the TCI router chip 300A, and the adhesive layer 400.
  • the semiconductor module 10A may include a bump layer 500, a package substrate 600, and a bump layer 700.
  • the semiconductor module 10A includes a configuration in which the semiconductor cube 100 and the TCI router chip 300 of the semiconductor module 10 are replaced with the semiconductor cube 100A and the TCI router chip 300A.
  • the configuration of the semiconductor module 10A other than the semiconductor cube 100A and the TCI router chip 300A is the same as that of the semiconductor module 10. In the description of the semiconductor module 10A, configurations similar to those of the semiconductor module 10 will be described as necessary.
  • the semiconductor cube 100A includes a sub-semiconductor cube 101, multiple DRAM chips 110A, and multiple NVM (Non Volatile Memory) chips 110B.
  • the sub-semiconductor cube 101 has the configuration and functions described in “1-1-1. Overall configuration of semiconductor module 10", “1-1-2. Overview of inductor 272 and inductor 372", “1-1-3. Circuit configuration of semiconductor module 10", and “1-2. Overview of semiconductor cube 100", and will be described as necessary.
  • Each of the multiple DRAM chips 110A has a similar configuration including a first surface 102A, which is the exposed surface of the DRAM chip 110A, a second surface 104A, which is the exposed surface of the DRAM chip 110A opposite the first surface 102A, and multiple inductors 172A (third inductors).
  • the multiple DRAM chips 110A include two DRAM chips 110A, and the second surface 104A of one DRAM chip 110A and the first surface 102A of the other DRAM chip 110A are bonded using fusion bonding.
  • Each of the multiple NVM chips 110B has a similar configuration including a first surface 102B which is the exposed surface of the NVM chip 110B, a second surface 104B which is the exposed surface of the NVM chip 110B opposite the first surface 102B, and multiple inductors 172B (third inductors).
  • the multiple NVM chips 110B include two NVM chips 110B, and the second surface 104B of one NVM chip and the first surface 102B of the other NVM chip 110B are bonded using fusion bonding.
  • the sub-semiconductor cube 101, the multiple NVM chips 110B, and the multiple DRAM chips 110A are stacked in this order in the D1 direction. More specifically, the second surface 104 of the SRAM chip 110 and the first surface 102B of one of the NVM chips 110B are bonded using fusion bonding, and the second surface 104B of the other NVM chip 110B and the first surface 102B of one of the DRAM chips 110A are bonded using fusion bonding.
  • the number of sub-semiconductor cubes 101, multiple NVM chips 110B, and multiple DRAM chips 110A, the stacking order, and the bonded surfaces are shown in the semiconductor cube 100A, but are not limited to the example shown here.
  • the number of sub-semiconductor cubes 101 and each chip, the stacking order, and the bonded surfaces can be changed as appropriate depending on the specifications and applications of the semiconductor module 10A.
  • the DRAM chip 110A includes multiple TCI-IOs 112 and multiple DRAM modules 111A.
  • the multiple TCI-IOs 112 included in the DRAM chip 110A are electrically connected to the DRAM module 111A.
  • the DRAM chip 110A includes multiple TCI-IOs 112, in FIG. 16, the number of TCI-IOs 112 in the DRAM chip 110A is reduced to one for clarity of illustration.
  • DRAM module 111A includes a memory cell array, similar to memory module 111.
  • the memory cell array included in DRAM module 111A is a DRAM including a plurality of DRAM cells.
  • DRAM module 111A can employ technology used in the technical field of DRAM. Therefore, a detailed description will be omitted here.
  • the DRAM module 111A has functions for controlling, for example, a large number of signals (data) including received programs, storing the signals (data) in a memory cell array, reading out a large number of signals (data) including programs from the memory cell array, transmitting a large number of signals (data) including programs to the logic chip 200, or receiving signals (data) from the logic chip 200.
  • Inductor 172A has the same function and configuration as inductor 272. Inductor 172A has the function of non-contact inductor communication with inductor 372 of TCI router chip 300.
  • the NVM chip 110B includes multiple TCI-IOs 112 and multiple NVM modules 111B.
  • the multiple TCI-IOs 112 (parallel-serial conversion circuits 113) included in the NVM chip 110B are electrically connected to the NVM module 111B.
  • the NVM chip 110B includes multiple TCI-IOs 112, but in FIG. 16, the number of TCI-IOs 112 in the NVM chip 110B is reduced to one for clarity of illustration.
  • the TCI-IO 112 included in the NVM chip 110B has the same configuration and function as the TCI-IO 112 included in the DRAM chip 110A, and will be described as necessary.
  • the inductor 172B included in the NVM chip 110B is given a different reference number from the inductor 172A to distinguish it from the inductor 172B included in the DRAM chip 110A, but the configuration and function of the inductor 172B are the same as those of the inductor 172A, and will be described as necessary.
  • NVM module 111B includes a memory cell array, similar to memory module 111.
  • the memory cell array included in NVM module 111B is an NVM that includes a plurality of NVM cells.
  • NVM module 111B can employ technology used in the technical field of NVM. Therefore, a detailed description will be omitted here.
  • NVM module 111B includes, for example, a function to read a large number of signals (data) from the memory cell array and transmit the large number of signals (data), as well as a function to store the large number of received signals in the memory cell array.
  • Inductor 172A has the same function and configuration as inductor 272. Inductor 172A has the function of non-contact inductor communication with inductor 372 of TCI router chip 300.
  • the TCI router chip 300A includes a configuration in which an NVM controller 319B and R318j are added to the configuration of the TCI router chip 300.
  • the configuration of the TCI router chip 300A other than the configuration in which the NVM controller 319B and R318j are added is the same as that of the semiconductor module 10.
  • the NVM controller 319B is electrically connected to R318j.
  • R318j is electrically connected to R318i and R318h, for example, using a plurality of signal buses 340.
  • the NVM controllers 319B and R318j are, for example, IP cores.
  • the NVM controller 319B includes an NI317, similar to the memory controller 319. Note that the NVM controller 319B may not include an NI317, and the NI317 may be located outside the NVM controller 319B, with the NVM controller 319B being electrically connected to the R318 via the NI317.
  • the NVM controller 319B is connected to the logic module 211 via R318j, TCI-IO312 (inductor 372), and TCI-IO212 (inductor 272).
  • the NVM controller 319B is also connected to the NVM module 111B via R318j, TCI-IO312 (inductor 372), and TCI-IO112 (inductor 172B).
  • the NVM controller 319B has the function of transmitting and receiving signals to and from the logic module 211 and NVM module 111B using inductor communication.
  • the memory controller 319 of the semiconductor module 10A includes, for example, a function to control the SRAM chip 110 and a function to control the DRAM.
  • the memory controller 319 may be connected to R318g, which is connected to the DRAMIO 311, via R318h.
  • the memory controller 319 is connected to the logic module 211 via R318h, R318g, the DRAMIO 311, the TCI-IO 312 (inductor 372), and the TCI-IO 212 (inductor 272).
  • the memory controller 319 is also connected to the DRAM module 111A via R318h, R318g, the DRAMIO 311, the TCI-IO 312 (inductor 372), and the TCI-IO 212 (inductor 272). That is, the memory controller 319 has a function to transmit and receive signals to and from the logic module 211 and the DRAM module 111A using inductor communication.
  • Semiconductor module 10A can achieve the same effects as semiconductor module 10.
  • semiconductor module 10A has better thermal conductivity and heat dissipation characteristics than conventional semiconductor modules, and can transmit signals including large-capacity programs and store large-capacity signals (data) non-volatilely at high speed with low power consumption.
  • the multiple TCI-IOs 312 include multiple inductors 372.
  • the multiple inductors 372 may be arranged in groups for inductors communicating with the logic chip 200, inductors communicating with the NVM chip 110B, and inductors communicating with the DRAM chip 110A.
  • the multiple inductors 372 included in the TCI-IO 312a that communicates with the logic chip 200 may be arranged in groups
  • the multiple inductors 372 included in the TCI-IOs 312d and 312e that communicate with the NVM chip 110B may be arranged in groups
  • the multiple inductors 372 included in the TCI-IOs 312b and 312c that communicate with the DRAM chip 110A may be arranged in groups.
  • the DRAM chip 110A includes a first surface 102A parallel to the D2 and D3 directions, and a second surface 104A opposite the first surface 102A in the D1 direction.
  • the first surface 102A is the exposed surface of the transistor layer 130A.
  • the second surface 104A is the exposed surface of the inductor layer 170A.
  • the first surface 102A and the second surface 104A are parallel to the first surface 142A and the second surface 144A.
  • the DRAM chip 110A includes a transistor layer 130A, a wiring layer 150A, and an inductor layer 170A.
  • the transistor layer 130A does not include a through electrode 160. That is, the transistor layer 130A includes a substrate 173, a wiring 163, an insulating layer 174, a fin 167, a wiring 166, an active region 184, a gate insulating film 175, a gate electrode 176, an N-type transistor 168, a P-type transistor 169, and an insulating layer 177.
  • wiring layer 150A does not include insulating layer 182. That is, wiring layer 150A includes wiring 178, insulating layer 179, wiring 180, and insulating layer 181.
  • the inductor layer 170A includes an insulating layer 182 and an inductor 172A.
  • the NVM chip 110B includes a first surface 102B parallel to the D2 and D3 directions, and a second surface 104B opposite the first surface 102B in the D1 direction.
  • the first surface 102B is the exposed surface of the transistor layer 130B.
  • the second surface 104B is the exposed surface of the inductor layer 170B.
  • the first surface 102B and the second surface 104B are parallel to the first surface 142A and the second surface 144A.
  • NVM chip 110B includes transistor layer 130B, wiring layer 150B, and inductor layer 170B.
  • the transistor layer 130B does not include a through electrode 160. That is, the transistor layer 130B includes a substrate 173, a wiring 163, an insulating layer 174, a fin 167, a wiring 166, an active region 184, a gate insulating film 175, a gate electrode 176, an N-type transistor 168, a P-type transistor 169, and an insulating layer 177.
  • wiring layer 150B does not include insulating layer 182. That is, wiring layer 150B includes wiring 178, insulating layer 179, wiring 180, and insulating layer 181.
  • the inductor layer 170B includes an insulating layer 182 and an inductor 172B.
  • Figure 19 is a cross-sectional view showing an outline of the configuration of the semiconductor module 10B.
  • Figure 20 is a schematic diagram showing the configurations of the semiconductor cube 100A and the TCI router chip 300B included in the semiconductor module 10B. Configurations that are the same as or similar to those in Figures 1 to 18 will be described as necessary.
  • the semiconductor module 10B includes two semiconductor cubes 100A, a TCI router chip 300B, and an adhesive layer 400.
  • the semiconductor module 10B may include a bump layer 500, a package substrate 600, and a bump layer 700.
  • the semiconductor module 10B includes one more semiconductor cube 100A than the semiconductor module 10A.
  • the configuration of the semiconductor module 10B is the same as that of the semiconductor module 10A, except that the semiconductor module 10B includes one more semiconductor cube 100A than the semiconductor module 10A. In the description of the semiconductor module 10B, configurations similar to those of the semiconductor module 10A will be described as necessary.
  • Two semiconductor cubes 100A are spaced apart in the D1 direction, connected to the adhesive layer 400, and placed on the second surface 304 of the TCI router chip 300B.
  • the TCI router chip 300B includes a plurality of inductors 372.
  • the plurality of inductors 372 are arranged at positions corresponding to the inductors 172A, 172B, and 272 included in the two semiconductor cubes 100A.
  • the configuration and function of the TCI router chip 300B is similar to that of the TCI router chip 300A, except that the TCI router chip 300B includes inductors corresponding to the inductors of the two semiconductor cubes 100A.
  • the TCI router chip 300B is configured to be capable of inductor communication with two semiconductor cubes 100A.
  • the semiconductor module 10B includes two semiconductor cubes 100A, but the number of semiconductor cubes 100A included in the semiconductor module 10B is not limited to two. The number of semiconductor cubes 100A included in the semiconductor module 10B may be three or more. The number of semiconductor cubes 100A included in the semiconductor module 10B can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10B.
  • the semiconductor module 10B can achieve the same effects as the semiconductor module 10. Furthermore, by including two semiconductor cubes 100A, the semiconductor module 10B can be equipped with two logic chips 200 and various memory chips, and has a so-called multi-core function.
  • the semiconductor module 10B has better thermal conductivity and heat dissipation characteristics than conventional semiconductor modules, so it can process at least two programs in parallel with low power consumption, and can execute data processing at high speed with low power consumption.
  • FIG. 21 is a cross-sectional view showing an outline of the configuration of the semiconductor module 10C.
  • Figure 22 is a schematic diagram showing the configuration of a plurality of sub-semiconductor cubes 101 and a TCI router chip 300C included in the semiconductor module 10C. Configurations that are the same as or similar to those in Figures 1 to 20 will be described as necessary.
  • the semiconductor module 10C includes three sub-semiconductor cubes 101, a TCI router chip 300C, and an adhesive layer 400.
  • the semiconductor module 10C may include a bump layer 500, a package substrate 600, and a bump layer 700.
  • the semiconductor module 10C includes a configuration in which multiple sub-semiconductor cubes 101 in the semiconductor cube 100 are spaced apart from each other, as compared to the semiconductor module 10.
  • the configuration of the semiconductor module 10C is the same as that of the semiconductor module 10, except that the semiconductor module 10C includes a configuration in which multiple sub-semiconductor cubes 101 are spaced apart from each other. In the description of the semiconductor module 10C, configurations similar to those of the semiconductor module 10 will be described as necessary.
  • the three sub-semiconductor cubes 101 are spaced apart in the D1 direction, connected to the adhesive layer 400, and disposed on the second surface 304 of the TCI router chip 300C.
  • the TCI router chip 300C includes a plurality of inductors 372.
  • the plurality of inductors 372 are arranged at positions corresponding to the respective inductors 272 included in the three sub-semiconductor cubes 101.
  • the configuration and function of the TCI router chip 300C are similar to the configuration and function of the TCI router chip 300, except that the TCI router chip 300C includes inductors 372 corresponding to the respective inductors 272 included in the three sub-semiconductor cubes 101.
  • the TCI router chip 300C includes the same configuration and functions as the TCI router chip 300, and is configured to be capable of inductor communication with each of the three sub-semiconductor cubes 101.
  • the semiconductor module 10C includes three sub-semiconductor cubes 101 as an example, the number of the three sub-semiconductor cubes 101 included in the semiconductor module 10C is not limited to three. The number of the three sub-semiconductor cubes 101 included in the semiconductor module 10C may be two or more. The number of the three sub-semiconductor cubes 101 included in the semiconductor module 10C can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10C.
  • the semiconductor module 10C can achieve the same effects as the semiconductor module 10.
  • the semiconductor module 10C can increase the surface area of the semiconductor cube by arranging the three sub-semiconductor cubes 101 at a distance from each other. As a result, the semiconductor module 10C has better thermal conduction and heat dissipation characteristics than, for example, conventional semiconductor modules.
  • Figure 23 is a cross-sectional view showing an outline of the configuration of the semiconductor module 10D.
  • Figure 24 is a schematic diagram showing the configuration of the semiconductor cube 100B and the TCI router chip 300D included in the semiconductor module 10D.
  • Figure 25 is a cross-sectional view showing an outline of the cross-sectional structure of the SRAM chip 110C.
  • Figure 26 is a cross-sectional view showing an outline of the cross-sectional structure of the DRAM chip 110D. Configurations that are the same as or similar to those in Figures 1 to 22 will be described as necessary.
  • Semiconductor module 10D includes semiconductor cube 100B, TCI router chip 300D, and adhesive layer 400.
  • Semiconductor module 10D may include bump layer 500, package substrate 600, and bump layer 700.
  • Semiconductor module 10D includes a configuration in which semiconductor cube 100A and TCI router chip 300B of semiconductor module 10B are replaced with semiconductor cube 100B and TCI router chip 300D.
  • the configuration of semiconductor module 10D other than semiconductor cube 100B and TCI router chip 300D is the same as that of semiconductor module 10B. In the description of semiconductor module 10D, configurations similar to those of semiconductor module 10B will be described as necessary.
  • the semiconductor cube 100B includes a sub-semiconductor cube 101A and a number of DRAM chips 110D.
  • the semiconductor cube 100B includes a first surface 142D parallel to the D2 and D3 directions, and a second surface 144D that is opposite to the first surface 142D with respect to the D1 direction and parallel to the first surface 142D.
  • the semiconductor cube 100B also includes a second side surface 146D parallel to the D1 and D2 directions and perpendicularly adjacent to the first surface 142 and the second surface 144, and a fourth side surface 148D parallel to the second side surface 146D and perpendicularly adjacent to the first surface 142 and the second surface 144.
  • the second side surface 146D is in contact with the adhesive layer 400 and faces the second surface 304 of the TCI router chip 300D, and the semiconductor cube 100B is disposed on the second surface 304 of the TCI router chip 300D.
  • the sub-semiconductor cube 101A includes a configuration in which a logic chip 200 and an SRAM chip 110C are stacked in the D1 direction.
  • the logic chip 200 is electrically connected to the SRAM chip 110C.
  • the configuration and functions of the logic chip 200 are the same as those described in “1-1-1.
  • Overall configuration of the semiconductor module 10 "1-1-2. Overview of the inductor 272 and inductor 372", “1-1-3.
  • Circuit configuration of the semiconductor module 10 and “1-2. Overview of the semiconductor cube 100", and will be described as necessary.
  • the SRAM chip 110C differs from the SRAM chip 110 in terms of the inductor layer 170C (FIG. 25). Other aspects of the SRAM chip 110C are similar to the SRAM chip 110. Here, functions and configurations similar to those of the SRAM chip 110 will be described as necessary.
  • the SRAM chip 110C includes a first surface 102C, which is the exposed surface of the SRAM chip 110C, a second surface 104C, which is the exposed surface of the SRAM chip 110C opposite to the first surface 102C, a plurality of inductors 172 (fourth inductor), and a plurality of inductors 172C (fifth inductor).
  • the first surface 102C is a surface that faces and contacts the first surface 202 of the logic chip 200.
  • a plurality of through electrodes 160 are exposed on the first surface 102C and are bonded to the through electrodes 260 exposed on the first surface 202 of the logic chip 200 using fusion bonding.
  • the first surface 102C and the second surface 104C are parallel to the first surface 142D and the second surface 144D.
  • Each of the multiple DRAM chips 110D has a similar configuration including a first surface 102D, which is the exposed surface of the DRAM chip 110D, a second surface 104D, which is the exposed surface of the DRAM chip 110D opposite to the first surface 102D, multiple inductors 172AD (sixth inductor), and multiple inductors 172AU (seventh inductor).
  • the multiple DRAM chips 110D are stacked in the D1 direction.
  • the multiple DRAM chips 110D include three DRAM chips 110D, as an example.
  • the second surface 104D of the first DRAM chip 110D and the first surface 102D of the second DRAM chip 110D are bonded using fusion bonding, and the first surface 102D of the second DRAM chip 110D and the second surface 104D of the third DRAM chip 110D are bonded using fusion bonding.
  • the first surface 102D of the first DRAM chip 110D is bonded to the second surface 104C of the SRAM chip 110C using fusion bonding.
  • the number of sub-semiconductor cubes 101A and the multiple DRAM chips 110D, the stacking order, the bonded surfaces, etc. are merely examples and are not limited to the examples shown here.
  • the number of sub-semiconductor cubes 101A and the multiple DRAM chips 110D, the stacking order, the bonded surfaces, etc. can be changed as appropriate depending on the specifications, applications, etc. of the semiconductor module 10D.
  • the TCI router chip 300D is connected to multiple semiconductor cubes 100B using inductor communication. More specifically, the TCI router chip 300D is connected to multiple semiconductor cubes 100B via inductors 372, 172, and 272.
  • the SRAM chip 110C includes multiple TCI-IOs 112, multiple TCI-IOs 112A, a DRAMIO 311, and multiple memory modules 111.
  • the multiple memory modules 111, multiple TCI-IOs 112, and multiple TCI-IOs 112A included in the SRAM chip 110C are electrically connected to the DRAMIO 311.
  • the SRAM chip 110C includes multiple TCI-IOs 112, multiple TCI-IOs 112A, and multiple memory modules 111, but in FIG. 24, to clarify the drawing, the number of TCI-IOs 112, the number of multiple TCI-IOs 112A, and the number of memory modules 111 in the SRAM chip 110C are each reduced to one.
  • the memory module 111 includes the same configuration and functions as the memory module 111 described in "1-1-3. Circuit configuration of semiconductor module 10" and “1-2. Overview of semiconductor cube 100", and will be described as necessary.
  • the TCI-IO 112 includes the same configuration and functions as the TCI-IO 112 described in “Second embodiment”, and will be described as necessary.
  • the configuration and functions of the DRAMIO 311 are the same as the configuration and functions described in "1-1-3. Circuit configuration of semiconductor module 10", "1-3. Overview of TCI router chip 300", and “Second embodiment”, and will be described as necessary.
  • TCI-IO112A includes a configuration in which inductor 172 of TCI-IO112 is replaced with inductor 172C.
  • the rest of the configuration of TCI-IO112A is the same as that of TCI-IO112, and will be described as necessary.
  • the inductor 272 (FIG. 23) and inductor 172 included in the logic chip 200 have the function of non-contact inductor communication with the inductor 372 of the TCI router chip 300.
  • the inductor 172C differs from the inductor 172 in that it performs inductor communication with the inductor 172AD included in the DRAM chip 110D. In all other respects, the inductor 172C is similar to the inductor 172.
  • functions and configurations similar to those of the inductor 172 will be described as necessary.
  • the DRAM chip 110D includes multiple TCI-IOs 112B, multiple TCI-IOs 112C, and multiple DRAM modules 111C.
  • the multiple TCI-IOs 112B (parallel-serial conversion circuits 113) and multiple TCI-IOs 112C (parallel-serial conversion circuits 113) are electrically connected to the multiple DRAM modules 111C.
  • the DRAM chip 110D includes multiple TCI-IOs 112B, multiple TCI-IOs 112C, and multiple DRAM modules 111C, but in FIG. 24, similar to the SRAM chip 110C, the number of TCI-IOs 112B, TCI-IOs 112C, and DRAM modules 111C in the DRAM chip 110D is reduced to one each for clarity of illustration.
  • TCI-IO112B includes a configuration in which the inductor 172 of TCI-IO112 is replaced with inductor 172AD
  • TCI-IO112C includes a configuration in which the inductor 172 of TCI-IO112 is replaced with inductor 172AU.
  • the rest of the configuration of TCI-IO112B and TCI-IO112C is the same as that of TCI-IO112 and will be described as necessary.
  • the configuration and function of DRAM module 111C is the same as that of DRAM module 111A described in the "second embodiment" and will be described as necessary.
  • Inductor 172AD included in DRAM chip 110D differs from inductor 172 in that it communicates with inductor 172C included in the adjacent SRAM chip 110C or inductor 172AU included in the adjacent DRAM chip 110D.
  • Inductor 172AU included in DRAM chip 110D differs from inductor 172 in that it communicates with inductor 172AD included in the adjacent DRAM chip 110D.
  • inductor 172AD and inductor 172AU are similar to inductor 172.
  • functions and configurations similar to inductor 172 will be described as necessary.
  • the TCI router chip 300D includes a configuration in which the DRAMIO 311 in the TCI router chip 300 is replaced with a DRAM controller 319A.
  • the configuration of the TCI router chip 300D other than the DRAM controller 319A is the same as that of the TCI router chip 300.
  • the SRAM chip 110C includes a DRAMIO 311.
  • the DRAM controller 319A is electrically connected to R318g.
  • the DRAM controller 319A is, for example, an IP core.
  • the DRAM controller 319A includes an NI317, just like the memory controller 319. Note that the DRAM controller 319A may not include the NI317, and the NI317 may be located outside the DRAM controller 319A, with the DRAM controller 319A being electrically connected to R318 via the NI317.
  • the DRAM controller 319A is connected to the DRAMIO 311 and memory module 111 using inductor communication, for example, via R318g, R318b, TCI-IO 312b (inductor 372) and TCI-IO 112 (inductor 172).
  • the DRAMIO 311 and memory module 111 are connected to the DRAM module 111C using inductor communication, for example, via TCI-IO 112A (inductor 172C), TCI-IO 112B (inductor 172AD) and TCI-IO 112C (inductor 172AU).
  • the DRAM controller 319A is also electrically connected to the logic module 211 included in the logic chip 200, for example, via R318g, R318a and TCI-IO 312a (inductor 372) and TCI-IO 212 (inductor 272) included in the logic chip 200. That is, the DRAM controller 319A has the function of transmitting and receiving signals between the logic module 211 and the DRAM module 111A using inductor communication.
  • Semiconductor module 10D is configured such that both logic chip 200 and SRAM chip 110C are capable of inductor communication with TCI router chip 300D.
  • Semiconductor module 10D also includes a configuration in which SRAM chip 110C and DRAM chip 110D are capable of inductor communication, and a configuration in which adjacent chips among multiple DRAM chips 110D are capable of inductor communication.
  • Semiconductor module 10D can achieve the same effects as semiconductor module 10B.
  • the SRAM chip 110C includes a transistor layer 130C, a wiring layer 150C, and an inductor layer 170C.
  • the first surface 102C of the SRAM chip 110C is parallel to the D2 and D3 directions and is the exposed surface of the transistor layer 130C.
  • the second surface 104C of the SRAM chip 110C is parallel to the D2 and D3 directions and is the exposed surface of the inductor layer 170C.
  • the transistor layer 130C and the wiring layer 150C have the same configuration as the transistor layer 130 and the wiring layer 150.
  • the inductor layer 170C includes an insulating layer 182, an inductor 172, and an inductor 172C.
  • the inductor 172 and the inductor 172C are electrically connected to, for example, the wiring 180, the wiring 178, the wiring 166, the wiring 163, and the through electrode 160, respectively.
  • the SRAM chip 110C can transmit and receive signals (data) via the inductor 172 and the inductor 172C.
  • the DRAM chip 110D includes a transistor layer 130D, a wiring layer 150D, and an inductor layer 170D.
  • the first surface 102D of the DRAM chip 110D is parallel to the D2 and D3 directions and is the exposed surface of the transistor layer 130D.
  • the second surface 104D of the SRAM chip 110C is parallel to the D2 and D3 directions and is the exposed surface of the inductor layer 170D.
  • the first surface 102D and the second surface 104D are parallel to the first surface 142D and the second surface 144D.
  • a part of the wiring 163 functions as an inductor 172AD, as compared with the transistor layer 130A.
  • the other configurations of the transistor layer 130D are the same as those of the transistor layer 130A.
  • the wiring layer 150D includes the same configuration as that of the wiring layer 150A.
  • the inductor layer 170D is different from the inductor layer 170A in that the inductor 172A of the inductor layer 170A is replaced with an inductor 172AU.
  • the other configurations of the inductor layer 170D are the same as those of the inductor layer 170A. Therefore, descriptions of the layers and wirings constituting the transistor layer 130D, the wiring layer 150D, and the inductor layer 170D are omitted.
  • the various configurations of the semiconductor modules 10, 10A, 10B, 10C, and 10D illustrated as an embodiment of the present invention can be appropriately interchanged as long as they are not mutually inconsistent and do not deviate from the spirit of the present invention.
  • the various configurations of the semiconductor modules 10, 10A, 10B, 10C, and 10D illustrated as an embodiment of the present invention can be appropriately combined as long as they are not mutually inconsistent and do not deviate from the spirit of the present invention.
  • technical matters common to each embodiment are included in each embodiment even if not explicitly stated.
  • 10 semiconductor module
  • 20 stack, 100: semiconductor cube, 101: sub semiconductor cube, 102: first surface, 104: second surface, 105: first side, 106: second side, 107: third side, 108: fourth side, 110: SRAM chip, 111: memory module, 112: TCI-IO, 115: memory cell array, 130: transistor layer, 142: first surface, 144: second surface, 145: first side, 146: second side, 147: third side, 148: fourth side, 150: wiring layer, 160: through electrode, 163: wiring, 164: power supply wiring, 165: ground wiring, 166: wiring, 167: fin, 168: N-type transistor, 169: P-type transistor, 173: substrate plate, 174: insulating layer, 175: gate insulating film, 176: gate electrode, 177: insulating layer, 178: wiring, 179: insulating layer, 180: wiring, 181: insulating layer, 182: insulating layer, 184: active region

Landscapes

  • Semiconductor Integrated Circuits (AREA)
PCT/JP2024/018677 2023-06-20 2024-05-21 半導体モジュール Ceased WO2024262221A1 (ja)

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WO2021095083A1 (ja) * 2019-11-11 2021-05-20 ウルトラメモリ株式会社 半導体モジュール、ｄｉｍｍモジュール、及びそれらの製造方法
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JPH03501428A (ja) * 1987-10-20 1991-03-28 アーヴィン・センサーズ・コーポレーション 高密度電子モジュール及びその製造方法
JPH0766371A (ja) * 1993-08-19 1995-03-10 Internatl Business Mach Corp <Ibm> 垂直チップ・マウントのメモリ・パッケージ及びそれを製造する方法
US5786628A (en) * 1994-09-28 1998-07-28 International Business Machines Corporation Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging
US20140223068A1 (en) * 2005-09-26 2014-08-07 Rambus Inc. Memory System Topologies Including A Buffer Device And An Integrated Circuit Memory Device
WO2009148007A1 (ja) * 2008-06-03 2009-12-10 学校法人慶應義塾 電子回路
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