WO2024256943A1 - 半導体装置、及び半導体装置の作製方法 - Google Patents

半導体装置、及び半導体装置の作製方法 Download PDF

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Publication number
WO2024256943A1
WO2024256943A1 PCT/IB2024/055638 IB2024055638W WO2024256943A1 WO 2024256943 A1 WO2024256943 A1 WO 2024256943A1 IB 2024055638 W IB2024055638 W IB 2024055638W WO 2024256943 A1 WO2024256943 A1 WO 2024256943A1
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Prior art keywords
insulating layer
layer
conductive layer
region
semiconductor
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PCT/IB2024/055638
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English (en)
French (fr)
Japanese (ja)
Inventor
肥塚純一
黒崎大輔
神長正美
保本清治
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020257042150A priority Critical patent/KR20260025317A/ko
Priority to CN202480037820.XA priority patent/CN121286117A/zh
Priority to JP2025526884A priority patent/JPWO2024256943A1/ja
Publication of WO2024256943A1 publication Critical patent/WO2024256943A1/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/021—Manufacture or treatment of multiple TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/411—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by materials, geometry or structure of the substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/451—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs characterised by the compositions or shapes of the interlayer dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays

Definitions

  • One aspect of the present invention relates to a semiconductor device and a manufacturing method thereof.
  • One aspect of the present invention relates to a transistor and a manufacturing method thereof.
  • One aspect of the present invention relates to a display device having a semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of technical fields of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. Also, it refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Also, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices may themselves be semiconductor devices and each may have a semiconductor device.
  • transistors having transistors are widely used in electronic devices. For example, in display devices, pixel size can be reduced and resolution can be increased by reducing the area occupied by transistors. For this reason, there is a demand for miniaturized transistors.
  • Devices requiring high-definition display devices such as those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), are being actively developed.
  • VR virtual reality
  • AR augmented reality
  • SR substitute reality
  • MR mixed reality
  • display devices for example, light-emitting devices having organic EL (Electro Luminescence) elements or light-emitting diodes (LEDs: Light Emitting Diodes) have been developed.
  • organic EL Electro Luminescence
  • LEDs Light Emitting Diodes
  • Patent document 1 discloses a high-definition display device that uses organic EL elements.
  • One aspect of the present invention has an object to provide a semiconductor device having a fine-sized transistor. Another object is to provide a semiconductor device having a transistor with a short channel length. Another object is to provide a semiconductor device having a transistor with high on-state current. Another object is to provide a semiconductor device having a transistor with high field-effect mobility. Another object is to provide a semiconductor device having a transistor with good electrical characteristics. Another object is to provide a semiconductor device that operates at high speed. Another object is to provide a semiconductor device that occupies a small area. Another object is to provide a semiconductor device with low wiring resistance. Another object is to provide a semiconductor device or display device with low power consumption. Another object is to provide a highly reliable transistor, semiconductor device, or display device. Another object is to provide a high-definition display device. Another object is to provide a method for manufacturing a semiconductor device or display device with high productivity. Another object is to provide a new transistor, semiconductor device, or display device, or a manufacturing method thereof.
  • One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer.
  • the first insulating layer is located on the first conductive layer.
  • the first insulating layer has a first opening that reaches the first conductive layer.
  • the second conductive layer is located on the first insulating layer.
  • the second conductive layer has a second opening in a region overlapping with the first opening.
  • the semiconductor layer has a first region in contact with a top surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer in the first opening.
  • the second insulating layer is located on the semiconductor layer.
  • the third conductive layer has a region overlapping with the semiconductor layer via the second insulating layer.
  • the first region and the second insulating layer each include a first element.
  • the first element is boron or phosphorus.
  • the concentration of the first element in the second region is 1 ⁇ 10 ⁇ 3 times or less than the concentration of the first element in the first region.
  • An angle between a side surface of the first insulating layer and a top surface of the first conductive layer in the first opening is 66 degrees or more and 90 degrees or less.
  • the semiconductor layer preferably has a region in contact with a side surface of the second conductive layer in the second opening, and a third region in contact with an upper surface of the second conductive layer.
  • the third region preferably contains the first element.
  • the concentration of the first element in the second region is preferably 1 ⁇ 10 ⁇ 3 times or less than the concentration of the first element in the third region.
  • One embodiment of the present invention is a semiconductor device including a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer.
  • the first insulating layer is located on the first conductive layer.
  • the first insulating layer has a first opening that reaches the first conductive layer.
  • the second conductive layer is located on the first insulating layer.
  • the second conductive layer has a second opening in a region overlapping with the first opening.
  • the semiconductor layer has a first region in contact with a top surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer in the first opening.
  • the second insulating layer is located on the semiconductor layer.
  • the third conductive layer has a region overlapping with the semiconductor layer via the second insulating layer.
  • the first region and the second insulating layer each include a first element.
  • the first element is boron or phosphorus.
  • the concentration of the first element in the second region is 1 ⁇ 10 ⁇ 3 times or less than the concentration of the first element in the first region.
  • the thickness of the portion of the second insulating layer in contact with the second region is 2.5 times or more than the thickness of the portion of the second insulating layer in contact with the first region.
  • the semiconductor layer preferably has a region in contact with a side surface of the second conductive layer in the second opening, and a third region in contact with an upper surface of the second conductive layer.
  • the third region preferably contains the first element.
  • the thickness of the portion in contact with the second region of the second insulating layer in a direction perpendicular to the upper surface of the first conductive layer is preferably 2.5 times or more the thickness of the portion in contact with the third region of the second insulating layer.
  • the first region preferably has a second element.
  • the second element is preferably argon, krypton, or xenon.
  • the concentration of the second element in the first region is preferably higher than the concentration of the second element in the second region.
  • the semiconductor layer preferably contains a metal oxide.
  • the first insulating layer preferably has a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer.
  • the third insulating layer and the fifth insulating layer preferably each have silicon and nitrogen.
  • the fourth insulating layer preferably has silicon and oxygen.
  • the first insulating layer preferably has a third insulating layer, a fourth insulating layer on the third insulating layer, and a fifth insulating layer on the fourth insulating layer.
  • the third insulating layer preferably has silicon and nitrogen.
  • the fourth insulating layer preferably has silicon and oxygen.
  • the fifth insulating layer preferably has one or both of aluminum and hafnium, and oxygen.
  • One embodiment of the present invention is a method for manufacturing a semiconductor device, which includes forming a first conductive layer, forming a first insulating film on the first conductive layer, forming the first conductive film on the first insulating film, processing the first conductive film and the first insulating film, forming a first insulating layer having a first opening reaching the first conductive layer and forming a second conductive layer having a second opening overlapping the first opening, forming a semiconductor layer on the first conductive layer, the first insulating layer, and the second conductive layer, forming a second insulating layer on the semiconductor layer, supplying a first element to the semiconductor layer through the second insulating layer by using a plasma ion doping method or an ion implantation method, and forming a third conductive layer on the second insulating layer.
  • the first element is boron or phosphorus.
  • the semiconductor layer has a first region in contact with a top surface of the first conductive layer and a second region in contact with a side surface of the first insulating layer.
  • the first region and the second insulating layer each contain the first element.
  • Pa represented by the following formula (1) is 1 ⁇ 10 ⁇ 3 or less.
  • the method for manufacturing a semiconductor device described above it is preferable to supply a second element to the semiconductor layer through the second insulating layer by using a plasma ion doping method or an ion implantation method before supplying the first element.
  • the second element is preferably argon, krypton, or xenon.
  • a semiconductor device having a finely sized transistor can be provided.
  • a semiconductor device having a transistor with a short channel length can be provided.
  • a semiconductor device having a transistor with a large on-state current can be provided.
  • a semiconductor device having a transistor with high field-effect mobility can be provided.
  • a semiconductor device having a transistor with good electrical characteristics can be provided.
  • a semiconductor device that operates at high speed can be provided.
  • a semiconductor device that occupies a small area can be provided.
  • a semiconductor device with low wiring resistance can be provided.
  • a semiconductor device or display device with low power consumption can be provided.
  • a highly reliable transistor, semiconductor device, or display device can be provided.
  • a high-definition display device can be provided.
  • a method for manufacturing a semiconductor device or display device with high productivity can be provided.
  • a novel transistor, semiconductor device, display device, or a manufacturing method thereof can be provided.
  • Fig. 1A is a top view illustrating an example of a semiconductor device
  • Fig. 1B and Fig. 1C are cross-sectional views illustrating the example of the semiconductor device.
  • 2A to 2D are perspective views showing an example of a semiconductor device.
  • 3A and 3B are a top view and a cross-sectional view illustrating an example of a semiconductor device.
  • FIG. 4 is a cross-sectional view showing an example of a semiconductor device.
  • 5A and 5B are diagrams showing an example of the concentration of an impurity element.
  • FIG. 6 is a diagram showing an example of the concentration ratio of impurity elements.
  • FIG. 7 is a cross-sectional view showing an example of a semiconductor device.
  • FIGS. 8A and 8B are diagrams showing an example of the ratio of concentrations of impurity elements.
  • FIG. 9 is a diagram showing an example of the concentration ratio of impurity elements.
  • FIG. 10 is a cross-sectional view showing an example of a semiconductor device.
  • 11A to 11D are cross-sectional views showing an example of a semiconductor device.
  • FIG. 12 is a cross-sectional view showing an example of a semiconductor device.
  • 13A to 13C are cross-sectional views showing an example of a semiconductor device.
  • 14A and 14B are cross-sectional views showing an example of a semiconductor device.
  • 15A and 15B are cross-sectional views showing an example of a semiconductor device.
  • 16A and 16B are cross-sectional views showing an example of a semiconductor device.
  • FIG. 17A and 17B are cross-sectional views showing an example of a semiconductor device.
  • FIG. 18 is a cross-sectional view showing an example of a semiconductor device.
  • 19A and 19B are cross-sectional views showing an example of a semiconductor device.
  • Fig. 20A is a top view illustrating an example of a semiconductor device, and Fig. 20B and Fig. 20C are cross-sectional views illustrating an example of the semiconductor device.
  • 21A to 21I are circuit diagrams showing an example of a semiconductor device.
  • Fig. 22A is a top view illustrating an example of a semiconductor device, and Fig. 22B and Fig. 22C are cross-sectional views illustrating an example of the semiconductor device.
  • Fig. 22A is a top view illustrating an example of a semiconductor device
  • Fig. 22B and Fig. 22C are cross-sectional views illustrating an example of the semiconductor device.
  • Fig. 22A is a top view illustrating an example of a semiconductor device
  • FIG. 23A is a top view illustrating an example of a semiconductor device
  • Fig. 23B and Fig. 23C are cross-sectional views illustrating an example of the semiconductor device.
  • 24A is a top view illustrating an example of a semiconductor device
  • FIG 24B is a cross-sectional view illustrating the example of the semiconductor device.
  • 25A is a top view illustrating an example of a semiconductor device
  • FIG 25B is a cross-sectional view illustrating the example of the semiconductor device.
  • 26A and 26B are equivalent circuit diagrams of a semiconductor device
  • Fig. 26C is a top view showing an example of the semiconductor device.
  • FIG. 27 is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 28 is a perspective view showing an example of a semiconductor device.
  • 29A to 29D are perspective views showing an example of a semiconductor device.
  • 30A and 30B are equivalent circuit diagrams of a semiconductor device
  • Fig. 30C is a top view showing an example of the semiconductor device.
  • FIG. 31 is a cross-sectional view showing an example of a semiconductor device.
  • FIG. 32 is a perspective view showing an example of a semiconductor device.
  • 33A to 33D are perspective views showing an example of a semiconductor device.
  • 34A to 34E are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 35A to 35D are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • 36A to 36C are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 37 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.
  • 38A and 38B are cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 39 is a perspective view showing an example of a display device.
  • 40A and 40B are cross-sectional views showing an example of a display device.
  • FIG. 41 is a cross-sectional view showing an example of a display device.
  • 42A to 42C are cross-sectional views showing an example of a display device.
  • 43A and 43B are cross-sectional views showing an example of a display device.
  • FIG. 44 is a cross-sectional view showing an example of a display device.
  • FIG. 45 is a cross-sectional view showing an example of a display device.
  • FIG. 45 is a cross-sectional view showing an example of a display device.
  • 46 is a cross-sectional view showing an example of a display device.
  • 47A and 47B are cross-sectional views showing an example of a display device.
  • 48A to 48D are diagrams showing an example of an electronic device.
  • 49A to 49F are diagrams showing an example of an electronic device.
  • 50A to 50G are diagrams showing an example of an electronic device.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., process order or stacking order).
  • an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be changed to the term “conductive film.”
  • insulating film can be changed to the term “insulating layer.”
  • a transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conduction.
  • transistor includes IGFETs (Insulated Gate Field Effect Transistors) and thin film transistors (TFTs).
  • source and drain may be interchanged when transistors of different polarity are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms “source” and “drain” may be used interchangeably. Note that the source and drain of a transistor may be appropriately referred to as the source terminal and drain terminal, or the source electrode and drain electrode, depending on the situation.
  • electrically connected includes cases where the connection is made via "something that has some kind of electrical action.”
  • something that has some kind of electrical action is not particularly limited as long as it allows the transmission and reception of electrical signals between the connected objects.
  • something that has some kind of electrical action includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.
  • the off-state current refers to the leakage current between the source and drain when the transistor is in the off state (also called the non-conducting state or cut-off state).
  • the off-state refers to a state in which the voltage Vgs between the gate and source is lower than the threshold voltage Vth for an n-channel transistor (higher than Vth for a p-channel transistor).
  • top surface shape of a component refers to the contour shape of the component when viewed from above (also called a planar view). Additionally, a top view refers to a view from the normal direction of the surface on which the component is formed, or the surface of the support (e.g., substrate) on which the component is formed.
  • top surface shapes roughly match means that at least a portion of the contours of the stacked layers overlap. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where parts of the mask pattern are the same. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer, in which case it may also be said that “top surface shapes roughly match.” Furthermore, when the top surface shapes match or roughly match, it can also be said that the edges are aligned or roughly aligned.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface or the surface on which the structure is to be formed.
  • the angle between the inclined side and the substrate surface or the surface on which the structure is to be formed is sometimes referred to as a taper angle.
  • the side of the structure, the substrate surface, and the surface on which the structure is to be formed do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with minute irregularities.
  • a device manufactured using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device manufactured without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • devices with an MML structure can be manufactured without using a metal mask, they can exceed the upper limit of fineness resulting from the alignment accuracy of the metal mask.
  • devices with an MML structure can eliminate the need for equipment related to the manufacture of metal masks and the process of cleaning the metal masks.
  • devices with an MML structure are suitable for mass production because they make it possible to keep manufacturing costs low.
  • SBS Side By Side
  • the SBS structure allows the materials and configuration to be optimized for each light-emitting element, increasing the freedom of material and configuration selection and making it easier to improve brightness and reliability.
  • holes or electrons may be referred to as "carriers".
  • the hole injection layer or electron injection layer in a light-emitting element may be referred to as a "carrier injection layer”
  • the hole transport layer or electron transport layer may be referred to as a “carrier transport layer”
  • the hole block layer or electron block layer may be referred to as a "carrier block layer”.
  • the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable.
  • one layer may have two or three functions among the carrier injection layer, carrier transport layer, and carrier block layer.
  • the light-emitting element has an EL layer between a pair of electrodes.
  • the EL layer has at least a light-emitting layer.
  • layers also called functional layers
  • the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer).
  • the light-receiving element also called a light-receiving device
  • one of the pair of electrodes may be referred to as a pixel electrode, and the other as a common electrode.
  • the sacrificial layer (which may also be referred to as a mask layer) is located at least above the light-emitting layer (more specifically, the layer that is processed into an island shape among the layers that make up the EL layer) and has the function of protecting the light-emitting layer during the manufacturing process.
  • step discontinuity refers to the phenomenon in which a layer, film, or electrode is separated due to the shape of the surface on which it is formed (e.g., a step, etc.).
  • One embodiment of the present invention is a semiconductor device having a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer.
  • the first conductive layer functions as one of a source electrode and a drain electrode of a transistor, and the second conductive layer functions as the other.
  • the third conductive layer functions as one of a gate electrode.
  • the second insulating layer functions as a gate insulating layer.
  • a region of the semiconductor layer in contact with the first conductive layer functions as one of a source region and a drain region, and a region in contact with the second conductive layer functions as the other.
  • the first insulating layer is located on the first conductive layer and has a first opening that reaches the first conductive layer.
  • the angle between the side of the first opening of the first insulating layer and the top surface of the first conductive layer is 66 degrees or more and 90 degrees or less.
  • the second conductive layer is located on the first insulating layer and has a second opening in a region that overlaps with the first opening.
  • the semiconductor layer has a first region that contacts the top surface of the first conductive layer in the first opening and a second region that contacts the side of the first insulating layer.
  • the semiconductor layer also has a region that contacts the side of the second conductive layer in the second opening and a third region that contacts the top surface of the second conductive layer.
  • the second insulating layer is located on the semiconductor layer.
  • the third conductive layer has a region that overlaps with the semiconductor layer via the second insulating layer.
  • the first region, the third region, and the second insulating layer each contain an impurity element. It is preferable to use a first element as the impurity element. It is preferable to use one or more of the following as the first element: boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).
  • the electrical resistance of the source and drain regions can be reduced, resulting in a transistor with a large on-current.
  • the second region functions as a channel formation region of the transistor.
  • the concentration of the first element in the second region is preferably 1 ⁇ 10 ⁇ 3 times or less than the concentration of the first element in the first region.
  • the concentration of the first element in the second region is preferably 1 ⁇ 10 ⁇ 3 times or less than the concentration of the first element in the third region.
  • the source electrode and drain electrode are located at different heights, and the current flowing through the semiconductor layer flows in the height direction.
  • the channel length direction has a component in the height direction (vertical direction), and therefore the transistor according to one embodiment of the present invention can also be called a VFET (Vertical Field Effect Transistor), vertical transistor, vertical channel transistor, vertical channel transistor, etc.
  • VFET Vertical Field Effect Transistor
  • the transistor can have a source electrode, a semiconductor layer, and a drain electrode that are stacked, so the area occupied can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape.
  • FIG. 1A shows a top view (also referred to as a plan view) of a semiconductor device 10.
  • FIG. 1B shows a cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 1A
  • FIG. 1C shows a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG. 1A.
  • FIG. 1A some of the components of the semiconductor device 10 (such as a gate insulating layer) are omitted.
  • FIG. 1A some of the components are omitted in the top views of the semiconductor device in the following drawings.
  • FIGS. 3A and 3B show enlarged views of FIGS. 1A and 1B.
  • the semiconductor device 10 has a transistor 100 and an insulating layer 110.
  • the semiconductor device 10 is provided on a substrate 102.
  • the transistor 100 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 104 functions as a gate electrode.
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other.
  • a region of the semiconductor layer 108 that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode functions as a channel formation region.
  • a region of the semiconductor layer 108 that is in contact with the source electrode functions as a source region
  • a region that is in contact with the drain electrode functions as a drain region.
  • a conductive layer 112a is provided on the substrate 102, an insulating layer 110 is provided on the conductive layer 112a, and a conductive layer 112b is provided on the insulating layer 110.
  • the insulating layer 110 contacts the conductive layer 112a and the conductive layer 112b and has a region sandwiched between them.
  • the conductive layer 112a has a region overlapping with the conductive layer 112b via the insulating layer 110.
  • the insulating layer 110 has an opening 141 that reaches the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141.
  • the conductive layer 112b has an opening 143 in a region overlapping with the conductive layer 112a.
  • the opening 143 is provided in a region overlapping with the opening 141.
  • the semiconductor layer 108 is provided so as to cover the opening 141 and the opening 143.
  • the semiconductor layer 108 has a region in contact with the top surface of the conductive layer 112a and a region in contact with the side surface of the insulating layer 110 in the opening 141, and a region in contact with the side surface of the conductive layer 112b in the opening 143. Furthermore, the semiconductor layer 108 preferably has a region in contact with the top surface of the conductive layer 112b.
  • the semiconductor layer 108 has a shape that follows the shapes of the top surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the top surface of the conductive layer 112a.
  • the semiconductor material used for the semiconductor layer 108 is not particularly limited.
  • a semiconductor made of a single element or a compound semiconductor can be used.
  • semiconductors made of a single element include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS: oxide semiconductor). Note that these semiconductor materials may contain impurities as dopants.
  • the crystallinity of the semiconductor material used for the semiconductor layer 108 is not particularly limited, and any of an amorphous semiconductor, a single crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) can be used.
  • the use of a single crystal semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the semiconductor layer 108 can be made of, for example, silicon.
  • silicon examples include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • polycrystalline silicon examples include low temperature polysilicon (LTPS).
  • Transistors using amorphous silicon in the channel formation region can be formed on a large glass substrate and can be manufactured at low cost. Transistors using polycrystalline silicon in the channel formation region have high field effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon in the channel formation region have higher field effect mobility and can operate at high speed than transistors using amorphous silicon.
  • the semiconductor layer 108 preferably contains a metal oxide (also referred to as an oxide semiconductor) that exhibits semiconductor characteristics.
  • a transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has an extremely high field-effect mobility compared to a transistor using amorphous silicon.
  • an OS transistor has an extremely small off-state current and can hold charge accumulated in a capacitance connected in series with the transistor for a long period of time. Furthermore, by using an OS transistor, the power consumption of a semiconductor device can be reduced.
  • the semiconductor layer 108 has a region 108Da in one part and a region 108Db in the other part. Regions 108Da and 108Db each contain an impurity element. Regions 108Da and 108Db each have a higher concentration of the impurity element than other regions of the semiconductor layer 108 (e.g., channel formation regions) and are regions with low electrical resistance (hereinafter also referred to as low resistance regions). In the semiconductor layer 108, the channel formation region is located between regions 108Da and 108Db.
  • FIGS. 1B, 1C, and 3B show an example in which region 108Da is formed in a region of semiconductor layer 108 that is in contact with the upper surface of conductive layer 112a, and is located between the upper surface of conductive layer 112a and the lower surface of conductive layer 104.
  • the region in which region 108Da is formed is not limited to this, and for example, region 108Da can be formed in the entire region that is in contact with the upper surface of conductive layer 112a.
  • the impurity element may diffuse due to heat applied when the impurity element is supplied to semiconductor layer 108 or in a process after the impurity element is supplied.
  • region 108Db is formed in a region of semiconductor layer 108 that contacts the top surface of conductive layer 112b.
  • Region 108Db can also be provided in a region of semiconductor layer 108 that contacts the side surface of conductive layer 112b.
  • Region 108Db can also be provided in a part of a region of semiconductor layer 108 that contacts the side surface of insulating layer 110.
  • the first element is used as the impurity element.
  • the first element it is preferable to use one or more of boron, aluminum, indium, carbon, silicon, germanium, tin, phosphorus, arsenic, antimony, magnesium, calcium, titanium, copper, zinc, tungsten, molybdenum, tantalum, hafnium, cerium, and noble gases (helium, neon, argon, krypton, xenon, etc.).
  • the first element is not limited to the above elements, but may be one or more of the first transition elements (3d transition elements, 3d transition metals), second transition elements (4d transition elements, 4d transition metals), third transition elements (5d transition elements, 5d transition metals), alkaline earth metal elements, and elements contained in the rare earth elements.
  • Supplying the first element to the source region and the drain region (also referred to as adding the first element or injecting the first element) generates oxygen vacancies (V O ) in the source region and the drain region. Then, carriers are generated by defects (hereinafter also referred to as V O H) in which hydrogen enters the oxygen vacancies (V O ).
  • V O H defects
  • the electrical resistance of the semiconductor layer 108, the contact resistance between the semiconductor layer 108 and the conductive layer 112a, and the contact resistance between the semiconductor layer 108 and the conductive layer 112b can each be reduced. Therefore, the on-current of the transistor 100 can be increased. By increasing the on-current, the operating voltage of the transistor 100 can be reduced. This can reduce the power consumption of the semiconductor device.
  • the first element When an element that easily bonds with oxygen is used as the first element, the first element takes away oxygen in the semiconductor layer 108 and exists in a state bonded with oxygen. In addition, oxygen vacancies (V 2 O 3 ) are generated in the semiconductor layer 108.
  • the first element in the semiconductor layer 108 exists stably in an oxidized state, so that it is difficult to be desorbed by heat or the like applied during the manufacturing process of the transistor 100, and the electrical resistance can be kept low. For this reason, it is preferable to use an element whose oxide can exist in a solid state at least at the temperature during the manufacturing process as the first element.
  • typical nonmetallic elements other than hydrogen, typical metallic elements, and transition elements (transition metals) can be mentioned as preferred first elements, and boron, phosphorus, magnesium, aluminum, and silicon can be mentioned as particularly preferred first elements.
  • boron, phosphorus, magnesium, aluminum, or silicon it is preferable to use boron, phosphorus, magnesium, aluminum, or silicon as one of the first elements.
  • boron or phosphorus it is preferable to use boron or phosphorus as one of the first elements.
  • Hydrogen is an ideal impurity element because it not only creates oxygen vacancies but also bonds with oxygen vacancies.
  • the impurity element can be preferably supplied by plasma ion doping or ion implantation. These methods allow for highly accurate control of the concentration profile in the depth direction by adjusting the ion acceleration energy and dose.
  • ion implantation which ionizes the source gas and supplies the ions after mass separation, it is possible to supply ions of a specific mass, thereby increasing the purity of the supplied impurity element.
  • plasma ion doping which supplies ions without mass separation, productivity can be increased.
  • boron used as the first element
  • BF3 gas can be used as the source gas.
  • phosphorus used as the first element
  • PH3 gas can be used as the source gas.
  • mass-separating the ions generated from these gases and supplying them it is possible to supply ions of a specific mass to the regions 108Da and 108Db, which is more preferable.
  • a gas containing the first element and hydrogen (for example, PH 3 gas and B 2 H 6 gas) can be used as the source gas.
  • a mixed gas of a gas containing the first element and a gas having hydrogen can be used as the source gas.
  • ions generated from the source gas can be supplied without mass separation, which is preferable because it can increase productivity.
  • B 2 H 6 gas as the source gas
  • boron and hydrogen can be supplied as impurity elements.
  • PH 3 gas for example, phosphorus and hydrogen can be supplied as impurity elements.
  • the region 108Da preferably includes a portion having an impurity element concentration Na of 1 ⁇ 10 19 atoms/cm 3 or more and 1 ⁇ 10 23 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or more and 5 ⁇ 10 22 atoms/cm 3 or less, and more preferably 5 ⁇ 10 19 atoms/cm 3 or more and 5 ⁇ 10 21 atoms/cm 3 or less.
  • the region 108Da when boron is used as the first element, the region 108Da preferably includes a portion having a boron concentration Na in the above-mentioned range.
  • the region 108Db preferably includes a portion having an impurity element concentration Nb of 1 ⁇ 10 19 atoms/cm 3 or more and 1 ⁇ 10 23 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or more and 5 ⁇ 10 22 atoms/cm 3 or less, and more preferably 5 ⁇ 10 19 atoms/cm 3 or more and 5 ⁇ 10 21 atoms/cm 3 or less.
  • the region 108Db when boron is used as the first element, the region 108Db preferably includes a portion having a boron concentration Nb in the above-mentioned range.
  • region 108Da contains two or more impurity elements, it is preferable that at least one of the impurity elements is in the above range. It is also more preferable that the concentration of each impurity element is in the above range. The same applies to region 108Db.
  • the impurity elements When the impurity elements are supplied to the regions 108Da and 108Db, the impurity elements may also be supplied to the channel formation region of the semiconductor layer 108. Alternatively, due to heat applied during the manufacturing process, some of the impurity elements contained in the regions 108Da and 108Db may diffuse into the channel formation region.
  • the concentration Nc of the impurity element in the channel formation region of the semiconductor layer 108 is preferably low.
  • the concentration Nc is preferably lower than the concentration Na of the impurity element in the region 108Da.
  • the concentration Nc is preferably lower than the concentration Nb of the impurity element in the region 108Db.
  • the concentration Nc is preferably 1 ⁇ 10 ⁇ 1 times or less than the concentration Na, more preferably 1 ⁇ 10 ⁇ 2 times or less, more preferably 1 ⁇ 10 ⁇ 3 times or less, and even more preferably 1 ⁇ 10 ⁇ 4 times or less.
  • the concentration Nc is preferably 1 ⁇ 10 ⁇ 1 times or less than the concentration Nb, more preferably 1 ⁇ 10 ⁇ 2 times or less, more preferably 1 ⁇ 10 ⁇ 3 times or less, and even more preferably 1 ⁇ 10 ⁇ 4 times or less.
  • the ratio Pa of the concentration Nc to the concentration Na can be expressed by formula (2).
  • the ratio Pb of the concentration Nc to the concentration Nb can be expressed by formula (3).
  • the ratios Pa and Pb are both dimensionless quantities and real numbers greater than 0.
  • Each of the ratios Pa and Pb is preferably 1 ⁇ 10 ⁇ 1 or less, more preferably 1 ⁇ 10 ⁇ 2 or less, further preferably 1 ⁇ 10 ⁇ 3 or less, and further preferably 1 ⁇ 10 ⁇ 4 or less. This allows a transistor to have both a small cutoff current and a large on-current. Therefore, a semiconductor device that has both low power consumption and high performance can be obtained.
  • the concentration of impurity elements (here, concentration Na, concentration Nb, and concentration Nc) in the channel formation region, region 108Da, and region 108Db of the semiconductor layer 108 can be analyzed using, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectrometry (XPS), or electron spectrometry for chemical analysis (ESCA).
  • SIMS secondary ion mass spectrometry
  • XPS X-ray photoelectron spectrometry
  • ESCA electron spectrometry for chemical analysis
  • concentration distribution in the depth direction can be known by combining ion sputtering from the front side or back side of the sample with XPS analysis.
  • the concentration Nc in the channel formation region is low. Therefore, the concentration Nc may be difficult to quantify or may be below the detection limit.
  • the impurity element is more easily supplied to the source and drain regions of the semiconductor layer 108 than to the channel formation region.
  • the impurity element is preferably supplied from a direction perpendicular or approximately perpendicular to the top surface of the substrate 102.
  • the amount of the impurity element supplied to a region inclined with respect to the top surface of the substrate 102 in the semiconductor layer 108 is smaller than that supplied to a region parallel or approximately parallel to the top surface of the substrate 102.
  • the amount of the impurity element supplied to the source and drain regions of the semiconductor layer 108 is larger than that supplied to the channel formation region. Therefore, the electrical resistance of the source and drain regions can be preferentially reduced.
  • the insulating layer 110 one or both of an inorganic insulating layer and an organic insulating layer can be used.
  • examples of materials that can be used for the organic insulating layer include acrylic resin and polyimide resin.
  • the insulating layer 110 has one or more inorganic insulating layers. Examples of materials that can be used for the inorganic insulating layer include oxides, nitrides, oxynitrides, and nitride oxides.
  • oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate.
  • nitrides include silicon nitride and aluminum nitride.
  • oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride.
  • nitride oxides include silicon nitride oxide and aluminum nitride oxide.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • the insulating layer 110 has a region in contact with the semiconductor layer 108.
  • a metal oxide is used for the semiconductor layer 108
  • the part of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 contains oxygen.
  • One or more of an oxide and an oxynitride can be suitably used for the part of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.
  • a metal oxide is used for the semiconductor layer 108
  • oxygen is supplied from the insulating layer 110 to the semiconductor layer 108, and oxygen vacancies ( VO ) and VOH in the semiconductor layer 108 can be reduced.
  • the insulating layer 106 which functions as a gate insulating layer of the transistor 100, is provided so as to cover the openings 141 and 143.
  • the insulating layer 106 is provided on the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110.
  • the insulating layer 106 has a region in contact with the top surface and side surfaces of the semiconductor layer 108, the top surface and side surfaces of the conductive layer 112b, and the top surface of the insulating layer 110.
  • the insulating layer 106 has a shape that follows the shapes of the top surface of the insulating layer 110, the top surface and side surfaces of the conductive layer 112b, the top surface and side surfaces of the semiconductor layer 108, and the top surface of the conductive layer 112a.
  • the thicknesses Ta, Tb, and Tc are thicknesses in a direction perpendicular or approximately perpendicular to the surface on which the insulating layer 106 is formed. More specifically, the thickness Ta is the shortest distance between the upper surface of the semiconductor layer 108 provided along the upper surface of the conductive layer 112a and the upper surface of the insulating layer 106.
  • the thickness Tb is the shortest distance between the upper surface of the semiconductor layer 108 provided along the upper surface of the conductive layer 112b and the upper surface of the insulating layer 106.
  • the thickness Tc is the shortest distance between the side surface of the semiconductor layer 108 on the insulating layer 106 side provided along the side surface of the insulating layer 110 and the side surface of the insulating layer 106 on the conductive layer 104 side.
  • FIG. 3B shows a configuration in which the thicknesses Ta, Tb, and Tc are the same, but one aspect of the present invention is not limited to this. A configuration in which some or all of the thicknesses Ta, Tb, and Tc are different may also be used.
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • the thickness Tc of the part of the insulating layer 106 in contact with the channel formation region is preferably 1 nm or more and 200 nm or less, more preferably 1 nm or more and 150 nm or less, and even more preferably 1 nm or more and 100 nm or less.
  • the thickness Tc is preferably 30 nm or more and 100 nm or less.
  • the thickness Tc is preferably 1 nm or more and 50 nm or less.
  • the thickness Tc is preferably 1 nm or more and 10 nm or less.
  • the conductive layer 104 which functions as the gate electrode of the transistor 100, is provided on the insulating layer 106 and has a region in contact with the top surface of the insulating layer 106.
  • the conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106.
  • the conductive layer 104 has a shape that follows the shape of the top surface of the insulating layer 106.
  • the transistor 100 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 108. Furthermore, since the bottom surface of the semiconductor layer 108 is in contact with the source electrode and the drain electrode, the transistor 100 can be called a TGBC (Top Gate Bottom Contact) type transistor. Furthermore, the source electrode and the drain electrode of the transistor 100 are located at different heights relative to the surface of the substrate 102 on which the transistor 100 is formed, and the drain current flows in a direction perpendicular to or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows vertically or approximately vertically in the transistor 100. Therefore, the transistor that is one aspect of the present invention can be called a VFET.
  • the channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length shorter than the minimum exposure dimension of an exposure device used to manufacture the transistor can be manufactured with high precision. In addition, the characteristic variation between multiple transistors 100 is also reduced. This makes it possible to stabilize the operation of the semiconductor device 10 and improve its reliability. Furthermore, reduced characteristic variation of the transistors increases the freedom of circuit design and allows the operating voltage of the semiconductor device to be lowered. This allows the power consumption of the semiconductor device to be reduced.
  • the transistor can have a source electrode, a semiconductor layer, and a drain electrode that are stacked, so the area occupied can be significantly reduced compared to a so-called planar type transistor in which the semiconductor layer is arranged in a planar shape.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each function as wiring, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit having the transistor 100 and the wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.
  • a semiconductor device of one embodiment of the present invention when a semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained.
  • a semiconductor device of one embodiment of the present invention when a semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.
  • the insulating layer 110 preferably has a laminated structure.
  • FIG. 1B and other figures show an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on the insulating layer 110a, and an insulating layer 110c on the insulating layer 110b.
  • the insulating layers 110a, 110b, and 110c can each be made of the materials listed in the description of the insulating layer 110.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region.
  • the insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. Specifically, one or both of silicon oxide and silicon oxynitride can be preferably used for the insulating layer 110b.
  • a material that releases oxygen when heated for the insulating layer 110b It is more preferable to use a material that releases oxygen when heated for the insulating layer 110b.
  • oxygen can be supplied to the semiconductor layer 108.
  • oxygen vacancies (V O ) are repaired and oxygen vacancies (V O ) can be reduced.
  • V O H can be reduced. Therefore, a transistor having good electrical characteristics and high reliability can be obtained.
  • oxygen can be supplied to the insulating layer 110b by performing a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere.
  • oxygen can be supplied to the insulating layer 110b by forming a film on the upper surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. The film may then be removed. Note that a method for supplying oxygen to the insulating layer 110b will be specifically described in embodiment 2.
  • the insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • a gas containing hydrogen e.g., hydrogen gas and ammonia gas
  • the sputtering method can be particularly preferably used for the insulating layer 110b. This can suppress the supply of hydrogen to the channel formation region, and stabilize the electrical characteristics of the transistor 100.
  • the insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a.
  • the insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. It is preferable that the amount of impurities (e.g., hydrogen and water) released from the insulating layer 110a and the insulating layer 110c is small. Furthermore, it is preferable that the insulating layer 110a and the insulating layer 110c are each impermeable to substances (e.g., atoms, molecules, and ions). It can be said that the insulating layer 110a and the insulating layer 110c function as a barrier film.
  • the insulating layer 110a and the insulating layer 110c are each impermeable to impurities. This makes it possible to suppress the diffusion of impurities contained in the insulating layer 110a and the insulating layer 110c into the channel formation region. Therefore, it is possible to obtain a transistor that exhibits good electrical characteristics and is highly reliable.
  • the insulating layer 110a and the insulating layer 110c are preferably made of a material through which oxygen does not easily permeate. This can suppress the oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a side through the insulating layer 110a. Similarly, the oxygen contained in the insulating layer 110b can suppress the oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112b side through the insulating layer 110c. This can increase the amount of oxygen supplied from the insulating layer 110b to the channel formation region of the semiconductor layer 108, thereby reducing oxygen vacancies (V O ) and V O H in the channel formation region. Therefore, a transistor having good electrical characteristics and high reliability can be obtained.
  • the conductive layer 112a is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112a is prevented from increasing.
  • the conductive layer 112b is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112b is prevented from increasing. Therefore, a transistor having a large on-current can be obtained.
  • a barrier film refers to a film that has barrier properties.
  • Barrier properties refer to one or both of the following functions: making it difficult for a target substance to diffuse, thereby suppressing the substance from permeating the film (also called low permeability), and the function of capturing or fixing the substance (also called gettering).
  • an insulating layer that has barrier properties can be called a barrier insulating layer.
  • the insulating layer 110a and the insulating layer 110c which function as a barrier film, can each be made of one or more of the following: an oxide having one or both of aluminum and hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, and a nitride oxide having silicon.
  • the insulating layer 110a and the insulating layer 110c can each be made of one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • the insulating layer 110a and the insulating layer 110c can be made of the same material. Alternatively, the insulating layer 110a and the insulating layer 110c can be made of different materials.
  • oxygen can be supplied to insulating layer 110b (or the insulating film that becomes insulating layer 110b) when forming insulating layer 110c (or the insulating film that becomes insulating layer 110c).
  • different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.
  • the impurity element is preferably supplied to the semiconductor layer 108 through the insulating layer 106.
  • the supply of the impurity element will be described with reference to FIG. 4.
  • the lower side of FIG. 4 shows a cross-sectional view of the insulating layer 106, the semiconductor layer 108, and their vicinity when the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106.
  • the impurity element is supplied from a direction perpendicular to the top surface of the substrate 102 will be described. Note that the cross-sectional view shown in FIG.
  • FIG 4 shows a configuration in which the surface of the insulating layer 106 (specifically, the top surface and side surface of the insulating layer 106) is parallel to the top surface and side surface of the semiconductor layer 108, which is the surface on which the insulating layer 106 is formed.
  • the thickness Td can be the thickness of the insulating layer 106 on a straight line extending from the midpoint between the upper surface end and the lower surface end of the insulating layer 110b in the direction in which the impurity element is supplied (here, the direction perpendicular to the upper surface of the substrate 102).
  • the thickness Ta of the region provided along the upper surface of the conductive layer 112a and the thickness Tb of the region provided along the upper surface of the conductive layer 112b are thin.
  • the region of the semiconductor layer 108 provided along the upper surface of the conductive layer 112a or the upper surface of the conductive layer 112b receives a larger amount of impurity element than the region provided along the side of the insulating layer 110.
  • the supply of the impurity element to the channel formation region of the semiconductor layer 108 can be suppressed, and the electrical resistance of the source region and the drain region can be preferentially reduced.
  • the thicker the insulating layer 106 the larger the difference between thickness Ta and thickness Td, and the difference between thickness Tb and thickness Td can be. This can prevent impurity elements from being supplied to the channel formation region of the semiconductor layer 108, and preferentially lower the electrical resistance of the source and drain regions.
  • the insulating layer 106 may also contain the impurity elements. It is preferable that each of the regions 108Da and 108Db has a portion with a higher concentration of the impurity element than the insulating layer 106, since this can reduce the electrical resistance of the regions 108Da and 108Db.
  • concentration of the impurity element in the insulating layer 106 please refer to the description related to the analysis of the concentration of the impurity element in the semiconductor layer 108.
  • the insulating layer 106 preferably has an insulating layer containing oxygen.
  • the impurity element exists in a state of being bonded with oxygen in the insulating layer 106 as in the semiconductor layer 108.
  • oxygen and the impurity element are bonded and stabilized, oxygen is less likely to be released from the region containing the impurity element even when heat is applied, so that the diffusion of oxygen to other layers can be suppressed.
  • This makes it possible to efficiently supply oxygen to the channel formation region while suppressing the supply of oxygen from the insulating layer 106 to the regions 108Da and 108Db. Therefore, oxygen deficiency in the channel formation region can be reduced while preventing the electrical resistance of the regions 108Da and 108Db from increasing. As a result, a transistor with good electrical characteristics and high reliability can be realized.
  • the boron contained in the regions 108Da, 108Db, and the insulating layer 106 may exist in a state of being bonded to oxygen. This can be confirmed, for example, by observing a peak due to a B 2 O 3 bond in an XPS analysis. In addition, in the XPS analysis, a spectrum peak due to the state in which the boron element exists alone is not observed, or the peak intensity is extremely small, to the level of background.
  • the impurity element When an impurity element is supplied to the semiconductor layer 108 through the insulating layer 106, the impurity element penetrates from the surface of the insulating layer 106, passes through the insulating layer 106, and then reaches the semiconductor layer 108 through the interface between the insulating layer 106 and the semiconductor layer 108.
  • the thickness of the insulating layer 106 in the direction in which the impurity element is supplied can also be said to be the depth D from the surface of the insulating layer 106 to the semiconductor layer 108.
  • the depth D in each region of the insulating layer 106 is shown in the upper part of FIG. 4.
  • the horizontal axis indicates the position of the insulating layer 106 in a cross-sectional view
  • the vertical axis indicates the depth D.
  • the depth D in the region provided along the upper surface of the conductive layer 112a of the insulating layer 106 corresponds to the thickness Ta of the insulating layer 106.
  • the depth D in the region provided along the upper surface of the conductive layer 112b of the insulating layer 106 corresponds to the thickness Tb of the insulating layer 106.
  • the depth D in the region provided along the side surface of the insulating layer 110 of the insulating layer 106 corresponds to the thickness Td.
  • the impurity element is supplied to the semiconductor layer 108 through the insulating layer 106
  • the insulating layer 106 and the semiconductor layer 108 may each be referred to as an implanted layer.
  • the depth "Td” in the region of insulating layer 106 that is provided along the side surface of insulating layer 110 is deeper than the depth "Ta” in the region that is provided along the top surface of conductive layer 112a, and is deeper than the depth "Tb” in the region that is provided along the top surface of conductive layer 112b.
  • depth D has a value between "Ta” and "Td”
  • depth D has a value between "Tb” and "Td”.
  • depth D has a value smaller than "Td”.
  • the concentration of the impurity element can be expressed by a Gaussian distribution.
  • the concentration N(x) of the impurity element at depth x can be expressed by formula (4).
  • the concentration N(x) is a real number greater than 0.
  • Q is the dose
  • m is the projected range (also referred to as Rp)
  • s is the standard deviation in the depth direction (also referred to as ⁇ Rp).
  • the dose Q, projected range m, and standard deviation s are all real numbers greater than 0. Note that the projected range m is the average depth at which ions stop during implantation, and the concentration of the impurity element is highest at depth "m.”
  • the Gaussian distribution of the concentration of an impurity element at a projected range m and a standard deviation s (variance s2 ) is shown in Figure 5A.
  • the horizontal axis indicates the depth D on a linear scale
  • the vertical axis indicates the concentration N(D) on a logarithmic scale.
  • the concentration N(m) is highest at a projected range m, which is indicated as " Nmax " in Figure 5A.
  • the projected range m and standard deviation s can be calculated, for example, using simulation software.
  • the simulation software include TRIM (Transport of Ion in Matter) and SRIM (Stopping and Range of Ions in Matter). These are software that simulate the ion implantation process using the Monte Carlo method.
  • the type of impurity element supplied (specifically, the type of ion), the composition and film density of the implanted layer, and the acceleration energy can be used as simulation parameters. For example, if the mass number of the impurity element supplied is large, the projected range m becomes small.
  • the stopping power in ion implantation differs depending on the type of element, the projected range m differs depending on the composition of the implanted layer.
  • the projected range m can be made different depending on the material used for the implanted layer (e.g., the insulating layer 106). Note that film density refers to the mass per unit volume. Also, if the acceleration energy is high, the projected range m will be large and the standard deviation s will be large.
  • the concentration Na of the impurity element in region 108Da is the concentration of the impurity element at depth "Ta” and can be expressed by formula (5).
  • the concentration Nb of the impurity element in region 108Db is the concentration of the impurity element at depth "Tb” and can be expressed by formula (6).
  • the concentration Nc of the impurity element in the channel formation region is the concentration of the impurity element at depth "Td” and can be expressed by formula (7).
  • the concentrations Na, Nb, and Nc are each real numbers greater than 0.
  • the ratio Pa of the impurity element concentration Nc in the channel formation region to the impurity element concentration Na in region 108Da can be expressed by formula (8).
  • the ratio Pb of the impurity element concentration Nc in the channel formation region to the impurity element concentration Nb in region 108Db can be expressed by formula (9).
  • the ratio Pa can be expressed by thickness Ta, thickness Td, projected range m, and standard deviation s, as shown in formula (8).
  • the ratio Pb can be expressed by thickness Tb, thickness Td, projected range m, and standard deviation s, as shown in formula (9). It is preferable to set thickness Ta, thickness Tb, thickness Td, projected range m, and standard deviation s so that ratio Pa and ratio Pab are each within the aforementioned range. As shown in formula (8), the ratio Pa can be made smaller as the difference between thickness Td and thickness Ta is increased. As shown in formula (9), the ratio Pb can be made smaller as the difference between thickness Td and thickness Tb is increased.
  • the thickness Td can be expressed by formula (10).
  • the angle ⁇ is greater than 0 degrees and less than 90 degrees, cos ⁇ is greater than 0 and less than 1. Therefore, the thickness Td is thicker than the thickness Tc.
  • the smaller the angle ⁇ the thinner the thickness Td is, and the larger the angle ⁇ , the thicker the thickness Td is.
  • the larger the angle ⁇ the greater the difference between the thickness Td and the thickness Ta can be, and the smaller the ratio Pa can be.
  • the larger the angle ⁇ the greater the difference between the thickness Td and the thickness Tb can be, and the smaller the ratio Pb can be.
  • the angle ⁇ is preferably equal to or less than 90 degrees, and more preferably less than 90 degrees.
  • the cross-sectional view shown in FIG. 4 shows a configuration in which the upper surface of the conductive layer 112a is parallel to the upper surface of the substrate 102.
  • the angle ⁇ is the same as the angle between the side surface of the insulating layer 110 and the upper surface of the substrate 102.
  • the impurity element is preferably supplied from a direction perpendicular or approximately perpendicular to the upper surface of the conductive layer 112a. In other words, the impurity element is preferably supplied from a direction perpendicular or approximately perpendicular to the upper surface of the substrate 102.
  • the impurity element is preferably supplied from a direction perpendicular or approximately perpendicular to the upper surface of the conductive layer 112a.
  • the ratio Pa can be expressed by formula (11), and the ratio Pb can be expressed by formula (12).
  • the ratio Pa can be expressed by the angle ⁇ , thickness Ta, thickness Tc, projected range m, and standard deviation s, as shown in formula (11).
  • the ratio Pb can be expressed by the angle ⁇ , thickness Tb, thickness Tc, projected range m, and standard deviation s, as shown in formula (12). It is preferable to set the angle ⁇ , thickness Ta, thickness Tb, thickness Tc, projected range m, and standard deviation s so that the ratio Pa and the ratio Pab are each within the aforementioned range.
  • the ratio Pa and the ratio Pb can be made smaller as the angle ⁇ increases.
  • the concentration N(D) of the impurity element is highest at the interface between the insulating layer 106 and the semiconductor layer 108 in the region provided along the top surface of the conductive layer 112a, and at the interface between the insulating layer 106 and the semiconductor layer 108 in the region provided along the top surface of the conductive layer 112b. It is also assumed that the thicknesses Ta, Tb, and Tc are the same. In other words, if the projected range m is "Ta”, then as shown in FIG. 5B, the concentration Na at the depth "Ta” and the concentration Nb at the depth "Tb” are highest. If the thickness Td is expressed as "Ta/cos ⁇ ", the ratio Pa can be expressed by formula (13), and the ratio Pb can be expressed by formula (14).
  • the ratios Pa and Pb can be expressed by the angle ⁇ , the thickness Ta, and the standard deviation s, respectively. It is preferable to set the angle ⁇ , the thickness Ta, and the standard deviation s so that the ratios Pa and Pab are each within the aforementioned ranges. Note that when the thicknesses Ta and Tb are different from each other, the ratio Pb can be calculated by using formula (12).
  • the projected range m and standard deviation s are determined by selecting the acceleration energy according to the type of impurity element supplied, the composition, film density, and thickness of the implanted layer, and the standard deviation s can be expressed by formula (15).
  • ⁇ is the ratio of the standard deviation s to the projected range m, and is a dimensionless quantity.
  • ⁇ is a real number greater than 0.
  • the ratio ⁇ is determined by selecting the acceleration energy according to the type of impurity element supplied, the composition, film density, and thickness of the implanted layer. Using the ratio ⁇ , the ratio Pa can be expressed by formula (16), and the ratio Pb can be expressed by formula (17).
  • the ratios Pa and Pb can be expressed by the angle ⁇ and the ratio ⁇ of the standard deviation s to the projected range m, respectively. It is preferable to set the angle ⁇ according to the ratio ⁇ so that the ratios Pa and Pb are each within the aforementioned range. As shown in formulas (16) and (17), the larger the ratio ⁇ , the larger the angle ⁇ can be made to make the ratio Pa smaller. This makes it possible to obtain a transistor that has both a small cutoff current and a large on-current. Therefore, it is possible to obtain a semiconductor device that has both low power consumption and high performance.
  • Figure 6 The relationship between the angle ⁇ and the ratio Pa is shown in Figure 6.
  • the horizontal axis represents the angle ⁇
  • the vertical axis represents the ratio Pa.
  • Figure 6 shows the ratio Pa when the ratio ⁇ is varied to 0.25, 0.30, 0.33, 0.35, 0.38, 0.40, 0.45, and 0.50.
  • the angle ⁇ is set to 59 degrees or more, when the ratio ⁇ is 0.30 or less, the angle ⁇ is set to 62 degrees or more, when the ratio ⁇ is 0.33 or less, the angle ⁇ is set to 64 degrees or more, when the ratio ⁇ is 0.35 or less, the angle ⁇ is set to 65 degrees or more, when the ratio ⁇ is 0.38 or less, the angle ⁇ is set to 66 degrees or more, when the ratio ⁇ is 0.40 or less, the angle ⁇ is set to 67 degrees or more, when the ratio ⁇ is 0.45 or less, the angle ⁇ is set to 69 degrees or more, and when the ratio ⁇ is 0.50 or less, the angle ⁇ is set to 70 degrees or more, which is preferable because it is possible to set the ratio Pa to 1 ⁇ 10 ⁇ 3 or less.
  • the angle ⁇ is 62 degrees or more, when the ratio ⁇ is 0.30 or less, the angle ⁇ is 65 degrees or more, when the ratio ⁇ is 0.33 or less, the angle ⁇ is 66 degrees or more, when the ratio ⁇ is 0.35 or less, the angle ⁇ is 67 degrees or more, when the ratio ⁇ is 0.38 or less, the angle ⁇ is 68 degrees or more, when the ratio ⁇ is 0.40 or less, the angle ⁇ is 69 degrees or more, when the ratio ⁇ is 0.45 or less, the angle ⁇ is 71 degrees or more, and when the ratio ⁇ is 0.50 or less, the angle ⁇ is 72 degrees or more, thereby making it possible to set the ratio Pa to 1 x 10-4 or less, which is even more preferable.
  • ratio Pa and ratio Pb will also be the same or approximately the same, so ratio Pa in FIG. 6 and the above description can be replaced with ratio Pb.
  • the ratios Pa and Pb are 1.6 ⁇ 10 ⁇ 3 when the angle ⁇ is 65 degrees, the ratios Pa and Pb are 6.3 ⁇ 10 ⁇ 4 when the angle ⁇ is 66 degrees, and the ratios Pa and Pb are 6.4 ⁇ 10 ⁇ 5 when the angle ⁇ is 68 degrees. Therefore, by setting the angle ⁇ to 66 degrees or more, the ratios Pa and Pb can each be set to 1 x 10-3 or less, and by setting the angle ⁇ to 68 degrees or more, the ratios Pa and Pb can each be set to 1 x 10-4 or less.
  • the ratios Pa and Pb can be reduced. Furthermore, depending on the impurity element used and the film density of the insulating layer 106, by increasing the angle ⁇ , the ratios Pa and Pb can be reduced.
  • the thickness Tc can be expressed by the formula (18) using the thickness Ta.
  • ⁇ is the ratio of the thickness Tc to the thickness Ta, and is a dimensionless quantity.
  • the ratio ⁇ is a real number greater than 0.
  • the ratio ⁇ is 1.
  • the thickness Tc of the insulating layer 106 in the region provided along the side surface of the insulating layer 110 may be thinner than the thickness Ta of the insulating layer 106 in the region provided along the upper surface of the conductive layer 112a.
  • the ratio ⁇ is a real number greater than 0 and less than 1.
  • the ratio ⁇ is a real number greater than 1.
  • the thickness Tc may be thinner than the thickness Ta, that is, the ratio ⁇ may be smaller than 1.
  • the ratio ⁇ can be closer to 1.
  • the thickness Tc when the thickness Tc is expressed by formula (18), the thickness Td can be expressed by formula (19). Furthermore, the ratio Pa shown in formula (11) above can be expressed by formula (20). The ratio Pb shown in formula (12) can be expressed by formula (21).
  • the ratio Pa can be expressed by the ratio ⁇ , the angle ⁇ , the thickness Ta, the projected range m, and the standard deviation s, as shown in formula (20).
  • the ratio Pb can be expressed by the ratio ⁇ , the thickness Ta, the thickness Tb, the projected range m, and the standard deviation s, as shown in formula (21). It is preferable to set the angle ⁇ , the thickness Ta, the thickness Tb, the projected range m, and the standard deviation s according to the ratio ⁇ so that the ratio Pa and the ratio Pab are each within the above-mentioned range.
  • the smaller the ratio ⁇ the larger the angle ⁇ can be to reduce the ratio Pa. This allows a transistor that has both a small cutoff current and a large on-current. Therefore, a semiconductor device that has both low power consumption and high performance can be obtained.
  • the concentration N of the impurity element is highest at the interface between the insulating layer 106 and the semiconductor layer 108. Also, it is assumed that the thicknesses Ta and Tb are the same. In other words, if the projected range m is "Ta", the ratio Pa can be expressed by formula (22) and the ratio Pb can be expressed by formula (23).
  • the ratios Pa and Pb can be expressed by the ratio ⁇ , the thickness Ta, the angle ⁇ , and the standard deviation s, respectively. It is preferable to set the angle ⁇ , the thickness Ta, and the standard deviation s according to the ratio ⁇ so that the ratios Pa and Pab are each within the aforementioned ranges.
  • the ratios Pa and Pb can be expressed by the ratio ⁇ of the standard deviation s to the projected range m, the ratio ⁇ of the thickness Tc to the thickness Ta, and the angle ⁇ , respectively. It is preferable to set the angle ⁇ according to the ratio ⁇ and the ratio ⁇ so that the ratios Pa and Pb are each within the aforementioned range.
  • the ratio Pa when ⁇ is set to 1 in formula (24) is the aforementioned formula (16).
  • the ratio Pb when ⁇ is set to 1 in formula (25) is the aforementioned formula (17).
  • Figures 8A and 8B The relationship between the angle ⁇ and the ratio Pa is shown in Figures 8A and 8B.
  • Figure 8A shows the relationship between the angle ⁇ and the ratio Pa when the ratio ⁇ is 0.85
  • Figure 8B shows the relationship between the angle ⁇ and the ratio Pa when the ratio ⁇ is 0.75.
  • the horizontal axis shows the angle ⁇
  • the vertical axis shows the ratio Pa.
  • Figures 8A and 8B show the ratio Pa when the ratio ⁇ is changed to 0.25, 0.30, 0.33, 0.35, 0.38, 0.40, 0.45, and 0.50, respectively.
  • Figure 6 shows the relationship between the angle ⁇ and the ratio Pa when the ratio ⁇ is 1.
  • the angle ⁇ is 64 degrees or more, if the ratio ⁇ is 0.30 or less, the angle ⁇ is 67 degrees or more, if the ratio ⁇ is 0.33 or less, the angle ⁇ is 68 degrees or more, if the ratio ⁇ is 0.35 or less, the angle ⁇ is 69 degrees or more, if the ratio ⁇ is 0.38 or less, the angle ⁇ is 70 degrees or more, if the ratio ⁇ is 0.40 or less, the angle ⁇ is 71 degrees or more, if the ratio ⁇ is 0.45 or less, the angle ⁇ is 72 degrees or more, and if the ratio ⁇ is 0.50 or less, the angle ⁇ is 73 degrees or more, thereby making it possible to set the ratio Pa to 1 ⁇ 10 ⁇ 3 or less, which is preferable.
  • the angle ⁇ is 66 degrees or more, when the ratio ⁇ is 0.30 or less, the angle ⁇ is 69 degrees or more, when the ratio ⁇ is 0.33 or less, the angle ⁇ is 70 degrees or more, when the ratio ⁇ is 0.35 or less, the angle ⁇ is 71 degrees or more, when the ratio ⁇ is 0.38 or less, the angle ⁇ is 72 degrees or more, when the ratio ⁇ is 0.40 or less, the angle ⁇ is 72 degrees or more, when the ratio ⁇ is 0.45 or less, the angle ⁇ is 74 degrees or more, and when the ratio ⁇ is 0.50 or less, the angle ⁇ is 75 degrees or more, thereby making it possible to set the ratio Pa to 1 x 10-4 or less, which is even more preferable.
  • the angle ⁇ is 68 degrees or more, if the ratio ⁇ is 0.30 or less, the angle ⁇ is 70 degrees or more, if the ratio ⁇ is 0.33 or less, the angle ⁇ is 71 degrees or more, if the ratio ⁇ is 0.35 or less, the angle ⁇ is 71 degrees or more, if the ratio ⁇ is 0.38 or less, the angle ⁇ is 72 degrees or more, if the ratio ⁇ is 0.40 or less, the angle ⁇ is 73 degrees or more, if the ratio ⁇ is 0.45 or less, the angle ⁇ is 74 degrees or more, and if the ratio ⁇ is 0.50 or less, the angle ⁇ is 75 degrees or more, which is preferable.
  • the angle ⁇ is 69 degrees or more, when the ratio ⁇ is 0.30 or less, the angle ⁇ is 71 degrees or more, when the ratio ⁇ is 0.33 or less, the angle ⁇ is 72 degrees or more, when the ratio ⁇ is 0.35 or less, the angle ⁇ is 73 degrees or more, when the ratio ⁇ is 0.38 or less, the angle ⁇ is 74 degrees or more, when the ratio ⁇ is 0.40 or less, the angle ⁇ is 74 degrees or more, when the ratio ⁇ is 0.45 or less, the angle ⁇ is 76 degrees or more, and when the ratio ⁇ is 0.50 or less, the angle ⁇ is 77 degrees or more, whereby the ratio Pa can be set to 1 x 10-4 or less, which is even more preferable.
  • ratio Pa and ratio Pb are the same or approximately the same, so ratio Pa in Figures 8A and 8B and the above description can be replaced with ratio Pb.
  • the difference between the thickness Td and the thickness Ta of the insulating layer 106 is large. It is preferable that the difference between the thickness Td and the thickness Tb of the insulating layer 106 is large. In other words, it is preferable that the ratio of the thickness Td to the thickness Ta is large. It is preferable that the ratio of the thickness Td to the thickness Tb is large.
  • the thickness Td can be expressed by the formula (26) using the thickness Ta.
  • ⁇ is the ratio of the thickness Td to the thickness Ta, and is a dimensionless quantity.
  • the ratio ⁇ is a real number greater than 0.
  • the ratio ⁇ corresponds to " ⁇ /cos ⁇ " in the formula (19).
  • the ratio Pa can be expressed by the formula (27). If the thicknesses Tb and Ta of the insulating layer 106 are the same, the ratio Pb can be expressed by the formula (28).
  • the ratios Pa and Pb can be expressed by the ratio ⁇ of the standard deviation s to the projected range m, and the ratio ⁇ of the thickness Td to the thickness Ta of the insulating layer 106, respectively. It is preferable to set the ratio ⁇ according to the ratio ⁇ so that the ratios Pa and Pb are each within the aforementioned range. As shown in formulas (27) and (28), the larger the ratio ⁇ , the smaller the ratios Pa and Pb can be. In other words, the larger the ratio of the thickness Td to the thickness Ta, the smaller the ratios Pa and Pb can be.
  • Figure 9 shows the relationship between the ratio ⁇ and the ratio Pa.
  • the horizontal axis represents the angle ⁇
  • the vertical axis represents the ratio Pa.
  • Figure 9 shows the ratio Pa when the ratio ⁇ is varied to 0.25, 0.30, 0.33, 0.35, 0.38, 0.40, 0.45, and 0.50.
  • the ratio ⁇ when the ratio ⁇ is 0.25 or less, the ratio ⁇ is set to 2.0 or more, when the ratio ⁇ is 0.30 or less, the ratio ⁇ is set to 2.2 or more, when the ratio ⁇ is 0.33 or less, the ratio ⁇ is set to 2.3 or more, when the ratio ⁇ is 0.35 or less, the ratio ⁇ is set to 2.4 or more, when the ratio ⁇ is 0.38 or less, the ratio ⁇ is set to 2.5 or more, when the ratio ⁇ is 0.40 or less, the ratio ⁇ is set to 2.5 or more, when the ratio ⁇ is 0.45 or less, the ratio ⁇ is set to 2.7 or more, and when the ratio ⁇ is 0.50 or less, the ratio ⁇ is set to 2.9 or more, which is preferable to make the ratio Pa 1 ⁇ 10 ⁇ 3 or less.
  • the ratio ⁇ is set to 2.1 or more, when the ratio ⁇ is 0.30 or less, the ratio ⁇ is set to 2.3 or more, when the ratio ⁇ is 0.33 or less, the ratio ⁇ is set to 2.5 or more, when the ratio ⁇ is 0.35 or less, the ratio ⁇ is set to 2.6 or more, when the ratio ⁇ is 0.38 or less, the ratio ⁇ is set to 2.7 or more, when the ratio ⁇ is 0.40 or less, the ratio ⁇ is set to 2.8 or more, when the ratio ⁇ is 0.45 or less, the ratio ⁇ is set to 3.0 or more, and when the ratio ⁇ is 0.50 or less, the ratio ⁇ is set to 3.2 or more, whereby the ratio Pa can be set to 1 ⁇ 10-4 or less, which is even more preferable.
  • ratio Pa and ratio Pb will also be the same or approximately the same, so ratio Pa in FIG. 9 and the above description can be replaced with ratio Pb.
  • the ratio Pa and the ratio Pb can each be set to 1 ⁇ 10 ⁇ 3 or less, and by setting the ratio ⁇ to 2.7 degrees or more, the ratio Pa and the ratio Pb can each be set to 1 ⁇ 10 ⁇ 4 or less.
  • the ratios Pa and Pb can be reduced. Furthermore, depending on the impurity element used and the film density of the insulating layer 106, by increasing the ratio ⁇ , the ratios Pa and Pb can be reduced.
  • the amount of impurity element supplied to the channel formation region is small. More specifically, it is preferable that the amount of impurity element supplied to the region of the semiconductor layer 108 that contacts the insulating layer 110b is small. Therefore, in a cross-sectional view, it is more preferable that the thickness Te of the insulating layer 106 on a straight line extending from the top surface end of the insulating layer 110b in the direction in which the impurity element is supplied (here, the direction perpendicular to the top surface of the substrate 102) is large. It is more preferable that the thickness Te is at least the same as the thickness Td, or approximately the same as the thickness Td.
  • the thickness Ha, Hb, and Hc are thicknesses in a direction perpendicular or approximately perpendicular to the surface on which the semiconductor layer 108 is formed. More specifically, the thickness Ha is the shortest distance between the upper surface of the conductive layer 112a and the upper surface of the semiconductor layer 108. The thickness Hb is the shortest distance between the upper surface of the conductive layer 112b and the upper surface of the semiconductor layer 108.
  • the thickness Hc is the shortest distance between the side of the insulating layer 110 and the side of the semiconductor layer 108 on the insulating layer 106 side. Although the thicknesses Ha, Hb, and Hc are the same in FIG. 4 and FIG. 7, one embodiment of the present invention is not limited thereto. The thicknesses Ha, Hb, and Hc may be configured to be partially or entirely different.
  • the sum of the thickness Tb of the insulating layer 106 provided along the upper surface of the insulating layer 110b, the thickness Hb of the semiconductor layer 108, the thickness T112b of the conductive layer 112b, and the thickness T110c of the insulating layer 110c is K.
  • the sum K is the distance between the upper surface of the insulating layer 106 provided along the upper surface of the conductive layer 112b and the upper surface of the insulating layer 110b in the direction in which the impurity element is supplied (here, the direction perpendicular to the upper surface of the substrate 102). If the sum K is small, the thickness Te of the insulating layer 106 may be thinner than the thickness Td (see region B in FIG. 4 or FIG. 7).
  • the sum K is thick. Also, as shown in formula (30), the sum of the thickness Hd of the semiconductor layer 108 and the thickness Td of the insulating layer 106 is L. As shown in formula (31), the sum K is preferably equal to or greater than the sum L. This allows the thickness Te of the insulating layer 106 to be thick.
  • the thicknesses Tb and Td of the insulating layer 106, the thicknesses Hb and Hd of the semiconductor layer 108, the thickness T112b of the conductive layer 112b, and the thickness T110c of the insulating layer 110c so as to satisfy formula (31).
  • the thickness Td can be expressed by formula (32). If the thicknesses Hb and Hc of the semiconductor layer 108 are the same, the thickness Hd can be expressed by formula (33). The sum L can be expressed by formula (34).
  • the angle ⁇ when the angle ⁇ is greater than 0 degrees and less than 90 degrees, it is preferable to increase the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c as the angle ⁇ increases. Specifically, it is preferable to increase one or both of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c as the angle ⁇ increases.
  • the angle ⁇ is 60 degrees or less, it is more preferable that the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is at least equal to or greater than the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the angle ⁇ is 65 degrees or less, it is more preferable that the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is at least 1.4 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the angle ⁇ is 70 degrees or less, it is more preferable that the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is at least 2.0 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the angle ⁇ is 75 degrees or less, it is more preferable that the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is at least 2.9 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the angle ⁇ is 80 degrees or less, it is more preferable that the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is at least 4.8 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the thicknesses Tb and Tc of the insulating layer 106 are the same, and the thicknesses Hb and Hc of the semiconductor layer 108 are the same, one embodiment of the present invention is not limited to this.
  • a configuration in which the thicknesses Tb and Tc are different from each other is also possible.
  • a configuration in which the thicknesses Hb and Hc are different from each other is also possible. Even in such cases, it is preferable to set the thicknesses of each layer so as to satisfy formula (31).
  • the thickness Tc of the insulating layer 106 is 0.85 times the thickness Tb
  • the thickness Hc of the semiconductor layer 108 is 0.85 times the thickness Hb.
  • the sum L can be expressed as "0.85 x (Tb + Hb) / cos ⁇ ", which can be applied to formula (31).
  • the angle ⁇ is 60 degrees or less, it is more preferable that the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is at least 0.7 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the angle ⁇ is 65 degrees or less, it is more preferable that the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is at least 1.1 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably at least 1.5 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably at least 2.3 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the sum of the thickness T112b of the conductive layer 112b and the thickness T110c of the insulating layer 110c is more preferably at least 3.9 times the sum of the thickness Tb of the insulating layer 106 and the thickness Hb of the semiconductor layer 108.
  • the concentration ratios Pa and Pb of the impurity elements are small.
  • the angle ⁇ can be determined so that the ratios Pa and Pb are each within the ranges mentioned above.
  • Region 108Da and region 108Db can each be configured to have a second element in addition to a first element as an impurity element.
  • the second element is different from the first element.
  • the second element one or more of the elements that can be used as the first element described above can be used. It is preferable that the second element has a larger mass number than the first element. It is also preferable that the first element is easily bonded to oxygen. For example, boron or phosphorus can be used as the first element, and argon, krypton, or xenon can be used as the second element.
  • the first element can be supplied to the semiconductor layer 108.
  • the mass number of the supplied element is large, the number of metal-oxygen bonds broken in the metal oxide of the semiconductor layer 108 increases. Furthermore, oxygen vacancies (V 2 O 3 ) occur in the region that will become the region 108Da and the region that will become the region 108Db due to the breaking of the metal-oxygen bonds.
  • oxygen vacancies are generated in the channel formation region, which may increase VOH and increase the carrier concentration.
  • concentration of the second element in the channel formation region is preferably lower than the concentration of the second element in the region 108Da.
  • the concentration of the second element in the channel formation region is preferably lower than the concentration of the second element in the region 108Db.
  • the second element is preferably supplied to the semiconductor layer 108 through the insulating layer 106.
  • the first element is preferably supplied to the semiconductor layer 108 through the insulating layer 106.
  • the insulating layer 106 may also contain the second impurity element.
  • the second element is preferably supplied from a direction perpendicular or approximately perpendicular to the upper surface of the substrate 102.
  • the second element can be supplied by a method that can be used to supply the first element.
  • plasma ion doping or ion implantation can be preferably used to supply the second element.
  • the amount of the second element supplied to the channel formation region can be reduced by setting the angle ⁇ of the insulating layer 110 or the thickness Td of the insulating layer 106 to the above-mentioned range, which is preferable.
  • the acceleration energy when supplying the second element is higher than the acceleration energy when supplying the first element. This increases the amount of the second element supplied to the regions 108Da and 108Db, and the electrical resistance of the regions 108Da and 108Db can be efficiently reduced.
  • the first element and the second element can be supplied in the same process.
  • the first element and the second element can be supplied to the semiconductor layer 108 using a source gas containing the first element and the second element.
  • a plasma ion doping method can be suitably used for supplying the first element and the second element.
  • a mixed gas of a gas containing the first element and a gas containing the second element can be used as the source gas.
  • a mixed gas of BF 3 gas and Ar gas can be used.
  • the source gas is not limited to the mixed gas, and a gas containing the first element and the second element can also be used as the source gas.
  • a step may be formed between the insulating layer 110 and the conductive layer 112b, and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step.
  • Metal oxides that can be used for the semiconductor layer 108 will be specifically described.
  • metal oxides include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide preferably contains one or more elements selected from indium, element M, and zinc.
  • the element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a bond energy with oxygen higher than that of indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification may include metalloid elements.
  • the semiconductor layer 108 may be, for example, indium zinc oxide (In-Zn oxide, also referred to as IZO (registered trademark)), indium tin oxide (In-Sn oxide, also referred to as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also referred to as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide), Indium aluminum zinc oxide (In-Al-Zn oxide, also written as AZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga
  • the metal oxide may have one or more metal elements with a higher period number in the periodic table instead of or in addition to indium.
  • metal elements with a higher period number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • Specific examples of the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all contained metal elements may be referred to as the indium content.
  • the sum of the ratios of the number of atoms of element M to the sum of the numbers of atoms of all contained metal elements can be taken as the content of element M.
  • Increasing the zinc content in the metal oxide results in a highly crystalline metal oxide, which can suppress the diffusion of impurities in the metal oxide. This suppresses fluctuations in the electrical characteristics of the transistor, and increases reliability.
  • the metal oxide By increasing the content of element M in the metal oxide, the metal oxide can have a large band gap. Furthermore, by suppressing the formation of oxygen vacancies (V 2 O 3 ) in the metal oxide, carrier generation due to oxygen vacancies (V 2 O 3 ) can be suppressed, and a shift in the threshold voltage of the transistor can be suppressed. As a result, the cutoff current can be reduced, and a normally-off transistor can be obtained. Furthermore, a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide applied to the semiconductor layer 108. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, it is possible to obtain a semiconductor device that has both excellent electrical characteristics and high reliability.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of element M.
  • the atomic ratio of In in the In-M-Zn oxide can be less than the atomic ratio of element M.
  • the sum of the atomic ratios of these elements can be regarded as the atomic ratio of element M.
  • the on-current or field effect mobility of the transistor can be increased. Furthermore, by having the element M, the generation of oxygen vacancies (V 0 ) can be suppressed.
  • the content of the element M (the ratio of the number of atoms of the element M to the sum of the number of atoms of all metal elements contained) is preferably 0.1% to 25% or less, more preferably 0.1% to 20% or less, more preferably 0.1% to 10% or less, more preferably 0.1% to 8% or less, more preferably 0.1% to 6% or less, and even more preferably 0.1% to 4% or less. This allows a transistor with good electrical characteristics to be obtained.
  • the element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium.
  • the grain boundaries become recombination centers, and carriers are captured, which may reduce the on-current of the transistor.
  • a polycrystalline metal oxide is used for the semiconductor layer 108, the surface of the semiconductor layer 108 may become uneven. This increases the step on the surface on which a layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 is formed, and defects such as breaks or pores may occur in the layer.
  • a metal oxide having a composition that is likely to form a polycrystalline structure is used for the semiconductor layer 108, it is preferable to include an element that inhibits crystallization.
  • the semiconductor layer 108 prevents the semiconductor layer 108 from becoming a polycrystalline structure, and a transistor with a large on-current can be obtained.
  • the coverage of the layer (e.g., the insulating layer 106) formed on the semiconductor layer 108 can be improved, and defects such as breaks or pores in the layer can be suppressed.
  • indium tin oxide (ITSO) containing silicon is less likely to have a polycrystalline structure, and therefore can be suitably used for the semiconductor layer 108.
  • the silicon content (the ratio of the number of silicon atoms to the sum of the numbers of atoms of all metal elements contained) is preferably 1 atomic% or more and 20 atomic% or less, more preferably 3 atomic% or more and 20 atomic% or less, more preferably 3 atomic% or more and 15 atomic% or less, and even more preferably 5 atomic% or more and 15 atomic% or less.
  • indium tin oxide (ITSO) containing silicon is used for the semiconductor layer 108, it is preferable that it has crystallinity.
  • the semiconductor layer 108 may have an amorphous region or may be amorphous.
  • a metal oxide that does not contain element M can be applied to the semiconductor layer 108.
  • the metal oxide is an In-Zn oxide
  • the atomic ratio of In is equal to or greater than the atomic ratio of Zn.
  • the composition of the semiconductor layer 108 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES).
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • a combination of these techniques can be used for analysis. It is preferable to separate the peaks of the spectrum obtained by the analysis and identify and quantify the elements.
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content, may be difficult to quantify, or may be below the detection limit
  • the sputtering method or the ALD method can be suitably used to form the metal oxide.
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the semiconductor layer 108 is preferably made of a crystalline metal oxide.
  • a crystalline metal oxide examples include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystalline (nc: nano-crystal) structure.
  • the semiconductor layer 108 is preferably made of CAAC-OS or nc-OS.
  • CAAC-OS has multiple layered crystals.
  • the c-axis of the crystals is oriented in the normal direction of the surface on which the semiconductor layer 108 is formed.
  • the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the surface on which the semiconductor layer 108 is formed.
  • the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the top surface in a region in contact with the top surface of the conductive layer 112b, and has layered crystals parallel or approximately parallel to the side surface in a region in contact with the side surface of the conductive layer 112b.
  • the semiconductor layer 108 preferably has layered crystals parallel or approximately parallel to the side surface of the insulating layer 110, which is the surface on which the semiconductor layer 108 is formed, in the opening 141.
  • the layered crystals of the semiconductor layer 108 are formed parallel or approximately parallel to the channel length direction of the transistor 100, and thus the transistor can have a large on-current.
  • the density of defect states in the channel formation region can be reduced.
  • a metal oxide with low crystallinity a transistor capable of passing a large current can be realized.
  • the substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation. Also, the higher the oxygen flow rate ratio of the deposition gas used for formation, or the oxygen partial pressure in the processing chamber, the more crystalline the metal oxide that can be formed.
  • the crystallinity of the semiconductor layer 108 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis can be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • VOH When a metal oxide is used for the semiconductor layer 108, it is preferable to reduce VOH in the channel formation region as much as possible to make it highly pure or substantially highly pure.
  • it is important to remove impurities such as water and hydrogen in the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies ( VOH ).
  • impurities such as water and hydrogen in the metal oxide
  • VOH oxygen vacancies
  • supplying oxygen to a metal oxide to repair oxygen vacancies ( VOH ) may be referred to as oxygen addition treatment.
  • the carrier concentration of the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , even more preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and even more preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the carrier concentration of the channel formation region can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 100, and the region in contact with the conductive layer 112b functions as the other.
  • the source and drain regions are regions with lower electrical resistance than the channel formation region.
  • the source and drain regions can also be said to be regions with a higher carrier concentration and a higher oxygen defect density than the channel formation region.
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., they have high resistance to radiation, and therefore can be suitably used in environments where radiation may be present. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be suitably used in semiconductor devices used in outer space.
  • radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).
  • the semiconductor layer 108 may have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • the insulating layer 110 preferably has a stacked structure.
  • the insulating layer 110b has a function of supplying oxygen to a channel formation region.
  • the insulating layers 110a and 110c function as barrier films.
  • the thickness T110a of the insulating layer 110a is preferably 3 nm or more and 500 nm or less, more preferably 5 nm or more and 400 nm or less, more preferably 10 nm or more and 300 nm or less, more preferably 20 nm or more and 300 nm or less, more preferably 50 nm or more and 300 nm or less, more preferably 100 nm or more and 300 nm or less, more preferably 100 nm or more and 250 nm or less, more preferably 150 nm or more and 250 nm or less. As shown in FIG.
  • the thickness T110a of the insulating layer 110a can be made thicker than the thickness T110c of the insulating layer 110c.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110a functions as a source region or a drain region
  • the distance from the source region or the drain region to the gate electrode can be made more uniform by making the thickness T110a thicker. This makes it possible to make the electric field of the gate electrode applied to the channel formation region more uniform.
  • the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the upper surface of the insulating layer 110c in a cross-sectional view.
  • the thickness T110c of the insulating layer 110c is preferably 3 nm or more and 200 nm or less, more preferably 3 nm or more and 100 nm or less, even more preferably 3 nm or more and 50 nm or less, even more preferably 3 nm or more and 30 nm or less, even more preferably 3 nm or more and 20 nm or less, even more preferably 3 nm or more and 10 nm or less, even more preferably 5 nm or more and 10 nm or less.
  • the thickness T110c is preferably a value that functions as a barrier film against oxygen.
  • the thickness T110c can be thinner than the thickness T110a. If the thickness T110c of the insulating layer 110c is thick, the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, if the thickness T110c is thin, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b side through the insulating layer 110c, and the amount of oxygen supplied to the channel formation region may decrease.
  • the thickness T110c By setting the thickness T110c within the above range, the amount of oxygen supplied to the channel formation region can be increased, and oxygen vacancies (V O ) and V O H in the channel formation region can be reduced.
  • the conductive layer 112b is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112b can be suppressed from increasing. Note that the thickness T110c is not limited to the above range.
  • At least one of the regions of the semiconductor layer 108 in contact with the insulating layer 110a and the insulating layer 110c can be a region having a lower electrical resistance than the channel formation region (hereinafter, also referred to as a low-resistance region).
  • the region can also be said to be a region having a higher carrier concentration and a higher oxygen defect density than the channel formation region.
  • impurities e.g., water and hydrogen
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region of the semiconductor layer 108 in contact with the insulating layer 110c can be a low-resistance region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region.
  • the low resistance regions can function as buffer regions to reduce the drain electric field. These low resistance regions can also function as source or drain regions.
  • impurities released from the insulating layer 110a may diffuse into the channel formation region through the insulating layer 110b or through one of the source region and the drain region of the semiconductor layer 108.
  • impurities released from the insulating layer 110c may diffuse into the channel formation region through the insulating layer 110b or through the other of the source region and the drain region of the semiconductor layer 108.
  • oxygen is supplied from the insulating layer 110b to at least the region of the semiconductor layer 108 in contact with the insulating layer 110b, so that oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. This suppresses the shift of the threshold voltage, and a transistor having both a small cutoff current and a large on-current can be obtained. Therefore, a semiconductor device having both low power consumption and high performance can be obtained.
  • the amount of impurities released from the insulating layers 110a and 110c becomes too large, the amount of oxygen vacancies ( VO ) and VOH generated by the impurities may be greater than the amount of oxygen vacancies ( VO ) and VOH repaired by oxygen supplied from the insulating layer 110b. Even when a material that releases impurities is used for the insulating layers 110a and 110c, it is more preferable that the amount of released impurities is small.
  • One or more of the insulating layers 110a, 110b, and 110c may have a laminated structure.
  • the materials mentioned in the description of the insulating layer 110c can be used for each layer constituting the insulating layer 110c.
  • An oxide or an oxynitride can be preferably used for the layer provided on the insulating layer 110b side. More specifically, one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, and gallium zinc oxide can be particularly preferably used for the layer provided on the insulating layer 110b side.
  • the insulating layer 110c can have a laminated structure of, for example, a first film having an oxide or an oxynitride and a second film having a nitride or a nitride oxide on the first film. More specifically, the insulating layer 110c can have a laminated structure of, for example, an aluminum oxide film and a silicon nitride film on the aluminum oxide film.
  • the upper surface shape of the opening 141 and the opening 143 is not limited, and each of them may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a rhombus, and a square), a polygon such as a pentagon, or a shape with rounded corners of these polygons.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • the upper surface shape of the opening 141 and the opening 143 is preferably a circle.
  • the top shape of the opening 141 refers to the shape of the top end of the insulating layer 110 on the opening 141 side.
  • the top shape of the opening 143 refers to the shape of the bottom end of the conductive layer 112b on the opening 143 side.
  • the top shapes of the openings 141 and 143 can be made to match or approximately match each other.
  • the bottom end of the conductive layer 112b on the opening 143 side is made to match or approximately match the top end of the insulating layer 110 on the opening 141 side.
  • the bottom surface of the conductive layer 112b refers to the surface on the insulating layer 110 side.
  • the top surface of the insulating layer 110 refers to the surface on the conductive layer 112b side.
  • the top shapes of the openings 141 and 143 can be configured not to match each other. When the top shapes of the openings 141 and 143 are circular, the openings 141 and 143 may or may not be concentric.
  • the channel length and channel width of transistor 100 are explained using Figures 3A and 3B.
  • the channel length L100 of the transistor 100 is indicated by a double-headed dashed arrow.
  • the channel length L100 of the transistor 100 corresponds to the length of the side of the insulating layer 110b on the opening 141 side in a cross-sectional view.
  • the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle ⁇ 110b between the side of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the minimum exposure dimension of the exposure device, and a transistor of a fine size can be realized.
  • a transistor with an extremely short channel length that could not be realized with a conventional exposure device for mass production of flat panel displays (for example, a minimum dimension of about 2 ⁇ m or 1.5 ⁇ m).
  • a transistor with a channel length of less than 10 nm without using an extremely expensive exposure device used in cutting-edge LSI technology.
  • the cross-sectional view shown in FIG. 3 shows a configuration in which the top surface of the insulating layer 110a, the top surface of the conductive layer 112a, and the top surface of the substrate 102 are parallel to one another.
  • the angle ⁇ 110b is the same as the angle ⁇ shown in FIG. 4.
  • the angle ⁇ please refer to the above description.
  • the channel length L100 can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length L100 can be 100 nm or more and 1 ⁇ m or less.
  • the on-state current of the transistor 100 can be increased.
  • the transistor 100 By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-definition display device, even if the number of wirings is increased, signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • the channel length L100 can be controlled by adjusting the thickness T110b and angle ⁇ 110b of the insulating layer 110b.
  • the thickness T110b of the insulating layer 110b can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the angle ⁇ 110b is shown as less than 90 degrees, but this is not a limitation of one embodiment of the present invention. As shown in FIG. 10, the angle ⁇ 110b can be set to 90 degrees or approximately 90 degrees. This allows the channel length L100 of the transistor 100 to be shortened.
  • the impurity element passes through the insulating layer 106, the region of the semiconductor layer 108 that contacts the conductive layer 112b, and the region that contacts the insulating layer 110c, in order to reach the channel formation region.
  • the impurity element passes through the insulating layer 106 with a thickness Tb and the semiconductor layer 108 with a thickness equal to the sum of the thickness Hb, the thickness T112b, and the thickness T110c (see FIG. 4). Therefore, the depth of the channel formation region is deeper than the depth of the region provided along the upper surface of the conductive layer 112b.
  • the concentration Nc of the impurity element in the channel formation region is lower than the concentration Nb of the impurity element in the region 108Db.
  • the concentration Nc is also lower than the concentration Na of the impurity element in the region 108Da.
  • the conductive layer 112b is not provided inside the opening 141. Specifically, it is preferable that the conductive layer 112b does not have a region in contact with the side surface of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side surface of the insulating layer 110b, and it may become difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 matches the top shape of the opening 141, or that the opening 143 encompasses the opening 141 in a top view (also referred to as a plan view).
  • the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region
  • one embodiment of the present invention is not limited to this.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region.
  • the region in contact with the insulating layer 110c may also function as a channel formation region.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each be made of a metal oxide having electrical conductivity (also called an oxide conductor).
  • oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called ITO containing silicon, ITSO), zinc oxide to which gallium is added, and In-Ga-Zn oxide.
  • oxide conductors containing indium are preferred because of their high electrical conductivity.
  • a metal oxide that has become a conductor can be called an oxide conductor.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) described above and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can be made of the same material. Alternatively, at least one of them can be made of a different material.
  • the conductive layer 112a and the conductive layer 112b each have a region in contact with the semiconductor layer 108.
  • an oxide semiconductor is used for the semiconductor layer 108
  • a metal that is easily oxidized e.g., aluminum
  • an insulating oxide e.g., aluminum oxide
  • the conductive layer 112a and the conductive layer 112b are preferably made of, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a or the conductive layer 112b has a stacked structure, it is preferable to use a conductive material that is difficult to oxidize at least for the layer in contact with the semiconductor layer 108.
  • the conductive layer 112a and the conductive layer 112b may each be made of a nitride conductor.
  • nitride conductors include tantalum nitride and titanium nitride.
  • the conductive layer 104 may also be made of the nitride conductor described above.
  • One or more of the conductive layers 112a, 112b, and 104 can have a stacked structure.
  • the semiconductor device 10A has a transistor 100A and an insulating layer 110.
  • the transistor 100A differs mainly from the transistor 100 shown in FIG. 1B etc. in that the conductive layer 112a has a stacked structure.
  • Figures 11A and 11B show a configuration in which the conductive layer 112a has a two-layer structure consisting of a conductive layer 112a_1 and a conductive layer 112a_2 on the conductive layer 112a_1.
  • the conductive layer 112a_2 having a region in contact with the semiconductor layer 108 is preferably made of a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductor.
  • the conductive layer 112a_2 can be made of any of the materials listed in the description of the conductive layer 112a.
  • the material used is not particularly limited. For example, it is preferable to use a material having a lower electrical resistivity than the conductive layer 112a_2 for the conductive layer 112a_1. This can reduce the electrical resistance of the conductive layer 112a. For example, it is preferable to use In-Sn-Si oxide (ITSO) for the conductive layer 112a_2, and copper or tungsten for the conductive layer 112a_1.
  • ITSO In-Sn-Si oxide
  • the end of conductive layer 112a_2 can be configured to be aligned or approximately aligned with the end of conductive layer 112a_1.
  • a first film that will become conductive layer 112a_1 and a second film that will become conductive layer 112a_2 are formed, and a mask layer (e.g., photoresist) is formed on the second film.
  • the first film and the second film are processed using the mask layer as a mask to form conductive layer 112a.
  • manufacturing costs can be reduced.
  • the end of the conductive layer 112a_2 may not be aligned with the end of the conductive layer 112a_1.
  • the conductive layer 112a_2 may be provided so as to cover the conductive layer 112a_1.
  • the conductive layer 112a_2 has a region in contact with the upper surface and side surface of the conductive layer 112a_1. It can also be said that the conductive layer 112a_2 has a portion protruding from the end of the conductive layer 112a_1.
  • the conductive layer 112a_1 may be formed, a film to become the conductive layer 112a_2 may be formed on the conductive layer 112a_1, and the film may be processed to form the conductive layer 112a_2.
  • the step of the surface to be formed of the layer (e.g., the insulating layer 110) formed on the conductive layer 112a is reduced, and the coverage of the layer can be improved. This can suppress the occurrence of defects such as step discontinuities or porosity in the layer.
  • the layers constituting the conductive layer 112a are shown to have the same or approximately the same thickness, but one embodiment of the present invention is not limited to this.
  • the layers constituting the conductive layer 112a may have different thicknesses in part or all. For example, by making the layer using a material with low electrical resistivity thicker than the other layers, the electrical resistance of the conductive layer 112a can be lowered, which is more preferable. Specifically, a material with lower electrical resistivity than the conductive layer 112a_2 can be used for the conductive layer 112a_1, and the thickness of the conductive layer 112a_1 can be made thicker than the thickness of the conductive layer 112a_2. This can lower the electrical resistance of the conductive layer 112a.
  • FIGS. 11C and 11D show a configuration in which the conductive layer 112a has a three-layer structure consisting of a conductive layer 112a_3, a conductive layer 112a_1 on the conductive layer 112a_3, and a conductive layer 112a_2 on the conductive layer 112a_1.
  • the end of the conductive layer 112a_1 can be configured to be in contact with the upper surface of the conductive layer 112a_3.
  • the conductive layer 112a_2 has an area in contact with the upper surface and side surface of the conductive layer 112a_1 and the upper surface of the conductive layer 112a_3.
  • the conductive layer 112a_2 and the conductive layer 112a_3 each have a portion that protrudes beyond the end of the conductive layer 112a_1.
  • the upper surface, side surface, and lower surface of the conductive layer 112a_1 are surrounded by the conductive layer 112a_2 and the conductive layer 112a_3. It is preferable to use a material for the conductive layer 112a_3 that has high adhesion to the surface on which the conductive layer 112a_3 is formed (here, the surface of the substrate 102).
  • the adhesiveness between the conductive layer 112a_1 and the surface on which the conductive layer 112a_1 is formed may be low, which may result in a low manufacturing yield of the semiconductor device.
  • the manufacturing yield of the semiconductor device can be increased.
  • the thickness of the conductive layer 112a_3 can be set to a thickness that has the effect of increasing the adhesiveness of the conductive layer 112a to the surface on which the conductive layer 112a is formed, and can be thinner than the thicknesses of the conductive layer 112a_1 and the conductive layer 112a_2. By reducing the thickness of the conductive layer 112a_3, the manufacturing cost can be reduced.
  • In-Sn-Si oxide can be suitably used for the conductive layer 112a_3, copper for the conductive layer 112a_1, and In-Sn-Si oxide (ITSO) for the conductive layer 112a_2.
  • the adhesion between the glass substrate and the ITSO film is higher than that between the glass substrate and the copper film.
  • the processing when forming the conductive layer 112a_2 and the conductive layer 112a_3 in the same process becomes easier, and the manufacturing yield of the semiconductor device can be increased.
  • the end of the conductive layer 112a_2 can be aligned or approximately aligned with the end of the conductive layer 112a_3.
  • a first film that will become the conductive layer 112a_3 is formed
  • a conductive layer 112a_1 is formed on the first film
  • a second film that will become the conductive layer 112a_2 is formed on the first film and the conductive layer 112a_1.
  • a mask layer e.g., photoresist
  • the first film and the second film are processed using the mask layer as a mask, thereby forming the conductive layer 112a having the conductive layer 112a_3, the conductive layer 112a_1, and the conductive layer 112a_2.
  • the manufacturing cost can be reduced.
  • the end of the conductive layer 112a_1 can be aligned or approximately aligned with the end of the conductive layer 112a_3.
  • the conductive layer 112a has a two-layer or three-layer stacked structure, but one embodiment of the present invention is not limited to this.
  • the conductive layer 112a can also have a four or more layer stacked structure.
  • the insulating layer 106 preferably includes one or more inorganic insulating layers.
  • the insulating layer 106 can be made of any of the materials that can be used for the insulating layer 110.
  • the insulating layer 106 has regions in contact with the semiconductor layer 108, the conductive layer 112b, the conductive layer 104, and the insulating layer 110.
  • a metal oxide is used for the semiconductor layer 108, it is preferable to use any of the above-mentioned oxides and oxynitrides for at least the film that is in contact with the semiconductor layer 108 among the films that constitute the insulating layer 106.
  • the insulating layer 106 has a single-layer structure, silicon oxide, silicon oxynitride, or aluminum oxide can be suitably used for the insulating layer 106.
  • the thickness of the gate insulating layer becomes thin, the leakage current may become large.
  • a material with a high relative dielectric constant also called a high-k material
  • high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • the insulating layer 106 is shown as having a single-layer structure, but one embodiment of the present invention is not limited to this.
  • the insulating layer 106 can have a stacked structure of two or more layers.
  • FIG. 12 shows a configuration in which the insulating layer 106 has a two-layer structure of an insulating layer 106a and an insulating layer 106b on the insulating layer 106a.
  • the insulating layer 110 can have a structure in which the insulating layer 110 has insulating layers 110a, 110b, 110c, and 110e.
  • the insulating layer 110e uses a material that releases impurities that reduce the electrical resistance of the conductive layer 112b. This can reduce the electrical resistance of the conductive layer 112b.
  • the impurities contain hydrogen.
  • the insulating layer 110 can also have a structure in which the insulating layer 110 has an insulating layer 110d.
  • the insulating layer 110 can be configured to have insulating layer 110a, insulating layer 110b, insulating layer 110c, insulating layer 110d, and insulating layer 110e.
  • the insulating layer 110 can be configured to contact the side of the insulating layer 109.
  • the end of the insulating layer 109 can be configured to be aligned or approximately aligned with the end of the conductive layer 112a.
  • an insulating film that will become the insulating layer 109 and a conductive film that will become the conductive layer 112a can be formed and processed to form the insulating layer 109 and the conductive layer 112a.
  • the end of the insulating layer 109 may not be aligned with the end of the conductive layer 112a. As shown in FIG. 16B, the insulating layer 109 may have a portion that protrudes beyond the end of the conductive layer 112a. The end of the conductive layer 112a contacts the upper surface of the insulating layer 109. With this configuration, the step on the surface on which the conductive layer 112a and the layer (e.g., insulating layer 110) formed on the insulating layer 109 are formed is reduced, and the coverage of the layer can be improved. This can prevent defects such as step discontinuities or voids in the layer.
  • the configuration of the insulating layer 109 shown in configuration example 1-3 can also be applied to other configuration examples.
  • the semiconductor device 10E has a transistor 100C and an insulating layer 110.
  • the transistor 100C differs from the transistor 100 shown in FIG. 1B etc. mainly in that the semiconductor layer 108 has a stacked structure.
  • the conduction band lower edge of the first metal oxide is preferably closer to the vacuum level than the conduction band lower edge of the second metal oxide.
  • the conduction band lower edge of the third metal oxide is preferably closer to the vacuum level than the conduction band lower edge of the second metal oxide.
  • the electron affinity of the first metal oxide is preferably smaller than the electron affinity of the second metal oxide.
  • the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the second metal oxide.
  • the band gaps of the first metal oxide, the second metal oxide, and the third metal oxide can be evaluated by optical evaluation using a spectrophotometer, spectroscopic ellipsometry, photoluminescence, X-ray photoelectron spectroscopy (XPS or ESCA), or X-ray absorption fine structure (XAFS).
  • the analysis can be performed by combining a plurality of these techniques.
  • the electron affinity or the bottom of the conduction band can be determined from the ionization potential, which is the difference in energy between the vacuum level and the top of the valence band, and the band gap.
  • the ionization potential can be evaluated by, for example, ultraviolet photoelectron spectroscopy (UPS).
  • Trap levels due to impurities or defects may be formed at the interface between the insulating layer 110 and the semiconductor layer 108 and in the vicinity thereof.
  • impurities include residual components of the etchant or etching gas used when forming the opening 141, and components of the conductive layers 112a and 112b that adhere to the side surfaces of the insulating layer 110 when forming the opening 141.
  • the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity may be damaged during the formation of the insulating layer 106. This may result in the formation of a trap level at the interface between the insulating layer 106 and the semiconductor layer 108 and its vicinity.
  • the semiconductor layer 108c By providing the semiconductor layer 108c between the semiconductor layer 108b and the insulating layer 106, the semiconductor layer 108b can be kept away from the trap level.
  • the composition of the first metal oxide is preferably different from that of the second metal oxide.
  • the composition of the third metal oxide is preferably different from that of the second metal oxide.
  • the band gap can be adjusted. Specifically, the content of element M in the first metal oxide and the content of element M in the third metal oxide are preferably higher than the content of element M in the second metal oxide. This allows the band gap of the first metal oxide and the band gap of the third metal oxide to be larger than the band gap of the second metal oxide.
  • the indium content in the second metal oxide is preferably higher than the indium content in the first metal oxide and the indium content in the third metal oxide. This allows a transistor with a large on-state current to be obtained.
  • the first metal oxide and the second metal oxide are In-M-Zn oxides
  • the element M in the first metal oxide, the element M in the second metal oxide, and the element M in the third metal oxide may be the same as each other, or may be partially or entirely different.
  • each element of the element M may be the same as the element M in the other metal oxide, or may be partially or entirely different.
  • the second metal oxide may be configured not to include element M.
  • the second metal oxide may be In-Zn oxide, and the first metal oxide and the third metal oxide may be In-M-Zn oxide.
  • the second metal oxide may be In-Zn oxide, and the first metal oxide and the third metal oxide may be In-M-Zn oxide.
  • Figure 18 shows an enlarged view of the side of insulating layer 110 and its vicinity.
  • the thickness T108a of semiconductor layer 108a, the thickness T108b of semiconductor layer 108b, and the thickness T108c of semiconductor layer 108c are each indicated by a solid double-headed arrow.
  • the thickness of semiconductor layer 108 is defined as the shortest distance between insulating layer 110 and insulating layer 106 in a cross-sectional view. Specifically, the thickness of each layer of semiconductor layer 108 at the midpoint between the height of the top surface and the height of the bottom surface of insulating layer 110 is shown.
  • the thickness T108b of the semiconductor layer 108b which is the main current path, a transistor with a large on-state current can be obtained.
  • the amount of oxygen vacancies (V O ) and V O H in the semiconductor layer 108b may be greater than the amount of oxygen vacancies (V O ) and V O H repaired by oxygen supplied from the insulating layer 110.
  • the thickness T108b is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, further preferably 3 nm or more and 20 nm or less, further preferably 5 nm or more and 20 nm or less, and further preferably 5 nm or more and 15 nm or less.
  • the thickness T108c of the semiconductor layer 108c is preferably thicker than the thickness T108a of the semiconductor layer 108a. By making the thickness T108c thicker, the semiconductor layer 108b can be separated from the trap level that may be formed at the interface between the insulating layer 106 and the semiconductor layer 108 and in the vicinity thereof. In addition, damage to the semiconductor layer 108b during the formation of the insulating layer 106 can be suppressed. If the thickness T108c is too thick, the distance between the conductive layer 104 functioning as the gate electrode and the semiconductor layer 108b becomes long, and the on-current may become small.
  • the thickness T108c is preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 20 nm or less, even more preferably 1 nm or more and 10 nm or less, and even more preferably 2 nm or more and 10 nm or less.
  • the oxygen contained in the insulating layer 110 is supplied to the semiconductor layer 108b through the semiconductor layer 108a. Therefore, it is preferable that the semiconductor layer 108a is easily permeable to oxygen.
  • the oxygen contained in the insulating layer 110 can be efficiently supplied to the semiconductor layer 108b. This makes it possible to reduce oxygen vacancies (V O ) and V O H in the semiconductor layer 108b, which is the main current path. If the thickness T108a is too thin, the distance between the interface between the insulating layer 110 and the semiconductor layer 108 and the trap level near the interface and the semiconductor layer 108b, which is the main current path, becomes shorter, and the on-current may become smaller. In addition, the reliability may deteriorate.
  • the thickness T108a is preferably 0.1 nm or more and 10 nm or less, more preferably 0.3 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, and even more preferably 0.5 nm or more and 3 nm or less.
  • the semiconductor layers 108a, 108b, and 108c each have crystallinity.
  • the crystallinity of the semiconductor layer 108b formed thereon can be increased.
  • the semiconductor layer 108b has crystallinity
  • the crystallinity of the semiconductor layer 108c formed thereon can be increased.
  • the band gap of the first metal oxide and the band gap of the third metal oxide can be different.
  • the band gap of the third metal oxide is preferably larger than the band gap of the first metal oxide.
  • the semiconductor layer 108a has a region in contact with the conductive layer 112a and the conductive layer 112b that function as a source electrode and a drain electrode.
  • the difference between the band gap of the first metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the conduction band lower edge of the third metal oxide is preferably closer to the vacuum level than the conduction band lower edge of the first metal oxide.
  • the electron affinity of the third metal oxide is preferably smaller than the electron affinity of the first metal oxide.
  • the content of element M in the third metal oxide is preferably higher than the content of element M in the first metal oxide. This allows the band gap of the third metal oxide to be larger than the band gap of the first metal oxide.
  • the first metal oxide, the second metal oxide, and the third metal oxide are In-M-Zn oxides
  • the second metal oxide may be configured not to include element M.
  • the second metal oxide may be an In-Zn oxide
  • the first metal oxide and the third metal oxide may be an In-M-Zn oxide.
  • the semiconductor layer 108 has a three-layer structure of semiconductor layers 108a, 108b, and 108c, but one embodiment of the present invention is not limited to this.
  • a structure that does not have one or both of the semiconductor layers 108a and 108c is also possible.
  • the semiconductor layer 108 can have a two-layer structure of the semiconductor layers 108a and 108b.
  • the semiconductor layer 108 can have a two-layer structure of the semiconductor layers 108b and 108c.
  • the semiconductor layer 108 can have a stacked structure of four or more layers.
  • configuration of the semiconductor layer 108 shown in configuration example 1-4 can also be applied to other configuration examples.
  • FIG 20A is a top view of a semiconductor device 10F according to one embodiment of the present invention
  • FIG 20B is a cross-sectional view taken along dashed dotted line A1-A2 in FIG 20A
  • FIG 20C is a cross-sectional view taken along dashed dotted line B1-B2 in FIG 20A.
  • the semiconductor device 10F has a transistor 100D and an insulating layer 110.
  • the transistor 100D differs from the transistor 100 shown in FIG. 1B etc. mainly in that the transistor 100D has a conductive layer 103 and an insulating layer 107.
  • the insulating layer 107 is located on the conductive layer 112a.
  • the insulating layer 107 is provided so as to cover the upper and side surfaces of the conductive layer 112a.
  • the conductive layer 103 is located on the insulating layer 107.
  • the conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 107.
  • the conductive layer 103 has an opening 148 that reaches the insulating layer 107 in the area that overlaps with the conductive layer 112a.
  • the insulating layer 110 is provided on the insulating layer 107 and the conductive layer 103.
  • the insulating layer 110 is provided so as to cover the upper and side surfaces of the conductive layer 103 and the upper surface of the insulating layer 107.
  • the insulating layer 110 and the insulating layer 107 are provided with an opening 141 that reaches the conductive layer 112a.
  • the thickness of the conductive layer 103 can be greater than the sum of the thickness of the portion of the semiconductor layer 108 that contacts the conductive layer 112a inside the opening 141 and the thickness of the insulating layer 106 that contacts that portion.
  • the conductive layer 112c can be formed using the same material as the conductive layer 112b.
  • the conductive layer 112c can be formed in the same process as the conductive layer 112b.
  • Transistor 100 and transistor 250 are each provided on substrate 102.
  • the semiconductor device 20B has a conductive layer 259 on the substrate 102, an insulating layer 252 on the substrate 102 and the conductive layer 259, and a semiconductor layer 253 on the insulating layer 252. It also has an insulating layer 254 on the insulating layer 252 and the semiconductor layer 253, and a conductive layer 255 on the insulating layer 254. The semiconductor layer 253 and the conductive layer 255 have an overlapping region.
  • the conductive layer 259 functions as a backgate electrode of the transistor 250, and the insulating layer 252 functions as a backgate insulating layer.
  • the insulating layer 254 functions as a gate insulating layer, and the conductive layer 255 functions as a gate electrode.
  • An insulating layer 256 is provided on the insulating layer 254 and the conductive layer 255.
  • An opening 257a is provided in the insulating layer 254 and the insulating layer 256 in a region overlapping with a part of the semiconductor layer 253.
  • An opening 257b is provided in the insulating layer 254 and the insulating layer 256 in a region overlapping with another part of the semiconductor layer 253.
  • a conductive layer 258a is provided on the insulating layer 256 and the opening 257a, and a conductive layer 258b is provided on the insulating layer 256 and the opening 257b.
  • the conductive layer 258a is electrically connected to the semiconductor layer 253 in the opening 257a.
  • the conductive layer 258b is electrically connected to the semiconductor layer 253 in the opening 257b.
  • a region overlapping with the conductive layer 255 functions as a channel formation region.
  • the semiconductor layer 253 has a pair of regions 253D that sandwich the channel formation region.
  • One of the pair of regions 253D functions as one of the source region and drain region, and is electrically connected to the conductive layer 258a.
  • the other of the pair of regions 253D functions as the other of the source region and drain region, and is electrically connected to the conductive layer 258b.
  • An insulating layer 110 is provided on the insulating layer 256, the conductive layer 258a, and the conductive layer 258b, and a conductive layer 112b is provided on the insulating layer 110.
  • the conductive layer 112b and the insulating layer 110 have an opening 146 in an area overlapping a portion of the conductive layer 258a (FIG. 24A).
  • the semiconductor layer 108 is provided to cover the opening 146.
  • An insulating layer 106 is provided on the insulating layer 110, the conductive layer 112b, and the semiconductor layer 108, and a conductive layer 104 is provided on the insulating layer 106.
  • an insulating layer 195 is provided on the insulating layer 106 and the conductive layer 104.
  • the conductive layer 259 preferably overlaps with the channel formation region and extends beyond the edge of the channel formation region. That is, the conductive layer 259 is preferably larger than the channel formation region. Also, the conductive layer 259 preferably extends beyond the edge of the semiconductor layer 253. That is, the conductive layer 259 is preferably larger than the semiconductor layer 253.
  • the gate electrode and the back gate electrode are arranged to sandwich the channel formation region of the semiconductor layer.
  • the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode.
  • the potential of the back gate electrode can be the ground potential or any potential.
  • the backgate electrode can be formed using the same materials and methods as the gate electrode, source electrode, drain electrode, etc.
  • the gate electrode and the backgate electrode are conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which the channel is formed (particularly an electric field shielding function against static electricity). In other words, it is possible to prevent the electrical characteristics of the transistor from fluctuating due to the influence of an external electric field such as static electricity.
  • a backgate electrode it is possible to reduce the amount of change in the threshold voltage of the transistor before and after a BT (Bias Temperature) stress test. By providing a backgate electrode, the variation in the characteristics of the transistor is reduced, and the reliability of the semiconductor device can be improved.
  • the transistor 250 can be configured such that the backgate and the gate are electrically connected. Also, as shown in FIG. 21F, the transistor 250 can be configured such that the backgate and the source or the drain are electrically connected. Also, as shown in FIG. 21G, the transistor 250 can be configured such that it does not have a backgate.
  • the transistor 100 is shown as an n-channel type and the transistor 250 is shown as a p-channel type, but one embodiment of the present invention is not limited to this. Both the transistor 100 and the transistor 250 can be n-channel types or p-channel types. Alternatively, the transistor 100 can be a p-channel type and the transistor 250 can be an n-channel type.
  • an OS transistor can also be used for transistor 250.
  • the same material can be used for the semiconductor layer 108 and the semiconductor layer 253. Alternatively, different materials can be used for these layers.
  • the description of the semiconductor layer 108 and the semiconductor layer 208 in the semiconductor device 20 can also be referred to.
  • Transistors using silicon in the channel formation region can also be used for the transistor 250.
  • transistors having LTPS in the semiconductor layer (hereinafter also referred to as LTPS transistors) have high field effect mobility and good frequency characteristics.
  • Transistor 100 has the same structure as described above, except that it has conductive layer 258a instead of conductive layer 112a (see FIG. 1).
  • the conductive layer 258a functions as one of the source electrode and drain electrode of the transistor 100 and also functions as one of the source electrode and drain electrode of the transistor 250. By sharing the conductive layer 258a between the transistor 100 and the transistor 250, the occupation area of the semiconductor device can be reduced.
  • transistor 100 is a vertical channel transistor.
  • transistor 250 the current flowing through the semiconductor layer flows horizontally, that is, parallel or nearly parallel to the surface of substrate 102.
  • Such a transistor can be called a horizontal channel transistor.
  • a semiconductor device can have a configuration including not only vertical channel transistors but also horizontal channel transistors.
  • the transistor 100 can also be formed in a region that overlaps with the opening 257a.
  • an opening 146 can be provided in the region that overlaps with the opening 257a, and the conductive layer 258a and the semiconductor layer 108 can be in contact with each other at the opening 257a.
  • a structure can be adopted in which the conductive layer 258a is not provided, and the region 253D and the semiconductor layer 108 are in contact with each other at the opening 257a. With such a structure, a semiconductor device that occupies a smaller area can be obtained.
  • FIG. 21H A circuit diagram of a semiconductor device 20C according to one embodiment of the present invention is shown in Fig. 21H.
  • a top view of the semiconductor device 20C is shown in Fig. 25A.
  • a cross-sectional view taken along dashed dotted line A1-A2 in Fig. 25A is shown in Fig. 25B.
  • the semiconductor device 20C has a transistor 100 and a transistor 250.
  • the gate of the transistor 250 is electrically connected to one of the source and drain of the transistor 100.
  • the semiconductor device 20C is different from the semiconductor device 20B mainly in that the opening 146 is provided so as to overlap the conductive layer 255 that functions as the gate electrode of the transistor 250. Therefore, in the semiconductor device 20B, the transistor 100 is provided so as to overlap the gate electrode of the transistor 250.
  • the opening 146 is provided overlapping the channel formation region, but this is not limited thereto.
  • the opening 146 can be provided not overlapping the channel formation region and overlapping the conductive layer 255.
  • the conductive layer 255 functions as the gate electrode of the transistor 250 and also functions as one of the source electrode and drain electrode of the transistor 100.
  • transistor 100 By stacking transistor 100 and transistor 250, a semiconductor device with a reduced occupied area can be realized.
  • Semiconductor device 20C differs from semiconductor device 20B in the configuration of opening 257a, opening 257b, conductive layer 258a, and conductive layer 258b.
  • Openings 257a and 257b are formed by selectively removing a portion of insulating layer 254 and insulating layer 110 in a region overlapping with region 253D of semiconductor layer 253.
  • Conductive layers 258a and 258b are provided on insulating layer 110 and are electrically connected to region 253D via openings 257a and 257b.
  • the conductive layer 258a and the conductive layer 258b can be formed in the same process as the conductive layer 112b. Since it is not necessary to form the conductive layer 258a and the conductive layer 258b in a separate process from the conductive layer 112b, the manufacturing process of the semiconductor device can be shortened, and the productivity of the semiconductor device can be increased.
  • a semiconductor device has at least one transistor and at least one capacitor, and has a structure in which the source or drain of the transistor is electrically connected to one of a pair of electrodes of the capacitor.
  • Figure 21I shows an example in which the source or drain of the transistor 100 is electrically connected to one electrode of the capacitor 190.
  • the transistor according to one embodiment of the present invention is a type of vertical transistor, and since the source electrode, the semiconductor layer, and the drain electrode can be stacked, the area occupied can be significantly reduced compared to a planar transistor.
  • a CMOS Complementary Metal Oxide Semiconductor
  • CMOS Complementary Metal Oxide Semiconductor
  • FIG. 26A illustrates an equivalent circuit diagram of a semiconductor device 30 which is one embodiment of the present invention.
  • the semiconductor device 30 includes transistors 100_1 to 100_p (p is an integer of 2 or more).
  • the transistors 100_1 to 100_p are connected in parallel, and the semiconductor device 30 can be regarded as one transistor.
  • the gate electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • the source electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • the drain electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • FIG. 26A illustrates the transistors 100_1 to 100_p as n-channel transistors, one embodiment of the present invention is not limited to this.
  • the transistors 100_1 to 100_p can also be p-channel transistors.
  • FIG. 26B shows an equivalent circuit diagram of a semiconductor device 30 which is one embodiment of the present invention.
  • FIG. 26C shows a top view of the semiconductor device 30.
  • FIG. 27 shows a cross-sectional view taken along dashed dotted line A3-A4 in FIG. 26C.
  • FIG. 28 shows a perspective view of the semiconductor device 30.
  • the semiconductor device 30 includes transistors 100_1 to 100_4.
  • the structure of the transistor 100 described above can be applied to each of the transistors 100_1 to 100_4. Note that although the transistor 100 is described here as an example, one embodiment of the present invention is not limited thereto. Any of the transistors 100A to 100D can be applied to the transistors 100_1 to 100_4.
  • the transistors 100_1 to 100_4 are arranged in two rows and two columns, but the arrangement of the transistors is not particularly limited.
  • the transistors 100_1 to 100_4 may be arranged in one row and four columns.
  • Transistors 100_1 to 100_4 each have a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 104 functions as a gate electrode of transistors 100_1 to 100_4.
  • a part of the insulating layer 106 functions as a gate insulating layer of transistors 100_1 to 100_4.
  • the conductive layer 112a functions as one of a source electrode and a drain electrode of transistors 100_1 to 100_4, and the conductive layer 112b functions as the other.
  • 29B is a perspective view showing the conductive layer 112a, the conductive layer 112b, the openings 141_1 to 141_4, and the openings 143_1 to 143_4. Note that the openings 141_1 to 141_4 provided in the insulating layer 110 are shown by dashed lines. The openings 141_1 to 141_4 and the openings 143_1 to 143_4 can be described with reference to the description of the openings 141 and 143, and therefore detailed description thereof will be omitted.
  • the channel width of the transistor is the sum of the channel widths of the transistors 100_1 to 100_4.
  • the semiconductor device 30 can be regarded as a transistor with a channel width of "D141 x ⁇ x 4" (see Figures 3A and 3B).
  • the semiconductor device 30, which is composed of p transistors, can be regarded as a transistor with a channel width of "D141 x ⁇ x p". Note that the semiconductor device 30 can be regarded as a transistor with a channel length L100 (see Figure 3B).
  • the channel width can be increased, and the on-current can be increased.
  • the channel width can be made different by adjusting the number (p) of transistors connected in parallel. The number (p) of transistors connected in parallel can be determined so as to obtain a desired on-current.
  • 29C is a perspective view showing the conductive layer 112a and the semiconductor layer 108.
  • the semiconductor layer 108 is provided to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4. Note that although FIG. 29C and other drawings show a structure in which the transistors 100_1 to 100_4 share the semiconductor layer 108, one embodiment of the present invention is not limited to this.
  • the semiconductor layer 108 may be separate for each of the transistors 100_1 to 100_4.
  • 29D is a perspective view showing the conductive layer 112a and the conductive layer 104.
  • the conductive layer 104 is provided so as to cover the openings 141_1 to 141_4 and the openings 143_1 to 143_4.
  • the configuration of the semiconductor device 30 shown in configuration example 2-5 can also be applied to other configuration examples.
  • the semiconductor device 30 can be applied to one or more of the transistors included in the semiconductor device shown in Figures 21A to 21I.
  • FIG. 30A illustrates an equivalent circuit diagram of a semiconductor device 40 which is one embodiment of the present invention.
  • the semiconductor device 40 includes transistors 100_1 to 100_q (q is an integer of 2 or more).
  • the transistors 100_1 to 100_q are connected in series, and the semiconductor device 40 can be regarded as one transistor.
  • FIG. 30A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this.
  • the transistors 100_1 to 100_q can also be p-channel transistors.
  • FIG. 30B shows an equivalent circuit diagram of a semiconductor device 40 which is one embodiment of the present invention.
  • FIG. 30C shows a top view of the semiconductor device 40.
  • FIG. 31 shows a cross-sectional view of the cut surface taken along dashed dotted line A5-A6 in FIG. 30C.
  • FIG. 32 shows a perspective view of the semiconductor device 40.
  • the semiconductor device 40 includes transistors 100_1 to 100_4.
  • the structure of the transistor 100 described above can be applied to each of the transistors 100_1 to 100_4. Note that although the transistor 100 is described here as an example, one embodiment of the present invention is not limited thereto. Any of the transistors 100A to 100D can be applied to the transistors 100_1 to 100_4.
  • the transistors 100_1 to 100_4 are arranged in two rows and two columns, but the arrangement of the transistors is not particularly limited.
  • the transistors 100_1 to 100_4 may be arranged in one row and four columns.
  • Transistor 100_1 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 112a functions as one of the source electrode and drain electrode of transistor 100_1, and the conductive layer 112b functions as the other.
  • Transistor 100_2 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c.
  • the conductive layer 112a functions as one of a source electrode and a drain electrode of transistor 100_2, and the conductive layer 112c functions as the other.
  • the conductive layer 112a is shared by transistors 100_1 and 100_2.
  • Transistor 100_3 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d.
  • the conductive layer 112c functions as one of a source electrode and a drain electrode of transistor 100_3, and the conductive layer 112d functions as the other.
  • the conductive layer 112c is shared by transistors 100_2 and 100_3.
  • Transistor 100_4 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e.
  • the conductive layer 112d functions as one of a source electrode and a drain electrode of transistor 100_4, and the conductive layer 112e functions as the other.
  • the conductive layer 112d is shared by transistors 100_3 and 100_4.
  • Figure 33A is a perspective view showing conductive layer 112a and conductive layer 112d. Conductive layer 112a and conductive layer 112d can be formed in the same process.
  • Figure 33B is a perspective view showing conductive layer 112a, conductive layer 112b, conductive layer 112c, conductive layer 112d, conductive layer 112e, openings 141_1 to 141_4, and openings 143_1 to 143_4.
  • Conductive layers 112a to 112e can be formed in the same process.
  • An opening 143_1 is provided in conductive layer 112b
  • openings 143_2 and 143_3 are provided in conductive layer 112c
  • opening 143_4 is provided in conductive layer 112e.
  • FIG. 33C is a perspective view showing the conductive layer 112a, the conductive layer 112d, and the semiconductor layers 108_1 to 108_4.
  • the semiconductor layers 108_1 to 108_4 can be formed in the same process.
  • 33D is a perspective view showing the conductive layer 112a, the conductive layer 112d, and the conductive layer 104.
  • the conductive layer 104 functions as the gate electrode of the transistors 100_1 to 100_4.
  • One of the source electrode and drain electrode of transistor 100_1 is electrically connected to one of the source electrode and drain electrode of transistor 100_2.
  • the other of the source electrode and drain electrode of transistor 100_2 is electrically connected to one of the source electrode and drain electrode of transistor 100_3.
  • the other of the source electrode and drain electrode of transistor 100_3 is electrically connected to one of the source electrode and drain electrode of transistor 100_4.
  • the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4.
  • the semiconductor device 40 can be regarded as a transistor with a channel length of "L100 x 4" (see FIG. 3B).
  • the semiconductor device 40 which is composed of q transistors, can be regarded as a transistor with a channel length of "L100 x q".
  • the semiconductor device 40 can be regarded as a transistor with a channel width of W100 (see FIGS. 3A and 3B).
  • the channel length can be made different by adjusting the number (q) of transistors connected in series.
  • the number (q) of transistors connected in series can be determined so as to achieve the desired saturation.
  • the configuration of the semiconductor device 40 shown in configuration example 2-6 can also be applied to other configuration examples.
  • the semiconductor device 40 can be applied to one or more of the transistors included in the semiconductor device shown in Figures 21A to 21I.
  • the semiconductor device 40 can be applied to each transistor of the semiconductor device 30.
  • a group of transistors connected in parallel can be further connected in series (hereinafter also referred to as series-parallel connection).
  • Embodiment 2 In this embodiment, a manufacturing method of a semiconductor device of one embodiment of the present invention will be described with reference to Figures 34A to 37. Note that with regard to materials and formation methods of elements, description of parts similar to those described in Embodiment 1 may be omitted.
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and ALD.
  • CVD methods include PECVD and thermal CVD.
  • One type of thermal CVD method is metal organic chemical vapor deposition (MOCVD).
  • the thin films (insulating films, semiconductor films, conductive films, etc.) that make up semiconductor devices can be formed by wet film formation methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • a photolithography method or the like can be used.
  • the thin film can be processed using a nanoimprint method, a sandblasting method, a lift-off method, or the like.
  • island-shaped thin films can be directly formed using a film formation method that uses a shielding mask such as a metal mask.
  • the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these.
  • ultraviolet light, KrF laser light, ArF laser light, etc. can also be used.
  • Exposure can also be performed by immersion exposure technology.
  • Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure.
  • Electron beams can also be used instead of the light used for exposure. Extreme ultraviolet light, X-rays, or electron beams are preferable because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.
  • etching the thin film one or more of the following methods can be used: dry etching, wet etching, and sandblasting.
  • Fig. 34A to Fig. 37 show a cross-sectional view taken along dashed line A1-A2 and a cross-sectional view taken along dashed line B1-B2 shown in Fig. 1A side by side.
  • an insulating layer 109 is formed on the substrate 102.
  • the insulating layer 109 can be formed preferably by a sputtering method or a PECVD method.
  • a conductive film that will become the conductive layer 112a is formed on the insulating layer 109, and the conductive film is processed to form the conductive layer 112a ( Figure 34A).
  • the conductive film can be preferably formed by a sputtering method.
  • an insulating film 110af that will become the insulating layer 110a, and an insulating film 110bf that will become the insulating layer 110b are formed on the conductive layer 112a ( Figure 34B).
  • the insulating films 110af and 110bf can be preferably formed by sputtering or PECVD. After forming the insulating film 110af, it is preferable to form the insulating film 110bf without exposing the surface of the insulating film 110af to the atmosphere. This makes it possible to prevent impurities from the atmosphere from adhering to the surface of the insulating film 110af. Examples of such impurities include water and organic matter. For example, it is preferable to form the insulating film 110bf continuously in the same device after forming the insulating film 110af.
  • the substrate temperature during the formation of the insulating film 110af and the insulating film 110bf is preferably 180°C or higher and 450°C or lower, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, even more preferably 350°C or higher and 400°C or lower.
  • the amount of impurities (e.g., water and hydrogen) released from the insulating film 110af and the insulating film 110bf can be reduced, and the diffusion of the impurities into the semiconductor layer 108 can be suppressed. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.
  • the insulating films 110af and 110bf are formed before the semiconductor layer 108, there is no need to worry about oxygen being desorbed from the semiconductor layer 108 due to the heat applied during the formation of the insulating films 110af and 110bf.
  • a heat treatment can be performed.
  • impurities e.g., water and hydrogen
  • oxygen can be supplied to the insulating film 110bf.
  • an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used as a method for supplying oxygen.
  • an apparatus that converts oxygen gas into plasma by high-frequency power can be suitably used.
  • a PECVD apparatus, a plasma etching apparatus, and a plasma ashing apparatus can be given as an apparatus that converts gas into plasma by high-frequency power.
  • the plasma treatment is preferably performed in an atmosphere containing oxygen.
  • the plasma treatment is preferably performed in an atmosphere containing one or more of oxygen, nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), carbon monoxide, and carbon dioxide.
  • the plasma treatment can be performed without exposing the surface of the insulating film 110bf to the air.
  • a PECVD apparatus is used to form the insulating film 110bf, it is preferable to perform the plasma treatment in the PECVD apparatus. This can increase productivity.
  • an N 2 O plasma treatment can be performed continuously.
  • FIG. 34D shows a schematic diagram with arrows of oxygen being supplied to insulating film 110bf.
  • the conductivity of the film 139 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the film 139.
  • aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can be used as the film 139.
  • the film 139 it is preferable to use an oxide material that contains one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material that can be applied to the semiconductor layer 108.
  • the oxygen flow ratio or oxygen partial pressure is, for example, preferably 50% or more and 100% or less, more preferably 60% or more and 100% or less, even more preferably 70% or more and 100% or less, even more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less.
  • oxygen can be supplied to the insulating film 110bf during the formation of the film 139, and oxygen can be prevented from being released from the insulating film 110bf.
  • a large amount of oxygen can be trapped in the insulating film 110bf.
  • a large amount of oxygen can be supplied to the semiconductor layer 108 by a later heat treatment.
  • oxygen vacancies and VOH in the semiconductor layer 108 can be reduced, and a transistor with good electrical characteristics and high reliability can be obtained.
  • a heat treatment may be performed. By performing a heat treatment after the film 139 is formed, oxygen can be effectively supplied from the film 139 to the insulating film 110bf.
  • the temperature of the heat treatment is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 450°C or lower, even more preferably 300°C or higher and 450°C or lower, even more preferably 300°C or higher and 400°C or lower, and even more preferably 350°C or higher and 400°C or lower.
  • the heat treatment can be performed in an atmosphere containing one or more of a noble gas, nitrogen, or oxygen.
  • a noble gas, nitrogen, or oxygen dry air (CDA: Clean Dry Air) can be used. Note that it is preferable that the content of hydrogen, water, and the like in the atmosphere is as small as possible.
  • a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower.
  • a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower.
  • Heat treatment can be performed using an oven, rapid thermal annealing (RTA) device, etc. Using an RTA device can shorten the heat treatment time.
  • oxygen can be further supplied to the insulating film 110bf through the film 139.
  • a method for supplying oxygen for example, an ion implantation method, an ion doping method, a plasma immersion ion implantation method, or a plasma treatment can be used.
  • the plasma treatment the above description can be referred to, and therefore a detailed description will be omitted.
  • film 139 is removed ( Figure 34E).
  • wet etching can be suitably used.
  • wet etching By using wet etching, etching of insulating film 110bf can be suppressed when film 139 is removed. This can suppress the thickness of insulating film 110bf from becoming thin, and the thickness of insulating layer 110b can be made uniform.
  • the process of supplying oxygen to the insulating film 110bf is not limited to the above-mentioned method.
  • oxygen radicals, oxygen atoms, oxygen atomic ions, or oxygen molecular ions are supplied to the insulating film 110bf by ion doping, ion implantation, or plasma treatment.
  • oxygen can be supplied to the insulating film 110bf through the film. It is preferable to remove the film after supplying oxygen.
  • a conductive film or a semiconductor film containing one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, and tungsten can be used.
  • an insulating film 110cf that will become the insulating layer 110c, and an insulating film 110ef that will become the insulating layer 110e are formed (FIG. 35A).
  • the insulating film 110cf can be preferably formed by a sputtering method.
  • the description of the formation of the insulating films 110af and 110bf can be referred to for the formation of the insulating films 110cf and 110ef, so a detailed description will be omitted.
  • a conductive film 112bf that will become the conductive layer 112b is formed on the insulating film 110ef (FIG. 35B).
  • the conductive film 112bf can be preferably formed by a sputtering method.
  • the conductive film 112bf is processed to form the conductive layer 112B (FIG. 35C).
  • the conductive layer 112B will later become the conductive layer 112b.
  • the conductive layer 112B can be preferably formed by, for example, wet etching.
  • a portion of the conductive layer 112B is removed to form a conductive layer 112b having an opening 143.
  • a wet etching method can be suitably used to form the conductive layer 112b.
  • a portion of the insulating film 110af, the insulating film 110bf, and the insulating film 110cf is removed to form the insulating layer 110 having an opening 141 (FIG. 35D).
  • the opening 141 is provided in a region overlapping with the opening 143.
  • the conductive layer 112a is exposed by forming the opening 141.
  • a dry etching method can be suitably used to form the insulating layer 110.
  • the opening 141 can be formed, for example, by using the resist mask used to form the opening 143. Specifically, a resist mask is formed on the conductive layer 112B, a part of the conductive layer 112B is removed using the resist mask to form the opening 143, and the insulating film 110af, the insulating film 110bf, and the insulating film 110cf are removed using the resist mask to form the opening 141.
  • the opening 141 can also be formed by using a resist mask different from the resist mask used to form the opening 143.
  • a metal oxide film 108f that will become the semiconductor layer 108 is formed so as to cover the openings 141 and 143 ( Figure 36A).
  • the metal oxide film 108f is provided in contact with the upper and side surfaces of the conductive layer 112b, the upper and side surfaces of the insulating layer 110, and the upper surface of the conductive layer 112a.
  • the metal oxide film 108f is preferably formed by sputtering using a metal oxide target.
  • the metal oxide film 108f is preferably formed by ALD. Since the ALD method has high coverage, it can be suitably used to form the metal oxide film 108f that covers the openings 141 and 143. By using the ALD method, a metal oxide film can be formed with high coverage on the side surface of the insulating layer 110. In addition, since the film formation speed is easy to control with the ALD method, a thin film can be formed with good yield. Therefore, the ALD method can be suitably used especially when the metal oxide film 108f is thin. In addition, instead of the sputtering method and the ALD method, the CVD method can also be used to form the metal oxide film 108f.
  • the metal oxide film 108f is preferably a dense film with as few defects as possible.
  • the metal oxide film 108f is preferably a high-purity film with as few impurities, including hydrogen, as possible reduced.
  • oxygen gas oxygen can be suitably supplied to the insulating layer 110.
  • oxygen gas oxygen can be suitably supplied to the insulating layer 110b.
  • oxygen vacancies and VOH in the semiconductor layer 108 can be reduced.
  • the metal oxide film 108f can be formed by mixing oxygen gas with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.).
  • an inert gas e.g., helium gas, argon gas, xenon gas, etc.
  • the higher the oxygen flow rate ratio or oxygen partial pressure of the deposition gas when forming the metal oxide film the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized.
  • the lower the oxygen flow rate ratio or oxygen partial pressure the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be, and the larger the on-current of the transistor can be.
  • the metal oxide film may become polycrystalline.
  • the grain boundaries become the recombination center, and carriers may be captured, resulting in a small on-current of the transistor. Therefore, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure so that the metal oxide film 108f does not become polycrystalline. Since the ease with which the metal oxide film becomes polycrystalline differs depending on the composition of the metal oxide film, it is preferable to adjust the oxygen flow ratio or oxygen partial pressure according to the composition of the metal oxide film 108f.
  • the higher the substrate temperature when forming the metal oxide film the higher the crystallinity and the denser the metal oxide film can be. This allows for a highly reliable transistor.
  • the lower the substrate temperature the lower the crystallinity and the higher the electrical conductivity of the metal oxide film can be. This allows for a transistor with a large on-state current.
  • the substrate temperature during the formation of the metal oxide film 108f is preferably from room temperature to 250°C, more preferably from room temperature to 200°C, and even more preferably from room temperature to 140°C.
  • a substrate temperature of from room temperature to 140°C is preferable because it increases productivity.
  • the crystallinity can be reduced.
  • the metal oxide film may have a polycrystalline structure. It is preferable to vary the substrate temperature depending on the composition of the material used for the metal oxide film 108f.
  • the ALD method it is preferable to use a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD).
  • a film formation method such as thermal ALD or PEALD (Plasma Enhanced ALD).
  • the thermal ALD method is preferable because it shows extremely high coating properties.
  • the PEALD method is preferable because it shows high coating properties and allows low-temperature film formation.
  • the metal oxide film can be formed, for example, by the ALD method using a precursor containing the constituent metal elements and an oxidizing agent.
  • three precursors can be used: a precursor containing indium, a precursor containing gallium, and a precursor containing zinc.
  • two precursors can be used: a precursor containing indium, and a precursor containing gallium and zinc.
  • precursors containing indium include triethylindium, trimethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, (3-(dimethylamino)propyl)dimethylindium, and [1,1,1-trimethyl-N-(trimethylsilyl)amide]-indium.
  • precursors containing gallium include trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, and diethylchlorogallium.
  • aluminum-containing precursors examples include aluminum chloride and trimethylaluminum.
  • precursors containing tin include tin(IV) chloride and tetrakis(dimethylamido)tin.
  • Examples of zinc-containing precursors include dimethylzinc, diethylzinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), and zinc chloride.
  • Oxidizing agents include, for example, ozone, oxygen, and water.
  • Methods for controlling the composition of the resulting film include adjusting one or more of the type of raw material gas, the flow rate ratio of the raw material gas, the time for which the raw material gas is flowed, and the order in which the raw material gas is flowed. By adjusting these, the composition of the metal oxide film 108f can be controlled. Furthermore, by adjusting these, it is also possible to form a metal oxide film 108f whose composition changes continuously.
  • a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 it is preferable to perform at least one of a treatment for removing water, hydrogen, organic substances, and the like adsorbed on the surface of the insulating layer 110 and a treatment for supplying oxygen into the insulating layer 110.
  • a heat treatment can be performed at a temperature of 70° C. or higher and 200° C. or lower in a reduced pressure atmosphere.
  • a plasma treatment in an atmosphere containing oxygen may be performed.
  • oxygen may be supplied to the insulating layer 110 by a plasma treatment in an atmosphere containing an oxidizing gas such as nitrous oxide ( N 2 O).
  • oxygen can be supplied while the organic substances on the surface of the insulating layer 110 are suitably removed. After such a treatment, it is preferable to continuously form the metal oxide film 108f without exposing the surface of the insulating layer 110 to the air.
  • the semiconductor layer 108 has a laminated structure, it is preferable to deposit a metal oxide film first, and then deposit the next metal oxide film in succession without exposing the surface to the air.
  • all layers constituting the semiconductor layer 108 can be formed by the same deposition method (e.g., sputtering or ALD).
  • ALD atomic layer deposition
  • different deposition methods can be used for different layers.
  • the first metal oxide layer can be deposited by sputtering
  • the second metal oxide layer can be deposited by ALD.
  • the metal oxide film 108f is processed into an island shape to form the semiconductor layer 108 ( Figure 36B).
  • the semiconductor layer 108 can be preferably formed by wet etching. At this time, a part of the conductive layer 112b in the region that does not overlap with the semiconductor layer 108 may be etched and become thinner. Similarly, a part of the insulating layer 110 in the region that does not overlap with both the semiconductor layer 108 and the conductive layer 112b may be etched and become thinner. For example, the insulating layer 110c of the insulating layer 110 may disappear by etching, and the surface of the insulating layer 110b may be exposed. Note that, in the etching of the metal oxide film 108f, by using a material with a high selectivity for the insulating layer 110c, it is possible to prevent the insulating layer 110c from becoming thinner.
  • the heat treatment can remove hydrogen and water contained in the metal oxide film 108f or the semiconductor layer 108 or adsorbed on the surface.
  • the heat treatment can also improve the film quality of the metal oxide film 108f or the semiconductor layer 108 (e.g., reduce defects or improve crystallinity).
  • oxygen can be supplied from the insulating layer 110b to the metal oxide film 108f or the semiconductor layer 108. In this case, it is more preferable to perform the heat treatment before processing into the semiconductor layer 108.
  • the above description can be referred to, and therefore a detailed description is omitted.
  • this heat treatment does not have to be performed if it is not necessary. Also, instead of performing the heat treatment here, it is possible to combine this with a heat treatment performed in a later process. Also, a high-temperature process in a later process (e.g., a film formation process) may also serve as this heat treatment.
  • the insulating layer 106 is formed to cover the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110 (FIG. 36C).
  • the insulating layer 106 can be formed by, for example, a PECVD method, a sputtering method, or an ALD method.
  • the insulating layer 106 When an oxide semiconductor is used for the semiconductor layer 108, the insulating layer 106 preferably functions as a barrier film that suppresses the diffusion of oxygen. Since the insulating layer 106 has the function of suppressing the diffusion of oxygen, the diffusion of oxygen from above the insulating layer 106 to the conductive layer 104 can be suppressed, and the oxidation of the conductive layer 104 can be suppressed. As a result, a transistor that exhibits good electrical characteristics and is highly reliable can be obtained.
  • the substrate temperature during the formation of the insulating layer 106 is preferably 180° C. to 450° C., more preferably 200° C. to 450° C., more preferably 250° C. to 450° C., even more preferably 300° C. to 450° C., and even more preferably 300° C. to 400° C.
  • the substrate temperature during the formation of the insulating layer 106 By setting the substrate temperature during the formation of the insulating layer 106 within the above range, defects in the insulating layer 106 can be reduced and oxygen can be prevented from being released from the semiconductor layer 108. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.
  • a plasma treatment may be performed on the surface of the semiconductor layer 108.
  • the plasma treatment can reduce impurities such as water adsorbed on the surface of the semiconductor layer 108.
  • impurities at the interface between the semiconductor layer 108 and the insulating layer 106 can be reduced, and a highly reliable transistor can be realized. This is particularly suitable for the case where the surface of the semiconductor layer 108 is exposed to the air between the formation of the semiconductor layer 108 and the formation of the insulating layer 106.
  • the plasma treatment can be performed in an atmosphere of oxygen, ozone, nitrogen, nitrous oxide, argon, or the like, for example.
  • it is preferable that the plasma treatment and the formation of the insulating layer 106 are performed successively without exposure to the air.
  • impurity elements 189 are supplied to the semiconductor layer 108 ( Figure 37). By supplying the impurity elements 189, regions 108Da and 108Db are formed.
  • the impurity element 189 is preferably supplied from a direction perpendicular or substantially perpendicular to the upper surface of the substrate 102.
  • the amount of the impurity element supplied to the region inclined with respect to the upper surface of the substrate 102 in the semiconductor layer 108 is smaller than that to the region parallel or substantially parallel to the upper surface of the substrate 102. That is, the amount of the impurity element supplied to the source region and the drain region of the semiconductor layer 108 is larger than that to the channel formation region. Therefore, the electrical resistance of the source region and the drain region can be preferentially reduced.
  • oxygen vacancies (V O ) may occur in the semiconductor layer 108.
  • the impurity element 189 may be combined with oxygen vacancies (V O ) in the semiconductor layer 108.
  • the impurity element 189 is preferably supplied to the semiconductor layer 108 through the insulating layer 106.
  • the thickness of the insulating layer 106 in the direction in which the impurity element 189 is supplied varies depending on the location. Therefore, the semiconductor layer 108 has regions with a large amount of the impurity element 189 supplied and regions with a small amount of the impurity element 189 supplied.
  • the region of the semiconductor layer 108 provided along the top surface of the conductive layer 112a or the top surface of the conductive layer 112b has a larger amount of the impurity element supplied than the region provided along the side surface of the insulating layer 110.
  • the supply of the impurity element to the channel formation region of the semiconductor layer 108 can be suppressed, and the electrical resistance of the source region and the drain region can be preferentially reduced.
  • the impurity element 189 is also supplied to the insulating layer 106.
  • impurity element 189 The elements that can be used for impurity element 189 are as described above.
  • the impurity element 189 can be preferably supplied by plasma ion doping or ion implantation.
  • the purity of the supplied impurity element can be increased.
  • the ion implantation method it is preferable to use the first element described above as the impurity element 189, and it is more preferable to use boron or phosphorus.
  • the impurity element 189 By using an element that becomes stable when bonded with oxygen as the impurity element 189, it is possible to realize regions 108Da and 108Db that are stable and have low electrical resistance.
  • the plasma ion doping method By using the plasma ion doping method in which the impurity element 189 is supplied without mass separation, productivity can be increased.
  • the plasma ion doping method it is preferable to use both the first element and hydrogen as the impurity element 189, and it is even more preferable to use both boron or phosphorus and hydrogen.
  • both an element that becomes stable when bonded with oxygen and hydrogen as the impurity element 189 it is easy to lower the electrical resistance of the regions 108Da and 108Db, and the low electrical resistance state can be stably maintained.
  • the ion implantation equipment or ion doping equipment used to supply the impurity element 189 is also used in the manufacture of Si transistors such as LTPS transistors, so equipment from existing LTPS production lines can be reused, which is preferable since no new capital investment is required. This makes it possible to reduce the initial capital investment costs involved in the manufacture of semiconductor devices.
  • boron and phosphorus are particularly preferable since they are used in ion implantation equipment or ion doping equipment in Si transistor production lines and no new capital investment is required.
  • the impurity element 189 In the supplying process of the impurity element 189, it is preferable to control the processing conditions so that the concentration of the impurity element in the portion of the semiconductor layer 108 that overlaps with the conductive layer 112a or the conductive layer 112b is higher than the concentration of the impurity element in other regions. This allows the impurity element 189 to be supplied at an optimal concentration to the source region and drain region of the semiconductor layer 108.
  • a gas containing the above - mentioned impurity element can be used as a source gas for the impurity element 189.
  • boron typically, B2H6 gas, BF3 gas, or the like can be used.
  • phosphorus typically, PH3 gas can be used.
  • a mixed gas in which these source gases are diluted with hydrogen or a noble gas may also be used.
  • source gas examples include CH4 , N2 , NH3, AlH3 , AlCl3 , SiH4 , Si2H6 , F2 , HF, H2 , ( C5H5 ) 2Mg , and noble gases.
  • the source material used to supply the impurity element is not limited to gas, and a solid or liquid may be heated and vaporized for use.
  • the impurity element 189 it is preferable to use a gas containing boron and hydrogen to supply boron and hydrogen as the impurity element 189.
  • the impurity element 189 can be supplied without mass separation, and it is easy to reduce the electrical resistance of the semiconductor layer 108, which is preferable because it is possible to improve both the productivity and characteristics of the semiconductor device.
  • the supply of the impurity element 189 can be controlled by setting conditions such as acceleration energy and dose amount, taking into consideration the type of impurity element 189, the composition, film density, and thickness of each of the insulating layer 106 and the semiconductor layer 108, etc.
  • the method of supplying the impurity element 189 is not limited, and for example, plasma processing or processing utilizing thermal diffusion by heating can be used.
  • the impurity element can be supplied by generating plasma in a gas atmosphere containing the impurity element to be supplied and performing plasma processing.
  • a dry etching apparatus, an ashing apparatus, a plasma CVD apparatus, a high density plasma CVD apparatus, etc. can be used as an apparatus for generating the above plasma.
  • the impurity element 189 is supplied to the semiconductor layer 108 through the insulating layer 106. This makes it possible to suppress a decrease in the crystallinity of the semiconductor layer 108 when the impurity element 189 is supplied. Therefore, it is possible to suppress an increase in electrical resistance due to a decrease in crystallinity.
  • the inside of the deposition chamber for the insulating layer 106 may be contaminated. For this reason, it is preferable to supply the impurity element 189 after the insulating layer 106 is formed.
  • the impurity element 189 can be directly supplied to the semiconductor layer 108, and then the insulating layer 106 can be formed on the semiconductor layer 108. This can prevent the insulating layer 106 from being damaged by the supply of the impurity element 189.
  • the supplying step of the impurity element 189 is preferably performed while heating the substrate 102. This allows damage to the semiconductor layer 108 that occurs when the impurity element 189 is supplied to be repaired. That is, the supply of the impurity element 189 to the semiconductor layer 108 and the repair of damage caused by the supply can be performed in parallel. In addition, damage to the insulating layer 106 that occurs when the impurity element 189 is supplied can also be repaired. Note that one embodiment of the present invention is not limited thereto, and the supplying step of the impurity element 189 can be performed without heating the substrate 102.
  • the substrate temperature during the supply process of the impurity element 189 is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.
  • a heat treatment can be performed. By performing this heat treatment, damage that the semiconductor layer 108 and the insulating layer 106 received during the process of supplying the impurity element 189 can be repaired.
  • the electrical resistance of region 108Da, the electrical resistance of region 108Db, the contact resistance between region 108Da and conductive layer 112a, and the contact resistance between region 108Db and conductive layer 112b may increase.
  • the temperature of the heat treatment after supplying the impurity element 189 is preferably 150°C or higher and lower than the distortion point of the substrate, more preferably 200°C or higher and 500°C or lower, even more preferably 200°C or higher and 450°C or lower, even more preferably 250°C or higher and 400°C or lower, even more preferably 250°C or higher and 350°C or lower, or 300°C or higher and 400°C or lower, even more preferably 300°C or higher and 350°C or lower.
  • the impurity element 189 By using an element that becomes stable when bonded with oxygen as the impurity element 189, it is possible to prevent the impurity element 189 from being detached during the process of applying heat. Therefore, after the impurity element 189 is supplied, the electrical resistance of the regions 108Da and 108Db can be kept low even after the process of applying heat is performed.
  • a conductive layer 104 is formed on the insulating layer 106 (FIGS. 15A and 15B).
  • the conductive film that becomes the conductive layer 104 can be formed by, for example, a sputtering method, a thermal CVD method (including an MOCVD method), or an ALD method.
  • a semiconductor device 10C according to one embodiment of the present invention can be manufactured.
  • FIGS. 38A and 38B show a cross-sectional view between dashed dotted lines A1-A2 and B1-B2 shown in FIG. 1A side by side.
  • the process is performed up to the formation of the insulating layer 106 in the same manner as in ⁇ Fabrication method example 1>. Since the description of FIG. 34A and FIG. 36C can be referred to for the formation of the insulating layer 106, detailed description will be omitted.
  • an impurity element 187 is supplied to the semiconductor layer 108 (FIG. 38A). It is preferable to use the second element described above as the impurity element 187, and argon can be suitably used.
  • regions 108Ea and 108Eb having the second element are formed. Later, region 108Ea becomes region 108Da, and region 108Eb becomes region 108Db.
  • the impurity element 187 can be supplied by the same method as that for supplying the impurity element 189 described above.
  • the impurity element 187 can be supplied by a plasma ion doping method or an ion implantation method.
  • the supply of the impurity element 187 can be controlled by setting conditions such as acceleration energy and dose amount, taking into consideration the type of impurity element 187, the composition, film density, and thickness of each of the insulating layer 106 and the semiconductor layer 108, and the like.
  • the impurity element 187 is preferably supplied from a direction perpendicular or approximately perpendicular to the upper surface of the substrate 102.
  • the above description of the supply of the impurity element 189 can be referred to.
  • the metal-oxygen bonds of the metal oxide are broken in the region 108Ea, which becomes the region 108Da, and in the region 108Eb, which becomes the region 108Db. Furthermore, the breaking of the metal-oxygen bonds causes oxygen vacancies (V O ) in the regions 108Ea and 108Eb. Thereafter, by supplying the first element to the regions 108Ea and 108Eb, the first element can be efficiently bonded to oxygen. Therefore, the electrical resistance of the regions 108Da and 108Db can be efficiently reduced.
  • impurity element 189 is supplied to semiconductor layer 108 (FIG. 38B). By supplying impurity element 189, regions 108Da and 108Db are formed. Regions 108Da and 108Db each have a first element and a second element.
  • the supply conditions of the impurity element 189 can be different from the supply conditions of the impurity element 187. It is preferable to set conditions such as acceleration energy and dose amount according to the type of the first element and the type of the second element.
  • the supply conditions of the impurity element 187 and the supply conditions of the impurity element 189 can be the same.
  • first element and the second element are supplied in different processes.
  • first element and the second element can be supplied in the same process.
  • a conductive layer 104 is formed on the insulating layer 106 (FIGS. 15A and 15B).
  • the conductive layer 104 please refer to the above description.
  • a semiconductor device 10C according to one embodiment of the present invention can be manufactured.
  • the display device of this embodiment can be a high-resolution display device or a large display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • electronic devices with relatively large screens such as television devices, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, in the display section of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display section of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR device, or a glasses-type AR device.
  • a wearable device such as a head-mounted display (HMD) or other VR device, or a glasses-type AR device.
  • HMD head-mounted display
  • AR device glasses-type AR device
  • the semiconductor device of one embodiment of the present invention can be used in a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (hereinafter, referred to as FPC) or a TCP (Tape Carrier Package) is attached to the display device, and a module in which an integrated circuit (IC) is mounted by a COG (chip on glass) method, a COF (chip on film) method, or the like.
  • the display device of this embodiment may have a function as a touch panel.
  • various detection elements also called sensor elements
  • various detection elements that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.
  • Sensor types include, for example, capacitive type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
  • Examples of the capacitance type include the surface capacitance type and the projected capacitance type.
  • Examples of the projected capacitance type include the self-capacitance type and the mutual capacitance type.
  • the mutual capacitance type is preferable because it allows simultaneous multi-point detection.
  • touch panels examples include out-cell, on-cell, and in-cell types.
  • an in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.
  • FIG. 39 shows a perspective view of a display device 50A.
  • Display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • the display device 50A has a display section 162, a connection section 140, a circuit section 164, a conductive layer 165, etc.
  • FIG. 39 shows an example in which an IC 173 and an FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in FIG. 39 can also be said to be a display module having the display device 50A, an IC, and an FPC.
  • connection portion 140 is provided on the outside of the display portion 162.
  • the connection portion 140 can be provided along one side or multiple sides of the display portion 162. There may be one or multiple connection portions 140.
  • Figure 39 shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion 162.
  • the connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.
  • the circuit portion 164 has, for example, a scanning line driver circuit (also called a gate driver).
  • the circuit portion 164 may also have both a scanning line driver circuit and a signal line driver circuit (also called a source driver).
  • the conductive layer 165 has a function of supplying signals and power to the display portion 162 and the circuit portion 164.
  • the signals and power are input to the conductive layer 165 from the outside via the FPC 172, or are input to the conductive layer 165 from the IC 173.
  • FIG. 39 shows an example in which an IC 173 is provided on a substrate 151 by a COG method, a COF method, or the like.
  • an IC having one or both of a scanning line driver circuit and a signal line driver circuit can be used as the IC 173.
  • the display device 50A and the display module may be configured without an IC.
  • the IC may be mounted on an FPC by a COF method, or the like.
  • the semiconductor device of one embodiment of the present invention can be applied to, for example, one or both of the display portion 162 and the circuit portion 164 of the display device 50A.
  • An oxide semiconductor (OS) can be preferably used for a channel formation region of a transistor included in the display device.
  • OS oxide semiconductor
  • the semiconductor device of one embodiment of the present invention can be used for both the display portion 162 and the circuit portion 164, that is, all the transistors included in the display device can be OS transistors. By using OS transistors for all the transistors included in the display device in this manner, an effect of keeping manufacturing costs low can be obtained.
  • the semiconductor device of one embodiment of the present invention when the semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained. Furthermore, when the semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained. Furthermore, since the semiconductor device of one embodiment of the present invention has good electrical characteristics, the reliability of the display device can be improved by using it in a display device.
  • a driver circuit of a display device e.g., one or both of a gate line driver circuit and a source line driver circuit
  • the display unit 162 is an area in the display device 50A that displays an image, and has a number of periodically arranged pixels 201.
  • Figure 39 shows an enlarged view of one pixel 201.
  • pixel arrangements there are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include a stripe arrangement, an S-stripe arrangement, a matrix arrangement, a delta arrangement, a Bayer arrangement, and a Pentile arrangement.
  • the pixel 201 shown in FIG. 39 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light. Note that there is no particular limit to the number of sub-pixels that one pixel has.
  • Each of the sub-pixels 11R, 11G, and 11B has a display element and a circuit that controls the driving of the display element.
  • Various elements can be used as display elements, including liquid crystal elements and light-emitting elements.
  • Other elements that can be used include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, display elements that use microcapsules, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods, etc.
  • QLEDs Quantum-dot LEDs that use a light source and color conversion technology using quantum dot materials.
  • Display devices using liquid crystal elements include, for example, transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.
  • Modes that can be used in displays using liquid crystal elements include, for example, vertical alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane Switching) mode, TN (Twisted Nematic) mode, and ASM (Axially Symmetrically aligned Micro-cell) mode.
  • VA mode include the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, and the ASV (Advanced Super View) mode.
  • Liquid crystal materials that can be used in liquid crystal elements include, for example, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystal, and antiferroelectric liquid crystal.
  • thermotropic liquid crystal low molecular weight liquid crystal
  • polymer liquid crystal polymer dispersed liquid crystal
  • PNLC Polymer Network liquid crystal
  • ferroelectric liquid crystal and antiferroelectric liquid crystal.
  • these liquid crystal materials can exhibit cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, blue phase, etc.
  • either positive type liquid crystal or negative type liquid crystal can be used as the liquid crystal material, and can be selected according to the mode or design to be applied.
  • Light-emitting elements include, for example, self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. LEDs can also include, for example, mini LEDs and micro LEDs.
  • Light-emitting materials that light-emitting elements have include, for example, materials that emit fluorescence (fluorescent materials), materials that emit phosphorescence (phosphorescent materials), materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (quantum dot materials, etc.).
  • fluorescent materials materials that emit fluorescence
  • phosphorescent materials materials that emit phosphorescence
  • TADF thermally activated delayed fluorescence
  • inorganic compounds quantum dot materials, etc.
  • the light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, or white.
  • the color purity can be increased by providing the light-emitting element with a microcavity structure.
  • one electrode functions as an anode and the other electrode functions as a cathode.
  • the display device of one embodiment of the present invention may be a top-emission type that emits light in a direction opposite to the substrate on which the light-emitting elements are formed, a bottom-emission type that emits light toward the substrate on which the light-emitting elements are formed, or a dual-emission type that emits light on both sides.
  • FIG. 40A shows an example of a cross section of the display device 50A when a portion of the area including the FPC 172, a portion of the circuit section 164, a portion of the display section 162, a portion of the connection section 140, and a portion of the area including the end portion are cut away.
  • Display device 50A shown in FIG. 40A has transistors 205D, 205R, 205G, 205B, light-emitting element 130R, light-emitting element 130G, light-emitting element 130B, etc. between substrate 151 and substrate 152.
  • Light-emitting element 130R is a display element of subpixel 11R that emits red light
  • light-emitting element 130G is a display element of subpixel 11G that emits green light
  • light-emitting element 130B is a display element of subpixel 11B that emits blue light.
  • the display device 50A uses an SBS structure.
  • the SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve brightness and reliability.
  • the display device 50A is a top emission type.
  • transistors and the like can be arranged so as to overlap the light emitting region of the light emitting element, so the aperture ratio of the pixel can be increased compared to a bottom emission type.
  • Transistor 205D, transistor 205R, transistor 205G, and transistor 205B are all formed on substrate 151. These transistors can be manufactured in the same process. Note that transistors 205D, transistor 205R, transistor 205G, and transistor 205B may have different structures.
  • Transistors of one embodiment of the present invention can be used as the transistors 205D, 205R, 205G, and 205B. That is, the display device 50A includes transistors of one embodiment of the present invention in both the display portion 162 and the circuit portion 164. By using a transistor of one embodiment of the present invention in the display portion 162, the pixel size can be reduced, leading to higher resolution. Furthermore, by using a transistor of one embodiment of the present invention in the circuit portion 164, the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame. For the transistors of one embodiment of the present invention, refer to the description of the previous embodiment.
  • transistors 205D, 205R, 205G, and 205B each have a conductive layer 104 that functions as a gate, an insulating layer 106 that functions as a gate insulating layer, conductive layers 112a and 112b that function as a source and drain, a semiconductor layer 108 having a metal oxide, and an insulating layer 110.
  • the same hatched pattern is applied to multiple layers obtained by processing the same conductive film.
  • the insulating layer 110 is located between the conductive layer 112a and the conductive layer 112b.
  • the insulating layer 106 is located between the conductive layer 104 and the semiconductor layer 108.
  • the transistors included in the display device of this embodiment are not limited to the transistors of one embodiment of the present invention.
  • the display device may include a combination of a transistor of one embodiment of the present invention and a transistor having another structure.
  • the display device of this embodiment may have, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor.
  • the transistors of the display device of this embodiment may be either a top-gate type or a bottom-gate type.
  • a gate may be provided above and below a semiconductor layer in which a channel is formed.
  • the display device of this embodiment may have a Si transistor.
  • an OS transistor When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current in response to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing between the source and drain can be precisely determined by changing the gate-source voltage, and the amount of current flowing to the light-emitting element can be controlled. This makes it possible to increase the number of gray levels in the pixel circuit.
  • an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to the light-emitting element, for example, even when there is variation in the current-voltage characteristics of the light-emitting element. In other words, when an OS transistor operates in the saturation region, the source-drain current hardly changes even when the source-drain voltage is changed, so the light emission luminance of the light-emitting element can be stabilized.
  • the transistors in the circuit unit 164 and the transistors in the display unit 162 may have the same structure or different structures.
  • the transistors in the circuit unit 164 may all have the same structure or may be of two or more types.
  • the transistors in the display unit 162 may all have the same structure or may be of two or more types.
  • All of the transistors in the display portion 162 may be OS transistors, all of the transistors in the display portion 162 may be Si transistors, or some of the transistors in the display portion 162 may be OS transistors and the rest may be Si transistors.
  • LTPS transistors and OS transistors are combined in the display unit 162
  • LTPO A configuration in which LTPS transistors and OS transistors are combined is sometimes called LTPO.
  • a more suitable example is a configuration in which an OS transistor is used as a transistor that functions as a switch for controlling conduction/non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current.
  • one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a driving transistor.
  • One of the source and drain of the driving transistor is electrically connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor as the driving transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.
  • the other one of the transistors in the display unit 162 functions as a switch for controlling pixel selection/non-selection and can also be called a selection transistor.
  • the gate of the selection transistor is electrically connected to a gate line, and one of the source and drain is electrically connected to a source line (signal line).
  • an OS transistor is used as the selection transistor. This makes it possible to maintain the gradation of the pixel even if the frame frequency is significantly lowered (for example, 1 fps or less), and therefore power consumption can be reduced by stopping the driver when displaying a still image.
  • An insulating layer 218 is provided to cover transistors 205D, 205R, 205G, and 205B, and an insulating layer 235 is provided on insulating layer 218.
  • the insulating layer 218 preferably functions as a protective layer for the transistor.
  • the insulating layer 218 is preferably made of a material through which impurities such as water and hydrogen do not easily diffuse. This allows the insulating layer 218 to function as a barrier film. With this structure, it is possible to effectively prevent impurities from diffusing from the outside into the transistor, and the reliability of the display device can be improved.
  • the insulating layer 218 preferably has one or more inorganic insulating layers.
  • the insulating layer 218 can be made of a material that can be used for the insulating layer 110.
  • the insulating layer 235 preferably functions as a planarization layer, and is preferably an organic insulating film.
  • Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.
  • the insulating layer 235 may also have a laminated structure of an organic insulating film and an inorganic insulating film.
  • the outermost layer of the insulating layer 235 preferably functions as an etching protection layer. This makes it possible to prevent the formation of recesses in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc. Alternatively, recesses may be provided in the insulating layer 235 when processing the pixel electrodes 111R, 111G, 111B, etc.
  • Light emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R.
  • the light-emitting element 130R shown in FIG. 40A emits red light (R).
  • the EL layer 113R has a light-emitting layer that emits red light.
  • the light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G.
  • the light-emitting element 130G shown in FIG. 40A emits green light (G).
  • the EL layer 113G has a light-emitting layer that emits green light.
  • the light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B.
  • the light-emitting element 130B shown in FIG. 40A emits blue light (B).
  • the EL layer 113B has a light-emitting layer that emits blue light.
  • EL layers 113R, 113G, and 113B are all shown to have the same thickness, but this is not limited to this.
  • EL layers 113R, 113G, and 113B may each have a different thickness.
  • the pixel electrode 111R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235.
  • the pixel electrode 111G is electrically connected to the conductive layer 112b of the transistor 205G
  • the pixel electrode 111B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the ends of each of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237.
  • the insulating layer 237 functions as a partition wall.
  • the insulating layer 237 can be formed in a single layer structure or a laminated structure using one or both of an inorganic insulating material and an organic insulating material.
  • the material that can be used for the insulating layer 218 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237.
  • the insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.
  • the insulating layer 237 is provided at least in the display section 162.
  • the insulating layer 237 may be provided not only in the display section 162, but also in the connection section 140 and the circuit section 164.
  • the insulating layer 237 may also be provided up to the edge of the display device 50A.
  • the common electrode 115 is a continuous film that is provided in common to the light-emitting elements 130R, 130G, and 130B.
  • the common electrode 115 that is shared by the multiple light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140.
  • a conductive layer 123 it is preferable to use a conductive layer formed from the same material and in the same process as the pixel electrodes 111R, 111G, and 111B.
  • a conductive film that transmits visible light is used for the pixel electrode and the common electrode, which is the electrode from which light is extracted. It is preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.
  • a conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted.
  • the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.
  • metals, alloys, electrically conductive compounds, and mixtures thereof can be appropriately used.
  • the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations.
  • examples of the material include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide.
  • examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver and magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, also called APC).
  • Such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) that are not listed above, rare earth metals such as europium and ytterbium, and alloys containing appropriate combinations of these, graphene, etc.
  • the light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transparent and semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode).
  • the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.
  • the light transmittance of the transparent electrode is 40% or more.
  • the visible light reflectance of the semi-transmissive/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less.
  • the visible light reflectance of the reflective electrode is 40% or more and 100% or less, preferably 70% or more and 100% or less.
  • the electrical resistivity of these electrodes is preferably 1 ⁇ 10 ⁇ 2 ⁇ cm or less.
  • the EL layers 113R, 113G, and 113B are each provided in an island shape.
  • the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap.
  • the ends of adjacent EL layers may overlap as shown in FIG. 40A, but this is not limited to this. In other words, adjacent EL layers may not overlap and may be separated from each other.
  • the EL layers 113R, 113G, and 113B each have at least a light-emitting layer.
  • the light-emitting layer has one or more types of light-emitting materials.
  • a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used.
  • a material that emits near-infrared light can also be used as the light-emitting material.
  • Light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.
  • the light-emitting layer may have one or more organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material).
  • the one or more organic compounds one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) can be used.
  • a bipolar substance a substance with high electron transport properties and hole transport properties
  • a TADF material may be used as the one or more organic compounds.
  • the light-emitting layer preferably contains, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex.
  • ExTET Exciplex-Triple Energy Transfer
  • the energy transfer becomes smooth and light emission can be efficiently obtained.
  • the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer).
  • the EL layer may contain one or both of a bipolar substance and a TADF material.
  • Either low molecular weight compounds or high molecular weight compounds can be used for the light emitting element, and it may contain inorganic compounds.
  • the layers constituting the light emitting element can be formed by a deposition method (including vacuum deposition), a transfer method, a printing method, an inkjet method, a coating method, etc.
  • the light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units).
  • the light-emitting unit has at least one light-emitting layer.
  • the tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other.
  • the tandem structure makes it possible to obtain a light-emitting element capable of emitting light with high brightness. Furthermore, the tandem structure can reduce the current required to obtain the same brightness compared to a single structure, thereby improving reliability.
  • the tandem structure can also be called a stack structure.
  • EL layer 113R has a structure having multiple light-emitting units that emit red light
  • EL layer 113G has a structure having multiple light-emitting units that emit green light
  • EL layer 113B has a structure having multiple light-emitting units that emit blue light.
  • a protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B.
  • the protective layer 131 and the substrate 152 are bonded via an adhesive layer 142.
  • the substrate 152 is provided with a light-shielding layer 117.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements.
  • the space between the substrates 152 and 151 is filled with an adhesive layer 142, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied.
  • the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements.
  • the space may also be filled with a resin different from the adhesive layer 142 provided in a frame shape.
  • the protective layer 131 is provided at least on the display unit 162, and is preferably provided so as to cover the entire display unit 162.
  • the protective layer 131 is preferably provided so as to cover not only the display unit 162, but also the connection unit 140 and the circuit unit 164.
  • the protective layer 131 is also preferably provided up to the end of the display device 50A.
  • the connection unit 197 has a portion where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.
  • the reliability of the light-emitting elements can be improved.
  • the protective layer 131 can be a single layer structure or a laminated structure of two or more layers.
  • the conductivity of the protective layer 131 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.
  • the protective layer 131 has an inorganic film, which prevents the common electrode 115 from being oxidized and prevents impurities (such as moisture and oxygen) from entering the light-emitting element, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.
  • the protective layer 131 preferably has one or more inorganic insulating layers.
  • the protective layer 131 can be made of a material that can be used for the insulating layer 110.
  • the protective layer 131 is preferably made of a nitride or a nitride oxide, and more preferably made of a nitride.
  • the protective layer 131 may be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like.
  • the inorganic film preferably has a high resistance, and more specifically, preferably has a higher resistance than the common electrode 115.
  • the inorganic film may further contain nitrogen.
  • the protective layer 131 has high transparency to visible light.
  • ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.
  • the protective layer 131 may be, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film. By using this laminated structure, it is possible to prevent impurities (water, oxygen, etc.) from entering the EL layer side.
  • the protective layer 131 may have an organic film.
  • the protective layer 131 may have both an organic film and an inorganic film.
  • An example of an organic film that can be used for the protective layer 131 is an organic insulating film that can be used for the insulating layer 235.
  • connection portion 197 is provided in an area of the substrate 151 where the substrate 152 does not overlap.
  • the conductive layer 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.
  • the conductive layer 165 is an example of a conductive layer obtained by processing the same conductive film as the conductive layer 112b.
  • the conductive layer 166 is an example of a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B.
  • the connection portion between the conductive layer 165 and the conductive layer 166 can have the same structure as the connection portion between the pixel electrode 111 and the conductive layer 112b. Specifically, FIG.
  • connection portion 197 shows an example in which an opening is provided in the upper layer of the conductive layer 165, and the conductive layer 166 contacts the upper surface of the conductive layer 165 through the opening.
  • the conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be electrically connected via the connection layer 242.
  • the display device 50A is a top emission type. Light emitted by the light emitting elements is emitted towards the substrate 152. It is preferable to use a material that is highly transparent to visible light for the substrate 152.
  • the pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.
  • the light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, etc.
  • a colored layer such as a color filter may be provided on the surface of substrate 152 facing substrate 151 or on protective layer 131. By providing a color filter over the light-emitting element, the color purity of the light emitted from the pixel can be increased.
  • the colored layers are colored layers that selectively transmit light in a specific wavelength range and absorb light in other wavelength ranges.
  • a red (R) color filter that transmits light in the red wavelength range
  • a green (G) color filter that transmits light in the green wavelength range
  • a blue (B) color filter that transmits light in the blue wavelength range
  • R red
  • G green
  • B blue
  • metal materials, resin materials, pigments, and dyes can be used.
  • the colored layers are formed at the desired positions by printing, inkjet, etching using photolithography, or the like.
  • optical members can be arranged on the outside of the substrate 152 (the surface opposite to the substrate 151).
  • optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light collecting film.
  • a surface protection layer such as an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches due to use, and an impact absorbing layer may be arranged on the outside of the substrate 152.
  • a glass layer or a silica layer As the surface protection layer, it is possible to suppress the occurrence of surface contamination and scratches, which is preferable.
  • DLC diamond-like carbon
  • AlO x aluminum oxide
  • a polyester-based material a polycarbonate-based material, or the like
  • the substrates 151 and 152 may each be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, or the like.
  • a material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. If a flexible material is used for the substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized.
  • a polarizing plate may also be used for at least one of the substrates 151 and 152.
  • the substrates 151 and 152 may each be made of polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. At least one of the substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyacrylonitrile resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • a substrate with high optical isotropy has low birefringence (it can also be said that the amount of birefringence is small).
  • films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.
  • connection layer 242 an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), etc. can be used.
  • ACF anisotropic conductive film
  • ACP anisotropic conductive paste
  • FIG. 40B shows an example of a cross section of the display unit 162 of the display device 50B.
  • the display device 50B is mainly different from the display device 50A in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used in each subpixel of each color.
  • the configuration shown in FIG. 40B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in FIG. 40A. Note that in the following description of the display device, the description of the same parts as those of the display device described above may be omitted.
  • the display device 50B shown in FIG. 40B has light emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light-emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.
  • the light-emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.
  • a tandem structure For light-emitting elements that emit white light, it is preferable to use a tandem structure. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and a light-emitting unit that emits blue light, or a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green or green light, and red light, and a light-emitting unit that emits blue light, etc.
  • the number of layers and the order of colors of the light-emitting units can be, from the anode side, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, and B, or a three-layer structure of B, X, and B.
  • the number of layers and the order of colors of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, or a three-layer structure of R, G, and R.
  • another layer may be provided between the two light-emitting layers.
  • a light-emitting element configured to emit white light may emit light of a specific wavelength, such as red, green, or blue, with the light being enhanced.
  • a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted. Furthermore, it is preferable to provide a colored layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a colored layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G.
  • Light emitted by the light-emitting element is emitted toward the substrate 151. It is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the translucency of the material used for the substrate 152 does not matter.
  • FIG. 41 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153.
  • the colored layers 132R, 132G, and 132B are provided on the insulating layer 218, and the insulating layer 235 is provided on the colored layers 132R, 132G, and 132B.
  • the light-emitting element 130G which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 115.
  • the light-emitting element 130B which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 115.
  • the pixel electrodes 111R, 111G, and 111B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom-emission display device, a metal with low electrical resistivity can be used for the common electrode 115, so that voltage drops caused by the electrical resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the pixel aperture ratio can be increased or the pixel size can be reduced.
  • a display device 50D shown in FIG. 42A differs from the display device 50A mainly in that a light receiving element 130S is included.
  • Display device 50D has a light-emitting element and a light-receiving element in each pixel.
  • display device 50D it is preferable to use an organic EL element as the light-emitting element and an organic photodiode as the light-receiving element.
  • the organic EL element and the organic photodiode can be formed on the same substrate. Therefore, an organic photodiode can be built into a display device that uses an organic EL element.
  • display unit 162 has one or both of an imaging function and a sensing function. For example, in addition to displaying an image using all of the sub-pixels of display device 50D, some of the sub-pixels can provide light as a light source, some other sub-pixels can perform light detection, and the remaining sub-pixels can display an image.
  • the light receiving element can be used as a touch sensor (also called a direct touch sensor) or a non-contact sensor (also called a hover sensor, hover touch sensor, or touchless sensor).
  • a touch sensor can detect an object (such as a finger, hand, or pen) when the display device and the object are in direct contact with each other.
  • a non-contact sensor can detect an object even if the object does not come into contact with the display device.
  • the light receiving element 130S has a pixel electrode 111S on an insulating layer 235, a functional layer 113S on the pixel electrode 111S, and a common electrode 115 on the functional layer 113S.
  • Light Lin is incident on the functional layer 113S from outside the display device 50D.
  • the pixel electrode 111S is electrically connected to the conductive layer 112b of the transistor 205S through openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235.
  • the ends of the pixel electrode 111S are covered by an insulating layer 237.
  • the common electrode 115 is a continuous film provided in common to the light receiving element 130S, the light emitting element 130R (not shown), the light emitting element 130G, and the light emitting element 130B.
  • the common electrode 115 shared by the light emitting element and the light receiving element is electrically connected to the conductive layer 123 provided in the connection portion 140.
  • the functional layer 113S has at least an active layer (also called a photoelectric conversion layer).
  • the active layer includes a semiconductor.
  • the semiconductor include inorganic semiconductors such as silicon, and organic semiconductors including organic compounds.
  • an organic semiconductor is used as the semiconductor of the active layer.
  • the light-emitting layer and the active layer can be formed by the same method (for example, vacuum deposition), which is preferable because the manufacturing equipment can be shared.
  • the functional layer 113S may further include a layer containing a material with high hole transport properties, a material with high electron transport properties, or a bipolar material, as a layer other than the active layer.
  • the functional layer 113S may further include a layer containing a material with high hole injection properties, a hole blocking material, a material with high electron injection properties, or an electron blocking material.
  • the materials that can be used in the light-emitting element described above can be used for the functional layer 113S.
  • the light receiving element can be made of either a low molecular weight compound or a high molecular weight compound, and may contain an inorganic compound.
  • the layers that make up the light receiving element can be formed by a deposition method (including vacuum deposition), a transfer method, a printing method, an inkjet method, a coating method, etc.
  • the display device 50D shown in Figures 42B and 42C has a layer 353 having light receiving elements, a circuit layer 355, and a layer 357 having light emitting elements between the substrate 151 and the substrate 152.
  • Layer 353 has, for example, light receiving element 130S.
  • Layer 357 has, for example, light emitting elements 130R, 130G, and 130B.
  • Circuit layer 355 has a circuit that drives the light receiving element and a circuit that drives the light emitting element.
  • Circuit layer 355 has, for example, transistors 205R, 205G, and 205B.
  • circuit layer 355 can be provided with one or more of switches, capacitance, resistance, wiring, and terminals.
  • Figure 42B shows an example in which the light receiving element 130S is used as a touch sensor. As shown in Figure 42B, light emitted by the light emitting element in layer 357 is reflected by a finger 352 that touches the display device 50D, and the light receiving element in layer 353 detects the reflected light. This makes it possible to detect that the finger 352 has touched the display device 50D.
  • Figure 42C shows an example in which the light receiving element 130S is used as a non-contact sensor. As shown in Figure 42C, light emitted by a light emitting element in layer 357 is reflected by a finger 352 that is close to (i.e., not in contact with) the display device 50D, and the light receiving element in layer 353 detects the reflected light.
  • ⁇ Display device 50E> 43A is an example of a display device to which an MML (metal maskless) structure is applied, that is, the display device 50E has light-emitting elements fabricated without using a fine metal mask.
  • MML metal maskless
  • the island-shaped light-emitting layer in the light-emitting element of a display device to which the MML structure is applied is formed by depositing a light-emitting layer on one surface and then processing it using photolithography. This makes it possible to realize a high-definition display device or a display device with a high aperture ratio, which has been difficult to achieve until now. Furthermore, since the light-emitting layer can be made separately for each color, a display device that is extremely vivid, has high contrast, and has high display quality can be realized.
  • a display device is composed of three types of light-emitting elements, one that emits blue light, one that emits green light, and one that emits red light
  • the deposition of the light-emitting layer and processing by photolithography can be repeated three times to form three types of island-shaped light-emitting layers.
  • Devices with an MML structure can be manufactured without using a metal mask, and therefore can exceed the upper limit of fineness resulting from the alignment accuracy of the metal mask. Furthermore, when devices are manufactured without using a metal mask, the equipment required for manufacturing the metal mask and the process of cleaning the metal mask are unnecessary. Furthermore, since the same or similar equipment as that used to manufacture transistors can be used for photolithography processing, there is no need to introduce special equipment to manufacture devices with an MML structure. In this way, the MML structure makes it possible to keep manufacturing costs low, making it suitable for mass production of devices.
  • a display device to which the MML structure is applied for example, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement, so it is possible to realize a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) with a so-called stripe arrangement in which R, G, and B sub-pixels are each arranged in one direction.
  • a special pixel arrangement such as a pentile arrangement
  • the layered structure from the substrate 151 to the insulating layer 235, and the layered structure from the protective layer 131 to the substrate 152 are similar to those of the display device 50A, and therefore will not be described.
  • light-emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130R shown in FIG. 43A emits red light (R).
  • the layer 133R has a light-emitting layer that emits red light.
  • the layer 133R and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124R and the conductive layer 126R can be referred to as a pixel electrode.
  • the light-emitting element 130G has a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130G shown in FIG. 43A emits green light (G).
  • the layer 133G has a light-emitting layer that emits green light.
  • the layer 133G and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124G and the conductive layer 126G can be referred to as a pixel electrode.
  • the light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130B shown in FIG. 43A emits blue light (B).
  • the layer 133B has a light-emitting layer that emits blue light.
  • the layer 133B and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layer 124B and the conductive layer 126B can be referred to as a pixel electrode.
  • layers provided in an island shape for each light-emitting element are indicated as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is indicated as common layer 114.
  • the layer 133R, layer 133G, and layer 133B may be referred to as an island-shaped EL layer or an EL layer formed in an island shape, without including the common layer 114.
  • a light-emitting element manufactured without using a metal mask may not have a common layer, and all layers constituting the EL layer may be formed in an island shape.
  • Layer 133R, layer 133G, and layer 133B are separated from each other.
  • an island-like EL layer for each light-emitting element it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission caused by crosstalk, and to realize a display device with extremely high contrast.
  • layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limited to this.
  • the thicknesses of layers 133R, 133G, and 133B may be different.
  • the conductive layer 124R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 218, and the insulating layer 235.
  • the conductive layer 124G is electrically connected to the conductive layer 112b of the transistor 205G
  • the conductive layer 124B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235.
  • Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.
  • Layer 128 has the function of planarizing the recesses of conductive layers 124R, 124G, and 124B.
  • Conductive layers 126R, 126G, and 126B that are electrically connected to conductive layers 124R, 124G, and 124B are provided on conductive layers 124R, 124G, and 124B and layer 128. Therefore, the regions that overlap with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for conductive layer 124R and conductive layer 126R.
  • Layer 128 may be an insulating layer or a conductive layer.
  • Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128.
  • layer 128 is preferably formed using an insulating material, and is particularly preferably formed using an organic insulating material.
  • the organic insulating material that can be used for insulating layer 237 described above can be used for layer 128.
  • FIG. 43A shows an example in which the top surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited.
  • the top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.
  • the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other.
  • the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.
  • the end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees.
  • the layer 133R provided along the side of the pixel electrode has an inclined portion.
  • the conductive layers 124G, 126G and the conductive layers 124B, 126B are similar to the conductive layers 124R, 126R, so detailed description will be omitted.
  • conductive layer 126R The upper and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the upper and side surfaces of conductive layer 126G are covered by layer 133G, and the upper and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area in which conductive layers 126R, 126G, and 126B are provided can be used as the light-emitting area of light-emitting elements 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.
  • a portion of the top surface and the side surfaces of layers 133R, 133G, and 133B are covered with insulating layers 125 and 127.
  • a common layer 114 is provided on layers 133R, 133G, 133B, and insulating layers 125 and 127, and a common electrode 115 is provided on common layer 114.
  • Common layer 114 and common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.
  • the insulating layer 237 shown in FIG. 40A and the like is not provided between the conductive layer 126R and the layer 133R.
  • the display device 50E does not have an insulating layer (also called a partition, bank, spacer, etc.) that contacts the pixel electrode and covers the upper end of the pixel electrode. This allows the distance between adjacent light-emitting elements to be extremely narrow. This allows a high-definition or high-resolution display device to be obtained.
  • a mask for forming the insulating layer is not required, which reduces the manufacturing costs of the display device.
  • each of the layers 133R, 133G, and 133B has a light-emitting layer.
  • Each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to suppress exposure of the light-emitting layer to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.
  • the common layer 114 has, for example, an electron injection layer or a hole injection layer.
  • the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together.
  • the common layer 114 is shared by the light-emitting elements 130R, 130G, and 130B.
  • Insulating layer 125 covers the sides of layers 133R, 133G, and 133B via insulating layer 125.
  • the side surfaces (and even parts of the top surfaces) of layers 133R, 133G, and 133B are covered with at least one of insulating layers 125 and 127, which prevents the common layer 114 (or common electrode 115) from coming into contact with the pixel electrodes and the side surfaces of layers 133R, 133G, and 133B, thereby preventing short circuits in the light-emitting elements. This improves the reliability of the light-emitting elements.
  • the insulating layer 125 has an area in contact with each side surface of the layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with the layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.
  • the insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. It is preferable that the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.
  • the gap between adjacent island-shaped layers can be filled, reducing the large unevenness of the surface on which layers (such as the carrier injection layer and the common electrode) are formed on the island-shaped layers, making it possible to make the surface flatter. This improves the coverage of the carrier injection layer, the common electrode, etc.
  • the common layer 114 and the common electrode 115 are provided on the layers 133R, 133G, and 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, there is a step between the region where the pixel electrode and the island-shaped EL layer are provided and the region (region between the light-emitting elements) where the pixel electrode and the island-shaped EL layer are not provided. In the display device of one embodiment of the present invention, the step can be flattened by having the insulating layer 125 and the insulating layer 127, and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, poor connection due to step disconnection can be suppressed. In addition, the step can be suppressed from locally thinning the common electrode 115 and increasing the electrical resistance.
  • the upper surface of the insulating layer 127 preferably has a highly flat shape.
  • the upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface.
  • the upper surface of the insulating layer 127 preferably has a convex curved shape with a large radius of curvature.
  • the insulating layer 125 can be a single layer structure or a laminated structure of two or more layers.
  • the insulating layer 125 preferably has one or more inorganic insulating layers.
  • the insulating layer 125 can be made of a material that can be used for the insulating layer 110.
  • aluminum oxide is preferable because it has a high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer in the formation of the insulating layer 127.
  • an inorganic insulating film such as an aluminum oxide film, a hafnium oxide film, or a silicon oxide film formed by the ALD method to the insulating layer 125, it is possible to form an insulating layer 125 that has few pinholes and has an excellent function of protecting the EL layer.
  • the insulating layer 125 may also be a laminated structure of a film formed by the ALD method and a film formed by the sputtering method.
  • the insulating layer 125 may be a laminated structure of, for example, an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.
  • the insulating layer 125 preferably functions as a barrier insulating layer against at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of suppressing the diffusion of at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of capturing or fixing (gettering) at least one of water and oxygen.
  • the insulating layer 125 functions as a barrier insulating layer, making it possible to suppress the intrusion of impurities (typically at least one of water and oxygen) that may diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and further a highly reliable display device.
  • impurities typically at least one of water and oxygen
  • the insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or carbon concentration, or preferably both.
  • the insulating layer 127 provided on the insulating layer 125 has the function of flattening the unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.
  • an insulating layer containing an organic material can be suitably used.
  • the organic material it is preferable to use a photosensitive resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.
  • the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulating layer 127 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.
  • PVA polyvinyl alcohol
  • a photoresist may be used as the photosensitive resin.
  • Either a positive-type material or a negative-type material may be used as the photosensitive resin.
  • the insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb the light emitted from the light-emitting element, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (such as polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials that can be used in color filters color filter materials.
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • Fig. 43B shows an example of a cross section of the display unit 162 of the display device 50F.
  • the display device 50F is mainly different from the display device 50E in that a colored layer (such as a color filter) is provided in each subpixel of each color.
  • the configuration shown in Fig. 43B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in Fig. 43A.
  • the display device 50F shown in FIG. 43B has light emitting elements 130R, 130G, and 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50F via the colored layer 132R.
  • the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50F via the colored layer 132G.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50F via the colored layer 132B.
  • Each of the light-emitting elements 130R, 130G, and 130B has a layer 133. These three layers 133 are formed using the same material and in the same process. In addition, these three layers 133 are separated from one another. By providing an island-like EL layer for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission due to crosstalk, and to realize a display device with extremely high contrast.
  • the light emitting elements 130R, 130G, and 130B shown in FIG. 43B emit white light.
  • the white light emitted by the light emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B to obtain light of the desired color.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 43B emit blue light.
  • the layer 133 has one or more light-emitting layers that emit blue light.
  • the blue light emitted by the light-emitting element 130B can be extracted.
  • a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • a colored layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a colored layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G.
  • a display device 50G shown in FIG. 44 differs from the display device 50F mainly in that it is a bottom emission type display device.
  • Light emitted by the light-emitting element is emitted toward the substrate 151. It is preferable to use a material that is highly transparent to visible light for the substrate 151. On the other hand, the translucency of the material used for the substrate 152 does not matter.
  • FIG. 44 shows an example in which the light-shielding layer 117 is provided on the substrate 151, the insulating layer 153 is provided on the light-shielding layer 117, and the transistors 205D, 205R (not shown), 205G, and 205B are provided on the insulating layer 153.
  • the colored layers 132R, 132G, and 132B are provided on the insulating layer 218, and the insulating layer 235 is provided on the colored layers 132R, 132G, and 132B.
  • the light-emitting element 130R which overlaps with the colored layer 132R, has a conductive layer 124R, a conductive layer 126R, a layer 133, a common layer 114, and a common electrode 115.
  • the light-emitting element 130G which overlaps with the colored layer 132G, has a conductive layer 124G, a conductive layer 126G, a layer 133, a common layer 114, and a common electrode 115.
  • the light-emitting element 130B which overlaps with the colored layer 132B, has a conductive layer 124B, a conductive layer 126B, a layer 133, a common layer 114, and a common electrode 115.
  • the conductive layers 124R, 124G, 124B, 126R, 126G, and 126B are each made of a material that is highly transparent to visible light. It is preferable to use a material that reflects visible light for the common electrode 115. In a bottom emission display device, a metal with low electrical resistivity can be used for the common electrode 115, so that voltage drops caused by the electrical resistance of the common electrode 115 can be suppressed, and high display quality can be achieved.
  • the transistor of one embodiment of the present invention can be miniaturized and its occupation area can be reduced, so that in a display device with a bottom emission structure, the pixel aperture ratio can be increased or the pixel size can be reduced.
  • a display device 50H shown in FIG. 45 is a VA mode liquid crystal display device.
  • Substrate 151 and substrate 152 are bonded together by adhesive layer 144.
  • Liquid crystal 262 is sealed in the area surrounded by substrate 151, substrate 152, and adhesive layer 144.
  • Polarizing plate 260a is located on the outer surface of substrate 152
  • polarizing plate 260b is located on the outer surface of substrate 151.
  • a backlight can be provided outside polarizing plate 260a or polarizing plate 260b.
  • Transistors 205D, 205R, and 205G, a connection portion 197, a spacer 224, and the like are provided on the substrate 151.
  • the transistor 205D is provided in the circuit portion 164, and the transistors 205R and 205G are provided in the display portion 162.
  • the conductive layer 112b of the transistors 205R and 205G functions as a pixel electrode of the liquid crystal element 60.
  • the substrate 152 is provided with colored layers 132R and 132G, a light-shielding layer 117, an insulating layer 225, a conductive layer 263, etc.
  • the conductive layer 263 functions as a common electrode for the liquid crystal element 60.
  • Transistors 205D, 205R, and 205G each have a conductive layer 112a, a semiconductor layer 108, an insulating layer 106, a conductive layer 104, and a conductive layer 112b.
  • the conductive layer 112a functions as one of the source electrode and the drain electrode, and the conductive layer 112b functions as the other of the source electrode and the drain electrode.
  • the conductive layer 104 functions as a gate electrode.
  • a part of the insulating layer 106 functions as a gate insulating layer.
  • the display device 50H includes transistors of one embodiment of the present invention in both the display portion 162 and the circuit portion 164.
  • the pixel size can be reduced, leading to higher resolution.
  • the area occupied by the circuit portion 164 can be reduced, leading to a narrower frame.
  • Transistors 205D, 205R, and 205G are covered with insulating layer 218.
  • Insulating layer 218 functions as a protective layer for transistors 205D, 205R, and 205G.
  • the subpixels of the display unit 162 each have a transistor, a liquid crystal element 60, and a colored layer.
  • a subpixel that emits red light has a transistor 205R, a liquid crystal element 60, and a colored layer 132R that transmits red light.
  • a subpixel that emits green light has a transistor 205G, a liquid crystal element 60, and a colored layer 132G that transmits green light.
  • a subpixel that emits blue light similarly has a transistor, a liquid crystal element 60, and a colored layer that transmits blue light.
  • the liquid crystal element 60 has a conductive layer 112b, a conductive layer 263, and a liquid crystal 262 sandwiched between them.
  • a conductive layer 264 is provided, which is located on the same plane as the conductive layer 112a.
  • the conductive layer 264 has a portion that overlaps with the conductive layer 112b via the insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c).
  • a storage capacitance is formed by the conductive layer 112b, the conductive layer 264, and the insulating layer 110 between them. Note that it is sufficient that there is one or more insulating layers between the conductive layer 112b and the conductive layer 264, and one or two of the insulating layers 110 may be removed by etching.
  • an insulating layer 225 is provided to cover the colored layers 132R and 132G and the light-shielding layer 117.
  • the insulating layer 225 may also function as a planarizing layer.
  • the insulating layer 225 can make the surface of the conductive layer 263 roughly flat, thereby making the orientation state of the liquid crystal 262 uniform.
  • an alignment film for controlling the alignment of the liquid crystal 262 may be provided on the surfaces of the conductive layer 263 and the insulating layer 218, etc. that come into contact with the liquid crystal 262 (see the alignment film 265 in Figures 47A and 47B).
  • the conductive layer 112b and the conductive layer 263 transmit visible light.
  • it can be a transmissive liquid crystal device.
  • the orientation of the liquid crystal 262 can be controlled by the voltage applied between the conductive layer 112b and the conductive layer 263, and the optical modulation of the light can be controlled.
  • the intensity of the light emitted through the polarizing plate 260b can be controlled.
  • the colored layer absorbs light other than a specific wavelength range of the incident light, so that the extracted light is, for example, red light.
  • a linear polarizing plate may be used as polarizing plate 260b, but a circular polarizing plate may also be used.
  • a linear polarizing plate and a quarter-wave retardation plate stacked together may be used as the circular polarizing plate.
  • the conductive layer 263 is electrically connected to the conductive layer 166b provided on the substrate 151 side by the connector 223 at the connection portion 140.
  • the conductive layer 166b is connected to the conductive layer 165b through an opening provided in the insulating layer 110. This allows a potential or signal to be supplied to the conductive layer 263 from an FPC or IC arranged on the substrate 151 side.
  • the configuration shown in FIG. 45 shows an example in which the conductive layer 165b is formed in the same process using the same material as the conductive layer 112a, and an example in which the conductive layer 166b is formed in the same process using the same material as the conductive layer 112b.
  • conductive particles can be used.
  • the conductive particles particles such as resin or silica whose surfaces are coated with a metal material can be used. Nickel or gold is preferably used as the metal material because it can reduce the contact resistance. It is also preferable to use particles coated with two or more metal materials in layers, such as nickel further coated with gold. It is also preferable to use a material that undergoes elastic or plastic deformation as the connector 223. In this case, the conductive particles may be crushed in the vertical direction as shown in FIG. 45. This increases the contact area between the connector 223 and the conductive layer electrically connected thereto, thereby reducing the contact resistance and suppressing the occurrence of problems such as poor connection. It is preferable to arrange the connector 223 so that it is covered by the adhesive layer 144. For example, it is preferable to disperse the connector 223 in the adhesive layer 144 before hardening.
  • connection portion 197 is provided in a region near the end of the substrate 151.
  • the conductive layer 166a is electrically connected to the FPC 172 via the connection layer 242.
  • the conductive layer 166a is connected to the conductive layer 165a via an opening provided in the insulating layer 110.
  • the configuration shown in FIG. 45 shows an example in which the conductive layer 165a is formed in the same process as the conductive layer 112a using the same material, and the conductive layer 166a is formed in the same process as the conductive layer 112b using the same material.
  • ⁇ Display device 50I> 46 is a liquid crystal display device in the FFS mode.
  • the display device 50I differs from the display device 50H mainly in the configuration of the liquid crystal element 60.
  • a conductive layer 263 that functions as a common electrode of the liquid crystal element 60 is provided on the insulating layer 110, and an insulating layer 261 is provided on the conductive layer 263.
  • a conductive layer 112b that functions as the other of the source electrode and drain electrode of the transistor and as a pixel electrode of the liquid crystal element 60 is provided on the insulating layer 261.
  • An insulating layer 218 is provided on the conductive layer 112b.
  • the conductive layer 112b has a comb-like shape or a shape with slits in a plan view.
  • the conductive layer 263 is disposed so as to overlap the conductive layer 112b. In the area overlapping the colored layer, there is a portion on the conductive layer 263 where the conductive layer 112b is not disposed.
  • a capacitance is formed by stacking the conductive layer 112b and the conductive layer 263 with the insulating layer 261 interposed therebetween. This eliminates the need to form a separate capacitive element, and allows the aperture ratio of the pixel to be increased.
  • ⁇ Display device 50J> In the display device 50J shown in Fig. 47A, the portion of the insulating layer 110b that overlaps with the liquid crystal element 60 is removed by etching.
  • the liquid crystal element 60 of the display device 50J has a portion in which a conductive layer 112b, an insulating layer 110a, an insulating layer 110c, and a conductive layer 112m are stacked in this order.
  • the conductive layer 112b functions as a pixel electrode of the liquid crystal element 60.
  • the conductive layer 112m functions as a common electrode of the liquid crystal element 60.
  • the conductive layer 112m is formed from the same conductive film as the conductive layer 112a.
  • either one or both of the insulating layers 106 and 218 may have a portion that overlaps with the liquid crystal element 60 removed by etching.
  • the insulating layer 218 may not be provided. This allows the electric field of the conductive layer 112b and the conductive layer 112m to be easily transmitted to the liquid crystal 262, enabling the liquid crystal element 60 to operate at high speed. Furthermore, not only is the light transmittance in the portion that overlaps with the liquid crystal element 60 increased, but the effects of interface reflection and interface scattering can be suppressed.
  • either one of the insulating layers 110a and 110c may have a portion that overlaps with the liquid crystal element 60 removed by etching. This also allows the electric field of the conductive layer 112b and the conductive layer 112m to be easily transmitted to the liquid crystal 262. Furthermore, the capacitance between the conductive layer 112b and the conductive layer 112m may be increased in some cases.
  • both the conductive layer 112b and the conductive layer 112m may have a comb-like upper surface shape.
  • the conductive layer 112b and the conductive layer 112m are configured to partially overlap. This allows the capacitance between the conductive layer 112b and the conductive layer 112m to be used as a storage capacitance, eliminating the need to provide a separate capacitive element and increasing the aperture ratio of the display device.
  • ⁇ Display device 50K> 47B is different from the display device 50I mainly in that a common electrode is provided over a pixel electrode.
  • a conductive layer 112b included in the transistor 100 functions as a pixel electrode in the liquid crystal element 60.
  • An insulating layer 106 and an insulating layer 218 are provided over the conductive layer 112b, and a conductive layer 263 is provided over the insulating layer 218.
  • the conductive layer 263 functions as a common electrode in the liquid crystal element 60.
  • the conductive layer 263 has a comb-like shape or a shape provided with slits in a plan view.
  • the electronic device of this embodiment has a display device of one embodiment of the present invention in a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, it can be used in the display portion of various electronic devices.
  • the semiconductor device of one embodiment of the present invention can be applied to parts other than the display part of an electronic device.
  • the semiconductor device of one embodiment of the present invention in a control part of an electronic device, it is possible to reduce power consumption, which is preferable.
  • Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, and MR devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the electronic device of this embodiment can be configured to have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 48A to 48D An example of a wearable device that can be worn on the head will be described using Figures 48A to 48D.
  • These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • a function to display AR content a function to display AR content
  • VR content a function to display VR content
  • SR content a function to display SR content
  • MR content a function to display MR content
  • a display device can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.
  • Electronic device 700A and electronic device 700B can each project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visible through optical member 753. Therefore, electronic device 700A and electronic device 700B are each electronic devices capable of AR display.
  • Electronic device 700A and electronic device 700B can be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B can each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and power supply potential can be connected.
  • Electronic device 700A and electronic device 700B are provided with a battery (not shown) and can be charged wirelessly, wired, or both.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • touch sensors can be used as the touch sensor module.
  • various types can be adopted, such as the capacitance type, resistive film type, infrared type, electromagnetic induction type, surface acoustic wave type, and optical type.
  • a photoelectric conversion element When using an optical touch sensor, a photoelectric conversion element can be used as the light receiving element.
  • the active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in Fig. 48C and electronic device 800B shown in Fig. 48D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832. Note that display unit 820, communication unit 822, and imaging unit 825 are omitted in Fig. 48D.
  • a display device can be applied to the display portion 820. Therefore, the electronic device can display images with extremely high resolution. This allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform a three-dimensional display using parallax.
  • the electronic device 800A and the electronic device 800B can each be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.
  • the attachment unit 823 allows the user to attach the electronic device 800A or electronic device 800B to the head. Note that in FIG. 48C and other figures, the attachment unit 823 is shaped like the temples of glasses, but is not limited to this. The attachment unit 823 may be shaped like a helmet or band, for example, as long as it can be worn by the user.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio by simply wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 48A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 48C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may have an earphone unit.
  • the electronic device 700B shown in FIG. 48B has an earphone unit 727.
  • the earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • a portion of the wiring connecting the earphone unit 727 and the control unit may be disposed inside the housing 721 or the attachment unit 723.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • electronic devices according to one embodiment of the present invention are suitable for both glasses-type devices (such as electronic device 700A and electronic device 700B) and goggle-type devices (such as electronic device 800A and electronic device 800B).
  • the electronic device of one embodiment of the present invention can transmit information to the earphones via wire or wirelessly.
  • the electronic device 6500 has a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508.
  • the display portion 6502 has a touch panel function.
  • the display device of one embodiment of the present invention can be applied to the display portion 6502.
  • Figure 49B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a translucent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • the display device of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 49C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • a display device can be applied to the display portion 7000.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to carry out one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • a display device can be applied to the display portion 7000.
  • Figures 49E and 49F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 49E has a housing 7301, a display unit 7000, and a speaker 7303. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, etc.
  • Figure 49F shows digital signage 7400 attached to a cylindrical pole 7401.
  • Digital signage 7400 has a display unit 7000 that is provided along the curved surface of pole 7401.
  • a display device according to one embodiment of the present invention can be applied to the display portion 7000.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of an advertisement, for example.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the electronic device shown in Figures 50A to 50G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light), a microphone 9008, etc.
  • a display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the electronic devices shown in Figures 50A to 50G have various functions. For example, they can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to control processing by various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc.
  • the functions of the electronic devices are not limited to these, and they can have various functions.
  • the electronic devices may have multiple display units.
  • the electronic devices may have a function to provide a camera or the like, capture still images or videos, and store them on a recording medium (external or built into the camera), display the captured images on the display unit, etc.
  • FIG. 50A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as a smartphone, for example.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • FIG. 50A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, and telephone calls, the title of e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength.
  • an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • Figure 50B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.
  • FIG. 50C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG. 50D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used, for example, as a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also make hands-free calls by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also transmit data to and from other information terminals and charge itself via a connection terminal 9006. Charging may be performed by wireless power supply.
  • FIG. 50E to 50G are perspective views showing a foldable mobile information terminal 9201.
  • FIG. 50E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • FIG. 50G is a perspective view of the mobile information terminal 9201 in a folded state
  • FIG. 50F is a perspective view of a state in the process of changing from one of FIG. 50E and FIG. 50G to the other.
  • the mobile information terminal 9201 is highly portable when folded, and is highly viewable due to a seamless, wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.

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PCT/IB2024/055638 2023-06-16 2024-06-10 半導体装置、及び半導体装置の作製方法 Ceased WO2024256943A1 (ja)

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