WO2024255099A1 - 一种半导体器件及其制造方法 - Google Patents

一种半导体器件及其制造方法 Download PDF

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Publication number
WO2024255099A1
WO2024255099A1 PCT/CN2023/131516 CN2023131516W WO2024255099A1 WO 2024255099 A1 WO2024255099 A1 WO 2024255099A1 CN 2023131516 W CN2023131516 W CN 2023131516W WO 2024255099 A1 WO2024255099 A1 WO 2024255099A1
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WIPO (PCT)
Prior art keywords
sub
trench
dielectric layer
layer
isolation
Prior art date
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PCT/CN2023/131516
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English (en)
French (fr)
Inventor
肖德元
杨晨
金泰均
邱云松
蒋懿
廖昱程
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Publication of WO2024255099A1 publication Critical patent/WO2024255099A1/zh
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/315—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor with the capacitor higher than a bit line
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/482—Bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48—Data lines or contacts therefor
    • H10B12/488—Word lines

Definitions

  • the embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a semiconductor device and a method for manufacturing the same.
  • the storage unit of Dynamic Random Access Memory includes a transistor and a capacitor (1 Transistor 1 Capacitor, 1T1C).
  • the gate of the transistor is connected to the word line, the source of the transistor is connected to the bit line, and the drain of the transistor is connected to the capacitor.
  • embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:
  • a substrate comprising a device region and a peripheral region, the device region comprising a first sub-region and a second sub-region, the second sub-region being located between the first sub-region and the peripheral region;
  • the substrate of the device region comprises a plurality of first isolation structures extending along a first direction and a plurality of second isolation structures extending along a second direction, the first isolation structures and the second isolation structures jointly isolate a plurality of active pillars;
  • the first isolation structure comprises a first sub-isolation structure located in the first sub-region and a second sub-isolation structure located in the second sub-region, the first sub-isolation structure comprises a first dielectric layer filling up a first sub-groove, the second sub-isolation structure comprises a first dielectric layer sequentially covering a sidewall and a bottom of the second sub-groove, a first isolation layer, and a second dielectric layer filling up the second sub-groove; wherein the first direction and the second direction are both parallel to the
  • the portion of the first isolation layer exposed in the second sub-trench is removed.
  • the second isolation structure includes a third sub-isolation structure located in the first sub-region and a fourth sub-isolation structure located in the second sub-region
  • the third sub-isolation structure includes a third dielectric layer filling the third sub-trench
  • the fourth sub-isolation structure includes a third dielectric layer sequentially covering the sidewall and bottom of the fourth sub-trench, a second isolation layer, and a fourth dielectric layer filling the fourth sub-trench;
  • the manufacturing method further includes:
  • the third isolation layer covers the first isolation structure and the second isolation structure of the device region;
  • a portion of the third isolation layer is removed to retain the third isolation layer covering the fourth dielectric layer in the fourth sub-trench.
  • the manufacturing method while removing a portion of the first dielectric layer in the first sub-groove and a portion of the first dielectric layer and the second dielectric layer in the second sub-groove, the manufacturing method further includes:
  • a portion of the third dielectric layer in the third sub-trench and a portion of the third dielectric layer in the fourth sub-trench are removed to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the second isolation layer.
  • the manufacturing method further includes:
  • a portion of the fourth dielectric layer in the fourth sub-groove is removed; wherein a surface of the fourth dielectric layer in the fourth sub-groove is higher than a surface of the third dielectric layer.
  • the manufacturing method while removing the portion of the first isolation layer exposed in the second sub-trench, the manufacturing method further includes:
  • a portion of the second isolation layer exposed in the fourth sub-trench is removed.
  • the active pillar includes a first end and a second end disposed opposite to each other along a third direction and a channel region between the first end and the second end; the third direction is perpendicular to the substrate;
  • the manufacturing method further includes:
  • a plurality of word line structures extending along the second direction are formed; the word line structures cover the channel regions of the active pillars in the same row.
  • first sub-groove and the second sub-groove together form a first groove
  • third sub-groove and the fourth sub-groove together form a second groove
  • the forming of a plurality of word line structures extending along the second direction comprises:
  • a gate dielectric layer at least covering a channel region of the active pillar in the first trench and the second trench;
  • a gate conductive layer covering at least a portion of the gate dielectric layer is formed in the first trench and the second trench; the gate conductive layer encapsulates the channel region of the active pillar located in the same row, and the gate conductive layers in the first sub-trench and the second sub-trench are electrically connected; wherein the gate dielectric layer and the gate conductive layer together form a word line structure.
  • forming a gate conductive layer in the first trench and the second trench to at least cover a portion of the gate dielectric layer includes:
  • the fourth isolation layer and the conductive material layer in the second trench are sequentially etched to form a word line trench and a gate conductive layer; wherein the word line trench extends along the second direction; the gate conductive layer in the second sub-trench is in direct contact with the gate dielectric layer, and the gate conductive layer in the fourth sub-trench is in direct contact with the fourth dielectric layer;
  • An isolation material is filled in the word line isolation groove to form a word line isolation structure.
  • the manufacturing method further includes:
  • bit line structures extending along the first direction; the bit line structures sequentially connecting the first ends of the active pillars located in the same column;
  • a plurality of storage capacitors are formed; the first electrodes of the storage capacitors are connected to the second ends of the active pillars, and the second electrodes of the storage capacitors are connected to a common end.
  • providing a substrate comprises:
  • first dielectric layer covers the sidewalls and the bottom of the second sub-trench and the third trench, and the first dielectric layer fills the first sub-trench to form a first sub-isolation structure
  • first isolation layer covers the first dielectric layer
  • a second dielectric layer is formed, and the second dielectric layer fills up the second sub-trench and the third trench to form a second sub-isolation structure and a third isolation structure, respectively.
  • providing a substrate further comprises:
  • a fourth dielectric layer is formed, wherein the fourth dielectric layer fills up the fourth sub-trench to form a fourth sub-isolation structure.
  • an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:
  • a substrate comprising a device region and a peripheral region, the device region comprises a first sub-region and a second sub-region, the second sub-region is located between the first sub-region and the peripheral region;
  • the substrate of the device region includes a plurality of first trenches extending along a first direction and a plurality of second trenches extending along a second direction, wherein the first trenches and the second trenches together isolate a plurality of active pillars;
  • the active pillars include a first end and a second end oppositely arranged along a third direction and a channel region located between the first end and the second end;
  • the first trench includes a first sub-trench located in the first sub-region and a second sub-trench located in the second sub-region; wherein the first direction and the second direction are both parallel to the substrate and intersect with the first direction, and the third direction is perpendicular to the substrate;
  • a plurality of word line structures extending along the second direction are located in the first trench and the second trench; the word line structures cover the channel regions of the active pillars located in the same row; wherein the word line structures in the first sub-trench and the word line structures in the second sub-trench are electrically connected.
  • the semiconductor device further comprises:
  • a fourth isolation layer extending along the second direction and located in the first trench and the second trench; the fourth isolation layer covers the second ends of the active pillars located in the same row;
  • a plurality of word line isolation structures extending along the second direction are located between adjacent word line structures and adjacent fourth isolation layers.
  • the word line structure includes:
  • a gate dielectric layer at least covers the channel region of the active pillar
  • a gate conductive layer is located on the surface of the gate dielectric layer and covers the channel region of the active pillars located in the same row; wherein the gate conductive layer in the first sub-groove is electrically connected to the gate conductive layer in the second sub-groove, and the gate conductive layer in the second sub-groove is in direct contact with the gate dielectric layer.
  • the semiconductor device further comprises:
  • a second dielectric layer is located in the second sub-trench, and the second dielectric layer is located below the gate conductive layer.
  • the second trench includes a third sub-trench located in the first sub-region and a fourth sub-trench located in the second sub-region; and the semiconductor device further includes:
  • a third dielectric layer located in the third sub-trench and the fourth sub-trench, wherein the third dielectric layer is located between the first ends of adjacent active pillars and covers the sidewall and bottom of the fourth sub-trench;
  • a fourth dielectric layer is located in the fourth sub-trench, and a sidewall of the fourth dielectric layer is in direct contact with the gate conductive layer and the fourth isolation layer.
  • the semiconductor device further comprises:
  • the third isolation structure located in the peripheral region and extending along the first direction, the third isolation structure comprising a first portion and a second portion, and a portion of the second trench extending into the third isolation structure being the second portion;
  • the first part includes a first dielectric layer, a first isolation layer, and a second dielectric layer covering the first isolation layer in sequence;
  • the second portion includes a third dielectric layer and a second isolation layer which sequentially cover the second trench and extend to at least a portion of the sidewall and the bottom of the third isolation structure, and a fourth dielectric layer which fills the second trench and extends to a portion of the third isolation structure.
  • the semiconductor device further comprises:
  • a plurality of storage capacitors a first electrode of the storage capacitor is connected to the second end of the active column, and a second electrode of the storage capacitor is connected to a common end.
  • the disclosed embodiment provides a semiconductor device and a method for manufacturing the same.
  • a portion of the first dielectric layer in the first sub-groove and a portion of the first dielectric layer and the second dielectric layer in the second sub-groove are removed to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the first isolation layer, respectively; the portion of the first isolation layer exposed in the second sub-groove is removed; thus, in the subsequent process of forming a word line structure, the word line structures in the first sub-groove and the second sub-groove can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected.
  • FIG1 is a schematic diagram of a top view of a semiconductor device provided in some examples.
  • FIG2 is a schematic cross-sectional view of a semiconductor device provided in some examples.
  • FIG3 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure
  • FIG4 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present disclosure.
  • 5A to 5O are schematic cross-sectional views of a semiconductor device during the manufacturing process according to an embodiment of the present disclosure
  • FIG6 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present disclosure.
  • FIG. 7 is a schematic cross-sectional structural diagram of a semiconductor device provided in an embodiment of the present disclosure.
  • the three directions may include an X direction, a Y direction, and a Z direction.
  • the X direction and the Y direction are both parallel to the substrate and intersect with the Y direction.
  • the Z direction is perpendicular to the substrate.
  • the storage units may be arranged in an array along the X direction and the Y direction.
  • the X direction may also be referred to as a row direction
  • the Y direction may also be referred to as a column direction.
  • first direction is defined as the Y direction
  • second direction is defined as the X direction
  • third direction is defined as the Z direction.
  • FIG. 1 is a schematic diagram of a top view structure of a semiconductor device provided in some examples
  • FIG. 2 is a schematic diagram of a cross-sectional structure of a semiconductor device provided in some examples.
  • a substrate 100 includes a device region 102 and a peripheral region 104, and the peripheral region 104 can be arranged around the device region 102; wherein a memory cell array is arranged in the device region 102, and the memory cell array includes a plurality of memory cells arranged in an array along the X direction and the Y direction; a peripheral circuit is arranged in the peripheral region 104, and the peripheral circuit can be used to control the memory cell array.
  • the device region 102 includes a first sub-region 106 (as shown in the dotted line box in FIG. 1 ) and a second sub-region 108 (as shown in the dotted line box in FIG. 1 ), and the second sub-region 108 is located between the first sub-region 106 and the peripheral region 104. More specifically, a plurality of active pillars 110 arranged in an array along the X direction and the Y direction are provided in the first sub-region 106.
  • the active pillars include a first end and a second end arranged opposite to each other along the Z direction and a channel region between the first end and the second end.
  • the drain of the transistor may be, for example, the first end of the active pillar
  • the source of the transistor may be, for example, the second end of the active pillar
  • the gate of the transistor may surround the channel region of the active pillar.
  • the first ends of the active pillars located in the same column i.e., arranged along the Y direction
  • the gates outside the channel regions of the active pillars located in the same row i.e., arranged along the X direction
  • the same word line (Word Line, WL), which may extend from the first sub-region to the second sub-region along the X direction.
  • no storage unit is provided in the second sub-region 108, and the second sub-region 108 includes a bit line end (Bit Line End) and a word line end (Word Line End).
  • FIG2 illustrates a schematic cross-sectional view along the a-a direction, b-b direction, c-c direction, d-d direction and e-e direction in FIG1, wherein the schematic cross-sectional views along the a-a direction and the b-b direction both illustrate schematic cross-sectional views of the first sub-region and the second sub-region of the device region along the Y direction; the schematic cross-sectional views along the c-c direction and the d-d direction both illustrate schematic cross-sectional views of the first sub-region and the second sub-region of the device region along the X direction; the schematic cross-sectional view along the e-e direction illustrates schematic cross-sectional views of the peripheral region along the X direction.
  • FIG1 and FIG2 illustrate a vertical channel transistor (Vertical Channel Transistor, VGT), and the vertical channel transistor is a gate-all-around (Gate-All-Around, GAA) structure.
  • VGT Vertical Channel Transistor
  • the substrate 100 of the device area 102 includes a first groove 112 extending along the Y direction, and the first groove 112 includes a first sub-groove 114 located in the first sub-area 106 and a second sub-groove 116 located in the second sub-area 108; the word line structure in the first sub-groove 114 and the word line structure in the second sub-groove 116 may be isolated by a first silicon nitride column 124 (as shown in the dotted circle in FIG2 ), that is, the word line structure located in the first sub-area 106 for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-area 108 may not be electrically connected, and there is a risk of high resistance at the end of the word line structure (WL End High Resistance) and a potential risk of word line structure disconnection (Potential Risk of WL Open).
  • the substrate 100 of the device area 102 also includes a second trench 118 extending along the X direction, and the second trench 118 includes a third sub-trench 120 located in the first sub-area 106 and a fourth sub-trench 122 located in the second sub-area 108; the second silicon nitride column 126 in the fourth sub-trench 122 (as shown in the dotted circle in FIG2 ) may cause pollution to the bit line structure formed in subsequent processes (SIN Pollution Risk).
  • embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same.
  • FIG3 is a schematic flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a method for manufacturing a semiconductor device, the method comprising:
  • Step S301 providing a substrate, the substrate comprising a device region and a peripheral region, the device region comprising a first sub-region and a second sub-region, the second sub-region being located between the first sub-region and the peripheral region; the substrate of the device region comprising a plurality of first isolation structures extending along a first direction and a plurality of second isolation structures extending along a second direction, the first isolation structures and the second isolation structures jointly isolating a plurality of active pillars; the first isolation structure comprising a first sub-isolation structure located in the first sub-region and a second sub-isolation structure located in the second sub-region, the first sub-isolation structure comprising a first dielectric layer filling up a first sub-groove, the second sub-isolation structure comprising a first dielectric layer sequentially covering a sidewall and a bottom of the second sub-groove, a first isolation layer, and a second dielectric layer filling up the second sub-groove; wherein the
  • Step S302 removing a portion of the first dielectric layer in the first sub-trench and a portion of the first dielectric layer and the second dielectric layer in the second sub-trench to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the first isolation layer, respectively;
  • Step S303 removing the portion of the first isolation layer exposed in the second sub-trench.
  • part of the first dielectric layer in the first sub-groove and part of the first dielectric layer and the second dielectric layer in the second sub-groove are removed to expose at least part of the side wall of the active pillar and at least part of the side wall of the first isolation layer, respectively; the part of the first isolation layer exposed in the second sub-groove is removed; in this way, in the subsequent process of forming the word line structure, the word line structures in the first sub-groove and the second sub-groove can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected.
  • Figure 4 is a top view structural schematic diagram of the semiconductor device provided in an embodiment of the present disclosure
  • Figures 5A to 5O are cross-sectional structural schematic diagrams during the manufacturing process of the semiconductor device provided in an embodiment of the present disclosure, which illustrate in detail the manufacturing method of the semiconductor device provided in an embodiment of the present disclosure.
  • Figures 5A to 5O all illustrate schematic cross-sectional structural diagrams along the a-a direction, b-b direction, c-c direction, d-d direction and e-e direction in Figure 4, wherein the schematic cross-sectional structural diagrams along the a-a direction and the b-b direction both illustrate schematic structural diagrams of the first sub-region 206 and the second sub-region 208 of the device region 202 along the Y direction; the schematic cross-sectional structural diagrams along the c-c direction and the d-d direction both illustrate schematic structural diagrams of the first sub-region 206 and the second sub-region 208 of the device region 202 along the X direction; the schematic cross-sectional structural diagram along the e-e direction illustrates a schematic structural diagram of the peripheral region 204 along the X direction.
  • step S301 includes:
  • the substrate 200 is etched to form a first trench 212 in the device region 202 and a third trench 218 in the peripheral region 204; the first trench 212 and the third trench 218 both extend along a first direction; the first trench 212 includes a first sub-trench 214 located in the first sub-region 206 and a second sub-trench 216 located in the second sub-region 208;
  • first dielectric layer 220 Forming a first dielectric layer 220, the first dielectric layer 220 covers the sidewalls and bottom of the second sub-trench 216 and the third trench 218, and the first dielectric layer 220 fills the first sub-trench 214 to form a first sub-isolation structure 228;
  • first isolation layer 222 covers the first dielectric layer 220;
  • a second dielectric layer 224 is formed to fill the second sub-trench 216 and the third trench 218 to form a second sub-isolation structure 230 and a third isolation structure 232 , respectively.
  • the substrate 200 includes a device region (Core) 202 and a peripheral region (Periphery) 204, and the peripheral region 204 can be arranged around the device region 202; wherein the device region 202 includes a first sub-region 206 (as shown in the dotted line box in FIG. 4) and a second sub-region 208 (as shown in the dotted line box in FIG. 4), and the second sub-region 208 is located between the first sub-region 206 and the peripheral region 204.
  • the device region 202 includes a first sub-region 206 (as shown in the dotted line box in FIG. 4) and a second sub-region 208 (as shown in the dotted line box in FIG. 4)
  • the second sub-region 208 is located between the first sub-region 206 and the peripheral region 204.
  • the first sub-region 206 includes a memory cell array, that is, a plurality of memory cells arranged in an array along the X direction and the Y direction; no memory cell is arranged in the second sub-region, and the second sub-region 208 includes a bit line structure end and a word line structure end; the peripheral region 204 includes a peripheral circuit.
  • the bit line structure end is the bit line end
  • the word line structure end is the word line end.
  • the substrate may be a semiconductor substrate; specifically, it may include at least one elemental semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), at least one III-V compound semiconductor material (e.g., a gallium nitride (GaN) substrate, a gallium arsenide (GaAs) substrate, an indium phosphide (InP) substrate, etc.), at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art, and may also include other substrates containing semiconductor materials, such as a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, a polycrystalline semiconductor layer on an insulating layer, a silicon-germanium substrate, etc.
  • SOI silicon-on-insulator
  • GeOI germanium-on-insulator
  • the disclosed embodiments do not specifically limit the material of the substrate.
  • the substrate 200 is etched to form a first trench 212 in the device region 202 and a third trench 218 in the peripheral region 204; wherein the first trench 212 includes a first sub-trench 214 located in the first sub-region 206 and a second sub-trench 216 located in the second sub-region 208; the first sub-trench 214, the second sub-trench 216 and the third trench 218 all extend along the Y direction.
  • the number of the first sub-grooves located in the first sub-region may be, for example, multiple, and the first sub-grooves are used to isolate active pillars located in different columns; the number of the second sub-grooves located in the second sub-region may be, for example, one or two.
  • the second sub-grooves located in the second sub-region may be between the first sub-grooves located in the first sub-region and the third grooves located in the peripheral region, the second sub-grooves may be located on one side of the first sub-region, or the second sub-grooves may be located on opposite sides of the first sub-region.
  • the first trench can be formed in the device region and the third trench can be formed in the peripheral region in the same etching process.
  • the heights of the first sub-trench, the second sub-trench and the third trench along the Z direction are substantially the same.
  • the width of the first sub-trench along the X direction is smaller than the width of the second sub-trench along the X direction, and the width of the first sub-trench along the X direction is smaller than the width of the third trench along the X direction.
  • a first dielectric layer 220 is formed in the first sub-trench 214, the second sub-trench 216, and the third trench 218.
  • the first dielectric layer 220 can fill the first sub-trench 214 to form a first sub-isolation structure, and the first dielectric layer 220 only covers the sidewalls and bottoms of the second sub-trench 216 and the third trench 218.
  • the process of forming the first dielectric layer in the first sub-groove can be performed using the following method, for example, forming a first dielectric material layer in the first sub-groove, the first dielectric material layer covering the substrate surface; performing a planarization process on the first dielectric material layer, removing a portion of the first dielectric material layer to expose the substrate surface, so that the remaining surface of the first dielectric material layer is substantially flush with the substrate surface, and the remaining first dielectric material layer is used as the first dielectric layer.
  • forming the first dielectric layer in the first sub-groove the first dielectric layer covering the substrate surface. In this way, a portion of the first dielectric layer can be removed again in a subsequent process to expose the substrate surface.
  • the planarization process includes but is not limited to a chemical mechanical polishing (CMP) process.
  • CMP chemical mechanical polishing
  • substantially flush means that the height difference between the substrate surface and the first dielectric layer surface along the Z direction is less than a preset value, that is, the height difference between the substrate surface and the first dielectric layer surface along the Z direction meets the process error requirement range.
  • the height difference between the substrate surface and the first dielectric layer surface along the Z direction is 0.
  • the process of forming the first dielectric layer includes but is not limited to chemical vapor deposition.
  • Deposition CVD
  • PVD physical vapor deposition
  • ALD atomic layer deposition
  • the material of the first dielectric layer may include, but is not limited to, silicon dioxide.
  • a first isolation layer 222 is formed in the second sub-groove 216 and the third groove 218, and the first isolation layer 222 covers the first dielectric layer 220;
  • a second dielectric layer 224 is formed in the second sub-groove 216 and the third groove 218, and the second dielectric layer 224 fills the second sub-groove 216 and the third groove 218 to form a second sub-isolation structure 230 and a third isolation structure 232 respectively; wherein the first sub-isolation structure 228 and the second sub-isolation structure 230 together form the first isolation structure 226.
  • the process of forming the first isolation layer and the second dielectric layer includes, but is not limited to, CVD, PVD, and ALD or any combination thereof.
  • the material of the first isolation layer may include but is not limited to silicon nitride; the material of the second dielectric layer may include but is not limited to silicon dioxide.
  • step S301 further includes:
  • the substrate 200, the first dielectric layer 220 and the second dielectric layer 224 are etched to form a second trench 234 in the device region 202, and the second trench 234 also extends into the third trench 218 in the peripheral region 204; the second trench 234 extends along the second direction; the second trench 234 includes a third sub-trench 236 located in the first sub-region 206 and a fourth sub-trench 238 located in the second sub-region 208;
  • third dielectric layer 240 forming a third dielectric layer 240 , wherein the third dielectric layer 240 covers the sidewall and the bottom of the fourth sub-trench 238 , and the third dielectric layer 240 fills up the third sub-trench 236 to form a third sub-isolation structure 248 ;
  • a fourth dielectric layer 244 is formed to fill up the fourth sub-trench 238 to form a fourth sub-isolation structure 250 .
  • the substrate 200, the first dielectric layer 220, and the second dielectric layer 224 are etched to form a second trench 234 in the device region 202.
  • the second trench 234 may extend into the third trench 218 of the peripheral region 204.
  • the second trench 234 includes a third sub-trench 236 in the first sub-region 206 and a fourth sub-trench 238 in the second sub-region 208. Both the third sub-trench 236 and the fourth sub-trench 238 extend along the X direction.
  • the third isolation structure includes a first dielectric layer and a first isolation layer that sequentially cover the sidewall and bottom of the third trench, and a second dielectric layer that fills the third trench.
  • part of the second dielectric layer in the third trench may be etched away, that is, the second trench may extend into the third trench.
  • the third sub-groove and the fourth sub-groove included in the second trench may both extend into the third trench along the X direction.
  • the number of the third sub-grooves located in the first sub-region may be, for example, multiple, and the third sub-grooves are used to isolate active pillars located in different rows;
  • the number of the fourth sub-grooves located in the second sub-region may be, for example, one or two.
  • the fourth sub-groove located in the second sub-region may be between the third sub-groove located in the first sub-region and the third groove located in the peripheral region, the fourth sub-groove may be located on one side of the first sub-region, or the fourth sub-groove may be located on two opposite sides of the first sub-region.
  • the heights of the third sub-groove and the fourth sub-groove along the Z direction are substantially the same, and the width of the third sub-groove along the Y direction is smaller than the width of the fourth sub-groove along the Y direction.
  • the height of the second groove along the Z direction is smaller than the height of the first groove along the Z direction.
  • a third dielectric layer 240 is formed in the third sub-trench 236 and the fourth sub-trench 238.
  • the third dielectric layer 240 can fill the third sub-trench 236 to form the third sub-isolation structure 248, while the third dielectric layer 240 only covers the sidewall and bottom of the fourth sub-trench 238.
  • a third dielectric layer is formed in the third sub-trench, and the third dielectric layer may cover the substrate surface.
  • a portion of the third dielectric layer may be removed in a subsequent process to expose the substrate surface.
  • the material of the third dielectric layer may include but is not limited to silicon dioxide.
  • a second isolation layer 242 is formed, and the second isolation layer 242 can cover the third dielectric layer 240 located on the surface of the substrate 200 and the surface of the third dielectric layer 240 located in the fourth sub-groove 238; a fourth dielectric layer 244 is formed in the fourth sub-groove 238, and the fourth dielectric layer 244 can cover the second isolation layer 242 located on the surface of the substrate 200 and the second isolation layer 242 located in the fourth sub-groove 238; wherein the fourth dielectric layer 244 can fill the fourth sub-groove 238.
  • the second isolation layer covers the device area and the peripheral area.
  • the second isolation layer covers the surface of the first dielectric layer in the first sub-groove of the first sub-area, the surface of the second dielectric layer in the second sub-groove of the second sub-area, and the surface of the second dielectric layer in the third groove of the peripheral area.
  • the fourth dielectric layer will also cover the surface of the second isolation layer in the device area and the peripheral area.
  • the process of forming the third dielectric layer, the second isolation layer and the fourth dielectric layer includes, but is not limited to, CVD, PVD and ALD or any combination thereof.
  • the material of the second isolation layer may include but is not limited to silicon nitride; the material of the fourth dielectric layer may include but is not limited to silicon dioxide.
  • the materials of the first isolation layer and the second isolation layer may be the same or different.
  • the materials of the first dielectric layer, the second dielectric layer, the third dielectric layer, and the fourth dielectric layer may be the same or different.
  • the fourth dielectric layer 244 can be planarized to expose the surface of the second isolation layer 242 located in the device area 202 and the peripheral area 204; the exposed second isolation layer 242 can also be etched back (Etch Back) to expose the first dielectric layer 220 in the first sub-groove 214, the second dielectric layer 224 in the second sub-groove 216, the third dielectric layer 240 in the third sub-groove 236, and the fourth dielectric layer 244 in the fourth sub-groove 238.
  • the second isolation structure includes a third sub-isolation structure and a fourth sub-isolation structure.
  • the third sub-isolation structure includes a third dielectric layer filling the third sub-groove.
  • the fourth sub-isolation structure includes a third dielectric layer sequentially covering the sidewall and bottom of the fourth sub-groove, a second isolation layer, and a fourth dielectric layer filling the fourth sub-groove.
  • the first sub-isolation structure and the second sub-isolation structure extending along the Y direction, and the third sub-isolation structure and the fourth sub-isolation structure extending along the X direction isolate the device area of the substrate into a plurality of active pillars arranged in an array along the X direction and the Y direction. More specifically, the first sub-isolation structure extending along the Y direction and the third sub-isolation structure extending along the X direction isolate the first sub-area of the substrate into a plurality of active pillars arranged in an array.
  • Each active pillar includes a first end and a second end arranged opposite to each other along the Z direction and a channel region between the first end and the second end, the drain of the transistor can be, for example, the first end of the active pillar, the source of the transistor can be, for example, the second end of the active pillar, and the gate of the transistor can surround the channel region of the active pillar.
  • the drains of multiple transistors located in the same column can be connected to the same bit line structure, and the end of the bit line structure is located in the second sub-area; the gates of multiple transistors located in the same row (i.e., arranged along the X direction) can be connected to the same word line structure, and the end of the word line structure is located in the second sub-area.
  • the third isolation structure extending along the Y direction isolates the peripheral region of the substrate into a plurality of active regions, which can be used to form transistors of the peripheral circuit later.
  • first isolation layer covering the sidewall and bottom of the second sub-groove and the first isolation layer covering the sidewall and bottom of the third groove are covered by the second dielectric layer and are not exposed, and the second isolation layer covering the sidewall and bottom of the fourth sub-groove is covered by the fourth dielectric layer and is not exposed. Therefore, it is difficult to remove the first isolation layer or the second isolation layer that is covered and not exposed by the etching back process.
  • the manufacturing method further includes:
  • third isolation layer 252 covers the first isolation structure 226 and the second isolation structure 246 of the device region 202 ;
  • a portion of the third isolation layer 252 is removed to retain the third isolation layer 252 covering the fourth dielectric layer 244 in the fourth sub-trench 238 .
  • a third isolation layer 252 is formed, and the third isolation layer 252 covers the device area 202 and the peripheral area 204; more specifically, the third isolation layer 252 covers the surface of the first isolation structure 226 (i.e., the first sub-isolation structure 228 and the second sub-isolation structure 230) located in the device area 202, the surface of the second isolation structure 246 (i.e., the third sub-isolation structure 248 and the fourth sub-isolation structure 250), and the surface of the third isolation structure 232 located in the peripheral area 204.
  • the first isolation structure 226 i.e., the first sub-isolation structure 228 and the second sub-isolation structure 230
  • the surface of the second isolation structure 246 i.e., the third sub-isolation structure 248 and the fourth sub-isolation structure 250
  • the surface of the third isolation structure 232 located in the peripheral area 204.
  • the process of forming the third isolation layer includes, but is not limited to, CVD, PVD, and ALD or any combination thereof.
  • the material of the third isolation layer includes but is not limited to silicon nitride.
  • a photoresist layer 254 is formed on the third isolation layer 252, and the photoresist layer 254 covers the third isolation layer 252 located in the peripheral region 204 and the fourth dielectric layer 244 located in the fourth sub-groove 238 of the second sub-region 208.
  • the orthographic projection of the third isolation structure 232 on the XY plane is within the range of the orthographic projection of the photoresist layer 254 on the XY plane
  • the orthographic projection of the fourth dielectric layer 244 of the fourth sub-isolation structure 250 on the XY plane is within the range of the orthographic projection of the photoresist layer 254 on the XY plane.
  • the photoresist layer 254 is used as a mask to remove the portion of the third isolation layer 252 not covered by the photoresist layer 254 , so as to retain the portion of the third isolation layer 252 covered by the photoresist layer 254 ; the photoresist layer 254 is removed.
  • the photoresist layer may be removed using an ashing process.
  • 5F shows that the third isolation layer 252 covering the peripheral region 204 and the third isolation layer 252 covering the fourth dielectric layer 244 in the fourth sub-groove 238 of the second sub-region 208 are still retained.
  • the third isolation layer can play a protective role to prevent the subsequent process from damaging the third isolation structure in the peripheral region and the fourth dielectric layer in the fourth sub-groove of the second sub-region.
  • the manufacturing method further includes:
  • a portion of the third dielectric layer 240 in the third sub-trench 236 and a portion of the third dielectric layer 240 in the fourth sub-trench 238 are removed to expose at least a portion of the sidewall of the active pillar 210 and at least a portion of the sidewall of the second isolation layer 242 .
  • a portion of the third dielectric layer 240 in the third sub-groove 236 and a portion of the third dielectric layer 240 in the fourth sub-groove 238 are removed; wherein, the portion of the first dielectric layer 220 in the first sub-groove 214 is removed to expose the side wall of the active pillar 210 parallel to the Y direction, the portion of the first dielectric layer 220 and the second dielectric layer 224 in the second sub-groove 216 is removed to expose the side wall of the active pillar 210 parallel to the Y direction and the two side walls of the first isolation layer 222 parallel to the Y direction, and the portion of the third sub-groove 236 is removed to expose the side wall of the active pillar 210 parallel to the Y direction and the
  • a portion of the third dielectric layer 240 in the fourth sub-trench 238 is removed to expose the sidewall of the active pillar 210 parallel to the X direction, and a portion of the third dielectric layer 240 in the fourth sub-trench 238 is removed to expose the sidewall of the active pillar 210 parallel to the X direction and a sidewall of the second isolation layer 242 of the device region 202 parallel to the X direction.
  • the active pillar extends along the Z direction, and the active pillar may have two side walls parallel to the X direction and two side walls parallel to the Y direction.
  • the four side walls of the active pillar may be exposed by removing the first dielectric layer, the second dielectric layer, and the third dielectric layer.
  • the substrate surface may also be exposed, that is, the top surface of the active pillar may be exposed.
  • the height h0 of the exposed sidewall of the active column along the Z direction is less than the height h1 of the first groove along the Z direction, and the height h0 of the exposed sidewall of the active column along the Z direction is less than the height h2 of the second groove along the Z direction.
  • the part of the sidewall of the active column parallel to the Y direction is still covered by the first dielectric layer, and the part of the sidewall of the active column parallel to the X direction is still covered by the third dielectric layer.
  • the height of the part of the active column whose sidewall is covered by the first dielectric layer along the Z direction is (h1-h0); as shown in the schematic cross-sectional structure diagram along the a-a direction in FIG5G, the height of the part of the active column whose sidewall is covered by the third dielectric layer along the Z direction is (h2-h0).
  • the two side walls of the exposed first isolation layer are parallel to the Y direction, and the two side walls of the unexposed first isolation layer are parallel to the Y direction and are in direct contact with the first dielectric layer and the second dielectric layer respectively.
  • the surfaces of the first dielectric layer and the second dielectric layer in the second sub-groove are substantially flush, that is, the heights of the two side walls of the exposed first isolation layer along the Z direction are substantially the same.
  • the height d1 of the side wall of the exposed first isolation layer along the Z direction is less than the height h1 of the second sub-groove along the Z direction. More specifically, the height d1 of the side wall of the exposed first isolation layer along the Z direction is substantially the same as the height h0 of the side wall of the exposed active column along the Z direction.
  • substantially the same means that the difference between the height of the exposed sidewall of the first isolation layer along the Z direction and the height of the exposed sidewall of the active pillar along the Z direction is less than a preset value, that is, the difference between the height of the exposed sidewall of the first isolation layer along the Z direction and the height of the exposed sidewall of the active pillar along the Z direction meets the process error requirement range.
  • the difference between the height of the exposed sidewall of the first isolation layer along the Z direction and the height of the exposed sidewall of the active pillar along the Z direction is 0.
  • the manufacturing method further includes:
  • a portion of the fourth dielectric layer 244 in the fourth sub-trench 238 is removed; wherein the surface of the fourth dielectric layer 244 in the fourth sub-trench 238 is higher than the surface of the third dielectric layer 240 .
  • the third isolation layer 252 covering the peripheral area 204 is also removed, so as to expose the fourth dielectric layer 244 in the fourth sub-groove 238 and the second dielectric layer 224 in the third groove 218, respectively; a portion of the fourth dielectric layer 244 in the fourth sub-groove 238 is removed to expose the other side wall of the second isolation layer 242 in the device area 202 parallel to the X direction; and a portion of the second dielectric layer 224, a portion of the third dielectric layer 240 and a portion of the fourth dielectric layer 244 in the peripheral area 204 are removed to expose the surface of the substrate 200 and the two side walls of the second isolation layer 242 in the peripheral area 204 parallel to the Y direction.
  • the exposed second isolation layer is parallel to the two side walls of the X direction
  • the unexposed second isolation layer is parallel to the two side walls of the X direction and directly contacts the third dielectric layer and the fourth dielectric layer respectively.
  • the height of the side wall of the exposed second isolation layer along the Z direction is less than the height h2 of the fourth sub-groove along the Z direction.
  • the surface of the fourth dielectric layer in the fourth sub-groove is higher than the surface of the third dielectric layer, that is, the heights of the two side walls of the exposed second isolation layer along the Z direction are different.
  • the height d2 of the side wall of the exposed second isolation layer close to the third dielectric layer along the Z direction is greater than the height d3 of the side wall of the exposed second isolation layer close to the fourth dielectric layer along the Z direction.
  • the surfaces of the first dielectric layer, the second dielectric layer and the third dielectric layer in the second sub-groove are substantially flush, and the surfaces of the first dielectric layer, the second dielectric layer and the third dielectric layer in the fourth sub-groove are lower than the surface of the fourth dielectric layer in the fourth sub-groove.
  • the surface of the fourth dielectric layer in the fourth sub-groove is substantially flush with the top surface of the active pillar.
  • the exposed second isolation layer has two side walls parallel to the Y direction
  • the unexposed second isolation layer has two side walls parallel to the Y direction that are in direct contact with the third dielectric layer and the fourth dielectric layer, respectively.
  • the surfaces of the third dielectric layer and the fourth dielectric layer in the second trench in the third isolation structure extending to the peripheral region are substantially flush, that is, the heights d4 of the two side walls of the exposed second isolation layer along the Z direction are substantially the same.
  • the manufacturing method while removing the portion of the first isolation layer 222 exposed in the second sub-trench 216, the manufacturing method further includes:
  • the portion of the second isolation layer 242 exposed in the fourth sub-trench 238 is removed.
  • the portion of the first isolation layer 222 exposed in the second sub-trench 216 is removed, the portion of the second isolation layer 242 exposed in the fourth sub-trench 238 is removed, and the portion of the second isolation layer 242 exposed in the third trench 218 is removed.
  • the surfaces of the first dielectric layer 220, the first isolation layer 222 and the second dielectric layer 224 in the groove 216 are substantially flush; the remaining second isolation layer 242 in the fourth sub-groove 238 is completely covered by the fourth dielectric layer 244; the surfaces of the third dielectric layer 240, the second isolation layer 242 and the fourth dielectric layer 244 extending from the second groove 234 to the third groove 218 are substantially flush.
  • the process of removing the first isolation layer and the second isolation layer includes dry etching, wet etching, or a combination thereof.
  • the disclosed embodiments do not specifically limit the process of removing the first isolation layer and the second isolation layer.
  • the manufacturing method further includes:
  • a plurality of word line structures 272 extending along the second direction are formed; the word line structures 272 cover the channel regions 266 of the active pillars 210 located in the same row.
  • first sub-groove 214 and the second sub-groove 216 together form the first groove 212
  • third sub-groove 236 and the fourth sub-groove 238 together form the second groove 234
  • a plurality of word line structures 272 extending along the second direction are formed, including:
  • a gate dielectric layer 256 is formed in the first trench 212 and the second trench 234 to at least cover the channel region 266 of the active pillar 210;
  • a gate conductive layer 270 covering at least a portion of the gate dielectric layer 256 is formed in the first trench 212 and the second trench 234; the gate conductive layer 270 encapsulates the channel region 266 of the active pillar 210 located in the same row, and the gate conductive layer 270 in the first sub-trench 214 and the second sub-trench 216 are electrically connected; wherein the gate dielectric layer 256 and the gate conductive layer 270 together form a word line structure 272.
  • a gate dielectric layer 256 is formed in the first trench 212 and the second trench 234 to cover the four exposed sidewalls of the active pillar 210 , and the gate dielectric layer 256 may also cover the top surface of the active pillar 210 .
  • the process of forming the gate dielectric layer includes but is not limited to CVD, PVD and ALD or any combination thereof.
  • the gate dielectric layer can be formed using an in-situ oxidation process, for example, the exposed sidewalls and top surfaces of the active pillars are oxidized to form the gate dielectric layer.
  • the material of the gate dielectric layer includes but is not limited to silicon dioxide.
  • a conductive material layer 258 is formed, and the conductive material layer 258 covers the device region 202 and the peripheral region 204.
  • the surfaces of the first dielectric layer 220, the second dielectric layer 224, and the third dielectric layer 240 are substantially flush, and the surfaces of the first dielectric layer 220, the second dielectric layer 224, and the third dielectric layer 240 are lower than the surface of the fourth dielectric layer 244. Therefore, the conductive material layer 258 can fill the first sub-trench 214, the third sub-trench 236, and the fourth sub-trench 238, but does not fill the second sub-trench 216.
  • the process of forming the conductive material layer includes, but is not limited to, CVD, PVD, and ALD or any combination thereof.
  • the material of the conductive material layer includes but is not limited to titanium nitride or a metal material, such as metal tungsten.
  • a gate conductive layer 270 covering at least a portion of the gate dielectric layer 256 is formed in the first trench 212 and the second trench 234, including:
  • the fourth isolation layer 268 and the conductive material layer 258 in the second trench 234 are sequentially etched to form a word line trench and a gate conductive layer 270; wherein the word line trench extends along the second direction; the gate conductive layer 270 in the second sub-trench 216 is in direct contact with the gate dielectric layer 256, and the gate conductive layer 270 in the fourth sub-trench 238 is in direct contact with the fourth dielectric layer 244;
  • An isolation material is filled in the word line trench to form a word line isolation structure 274 .
  • an insulating layer 260 is formed, and the insulating layer 260 covers the device region 202 and the peripheral region 204.
  • the conductive material layer 258 fills the first sub-trench 214, the third sub-trench 236, and the fourth sub-trench 238, but does not fill the second sub-trench 216. Therefore, the insulating layer 260 may fill the second sub-trench 216.
  • the process of forming the insulating layer includes, but is not limited to, ALD.
  • the material of the insulating layer includes, but is not limited to, silicon dioxide.
  • the insulating layer 260 may be planarized to expose the conductive material layer 258 .
  • the planarization process may include, but is not limited to, CMP.
  • a portion of the conductive material layer 258 is etched away to expose the second end 264 of the active pillar, and the remaining conductive material layer 258 covers the channel region 266 of the active pillar.
  • the gate dielectric layer 256 located on the top surface of the active pillar 210 can also be removed, and only the gate dielectric layer 256 covering the sidewall of the active pillar 210 is retained, that is, the gate dielectric layer 256 can cover the channel region 266 and the second end 264 of the active pillar 210.
  • the surfaces of the remaining conductive material layers in the first sub-groove and the second sub-groove are substantially flush, and part of the remaining conductive material layer in the second sub-groove is covered with an insulating layer; the surfaces of the remaining conductive material layers in the third sub-groove and the fourth sub-groove are substantially flush.
  • a fourth isolation layer 268 is formed in the first groove 212 and the second groove 234, and the fourth isolation layer 268 covers the surface of the remaining conductive material layer 258 located in the first sub-groove 214, the second sub-groove 216, the third sub-groove 236 and the fourth sub-groove 238; wherein the fourth isolation layer 268 fills the first sub-groove 214, the second sub-groove 216, the third sub-groove 236 and the fourth sub-groove 238.
  • a fourth isolation material layer is formed in the first trench and the second trench, and the fourth isolation material layer may cover the top surface of the active pillar; the fourth isolation material layer is planarized or etched back to remove a portion of the fourth isolation material layer to expose the top surface of the active pillar, so that the remaining surface of the fourth isolation material layer is basically flush with the top surface of the active pillar, and the remaining fourth isolation material layer is used as the fourth isolation layer.
  • the process of forming the fourth isolation layer includes, but is not limited to, CVD, PVD, and ALD or any combination thereof.
  • the material of the fourth isolation layer includes but is not limited to silicon nitride.
  • the fourth isolation layer 268 and the remaining conductive material layer 258 in the second trench 234 may be etched in sequence to form a word line isolation groove and a gate conductive layer 270 ; wherein the word line isolation groove extends along the X direction; and isolation material may be filled in the word line isolation groove to form a word line isolation structure 274 .
  • the purpose of forming the word line isolation structure is to isolate different word line structures.
  • the gate conductive layer of the word line structure may be a composite conductive layer, for example, the gate conductive layer may include titanium nitride and metal tungsten.
  • the embodiment of the present disclosure has no special limitation on the number of layers and materials of the gate conductive layer.
  • the word line structure extending along the X direction includes a gate dielectric layer and a gate conductive layer, the gate dielectric layer covers the channel region of the active pillars located in the same row, and the gate conductive layer covers the gate dielectric layer of the channel region of the active pillars located in the same row; wherein the gate conductive layer and the gate dielectric layer in the second sub-groove are in direct contact, that is, the gate conductive layer in the second sub-groove is not isolated by the first isolation layer; thus, the gate conductive layer in the first sub-groove and the gate conductive layer in the second sub-groove are electrically connected.
  • the word line structure in the first sub-region can be electrically connected to the end of the word line structure in the second sub-region, and there is no risk of disconnection of the word line structure.
  • different word line structures are isolated by the word line isolation structure, and the gate conductive layer in the fourth sub-groove is in direct contact with the fourth dielectric layer, that is, the gate conductive layer in the fourth sub-groove is not in contact with the second isolation layer; in this way, the second isolation layer in the fourth sub-groove is buried under the fourth dielectric layer, which can prevent the second isolation layer exposed in the fourth sub-groove from contaminating the subsequently formed bit line structure.
  • the manufacturing method further includes:
  • bit line structures 276 extending along a first direction are formed; the bit line structures 276 sequentially connect the first ends 262 of the active pillars 210 located in the same column;
  • a plurality of storage capacitors are formed; a first electrode of the storage capacitor is connected to the second end 264 of the active pillar, and a second electrode of the storage capacitor is connected to the common end.
  • a bit line structure extending along the Y direction can also be formed, which connects the first ends of the active pillars in the same column in sequence; the first electrode of the storage capacitor is connected to the second end of the active pillar, and the second electrode of the storage capacitor is connected to the common end.
  • the first end of the active column may be, for example, a source, and the second end of the active column may be, for example, a drain; or, the first end of the active column may be, for example, a drain, and the second end of the active column may be, for example, a source.
  • part of the first dielectric layer in the first sub-groove and part of the first dielectric layer and the second dielectric layer in the second sub-groove are removed to expose at least part of the sidewall of the active pillar and part of the sidewall of the first isolation layer respectively; part of the first isolation layer exposed in the second sub-groove is removed; in this way, in the process of forming the word line structure, the word line structures in the first sub-groove and the second sub-groove can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected. Furthermore, while removing the part of the first isolation layer exposed in the second sub-groove, the part of the second isolation layer exposed in the fourth sub-groove can also be removed to prevent the exposed second isolation layer from contaminating the subsequently formed bit line structure.
  • FIG. 6 is a schematic diagram of a top view of a semiconductor device provided in an embodiment of the present disclosure
  • FIG. 7 is a schematic diagram of a cross-sectional view of a semiconductor device provided in an embodiment of the present disclosure.
  • an embodiment of the present disclosure provides a semiconductor device, the semiconductor device comprising:
  • Substrate 200 the substrate 200 includes a device region 202 and a peripheral region 204, the device region 202 includes a first sub-region 206 and a second sub-region 208, and the second sub-region 208 is located between the first sub-region 206 and the peripheral region 204;
  • the substrate 200 of the device region 202 includes a plurality of first trenches 212 extending along a first direction and a plurality of second trenches 234 extending along a second direction, wherein the first trenches 212 and the second trenches 234 together isolate a plurality of active pillars 210;
  • the active pillars 210 include a first end 262 and a second end 264 disposed opposite to each other along a third direction and a channel region 266 located between the first end 262 and the second end 264;
  • the first trenches 212 include a first sub-trench 214 located in the first sub-region 206 and a second sub-trench 216 located in the second sub-region 208; wherein the first direction
  • the first direction and the second direction are both parallel to the substrate 200 and the first direction and the second direction intersect, and the third direction is perpendicular to the substrate 200;
  • a plurality of word line structures 272 extending along the second direction are located in the first trench 212 and the second trench 234 ; the word line structures 272 cover the channel regions 266 of the active pillars located in the same row; wherein the word line structures 272 in the first sub-trench 214 and the word line structures 272 in the second sub-trench 216 are electrically connected.
  • the dashed box in the cross-sectional structural diagram along the c-c direction in Figure 7 illustrates the active pillar 210, and the active pillar 210 includes a first end 262 and a second end 264 arranged opposite to each other along the Z direction and a channel region 266 located between the first end 262 and the second end 264.
  • the word line structures in the first sub-trench and the second sub-trench can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected.
  • the semiconductor device further includes:
  • the fourth isolation layer 268 extending along the second direction is located in the first trench 212 and the second trench 234 ; the fourth isolation layer 268 covers the second ends 264 of the active pillars 210 located in the same row;
  • a plurality of word line isolation structures 274 extending along the second direction are located between adjacent word line structures 272 and adjacent fourth isolation layers 268 .
  • the word line isolation structure 274 extends along the X direction, a portion of the word line isolation structure 274 is located between adjacent word line structures 272 , and a portion of the word line isolation structure 274 is located between adjacent fourth isolation layers 268 .
  • the word line structure 272 includes: a gate dielectric layer 256 at least covering the channel region 266 of the active pillar 210;
  • the gate conductive layer 270 is located on the surface of the gate dielectric layer 256 and covers the channel region 266 of the active pillars 210 located in the same row; wherein the gate conductive layer 270 in the first sub-groove 214 and the second sub-groove 216 are electrically connected, and the gate conductive layer 270 in the second sub-groove 216 is in direct contact with the gate dielectric layer 256.
  • the semiconductor device further includes:
  • a first dielectric layer 220 located in the first sub-trench 214 and the second sub-trench 216 , wherein the first dielectric layer 220 is located between the first ends 262 of adjacent active pillars 210 and covers the sidewall and bottom of the second sub-trench 216 ;
  • the second dielectric layer 224 is located in the second sub-trench 216 , and the second dielectric layer 224 is located below the gate conductive layer 270 .
  • the surfaces of the first dielectric layer 220, the first isolation layer 222 and the second dielectric layer 224 in the second sub-groove 216 are substantially flush; wherein the first dielectric layer 220 covers the bottom and part of the sidewall of the second sub-groove 216, the first isolation layer 222 covers the first dielectric layer 220, and the second dielectric layer 224 covers the first isolation layer 222; the gate conductive layer 270 in the second sub-groove 216 is located above the first dielectric layer 220, the first isolation layer 222 and the second dielectric layer 224; and the fourth isolation layer 268 and the insulating layer 260 are also located in the second sub-groove 216, and the fourth isolation layer 268 and the insulating layer 260 are located above the gate conductive layer 270.
  • the top surface of the second dielectric layer 224 is in direct contact with the gate conductive layer 270.
  • the orthographic projections of the first dielectric layer 220, the first isolation layer 222, and the second dielectric layer 224 in the second sub-trench 216 on the XY plane are within the orthographic projection range of the gate conductive layer in the second sub-trench 216 on the XY plane.
  • the second trench 234 includes a third sub-trench 236 located in the first sub-region 206 and a fourth sub-trench 238 located in the second sub-region 208; the semiconductor device further includes:
  • a third dielectric layer 240 located in the third sub-trench 236 and the fourth sub-trench 238 , wherein the third dielectric layer 240 is located between the first ends 262 of adjacent active pillars 210 and covers the sidewall and bottom of the fourth sub-trench 238 ;
  • the fourth dielectric layer 244 is located in the fourth sub-trench 238 , and the sidewall of the fourth dielectric layer 244 is in direct contact with the gate conductive layer 270 and the fourth isolation layer 268 .
  • the third dielectric layer 240 covers the bottom and part of the sidewall of the fourth sub-groove 238, the second isolation layer 242 covers part of the third dielectric layer 240, and the fourth dielectric layer 244 covers the second isolation layer 242, that is, the orthographic projection of the second isolation layer 242 on the XY plane is within the orthographic projection range of the fourth dielectric layer 244 on the XY plane.
  • the gate conductive layer 270 is located above the third dielectric layer 240, and the fourth isolation layer 268 is located above the gate conductive layer 270; wherein the surfaces of the fourth isolation layer 268 and the fourth dielectric layer 244 are substantially flush.
  • the sidewall of the fourth dielectric layer 244 parallel to the X direction directly contacts the gate conductive layer 270.
  • the orthographic projections of the second isolation layer 242 and the fourth dielectric layer 244 in the fourth sub-trench 238 on the XY plane are outside the orthographic projection range of the gate conductive layer in the second sub-trench 216 on the XY plane.
  • the semiconductor device further includes:
  • the first portion 278 (as shown in the dashed box in the cross-sectional structural diagram along the e-e direction in FIG7 ) includes a first dielectric layer 220, a first isolation layer 222, and a second dielectric layer 224 covering the first isolation layer 222, which sequentially cover the sidewalls and the bottom of the third trench 218;
  • the second portion 280 (as shown in the dashed box in the cross-sectional structure schematic diagram in the ee direction in FIG. 7 ) includes the second grooves sequentially covered
  • the third dielectric layer 240 and the second isolation layer 242 234 extend to at least a portion of the sidewall and the bottom of the third isolation structure 232
  • the fourth dielectric layer 244 fills the second trench 234 and extends to a portion of the third isolation structure 232 .
  • the semiconductor device further includes:
  • a plurality of bit line structures 276 are extended along a first direction, and the bit line structures 276 sequentially connect the first ends 262 of the active pillars 210 located in the same column;
  • a plurality of storage capacitors a first electrode of the storage capacitor is connected to the second end 264 of the active pillar 210, and a second electrode of the storage capacitor is connected to a common end.
  • the disclosed embodiment provides a semiconductor device and a method for manufacturing the same.
  • a portion of the first dielectric layer in the first sub-groove and a portion of the first dielectric layer and the second dielectric layer in the second sub-groove are removed to expose at least a portion of the sidewall of the active pillar and at least a portion of the sidewall of the first isolation layer, respectively; the portion of the first isolation layer exposed in the second sub-groove is removed; thus, in the subsequent process of forming a word line structure, the word line structures in the first sub-groove and the second sub-groove can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected.
  • part of the first dielectric layer in the first sub-groove and part of the first dielectric layer and the second dielectric layer in the second sub-groove are removed to expose at least part of the side wall of the active pillar and at least part of the side wall of the first isolation layer, respectively; the part of the first isolation layer exposed in the second sub-groove is removed; in this way, in the subsequent process of forming the word line structure, the word line structures in the first sub-groove and the second sub-groove can be electrically connected, that is, the word line structure located in the first sub-region for connecting the gates of the storage cells in the same row and the end of the word line structure located in the second sub-region can be electrically connected.

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Abstract

本公开提供一种半导体器件及其制造方法。该制造方法包括：提供衬底，衬底的器件区包括第一子区和第二子区；位于第一子区的第一子隔离结构包括填满第一子沟槽的第一介质层，位于第二子区的第二子隔离结构包括依次覆盖第二子沟槽侧壁和底部的第一介质层、第一隔离层和填满第二子沟槽的第二介质层；去除第二子沟槽内的部分第一介质层和第二介质层，以暴露出第一隔离层的至少部分侧壁；去除第二子沟槽内暴露出的部分第一隔离层。

Description

一种半导体器件及其制造方法
相关申请的交叉引用
本公开基于申请号为202310713541.8、申请日为2023年06月14日、发明名称为“一种半导体器件及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本公开作为参考。
技术领域
本公开实施例涉及半导体技术领域，尤其涉及一种半导体器件及其制造方法。
背景技术
动态随机存取存储器(Dynamic Random Access Memory，DRAM)的存储单元包括一个晶体管和一个电容(1 Transistor 1 Capacitor，1T1C)，晶体管的栅极和字线连接，晶体管的源极和位线连接，晶体管的漏极和电容连接。
目前，如何对DRAM进行改进以提升其性能仍存在挑战。
发明内容
有鉴于此，本公开实施例提供一种半导体器件及其制造方法。
为达到上述目的，本公开的技术方案是这样实现的：
第一方面，本公开实施例提供一种半导体器件的制造方法，所述制造方法包括：
提供衬底，所述衬底包括器件区和外围区，所述器件区包括第一子区和第二子区，所述第二子区位于所述第一子区和所述外围区之间；所述器件区的衬底包括沿第一方向延伸的多个第一隔离结构和沿第二方向延伸的多个第二隔离结构，所述第一隔离结构和所述第二隔离结构共同隔离出多个有源柱；所述第一隔离结构包括位于所述第一子区的第一子隔离结构和位于所述第二子区的第二子隔离结构，所述第一子隔离结构包括填满第一子沟槽的第一介质层，所述第二子隔离结构包括依次覆盖第二子沟槽侧壁和底部的第一介质层、第一隔离层和填满第二子沟槽的第二介质层；其中，所述第一方向和所述第二方向均平行于所述衬底且所述第一方向和所述第二方向相交；
去除所述第一子沟槽内的部分第一介质层和所述第二子沟槽内的部分第一介质层和第二介质层，以分别暴露出所述有源柱的至少部分侧壁和所述第一隔离层的至少部分侧壁；
去除所述第二子沟槽内暴露出的部分第一隔离层。
在一些实施例中，所述第二隔离结构包括位于所述第一子区的第三子隔离结构和位于所述第二子区的第四子隔离结构，所述第三子隔离结构包括填满第三子沟槽的第三介质层，所述第四子隔离结构包括依次覆盖第四子沟槽侧壁和底部的第三介质层、第二隔离层和填满第四子沟槽的第四介质层；
所述去除所述第一子沟槽内的部分第一介质层和所述第二子沟槽内的部分第一介质层和第二介质层之前，所述制造方法还包括：
形成第三隔离层，所述第三隔离层覆盖所述器件区的第一隔离结构和第二隔离结构；
去除部分所述第三隔离层，以保留覆盖所述第四子沟槽内第四介质层的第三隔离层。
在一些实施例中，所述去除所述第一子沟槽内的部分第一介质层和所述第二子沟槽内的部分第一介质层和第二介质层的同时，所述制造方法还包括：
去除所述第三子沟槽内的部分第三介质层和所述第四子沟槽内的部分第三介质层，以暴露出所述有源柱的至少部分侧壁和所述第二隔离层的至少部分侧壁。
在一些实施例中，所述去除所述第三子沟槽内的部分第三介质层和所述第四子沟槽内的部分第三介质层之后，所述制造方法还包括：
去除覆盖所述第四子沟槽内第四介质层的第三隔离层；
去除所述第四子沟槽内的部分第四介质层；其中，所述第四子沟槽内的第四介质层的表面高于所述第三介质层的表面。
在一些实施例中，所述去除所述第二子沟槽内暴露出的部分第一隔离层的同时，所述制造方法还包括：
去除所述第四子沟槽内暴露出的部分第二隔离层。
在一些实施例中，所述有源柱包括沿第三方向相对设置的第一端和第二端以及位于所述第一端和所述第二端之间的沟道区；所述第三方向垂直于所述衬底；
所述去除所述第二子沟槽内暴露出的部分第一隔离层之后，所述制造方法还包括：
形成沿所述第二方向延伸的多个字线结构；所述字线结构包覆位于同一行的所述有源柱的沟道区。
在一些实施例中，所述第一子沟槽和所述第二子沟槽共同形成第一沟槽，所述第三子沟槽和所述第四子沟槽共同形成第二沟槽；
所述形成沿所述第二方向延伸的多个字线结构，包括：
在所述第一沟槽和所述第二沟槽内形成至少包覆所述有源柱的沟道区的栅介质层；
在所述第一沟槽和所述第二沟槽内形成至少覆盖部分所述栅介质层的栅导电层；所述栅导电层包覆位于同一行的所述有源柱的沟道区，所述第一子沟槽和所述第二子沟槽内的栅导电层电连接；其中，所述栅介质层和所述栅导电层共同形成字线结构。
在一些实施例中，所述在所述第一沟槽和所述第二沟槽内形成至少覆盖部分所述栅介质层的栅导电层，包括：
形成导电材料层，所述导电材料层填满所述第一沟槽和所述第二沟槽；
去除覆盖所述有源柱的第二端的导电材料层；
形成第四隔离层，所述第四隔离层填满所述第一沟槽和所述第二沟槽；
依次对所述第二沟槽内的第四隔离层和导电材料层进行刻蚀，以形成字线隔槽和栅导电层；其中，所述字线隔槽沿所述第二方向延伸；所述第二子沟槽内的栅导电层和栅介质层直接接触，所述第四子沟槽内的栅导电层和第四介质层直接接触；
在所述字线隔槽中填充隔离材料，以形成字线隔离结构。
在一些实施例中，所述去除所述第二子沟槽内暴露出的部分第一隔离层之后，所述制造方法还包括：
形成沿所述第一方向延伸的多个位线结构；所述位线结构将位于同一列的所述有源柱的第一端依次连接；
形成多个存储电容；所述存储电容的第一电极和所述有源柱的第二端连接，所述存储电容的第二电极和公共端连接。
在一些实施例中，所述提供衬底，包括：
刻蚀所述衬底，以在所述器件区内形成第一沟槽且在所述外围区内形成第三沟槽；所述第一沟槽和所述第三沟槽均沿所述第一方向延伸；所述第一沟槽包括位于所述第一子区的第一子沟槽和位于所述第二子区的第二子沟槽；
形成第一介质层，所述第一介质层覆盖所述第二子沟槽和所述第三沟槽的侧壁和底部，且所述第一介质层填满所述第一子沟槽，以形成第一子隔离结构；
形成第一隔离层，所述第一隔离层覆盖所述第一介质层；
形成第二介质层，所述第二介质层填满所述第二子沟槽和所述第三沟槽，以分别形成第二子隔离结构和第三隔离结构。
在一些实施例中，所述提供衬底，还包括：
刻蚀所述衬底、所述第一介质层和所述第二介质层，以在所述器件区内形成第二沟槽，所述第二沟槽还延伸至所述外围区的第三沟槽内；所述第二沟槽沿所述第二方向延伸；所述第二沟槽包括位于所述第一子区的第三子沟槽和位于所述第二子区的第四子沟槽；
形成第三介质层，所述第三介质层覆盖所述第四子沟槽的侧壁和底部，且所述第三介质层填满所述第三子沟槽，以形成第三子隔离结构；
形成第二隔离层，所述第二隔离层覆盖所述第三介质层；
形成第四介质层，所述第四介质层填满所述第四子沟槽，以形成第四子隔离结构。
第二方面，本公开实施例提供一种半导体器件，所述半导体器件包括：
衬底；所述衬底包括器件区和外围区，所述器件区包括第一子区和第二子区，所述第二子区位于所述第一子区和所述外围区之间；
所述器件区的衬底包括沿第一方向延伸的多个第一沟槽和沿第二方向延伸的多个第二沟槽，所述第一沟槽和所述第二沟槽共同隔离出多个有源柱；所述有源柱包括沿第三方向相对设置的第一端和第二端以及位于所述第一端和所述第二端之间的沟道区；所述第一沟槽包括位于所述第一子区的第一子沟槽和位于所述第二子区的第二子沟槽；其中，所述第一方向和所述第二方向均平行于所述衬底且所述第一方向和所述第二方向相交，所述第三方向垂直于所述衬底；
沿所述第二方向延伸的多个字线结构，位于所述第一沟槽和所述第二沟槽内；所述字线结构包覆位于同一行的所述有源柱的沟道区；其中，所述第一子沟槽内的字线结构和所述第二子沟槽内的字线结构电连接。
在一些实施例中，所述半导体器件还包括：
沿所述第二方向延伸的第四隔离层，位于所述第一沟槽和所述第二沟槽内；所述第四隔离层包覆位于同一行的所述有源柱的第二端；
沿所述第二方向延伸的多个字线隔离结构，位于相邻所述字线结构和相邻所述第四隔离层之间。
在一些实施例中，所述字线结构包括：
栅介质层，至少包覆所述有源柱的沟道区；
栅导电层，位于所述栅介质层表面，且包覆位于同一行的所述有源柱的沟道区；其中，所述第一子沟槽和所述第二子沟槽内的栅导电层电连接，所述第二子沟槽内的栅导电层和栅介质层直接接触。
在一些实施例中，所述半导体器件还包括：
位于所述第一子沟槽和第二子沟槽内的第一介质层，所述第一介质层位于相邻所述有源柱的第一端之间且第一介质层覆盖第二子沟槽侧壁和底部；
覆盖所述第二子沟槽侧壁和底部的第一介质层的第一隔离层；
位于所述第二子沟槽内的第二介质层，且所述第二介质层位于所述栅导电层下方。
在一些实施例中，所述第二沟槽包括位于所述第一子区的第三子沟槽和位于所述第二子区的第四子沟槽；所述半导体器件还包括：
位于所述第三子沟槽和第四子沟槽内的第三介质层，所述第三介质层位于相邻所述有源柱的第一端之间且第三介质层覆盖第四子沟槽侧壁和底部；
覆盖所述第四子沟槽底部的第三介质层的第二隔离层；
位于所述第四子沟槽内的第四介质层，且所述第四介质层侧壁和所述栅导电层、第四隔离层直接接触。
在一些实施例中，所述半导体器件还包括：
位于所述外围区且沿所述第一方向延伸的第三隔离结构，所述第三隔离结构包括第一部分和第二部分，所述第二沟槽延伸至所述第三隔离结构内的部分为第二部分；
所述第一部分包括依次覆盖第三沟槽侧壁和底部的第一介质层、第一隔离层和覆盖所述第一隔离层的第二介质层；
所述第二部分包括依次覆盖所述第二沟槽延伸至所述第三隔离结构至少部分侧壁和底部的第三介质层和第二隔离层和填满所述第二沟槽延伸至所述第三隔离结构部分的第四介质层。
在一些实施例中，所述半导体器件还包括：
沿所述第一方向延伸多个位线结构，所述位线结构将位于同一列的所述有源柱的第一端依次连接；
多个存储电容；所述存储电容的第一电极和所述有源柱的第二端连接，所述存储电容的第二电极和公共端连接。
本公开实施例提供一种半导体器件及其制造方法。本公开实施例中，去除第一子沟槽内的部分第一介质层和第二子沟槽内的部分第一介质层和第二介质层，以分别暴露出有源柱的至少部分侧壁和第一隔离层的至少部分侧壁；去除第二子沟槽内暴露出的部分第一隔离层；如此，在后续形成字线结构的过程中，第一子沟槽和第二子沟槽内的字线结构可以实现电连接，即，位于第一子区内用于连接同一行的存储单元栅极的字线结构和位于第二子区内的字线结构末端可以实现电连接。
附图说明
图1为一些示例提供的半导体器件的俯视结构示意图；
图2为一些示例提供的半导体器件的剖视结构示意图；
图3为本公开实施例提供的半导体器件的制造方法的流程示意图；
图4为本公开实施例提供的半导体器件的俯视结构示意图；
图5A至图5O为本公开实施例提供的半导体器件的制造过程中的剖视结构示意图；
图6为本公开实施例提供的半导体器件的俯视结构示意图；
图7为本公开实施例提供的半导体器件的剖视结构示意图。
具体实施方式
下面将结合本公开实施方式及附图，对本公开实施方式中的技术方案进行清楚、完整地描述，显然，所描述的实施方式仅仅是本公开的一部分实施方式，而不是全部的实施方式。基于本公开中的实施方式，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施方式，都属于本公开保护的范围。
在下文的描述中，给出了大量具体的细节以便提供对本公开更为彻底的理解。然而，对于本领域技术人员而言显而易见的是，本公开可以无需一个或多个这些细节而得以实施。在其他的例子中，为了避免与本公开发生混淆，对于本领域公知的一些技术特征未进行描述；即，这里不描述实际实施例的全部特征，不详细描述公知的功能和结构。
在附图中，为了清楚，层、区、元件的尺寸以及其相对尺寸可能被夸大。自始至终相同附图标记表示相同的元件。
应当明白，当元件或层被称为“在……上”、“与……相邻”、“连接到”或“耦合到”其它元件或层时，其可以直接地在其它元件或层上、与之相邻、连接或耦合到其它元件或层，或者可以存在居间的元件或层。相反，当元件被称为“直接在……上”、“与……直接相邻”、“直接连接到”或“直接耦合到”其它元件或层时，则不存在居间的元件或层。应当明白，尽管可使用术语第一、第二、第三等描述各种元件、部件、区、层和/或部分，这些元件、部件、区、层和/或部分不应当被这些术语限制。这些术语仅仅用来区分一个元件、部件、区、层或部分与另一个元件、部件、区、层或部分。因此，在不脱离本公开教导之下，下面讨论的第一元件、部件、区、层或部分可表示为第二元件、部件、区、层或部分。而当讨论第二元件、部件、区、层或部分时，并不表明本公开必然存在第一元件、部件、区、层或部分。
空间关系术语例如“在……下”、“在……下面”、“下面的”、“在……之下”、“在……之上”、“上面的”等，在这里可为了方便描述而被使用从而描述图中所示的一个元件或特征与其它元件或特征的关系。应当明白，除了图中所示的取向以外，空间关系术语意图还包括使用和操作中的器件的不同取向。例如，如果附图中的器件翻转，然后，描述为“在其它元件下面”或“在其之下”或“在其下”元件或特征将取向为在其它元件或特征“上”。因此，示例性术语“在……下面”和“在……下”可包括上和下两个取向。器件可以另外地取向(旋转90度或其它取向)并且在此使用的空间描述语相应地被解释。
在此使用的术语的目的仅在于描述具体实施例并且不作为本公开的限制。在此使用时，单数形式的“一”、“一个”和“所述/该”也意图包括复数形式，除非上下文清楚指出另外的方式。还应明白术语“组成”和/或“包括”，当在该说明书中使用时，确定所述特征、整数、步骤、操作、元件和/或部件的存在，但不排除一个或更多其它的特征、整数、步骤、操作、元件、部件和/或组的存在或添加。在此使用时，术语“和/或”包括相关所列项目的任何及所有组合。
为了彻底理解本公开，将在下列的描述中提出详细的步骤以及详细的结构，以便阐释本公开的技术方案。本公开的较佳实施例详细描述如下，然而除了这些详细描述外，本公开还可以具有其他实施方式。
在介绍本公开实施例之前，先定义本公开实施例可能用到的描述结构的三个方向，三个方向可以包括X方向、Y方向和Z方向，X方向和Y方向均平行于衬底且X方向和Y方向相交，Z方向垂直于衬底。本公开实施例中，存储单元可以沿X方向和Y方向呈阵列排布，X方向也可以称为行方向，Y方向也可以称为列方向。
需要说明的是，可以定义第一方向、第二方向和第三方向。本公开实施例中，定义第一方向为Y方向，定义第二方向为X方向，定义第三方向为Z方向。
参考图1和图2，图1为一些示例提供的半导体器件的俯视结构示意图，图2为一些示例提供的半导体器件的剖视结构示意图。如图1和图2所示，衬底100包括器件区102和外围区104，外围区104可以围绕器件区102设置；其中，器件区102内设置有存储单元阵列，存储单元阵列包括沿X方向和Y方向呈阵列排布的多个存储单元；外围区104内设置有外围电路，外围电路可以用于对存储单元阵列进行控制。器件区102包括第一子区106(如图1中点划线方框所示)和第二子区108(如图1中虚线方框所示)，第二子区108位于第一子区106和外围区104之间。更具体而言，第一子区106内设置有沿X方向和Y方向呈阵列排布的多个有源柱110，有源柱包括沿Z方向相对设置的第一端和第二端以及位于第一端和第二端之间的沟道区，晶体管的漏极可以例如为有源柱的第一端，晶体管的源极可以例如为有源柱的第二端，晶体管的栅极可以围绕有源柱的沟道区。位于同一列(即，沿Y方向排列)的有源柱的第一端可以连接至同一位线(Bit Line，BL)，位线可以由第一子区沿Y方向延伸至第二子区；位于同一行(即，沿X方向排列)的有源柱的沟道区外侧的栅极可以连接至同一字线(Word Line，WL)，字线可以由第一子区沿X方向延伸至第二子区。换言之，第二子区108内未设置存储单元，第二子区108包括位线末端(Bit Line End)和字线末端(Word Line End)。
图2示意出沿图1中a-a方向、b-b方向、c-c方向、d-d方向和e-e方向的剖视结构示意图，其中，沿a-a方向和b-b方向的剖视结构示意图均示意出器件区的第一子区和第二子区沿Y方向的结构示意图；沿c-c方向和d-d方向的剖视结构示意图均示意出器件区的第一子区和第二子区沿X方向的结构示意图；沿e-e方向的剖视结构示意图示意出外围区沿X方向的结构示意图。图1和图2示意出垂直沟道晶体管(Vertical Channel Transistor，VGT)，且该垂直沟道晶体管为全环绕栅结构(Gate-All-Around，GAA)。
如图2中c-c方向剖视结构示意图所示，器件区102的衬底100包括沿Y方向延伸的第一沟槽112，第一沟槽112包括位于第一子区106的第一子沟槽114和位于第二子区108的第二子沟槽116；第一子沟槽114内的字线结构和第二子沟槽116内的字线结构之间可能被第一氮化硅柱124(如图2中虚线圆框所示)隔离开，也就是说，位于第一子区106内用于连接同一行的存储单元栅极的字线结构和位于第二子区108内的字线结构末端可能无法实现电连接，存在字线结构末端高电阻(WL End High Resistance)以及字线结构断开的风险(Potential Risk of WL Open)。如图2中a-a方向剖视结构示意图所示，器件区102的衬底100还包括沿X方向延伸的第二沟槽118，第二沟槽118包括位于第一子区106的第三子沟槽120和位于第二子区108的第四子沟槽122；第四子沟槽122内的第二氮化硅柱126(如图2中虚线圆框所示)可能对后续工艺形成的位线结构造成污染(SIN Pollution Risk)。
有鉴于此，本公开实施例提供一种半导体器件及其制造方法。
参考图3，图3为本公开实施例提供的半导体器件的制造方法的流程示意图。如图3所示，本公开实施例提供一种半导体器件的制造方法，该制造方法包括：
步骤S301：提供衬底，衬底包括器件区和外围区，器件区包括第一子区和第二子区，第二子区位于第一子区和外围区之间；器件区的衬底包括沿第一方向延伸的多个第一隔离结构和沿第二方向延伸的多个第二隔离结构，第一隔离结构和第二隔离结构共同隔离出多个有源柱；第一隔离结构包括位于第一子区的第一子隔离结构和位于第二子区的第二子隔离结构，第一子隔离结构包括填满第一子沟槽的第一介质层，第二子隔离结构包括依次覆盖第二子沟槽侧壁和底部的第一介质层、第一隔离层和填满第二子沟槽的第二介质层；其中，第一方向和第二方向均平行于衬底且第一方向和第二方向相交；
步骤S302：去除第一子沟槽内的部分第一介质层和第二子沟槽内的部分第一介质层和第二介质层，以分别暴露出有源柱的至少部分侧壁和第一隔离层的至少部分侧壁；
步骤S303：去除第二子沟槽内暴露出的部分第一隔离层。
本公开实施例中，去除第一子沟槽内的部分第一介质层和第二子沟槽内的部分第一介质层和第二介质层，以分别暴露出有源柱的至少部分侧壁和第一隔离层的至少部分侧壁；去除第二子沟槽内暴露出的部分第一隔离层；如此，在后续形成字线结构的过程中，第一子沟槽和第二子沟槽内的字线结构可以实现电连接，即，位于第一子区内用于连接同一行的存储单元栅极的字线结构和位于第二子区内的字线结构末端可以实现电连接。
参考图4和图5A至图5O，图4为本公开实施例提供的半导体器件的俯视结构示意图，图5A至图5O为本公开实施例提供的半导体器件的制造过程中的剖视结构示意图，详细地说明本公开实施例提供的半导体器件的制造方法。
需要说明的是，图5A至图5O均示意出沿图4中a-a方向、b-b方向、c-c方向、d-d方向和e-e方向的剖视结构示意图，其中，沿a-a方向和b-b方向的剖视结构示意图均示意出器件区202的第一子区206和第二子区208沿Y方向的结构示意图；沿c-c方向和d-d方向的剖视结构示意图均示意出器件区202的第一子区206和第二子区208沿X方向的结构示意图；沿e-e方向的剖视结构示意图示意出外围区204沿X方向的结构示意图。
本公开实施例中，步骤S301包括：
刻蚀衬底200，以在器件区202内形成第一沟槽212且在外围区204内形成第三沟槽218；第一沟槽212和第三沟槽218均沿第一方向延伸；第一沟槽212包括位于第一子区206的第一子沟槽214和位于第二子区208的第二子沟槽216；
形成第一介质层220，第一介质层220覆盖第二子沟槽216和第三沟槽218的侧壁和底部，且第一介质层220填满第一子沟槽214，以形成第一子隔离结构228；
形成第一隔离层222，第一隔离层222覆盖第一介质层220；
形成第二介质层224，第二介质层224填满第二子沟槽216和第三沟槽218，以分别形成第二子隔离结构230和第三隔离结构232。
如图4和图5A所示，衬底200包括器件区(Core)202和外围区(Periphery)204，外围区204可以围绕器件区202设置；其中，器件区202包括第一子区206(如图4中点划线方框所示)和第二子区208(如图4中虚线方框所示)，第二子区208位于第一子区206和外围区204之间。第一子区206包括存储单元阵列，即，沿X方向和Y方向呈阵列排布的多个存储单元；第二子区内未设置存储单元，第二子区208包括位线结构末端和字线结构末端；外围区204包括外围电路。这里，位线结构末端即为位线末端，字线结构末端即为字线末端。
在一些实施例中，衬底可以是半导体衬底；具体包括至少一个单质半导体材料(例如为硅(Si)衬底、锗(Ge)衬底等)、至少一个III-V化合物半导体材料(例如为氮化镓(GaN)衬底、砷化镓(GaAs)衬底、磷化铟(InP)衬底等)、至少一个II-VI化合物半导体材料、至少一个有机半导体材料或者在本领域已知的其他半导体材料，还可以包括其他含半导体材料的衬底，例如绝缘体上硅(SOI)衬底、绝缘体上锗(GeOI)衬底、绝缘层上的多晶半导体层、硅锗衬底等。本公开实施例对衬底的材料并无特殊的限定。
如图5A所示，刻蚀衬底200，以在器件区202内形成第一沟槽212且在外围区204内形成第三沟槽218；其中，第一沟槽212包括位于第一子区206的第一子沟槽214和位于第二子区208的第二子沟槽216；第一子沟槽214、第二子沟槽216和第三沟槽218均沿Y方向延伸。
这里，位于第一子区的第一子沟槽的数量可以例如为多个，第一子沟槽用于将位于不同列的有源柱隔离开；位于第二子区的第二子沟槽的数量可以例如为一个或者两个。在一具体示例中，位于第二子区的第二子沟槽可以在位于第一子区的第一子沟槽和位于外围区的第三沟槽之间，第二子沟槽可以位于第一子区的一侧，或者，第二子沟槽可以位于第一子区的相对设置的两侧。
这里，可以在同一刻蚀工艺中，同时在器件区内形成第一沟槽且在外围区内形成第三沟槽。第一子沟槽、第二子沟槽和第三沟槽沿Z方向上的高度基本相同。第一子沟槽沿X方向上的宽度小于第二子沟槽沿X方向上的宽度，第一子沟槽沿X方向上的宽度小于第三沟槽沿X方向上的宽度。
如图5A所示，在第一子沟槽214、第二子沟槽216和第三沟槽218内形成第一介质层220。这里，由于第一子沟槽214、第二子沟槽216和第三沟槽218的尺寸不同，因此，第一介质层220可以填满第一子沟槽214以形成第一子隔离结构，而第一介质层220仅覆盖第二子沟槽216和第三沟槽218的侧壁和底部。
示例性地，在第一子沟槽内形成第一介质层的过程可以使用如下方法进行，例如，在第一子沟槽内形成第一介质材料层，第一介质材料层覆盖衬底表面；对第一介质材料层进行平坦化处理，去除部分第一介质材料层以暴露出衬底表面，使得剩余的第一介质材料层表面和衬底表面基本齐平，将剩余的第一介质材料层作为第一介质层。又例如，在第一子沟槽内形成第一介质层，第一介质层覆盖衬底表面。如此，可以在后续工艺过程中再去除部分第一介质层以暴露出衬底表面。
在一具体示例中，平坦化处理包括但不限于化学机械研磨(Chemical Mehanical Polishing，CMP)工艺。
需要说明的是，基本齐平指的是衬底表面和第一介质层表面沿Z方向上的高度差小于预设值，即，衬底表面和第一介质层表面沿Z方向上的高度差满足工艺误差要求范围。在一具体示例中，衬底表面和第一介质层表面沿Z方向上的高度差为0。
在一些实施例中，形成第一介质层的工艺包括但不限于化学气相沉积(Chemical Vapor  Deposition，CVD)、物理气相沉积(Physical Vapor Deposition，PVD)以及原子层沉积(Atomic layer deposition，ALD)或其任意组合。
在一些实施例中，第一介质层的材料可以包括但不限于二氧化硅。
如图5A所示，在第二子沟槽216和第三沟槽218内形成第一隔离层222，第一隔离层222覆盖第一介质层220；在第二子沟槽216和第三沟槽218内形成第二介质层224，第二介质层224填满第二子沟槽216和第三沟槽218，以分别形成第二子隔离结构230和第三隔离结构232；其中，第一子隔离结构228和第二子隔离结构230共同形成第一隔离结构226。
在一些实施例中，形成第一隔离层和第二介质层的工艺包括但不限于CVD、PVD以及ALD或其任意组合。
在一些实施例中，第一隔离层的材料可以包括但不限于氮化硅；第二介质层的材料可以包括但不限于二氧化硅。
本公开实施例中，步骤S301还包括：
刻蚀衬底200、第一介质层220和第二介质层224，以在器件区202内形成第二沟槽234，第二沟槽234还延伸至外围区204的第三沟槽218内；第二沟槽234沿第二方向延伸；第二沟槽234包括位于第一子区206的第三子沟槽236和位于第二子区208的第四子沟槽238；
形成第三介质层240，第三介质层240覆盖第四子沟槽238的侧壁和底部，且第三介质层240填满第三子沟槽236，以形成第三子隔离结构248；
形成第二隔离层242，第二隔离层242覆盖第三介质层240；
形成第四介质层244，第四介质层244填满第四子沟槽238，以形成第四子隔离结构250。
如图5A所示，刻蚀衬底200、第一介质层220和第二介质层224，以在器件区202内形成第二沟槽234，第二沟槽234可能延伸至外围区204的第三沟槽218内；其中，第二沟槽234包括位于第一子区206内的第三子沟槽236和位于第二子区208内的第四子沟槽238；第三子沟槽236和第四子沟槽238均沿X方向延伸。
这里，基于第三沟槽已经被填充形成第三隔离结构，第三隔离结构包括依次覆盖第三沟槽的侧壁和底部的第一介质层和第一隔离层以及填满第三沟槽的第二介质层。刻蚀形成第二沟槽的过程中，可能刻蚀去除第三沟槽内的部分第二介质层，即，第二沟槽可能延伸至第三沟槽内。第二沟槽所包括的第三子沟槽和第四子沟槽均可能沿X方向延伸至第三沟槽内。
这里，位于第一子区的第三子沟槽的数量可以例如为多个，第三子沟槽用于将位于不同行的有源柱隔离开；位于第二子区的第四子沟槽的数量可以例如为一个或者两个。在一具体示例中，位于第二子区的第四子沟槽可以在位于第一子区的第三子沟槽和位于外围区的第三沟槽之间，第四子沟槽可以位于第一子区的一侧，或者，第四子沟槽可以位于第一子区的相对设置的两侧。
这里，第三子沟槽和第四子沟槽沿Z方向上的高度基本相同，第三子沟槽沿Y方向上的宽度小于第四子沟槽沿Y方向上的宽度。在一具体示例中，第二沟槽沿Z方向上的高度小于第一沟槽沿Z方向上的高度。
如图5B所示，在第三子沟槽236和第四子沟槽238内形成第三介质层240。这里，由于第三子沟槽236和第四子沟槽238的尺寸不同，因此，第三介质层240可以填满第三子沟槽236以形成第三子隔离结构248，而第三介质层240仅覆盖第四子沟槽238的侧壁和底部。
示例性地，在第三子沟槽内形成第三介质层，第三介质层可以覆盖衬底表面。如此，可以在后续工艺过程中再去除部分第三介质层以暴露出衬底表面。
在一些实施例中，第三介质层的材料可以包括但不限于二氧化硅。
如图5B所示，形成第二隔离层242，第二隔离层242可以覆盖位于衬底200表面的第三介质层240和位于第四子沟槽238内的第三介质层240的表面；在第四子沟槽238内形成第四介质层244，第四介质层244可以覆盖位于衬底200表面的第二隔离层242和位于第四子沟槽238内的第二隔离层242；其中，第四介质层244可以填满第四子沟槽238。
这里，第二隔离层覆盖器件区和外围区，当然，第二隔离层覆盖位于第一子区的第一子沟槽内的第一介质层的表面、位于第二子区的第二子沟槽内的第二介质层的表面和位于外围区的第三沟槽内的第二介质层的表面。当然，第四介质层也会覆盖位于器件区和外围区的第二隔离层的表面。
在一些实施例中，形成第三介质层、第二隔离层和第四介质层的工艺包括但不限于CVD、PVD以及ALD或其任意组合。
在一些实施例中，第二隔离层的材料可以包括但不限于氮化硅；第四介质层的材料可以包括但不限于二氧化硅。
在一些实施例中，第一隔离层和第二隔离层的材料可以相同或者不同。
在一些实施例中，第一介质层、第二介质层、第三介质层和第四介质层的材料可以相同或者不同。
如图5B和图5C所示，可以对第四介质层244进行平坦化处理，以暴露出位于器件区202和外围区204的第二隔离层242的表面；还可以对暴露出的第二隔离层242进行回刻处理(Etch Back)，以暴露出第一子沟槽214内的第一介质层220、第二子沟槽216内的第二介质层224、第三子沟槽236内的第三介质层240和第四子沟槽238内的第四介质层244。
这里，第二隔离结构包括第三子隔离结构和第四子隔离结构，第三子隔离结构包括填满第三子沟槽的第三介质层，第四子隔离结构包括依次覆盖第四子沟槽侧壁和底部的第三介质层、第二隔离层和填满第四子沟槽的第四介质层。
这里，沿Y方向延伸的第一子隔离结构和第二子隔离结构，以及沿X方向延伸的第三子隔离结构和第四子隔离结构将衬底的器件区隔离为沿X方向和Y方向呈阵列排布的多个有源柱。更具体而言，沿Y方向延伸的第一子隔离结构和沿X方向延伸的第三子隔离结构将衬底的第一子区隔离为呈阵列排布的多个有源柱。每个有源柱包括沿Z方向相对设置的第一端和第二端以及位于第一端和第二端之间的沟道区，晶体管的漏极可以例如为有源柱的第一端，晶体管的源极可以例如为有源柱的第二端，晶体管的栅极可以围绕有源柱的沟道区。位于同一列(即，沿Y方向排列)的多个晶体管的漏极可以连接至同一位线结构，位线结构末端位于第二子区内；位于同一行(即，沿X方向排列)的多个晶体管的栅极可以连接至同一字线结构，字线结构末端位于第二子区内。
这里，沿Y方向延伸的第三隔离结构将衬底的外围区隔离为多个有源区，后续可以用于形成外围电路的晶体管。
需要说明的是，覆盖第二子沟槽侧壁和底部的第一隔离层和覆盖第三沟槽侧壁和底部的第一隔离层被第二介质层掩盖而未暴露出，覆盖第四子沟槽侧壁和底部的第二隔离层被第四介质层掩盖而未暴露出。因此，回刻处理难以去除这些被遮挡而未暴露出的第一隔离层或者第二隔离层。
本公开实施例中，在步骤S302之前，该制造方法还包括：
形成第三隔离层252，第三隔离层252覆盖器件区202的第一隔离结构226和第二隔离结构246；
去除部分第三隔离层252，以保留覆盖第四子沟槽238内第四介质层244的第三隔离层252。
如图5D所示，形成第三隔离层252，第三隔离层252覆盖器件区202和外围区204；更具体而言，第三隔离层252覆盖位于器件区202的第一隔离结构226(即，第一子隔离结构228和第二子隔离结构230)的表面、第二隔离结构246(即，第三子隔离结构248和第四子隔离结构250)的表面以及位于外围区204的第三隔离结构232的表面。
在一些实施例中，形成第三隔离层的工艺包括但不限于CVD、PVD以及ALD或其任意组合。
在一些实施例中，第三隔离层的材料包括但不限于氮化硅。
如图5E所示，在第三隔离层252上形成光刻胶层254，光刻胶层254覆盖位于外围区204的第三隔离层252和位于第二子区208的第四子沟槽238内的第四介质层244。也就是说，第三隔离结构232在XY平面上的正投影位于光刻胶层254在XY平面上的正投影的范围之内，且第四子隔离结构250的第四介质层244在XY平面上的正投影位于光刻胶层254在XY平面上的正投影的范围之内。
如图5E和图5F所示，以光刻胶层254作为掩膜，去除未被光刻胶层254覆盖的部分第三隔离层252，以保留被光刻胶层254覆盖的部分第三隔离层252；去除光刻胶层254。
示例性地，可以使用灰化工艺去除光刻胶层。
这里，图5F示意出仍保留覆盖外围区204的第三隔离层252和覆盖第二子区208的第四子沟槽238内第四介质层244的第三隔离层252。如此，在后续工艺过程中，第三隔离层可以起到保护作用，避免后续工艺损伤外围区的第三隔离结构以及第二子区的第四子沟槽内的第四介质层。
本公开实施例中，在步骤S302的同时，该制造方法还包括：
去除第三子沟槽236内的部分第三介质层240和第四子沟槽238内的部分第三介质层240，以暴露出有源柱210的至少部分侧壁和第二隔离层242的至少部分侧壁。
如图5G所示，去除第一子沟槽214内的部分第一介质层220和第二子沟槽216内的部分第一介质层220和第二介质层224的同时，去除第三子沟槽236内的部分第三介质层240和第四子沟槽238内的部分第三介质层240；其中，去除第一子沟槽214内的部分第一介质层220以暴露出有源柱210平行于Y方向的侧壁，去除第二子沟槽216内的部分第一介质层220和第二介质层224以暴露出有源柱210平行于Y方向的侧壁和第一隔离层222平行于Y方向的两个侧壁，去除第三子沟槽236 内的部分第三介质层240以暴露出有源柱210平行于X方向的侧壁，去除第四子沟槽238内的部分第三介质层240以暴露出有源柱210平行于X方向的侧壁和器件区202的第二隔离层242平行于X方向的一个侧壁。
这里，有源柱沿Z方向延伸，有源柱可以具有平行X方向的两个侧壁和平行Y方向的两个侧壁，去除第一介质层、第二介质层和第三介质层，可以暴露出有源柱的四个侧壁。当然，也可以暴露出衬底表面，即，暴露出有源柱的顶表面。
需要说明的是，暴露出的有源柱的侧壁沿Z方向上的高度h0小于第一沟槽沿Z方向上的高度h1，且暴露出的有源柱的侧壁沿Z方向上的高度h0小于第二沟槽沿Z方向上的高度h2。有源柱平行于Y方向的部分侧壁仍被第一介质层覆盖，有源柱平行于X方向的部分侧壁仍被第三介质层覆盖。如图5G中c-c方向的剖视结构示意图所示，侧壁被第一介质层覆盖的部分有源柱沿Z方向上的高度为(h1-h0)；如图5G中a-a方向的剖视结构示意图所示，侧壁被第三介质层覆盖的部分有源柱沿Z方向上的高度为(h2-h0)。
需要说明的是，暴露出的第一隔离层平行于Y方向的两个侧壁，且未暴露出的第一隔离层平行于Y方向的两个侧壁分别和第一介质层、第二介质层直接接触。第二子沟槽内第一介质层和第二介质层的表面基本齐平，即，暴露出的第一隔离层的两个侧壁沿Z方向上的高度基本相同。当然，暴露出的第一隔离层的侧壁沿Z方向上的高度d1小于第二子沟槽沿Z方向上的高度h1。更具体而言，暴露出的第一隔离层的侧壁沿Z方向上的高度d1和暴露出的有源柱的侧壁沿Z方向上的高度h0基本相同。
需要说明的是，基本相同指的是暴露出的第一隔离层的侧壁沿Z方向上的高度和暴露出的有源柱的侧壁沿Z方向上的高度之差小于预设值，即，暴露出的第一隔离层的侧壁沿Z方向上的高度和暴露出的有源柱的侧壁沿Z方向上的高度之差满足工艺误差要求范围。在一具体示例中，暴露出的第一隔离层的侧壁沿Z方向上的高度和暴露出的有源柱的侧壁沿Z方向上的高度之差为0。
本公开实施例中，去除第三子沟槽236内的部分第三介质层240和第四子沟槽238内的部分第三介质层240之后，该制造方法还包括：
去除覆盖第四子沟槽238内第四介质层244的第三隔离层252；
去除第四子沟槽238内的部分第四介质层244；其中，第四子沟槽238内的第四介质层244的表面高于第三介质层240的表面。
仍如图5G所示，去除覆盖第四子沟槽238内第四介质层244的第三隔离层252的同时，也去除覆盖外围区204的第三隔离层252，分别以暴露出第四子沟槽238内的第四介质层244和第三沟槽218内的第二介质层224；去除第四子沟槽238内的部分第四介质层244，以暴露出器件区202的第二隔离层242平行于X方向的另一个侧壁；以及去除外围区204的部分第二介质层224、部分第三介质层240和部分第四介质层244，以暴露出衬底200表面以及暴露出外围区204的第二隔离层242平行于Y方向的两个侧壁。
需要说明的是，对于器件区的第二子区而言，暴露出的第二隔离层平行于X方向的两个侧壁，且未暴露出的第二隔离层平行于X方向的两个侧壁分别和第三介质层、第四介质层直接接触。当然，暴露出的第二隔离层的侧壁沿Z方向上的高度小于第四子沟槽沿Z方向上的高度h2。第四子沟槽内第四介质层表面高于第三介质层表面，即，暴露出第二隔离层的两个侧壁沿Z方向上的高度不同。更具体而言，暴露出的第二隔离层的靠近第三介质层的侧壁沿Z方向上的高度d2大于暴露出的第二隔离层的靠近第四介质层的侧壁沿Z方向上的高度d3。也就是说，第二子沟槽内的第一介质层、第二介质层和第四子沟槽内的第三介质层的表面基本齐平，且第二子沟槽内的第一介质层、第二介质层和第四子沟槽内的第三介质层的表面低于第四子沟槽内的第四介质层的表面。在一具体示例中，第四子沟槽内的第四介质层的表面和有源柱的顶表面基本齐平。
需要说明的是，对于外围区而言，暴露出的第二隔离层平行于Y方向的两个侧壁，且未暴露出的第二隔离层平行于Y方向的两个侧壁分别和第三介质层、第四介质层直接接触。延伸至外围区的第三隔离结构内的第二沟槽内第三介质层和第四介质层的表面基本齐平，即，暴露出的第二隔离层的两个侧壁沿Z方向上的高度d4基本相同。
本公开实施例中，去除第二子沟槽216内暴露出的部分第一隔离层222的同时，该制造方法还包括：
去除第四子沟槽238内暴露出的部分第二隔离层242。
如图5H所示，去除第二子沟槽216内暴露出的部分第一隔离层222、去除第四子沟槽238内暴露出的部分第二隔离层242以及去除第三沟槽218内暴露出的部分第二隔离层242。如此，第二子 沟槽216内的第一介质层220、第一隔离层222和第二介质层224的表面基本齐平；第四子沟槽238内剩余的第二隔离层242完全被第四介质层244覆盖；第二沟槽234延伸至第三沟槽218内的第三介质层240、第二隔离层242和第四介质层244的表面基本齐平。
在一些实施例中，去除第一隔离层和第二隔离层的工艺包括干法刻蚀(Dry Etch)、湿法刻蚀(Wet Etch)或其组合。本公开实施例对于去除第一隔离层和第二隔离层的工艺并无特殊的限定。
本公开实施例中，去除第二子沟槽216内暴露出的部分第一隔离层222之后，该制造方法还包括：
形成沿第二方向延伸的多个字线结构272；字线结构272包覆位于同一行的有源柱210的沟道区266。
本公开实施例中，第一子沟槽214和第二子沟槽216共同形成第一沟槽212，第三子沟槽236和第四子沟槽238共同形成第二沟槽234；
形成沿第二方向延伸的多个字线结构272，包括：
在第一沟槽212和第二沟槽234内形成至少包覆有源柱210的沟道区266的栅介质层256；
在第一沟槽212和第二沟槽234内形成至少覆盖部分栅介质层256的栅导电层270；栅导电层270包覆位于同一行的有源柱210的沟道区266，第一子沟槽214和第二子沟槽216内的栅导电层270电连接；其中，栅介质层256和栅导电层270共同形成字线结构272。
如图5I所示，在第一沟槽212和第二沟槽234内形成覆盖有源柱210暴露出的四个侧壁的栅介质层256，且栅介质层256还可以覆盖有源柱210的顶表面。
在一些实施例中，形成栅介质层的工艺包括但不限于CVD、PVD以及ALD或其任意组合。在另一些实施例中，可以使用原位氧化工艺形成栅介质层，例如，对有源柱暴露出的侧壁和顶表面进行氧化处理，以形成栅介质层。
在一些实施例中，栅介质层的材料包括但不限于二氧化硅。
如图5J所示，形成导电材料层258，导电材料层258覆盖器件区202和外围区204。如前所述，第一介质层220、第二介质层224和第三介质层240的表面基本齐平，且第一介质层220、第二介质层224和第三介质层240的表面低于第四介质层244表面。因此，导电材料层258可以填满第一子沟槽214、第三子沟槽236和第四子沟槽238且未填满第二子沟槽216。
在一些实施例中，形成导电材料层的工艺包括但不限于CVD、PVD以及ALD或其任意组合。
在一些实施例中，导电材料层的材料包括但不限于氮化钛或者金属材料，例如，金属钨。
本公开实施例中，在第一沟槽212和第二沟槽234内形成至少覆盖部分栅介质层256的栅导电层270，包括：
形成导电材料层258，导电材料层258填满第一沟槽212和第二沟槽234；
去除覆盖有源柱的第二端264的导电材料层258；
形成第四隔离层268，第四隔离层268填满第一沟槽212和第二沟槽234；
依次对第二沟槽234内的第四隔离层268和导电材料层258进行刻蚀，以形成字线隔槽和栅导电层270；其中，字线隔槽沿第二方向延伸；第二子沟槽216内的栅导电层270和栅介质层256直接接触，第四子沟槽238内的栅导电层270和第四介质层244直接接触；
在字线隔槽中填充隔离材料，以形成字线隔离结构274。
如图5K所示，形成绝缘层260，绝缘层260覆盖器件区202和外围区204。如前所述，导电材料层258填满第一子沟槽214、第三子沟槽236和第四子沟槽238且未填满第二子沟槽216。因此，绝缘层260可以填满第二子沟槽216。
在一些实施例中，形成绝缘层的工艺包括但不限于ALD。
在一些实施例中，绝缘层的材料包括但不限于二氧化硅。
如图5L所示，可以对绝缘层260进行平坦化处理，以暴露出导电材料层258。
在一些实施例中，平坦化处理可以包括但不限于CMP。
如图5M所示，刻蚀去除部分导电材料层258，以暴露出有源柱的第二端264，剩余的导电材料层258包覆有源柱的沟道区266。这里，还可以去除位于有源柱210顶表面的栅介质层256，仅保留覆盖有源柱210侧壁的栅介质层256，即，栅介质层256可以覆盖有源柱210的沟道区266和第二端264。
需要说明的是，第一子沟槽和第二子沟槽内剩余的导电材料层的表面基本齐平，且第二子沟槽内部分剩余的导电材料层上覆盖有绝缘层；第三子沟槽和第四子沟槽内剩余的导电材料层的表面基本齐平。
如图5N所示，在第一沟槽212和第二沟槽234内形成第四隔离层268，第四隔离层268覆盖位于第一子沟槽214、第二子沟槽216、第三子沟槽236和第四子沟槽238内剩余的导电材料层258的表面；其中，第四隔离层268填满第一子沟槽214、第二子沟槽216、第三子沟槽236和第四子沟槽238。
示例性地，在第一沟槽和第二沟槽内形成第四隔离材料层，第四隔离材料层可能覆盖有源柱的顶表面；对第四隔离材料层进行平坦化处理或者回刻处理，去除部分第四隔离材料层，以暴露出有源柱的顶表面，使得剩余的第四隔离材料层表面和有源柱顶表面基本齐平，将剩余的第四隔离材料层作为第四隔离层。
在一些实施例中，形成第四隔离层的工艺包括但不限于CVD、PVD以及ALD或其任意组合。
在一些实施例中，第四隔离层的材料包括但不限于氮化硅。
仍如图5N和图5O所示，还可以依次对第二沟槽234内的第四隔离层268和剩余的导电材料层258进行刻蚀，以形成字线隔槽和栅导电层270；其中，字线隔槽沿X方向延伸；还可以在字线隔槽中填充隔离材料，以形成字线隔离结构274。
这里，形成字线隔离结构的目的在于将不同的字线结构隔离开。
这里，字线结构的栅导电层可以为复合导电层，例如，栅导电层可以包括氮化钛和金属钨。本公开实施例对于栅导电层的层数和材料并无特殊的限定。
本公开实施例中，沿X方向延伸的字线结构包括栅介质层和栅导电层，栅介质层包覆位于同一行的有源柱的沟道区，栅导电层包覆位于同一行的有源柱的沟道区的栅介质层；其中，第二子沟槽内的栅导电层和栅介质层直接接触，即，第二子沟槽内的栅导电层未被第一隔离层隔离开；如此，第一子沟槽和第二子沟槽内的栅导电层电连接。换言之，第一子区内的字线结构和第二子区内的字线结构末端可以实现电连接，不存在字线结构断开的风险。
本公开实施例中，不同字线结构被字线隔离结构隔离开，第四子沟槽内的栅导电层和第四介质层直接接触，即，第四子沟槽内的栅导电层未和第二隔离层接触；如此，第四子沟槽内的第二隔离层被埋入第四介质层下方，可以避免第四子沟槽内暴露出的第二隔离层对后续形成的位线结构造成污染。
本公开实施例中，去除第二子沟槽216内暴露出的部分第一隔离层222之后，该制造方法还包括：
形成沿第一方向延伸的多个位线结构276；位线结构276将位于同一列的有源柱210的第一端262依次连接；
形成多个存储电容；存储电容的第一电极和有源柱的第二端264连接，存储电容的第二电极和公共端连接。
这里，还可以形成沿Y方向延伸的位线结构，位线结构将位于同一列的有源柱的第一端依次连接；存储电容的第一电极和有源柱的第二端连接，存储电容的第二电极和公共端连接。
需要说明的是，本公开实施例中，有源柱的第一端可以例如为源极，有源柱的第二端可以例如为漏极；或者，有源柱的第一端可以例如为漏极，有源柱的第二端可以例如为源极。
本公开实施例中，去除第一子沟槽内的部分第一介质层和第二子沟槽内的部分第一介质层和第二介质层，以分别暴露出有源柱的至少部分侧壁和第一隔离层的部分侧壁；去除第二子沟槽内暴露出的部分第一隔离层；如此，在形成字线结构的过程中，第一子沟槽和第二子沟槽内的字线结构可以实现电连接，即，位于第一子区内用于连接同一行的存储单元栅极的字线结构和位于第二子区内的字线结构末端可以实现电连接。进一步地，去除第二子沟槽内暴露出的部分第一隔离层的同时，还可以去除第四子沟槽内暴露出的部分第二隔离层，以避免暴露出的第二隔离层对后续形成的位线结构造成污染。
参考图6和图7，图6为本公开实施例提供的半导体器件的俯视结构示意图，图7为本公开实施例提供的半导体器件的剖视结构示意图。如图6和图7所示，本公开实施例提供一种半导体器件，该半导体器件包括：
衬底200；衬底200包括器件区202和外围区204，器件区202包括第一子区206和第二子区208，第二子区208位于第一子区206和外围区204之间；
器件区202的衬底200包括沿第一方向延伸的多个第一沟槽212和沿第二方向延伸的多个第二沟槽234，第一沟槽212和第二沟槽234共同隔离出多个有源柱210；有源柱210包括沿第三方向相对设置的第一端262和第二端264以及位于第一端262和第二端264之间的沟道区266；第一沟槽212包括位于第一子区206的第一子沟槽214和位于第二子区208的第二子沟槽216；其中，第一方 向和第二方向均平行于衬底200且第一方向和第二方向相交，第三方向垂直于衬底200；
沿第二方向延伸的多个字线结构272，位于第一沟槽212和第二沟槽234内；字线结构272包覆位于同一行的有源柱的沟道区266；其中，第一子沟槽214内的字线结构272和第二子沟槽216内的字线结构272电连接。
图7中c-c方向的剖面结构示意图中虚线方框示意出有源柱210，有源柱210包括沿Z方向相对设置的第一端262和第二端264以及位于第一端262和第二端264之间的沟道区266。
本公开实施例中，第一子沟槽和第二子沟槽内的字线结构可以电连接，即，位于第一子区内用于连接同一行的存储单元栅极的字线结构和位于第二子区内的字线结构末端可以电连接。
本公开实施例中，该半导体器件还包括：
沿第二方向延伸的第四隔离层268，位于第一沟槽212和第二沟槽234内；第四隔离层268包覆位于同一行的有源柱210的第二端264；
沿第二方向延伸的多个字线隔离结构274，位于相邻字线结构272和相邻第四隔离层268之间。
这里，字线隔离结构274沿X方向延伸，部分字线隔离结构274位于相邻字线结构272之间，且部分字线隔离结构274位于相邻第四隔离层268之间。
本公开实施例中，字线结构272包括：栅介质层256，至少包覆有源柱210的沟道区266；
栅导电层270，位于栅介质层256表面，且包覆位于同一行的有源柱210的沟道区266；其中，第一子沟槽214和第二子沟槽216内的栅导电层270电连接，第二子沟槽216内的栅导电层270和栅介质层256直接接触。
本公开实施例中，该半导体器件还包括：
位于第一子沟槽214和第二子沟槽216内的第一介质层220，第一介质层220位于相邻有源柱210的第一端262之间且第一介质层220覆盖第二子沟槽216侧壁和底部；
覆盖第二子沟槽216侧壁和底部的第一介质层220的第一隔离层222；
位于第二子沟槽216内的第二介质层224，且第二介质层224位于栅导电层270下方。
这里，第二子沟槽216内的第一介质层220、第一隔离层222和第二介质层224的表面基本齐平；其中，第一介质层220覆盖第二子沟槽216的底部和部分侧壁，第一隔离层222覆盖第一介质层220，第二介质层224覆盖第一隔离层222；第二子沟槽216内的栅导电层270位于第一介质层220、第一隔离层222和第二介质层224的上方；第二子沟槽216内还有第四隔离层268和绝缘层260，第四隔离层268和绝缘层260位于栅导电层270上方。
换言之，第二介质层224的顶表面和栅导电层270直接接触。第二子沟槽216内的第一介质层220、第一隔离层222和第二介质层224在XY平面上的正投影位于第二子沟槽216内的栅导电层在XY平面上的正投影范围之内。
本公开实施例中，第二沟槽234包括位于第一子区206的第三子沟槽236和位于第二子区208的第四子沟槽238；该半导体器件还包括：
位于第三子沟槽236和第四子沟槽238内的第三介质层240，第三介质层240位于相邻有源柱210的第一端262之间且第三介质层240覆盖第四子沟槽238侧壁和底部；
覆盖第四子沟槽238底部的第三介质层240的第二隔离层242；
位于第四子沟槽238内的第四介质层244，且第四介质层244侧壁和栅导电层270、第四隔离层268直接接触。
这里，第三介质层240覆盖第四子沟槽238的底部和部分侧壁，第二隔离层242覆盖部分第三介质层240，第四介质层244覆盖第二隔离层242，即，第二隔离层242在XY平面上的正投影位于第四介质层244在XY平面上的正投影范围之内。栅导电层270位于第三介质层240上方，第四隔离层268位于栅导电层270上方；其中，第四隔离层268和第四介质层244的表面基本齐平。
换言之，第四介质层244平行于X方向的侧壁和栅导电层270直接接触。第四子沟槽238内的第二隔离层242和第四介质层244在XY平面上的正投影位于第二子沟槽216内的栅导电层在XY平面上的正投影范围之外。
本公开实施例中，该半导体器件还包括：
位于外围区204且沿第一方向延伸的第三隔离结构232，第三隔离结构232包括第一部分278和第二部分280，第二沟槽234延伸至第三隔离结构232内的部分为第二部分280；
第一部分278(如图7中e-e方向的剖面结构示意图中虚线方框所示)包括依次覆盖第三沟槽218侧壁和底部的第一介质层220、第一隔离层222和覆盖第一隔离层222的第二介质层224；
第二部分280(如图7中e-e方向的剖面结构示意图中虚线方框所示)包括依次覆盖第二沟槽 234延伸至第三隔离结构232至少部分侧壁和底部的第三介质层240和第二隔离层242和填满第二沟槽234延伸至第三隔离结构232部分的第四介质层244。
本公开实施例中，该半导体器件还包括：
沿第一方向延伸多个位线结构276，位线结构276将位于同一列的有源柱210的第一端262依次连接；
多个存储电容；存储电容的第一电极和有源柱210的第二端264连接，存储电容的第二电极和公共端连接。
本公开实施例提供一种半导体器件及其制造方法。本公开实施例中，去除第一子沟槽内的部分第一介质层和第二子沟槽内的部分第一介质层和第二介质层，以分别暴露出有源柱的至少部分侧壁和第一隔离层的至少部分侧壁；去除第二子沟槽内暴露出的部分第一隔离层；如此，在后续形成字线结构的过程中，第一子沟槽和第二子沟槽内的字线结构可以实现电连接，即，位于第一子区内用于连接同一行的存储单元栅极的字线结构和位于第二子区内的字线结构末端可以实现电连接。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本公开的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本公开的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本公开实施例的实施过程构成任何限定。上述本公开实施例序号仅仅为了描述，不代表实施例的优劣。
以上所述仅为本公开的优选实施方式，并非因此限制本公开的专利范围，凡是在本公开的发明构思下，利用本公开说明书及附图内容所作的等效结构变换，或直接/间接运用在其他相关的技术领域均包括在本公开的专利保护范围内。
工业实用性
本公开实施例中，去除第一子沟槽内的部分第一介质层和第二子沟槽内的部分第一介质层和第二介质层，以分别暴露出有源柱的至少部分侧壁和第一隔离层的至少部分侧壁；去除第二子沟槽内暴露出的部分第一隔离层；如此，在后续形成字线结构的过程中，第一子沟槽和第二子沟槽内的字线结构可以实现电连接，即，位于第一子区内用于连接同一行的存储单元栅极的字线结构和位于第二子区内的字线结构末端可以实现电连接。

Claims (18)

  1. 一种半导体器件的制造方法，所述制造方法包括：
    提供衬底(100)，所述衬底(100)包括器件区(102)和外围区(104)，所述器件区(102)包括第一子区(106)和第二子区(108)，所述第二子区(108)位于所述第一子区(106)和所述外围区(104)之间；所述器件区(102)的衬底(100)包括沿第一方向延伸的多个第一隔离结构(226)和沿第二方向延伸的多个第二隔离结构(246)，所述第一隔离结构(226)和所述第二隔离结构(246)共同隔离出多个有源柱(110)；所述第一隔离结构(226)包括位于所述第一子区(106)的第一子隔离结构(228)和位于所述第二子区(208)的第二子隔离结构(230)，所述第一子隔离结构(228)包括填满第一子沟槽(214)的第一介质层(220)，所述第二子隔离结构(230)包括依次覆盖第二子沟槽(216)侧壁和底部的第一介质层(220)、第一隔离层(222)和填满第二子沟槽(216)的第二介质层(224)；其中，所述第一方向和所述第二方向均平行于所述衬底(100)且所述第一方向和所述第二方向相交；
    去除所述第一子沟槽(214)内的部分第一介质层(214)和所述第二子沟槽(216)内的部分第一介质层(214)和第二介质层(224)，以分别暴露出所述有源柱(110)的至少部分侧壁和所述第一隔离层(222)的至少部分侧壁；
    去除所述第二子沟槽(216)内暴露出的部分第一隔离层(222)。
  2. 根据权利要求1所述的半导体器件的制造方法，其中，所述第二隔离结构(246)包括位于所述第一子区(206)的第三子隔离结构(248)和位于所述第二子区(208)的第四子隔离结构(250)，所述第三子隔离结构(248)包括填满第三子沟槽(236)的第三介质层(240)，所述第四子隔离结构(250)包括依次覆盖第四子沟槽(238)侧壁和底部的第三介质层(240)、第二隔离层(242)和填满第四子沟槽(238)的第四介质层(244)；
    所述去除所述第一子沟槽(214)内的部分第一介质层(220)和所述第二子沟槽(216)内的部分第一介质层(220)和第二介质层(224)之前，所述制造方法还包括：
    形成第三隔离层(252)，所述第三隔离层(252)覆盖所述器件区(102)的第一隔离结构(226)和第二隔离结构(246)；
    去除部分所述第三隔离层(252)，以保留覆盖所述第四子沟槽(238)内第四介质层(244)的第三隔离层(252)。
  3. 根据权利要求2所述的半导体器件的制造方法，其中，所述去除所述第一子沟槽(214)内的部分第一介质层(220)和所述第二子沟槽(216)内的部分第一介质层(220)和第二介质层(224)的同时，所述制造方法还包括：
    去除所述第三子沟槽(236)内的部分第三介质层(240)和所述第四子沟槽(238)内的部分第三介质层(240)，以暴露出所述有源柱(110)的至少部分侧壁和所述第二隔离层(242)的至少部分侧壁。
  4. 根据权利要求3所述的半导体器件的制造方法，其中，所述去除所述第三子沟槽(236)内的部分第三介质层(240)和所述第四子沟槽(238)内的部分第三介质层(240)之后，所述制造方法还包括：
    去除覆盖所述第四子沟槽(238)内第四介质层(244)的第三隔离层(252)；
    去除所述第四子沟槽(238)内的部分第四介质层(244)；其中，所述第四子沟槽(238)内的第四介质层(244)的表面高于所述第三介质层(240)的表面。
  5. 根据权利要求4所述的半导体器件的制造方法，其中，所述去除所述第二子沟槽(216)内暴露出的部分第一隔离层(222)的同时，所述制造方法还包括：
    去除所述第四子沟槽(238)内暴露出的部分第二隔离层(242)。
  6. 根据权利要求5所述的半导体器件的制造方法，其中，所述有源柱(210)包括沿第三方向相对设置的第一端(262)和第二端(264)以及位于所述第一端(262)和所述第二端(264)之间的沟道区(266)；所述第三方向垂直于所述衬底(100)；
    所述去除所述第二子沟槽(216)内暴露出的部分第一隔离层(222)之后，所述制造方法还包括：
    形成沿所述第二方向延伸的多个字线结构(272)；所述字线结构(272)包覆位于同一行的所述有源柱(210)的沟道区(266)。
  7. 根据权利要求6所述的半导体器件的制造方法，其中，所述第一子沟槽(114)和所述第二子沟槽(116)共同形成第一沟槽(112)，所述第三子沟槽(120)和所述第四子沟槽(122)共同形成第二沟槽(118)；
    所述形成沿所述第二方向延伸的多个字线结构(272)，包括：
    在所述第一沟槽(112)和所述第二沟槽(118)内形成至少包覆所述有源柱(210)的沟道区(266)的栅介质层(256)；
    在所述第一沟槽(112)和所述第二沟槽(118)内形成至少覆盖部分所述栅介质层(256)的栅导电层(270)；所述栅导电层(270)包覆位于同一行的所述有源柱(210)的沟道区(266)，所述第一子沟槽(114)和所述第二子沟槽(116)内的栅导电层电连接；其中，所述栅介质层(256)和所述栅导电层(270)共同形成字线结构(272)。
  8. 根据权利要求7所述的半导体器件的制造方法，其中，所述在所述第一沟槽(112)和所述第二沟槽(118)内形成至少覆盖部分所述栅介质层(256)的栅导电层(270)，包括：
    形成导电材料层(258)，所述导电材料层(258)填满所述第一沟槽(112)和所述第二沟槽(118)；
    去除覆盖所述有源柱(210)的第二端(264)的导电材料层(258)；
    形成第四隔离层(268)，所述第四隔离层(268)填满所述第一沟槽(212)和所述第二沟槽(234)；
    依次对所述第二沟槽(234)内的第四隔离层(268)和导电材料层(258)进行刻蚀，以形成字线隔槽和栅导电层(270)；其中，所述字线隔槽沿所述第二方向延伸；所述第二子沟槽(216)内的栅导电层(270)和栅介质层(256)直接接触，所述第四子沟槽(238)内的栅导电层(270)和第四介质层(244)直接接触；
    在所述字线隔槽中填充隔离材料，以形成字线隔离结构(274)。
  9. 根据权利要求6至8中任一项所述的半导体器件的制造方法，其中，所述去除所述第二子沟槽(216)内暴露出的部分第一隔离层(222)之后，所述制造方法还包括：
    形成沿所述第一方向延伸的多个位线结构(276)；所述位线结构(276)将位于同一列的所述有源柱(210)的第一端(262)依次连接；
    形成多个存储电容；所述存储电容的第一电极和所述有源柱(210)的第二端(264)连接，所述存储电容的第二电极和公共端连接。
  10. 根据权利要求2至9中任一项所述的半导体器件的制造方法，其中，所述提供衬底(200)，包括：
    刻蚀所述衬底(200)，以在所述器件区(202)内形成第一沟槽(212)且在所述外围区(204)内形成第三沟槽(218)；所述第一沟槽(212)和所述第三沟槽(218)均沿所述第一方向延伸；所述第一沟槽(212)包括位于所述第一子区(206)的第一子沟槽(214)和位于所述第二子区(208)的第二子沟槽(216)；
    形成第一介质层(220)，所述第一介质层(220)覆盖所述第二子沟槽(216)和所述第三沟槽(218)的侧壁和底部，且所述第一介质层(220)填满所述第一子沟槽(214)，以形成第一子隔离结构(228)；
    形成第一隔离层(222)，所述第一隔离层(222)覆盖所述第一介质层(220)；
    形成第二介质层(224)，所述第二介质层(224)填满所述第二子沟槽(216)和所述第三沟槽(218)，以分别形成第二子隔离结构(230)和第三隔离结构(232)。
  11. 根据权利要求10所述的半导体器件的制造方法，其中，所述提供衬底(200)，还包括：
    刻蚀所述衬底(200)、所述第一介质层(220)和所述第二介质层(224)，以在所述器件区(202)内形成第二沟槽(234)，所述第二沟槽(234)还延伸至所述外围区(204)的第三沟槽(218)内；所述第二沟槽(234)沿所述第二方向延伸；所述第二沟槽(234)包括位于所述第一子区(206)的第三子沟槽(236)和位于所述第二子区(208)的第四子沟槽(238)；
    形成第三介质层(240)，所述第三介质层(240)覆盖所述第四子沟槽(238)的侧壁和底部，且所述第三介质层(240)填满所述第三子沟槽(236)，以形成第三子隔离结构(248)；
    形成第二隔离层(242)，所述第二隔离层(242)覆盖所述第三介质层(240)；
    形成第四介质层(244)，所述第四介质层(244)填满所述第四子沟槽(238)，以形成第四子隔离结构(250)。
  12. 一种半导体器件，所述半导体器件包括：
    衬底(200)；所述衬底(200)包括器件区(202)和外围区(204)，所述器件区(202)包括第一子区(206)和第二子区(208)，所述第二子区(208)位于所述第一子区(206)和所述外围区(204)之间；
    所述器件区(202)的衬底(200)包括沿第一方向延伸的多个第一沟槽(212)和沿第二方向延伸的多个第二沟槽(234)，所述第一沟槽(212)和所述第二沟槽(234)共同隔离出多个有源柱(210)；所述有源柱(210)包括沿第三方向相对设置的第一端(262)和第二端(264)以及位于所述第一端(262)和所述第二端(264)之间的沟道区(266)；所述第一沟槽(212)包括位于所述第一子区(206)的第一子沟槽(214)和位于所述第二子区(208)的第二子沟槽(216)；其中，所述第一方向和所述第二方向均平行于所述衬底(200)且所述第一方向和所述第二方向相交，所述第三方向垂直于所述衬底(200)；
    沿所述第二方向延伸的多个字线结构(272)，位于所述第一沟槽(212)和所述第二沟槽(234)内；所述字线结构(272)包覆位于同一行的所述有源柱(210)的沟道区(266)；其中，所述第一子沟槽(214) 内的字线结构(272)和所述第二子沟槽(216)内的字线结构(272)电连接。
  13. 根据权利要求12所述的半导体器件，其中，所述半导体器件还包括：
    沿所述第二方向延伸的第四隔离层(268)，位于所述第一沟槽(212)和所述第二沟槽(234)内；所述第四隔离层(268)包覆位于同一行的所述有源柱(210)的第二端(264)；
    沿所述第二方向延伸的多个字线隔离结构(274)，位于相邻所述字线结构(272)和相邻所述第四隔离层(268)之间。
  14. 根据权利要求13所述的半导体器件，其中，所述字线结构(272)包括：
    栅介质层(256)，至少包覆所述有源柱(210)的沟道区(266)；
    栅导电层(270)，位于所述栅介质层(256)表面，且包覆位于同一行的所述有源柱(210)的沟道区(266)；其中，所述第一子沟槽(214)和所述第二子沟槽(216)内的栅导电层(270)电连接，所述第二子沟槽(216)内的栅导电层(270)和栅介质层(256)直接接触。
  15. 根据权利要求14所述的半导体器件，其中，所述半导体器件还包括：
    位于所述第一子沟槽(214)和第二子沟槽(216)内的第一介质层(220)，所述第一介质层(220)位于相邻所述有源柱(210)的第一端(262)之间且第一介质层(220)覆盖第二子沟槽(216)侧壁和底部；
    覆盖所述第二子沟槽(216)侧壁和底部的第一介质层(220)的第一隔离层(222)；
    位于所述第二子沟槽(216)内的第二介质层(224)，且所述第二介质层(224)位于所述栅导电层下方。
  16. 根据权利要求14或15所述的半导体器件，其中，所述第二沟槽(234)包括位于所述第一子区(206)的第三子沟槽(236)和位于所述第二子区(208)的第四子沟槽(238)；所述半导体器件还包括：
    位于所述第三子沟槽(236)和第四子沟槽(238)内的第三介质层(240)，所述第三介质层(240)位于相邻所述有源柱(210)的第一端(262)之间且第三介质层(240)覆盖第四子沟槽(238)侧壁和底部；
    覆盖所述第四子沟槽(238)底部的第三介质层(240)的第二隔离层(242)；
    位于所述第四子沟槽(238)内的第四介质层(244)，且所述第四介质层(244)侧壁和所述栅导电层(270)、第四隔离层(268)直接接触。
  17. 根据权利要求16所述的半导体器件，其中，所述半导体器件还包括：
    位于所述外围区(204)且沿所述第一方向延伸的第三隔离结构(232)，所述第三隔离结构(232)包括第一部分和第二部分，所述第二沟槽(234)延伸至所述第三隔离结构(232)内的部分为第二部分；
    所述第一部分包括依次覆盖第三沟槽(218)侧壁和底部的第一介质层(220)、第一隔离层(222)和覆盖所述第一隔离层(222)的第二介质层(224)；
    所述第二部分包括依次覆盖所述第二沟槽(234)延伸至所述第三隔离结构(232)至少部分侧壁和底部的第三介质层(240)和第二隔离层(242)和填满所述第二沟槽(234)延伸至所述第三隔离结构(232)部分的第四介质层(244)。
  18. 根据权利要求12至17中任一项所述的半导体器件，其中，所述半导体器件还包括：
    沿所述第一方向延伸多个位线结构(276)，所述位线结构(276)将位于同一列的所述有源柱(210)的第一端(262)依次连接；
    多个存储电容；所述存储电容的第一电极和所述有源柱(210)的第二端(264)连接，所述存储电容的第二电极和公共端连接。
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