WO2024252971A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024252971A1
WO2024252971A1 PCT/JP2024/019425 JP2024019425W WO2024252971A1 WO 2024252971 A1 WO2024252971 A1 WO 2024252971A1 JP 2024019425 W JP2024019425 W JP 2024019425W WO 2024252971 A1 WO2024252971 A1 WO 2024252971A1
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Prior art keywords
region
regions
semiconductor device
main surface
concentration
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PCT/JP2024/019425
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English (en)
French (fr)
Japanese (ja)
Inventor
一 和栗
佑紀 中野
誠悟 森
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2025526057A priority Critical patent/JPWO2024252971A1/ja
Publication of WO2024252971A1 publication Critical patent/WO2024252971A1/ja
Priority to US19/409,917 priority patent/US20260090037A1/en
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    • H10D62/81—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation
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    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
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    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
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    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
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    • H10D62/051—Forming charge compensation regions, e.g. superjunctions
    • H10D62/054—Forming charge compensation regions, e.g. superjunctions by high energy implantations in bulk semiconductor bodies, e.g. forming pillars
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    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/109—Reduced surface field [RESURF] PN junction structures
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    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
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    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
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    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping

Definitions

  • Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a drift region, a body region, a gate trench, a gate insulating film, a gate electrode, and a p-type diffusion region.
  • the drift region is formed on the upper surface side of the semiconductor substrate.
  • the body region is formed on the upper surface side of the semiconductor substrate relative to the drift region.
  • the gate trench is formed on the upper surface of the semiconductor substrate and penetrates the body region.
  • the gate insulating film covers the wall surface of the gate trench.
  • the gate electrode is embedded in the gate trench via the gate insulating film.
  • the p-type diffusion region is formed along the bottom wall of the gate trench in the drift region.
  • the present disclosure provides a semiconductor device capable of improving electrical characteristics.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a first conductivity type semiconductor region formed on a surface layer portion of the main surface, a trench-type gate structure formed on the main surface and positioned within the semiconductor region, a second conductivity type body region formed in a region on the main surface side relative to a depth position of a bottom wall of the gate structure in the surface layer portion of the main surface, and a first conductivity type high concentration region formed in a thickness range between the bottom wall of the gate structure and the bottom of the body region within the chip and having an impurity concentration higher than the impurity concentration of the semiconductor region.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing an example of the layout of the first main surface.
  • FIG. 4 is an enlarged plan view showing an example of the layout of a main part of the first main surface.
  • FIG. 5 is a cross-sectional view taken along line V-V shown in FIG.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is an enlarged cross-sectional view of a region including the gate structure shown in FIG.
  • FIG. 8 is an enlarged cross-sectional view of a region including the gate structure shown in FIG. FIG.
  • FIG. 10A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.
  • FIG. 10B is a cross-sectional view showing a step subsequent to that of FIG. 10A.
  • FIG. 10C is a cross-sectional view showing a step subsequent to FIG. 10B.
  • FIG. 10D is a cross-sectional view showing a step subsequent to FIG. 10C.
  • FIG. 10E is a cross-sectional view showing a step subsequent to FIG. 10D.
  • FIG. 10F is a cross-sectional view showing a step subsequent to FIG. 10E.
  • FIG. 10G is a cross-sectional view showing a step subsequent to FIG. 10F.
  • FIG. 10A is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.
  • FIG. 10B is a cross-sectional view showing a step subsequent to that of FIG. 10A.
  • FIG. 10C is a cross-sectional view showing a step subsequent to FIG
  • FIG. 10H is a cross-sectional view showing a step subsequent to FIG. 10G.
  • FIG. 10I is a cross-sectional view showing a step subsequent to FIG. 10H.
  • FIG. 10J is a cross-sectional view showing a step subsequent to FIG. 10I.
  • FIG. 10K is a cross-sectional view showing a step subsequent to FIG. 10J.
  • FIG. 10L is a cross-sectional view showing a step subsequent to FIG. 10K.
  • FIG. 10M is a cross-sectional view showing a step subsequent to FIG. 10L.
  • FIG. 10N is a cross-sectional view showing a step subsequent to FIG. 10M.
  • FIG. 10O is a cross-sectional view showing a step subsequent to FIG. 10N.
  • FIG. 10N is a cross-sectional view showing a step subsequent to FIG. 10N.
  • FIG. 10P is a cross-sectional view showing a step subsequent to that shown in FIG. 10O.
  • FIG. 11 is a cross-sectional view showing a main part of a semiconductor device according to the second embodiment.
  • FIG. 12 is a plan view showing a main part of a semiconductor device according to a third embodiment.
  • 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 12.
  • FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. 12.
  • FIG. 15 is an enlarged cross-sectional view of a region including the source structure shown in FIG.
  • FIG. 16 is an enlarged cross-sectional view of the area including the source structure shown in FIG. FIG.
  • FIG. 17 is a plan view showing a main part of a semiconductor device according to the fourth embodiment.
  • FIG. 18 is a cross-sectional view showing a semiconductor device according to a first modification.
  • FIG. 19 is a cross-sectional view showing a semiconductor device according to a second modification.
  • FIG. 20 is a cross-sectional view showing a semiconductor device according to a third modification.
  • FIG. 21 is a cross-sectional view showing a semiconductor device according to a fourth modification.
  • FIG. 22 is a cross-sectional view showing a semiconductor device according to a fifth modification.
  • FIG. 23 is a cross-sectional view showing a semiconductor device according to a sixth modification.
  • FIG. 24 is a cross-sectional view showing a semiconductor device according to a seventh modification.
  • FIG. 25 is a cross-sectional view showing a semiconductor device according to an eighth modification.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing an example layout of the first main surface 3.
  • FIG. 4 is an enlarged plan view showing an example layout of a major portion of the first main surface 3.
  • FIG. 5 is a cross-sectional view taken along line V-V shown in FIG. 4.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 4.
  • FIG. 7 is an enlarged cross-sectional view of a region including the gate structure 15 shown in FIG. 5.
  • FIG. 8 is an enlarged cross-sectional view of a region including the gate structure 15 shown in FIG. 6.
  • semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure.
  • the transistor structure Tr has a vertical structure.
  • Semiconductor device 1A is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip” or a "semiconductor chip.”
  • the chip 2 is made of hexagonal SiC single crystal and is formed into a rectangular parallelepiped shape.
  • the hexagonal SiC single crystal has a number of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the direction extending along the first main surface 3 may be referred to as the "horizontal direction.”
  • the horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical line toward the off direction by the off angle.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the semiconductor device 1A includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4 of the chip 2.
  • a drain potential is applied to the first semiconductor region 6 as a first potential (high potential).
  • the first semiconductor region 6 may be referred to as a "semiconductor layer", a “first semiconductor layer”, a “drain region”, or the like.
  • the first semiconductor region 6 may have an n-type impurity concentration of 1 ⁇ 10 14 cm -3 or more and 1 ⁇ 10 21 cm -3 or less.
  • the first semiconductor region 6 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • the first semiconductor region 6 is made of an n-type semiconductor layer.
  • the first semiconductor region 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and forms the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • the first semiconductor region 6 (substrate) has the off direction and off angle described above.
  • the first semiconductor region 6 may have a thickness of 10 ⁇ m or more and 500 ⁇ m or less.
  • the thickness of the first semiconductor region 6 may have a value that belongs to at least one of the following ranges: 10 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 300 ⁇ m or less, 300 ⁇ m or more and 400 ⁇ m or less, and 400 ⁇ m or more and 500 ⁇ m or less.
  • the semiconductor device 1A includes an n-type second semiconductor region 7 formed in a surface layer portion of the first main surface 3 of the chip 2.
  • the second semiconductor region 7 may be referred to as a "semiconductor layer,” a “second semiconductor layer,” a “drift region,” or the like.
  • the second semiconductor region 7 has an n-type impurity concentration less than the n-type impurity concentration of the first semiconductor region 6.
  • the n-type impurity concentration of the second semiconductor region 7 may be not less than 1 ⁇ 10 14 cm -3 and not more than 1 ⁇ 10 18 cm -3 .
  • the second semiconductor region 7 is formed in a layer extending along the first main surface 3, and is electrically connected to the first semiconductor region 6.
  • the second semiconductor region 7 is exposed from the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • the second semiconductor region 7 is made of an n-type semiconductor layer.
  • the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) containing SiC single crystal (semiconductor single crystal), and forms the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • the second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above. It is preferable that the second semiconductor region 7 has a thickness less than the thickness of the first semiconductor region 6. The thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6.
  • the thickness of the second semiconductor region 7 may be 5 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the second semiconductor region 7 may have a value that belongs to at least one of the following ranges: 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 25 ⁇ m or less, 25 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 35 ⁇ m or less, 35 ⁇ m or more and 40 ⁇ m or less, 40 ⁇ m or more and 45 ⁇ m, and 45 ⁇ m or more and 50 ⁇ m or less.
  • the semiconductor device 1A includes a first surface portion 8, a second surface portion 9, and first to fourth connection surface portions 10A to 10D formed on the first main surface 3.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D define a mesa 11 on the first main surface 3.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D may be considered to be components of the chip 2 (first main surface 3).
  • the first surface portion 8 may be referred to as the "active surface”
  • the second surface portion 9 may be referred to as the “outer surface”
  • the first to fourth connecting surface portions 10A to 10D may be referred to as “connecting surfaces”
  • the mesa 11 may be referred to as the "active mesa”.
  • the first surface portion 8 is formed at a distance inward from the periphery (first to fourth side faces 5A to 5D) of the first main surface 3.
  • the first surface portion 8 has a flat surface extending horizontally, and is formed by a c-plane (Si-plane).
  • the first surface portion 8 is formed in a quadrangle shape having four sides parallel to the first to fourth side faces 5A to 5D in a plan view. It is preferable that the planar area of the first surface portion 8 is 50% to 90% of the planar area of the first main surface 3.
  • the second surface portion 9 is located on the peripheral side of the first main surface 3 relative to the first surface portion 8, and is recessed from the height position of the first surface portion 8 in the thickness direction of the chip 2 (towards the second main surface 4).
  • the second surface portion 9 extends in a band shape along the first surface portion 8 in a plan view, and is formed in a ring shape (specifically, a square ring shape) surrounding the first surface portion 8.
  • the second surface portion 9 is connected to the first to fourth side surfaces 5A to 5D.
  • the second surface 9 is formed approximately parallel to the first surface 8, and has a flat surface extending horizontally.
  • the second surface 9 is formed by the c-plane (Si-plane).
  • the second surface 9 is formed in the second semiconductor region 7 with a space therebetween from the first semiconductor region 6. In other words, the second surface 9 is recessed to a depth less than the thickness of the second semiconductor region 7, exposing the second semiconductor region 7.
  • the second surface portion 9 has a depth of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second surface portion 9 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second surface portion 9 is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9.
  • the first connection surface portion 10A is located on the first side surface 5A side
  • the second connection surface portion 10B is located on the second side surface 5B side
  • the third connection surface portion 10C is located on the third side surface 5C side
  • the fourth connection surface portion 10D is located on the fourth side surface 5D side.
  • the first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y.
  • the third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.
  • the first to fourth connection surface portions 10A to 10D may extend almost vertically between the first surface portion 8 and the second surface portion 9, and define a mesa 11 in the shape of a rectangular prism.
  • the first to fourth connection surface portions 10A to 10D may be inclined obliquely downward from the first surface portion 8 toward the second surface portion 9, and define a mesa 11 in the shape of a truncated rectangular pyramid.
  • the first to fourth connection surface portions 10A to 10D may be inclined at an angle of more than 90° and not more than 135° with respect to the first surface portion 8.
  • the mesa 11 is defined in a protruding shape in the second semiconductor region 7 on the first main surface 3.
  • the mesa 11 is formed only in the second semiconductor region 7, and is not formed in the first semiconductor region 6.
  • the semiconductor device 1A includes an active region 12 set in the chip 2.
  • the active region 12 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 12 is set in the inner part of the chip 2. Specifically, the active region 12 is set in the first surface portion 8.
  • the semiconductor device 1A includes a peripheral region 13 that is set outside the active region 12 in the chip 2.
  • the peripheral region 13 is a region that does not include a device structure (transistor structure Tr).
  • the peripheral region 13 is set on the periphery of the chip 2.
  • the peripheral region 13 is set on the second surface 9.
  • the peripheral region 13 is set in the region between the periphery of the first surface 8 and the periphery of the second surface 9 in a plan view.
  • the semiconductor device 1A includes a plurality of trench-type (trench electrode-type) gate structures 15 formed on the first main surface 3 (first surface portion 8).
  • the gate structures 15 may be referred to as “trench gate structures", “trench structures”, etc.
  • a gate potential is applied to the plurality of gate structures 15 as a control potential.
  • the multiple gate structures 15 are formed on the first surface portion 8 at intervals inward from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D).
  • the multiple gate structures 15 are arranged at intervals in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. In other words, the multiple gate structures 15 are arranged in stripes extending in the second direction Y in a plan view.
  • the multiple gate structures 15 may be arranged with an interval of 0.25 ⁇ m or more and 3 ⁇ m or less.
  • the interval between the gate structures 15 may have a value that belongs to at least one of the following ranges: 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, 2.25 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 2.75 ⁇ m or less, and 2.75 ⁇ m or more and 3 ⁇ m or less.
  • the interval between the gate structures 15 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the multiple gate structures 15 are located within the second semiconductor region 7.
  • the multiple gate structures 15 are formed at intervals from the bottom of the second semiconductor region 7 toward the first main surface 3, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the multiple gate structures 15 are formed approximately perpendicular to the first main surface 3 (first surface portion 8).
  • each of the gate structures 15 has a first side wall 15a on one side in the first direction X (the third side surface 5C side), a second side wall 15b on the other side in the first direction X (the fourth side surface 5D side), and a bottom wall 15c connecting the first side wall 15a and the second side wall 15b.
  • the first sidewall 15a and the second sidewall 15b are each formed by the a-plane ((11-20) plane) of the SiC single crystal.
  • the first sidewall 15a and the second sidewall 15b may each be formed by the m-plane ((1-100) plane) of the SiC single crystal depending on the extension direction of the gate structure 15.
  • the first sidewall 15a and the second sidewall 15b are formed approximately perpendicular to the first main surface 3.
  • the inclination angle (absolute value) of the first side wall 15a (second side wall 15b) based on the vertical line may be 85° or more and 95° or less.
  • the inclination angle of the first side wall 15a (second side wall 15b) may have a value that belongs to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle of the first side wall 15a (second side wall 15b) is preferably 87° or more and 93° or less.
  • the bottom wall 15c is formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom wall 15c extends almost flat along the horizontal direction. Of course, the bottom wall 15c may be curved in an arc shape toward the second main surface 4.
  • the gate structure 15 may have a width of 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the gate structure 15 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, and 1.25 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the gate structure 15 is preferably 0.25 ⁇ m or more and 0.75 ⁇ m or less.
  • the gate structure 15 may have a depth of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the gate structure 15 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the gate structure 15 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the depth of the gate structure 15 is preferably approximately equal to the depth of the second surface portion 9.
  • Each of the multiple gate structures 15 includes a trench 16, an insulating film 17, and a buried electrode 18.
  • the trench 16 is formed in the first main surface 3 (first surface portion 8) and defines the walls of the gate structure 15 (first sidewall 15a, second sidewall 15b, and bottom wall 15c).
  • the insulating film 17 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 17 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 17 includes a silicon oxide film made of an oxide of the chip 2.
  • the insulating film 17 coats the wall surface of the trench 16 in a film-like manner.
  • the insulating film 17 includes a first film portion, a second film portion, and a third film portion.
  • the first film portion coats the first side wall 15a in a film-like manner.
  • the second film portion coats the second side wall 15b in a film-like manner.
  • the third film portion coats the bottom wall 15c in a film-like manner, and is connected to the first film portion and the second film portion.
  • the second membrane portion has a thickness approximately equal to that of the first membrane portion.
  • the third membrane portion has a thickness greater than both the thickness of the first membrane portion and the thickness of the second membrane portion.
  • the thickness of the third membrane portion may be approximately equal to the thickness of the first membrane portion and the thickness of the second membrane portion.
  • the insulating film 17 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the insulating film 17 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the buried electrode 18 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the buried electrode 18 is buried in the trench 16 with the insulating film 17 sandwiched therebetween.
  • the buried electrode 18 has an electrode surface exposed from the trench 16.
  • the electrode surface is located on the bottom wall 15c side relative to the height position of the first main surface 3.
  • the electrode surface has a recess in its inner part that tapers toward the bottom wall 15c side. It is preferable that the bottom of the recess is located on the first main surface 3 side relative to the depth position of the middle part of the trench 16.
  • the semiconductor device 1A includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 (first surface portion 8).
  • a source potential is applied to the plurality of body regions 20 as a second potential (low potential) different from a first potential (high potential).
  • the body regions 20 may be referred to as a "channel region", a "base region”, or the like.
  • the plurality of body regions 20 may have a p-type impurity concentration of 1 ⁇ 10 17 cm -3 or more and 1 ⁇ 10 19 cm -3 or less.
  • the multiple body regions 20 are formed in regions along the multiple gate structures 15. Specifically, the multiple body regions 20 are formed in regions between the multiple gate structures 15, and extend in stripes along the multiple gate structures 15.
  • the body region 20 is formed in a layer extending in the first direction X in a cross-sectional view, and is connected to one or both (both in this embodiment) of the multiple adjacent gate structures 15.
  • the body region 20 faces the buried electrodes 18 of the multiple gate structures 15, with the insulating films 17 of the multiple gate structures 15 sandwiched therebetween.
  • the body region 20 is formed at a distance from the depth position of the second surface 9 to the region on the first surface 8 side.
  • the body region 20 is formed at a distance from the depth position of the bottom wall 15c of the gate structure 15 to the first main surface 3 side.
  • the body region 20 has a bottom located on the bottom wall 15c side of the gate structure 15 with respect to the depth position of the middle part of the gate structure 15.
  • the bottom of the body region 20 is located in the region between the bottom wall 15c of the gate structure 15 and the middle part of the gate structure 15. In other words, the distance between the bottom of the body region 20 and the bottom wall 15c of the gate structure 15 is less than the thickness (depth) of the body region 20.
  • the bottom of the body region 20 is located on the bottom wall 15c side of the gate structure 15 with respect to the bottom of the recess of the buried electrode 18.
  • the bottom of the body region 20 may be located on the first main surface 3 side with respect to the depth position of the middle part of the gate structure 15.
  • the body region 20 may have a thickness of 0.1 ⁇ m or more and 1 ⁇ m or less.
  • the thickness of the body region 20 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.2 ⁇ m or less, 0.2 ⁇ m or more and 0.4 ⁇ m or less, 0.4 ⁇ m or more and 0.6 ⁇ m or less, 0.6 ⁇ m or more and 0.8 ⁇ m or less, and 0.8 ⁇ m or more and 1 ⁇ m or less.
  • the thickness of the body region 20 is preferably 0.3 ⁇ m or more and 0.7 ⁇ m or less.
  • the semiconductor device 1A includes a plurality of n-type source regions 21 formed in a region on the first main surface 3 side with respect to the plurality of body regions 20.
  • the plurality of source regions 21 have an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.
  • the n-type impurity concentration of the plurality of source regions 21 may be not less than 1 ⁇ 10 18 cm ⁇ 3 and not more than 1 ⁇ 10 21 cm ⁇ 3 .
  • the multiple source regions 21 are formed in regions along the multiple gate structures 15 in the surface layer of the multiple body regions 20. Specifically, the multiple source regions 21 are formed in regions between the multiple gate structures 15, and extend in stripes along the multiple gate structures 15.
  • the configuration of one source region 21 will be described below.
  • the source region 21 is formed at a distance from the bottom of the body region 20 toward the first main surface 3.
  • the source region 21 is formed in a layer extending in the first direction X in a cross-sectional view, and is connected to one or both (both in this embodiment) of the adjacent gate structures 15.
  • the source region 21 faces the buried electrodes 18 of the gate structures 15 with the insulating films 17 of the gate structures 15 in between.
  • the source region 21 has a bottom portion located on the bottom wall 15c side of the trench 16 relative to the height position of the electrode surface of the buried electrode 18, and a surface portion located on the first main surface 3 side relative to the height position of the electrode surface of the buried electrode 18.
  • the source region 21 has a portion (bottom portion) that faces the buried electrode 18 across the insulating film 17, and a portion (surface portion) that does not face the buried electrode 18 across the insulating film 17.
  • the bottom of the source region 21 may be located on the first main surface 3 side relative to the depth position of the bottom of the recess of the buried electrode 18.
  • the bottom of the source region 21 may be located on the bottom side of the body region 20 relative to the depth position of the bottom of the recess.
  • the semiconductor device 1A includes a plurality of p-type well regions 22 formed in the chip 2 (second semiconductor region 7).
  • the plurality of well regions 22 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the plurality of well regions 22 may be lower than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the plurality of well regions 22 may be not less than 1 ⁇ 10 16 cm ⁇ 3 and not more than 1 ⁇ 10 20 cm ⁇ 3 .
  • the multiple well regions 22 are formed in the chip 2 (second semiconductor region 7) in regions along the bottom walls 15c of the multiple gate structures 15 at intervals in the first direction X.
  • the multiple well regions 22 are formed in a one-to-one correspondence with the multiple gate structures 15.
  • the multiple well regions 22 are each formed in a strip shape extending along the corresponding gate structure 15 in a plan view, and face the corresponding buried electrode 18 across the corresponding insulating film 17.
  • multiple well regions 22 may be formed in a one-to-many correspondence with one gate structure 15. In this case, the multiple well regions 22 are formed at intervals in the second direction Y.
  • the configuration of one well region 22 is described below.
  • the well region 22 is formed to be wider than the gate structure 15 in a plan view.
  • the well region 22 is formed in a columnar shape extending in the thickness direction (vertical direction Z) of the second semiconductor region 7 in a cross-sectional view.
  • the well region 22 may have a depth that crosses the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall 15c of the gate structure 15.
  • the well region 22 may be formed at a distance from the intermediate portion between the bottom of the second semiconductor region 7 and the bottom wall 15c of the gate structure 15 toward the first main surface 3.
  • the well region 22 is formed at a distance from the bottom of the second semiconductor region 7 toward the first surface portion 8, and faces the first semiconductor region 6 across a portion of the second semiconductor region 7. Of course, the well region 22 may cross the bottom of the second semiconductor region 7 and have a bottom located within the first semiconductor region 6. The well region 22 forms a pn junction with the second semiconductor region 7.
  • the well region 22 has a thickness (depth) greater than the thickness (depth) of the body region 20.
  • the thickness of the well region 22 is the thickness of the well region 22 in the vertical direction Z based on the bottom wall 15c of the gate structure 15. In this embodiment, the thickness of the well region 22 is greater than the depth of the gate structure 15.
  • the thickness of the well region 22 may be less than the depth of the gate structure 15. In this case, the thickness of the well region 22 may be less than the thickness of the body region 20.
  • the well region 22 has an upper end that is aligned with the corner of the bottom wall 15c of the gate structure 15. At the upper end, the well region 22 has a first extension 22a on the first sidewall 15a side and a second extension 22b on the second sidewall 15b side (see FIG. 7).
  • the first extension 22a is drawn out from the region directly below the gate structure 15 to the lower end of the first sidewall 15a.
  • the first extension 22a is formed at a distance from the bottom of the body region 20 toward the bottom wall 15c of the gate structure 15.
  • the first extension 22a faces the buried electrode 18 in the horizontal direction, sandwiching the insulating film 17 therebetween.
  • the first extension 22a may be formed on the bottom wall 15c side of the trench 16 with respect to the depth position of the lower end of the buried electrode 18, and may face only the insulating film 17 (third film portion) in the horizontal direction.
  • the first extension 22a is formed in a tapered shape toward the first main surface 3 (the bottom side of the body region 20) in a cross-sectional view.
  • the second extension 22b is drawn out from the region directly below the gate structure 15 to the lower end of the second sidewall 15b, and faces the first extension 22a across the gate structure 15.
  • the second extension 22b is formed at a distance from the bottom of the body region 20 toward the bottom wall 15c of the gate structure 15.
  • the second extension 22b faces the buried electrode 18 in the horizontal direction, with the insulating film 17 in between.
  • the second extension 22b may be formed on the bottom wall 15c side of the trench 16 with respect to the depth position of the lower end of the buried electrode 18, and may face only the insulating film 17 (third film portion) in the horizontal direction.
  • the second extension 22b is formed in a tapered shape toward the first main surface 3 (the bottom side of the body region 20) in a cross-sectional view.
  • the well region 22 has one or more (multiple in this embodiment) first bulge portions 22c.
  • first bulge portions 22c In the attached drawings, a well region 22 having four first bulge portions 22c is illustrated as an example. The number of first bulge portions 22c is adjusted appropriately by adjusting the process conditions.
  • the multiple first bulge portions 22c are each formed by a portion of the well region 22 whose width in the horizontal direction (first direction X) gradually increases and decreases in the thickness direction, and are formed in multiple stages from the bottom wall 15c of the gate structure 15 toward the bottom of the second semiconductor region 7.
  • the multiple first bulges 22c extend in an arc shape (circular arc) from the region directly below the gate structure 15 to both sides of the gate structure 15.
  • the single first bulge 22c may be formed in the middle of the well region 22 so as to extend in an arc shape (circular arc) to both sides of the gate structure 15.
  • the semiconductor device 1A includes a plurality of p-type high-concentration well regions 23 formed in each of the plurality of well regions 22.
  • the plurality of high-concentration well regions 23 are regions in which the p-type impurity concentration of the well region 22 is increased, and have a p-type impurity concentration higher than the p-type impurity concentration of the well region 22.
  • the high-concentration well regions 23 may be regarded as a high-concentration portion of the well region 22.
  • the p-type impurity concentration of the plurality of high-concentration well regions 23 may be not less than 1 ⁇ 10 18 cm ⁇ 3 and not more than 1 ⁇ 10 20 cm ⁇ 3 .
  • the multiple high-concentration well regions 23 are formed in a one-to-one correspondence with the multiple well regions 22.
  • the multiple high-concentration well regions 23 are each formed in a region along the bottom wall 15c of the corresponding gate structure 15.
  • the multiple high-concentration well regions 23 are each formed in a strip shape extending along the corresponding gate structure 15 (well region 22) in a plan view, and face the corresponding buried electrode 18 with the corresponding insulating film 17 in between.
  • multiple high-concentration well regions 23 may be formed in a one-to-many correspondence with one well region 22.
  • the multiple high-concentration well regions 23 are formed at intervals in the second direction Y within one well region 22.
  • the configuration of one high-concentration well region 23 is described below.
  • the high-concentration well region 23 is formed at a distance from the bottom of the well region 22 toward the bottom wall 15c of the gate structure 15. It is preferable that the high-concentration well region 23 has a bottom located toward the bottom wall 15c of the gate structure 15 with respect to the depth position of the middle part of the well region 22.
  • the bottom of the high-concentration well region 23 is defined by a concentration transition portion where the p-type impurity concentration gradually decreases toward the bottom side of the well region 22.
  • the bottom of the high-concentration well region 23 may be located on the bottom side of the well region 22 with respect to the depth position of the middle part of the well region 22.
  • the high-concentration well region 23 is formed narrower than the well region 22.
  • the high-concentration well region 23 is formed narrower than the gate structure 15.
  • the high-concentration well region 23 may be formed wider than the gate structure 15 and extend out on both sides of the gate structure 15.
  • the high-concentration well region 23 has a thickness (depth) less than the depth of the gate structure 15.
  • the thickness of the high-concentration well region 23 is the thickness in the vertical direction Z of the high-concentration well region 23 based on the bottom wall 15c of the gate structure 15.
  • the thickness of the high-concentration well region 23 is less than the thickness of the body region 20.
  • the thickness of the high-concentration well region 23 may be greater than the thickness of the body region 20 or greater than the depth of the gate structure 15.
  • the semiconductor device 1A includes a plurality of n-type high concentration regions 24 formed in the chip 2 (second semiconductor region 7) in regions below the plurality of body regions 20.
  • the plurality of high concentration regions 24 are regions (low resistance regions) in which the n-type impurity concentration of the second semiconductor region 7 is increased, and have a higher n-type impurity concentration than the n-type impurity concentration of the second semiconductor region 7.
  • the plurality of high concentration regions 24 may be regarded as high concentration portions of the second semiconductor region 7.
  • the n-type impurity concentration of the multiple high concentration regions 24 may be not less than 1 ⁇ 10 16 cm ⁇ 3 and not more than 1 ⁇ 10 19 cm ⁇ 3 .
  • the n-type impurity concentration of the multiple high concentration regions 24 can be appropriately compared by comparing it with the n-type impurity concentration on the bottom side of the second semiconductor region 7.
  • the high concentration region 24 may be referred to as a “high concentration drift region”.
  • the multiple high concentration regions 24 are formed in the regions below the multiple body regions 20 and along the multiple gate structures 15. Specifically, the multiple high concentration regions 24 are formed in the regions between the multiple gate structures 15 in the thickness range between the bottom walls 15c of the multiple gate structures 15 and the bottoms of the multiple body regions 20. The multiple high concentration regions 24 each extend in a band shape along the multiple gate structures 15 in a plan view.
  • the high concentration region 24 is formed in a layer extending in the first direction X in a cross-sectional view, and is connected to one or both (both in this embodiment) of the multiple adjacent gate structures 15.
  • the high concentration region 24 faces the buried electrodes 18 of the multiple gate structures 15, sandwiching the insulating films 17 of the multiple gate structures 15 therebetween.
  • the high concentration region 24 faces the source region 21 in the thickness direction, sandwiching a portion of the body region 20 therebetween.
  • the high concentration region 24 faces the source region 21 in a one-to-one correspondence in the thickness direction.
  • the high concentration region 24 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a portion of the second semiconductor region 7. It is preferable that the high concentration region 24 is formed at a distance from the middle of the second semiconductor region 7 toward the first main surface 3.
  • the high concentration region 24 has a bottom located on the first main surface 3 side relative to the depth position of the bottom wall 15c of the gate structure 15.
  • the bottom of the high concentration region 24 is defined by a concentration transition section where the n-type impurity concentration gradually decreases toward the bottom side of the second semiconductor region 7.
  • the high concentration region 24 is formed at a distance from the depth position of the bottom wall 15c of the gate structure 15 toward the first main surface 3.
  • the high concentration region 24 is formed in a thickness range between the body region 20 and the well region 22, and separates the well region 22 from the body region 20. In other words, the high concentration region 24 suppresses an increase in the p-type impurity concentration in the portion along the sidewall (first sidewall 15a and second sidewall 15b) of the gate structure 15.
  • the high concentration region 24 has a thickness (depth) in the vertical direction Z that is less than the thickness (depth) of the body region 20.
  • the thickness of the high concentration region 24 may be 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • the thickness of the high concentration region 24 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.15 ⁇ m or less, 0.15 ⁇ m or more and 0.2 ⁇ m or less, 0.2 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.3 ⁇ m or less, 0.3 ⁇ m or more and 0.35 ⁇ m or less, 0.35 ⁇ m or more and 0.4 ⁇ m or less, 0.4 ⁇ m or more and 0.45 ⁇ m or less, and 0.45 ⁇ m or more and 0.5 ⁇ m or less.
  • the thickness of the high concentration region 24 is preferably 0.1 ⁇ m or more and 0.3 ⁇ m or less.
  • the distance in the vertical direction Z between the bottom wall 15c of the gate structure 15 and the bottom of the high concentration region 24 may be 0 ⁇ m or more and 0.4 ⁇ m or less.
  • the distance may have a value that belongs to at least one of the following ranges: 0 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.15 ⁇ m or less, 0.15 ⁇ m or more and 0.2 ⁇ m or less, 0.2 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.3 ⁇ m or less, 0.3 ⁇ m or more and 0.35 ⁇ m or less, and 0.35 ⁇ m or more and 0.4 ⁇ m or less.
  • the distance is preferably 0.05 ⁇ m or more and 0.2 ⁇ m or less.
  • the bottom of the high concentration region 24 may be located on the bottom side of the second semiconductor region 7 relative to the bottom wall 15c of the gate structure 15.
  • the current density in the vicinity of the bottom wall 15c of the gate structure 15 is increased, and attention must be paid to electric field concentration in the vicinity of the bottom wall 15c of the gate structure 15 (especially in the vicinity of the corners of the bottom wall 15c).
  • the multiple high concentration regions 24 may have approximately the same n-type impurity concentration, or may have different n-type impurity concentrations.
  • the n-type impurity concentration of the other high concentration region 24 may be different from the n-type impurity concentration of the one high concentration region 24.
  • the n-type impurity concentration of the other high concentration region 24 may be higher than the n-type impurity concentration of the one high concentration region 24, or may be lower than the n-type impurity concentration of the one high concentration region 24.
  • the semiconductor device 1A includes a plurality of n-type medium concentration regions 25 formed in the chip 2 (second semiconductor region 7) in a region below a plurality of high concentration regions 24.
  • the plurality of medium concentration regions 25 are regions (low resistance regions) in which the n-type impurity concentration of the second semiconductor region 7 is increased, and have an n-type impurity concentration that is higher than the n-type impurity concentration of the second semiconductor region 7 and lower than the n-type impurity concentration of the high concentration region 24.
  • the plurality of medium concentration regions 25 may be regarded as high concentration portions of the second semiconductor region 7.
  • the n-type impurity concentration of the plurality of medium concentration regions 25 may be not less than 1 ⁇ 10 15 cm ⁇ 3 and not more than 1 ⁇ 10 17 cm ⁇ 3 .
  • the n-type impurity concentration of the plurality of medium concentration regions 25 can be appropriately compared by comparing it with the n-type impurity concentration on the bottom side of the second semiconductor region 7.
  • the medium concentration region 25 may be referred to as a “medium concentration drift region”.
  • the multiple medium concentration regions 25 are each formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom of the multiple high concentration regions 24 in the region between the multiple gate structures 15.
  • the multiple medium concentration regions 25 each have a portion interposed in the region between the multiple well regions 22.
  • the multiple medium concentration regions 25 each have a portion interposed in the region of the multiple gate structures 15.
  • the multiple medium concentration regions 25 each extend in a strip shape along the multiple gate structures 15 in a plan view.
  • the multiple medium concentration regions 25 are connected to one or both (in this embodiment, both) of two adjacent well regions 22.
  • the configuration of one medium concentration region 25 is described below.
  • the medium concentration region 25 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the medium concentration region 25 has an upper end located above the depth position of the bottom wall 15c of the gate structure 15.
  • the upper end of the medium concentration region 25 is located in a region between multiple gate structures 15 and faces the gate structure 15 across the upper end (first extension 22a and second extension 22b) of the well region 22.
  • the upper end of the medium concentration region 25 may have a portion connected to the gate structure 15.
  • the medium concentration region 25 has a bottom that is located below the depth position of the bottom wall 15c of the gate structure 15. Specifically, the bottom of the medium concentration region 25 is formed at a distance from the bottom of the well region 22 toward the first main surface 3. It is preferable that the bottom of the medium concentration region 25 is located closer to the bottom of the well region 22 than the bottom of the high concentration well region 23.
  • the bottom of the medium concentration region 25 may be located closer to the bottom of the second semiconductor region 7 than the middle part of the well region 22.
  • the bottom of the medium concentration region 25 may be located closer to the bottom wall 15c of the gate structure 15 than the middle part of the well region 22.
  • the semiconductor device 1A includes a plurality of channel regions 26 formed between the plurality of source regions 21 and the plurality of high concentration regions 24 in the plurality of body regions 20.
  • the inversion and non-inversion of the plurality of channel regions 26 is controlled by the gate structure 15.
  • the plurality of channel regions 26 form current paths connecting the plurality of source regions 21 and the plurality of high concentration regions 24 along the sidewalls (first sidewall 15a and second sidewall 15b) of the plurality of gate structures 15 in the plurality of body regions 20.
  • the semiconductor device 1A includes a plurality of p-type first contact regions 27 formed in regions along the plurality of gate structures 15 in the surface layer portion of the first main surface 3 (first surface portion 8).
  • the multiple first contact regions 27 have a p-type impurity concentration higher than the p-type impurity concentration of the multiple body regions 20.
  • the p-type impurity concentration of the multiple first contact regions 27 is higher than the p-type impurity concentration of the multiple well regions 22.
  • the p-type impurity concentration of the multiple first contact regions 27 may be not less than 1 ⁇ 10 17 cm ⁇ 3 and not more than 1 ⁇ 10 19 cm ⁇ 3 .
  • the multiple first contact regions 27 are formed in the regions between the multiple gate structures 15. That is, the multiple first contact regions 27 are formed on both sides of the multiple gate structures 15.
  • the multiple first contact regions 27 are arranged at intervals in the second direction Y along the multiple gate structures 15, and are each formed in a strip shape extending in the second direction Y.
  • the multiple first contact regions 27 overlap the multiple body regions 20, increasing the p-type impurity concentration of the multiple body regions 20.
  • the other first contact region 27 faces the first contact region 27 across the gate structure 15.
  • the multiple first contact regions 27 are arranged in a matrix as a whole in a plan view.
  • the length and spacing of the multiple first contact regions 27 are adjusted appropriately according to the channel area to be achieved.
  • the channel area corresponds to the total area of the multiple source regions 21.
  • the length of the first contact regions 27 in the second direction Y may be greater than the width of the gate structure 15 in the first direction X.
  • the length of the first contact regions 27 may be less than the width of the gate structure 15.
  • the first ratio of the length of the first contact region 27 to the width of the gate structure 15 may be 0.5 or more and 10 or less.
  • the first ratio may have a value that belongs to at least one of the following ranges: 0.5 or more and 1 or less, 1 or more and 2.5 or less, 2.5 or more and 5 or less, 5 or more and 7.5 or less, and 7.5 or more and 10 or less.
  • the first ratio is preferably 1 or more and 5 or less.
  • the second ratio of the spacing of the first contact regions 27 to the length of the first contact regions 27 may be 1 or more and 50 or less.
  • the second ratio may have a value that belongs to at least one of the following ranges: 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, 15 or more and 20 or less, 20 or more and 25 or less, 25 or more and 30 or less, 30 or more and 35 or less, 35 or more and 40 or less, 40 or more and 45 or less, and 45 or more and 50 or less.
  • the configuration of one first contact region 27 will be described below.
  • the first contact region 27 is formed in a layer extending horizontally along the first main surface 3, and is connected to one or both (in this embodiment, both) of the adjacent gate structures 15.
  • the first contact region 27 faces the buried electrodes 18 of the multiple gate structures 15, sandwiching the insulating films 17 of the multiple gate structures 15 therebetween.
  • the first contact region 27 has a thickness greater than the thickness of the source region 21, and has a bottom located closer to the bottom of the second semiconductor region 7 than the bottom of the source region 21.
  • the bottom of the first contact region 27 is located closer to the bottom of the body region 20 than the depth position of the bottom of the recess of the buried electrode 18.
  • the first contact region 27 has a thickness greater than the thickness of the body region 20, and has a bottom located closer to the bottom of the second semiconductor region 7 than the bottom of the body region 20.
  • the bottom of the first contact region 27 is defined by a concentration transition portion where the p-type impurity concentration gradually decreases toward the bottom of the second semiconductor region 7.
  • the bottom of the first contact region 27 may be located closer to the first major surface 3 than the depth position of the bottom wall 15c of the gate structure 15.
  • the first contact region 27 may have a thickness less than the thickness of the body region 20, and may have a bottom located closer to the first major surface 3 than the bottom of the body region 20.
  • the first contact region 27 may face the high concentration region 24 across a portion of the body region 20.
  • the bottom of the first contact region 27 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 15c of the gate structure 15.
  • the first contact region 27 overlaps part or all of the high concentration region 24 in a cross-sectional view.
  • the first contact region 27 replaces the n-type impurity concentration of part or all of the high concentration region 24 with a p-type impurity concentration. Therefore, the p-type impurity concentration at the bottom (lower end) of the first contact region 27 is reduced by the amount of the n-type impurity concentration of the high concentration region 24.
  • the first contact region 27 has a bottom that crosses the bottom of the high concentration region 24 and is located within the medium concentration region 25. Therefore, the first contact region 27 also replaces the n-type impurity concentration of a portion of the medium concentration region 25 with a p-type impurity concentration. It is preferable that the bottom of the first contact region 27 is located closer to the first main surface 3 than the depth position of the middle part of the well region 22.
  • the bottom of the first contact region 27 overlaps with the upper end of the well region 22 (first extension 22a and second extension 22b) in a region closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 15c of the gate structure 15. As a result, the first contact region 27 electrically connects the well region 22 to the body region 20.
  • the first contact region 27 has a high concentration portion 27a on the first main surface 3 side and a low concentration portion 27b on the bottom side of the second semiconductor region 7.
  • the high concentration portion 27a is formed at least closer to the first main surface 3 than the depth position of the bottom wall 15c of the gate structure 15, and forms the main body of the first contact region 27.
  • the high concentration portion 27a extends horizontally in a layer along the first main surface 3.
  • the low concentration portion 27b is formed on the bottom side of the second semiconductor region 7 relative to the high concentration portion 27a, and forms the bottom (concentration transition portion) of the first contact region 27.
  • the low concentration portion 27b is also a portion where the p-type impurity concentration is reduced by the n-type impurity concentration of the high concentration region 24.
  • the low concentration portion 27b has a thickness less than the thickness of the high concentration portion 27a, and extends horizontally in a layer along the high concentration portion 27a.
  • the low concentration portion 27b crosses the depth position of the bottom wall 15c of the gate structure 15 in the thickness direction.
  • the low concentration portion 27b has a portion located closer to the first main surface 3 than the depth position of the bottom wall 15c of the gate structure 15, and a portion located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 15c of the gate structure 15.
  • the low concentration portion 27b overlaps the upper ends of the multiple well regions 22 and is electrically connected to the multiple well regions 22.
  • the low concentration portion 27b may be located only on the first main surface 3 side from the depth position of the bottom wall 15c of the gate structure 15 depending on the thickness of the high concentration portion 27a.
  • the low concentration portion 27b may be located only on the bottom side of the second semiconductor region 7 from the depth position of the bottom wall 15c of the gate structure 15 depending on the thickness of the high concentration portion 27a.
  • the semiconductor device 1A includes a plurality of p-type second contact regions 28 formed in regions along the bottom walls 15c of the plurality of gate structures 15 in the chip 2.
  • the plurality of second contact regions 28 have a p-type impurity concentration higher than the p-type impurity concentration of the plurality of body regions 20.
  • the p-type impurity concentration of the plurality of second contact regions 28 is higher than the p-type impurity concentration of the plurality of well regions 22.
  • the p-type impurity concentration of the second contact regions 28 may be not less than 1 ⁇ 10 18 cm ⁇ 3 and not more than 1 ⁇ 10 20 cm ⁇ 3 .
  • the p-type impurity concentration of the second contact regions 28 is preferably approximately equal to the p-type impurity concentration of the first contact regions 27.
  • the second contact regions 28 are formed in a one-to-many correspondence with the bottom walls 15c of the gate structures 15.
  • the second contact regions 28 are each interposed in the region between the first contact regions 27 adjacent to each other in the first direction X in a plan view. In other words, the second contact regions 28 are positioned on the same straight line as the first contact regions 27 in the first direction X.
  • the second contact regions 28 are each formed in a band shape extending along the corresponding gate structure 15 in a plan view, and face the buried electrode 18 across the insulating film 17.
  • the length of the second contact regions 28 is approximately equal to the length of the first contact regions 27.
  • the spacing between the second contact regions 28 is approximately equal to the spacing between the first contact regions 27.
  • the configuration of one second contact region 28 will be described below.
  • the second contact region 28 is formed in one corresponding well region 22.
  • the second contact region 28 overlaps with the high concentration well region 23 and is electrically connected to the high concentration well region 23 within the well region 22.
  • the second contact region 28 is formed at a distance inward from the periphery of the well region 22.
  • the second contact regions 28 are formed at a distance from the bottom of the well region 22 toward the bottom wall 15c of the gate structure 15, and face the bottom of the second semiconductor region 7 across a portion of the well region 22.
  • the second contact regions 28 are each formed in a columnar shape extending in the thickness direction (vertical direction Z) of the second semiconductor region 7 in a cross-sectional view.
  • the second contact region 28 has a bottom that is located closer to the bottom of the well region 22 than the thickness position of the middle part of the well region 22.
  • the bottom of the second contact region 28 may be located closer to the bottom wall 15c of the gate structure 15 than the thickness position of the middle part of the well region 22.
  • the bottom of the second contact region 28 is located closer to the bottom wall 15c of the gate structure 15 than the bottom of the medium concentration region 25.
  • the bottom of the second contact region 28 may be located closer to the bottom of the second semiconductor region 7 than the bottom of the medium concentration region 25.
  • the second contact region 28 may be formed to cross the bottom of the well region 22 and have a bottom located within the second semiconductor region 7.
  • the second contact region 28 has an upper end that is aligned with a corner of the bottom wall 15c of the gate structure 15.
  • the second contact region 28 is electrically connected to the multiple first contact regions 27 at its upper end.
  • the second contact region 28 electrically connects the well region 22 and the high-concentration well region 23 to the body region 20 via the multiple first contact regions 27.
  • the second contact region 28 has a first extension 28a on the first sidewall 15a side and a second extension 28b on the second sidewall 15b side.
  • the first extension 28a is drawn out from the region directly below the gate structure 15 to the lower end of the first sidewall 15a.
  • the first extension 28a faces the buried electrode 18 in the horizontal direction, sandwiching the insulating film 17 therebetween.
  • the first extension 28a is connected to the first contact region 27 in a region along the first sidewall 15a. Specifically, the first extension 28a is connected to both the high concentration portion 27a and the low concentration portion 27b of the first contact region 27.
  • the second extension 28b is drawn out from the region directly below the gate structure 15 to the lower end of the second sidewall 15b, and faces the first extension 28a across the gate structure 15.
  • the second extension 28b faces the buried electrode 18 in the horizontal direction, across the insulating film 17.
  • the second extension 28b is connected to the first contact region 27 in a region along the second sidewall 15b. Specifically, the second extension 28b is connected to both the high concentration portion 27a and the low concentration portion 27b of the first contact region 27.
  • the second contact region 28 has one or more (multiple in this embodiment) second bulge portions 28c.
  • a second contact region 28 having two second bulge portions 28c is illustrated as an example. The number of second bulge portions 28c is adjusted as appropriate by adjusting the process conditions.
  • the multiple second bulges 28c are each formed by a portion of the second contact region 28 whose width in the horizontal direction (first direction X) gradually increases or decreases in the thickness direction, and are formed in multiple steps from the bottom wall 15c of the gate structure 15 toward the bottom of the second semiconductor region 7.
  • the multiple second bulges 28c extend in an arc shape (circular arc) from the region directly below the gate structure 15 to both sides of the gate structure 15.
  • the single second bulge 28c may be formed in the middle of the second contact region 28 so as to extend in an arc shape (circular arc) to both sides of the gate structure 15.
  • the semiconductor device 1A includes a main surface insulating film 30 that covers the first main surface 3.
  • the main surface insulating film 30 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D.
  • the main surface insulating film 30 is connected to the insulating films 17 of the multiple gate structures 15 on the first surface portion 8, and exposes the buried electrodes 18 of the multiple gate structures 15.
  • the main surface insulating film 30 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the main surface insulating film 30 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the main surface insulating film 30 includes a silicon oxide film made of an oxide of the chip 2.
  • the semiconductor device 1A includes an insulating interlayer film 31 that covers the main surface insulating film 30.
  • the interlayer film 31 may be called an "insulating film,” an “interlayer insulating film,” an “intermediate insulating film,” or the like.
  • the interlayer film 31 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D, sandwiching the main surface insulating film 30 therebetween.
  • the interlayer film 31 covers a plurality of gate structures 15 (buried electrodes 18) on the first surface portion 8.
  • the interlayer film 31 is continuous with the first to fourth side faces 5A to 5D at the periphery of the second surface 9.
  • the interlayer film 31 may be formed at a distance inward from the periphery of the second surface 9, exposing the second semiconductor region 7 from the periphery of the second surface 9.
  • the interlayer film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the interlayer film 31 includes a silicon oxide film.
  • the interlayer film 31 may have a thickness of 0.5 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the interlayer film 31 may have a value that falls within at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the semiconductor device 1A includes a plurality of source openings 32 formed in an interlayer film 31.
  • the plurality of source openings 32 are formed in the regions between the plurality of gate structures 15, respectively, and expose the plurality of source regions 21 and the plurality of first contact regions 27.
  • the plurality of source openings 32 extend in a band shape along the plurality of gate structures 15 in the second direction Y.
  • each of the multiple source openings 32 has an opening end curved in an arc shape.
  • the multiple source openings 32 may be formed at intervals in the second direction Y.
  • the multiple source openings 32 may be formed in a square shape, a rectangular shape (strip shape), a circular shape, etc. in a plan view.
  • the semiconductor device 1A includes a plurality of gate openings 33 formed in the interlayer film 31 (see FIG. 3).
  • the plurality of gate openings 33 selectively expose both ends of a corresponding one of the gate structures 15.
  • each of the multiple gate openings 33 exposes both ends of the buried electrode 18 of a corresponding gate structure 15. It is preferable that each of the multiple gate openings 33 has an opening end that is curved in an arc, similar to the source opening 32.
  • the multiple gate openings 33 may be formed in a square shape, a rectangular shape (strip shape), a circle shape, etc., when viewed in a plan view.
  • the semiconductor device 1A includes a source electrode 35 disposed on the first main surface 3.
  • the source electrode 35 is a terminal electrode to which a source potential is applied from the outside.
  • the source electrode 35 may also be referred to as a "source pad electrode,” a “first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” etc.
  • the source electrode 35 is disposed on a portion of the interlayer film 31 that covers the first surface portion 8.
  • the source electrode 35 has a first pad portion 35a, a second pad portion 35b, and a third pad portion 35c.
  • the first pad portion 35a has a relatively large planar area and forms the main body of the source electrode 35.
  • the first pad portion 35a is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the fourth side surface 5D relative to the center of the first surface portion 8.
  • the second pad portion 35b has a planar area less than that of the first pad portion 35a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 35a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C.
  • the third pad portion 35c has a planar area less than that of the first pad portion 35a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 35a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 35b in the second direction Y.
  • the plane area of the third pad portion 35c may be approximately equal to the plane area of the second pad portion 35b. Of course, the plane area of the third pad portion 35c may be greater than the plane area of the second pad portion 35b, or may be less than the plane area of the second pad portion 35b. Either or both of the second pad portion 35b and the third pad portion 35c may be used as a terminal portion for monitoring a current.
  • the source electrode 35 does not necessarily have to have both the second pad portion 35b and the third pad portion 35c at the same time.
  • the source electrode 35 may have only one of the second pad portion 35b and the third pad portion 35c.
  • the source electrode 35 may be composed of only the first pad portion 35a and may not have both the second pad portion 35b and the third pad portion 35c.
  • the source electrode 35 penetrates the multiple source openings 32 from above the interlayer film 31 and is connected to the first main surface 3 (first surface portion 8) within the multiple source openings 32.
  • the source electrode 35 is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 within the multiple source openings 32.
  • the source electrode 35 has a layered structure including a lower electrode film 36 and a main electrode film 37, which are layered in this order from the chip 2 side.
  • the lower electrode film 36 has a layered structure including a first electrode film 38 and a second electrode film 39.
  • the first electrode film 38 includes a Ti film
  • the second electrode film 39 includes a TiN film.
  • the lower electrode film 36 does not necessarily have to have a layered structure, and may have a single layer structure consisting of either the first electrode film 38 (Ti film) or the second electrode film 39 (TiN film).
  • the first electrode film 38 has a thickness less than the thickness of the interlayer film 31.
  • the thickness of the first electrode film 38 may be 10 nm or more and 100 nm or less.
  • the thickness of the first electrode film 38 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the second electrode film 39 has a thickness less than the thickness of the interlayer film 31.
  • the thickness of the second electrode film 39 is preferably greater than the thickness of the first electrode film 38.
  • the thickness of the second electrode film 39 may be 50 nm or more and 200 nm or less.
  • the thickness of the second electrode film 39 may have a value belonging to at least one of the following ranges: 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.
  • the first electrode film 38 collectively covers the area of the interlayer film 31 where the multiple source openings 32 are formed, and extends from above the interlayer film 31 into the multiple source openings 32.
  • the first electrode film 38 has a portion that covers the insulating main surface of the interlayer film 31 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 32 in a film-like manner, and a portion that covers the first main surface 3 in the multiple source openings 32 in a film-like manner.
  • the first electrode film 38 directly covers the insulating main surface of the interlayer film 31 and faces the gate structure 15 across the interlayer film 31.
  • the first electrode film 38 extends in an arc shape from above the insulating main surface of the interlayer film 31 following the opening edge of the source opening 32, and covers the wall surface of the source opening 32 in a film-like manner.
  • the first electrode film 38 covers the first main surface 3 (first surface portion 8) in the source opening 32 in a film-like manner, and is mechanically and electrically connected to the multiple source regions 21 and multiple first contact regions 27 on the first main surface 3.
  • the second electrode film 39 directly covers the first electrode film 38.
  • the second electrode film 39 collectively covers the area of the interlayer film 31 in which the multiple source openings 32 are formed, sandwiching the first electrode film 38 between them, and penetrates into the multiple source openings 32 from above the interlayer film 31.
  • the second electrode film 39 has a portion that sandwiches the first electrode film 38 to cover the insulating main surface of the interlayer film 31 in a film-like manner, a portion that sandwiches the first electrode film 38 to cover the wall surfaces of the multiple source openings 32 in a film-like manner, and a portion that sandwiches the first electrode film 38 within the multiple source openings 32 to cover the first main surface 3 in a film-like manner.
  • the second electrode film 39 covers the insulating main surface of the interlayer film 31 with the first electrode film 38 in between, and faces the gate structure 15 with the interlayer film 31 and the first electrode film 38 in between.
  • the second electrode film 39 covers the opening end of the source opening 32 in an arc shape with the first electrode film 38 in between, and covers the wall surface of the source opening 32 in a film shape with the first electrode film 38 in between.
  • the second electrode film 39 covers the first main surface 3 (first surface portion 8) in a film shape within the source opening 32 with the first electrode film 38 in between, and is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 via the first electrode film 38.
  • the main electrode film 37 contains a conductive material different from that of the lower electrode film 36 (the first electrode film 38 and the second electrode film 39).
  • the main electrode film 37 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the main electrode film 37 has a thickness greater than the thickness (total thickness) of the lower electrode film 36.
  • the thickness of the main electrode film 37 is preferably greater than the thickness of the interlayer film 31.
  • the thickness of the main electrode film 37 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the main electrode film 37 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the main electrode film 37 directly covers the lower electrode film 36 (second electrode film 39).
  • the main electrode film 37 backfills the multiple source openings 32, and collectively covers the area of the interlayer film 31 in which the multiple source openings 32 are formed.
  • the main electrode film 37 has a portion that covers the insulating main surface of the interlayer film 31 with the lower electrode film 36 in between, a portion that covers the wall surfaces of the multiple source openings 32 with the lower electrode film 36 in between, and a portion that covers the first main surface 3 with the lower electrode film 36 in between.
  • the main electrode film 37 covers the insulating main surface of the interlayer film 31 with the lower electrode film 36 in between, and faces the gate structure 15 with the interlayer film 31 and the lower electrode film 36 in between.
  • the main electrode film 37 covers the opening end of the source opening 32 with the lower electrode film 36 in between.
  • the main electrode film 37 covers the first main surface 3 (first surface portion 8) within the source opening 32 with the lower electrode film 36 in between, and is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 via the lower electrode film 36.
  • the semiconductor device 1A includes a gate electrode 40 disposed on the first main surface 3.
  • the gate electrode 40 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate electrode 40 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the gate electrode 40 includes a lower electrode film 36 and a main electrode film 37, which are stacked in this order from the chip 2 side, similar to the source electrode 35.
  • the gate electrode 40 is disposed on a portion of the interlayer film 31 that covers the first surface portion 8, spaced apart from the source electrode 35.
  • the gate electrode 40 is disposed in a region on the third side surface 5C side of the first pad portion 35a, and faces the first pad portion 35a in the first direction X.
  • the gate electrode 40 is also interposed in a region between the second pad portion 35b and the third pad portion 35c, and faces both the second pad portion 35b and the third pad portion 35c in the second direction Y.
  • the gate electrode 40 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate electrode 40 has a planar area less than the planar area of the source electrode 35.
  • the gate electrode 40 has a planar area less than the planar area of the first pad portion 35a.
  • the gate electrode 40 may have a planar area less than the planar area of the second pad portion 35b (third pad portion 35c).
  • the gate electrode 40 partially faces the multiple gate structures 15 across the interlayer film 31. Specifically, the gate electrode 40 is disposed inwardly from both ends of the multiple gate structures 15 with a space therebetween, and faces the inner parts (middle parts in this embodiment) of the multiple gate structures 15 across the interlayer film 31.
  • the gate electrode 40 does not have a direct electrical connection to the multiple gate structures 15.
  • the gate electrode 40 may be electrically connected to the multiple gate structures 15 via multiple gate openings 33.
  • the portion of the multiple gate structures 15 that is located at the gate electrode 40 may be removed.
  • the gate electrode 40 may face the body region 20 with the main surface insulating film 30 and the interlayer film 31 sandwiched therebetween.
  • the semiconductor device 1A includes a gate wiring 41 extending from the gate electrode 40 onto the first main surface 3.
  • the gate wiring 41 may also be referred to as a "gate finger” or “gate finger electrode.”
  • the gate wiring 41 transmits the gate potential applied to the gate electrode 40 to other regions.
  • the gate wiring 41 includes a lower electrode film 36 and a main electrode film 37, which are stacked in this order from the chip 2 side, similar to the source electrode 35 (gate electrode 40).
  • the gate wiring 41 is drawn out from the gate electrode 40 onto a portion of the interlayer film 31 that covers the first surface 8.
  • the gate wiring 41 is routed in a strip shape in the region between the periphery of the first surface 8 and the source electrode 35.
  • the gate wiring 41 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y.
  • the gate wiring 41 is formed in a strip shape with ends having four sides parallel to the periphery of the first main surface 3, and surrounds the source electrode 35.
  • the gate wiring 41 intersects (specifically, perpendicular to) the ends (both ends in this embodiment) of the multiple gate structures 15.
  • the gate wiring 41 enters the multiple gate openings 33 from above the interlayer film 31, and is mechanically and electrically connected to the ends (both ends) of the multiple gate structures 15 (buried electrodes 18) within the multiple gate openings 33.
  • the gate potential applied to the gate electrode 40 is applied to the multiple gate structures 15 via the gate wiring 41.
  • the semiconductor device 1A includes a drain electrode 42 covering the second main surface 4.
  • the drain electrode 42 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain electrode 42 may also be referred to as a "third pad electrode,” a “third main surface electrode,” a “third terminal electrode,” etc.
  • the drain electrode 42 is electrically connected to the first semiconductor region 6.
  • the drain electrode 42 may cover the entire second major surface 4 so as to be continuous with the periphery of the second major surface 4 (first to fourth side surfaces 5A to 5D).
  • the drain electrode 42 may partially cover the second major surface 4 so as to expose the periphery of the second major surface 4.
  • the breakdown voltage that can be applied between the source electrode 35 and the drain electrode 42 (between the first major surface 3 and the second major surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • the semiconductor device 1A includes the chip 2, the n-type second semiconductor region 7 (semiconductor layer), the trench-type gate structure 15, the p-type body region 20, and the n-type high-concentration region 24.
  • the chip 2 has a first main surface 3.
  • the second semiconductor region 7 is formed in a surface layer portion of the first main surface 3.
  • the gate structure 15 is formed on the first main surface 3 and is located within the second semiconductor region 7.
  • the body region 20 is formed in a surface layer of the first main surface 3 in a region on the first main surface 3 side with respect to the depth position of the bottom wall 15c of the gate structure 15.
  • the high concentration region 24 is formed in the chip 2 in a thickness range between the bottom wall 15c of the gate structure 15 and the bottom of the body region 20.
  • the high concentration region 24 has an impurity concentration higher than the impurity concentration of the second semiconductor region 7.
  • This configuration allows the application of a semiconductor device 1A that can improve electrical characteristics.
  • the resistance value in the vicinity of the gate structure 15 is reduced by the high concentration region 24 formed below the body region 20.
  • This configuration is effective in reducing the on-resistance and JFET resistance.
  • the high concentration region 24 offsets undesired p-type impurities introduced to the side of the gate structure 15 due to process errors, etc. This suppresses fluctuations in the gate threshold voltage caused by undesired p-type impurities.
  • the chip 2 preferably contains SiC.
  • This configuration provides the semiconductor device 1A as a SiC semiconductor device capable of improving electrical characteristics.
  • the high concentration region 24 may have a bottom located on the first main surface 3 side relative to the depth position of the bottom wall 15c of the gate structure 15. This configuration suppresses an increase in current density in the vicinity of the bottom wall 15c of the gate structure 15. This reduces the electric field with respect to the bottom wall 15c of the gate structure 15, suppressing a decrease in breakdown voltage due to electric field concentration.
  • the high concentration region 24 may be connected to the gate structure 15. With this configuration, the undesired p-type impurities introduced to the side of the gate structure 15 are appropriately offset by the high concentration region 24. This appropriately suppresses the fluctuation of the gate threshold voltage.
  • the high concentration region 24 may have a thickness less than the thickness of the body region 20. With this configuration, the reduction in the cross-sectional area of the body region 20 caused by the high concentration region 24 is suppressed. Therefore, the function of the body region 20 is properly ensured in a configuration in which the high concentration region 24 is present.
  • the gate structure 15 may have sidewalls (first sidewall 15a and second sidewall 15b) with an inclination angle of 87° or more and 93° or less. For example, if the gate structure 15 has sidewalls (first sidewall 15a and second sidewall 15b) that are inclined at an angle of less than 87°, depending on the process conditions, p-type impurities may be easily introduced to the sides of the gate structure 15 through the sidewalls (first sidewall 15a and second sidewall 15b) of the trench 16 of the gate structure 15.
  • the gate structure 15 having sidewalls (first sidewall 15a and second sidewall 15b) that are nearly perpendicular to the first main surface 3 suppresses undesired introduction of p-type impurities through the sidewalls (first sidewall 15a and second sidewall 15b). Even if p-type impurities are introduced, the p-type impurities are offset by the high concentration region 24. Therefore, fluctuations in the gate threshold voltage are appropriately suppressed.
  • a plurality of gate structures 15 may be formed at intervals on the first main surface 3.
  • the body region 20 may be formed in the region between the plurality of gate structures 15.
  • the high concentration region 24 may be formed in the thickness range between the bottom walls 15c of the plurality of gate structures 15 and the bottom of the body region 20 in the region between the plurality of gate structures 15.
  • the high concentration region 24 reduces the resistance in the region between the multiple gate structures 15.
  • the gate threshold voltage fluctuation suppression effect is obtained for the multiple gate structures 15.
  • the high concentration region 24 may be connected to the multiple gate structures 15.
  • the semiconductor device 1A may include an n-type source region 21 (impurity region) and a channel region 26.
  • the source region 21 may be formed in a region on the first main surface 3 side with respect to the body region 20 so as to be aligned with the gate structure 15.
  • the high concentration region 24 may face the source region 21 across a portion of the body region 20.
  • the channel region 26 may be formed in the body region 20 between the source region 21 and the high concentration region 24.
  • the high concentration region 24 may have an n-type impurity concentration less than the n-type impurity concentration of the source region 21.
  • the semiconductor device 1A may include a p-type well region 22 formed in a region along the bottom wall 15c of the gate structure 15 within the chip 2. With this configuration, a depletion layer spreads from the pn junction between the well region 22 and the second semiconductor region 7 when a reverse bias voltage is applied.
  • the well region 22 may have an upper end that is aligned with a corner of the bottom wall 15c of the gate structure 15.
  • the high concentration region 24 may be formed in a thickness range between the bottom of the body region 20 and the upper end of the well region 22. With this configuration, the fluctuation in the gate threshold voltage caused by the p-type impurity that constitutes the upper end of the well region 22 is appropriately suppressed by the high concentration region 24.
  • the well region 22 may have a thickness greater than the thickness of the body region 20.
  • the semiconductor device 1A may include a p-type high-concentration well region 23 formed in the well region 22 at a distance from the bottom of the well region 22 toward the bottom wall 15c of the gate structure 15.
  • the high-concentration well region 23 may have a p-type impurity concentration higher than the p-type impurity concentration of the well region 22.
  • the high-concentration well region 23 may have a bottom located on the bottom wall 15c side of the gate structure 15 with respect to the depth position of the middle part of the well region 22.
  • the semiconductor device 1A may include a p-type first contact region 27 formed in a region along the sidewall of the gate structure 15 within the chip 2.
  • the first contact region 27 may have an impurity concentration higher than the impurity concentration of the body region 20. With this configuration, the electrical response of the body region 20 is improved by the first contact region 27.
  • the semiconductor device 1A may include a p-type first contact region 27 formed in a region along the bottom wall 15c of the gate structure 15 within the chip 2.
  • the first contact region 27 may have an impurity concentration higher than the impurity concentration of the body region 20. With this configuration, the electrical response of the body region 20 is improved by the first contact region 27.
  • the semiconductor device 1A may include a p-type second contact region 28 formed in a region along the bottom wall 15c of the gate structure 15 within the chip 2.
  • the second contact region 28 may have an impurity concentration higher than the impurity concentration of the body region 20.
  • the second contact region 28 may be electrically connected to the first contact region 27. With this configuration, the electrical response of the second contact region 28 is improved by the first contact region 27.
  • the second contact region 28 may electrically connect the well region 22 to the first contact region 27. With this configuration, the electrical response of the well region 22 is improved by the second contact region 28.
  • the semiconductor device 1A may include an n-type medium concentration region 25 formed in a region below the high concentration region 24 within the chip 2.
  • the medium concentration region 25 may have an impurity concentration higher than the impurity concentration of the second semiconductor region 7 and lower than the impurity concentration of the high concentration region 24.
  • the resistance value in the region below the high concentration region 24 is reduced by the medium concentration region 25.
  • Such a configuration is effective in reducing the on-resistance and JFET resistance. Since the medium concentration region 25 has a lower impurity concentration than the high concentration region 24, an increase in current density near the bottom wall 15c of the gate structure 15 is suppressed. Therefore, a decrease in breakdown voltage caused by electric field concentration is suppressed.
  • the medium concentration region 25 may have a region located above the depth position of the bottom wall 15c of the gate structure 15, and a region located below the depth position of the bottom wall 15c of the gate structure 15.
  • FIG. 9 is a schematic diagram showing a wafer 45 used in the manufacture of semiconductor device 1A.
  • Wafer 45 is the base material of chip 2 and contains SiC single crystal.
  • Wafer 45 is formed in a flat disk shape. Of course, wafer 45 may also be formed in a flat rectangular parallelepiped shape.
  • Wafer 45 has a first wafer main surface 46 on one side, a second wafer main surface 47 on the other side, and a wafer side surface 48 connecting first wafer main surface 46 and second wafer main surface 47.
  • the first wafer main surface 46 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 47 corresponds to the second main surface 4 of the chip 2.
  • the first wafer main surface 46 and the second wafer main surface 47 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 46 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 47 is formed by the carbon surface of the SiC single crystal.
  • the wafer 45 (the first wafer main surface 46 and the second wafer main surface 47) has the off-direction and off-angle described above.
  • the wafer 45 has a mark 49 on the wafer side surface 48 that indicates the crystal orientation of the SiC single crystal.
  • the mark 49 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 46 in a plan view.
  • the mark 49 may include either or both of a first orientation flat extending in the a-axis direction and a second orientation flat extending in the m-axis direction.
  • the mark 49 may include either or both of an orientation notch recessed in the a-axis direction and an orientation notch recessed in the m-axis direction.
  • the wafer 45 includes an n-type first semiconductor region 6 formed in a surface layer of the second wafer main surface 47.
  • the first semiconductor region 6 is formed in a layer extending along the second wafer main surface 47, and is exposed from the second wafer main surface 47 and the wafer side surface 48.
  • the first semiconductor region 6 is made of an n-type semiconductor wafer (SiC wafer) containing SiC single crystal (semiconductor single crystal), and has the off direction and off angle described above.
  • the wafer 45 includes an n-type second semiconductor region 7 formed in a surface layer of the first wafer main surface 46.
  • the second semiconductor region 7 is formed in a layer extending along the first wafer main surface 46 and is exposed from the first wafer main surface 46 and the wafer side surface 48.
  • the second semiconductor region 7 is made of an n-type epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal) and is layered on the first semiconductor region 6.
  • the second semiconductor region 7 has the off-direction and off-angle described above.
  • the wafer 45 is made of an epitaxial wafer (a so-called epiwafer) having a layered structure including a semiconductor wafer and an epitaxial layer.
  • the wafer 45 includes a plurality of device regions 50 and a plurality of cutting lines 51.
  • the plurality of device regions 50 and the plurality of cutting lines 51 are defined by alignment marks or the like formed on the first wafer main surface 46 side.
  • Each device region 50 is an area corresponding to the semiconductor device 1A.
  • the plurality of device regions 50 are each set to have a rectangular shape in a plan view.
  • the multiple device regions 50 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 50 are each set at intervals inward from the periphery of the first wafer main surface 46 in a plan view.
  • the multiple cutting lines 51 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 50.
  • FIGS. 10A to 10P are cross-sectional views showing an example of a manufacturing method for semiconductor device 1A.
  • FIG. 10A to FIG. 10P a cross section of the area corresponding to FIG. 5 is shown.
  • the aforementioned wafer 45 (see FIG. 9) is prepared.
  • a base medium concentration region 52 is formed in the surface layer of the first wafer main surface 46 in the wafer 45 (second semiconductor region 7).
  • the base medium concentration region 52 is the base of the multiple medium concentration regions 25.
  • n-type impurities are introduced into the second semiconductor region 7 by ion implantation.
  • the ion implantation method may be either one or both of channeling ion implantation and random ion implantation.
  • n-type impurities are introduced into the second semiconductor region 7 along the axial channel of the second semiconductor region 7.
  • the axial channel is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the second semiconductor region 7, and is surrounded by atomic rows that form a crystal axis that extends in the stacking direction (crystal growth direction).
  • the axial channel is a region in which the atomic rows are sparse extending in the stacking direction, and in which the atomic rows (atomic distance/atomic density) are sparse in the horizontal direction in a planar view.
  • the axial channel is preferably a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • a low-index crystal axis is a crystal axis in which the absolute values of "a1", "a2", “a3" and "c" are all expressed as 2 or less (preferably 1 or less) with respect to the Miller indices (a1, a2, a3, c).
  • the axial channel consists of a region surrounded by atomic rows along the c-axis ((0001) axis) of the SiC single crystal.
  • the axial channel extends along the c-axis and has the off-direction and off-angle described above.
  • the axial channel is inclined from the vertical axis toward the off-direction by the off-angle.
  • n-type impurities are implanted deep into the second semiconductor region 7 while repeatedly undergoing small-angle scattering due to the channeling effect.
  • the channeling implantation method reduces the probability of n-type impurities colliding with the atomic rows of the SiC single crystal. Therefore, the channeling ion implantation process is effective when forming a relatively deep base medium concentration region 52.
  • n-type impurities are introduced into the second semiconductor region 7 in a random direction.
  • the random direction is a direction other than the axial channel of the second semiconductor region 7 (i.e., a direction intersecting the axial channel).
  • the random direction is the vertical direction Z.
  • the probability of collision of n-type impurities with the atomic rows of the SiC single crystal is high, so the base medium concentration region 52 is formed in a relatively shallow region. Therefore, the random ion implantation process is effective when forming a relatively shallow base medium concentration region 52.
  • the base medium concentration region 52 is formed in a layer extending horizontally along the first wafer main surface 46.
  • the base medium concentration region 52 may be formed in the second semiconductor region 7 at a distance from the first wafer main surface 46 to the bottom side of the second semiconductor region 7.
  • the base medium concentration region 52 may be exposed from the first wafer main surface 46.
  • the base high concentration region 53 is formed at a distance from the first wafer main surface 46.
  • a base high concentration region 53 is formed in the surface layer of the first wafer main surface 46 in the wafer 45 (second semiconductor region 7).
  • the base high concentration region 53 is the base of the multiple high concentration regions 24.
  • n-type impurities are introduced into the second semiconductor region 7 by ion implantation.
  • the ion implantation may be either one or both of channeling ion implantation and random ion implantation. Since the n-type impurities are introduced into a region shallower than the medium concentration base region 52, it is preferable that the ion implantation is random ion implantation.
  • the n-type impurity is introduced into the thickness range of the first wafer main surface 46 and the base medium concentration region 52. This forms a high concentration base region 53 that extends horizontally in a layer along the first wafer main surface 46.
  • the high concentration base region 53 may be formed in the second semiconductor region 7 at a distance from the first wafer main surface 46 to the bottom side of the second semiconductor region 7.
  • the high concentration base region 53 may be exposed from the first wafer main surface 46. Considering the offsetting of p-type impurities and n-type impurities in later processes, it is preferable that the high concentration base region 53 is formed at a distance from the first wafer main surface 46 to the bottom side of the second semiconductor region 7.
  • a base body region 54 is formed in the surface layer of the first wafer main surface 46 in the wafer 45 (second semiconductor region 7).
  • the base high concentration region 53 is the base of the multiple body regions 20.
  • p-type impurities are introduced into the second semiconductor region 7 by ion implantation.
  • the ion implantation method may be either one or both of channeling ion implantation and random ion implantation. Since the p-type impurity is introduced into a region shallower than the high concentration base region 53, the ion implantation method is preferably random ion implantation. In this embodiment, the p-type impurity is introduced into the thickness range of the first wafer main surface 46 and the high concentration base region 53. This forms a base body region 54 that extends in layers horizontally along the first wafer main surface 46.
  • a base source region 55 is formed in the surface layer of the first wafer main surface 46 in the wafer 45 (base body region 54).
  • the base source region 55 is the base of the multiple source regions 21.
  • n-type impurities are introduced into the base body region 54 by ion implantation.
  • the ion implantation method may be either one or both of channeling ion implantation and random ion implantation. Since the n-type impurity is introduced into a region shallower than the base body region 54, the ion implantation method is preferably random ion implantation. This forms a base source region 55 that extends horizontally in layers along the first wafer main surface 46.
  • the process order of the base medium concentration region 52 formation process, the base high concentration region 53 formation process, the body region 20 formation process, and the base source region 55 formation process may be arbitrarily changed and performed as appropriate.
  • a mesa 11 and a plurality of trenches 16 are formed on the first wafer main surface 46.
  • a first mask 56 having a predetermined layout is first formed on the first wafer main surface 46.
  • the first mask 56 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (resist mask).
  • the first mask 56 exposes the second surface 9 and the area where the plurality of trenches 16 are to be formed, and covers the other areas.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • the first surface portion 8, the second surface portion 9, the first to fourth connection surface portions 10A to 10D, and a plurality of trenches 16 are formed.
  • the base high concentration region 53, the base body region 54, and the base source region 55 are separated by the plurality of trenches 16, and a plurality of body regions 20, a plurality of source regions 21, and a plurality of high concentration regions 24 are formed.
  • the multiple trenches 16 are formed approximately perpendicular to the first wafer main surface 46. That is, the first sidewall 15a and the second sidewall 15b of the multiple trenches 16 have an inclination angle of 87° or more and 93° or less.
  • the bottom walls 15c of the multiple trenches 16 are formed flat along the horizontal direction.
  • the trenches 16 having bottom walls 15c made of a flat surface improve the accuracy of introducing impurities through the bottom walls 15c.
  • the first mask 56 is removed after this process.
  • a plurality of well regions 22 are formed in the wafer 45 (second semiconductor region 7) in regions along the bottom walls 15c of the plurality of trenches 16.
  • a second mask 57 having a predetermined layout is formed on the first wafer main surface 46.
  • the second mask 57 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (resist mask).
  • the second mask 57 exposes the regions where the multiple well regions 22 are to be formed (i.e., the multiple trenches 16) and covers the other regions.
  • p-type impurities are introduced into the second semiconductor region 7 through the bottom walls 15c of the multiple trenches 16 by ion implantation through the second mask 57.
  • the ion implantation may be either one or both of channeling ion implantation and random ion implantation.
  • the ion implantation method is preferably a random ion implantation method, and the p-type impurity is introduced into the wafer 45 at an implantation angle that is approximately perpendicular to the first wafer main surface 46.
  • the ion implantation method is preferably a vertical ion implantation method, not an oblique ion implantation method. This process suppresses the introduction of the p-type impurity into the wafer 45 through the first sidewall 15a and the second sidewall 15b of the trench 16.
  • the p-type impurity may be implanted in a single step at a target depth position in the second semiconductor region 7 (medium base concentration region 52).
  • the p-type impurity may be implanted in multiple steps at different target depth positions in the second semiconductor region 7 (medium base concentration region 52) with different implantation energies.
  • the p-type impurity implantation process may include a step of implanting the p-type impurity multiple times at the same target depth position in the second semiconductor region 7 (medium base concentration region 52).
  • the number of injection stages (the number of target depth positions) of p-type impurities in the multi-stage injection process is adjusted appropriately according to the thickness of the well region 22.
  • the number of injection stages may be 2, 3, 4, 5, 6, 7, 8, 9, or 10.
  • the number of injection stages is preferably 2 to 5.
  • p-type impurities are injected into different target depth positions so that the injection sites of the p-type impurities overlap.
  • the dose (impurity concentration) of the p-type impurity into the second semiconductor region 7 may be adjusted to increase as the injection site becomes deeper.
  • the injection energy of the p-type impurity into the second semiconductor region 7 may be adjusted to increase as the injection site becomes deeper.
  • multiple well regions 22 having multiple first bulges 22c that gradually increase and decrease in multiple steps along the thickness direction are formed in the regions along the bottom walls 15c of the multiple trenches 16.
  • the base medium concentration region 52 is separated by the multiple well regions 22, and multiple medium concentration regions 25 are formed.
  • multiple high concentration well regions 23 are formed in the multiple well regions 22 in regions along the bottom walls 15c of the multiple trenches 16.
  • p-type impurities are introduced into the wafer 45 through the bottom walls 15c of the multiple trenches 16 by ion implantation through the second mask 57 described above.
  • the ion implantation may be either one or both of channeling ion implantation and random ion implantation.
  • the ion implantation method is preferably a random ion implantation method, and the p-type impurity is introduced into the wafer 45 at an implantation angle that is approximately perpendicular to the first wafer main surface 46.
  • the ion implantation method is preferably a vertical ion implantation method, not an oblique ion implantation method. This process suppresses the introduction of the p-type impurity into the second semiconductor region 7 through the first sidewall 15a and the second sidewall 15b of the trench 16.
  • multiple high-concentration well regions 23 are formed in each of the multiple well regions 22.
  • the second mask 57 related to the well region 22 formation process is used.
  • the multiple high-concentration well regions 23 may be formed using a mask different from the second mask 57. The second mask 57 is then removed.
  • a plurality of first contact regions 27 and a plurality of second contact regions 28 are formed in the wafer 45 (second semiconductor region 7) in regions along the plurality of trenches 16.
  • a third mask 58 having a predetermined layout is formed on the first wafer main surface 46.
  • the third mask 58 may be an inorganic mask (e.g., a silicon oxide film) or an organic mask (resist mask).
  • the third mask 58 exposes the areas where the multiple first contact regions 27 and the multiple second contact regions 28 are to be formed, and covers the other areas. In other words, the third mask 58 selectively exposes a portion of the first wafer main surface 46 and a portion of the multiple trenches 16.
  • p-type impurities are introduced into the wafer 45 through the first wafer main surface 46 and the multiple trenches 16 by ion implantation through the third mask 58.
  • the ion implantation may be either or both of a channeling ion implantation method and a random ion implantation method.
  • the ion implantation method is a random ion implantation method.
  • the random ion implantation method may be a vertical ion implantation method.
  • the p-type impurity is introduced into the wafer 45 at an implantation angle that is approximately perpendicular to the first wafer main surface 46.
  • the random ion implantation method may be an oblique ion implantation method.
  • p-type impurities are introduced into the wafer 45 at an implantation angle that is oblique to the first wafer main surface 46.
  • the implantation angle may be greater than 0° and less than or equal to 10°.
  • a plurality of first contact regions 27 and a plurality of second contact regions 28 are respectively formed in the second semiconductor region 7.
  • the third mask 58 is then removed.
  • a base insulating film 59 is formed on the first wafer main surface 46.
  • the base insulating film 59 serves as a base for the multiple insulating films 17 and the main surface insulating film 30.
  • the base insulating film 59 is formed in the form of a film along the first wafer main surface 46 and the wall surfaces of the multiple trenches 16.
  • the base insulating film 59 may be formed by either one or both of a CVD method and an oxidation process (e.g., a thermal oxidation process).
  • a first base electrode film 60 is formed on the base insulating film 59.
  • the first base electrode film 60 serves as a base for the multiple buried electrodes 18.
  • the first base electrode film 60 has a portion that covers the first wafer main surface 46 with the base insulating film 59 in between, and a portion that is embedded in the multiple trenches 16 with the base insulating film 59 in between.
  • the base insulating film 59 may be formed by a CVD method.
  • the etching method may be either or both of a wet etching method and a dry etching method. As a result, a plurality of buried electrodes 18 are formed. Also, a plurality of gate structures 15 are formed.
  • the interlayer film 31 is formed on the first wafer main surface 46.
  • the interlayer film 31 collectively covers the first surface portion 8, the second surface portion 9, the first to fourth connection surface portions 10A to 10D, and the multiple gate structures 15 in a film-like manner.
  • the interlayer film 31 may be formed by a CVD method.
  • a fourth mask 61 having a predetermined layout is formed on the interlayer film 31.
  • the fourth mask 61 may be an organic mask (resist mask).
  • the fourth mask 61 exposes areas where the source openings 32 and the gate openings 33 are to be formed, and covers the other areas.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • Unnecessary portions of the base insulating film 59 may be removed simultaneously with the interlayer film 31. This results in a plurality of source openings 32 and a plurality of gate openings 33 being formed in the interlayer film 31.
  • the base insulating film 59 is also divided into an insulating film 17 and a main surface insulating film 30. The fourth mask 61 is then removed.
  • a second base electrode film 62 is formed on the interlayer film 31.
  • the second base electrode film 62 is the base for the source electrode 35, the gate electrode 40, and the gate wiring 41.
  • the second base electrode film 62 has a layered structure including the lower electrode film 36 and the main electrode film 37.
  • the lower electrode film 36 has a layered structure including the first electrode film 38 and the second electrode film 39.
  • the first electrode film 38 may be formed by either or both of a sputtering method and a vapor deposition method.
  • the first electrode film 38 is formed in the form of a film along the first wafer main surface 46, the interlayer film 31, the wall surfaces of the multiple source openings 32, and the wall surfaces of the multiple gate openings 33.
  • the second electrode film 39 may be formed by either or both of a sputtering method and a vapor deposition method.
  • the second electrode film 39 is laminated on the first electrode film 38 and formed in a film shape along the first wafer main surface 46, the interlayer film 31, the wall surfaces of the multiple source openings 32, and the wall surfaces of the multiple gate openings 33.
  • the main electrode film 37 is formed on the lower electrode film 36.
  • the main electrode film 37 may be formed by either or both of a sputtering method and a vapor deposition method.
  • the main electrode film 37 is laminated on the lower electrode film 36 and formed in the form of a film along the first wafer main surface 46, the interlayer film 31, the wall surfaces of the multiple source openings 32, and the wall surfaces of the multiple gate openings 33.
  • the second base electrode film 62 is divided into the source electrode 35, the gate electrode 40, and the gate wiring 41.
  • a mask (not shown) having a predetermined layout is formed on the main electrode film 37.
  • the mask (not shown) covers the areas where the source electrode 35, the gate electrode 40, and the gate wiring 41 are to be formed, and leaves the other areas exposed.
  • unnecessary portions of the main electrode film 37 are removed by etching through a mask (not shown).
  • the unnecessary portions of the main electrode film 37 are removed until the lower electrode film 36 is exposed.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • the mask (not shown) is removed after the etching process of the main electrode film 37.
  • the process of removing the lower electrode film 36 includes a process of removing the second electrode film 39 by an etching method, and a process of removing the first electrode film 38 by an etching method.
  • the etching method may be either or both of a wet etching method and a dry etching method.
  • unnecessary portions of the lower electrode film 36 may be removed by an etching method using a mask (not shown) in the etching process of the main electrode film 37.
  • a drain electrode 42 is formed on the second wafer main surface 47.
  • the drain electrode 42 may be formed by either or both of a sputtering method and a vapor deposition method. Thereafter, the wafer 45 is cut along the intended cutting lines 51 (see FIG. 9) to cut out a plurality of semiconductor devices 1A. Through the steps including those described above, the semiconductor device 1A is manufactured.
  • FIG. 11 is a cross-sectional view showing a main portion of a semiconductor device 1B according to the second embodiment.
  • the semiconductor device 1B includes a plurality of well regions 22 each formed as a column region forming a superjunction structure.
  • the multiple well regions 22 are formed in a columnar shape extending in the thickness direction in a cross-sectional view.
  • the semiconductor device 1B includes a plurality of n-type intermediate drift regions 64 formed in the chip 2 (second semiconductor region 7).
  • Each of the plurality of intermediate drift regions 64 is made up of a region partitioned between a plurality of well regions 22 in the second semiconductor region 7. That is, in this embodiment, the plurality of intermediate drift regions 64 each include a part of the second semiconductor region 7, a high concentration region 24, and a medium concentration region 25.
  • the multiple intermediate drift regions 64 are arranged alternately with the multiple well regions 22 in the first direction X, and are each formed in a band shape extending in the second direction Y. That is, the multiple intermediate drift regions 64 are formed in stripes extending in the second direction Y along the multiple well regions 22.
  • the extension direction of the multiple intermediate drift regions 64 coincides with the off-direction of the SiC single crystal.
  • the multiple intermediate drift regions 64 are formed in columns extending in the thickness direction in a cross-sectional view, and face the multiple body regions 20 in a one-to-one correspondence.
  • the intermediate drift regions 64 form charge-balanced pn junctions together with the well regions 22 in the thickness range below the gate structures 15.
  • the charge-balanced state means that, for adjacent well regions 22, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the intermediate drift regions 64.
  • the semiconductor device 1B includes an n-type intermediate drift region 64 that is partitioned between multiple well regions 22 in the chip 2 (second semiconductor region 7).
  • the intermediate drift region 64 is partitioned in a region between multiple well regions 22 in the second semiconductor region 7.
  • the intermediate drift region 64 and the multiple well regions 22 form a superjunction structure.
  • a superjunction type semiconductor device 1B is provided.
  • the chip 2 includes SiC, a superjunction type SiC semiconductor device is provided.
  • FIG. 12 is a plan view showing a main part of a semiconductor device 1C according to the third embodiment.
  • FIG. 13 is a cross-sectional view taken along line XIII-XIII shown in FIG. 12.
  • FIG. 14 is a cross-sectional view taken along line XIV-XIV shown in FIG. 12.
  • FIG. 15 is an enlarged cross-sectional view of a region including source structure 65 shown in FIG. 13.
  • FIG. 16 is an enlarged cross-sectional view of a region including source structure 65 shown in FIG. 14.
  • the semiconductor device 1C differs from the semiconductor device 1A in that it includes multiple trench-type (trench electrode-type) source structures 65 formed on the first main surface 3 (first surface portion 8).
  • the source structures 65 may be referred to as “trench source structures", “second trench structures”, etc.
  • a source potential is applied to the multiple source structures 65.
  • semiconductor device 1C the layout of other components relative to gate structure 15 is similar to that of semiconductor device 1A, so the following mainly describes the form of other components relative to source structure 65. Descriptions of other components relative to gate structure 15 will be omitted unless otherwise specified. For omitted descriptions, the descriptions given in semiconductor device 1A apply.
  • the multiple source structures 65 are formed adjacent to the multiple gate structures 15 in the first direction X. Specifically, the multiple source structures 65 are each disposed in a region between the multiple adjacent gate structures 15, and face the multiple gate structures 15 in the first direction X. The multiple source structures 65 are arranged alternately with the multiple gate structures 15 in the first direction X.
  • the multiple source structures 65 may be formed on the first surface portion 8 at intervals inward from the periphery of the first surface portion 8 (the first to fourth connection surface portions 10A to 10D). The multiple source structures 65 may penetrate the periphery of the first surface portion 8 and be exposed from the first to fourth connection surface portions 10A to 10D.
  • the multiple source structures 65 are formed at intervals from the bottom of the second semiconductor region 7 toward the first major surface 3, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the multiple source structures 65 are formed approximately perpendicular to the first major surface 3 (first surface portion 8).
  • each of the source structures 65 has a first side wall 65a on one side in the first direction X (the third side surface 5C side), a second side wall 65b on the other side in the first direction X (the fourth side surface 5D side), and a bottom wall 65c connecting the first side wall 65a and the second side wall 65b.
  • the first sidewall 65a and the second sidewall 65b are each formed by the a-plane ((11-20) plane) of the SiC single crystal.
  • the first sidewall 65a and the second sidewall 65b may each be formed by the m-plane ((1-100) plane) of the SiC single crystal depending on the extension direction of the source structure 65.
  • the first sidewall 65a and the second sidewall 65b are formed approximately perpendicular to the first main surface 3.
  • the inclination angle (absolute value) of the first side wall 65a (second side wall 65b) based on the vertical line may be 85° or more and 95° or less.
  • the inclination angle of the first side wall 65a (second side wall 65b) may have a value that belongs to at least one of the ranges of 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle of the first side wall 65a (second side wall 65b) is preferably 87° or more and 93° or less.
  • the bottom wall 65c is formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom wall 65c extends almost flat along the horizontal direction. Of course, the bottom wall 65c may be curved in an arc shape toward the second main surface 4.
  • the width of the source structure 65 may be approximately equal to the width of the gate structure 15.
  • the width of the source structure 65 may be greater than the width of the gate structure 15 or less than the width of the gate structure 15.
  • the source structure 65 may have a width of 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the width of the source structure 65 may have a value that falls within at least one of the following ranges: 0.1 ⁇ m to 0.25 ⁇ m, 0.25 ⁇ m to 0.5 ⁇ m, 0.5 ⁇ m to 0.75 ⁇ m, 0.75 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.25 ⁇ m, and 1.25 ⁇ m to 1.5 ⁇ m.
  • the width of the source structure 65 is preferably 0.25 ⁇ m to 0.75 ⁇ m.
  • the depth of the source structure 65 may be approximately equal to the depth of the second surface portion 9. The depth of the source structure 65 may be greater than the depth of the second surface portion 9 or less than the depth of the second surface portion 9. The depth of the source structure 65 may be approximately equal to the depth of the gate structure 15. The depth of the source structure 65 may be greater than the depth of the gate structure 15 or less than the depth of the gate structure 15.
  • the depth of the source structure 65 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the source structure 65 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the source structure 65 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • Each of the multiple source structures 65 includes a second trench 66, a second insulating film 67, and a second buried electrode 68.
  • the second trench 66 is formed in the first main surface 3 and defines the walls of the source structure 65 (the first sidewall 65a, the second sidewall 65b, and the bottom wall 65c).
  • the second insulating film 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the second insulating film 67 includes the same type of insulating material as the insulating film 17. In this embodiment, the second insulating film 67 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 67 includes a silicon oxide film made of an oxide of the chip 2.
  • the second insulating film 67 coats the wall surface of the second trench 66 in a film-like manner.
  • the second insulating film 67 coats the first sidewall 65a and the second sidewall 65b at a distance from the first main surface 3 toward the bottom wall 65c.
  • the second insulating film 67 exposes a part of the first sidewall 65a and a part of the second sidewall 65b from the opening end of the second trench 66.
  • the second insulating film 67 includes a first film portion, a second film portion, and a third film portion.
  • the first film portion covers the first sidewall 65a of the second trench 66 in a film-like manner.
  • the second film portion covers the second sidewall 65b of the second trench 66 in a film-like manner.
  • the third film portion covers the bottom wall 65c of the second trench 66 in a film-like manner, and is connected to the first film portion and the second film portion.
  • the second membrane portion has a thickness approximately equal to the thickness of the first membrane portion.
  • the third membrane portion has a thickness greater than the thickness of the first membrane portion and the thickness of the second membrane portion.
  • the thickness of the third membrane portion may be approximately equal to the thickness of the first membrane portion and the thickness of the second membrane portion.
  • the first film portion of the second insulating film 67 may have a thickness approximately equal to that of the first film portion of the insulating film 17.
  • the second film portion of the second insulating film 67 may have a thickness approximately equal to that of the second film portion of the insulating film 17.
  • the third film portion of the second insulating film 67 may have a thickness approximately equal to that of the third film portion of the insulating film 17.
  • the second insulating film 67 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the second insulating film 67 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the second buried electrode 68 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the second buried electrode 68 is buried in the second trench 66 with the second insulating film 67 sandwiched therebetween.
  • the second buried electrode 68 has an electrode surface exposed from the second trench 66.
  • the electrode surface of the second buried electrode 68 is located on the bottom wall 65c side of the second trench 66 with respect to the height position of the first main surface 3.
  • the electrode surface of the second buried electrode 68 may be located on the bottom wall 65c side with respect to the height position of the electrode surface of the buried electrode 18.
  • the height position of the electrode surface of the second buried electrode 68 may be approximately equal to the height position of the electrode surface of the buried electrode 18.
  • the electrode surface of the second buried electrode 68 has a recess in the inner part that is tapered toward the bottom wall 15c. It is preferable that the bottom of the recess is located on the first main surface 3 side with respect to the depth position of the middle part of the second trench 66.
  • the semiconductor device 1C includes a plurality of body regions 20 formed in a region along the plurality of gate structures 15 in the surface portion of the first main surface 3 (first surface portion 8).
  • the plurality of body regions 20 are formed in the regions between the plurality of gate structures 15 and the plurality of source structures 65, respectively, and extend in a strip shape along the plurality of gate structures 15 and the plurality of source structures 65, respectively.
  • the body region 20 is formed in a layer extending in the first direction X in a cross-sectional view, and is connected to the gate structure 15 and the source structure 65.
  • the body region 20 faces the second buried electrode 68 on the source structure 65 side, with the second insulating film 67 sandwiched therebetween.
  • the body region 20 is formed in a region on the first main surface 3 side with respect to the depth position of the bottom wall 65c of the source structure 65.
  • the body region 20 has a bottom portion located on the bottom wall 65c side of the source structure 65 with respect to the depth position of the middle part of the source structure 65.
  • the bottom of the body region 20 is located in the region between the bottom wall 65c of the source structure 65 and the middle part of the source structure 65. In other words, the distance between the bottom of the body region 20 and the bottom wall 65c of the source structure 65 is less than the thickness (depth) of the body region 20.
  • the bottom of the body region 20 is located on the bottom wall 65c side with respect to the bottom of the recess of the second buried electrode 68.
  • the semiconductor device 1C includes a plurality of source regions 21 formed in a region on the first main surface 3 side relative to the plurality of body regions 20.
  • the plurality of source regions 21 are formed in regions between the plurality of gate structures 15 and the plurality of source structures 65, respectively, and extend in a strip shape along the plurality of gate structures 15 and the plurality of source structures 65, respectively.
  • the configuration of one source region 21 is described below.
  • the source region 21 is formed at a distance from the bottom of the body region 20 toward the first main surface 3.
  • the source region 21 is formed in a layer extending in the first direction X in a cross-sectional view, and is connected to the gate structure 15 and the source structure 65.
  • the multiple source regions 21 face the second buried electrode 68 on the source structure 65 side, with the second insulating film 67 between them.
  • the source region 21 has a bottom portion located on the bottom wall 65c side of the second trench 66 relative to the height position of the electrode surface of the second buried electrode 68, and a surface portion located on the first main surface 3 side relative to the height position of the electrode surface of the second buried electrode 68.
  • the source region 21 has a portion (bottom portion) that faces the second buried electrode 68 across the second insulating film 67, and a portion (surface portion) that does not face the second buried electrode 68 across the second insulating film 67.
  • the bottom of the source region 21 is preferably located on the bottom side of the body region 20 relative to the depth position of the bottom of the recess of the second buried electrode 68.
  • the bottom of the source region 21 may be located on the first main surface 3 side relative to the depth position of the bottom of the recess.
  • the surface portion of the source region 21 is exposed from the upper end of the first sidewall 65a or the upper end of the second sidewall 65b of the source structure 65.
  • the semiconductor device 1C includes multiple well regions 22 formed in the chip 2 (second semiconductor region 7).
  • the explanation of the multiple well regions 22 is omitted because it is similar to the case of the semiconductor device 1A.
  • the semiconductor device 1C includes a plurality of p-type second well regions 72 formed in the chip 2 (second semiconductor region 7) in regions along the bottom walls 65c of the plurality of source structures 65.
  • the plurality of second well regions 72 are formed in a manner similar to the plurality of well regions 22, and have a p-type impurity concentration approximately equal to the p-type impurity concentration of the plurality of well regions 22.
  • the second well regions 72 are formed in regions along the bottom walls 65c of the source structures 65 at intervals in the first direction X from the well regions 22.
  • the second well regions 72 are formed in one-to-one correspondence with the source structures 65.
  • the second well regions 72 are each formed in a band shape extending along the source structures 65 in a plan view, and face the corresponding second buried electrodes 68 across the corresponding second insulating films 67.
  • the second well regions 72 may be formed in a one-to-many correspondence with one source structure 65. In this case, the second well regions 72 are formed at intervals in the second direction Y.
  • Each second well region 72 is formed to be wider than the source structure 65 in a plan view. In a cross-sectional view, the second well region 72 is formed in a columnar shape extending in the thickness direction (vertical direction Z) of the second semiconductor region 7.
  • the second well region 72 is formed at a distance from the bottom of the second semiconductor region 7 toward the first surface portion 8, and faces the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the second well region 72 may be formed to cross the bottom of the second semiconductor region 7 and have a bottom located within the first semiconductor region 6.
  • the second well region 72 forms a pn junction with the second semiconductor region 7.
  • the second well region 72 has a thickness (depth) greater than the thickness (depth) of the body region 20.
  • the thickness of the second well region 72 is the thickness of the second well region 72 in the vertical direction Z based on the bottom wall 65c of the source structure 65. In this embodiment, the thickness of the second well region 72 is greater than the depth of the source structure 65.
  • the thickness of the second well region 72 may be less than the depth of the source structure 65. In this case, the thickness of the second well region 72 may be less than the thickness of the body region 20. It is preferable that the thickness of the second well region 72 is approximately equal to the thickness of the well region 22. Of course, the thickness of the second well region 72 may be greater than the thickness of the well region 22 or less than the thickness of the well region 22.
  • the second well region 72 has an upper end that fits along the corner of the bottom wall 65c of the source structure 65. At the upper end, the second well region 72 has a first extension 72a on the first sidewall 65a side and a second extension 72b on the second sidewall 65b side (see FIG. 15).
  • the first extension 72a is drawn out from the region directly below the source structure 65 to the lower end of the first sidewall 65a.
  • the first extension 72a is formed at a distance from the bottom of the body region 20 toward the bottom wall 65c of the source structure 65.
  • the first extension 72a faces the second buried electrode 68 in the horizontal direction, sandwiching the second insulating film 67 therebetween.
  • the first extension 72a may be formed on the bottom wall 65c side of the second trench 66 with respect to the depth position of the lower end of the second buried electrode 68, and may face only the second insulating film 67 (third film portion) in the horizontal direction.
  • the first extension 72a is formed in a tapered shape toward the first main surface 3 (the bottom side of the body region 20) in a cross-sectional view.
  • the second extension 72b is drawn out from the region directly below the source structure 65 to the lower end of the second sidewall 65b, and faces the first extension 72a across the source structure 65.
  • the second extension 72b is formed at a distance from the bottom of the body region 20 toward the bottom wall 65c of the source structure 65.
  • the second extension 72b faces the second buried electrode 68 in the horizontal direction, across the second insulating film 67.
  • the second extension 72b may be formed on the bottom wall 65c side of the second trench 66 with respect to the depth position of the lower end of the second buried electrode 68, and may face only the second insulating film 67 (third film portion) in the horizontal direction.
  • the second extension 72b is formed in a tapered shape toward the first main surface 3 (the bottom side of the body region 20) in a cross-sectional view.
  • the second well region 72 has one or more (multiple in this embodiment) third bulge portions 72c.
  • a second well region 72 having four third bulge portions 72c is illustrated.
  • the multiple third bulge portions 72c are each formed by a portion of the second well region 72 whose width in the horizontal direction (first direction X) gradually increases and decreases in the thickness direction, and are formed in multiple stages from the bottom wall 65c of the source structure 65 toward the bottom of the second semiconductor region 7.
  • the multiple third bulge portions 72c extend in an arc shape (circular arc shape) from the region directly below the source structure 65 to both sides of the source structure 65.
  • the single third bulge portion 72c may be formed in the middle of the second well region 72 so as to extend in an arc shape (circular arc shape) to both sides of the source structure 65.
  • the semiconductor device 1C includes a plurality of high-concentration well regions 23 formed within each of the plurality of well regions 22.
  • the description of the multiple high-concentration well regions 23 is omitted because it is similar to the case of the semiconductor device 1A.
  • the semiconductor device 1C includes a plurality of second high concentration well regions 73 of p-type formed respectively within the plurality of second well regions 72.
  • the plurality of second high concentration well regions 73 are formed in a manner similar to the plurality of high concentration well regions 23, and have a p-type impurity concentration approximately equal to the p-type impurity concentration of the plurality of high concentration well regions 23.
  • the second high concentration well regions 73 are each formed in a one-to-one correspondence with the corresponding second well region 72.
  • the second high concentration well regions 73 are each formed in a region along the bottom wall 65c of the corresponding source structure 65.
  • the second high concentration well regions 73 are each formed in a band shape extending along the corresponding source structure 65 (second well region 72) in a plan view, and face the corresponding second buried electrode 68 across the corresponding second insulating film 67.
  • multiple second high-concentration well regions 73 may be formed in a one-to-many correspondence with one second well region 72.
  • the multiple second high-concentration well regions 73 are formed at intervals in the second direction Y within one second well region 72.
  • the configuration of one second high-concentration well region 73 will be described below.
  • the second high-concentration well region 73 is formed at a distance from the bottom of the second well region 72 toward the bottom wall 65c of the source structure 65. It is preferable that the second high-concentration well region 73 has a bottom that is located toward the bottom wall 65c of the source structure 65 with respect to the depth position of the middle part of the second well region 72.
  • the bottom of the second high concentration well region 73 is defined by a concentration transition portion where the p-type impurity concentration gradually decreases toward the bottom side of the second well region 72.
  • the bottom of the second high concentration well region 73 may be located on the bottom side of the second well region 72 with respect to the depth position of the middle part of the second well region 72.
  • the bottom of the second high concentration well region 73 is formed at a depth position that is approximately equal to the depth position of the bottom of the high concentration well region 23.
  • the second high concentration well region 73 is formed narrower than the second well region 72.
  • the second high concentration well region 73 is formed narrower than the source structure 65.
  • the second high concentration well region 73 may be formed wider than the source structure 65 and extend out on both sides of the source structure 65.
  • the width of the second high concentration well region 73 is approximately equal to the width of the high concentration well region 23.
  • the width of the second high concentration well region 73 may be greater than the width of the high concentration well region 23, or may be smaller than the width of the high concentration well region 23.
  • the second high concentration well region 73 has a thickness (depth) less than the depth of the source structure 65.
  • the thickness of the second high concentration well region 73 is the thickness of the second high concentration well region 73 in the vertical direction Z based on the bottom wall 65c of the source structure 65.
  • the thickness of the second high concentration well region 73 is less than the thickness of the body region 20.
  • the thickness of the second high concentration well region 73 may be greater than the thickness of the body region 20 or greater than the depth of the source structure 65.
  • the thickness of the second high concentration well region 73 is preferably approximately equal to the thickness of the high concentration well region 23.
  • the thickness of the second well region 72 may be greater than the thickness of the high concentration well region 23, or may be less than the thickness of the high concentration well region 23.
  • the semiconductor device 1C includes a plurality of high concentration regions 24 formed in the chip 2 (second semiconductor region 7) in regions below the plurality of body regions 20.
  • the plurality of high concentration regions 24 are formed in regions between the plurality of gate structures 15 and the plurality of source structures 65.
  • the multiple high concentration regions 24 are formed in the thickness range between the bottom walls 65c of the multiple source structures 65 and the bottoms of the multiple body regions 20 with respect to the multiple source structures 65.
  • the multiple high concentration regions 24 extend in a band shape along the multiple gate structures 15 and the multiple source structures 65 in a plan view.
  • the high concentration region 24 is formed in a layer extending in the first direction X in a cross-sectional view, and is connected to both the gate structure 15 and the source structure 65.
  • the high concentration region 24 faces the second buried electrode 68 on the source structure 65 side, with the second insulating film 67 sandwiched therebetween.
  • the high concentration region 24 has a bottom located on the first main surface 3 side with respect to the depth position of the bottom wall 65c of the source structure 65. In other words, the high concentration region 24 is formed at a distance from the depth position of the bottom wall 65c of the source structure 65 to the first main surface 3 side.
  • the high concentration region 24 is formed in a thickness range between the body region 20 and the second well region 72, and separates the second well region 72 from the body region 20. In other words, the high concentration region 24 suppresses an increase in the p-type impurity concentration in the portion along the sidewall (first sidewall 65a or second sidewall 65b) of the source structure 65.
  • the bottom of the high concentration region 24 may be located on the bottom side of the second semiconductor region 7 relative to the bottom wall 65c of the source structure 65.
  • semiconductor device 1C includes a plurality of n-type medium concentration regions 25 formed in the chip 2 (second semiconductor region 7) in regions below the plurality of high concentration regions 24.
  • the plurality of medium concentration regions 25 are formed in regions between the plurality of gate structures 15 and the plurality of source structures 65.
  • the plurality of medium concentration regions 25 are each formed in a thickness range between the bottom of the second semiconductor region 7 and the bottom of the plurality of high concentration regions 24.
  • the plurality of medium concentration regions 25 each have a portion interposed in a region between the plurality of well regions 22 and the plurality of second well regions 72.
  • the plurality of medium concentration regions 25 each have a portion interposed in a region between the plurality of gate structures 15 and the plurality of source structures 65.
  • the multiple medium concentration regions 25 extend in a band shape along the multiple gate structures 15 and the multiple source structures 65 in a plan view.
  • the multiple medium concentration regions 25 are connected to either one or both of the adjacent well regions 22 and second well regions 72 (both in this embodiment).
  • the configuration of one medium concentration region 25 is described below.
  • the medium concentration region 25 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the medium concentration region 25 has an upper end located above the depth position of the bottom wall 65c of the source structure 65.
  • the upper end of the medium concentration region 25 is located in the region between the gate structure 15 and the source structure 65.
  • the upper end of the medium concentration region 25 faces the source structure 65 across the upper end (first extension 72a or second extension 72b) of the second well region 72.
  • the upper end of the medium concentration region 25 may have a portion connected to the source structure 65.
  • the medium concentration region 25 has a bottom that is located below the depth position of the bottom wall 65c of the source structure 65. Specifically, the bottom of the medium concentration region 25 is formed at a distance from the bottom of the second well region 72 toward the first main surface 3. It is preferable that the bottom of the medium concentration region 25 is located closer to the bottom of the second well region 72 than the bottom of the second high concentration well region 73.
  • the bottom of the medium concentration region 25 may be located closer to the bottom of the second semiconductor region 7 than the middle part of the second well region 72.
  • the bottom of the medium concentration region 25 may be located closer to the bottom wall 65c of the source structure 65 than the middle part of the second well region 72.
  • the semiconductor device 1C includes a plurality of channel regions 26 formed between a plurality of source regions 21 and a plurality of high concentration regions 24 in the body region 20.
  • the description of the plurality of channel regions 26 is omitted because it is similar to the case of the semiconductor device 1A.
  • the semiconductor device 1C includes a plurality of first contact regions 27 formed in regions along the plurality of gate structures 15 in the surface layer portion of the first main surface 3.
  • the plurality of first contact regions 27 are each formed in the body region 20 in regions between the plurality of gate structures 15 and the plurality of source structures 65.
  • the multiple first contact regions 27 are formed on both sides of the multiple gate structures 15 and on both sides of the multiple source structures 65.
  • the multiple first contact regions 27 are arranged at intervals in the second direction Y along the multiple gate structures 15 and the multiple source structures 65, and are each formed in a strip shape extending in the second direction Y.
  • the multiple first contact regions 27 are formed so as to overlap the body region 20, increasing the p-type impurity concentration of the body region 20.
  • the other first contact region 27 faces the first contact region 27 across the source structure 65 (gate structure 15).
  • the multiple first contact regions 27 are arranged in a matrix as a whole in a plan view.
  • the configuration of one first contact region 27 will be described below.
  • the first contact region 27 is formed in a layer extending horizontally along the first main surface 3, and is connected to either or both of the gate structure 15 and the source structure 65 (both in this embodiment).
  • the first contact region 27 faces the second buried electrode 68 of the source structure 65, with the second insulating film 67 of the source structure 65 in between.
  • the bottom of the first contact region 27 is located on the bottom side of the body region 20 relative to the depth position of the bottom of the recess of the second buried electrode 68. In this embodiment, the bottom of the first contact region 27 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 65c of the source structure 65. Of course, the bottom of the first contact region 27 may also be located closer to the first main surface 3 than the depth position of the bottom wall 65c of the source structure 65.
  • the first contact region 27 overlaps part or all (all in this embodiment) of the high concentration region 24 in a cross-sectional view, as in the case of the semiconductor device 1A.
  • the first contact region 27 has a bottom that crosses the bottom of the high concentration region 24 and is positioned within the medium concentration region 25.
  • the bottom of the first contact region 27 overlaps the upper end of the well region 22 (first extension 72a and second extension 72b).
  • the first contact region 27 has a high concentration portion 27a and a low concentration portion 27b, as in the case of the semiconductor device 1A.
  • the high concentration portion 27a is formed at least closer to the first main surface 3 than the depth position of the bottom wall 65c of the source structure 65, and extends in a layer in the horizontal direction along the first main surface 3.
  • the high concentration portion 27a is connected to the gate structure 15 and the source structure 65.
  • the low concentration portion 27b crosses the depth position of the bottom wall 65c of the source structure 65 in the thickness direction.
  • the low concentration portion 27b has a portion located closer to the first main surface 3 than the depth position of the bottom wall 65c of the source structure 65, and a portion located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom wall 65c of the source structure 65.
  • the low concentration portion 27b overlaps the upper ends of the multiple second well regions 72 and is electrically connected to the multiple second well regions 72.
  • the low concentration portion 27b may be located only on the first main surface 3 side from the depth position of the bottom wall 65c of the source structure 65 depending on the thickness of the high concentration portion 27a.
  • the low concentration portion 27b may be located only on the bottom side of the second semiconductor region 7 from the depth position of the bottom wall 65c of the source structure 65 depending on the thickness of the high concentration portion 27a.
  • the semiconductor device 1C includes a plurality of second contact regions 28 formed in the chip 2 in regions along the bottom walls 15c of the plurality of gate structures 15.
  • the description of the plurality of second contact regions 28 is omitted because it is similar to the semiconductor device 1A.
  • the semiconductor device 1C includes a plurality of third contact regions 78 formed in regions along the bottom walls 65c of the plurality of source structures 65 in the chip 2.
  • the plurality of third contact regions 78 are formed in a manner similar to the plurality of second contact regions 28, and have a p-type impurity concentration approximately equal to the p-type impurity concentration of the plurality of second contact regions 28.
  • the third contact regions 78 are formed in a one-to-many correspondence with the bottom walls 65c of the source structures 65.
  • the third contact regions 78 are each interposed in the region between the first contact regions 27 adjacent to each other in the first direction X in a plan view. In other words, the third contact regions 78 are positioned on the same straight line as the first contact regions 27 in the first direction X.
  • the multiple third contact regions 78 are formed in the regions between the multiple well regions 22 (second contact regions 28) at intervals in the first direction X from the multiple well regions 22 (second contact regions 28).
  • the multiple third contact regions 78 are each formed in a strip shape extending along the bottom wall 65c of the corresponding source structure 65 in a plan view, and face the second buried electrode 68 with the second insulating film 67 in between.
  • the length of the multiple third contact regions 78 is approximately equal to the length of the multiple first contact regions 27.
  • the length of the multiple third contact regions 78 is approximately equal to the length of the multiple second contact regions 28.
  • the spacing between the multiple third contact regions 78 is approximately equal to the spacing between the multiple first contact regions 27.
  • the spacing between the multiple third contact regions 78 is approximately equal to the spacing between the multiple second contact regions 28.
  • the configuration of one third contact region 78 will be described below.
  • the third contact region 78 is formed in one corresponding second well region 72.
  • the third contact region 78 overlaps with the second high concentration well region 73 and is electrically connected to the second high concentration well region 73 within the second well region 72.
  • the third contact region 78 is formed at a distance inward from the peripheral portion of the second well region 72.
  • the third contact region 78 is formed at a distance from the bottom of the second well region 72 toward the bottom wall 65c of the source structure 65, and faces the bottom of the second semiconductor region 7 across a portion of the second well region 72.
  • the third contact regions 78 are each formed in a columnar shape extending in the thickness direction (vertical direction Z) of the second semiconductor region 7 in a cross-sectional view.
  • the third contact region 78 has a bottom that is located closer to the bottom of the second well region 72 than the thickness position of the intermediate portion of the second well region 72.
  • the bottom of the third contact region 78 may be located closer to the bottom wall 65c of the source structure 65 than the thickness position of the intermediate portion of the second well region 72.
  • the bottom of the third contact region 78 is located closer to the bottom wall 65c of the source structure 65 than the bottom of the medium concentration region 25.
  • the bottom of the third contact region 78 may be located closer to the bottom of the second semiconductor region 7 than the bottom of the medium concentration region 25.
  • the third contact region 78 may be formed to cross the bottom of the second well region 72 and have a bottom located within the second semiconductor region 7.
  • the thickness of the third contact region 78 is preferably approximately equal to the thickness of the second contact region 28.
  • the thickness of the third contact region 78 may be greater than the thickness of the second contact region 28, or may be less than the thickness of the second contact region 28.
  • the third contact region 78 has an upper end that is aligned with a corner of the bottom wall 65c of the source structure 65.
  • the third contact region 78 is electrically connected to a plurality of first contact regions 27 at its upper end.
  • the third contact region 78 electrically connects the second well region 72 and the second high concentration well region 73 to the body region 20 via the plurality of first contact regions 27.
  • the third contact region 78 has a first extension 78a on the first sidewall 65a side and a second extension 78b on the second sidewall 65b side.
  • the first extension 78a is extended from the region directly below the source structure 65 to the lower end of the first sidewall 65a.
  • the first extension 78a faces the second buried electrode 68 across the second insulating film 67 in the horizontal direction.
  • the first extension 78a is connected to the first contact region 27 in a region along the first sidewall 65a. Specifically, the first extension 78a is connected to both the high concentration portion 27a and the low concentration portion 27b of the first contact region 27.
  • the second extension 78b is drawn out from the region directly below the source structure 65 to the lower end of the second sidewall 65b, and faces the second extension 78b across the source structure 65.
  • the second extension 78b faces the second buried electrode 68 across the second insulating film 67 in the horizontal direction.
  • the second extension 78b is connected to the first contact region 27 in the region along the second sidewall 65b. Specifically, the second extension 78b is connected to both the high concentration portion 27a and the low concentration portion 27b of the first contact region 27.
  • the third contact region 78 has one or more (multiple in this embodiment) fourth bulges 78c.
  • a third contact region 78 having two fourth bulges 78c is illustrated. The number of fourth bulges 78c is adjusted as appropriate by adjusting the process conditions.
  • the multiple fourth bulges 78c are each formed by a portion of the third contact region 78 whose width in the horizontal direction (first direction X) gradually increases or decreases in the thickness direction, and are formed in multiple stages from the bottom wall 65c of the source structure 65 toward the bottom of the second semiconductor region 7.
  • the multiple fourth bulges 78c extend in an arc shape (circular arc) from the region directly below the source structure 65 to both sides of the source structure 65.
  • the single third bulge 72c may be formed to extend in an arc shape (circular arc) to both sides of the source structure 65 in the middle of the third contact region 78.
  • the semiconductor device 1C includes a main surface insulating film 30 that covers the first main surface 3.
  • the main surface insulating film 30 is connected to the insulating film 17 at the first surface portion 8, exposing the buried electrode 18.
  • the main surface insulating film 30 is connected to the second insulating film 67 at the periphery of the first surface portion 8, exposing the second buried electrode 68.
  • the semiconductor device 1C includes an interlayer film 31 that covers the main surface insulating film 30.
  • the interlayer film 31 covers a plurality of gate structures 15 (buried electrodes 18) on the first surface portion 8.
  • the interlayer film 31 covers a plurality of source structures 65 (second buried electrodes 68) on the periphery of the first surface portion 8.
  • the semiconductor device 1C includes a plurality of source openings 32 and a plurality of gate openings 33 (see FIG. 3) formed in the interlayer film 31.
  • the plurality of source openings 32 are formed in a one-to-one correspondence with the plurality of source structures 65.
  • Each of the plurality of source openings 32 exposes a corresponding one of the source structures 65, the plurality of source regions 21, and the plurality of first contact regions 27. It is preferable that each of the plurality of source openings 32 has an opening end curved in an arc shape.
  • the multiple source openings 32 are formed in a band shape extending in the second direction Y along the corresponding source structures 65.
  • the multiple source openings 32 may be formed in a one-to-many correspondence with the corresponding source structures 65. In this case, the multiple source openings 32 may be formed at intervals along the corresponding source structure 65. Also, in this case, the multiple source openings 32 may be formed in a square shape, a rectangular shape (band shape), a circle shape, etc. in a plan view.
  • the semiconductor device 1C includes a source electrode 35, a gate electrode 40, a gate wiring 41, and a drain electrode 42 arranged on the first main surface 3.
  • the description of the gate electrode 40, the gate wiring 41, and the drain electrode 42 is omitted because they are similar to those of the semiconductor device 1A.
  • the source electrode 35 penetrates into the multiple source openings 32 from above the interlayer film 31, and is electrically connected to the multiple source structures 65, the multiple source regions 21, and the multiple first contact regions 27 within the multiple source openings 32. Specifically, the source electrode 35 covers the first main surface 3 (first surface portion 8) within the multiple source openings 32, and is mechanically and electrically connected to the multiple source structures 65, the multiple source regions 21, and the multiple first contact regions 27 on the first main surface 3.
  • the source electrode 35 extends further into the second trenches 66 from above the first main surface 3, and is mechanically and electrically connected to the second buried electrode 68, the source regions 21, and the first contact regions 27 within the second trenches 66.
  • the source electrode 35 has a layered structure including a lower electrode film 36 and a main electrode film 37, which are layered in this order from the chip 2 side, as in the case of the semiconductor device 1A.
  • the lower electrode film 36 has a layered structure including a first electrode film 38 and a second electrode film 39.
  • the first electrode film 38 collectively covers the region of the interlayer film 31 where the multiple source openings 32 are formed, and extends from above the interlayer film 31 into the multiple source openings 32.
  • the first electrode film 38 has a portion that covers the insulating main surface of the interlayer film 31 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 32 in a film-like manner, a portion that covers the first main surface 3 within the multiple source openings 32 in a film-like manner, and a portion that covers the multiple source structures 65 in a film-like manner.
  • the first electrode film 38 directly covers the insulating main surface of the interlayer film 31 and faces the gate structure 15 across the interlayer film 31.
  • the first electrode film 38 extends in an arc shape from above the insulating main surface of the interlayer film 31 following the opening edge of the source opening 32, and covers the wall surface of the source opening 32 in a film shape.
  • the first electrode film 38 covers the first main surface 3 in the source opening 32 in the form of a film, and is mechanically and electrically connected to the multiple source regions 21 and the multiple first contact regions 27 on the first main surface 3.
  • the first electrode film 38 penetrates into the second trench 66 from above the first main surface 3, and in the second trench 66 covers the first sidewall 65a, the second sidewall 65b, the second insulating film 67, and the second buried electrode 68 in a film-like manner.
  • the first electrode film 38 is mechanically and electrically connected to the second buried electrode 68, the multiple source regions 21, and the multiple first contact regions 27.
  • the second electrode film 39 directly covers the first electrode film 38.
  • the second electrode film 39 collectively covers the area of the interlayer film 31 in which the multiple source openings 32 are formed, sandwiching the first electrode film 38 between them, and penetrates into the multiple source openings 32 from above the interlayer film 31.
  • the second electrode film 39 has a portion that covers the insulating main surface of the interlayer film 31 in a film-like manner by sandwiching the first electrode film 38, a portion that covers the wall surfaces of the multiple source openings 32 in a film-like manner by sandwiching the first electrode film 38, a portion that covers the first main surface 3 in the multiple source openings 32 in a film-like manner by sandwiching the first electrode film 38, and a portion that covers the multiple source structures 65 in a film-like manner by sandwiching the first electrode film 38.
  • the second electrode film 39 covers the insulating main surface of the interlayer film 31 with the first electrode film 38 in between, and faces the gate structure 15 with the interlayer film 31 and the first electrode film 38 in between.
  • the second electrode film 39 covers the opening end of the source opening 32 in an arc shape with the first electrode film 38 in between, and covers the wall surface of the source opening 32 in a film shape with the first electrode film 38 in between.
  • the second electrode film 39 covers the first main surface 3 in the source opening 32 with the first electrode film 38 sandwiched therebetween, and is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 via the first electrode film 38.
  • the second electrode film 39 enters the second trench 66 from above the first main surface 3, and in the second trench 66, sandwiches the first electrode film 38, covering the first sidewall 65a, the second sidewall 65b, the second insulating film 67, and the second buried electrode 68 in a film-like manner.
  • the second electrode film 39 is electrically connected to the second buried electrode 68, the multiple source regions 21, and the multiple first contact regions 27 via the first electrode film 38.
  • the main electrode film 37 directly covers the lower electrode film 36 (second electrode film 39).
  • the main electrode film 37 backfills the second trenches 66 and the source openings 32 with the lower electrode film 36 in between, and collectively covers the region of the interlayer film 31 in which the source openings 32 are formed with the lower electrode film 36 in between.
  • the main electrode film 37 has a portion that covers the insulating main surface of the interlayer film 31 with the lower electrode film 36 in between, a portion that covers the wall surfaces of the multiple source openings 32 with the lower electrode film 36 in between, a portion that covers the first main surface 3 with the lower electrode film 36 in between, and a portion that covers the second trench 66 with the lower electrode film 36 in between.
  • the main electrode film 37 covers the insulating main surface of the interlayer film 31 with the lower electrode film 36 in between, and faces the gate structure 15 with the interlayer film 31 and the lower electrode film 36 in between.
  • the main electrode film 37 covers the opening end of the source opening 32 with the lower electrode film 36 in between.
  • the main electrode film 37 covers the first main surface 3 within the source opening 32 with the lower electrode film 36 in between, and is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 via the lower electrode film 36.
  • the main electrode film 37 enters the second trench 66 from above the first major surface 3, and within the second trench 66, sandwiching the lower electrode film 36 to cover the first sidewall 65a, the second sidewall 65b, the second insulating film 67, and the second buried electrode 68.
  • the main electrode film 37 is electrically connected to the second buried electrode 68, the source region 21, and the first contact region 27 via the lower electrode film 36 within the second trench 66.
  • Semiconductor device 1C is manufactured by modifying the layout of various masks in the manufacturing method of semiconductor device 1A.
  • source structure 65 is formed simultaneously with gate structure 15 by utilizing the formation process of gate structure 15.
  • second well region 72 is formed simultaneously with well region 22 by utilizing the formation process of well region 22.
  • the second high-concentration well region 73 is formed simultaneously with the high-concentration well region 23 by utilizing the formation process of the high-concentration well region 23.
  • the third contact region 78 is formed simultaneously with the first contact region 27 (second contact region 28) by utilizing the formation process of the first contact region 27 (second contact region 28).
  • FIG. 17 is a cross-sectional view showing a main portion of a semiconductor device 1D according to the fourth embodiment.
  • the semiconductor device 1D includes a plurality of well regions 22 formed as column regions forming a super junction structure, and a plurality of second well regions 72 formed as column regions forming a super junction structure.
  • the multiple well regions 22 and the multiple second well regions 72 are each formed in a columnar shape extending in the thickness direction in a cross-sectional view.
  • the semiconductor device 1D includes a plurality of n-type intermediate drift regions 64 formed in the second semiconductor region 7.
  • Each of the plurality of intermediate drift regions 64 is made up of a region partitioned between the plurality of well regions 22 and the plurality of second well regions 72 in the second semiconductor region 7. That is, in this embodiment, the plurality of intermediate drift regions 64 each include a part of the second semiconductor region 7, a high concentration region 24, and a medium concentration region 25.
  • the multiple intermediate drift regions 64 are arranged alternately with the multiple well regions 22 and the multiple second well regions 72 in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the multiple intermediate drift regions 64 are formed in a stripe shape extending in the second direction Y along the multiple well regions 22 and the multiple second well regions 72.
  • the extension direction of the multiple intermediate drift regions 64 coincides with the off-direction of the SiC single crystal.
  • the multiple intermediate drift regions 64 are formed in a columnar shape extending in the thickness direction in a cross-sectional view, and face the multiple body regions 20 in a one-to-one correspondence.
  • the intermediate drift regions 64 form a plurality of pn junctions having charge balance with the well regions 22 and the second well regions 72 in the thickness range below the gate structures 15.
  • the state of having charge balance means a state in which the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the intermediate drift region 64 with respect to the adjacent well regions 22 and second well regions 72.
  • first to eighth modified examples of semiconductor devices 1A to 1D are shown with reference to Figures 18 to 25.
  • Figures 18 to 25 show examples in which the first to eighth embodiments are applied to semiconductor device 1A, but the first to eighth embodiments can also be applied to semiconductor devices 1B to 1D.
  • the semiconductor devices 1A to 1D according to the first modification do not have the well region 22, the high-concentration well region 23, the first contact region 27, and the second contact region 28.
  • the multiple medium concentration regions 25 are integrated directly below the multiple gate structures 15, and are formed as a single medium concentration region 25 extending along the horizontal direction.
  • the single medium concentration region 25 corresponds to the base medium concentration region 52 described above.
  • the second well region 72, the second high concentration well region 73, and the third contact region 78 are further removed.
  • the multiple medium concentration regions 25 are integrated directly below the multiple gate structures 15 and directly below the multiple source structures 65, and are formed as a single medium concentration region 25 extending along the horizontal direction.
  • the semiconductor devices 1A to 1D according to the second modification do not have the medium concentration region 25.
  • the semiconductor devices 1A to 1D according to the third modification have a configuration in which the well region 22 (second well region 72), the high concentration well region 23 (second high concentration well region 73), the first contact region 27, and the second contact region 28 (third contact region 78) have been removed from the configuration of the semiconductor devices 1A to 1D according to the second modification.
  • the semiconductor devices 1A to 1D according to the fourth modification do not have the high concentration region 24.
  • the medium concentration region 25 is formed in the region below the body region 20 as the high concentration region 24 having an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.
  • the medium concentration region 25 has a portion formed in the second semiconductor region 7 in a thickness range between the bottom wall 15c of the gate structure 15 (source structure 65) and the bottom of the body region 20.
  • the resistance value near the gate structure 15 is reduced by the medium concentration region 25 formed below the body region 20.
  • the medium concentration region 25 offsets undesired p-type impurities introduced to the side of the gate structure 15 due to process errors, etc.
  • the semiconductor devices 1A to 1D according to the fifth modification have a configuration in which the well region 22 (second well region 72), the high concentration well region 23 (second high concentration well region 73), the first contact region 27, and the second contact region 28 (third contact region 78) are removed from the configuration of the semiconductor devices 1A to 1D according to the fourth modification.
  • the semiconductor devices 1A to 1D according to the sixth modification include a plurality of high concentration regions 24 formed in the second semiconductor region 7 at a distance from the plurality of gate structures 15.
  • the plurality of high concentration regions 24 face the sidewalls of the plurality of gate structures 15, sandwiching a portion of the medium concentration region 25 therebetween.
  • the multiple high concentration regions 24 face the sidewalls of the multiple gate structures 15, sandwiching a portion of the second semiconductor region 7 between them.
  • the multiple high concentration regions 24 may have approximately the same n-type impurity concentration as each other, or may have different n-type impurity concentrations as each other.
  • the multiple high concentration regions 24 are formed at intervals from the multiple gate structures 15 toward the multiple source structures 65.
  • the multiple high concentration regions 24 may be connected to the multiple source structures 65.
  • the multiple high concentration regions 24 may also be formed at intervals from the multiple source structures 65 toward the multiple gate structures 15.
  • the high concentration region 24 in the sixth modified example is obtained by introducing n-type impurities into the second semiconductor region 7 through a mask having a number of openings that expose the regions in which the high concentration regions 24 are to be formed during the process of forming the high concentration regions 24.
  • semiconductor devices 1A to 1D according to the seventh modification include a plurality of high concentration regions 24 formed in regions along the lower ends of the sidewalls (first sidewall 15a and second sidewall 15b) of a plurality of gate structures 15 in the second semiconductor region 7.
  • the multiple high concentration regions 24 are formed at intervals in the regions between the multiple gate structures 15, and face each other with a portion of the second semiconductor region 7 in between.
  • the multiple high concentration regions 24 may extend in the vertical direction Z along the side walls (first side wall 15a and second side wall 15b) of the multiple gate structures 15.
  • the multiple high concentration regions 24 may be formed so as to bulge outward from the side walls (first side wall 15a and second side wall 15b) of the multiple gate structures 15.
  • the plurality of medium concentration regions 25 have portions interposed between the plurality of high concentration regions 24 in the regions between the plurality of gate structures 15.
  • the plurality of medium concentration regions 25 are electrically connected to the bottoms of the plurality of body regions 20.
  • the multiple high concentration regions 24 are formed in regions along the lower ends of the sidewalls (first sidewall 15a and second sidewall 15b) of the multiple gate structures 15, spaced apart from the multiple source structures 65.
  • the high concentration region 24 in the seventh modification is obtained by introducing an n-type impurity into the second semiconductor region 7 through the sidewalls (first sidewall 15a and second sidewall 15b) of the trench 16 of the gate structure 15.
  • the n-type impurity may be introduced into the second semiconductor region 7 by oblique ion implantation.
  • semiconductor devices 1A to 1D include gate structures 15 each having a trench 16, an insulating film 17, a buried electrode 18, and a buried insulator 80.
  • the buried insulator 80 is buried in the trench 16 so as to expose the first main surface 3, and covers the insulating film 17 and the buried electrode 18 within the trench 16.
  • the buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the buried insulator 80 includes a silicon oxide film.
  • the source electrode 35 has a portion that directly covers the first major surface 3 and a portion that directly covers the buried insulator 80.
  • the source electrode 35 is electrically connected to the multiple source regions 21 and the multiple first contact regions 27 on the first major surface 3, and is electrically insulated from the multiple buried electrodes 18 by the buried insulator 80. With this configuration, the connection area of the source electrode 35 to the multiple source regions 21 and the multiple first contact regions 27 is increased.
  • the chip 2 including single crystal SiC is used.
  • the chip 2 may include a wide band gap semiconductor single crystal other than single crystal SiC.
  • a wide band gap semiconductor is a semiconductor that has a band gap larger than the band gap of silicon.
  • the chip 2 may include gallium nitride, gallium oxide, diamond, etc.
  • the chip 2 may include single crystal silicon.
  • the first semiconductor region 6 may contain a wide band gap semiconductor single crystal other than a SiC single crystal.
  • the first semiconductor region 6 may contain gallium nitride, gallium oxide, diamond, etc.
  • the first semiconductor region 6 may also contain a silicon single crystal.
  • the second semiconductor region 7 may contain a wide band gap semiconductor single crystal other than a SiC single crystal.
  • the second semiconductor region 7 may contain gallium nitride, gallium oxide, diamond, etc.
  • the second semiconductor region 7 may also contain a silicon single crystal.
  • a p-type collector region may be formed in the surface layer of the second main surface 4 of the chip 2.
  • the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.
  • the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure. The specific configuration in this case is obtained by replacing the "source" of the MISFET structure with the "emitter” of the IGBT structure and the "drain” of the MISFET structure with the "collector” of the IGBT structure in the above explanation.
  • IGBT Insulated Gate Bipolar Transistor
  • a semiconductor device (1A-1D) including: a chip (2) having a main surface (3); a semiconductor region (7) of a first conductivity type (n-type) formed on the main surface (3); a trench-type gate structure (15) formed on the main surface (3) and positioned within the semiconductor region (7); a body region (20) of a second conductivity type (p-type) formed in a region on the main surface (3) side with respect to a depth position of a bottom wall (15c) of the gate structure (15) in a surface layer portion of the main surface (3); and a high-concentration region (24) of the first conductivity type (n-type) formed in the chip (2) in a thickness range between the bottom wall (15c) of the gate structure (15) and the bottom of the body region (20) and having an impurity concentration higher than the impurity concentration of the semiconductor region (7).
  • a semiconductor device (1A-1D) according to any one of A1 to A9, further including a first conductivity type (n-type) impurity region (21) formed in a region on the main surface (3) side of the body region (20) along the gate structure (15), the high concentration region (24) facing the impurity region (21) across a portion of the body region (20), and a channel (26) formed between the impurity region (21) and the high concentration region (24) within the body region (20).
  • n-type impurity region (21) formed in a region on the main surface (3) side of the body region (20) along the gate structure (15)
  • the high concentration region (24) facing the impurity region (21) across a portion of the body region (20)
  • a channel (26) formed between the impurity region (21) and the high concentration region (24) within the body region (20).
  • a well region (22) of a second conductivity type (p-type) formed in a region along the bottom wall (15c) of the gate structure (15) within the chip (2).
  • a contact region (27) of a second conductivity type (p-type) formed in a region along the sidewall of the gate structure (15) within the chip (2) and having an impurity concentration higher than the impurity concentration of the body region (20).
  • a bottom contact region (28) of a second conductivity type (p-type) formed in a region along the bottom wall (15c) of the gate structure (15) within the chip (2) and having an impurity concentration higher than the impurity concentration of the body region (20).
  • n-type first conductivity type

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WO2017038518A1 (ja) * 2015-09-04 2017-03-09 株式会社デンソー 炭化珪素半導体装置
JP2018026562A (ja) * 2016-08-05 2018-02-15 国立研究開発法人産業技術総合研究所 半導体装置および半導体装置の製造方法
JP2018107167A (ja) * 2016-12-22 2018-07-05 国立研究開発法人産業技術総合研究所 半導体装置および半導体装置の製造方法
JP2018186305A (ja) * 2015-03-03 2018-11-22 インフィネオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ ダイオード領域用のゲート電極とコンタクト構造とを含んでいるトレンチ構造を備えた半導体デバイス
JP2021182639A (ja) * 2017-06-06 2021-11-25 三菱電機株式会社 半導体装置および電力変換装置
JP2022120620A (ja) * 2021-02-05 2022-08-18 三菱電機株式会社 半導体装置およびその製造方法

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JP2018186305A (ja) * 2015-03-03 2018-11-22 インフィネオン テクノロジーズ アクチエンゲゼルシャフトＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ ＡＧ ダイオード領域用のゲート電極とコンタクト構造とを含んでいるトレンチ構造を備えた半導体デバイス
WO2017038518A1 (ja) * 2015-09-04 2017-03-09 株式会社デンソー 炭化珪素半導体装置
JP2018026562A (ja) * 2016-08-05 2018-02-15 国立研究開発法人産業技術総合研究所 半導体装置および半導体装置の製造方法
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JP2021182639A (ja) * 2017-06-06 2021-11-25 三菱電機株式会社 半導体装置および電力変換装置
JP2022120620A (ja) * 2021-02-05 2022-08-18 三菱電機株式会社 半導体装置およびその製造方法

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