WO2024248020A1 - 電子部品 - Google Patents

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Publication number
WO2024248020A1
WO2024248020A1 PCT/JP2024/019655 JP2024019655W WO2024248020A1 WO 2024248020 A1 WO2024248020 A1 WO 2024248020A1 JP 2024019655 W JP2024019655 W JP 2024019655W WO 2024248020 A1 WO2024248020 A1 WO 2024248020A1
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WIPO (PCT)
Prior art keywords
electrode
source
film
wiring
region
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Ceased
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PCT/JP2024/019655
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN202480036264.4A priority Critical patent/CN121241431A/zh
Priority to JP2025524122A priority patent/JPWO2024248020A1/ja
Priority to DE112024002407.6T priority patent/DE112024002407T5/de
Publication of WO2024248020A1 publication Critical patent/WO2024248020A1/ja
Priority to US19/404,127 priority patent/US20260090013A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations

Definitions

  • Patent document 1 discloses a semiconductor device including a semiconductor substrate, an interlayer insulating layer, an electrode, an inorganic protective layer, and an organic protective layer.
  • the interlayer insulating layer is formed on the semiconductor substrate and has an opening that exposes the semiconductor substrate.
  • the electrode penetrates into the opening from above the interlayer insulating layer and is electrically connected to the semiconductor substrate within the opening.
  • the inorganic protective layer covers the edge of the electrode.
  • the organic protective layer covers the electrode and the interlayer insulating layer with the inorganic protective layer sandwiched therebetween.
  • the present disclosure provides an electronic component having a novel layout.
  • the present disclosure provides an electronic component including an object to be coated, an electrode disposed on the object to be coated and having an electrode sidewall on the object to be coated, wiring disposed around the electrode on the object to be coated, an insulating inorganic film having an inner coating portion that covers the electrode so as to expose the electrode sidewall, and an outer coating portion that covers the wiring at a distance from the inner coating portion, and an insulating organic film that spans the inner coating portion and the outer coating portion and covers the electrode between the inner coating portion and the outer coating portion.
  • the present disclosure provides an electronic component including a terminal electrode, wiring arranged around the terminal electrode, an insulating inorganic film covering the wiring at a distance from the terminal electrode, and an insulating organic film having a portion that directly covers the electrode and a portion that covers the wiring with the inorganic film sandwiched therebetween.
  • the present disclosure provides an electronic component including an electrode disposed in a first region having a first electric field, wiring disposed in a second region having a second electric field higher than the first electric field around the electrode, an insulating inorganic film exposing the electrode and covering the wiring, and an insulating organic film having a portion that directly covers the electrode and a portion that covers the wiring with the inorganic film sandwiched therebetween.
  • the present disclosure provides an electronic component including a chip having a main surface, an active region provided on the inside of the main surface, a peripheral region provided on the periphery of the main surface, a device structure formed on the main surface in the active region, an impurity region formed on a surface layer of the main surface in the peripheral region, an electrode disposed on the main surface in the active region and electrically connected to the device structure, a wiring disposed on the main surface in the peripheral region and electrically connected to the impurity region, an insulating inorganic film exposing the electrode and covering the wiring, and an insulating organic film having a portion directly covering the electrode and a portion covering the wiring with the inorganic film sandwiched therebetween.
  • the present disclosure provides an electronic component including a coating target, a gate electrode disposed on the coating target and having an electrode sidewall on the coating target, a gate wiring disposed around the gate electrode on the coating target, an insulating inorganic film having an inner coating portion that coats the gate electrode so as to expose the electrode sidewall, and an outer coating portion that coats the gate wiring at a distance from the inner coating portion, and an insulating organic film that spans the inner coating portion and the outer coating portion and coats the gate electrode between the inner coating portion and the outer coating portion.
  • the present disclosure provides an electronic component including a coating target, a source electrode disposed on the coating target and having an electrode sidewall on the coating target, a gate wiring disposed around the source electrode on the coating target, an insulating inorganic film having an inner coating portion that covers the source electrode so as to expose the electrode sidewall, and an outer coating portion that is spaced apart from the inner coating portion and covers the gate wiring, and an insulating organic film that spans the inner coating portion and the outer coating portion and covers the source electrode between the inner coating portion and the outer coating portion.
  • the present disclosure provides an electronic component including a coating target, a gate electrode disposed on the coating target and having an electrode sidewall on the coating target, a source wiring disposed around the gate electrode on the coating target, an insulating inorganic film having an inner coating portion that coats the gate electrode so as to expose the electrode sidewall, and an outer coating portion that coats the source wiring at a distance from the inner coating portion, and an insulating organic film that spans the inner coating portion and the outer coating portion and coats the gate electrode between the inner coating portion and the outer coating portion.
  • FIG. 1 is a plan view showing a semiconductor device.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a cross-sectional view taken along line III-III shown in FIG.
  • FIG. 4 is a plan view showing an example of the layout of the first main surface.
  • FIG. 5 is an enlarged plan view showing a main portion of the active region.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG.
  • FIG. 8 is an enlarged plan view showing a main portion of the first side end region.
  • FIG. 9 is a cross-sectional view taken along line IX-IX shown in FIG. FIG.
  • FIG. 10 is a cross-sectional view taken along line X-X shown in FIG.
  • FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIG.
  • FIG. 12 is a cross-sectional view taken along line XII-XII shown in FIG.
  • FIG. 13 is an enlarged plan view showing a main portion of the first termination region.
  • 14 is a cross-sectional view taken along the line XIV-XIV shown in FIG. 13.
  • FIG. FIG. 15 is an enlarged plan view showing a main portion of the third termination region.
  • 16 is a cross-sectional view taken along line XVI-XVI shown in FIG. 15.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG.
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG.
  • FIG. 19 is a plan view showing an example of the layout of main electrodes.
  • FIG. 20 is a plan view showing a first layout example of the second inorganic film.
  • FIG. 21 is an enlarged plan view showing a main portion of the second inorganic film.
  • FIG. 22A is a cross-sectional view showing a second layout example of the second inorganic film.
  • FIG. 22B is a cross-sectional view showing a third layout example of the second inorganic film.
  • FIG. 22C is a cross-sectional view showing a fourth layout example of the second inorganic film.
  • FIG. 22D is a cross-sectional view showing a fifth layout example of the second inorganic film.
  • FIG. 22E is a cross-sectional view showing a sixth layout example of the second inorganic film.
  • FIG. 22F is an enlarged plan view showing a seventh layout example of the second inorganic film.
  • FIG. 22G is an enlarged plan view showing an eighth layout example of the second inorganic film.
  • FIG. 22H is an enlarged plan view showing a ninth layout example of the second inorganic film.
  • FIG. 22I is an enlarged plan view showing a tenth layout example of the second inorganic film.
  • FIG. 22J is an enlarged plan view showing an eleventh layout example of the second inorganic film.
  • FIG. 22K is an enlarged plan view showing a twelfth layout example of the second inorganic film.
  • FIG. 22E is a cross-sectional view showing a sixth layout example of the second inorganic film.
  • FIG. 22F is an enlarged plan view showing a seventh layout example of the second inorganic film.
  • FIG. 22G is an enlarged plan view showing
  • FIG. 22L is a cross-sectional view showing a thirteenth layout example of the second inorganic film.
  • FIG. 22M is a cross-sectional view showing a fourteenth layout example of the second inorganic film.
  • FIG. 22N is a cross-sectional view showing a fifteenth layout example of the second inorganic film.
  • FIG. 22O is a cross-sectional view showing a 16th layout example of the second inorganic film.
  • FIG. 22P is a cross-sectional view showing a 17th layout example of the second inorganic film.
  • FIG. 22Q is a cross-sectional view showing an 18th layout example of the second inorganic film.
  • FIG. 22R is a cross-sectional view showing a 19th layout example of the second inorganic film.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1 (electronic component).
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. 1.
  • FIG. 4 is a plan view showing an example layout of a first main surface 3.
  • the semiconductor device 1 is a semiconductor switching device including an insulated gate type transistor structure Tr.
  • the transistor structure Tr may be referred to as a MISFET structure (Metal Insulator Semiconductor Field Effect Transistor structure).
  • semiconductor device 1 includes chip 2 that includes a single crystal of a wide bandgap semiconductor and is formed in a hexahedral shape (specifically, a rectangular parallelepiped shape).
  • semiconductor device 1 is a "wide bandgap semiconductor device.”
  • Chip 2 may be referred to as a “semiconductor chip,” a “wide bandgap semiconductor chip,” etc.
  • a wide bandgap semiconductor is a semiconductor that has a bandgap that exceeds the bandgap of Si (silicon).
  • Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).
  • chip 2 is a "SiC chip” that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor.
  • semiconductor device 1 is a "SiC semiconductor device.”
  • the semiconductor device 1 may be referred to as a "SiC-MISFET.”
  • the hexagonal SiC single crystal has multiple polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, and the like.
  • the chip 2 includes a 4H-SiC single crystal, but the chip 2 may include other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal
  • the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal.
  • the first direction X may be the m-axis direction of the SiC single crystal
  • the second direction Y may be the a-axis direction of the SiC single crystal.
  • the direction extending along the first main surface 3 may be referred to as the "horizontal direction.”
  • the horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.
  • the first main surface 3 and the second main surface 4 may have an off angle inclined at a predetermined angle in a predetermined off direction with respect to the c-plane.
  • the off direction is preferably the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the off angle may be greater than 0° and less than or equal to 10°.
  • the off angle is preferably less than or equal to 5°.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical line toward the off direction by the off angle.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the first direction X).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the semiconductor device 1 includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4 of the chip 2.
  • a drain potential is applied to the first semiconductor region 6 as a first potential (high potential).
  • the first semiconductor region 6 may be referred to as a "semiconductor layer,” a “first semiconductor layer,” a “drain region,” or the like.
  • the first semiconductor region 6 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) containing SiC single crystal (semiconductor single crystal), and forms the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • the first semiconductor region 6 (substrate) has the off direction and off angle described above.
  • the first semiconductor region 6 may have a thickness of 10 ⁇ m or more and 500 ⁇ m or less.
  • the thickness of the first semiconductor region 6 may have a value that belongs to at least one of the following ranges: 10 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 300 ⁇ m or less, 300 ⁇ m or more and 400 ⁇ m or less, and 400 ⁇ m or more and 500 ⁇ m or less.
  • the semiconductor device 1 includes an n-type second semiconductor region 7 formed in a surface layer of the first main surface 3 of the chip 2.
  • the second semiconductor region 7 may be referred to as a "semiconductor layer,” a “second semiconductor layer,” a “drift region,” or the like.
  • the second semiconductor region 7 has an n-type impurity concentration that is less than the n-type impurity concentration of the first semiconductor region 6.
  • the second semiconductor region 7 is formed in a layer extending along the first main surface 3, and is electrically connected to the first semiconductor region 6.
  • the second semiconductor region 7 is exposed from the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • the second semiconductor region 7 is made of an n-type semiconductor layer.
  • the second semiconductor region 7 is made of an n-type semiconductor layer.
  • the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) containing SiC single crystal (semiconductor single crystal), and forms the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2.
  • the second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above.
  • the second semiconductor region 7 preferably has a thickness less than that of the first semiconductor region 6.
  • the thickness of the second semiconductor region 7 may be greater than the thickness of the first semiconductor region 6.
  • the thickness of the second semiconductor region 7 may be greater than or equal to 5 ⁇ m and less than or equal to 50 ⁇ m.
  • the thickness of the second semiconductor region 7 may have a value that falls within at least one of the following ranges: 5 ⁇ m to 10 ⁇ m, 10 ⁇ m to 15 ⁇ m, 15 ⁇ m to 20 ⁇ m, 20 ⁇ m to 25 ⁇ m, 25 ⁇ m to 30 ⁇ m, 30 ⁇ m to 35 ⁇ m, 35 ⁇ m to 40 ⁇ m, 40 ⁇ m to 45 ⁇ m, and 45 ⁇ m to 50 ⁇ m.
  • the semiconductor device 1 includes a first surface portion 8, a second surface portion 9, and first to fourth connection surface portions 10A to 10D formed on the first main surface 3.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D define a mesa 11 on the first main surface 3.
  • the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D may be considered to be components of the chip 2 (first main surface 3).
  • the first surface portion 8 may be referred to as the "active surface”
  • the second surface portion 9 may be referred to as the “outer surface”
  • the first to fourth connecting surface portions 10A to 10D may be referred to as “connecting surfaces”
  • the mesa 11 may be referred to as the "active mesa”.
  • the first surface portion 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the first surface portion 8 has a flat surface extending horizontally, and is formed by a c-plane (Si-plane).
  • the first surface portion 8 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the planar area of the first surface portion 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the second surface portion 9 is located on the peripheral side of the first main surface 3 relative to the first surface portion 8, and is recessed from the height position of the first surface portion 8 in the thickness direction of the chip 2 (towards the second main surface 4).
  • the second surface portion 9 extends in a band shape along the first surface portion 8 in a plan view, and is formed in a ring shape (specifically, a square ring shape) surrounding the first surface portion 8.
  • the second surface portion 9 is connected to the first to fourth side surfaces 5A to 5D.
  • the second surface 9 is formed approximately parallel to the first surface 8, and has a flat surface extending horizontally.
  • the second surface 9 is formed by the c-plane (Si-plane).
  • the second surface 9 is formed in the second semiconductor region 7 with a space therebetween from the first semiconductor region 6. In other words, the second surface 9 is recessed to a depth less than the thickness of the second semiconductor region 7, exposing the second semiconductor region 7.
  • the second surface portion 9 has a depth of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second surface portion 9 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second surface portion 9 is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9.
  • the first connection surface portion 10A is located on the first side surface 5A side
  • the second connection surface portion 10B is located on the second side surface 5B side
  • the third connection surface portion 10C is located on the third side surface 5C side
  • the fourth connection surface portion 10D is located on the fourth side surface 5D side.
  • the first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y.
  • the third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.
  • the mesa 11 is defined as a protrusion (convex shape) on the first main surface 3.
  • the mesa 11 is formed only in the second semiconductor region 7, and not in the first semiconductor region 6.
  • the first to fourth connection surface portions 10A to 10D may extend approximately perpendicularly between the first surface portion 8 and the second surface portion 9, and define the mesa 11 in the shape of a rectangular pillar.
  • the first to fourth connection surface portions 10A to 10D may be inclined obliquely downward from the first surface portion 8 toward the second surface portion 9, and may define a mesa 11 in the shape of a truncated quadrangular pyramid.
  • the first to fourth connection surface portions 10A to 10D may be inclined at an angle of more than 90° and not more than 135° with respect to the first surface portion 8.
  • the semiconductor device 1 includes an active region 12, a first side end region 13, a second side end region 14, a first termination region 15, a second termination region 16, a third termination region 17, a fourth termination region 18, and a peripheral region 19 on the first main surface 3.
  • the active region 12 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 12 is set in the inner part of the first surface portion 8. Specifically, the active region 12 is provided in the inner part of the first surface portion 8 at a distance from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D).
  • the active region 12 is provided in a polygonal shape (specifically, a rectangular shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the proportion of the active region 12 in the first surface portion 8 is preferably 50% or more and 95% or less.
  • the proportion of the active region 12 may have a value that falls within any one of the following ranges: 50% or more and 60% or more, 60% or more and 70% or less, 70% or more and 80% or less, 80% or more and 90% or less, and 90% or more and 95% or less.
  • the proportion of the active region 12 is preferably 70% or more.
  • the first side end region 13 is provided on one side of the active region 12 in the first direction X (the third connection surface portion 10C side) on the first surface portion 8, and faces the active region 12 in the first direction X.
  • the first side end region 13 extends in a band shape in the second direction Y in a plan view.
  • the second side end region 14 is provided on the other side of the first direction X (the fourth connection surface portion 10D side) of the active region 12 on the first surface portion 8, and faces the first side end region 13 across the active region 12 in the first direction X.
  • the second side end region 14 extends in a band shape in the second direction Y in a plan view.
  • the first termination region 15 is provided on one side of the active region 12 in the second direction Y (the first connection surface portion 10A side) and faces the active region 12 in the second direction Y.
  • the first termination region 15 extends in the first direction X in a plan view and faces the first side end region 13 and the second side end region 14 in the second direction Y.
  • the second termination region 16 is provided on the other side in the second direction Y (the second connection surface portion 10B side) of the active region 12, and faces the first termination region 15 across the active region 12 in the second direction Y.
  • the second termination region 16 extends in the first direction X in a plan view, and faces the first side end region 13 and the second side end region 14 across the active region 12 in the second direction Y.
  • the third termination region 17 is provided on one side in the second direction Y (the first connection surface portion 10A side) of the first termination region 15, and faces the active region 12 across the first termination region 15 in the second direction Y.
  • the third termination region 17 is provided in the region between the periphery of the first surface portion 8 and the first termination region 15.
  • the third termination region 17 extends in a band shape in the first direction X in a plan view, and faces the first side end region 13 and the second side end region 14 across the first termination region 15.
  • the fourth termination region 18 is provided on the other side in the second direction Y (the second connection surface portion 10B side) of the second termination region 16, and faces the active region 12 across the second termination region 16 in the second direction Y.
  • the fourth termination region 18 is provided in the region between the periphery of the first surface portion 8 and the third termination region 17.
  • the fourth termination region 18 extends in a band shape in the first direction X in a plan view, and faces the first side end region 13 and the second side end region 14 across the second termination region 16.
  • the peripheral region 19 is provided on the second surface portion 9 as a non-active region.
  • the peripheral region 19 is provided in a ring shape (specifically, a rectangular ring shape) surrounding the first surface portion 8 (mesa 11) in a plan view.
  • the peripheral region 19 surrounds the active region 12, the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18 in a plan view.
  • FIG. 5 is an enlarged plan view showing a main portion of the active region 12.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5.
  • FIG. 7 is a cross-sectional view taken along line VII-VII shown in FIG. 5.
  • the semiconductor device 1 includes a p-type body region 20 formed in a surface layer of the first surface portion 8 (first main surface 3) in the active region 12.
  • the body region 20 may be referred to as a "channel region", a "base region”, or the like.
  • a source potential is applied to the body region 20 as a second potential (low potential) different from a first potential (high potential).
  • the source potential may be a reference potential that serves as a reference for circuit operation.
  • the reference potential may be a ground potential or a potential other than the ground potential.
  • the body region 20 is formed at a distance from the bottom of the second semiconductor region 7 toward the first surface portion 8, and faces the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the body region 20 is formed at a distance from the depth position of the second surface portion 9 toward the first surface portion 8.
  • the body region 20 is formed in a layer extending along the first surface portion 8. In this embodiment, the body region 20 is formed over the entire first surface portion 8 and is exposed from the first to fourth connection surface portions 10A to 10D. Of course, the body region 20 may also be formed at a distance inward from the periphery of the first surface portion 8.
  • the semiconductor device 1 includes an n-type source region 21 (impurity region) formed in the surface layer of the first surface portion 8 (first main surface 3) in the active region 12. A source potential is applied to the source region 21.
  • the source region 21 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.
  • the source region 21 is formed in the surface layer of the body region 20. Specifically, the source region 21 is formed at a distance from the bottom of the body region 20 toward the first surface portion 8. In other words, the source region 21 is formed in a region on the first surface portion 8 side of the body region 20. The source region 21 forms a transistor channel with the second semiconductor region 7 in the body region 20.
  • the source region 21 is formed at a distance inward from the periphery of the first surface portion 8. Therefore, the source region 21 is not exposed from the first to fourth connection surface portions 10A to 10D. In this embodiment, the source region 21 is formed only in the active region 12, and not in any other region than the active region 12.
  • the source region 21 may be formed in at least one of the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18, as long as the electrical characteristics are not affected.
  • the source region 21 may be formed on the entire surface of the first surface portion 8 and exposed from the first to fourth connection surface portions 10A to 10D.
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) gate structures 25 formed in the first surface portion 8 (first main surface 3) in the active region 12.
  • the gate structures 25 may also be referred to as “trench structures” or “trench gate structures.”
  • a gate potential is applied to the plurality of gate structures 25 as a control potential.
  • the plurality of gate structures 25 control the inversion and non-inversion of the channel in the body region 20 in response to the gate potential.
  • the multiple gate structures 25 are disposed on the first surface portion 8 at intervals inward from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D), and define the active region 12 in the inner portion of the first surface portion 8.
  • the multiple gate structures 25 are formed only in the active region 12, and are not formed in the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the third termination region 17, or the fourth termination region 18.
  • the multiple gate structures 25 each extend in a band shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. In other words, the multiple gate structures 25 are arranged in stripes extending in the first direction X in a plan view.
  • the multiple gate structures 25 penetrate the body region 20 and the source region 21 to reach the second semiconductor region 7.
  • the body region 20 and the source region 21 are located on both sides of the multiple gate structures 25.
  • the multiple gate structures 25 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. In this embodiment, the multiple gate structures 25 are formed substantially perpendicular to the first surface portion 8. Of course, the multiple gate structures 25 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.
  • the side walls of the multiple gate structures 25 are each formed by the m-plane ((1-100) plane) of the SiC single crystal.
  • the side walls of the multiple gate structures 25 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 25.
  • the side walls of the multiple gate structures 25 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the multiple gate structures 25 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple gate structures 25 extend almost flat along the horizontal direction. Of course, the bottom walls of the multiple gate structures 25 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the sidewall of the gate structure 25 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the gate structure 25 may have a width of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the gate structure 25 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the width of the gate structure 25 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the gate structure 25 has a depth less than the depth of the second surface portion 9.
  • the depth of the gate structure 25 may be approximately equal to the depth of the second surface portion 9, or may be greater than the depth of the second surface portion 9.
  • the depth of the gate structure 25 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the gate structure 25 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the gate structure 25 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the gate structure 25 includes a first trench 26, a first insulating film 27, and a first buried electrode 28.
  • the first trench 26 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the gate structure 25.
  • the first insulating film 27 covers the wall surface of the first trench 26.
  • the first insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the first insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the first insulating film 27 includes a silicon oxide film made of an oxide of the chip 2.
  • the first insulating film 27 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the first trench 26 in a film-like manner.
  • the second film portion covers the bottom wall of the first trench 26 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than the thickness of the first film portion. The thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the first insulating film 27 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the first insulating film 27 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the first buried electrode 28 is buried in the first trench 26 with the first insulating film 27 in between.
  • the first buried electrode 28 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the first buried electrode 28 faces the channel with the first insulating film 27 in between. In other words, the first buried electrode 28 faces the second semiconductor region 7, the body region 20, and the source region 21 with the first insulating film 27 in between.
  • the first buried electrode 28 has an electrode surface exposed from the first trench 26.
  • the electrode surface of the first buried electrode 28 is located on the bottom wall side of the first trench 26 with respect to the height position of the first surface portion 8.
  • the electrode surface of the first buried electrode 28 is located on the first main surface 3 with respect to the depth position of the bottom of the body region 20.
  • the electrode surface of the first buried electrode 28 has a recess in an inner portion that tapers toward the bottom wall side of the first trench 26.
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) first source structures 30 formed on the first main surface 3 (first surface portion 8) in the active region 12.
  • the first source structures 30 may be referred to as “trench structures,” “trench source structures,” “first trench source structures,” etc.
  • a source potential is applied to the plurality of first source structures 30.
  • the multiple first source structures 30 are formed in the first surface portion 8 so as to be adjacent to the multiple gate structures 25 in the second direction Y in the active region 12. Specifically, the multiple first source structures 30 are respectively disposed in regions between the multiple gate structures 25 and face the multiple gate structures 25 in the second direction Y. In other words, the multiple first source structures 30 are arranged alternately with the multiple gate structures 25 in the second direction Y.
  • the multiple first source structures 30 each extend in a band shape in the first direction X in a plan view.
  • the multiple first source structures 30 are drawn out from the active region 12 to either or both of the first side end region 13 and the second side end region 14 (both in this embodiment).
  • the multiple first source structures 30 face the gate structure 25 in the second direction Y in the active region 12, but do not face the gate structure 25 in the second direction Y in the first side end region 13 (second side end region 14).
  • the multiple first source structures 30 are exposed from at least one of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple first source structures 30 penetrate both the third connection surface portion 10C and the fourth connection surface portion 10D and are exposed from both the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple first source structures 30 penetrate the body region 20 and the source region 21 to reach the second semiconductor region 7.
  • the body region 20 and the source region 21 are located on both sides of the multiple first source structures 30.
  • the multiple first source structures 30 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. In this embodiment, the multiple first source structures 30 are formed substantially perpendicular to the first surface portion 8. Of course, the multiple first source structures 30 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.
  • the sidewalls of the multiple first source structures 30 are each formed by the m-plane of the SiC single crystal.
  • the sidewalls of the multiple first source structures 30 may each be formed by the a-plane of the SiC single crystal depending on the extension direction of the first source structures 30.
  • the sidewalls of the multiple first source structures 30 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the multiple first source structures 30 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple first source structures 30 extend almost flat along the horizontal direction. Of course, the bottom walls of the multiple first source structures 30 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the sidewall of the first source structure 30 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the first source structure 30 preferably has a width greater than the width of the gate structure 25.
  • the width of the first source structure 30 may be approximately equal to the width of the gate structure 25, or may be less than the width of the gate structure 25.
  • the width of the first source structure 30 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the first source structure 30 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the width of the first source structure 30 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the first source structure 30 has a depth greater than the depth of the gate structure 25.
  • the depth of the first source structure 30 may be approximately equal to the depth of the gate structure 25, or may be less than the depth of the gate structure 25.
  • the depth of the first source structure 30 is approximately equal to the depth of the second surface portion 9.
  • the depth of the first source structure 30 may be less than the depth of the second surface portion 9, or may be greater than the depth of the second surface portion 9.
  • the ratio (depth ratio) of the depth of the first source structure 30 to the depth of the gate structure 25 is preferably 1 or more and 3 or less.
  • the depth ratio may have a value that belongs to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less.
  • the depth ratio is preferably 1.5 or more and 2.5 or less.
  • the depth of the first source structure 30 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the first source structure 30 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the first source structure 30 is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the first source structure 30 includes a second trench 31, a second insulating film 32, and a second buried electrode 33.
  • the second trench 31 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the first source structure 30.
  • the side walls of the second trench 31 are connected to either one or both (both in this embodiment) of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the bottom wall of the second trench 31 is connected to the second surface portion 9.
  • the second insulating film 32 covers the wall surface of the second trench 31.
  • the second insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the second insulating film 32 includes the same type of insulating material as the insulating material of the first insulating film 27. In this embodiment, the second insulating film 32 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the second insulating film 32 includes a silicon oxide film made of an oxide of the chip 2.
  • the second insulating film 32 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the second trench 31 in a film-like manner.
  • the second film portion covers the bottom wall of the second trench 31 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than the thickness of the first film portion.
  • the thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the thickness of the first film portion of the second insulating film 32 may be approximately equal to the thickness of the first film portion of the first insulating film 27.
  • the thickness of the second film portion of the second insulating film 32 may be approximately equal to the thickness of the second film portion of the first insulating film 27.
  • the second insulating film 32 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the second insulating film 32 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the second buried electrode 33 is buried in the second trench 31 with the second insulating film 32 in between.
  • the second buried electrode 33 may contain either one or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the second buried electrode 33 contains the same type of conductive material as the conductive material of the first buried electrode 28.
  • the second buried electrode 33 faces the second semiconductor region 7, the body region 20, and the source region 21 with the second insulating film 32 in between.
  • the second buried electrode 33 has an electrode surface exposed from the second trench 31.
  • the electrode surface of the second buried electrode 33 is located on the bottom wall side of the second trench 31 with respect to the height position of the first surface portion 8.
  • the electrode surface of the second buried electrode 33 is located on the second main surface 4 with respect to the depth position of the bottom of the body region 20.
  • the electrode surface of the second buried electrode 33 has a recess tapered toward the bottom wall side of the second trench 31 at the inner portion.
  • the semiconductor device 1 includes a plurality of p-type first well regions 35 formed in a region along the plurality of gate structures 25 in the surface layer portion of the first surface portion 8 (first main surface 3) of the active region 12.
  • the first well regions 35 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the first well regions 35 may be less than the p-type impurity concentration of the body region 20.
  • the multiple first well regions 35 are formed in one-to-one correspondence with the multiple gate structures 25.
  • the multiple first well regions 35 are formed in regions along the corresponding gate structures 25 at intervals from the multiple first source structures 30.
  • the multiple first well regions 35 are formed along the sidewalls and bottom walls of the corresponding gate structures 25, and are each electrically connected to the body region 20 in the surface layer of the first surface portion 8.
  • the multiple first well regions 35 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a portion of the second semiconductor region 7 in between.
  • the multiple first well regions 35 form pn junctions with the second semiconductor region 7.
  • the semiconductor device 1 includes a plurality of p-type second well regions 36 formed in a region along the plurality of first source structures 30 in the surface layer portion of the first surface portion 8 (first main surface 3) of the active region 12.
  • the second well regions 36 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the second well regions 36 may be less than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the second well regions 36 is approximately equal to the p-type impurity concentration of the first well region 35.
  • the second well regions 36 are formed in one-to-one correspondence with the first source structures 30.
  • the second well regions 36 are formed in regions along the corresponding first source structures 30, spaced apart from the gate structures 25.
  • the second well regions 36 are formed along the sidewalls and bottom wall of the corresponding first source structures 30, and are each electrically connected to the body region 20 in the surface portion of the first surface portion 8.
  • the second well regions 36 extend along the wall surfaces of the corresponding first source structures 30 in the active region 12, the first side end region 13, and the second side end region 14, and are exposed from the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple second well regions 36 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the bottoms of the multiple second well regions 36 are located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottoms of the multiple first well regions 35.
  • the multiple second well regions 36 form pn junctions with the second semiconductor region 7.
  • the semiconductor device 1 includes a plurality of p-type contact regions 37 formed in a region along a plurality of first well regions 35 in a surface layer portion of the first surface portion 8 (first main surface 3) of the active region 12.
  • the contact regions 37 may be referred to as "backgate regions.”
  • the contact regions 37 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the contact regions 37 is higher than the p-type impurity concentration of the first well region 35 (second well region 36).
  • the multiple contact regions 37 are formed in the multiple second well regions 36.
  • the multiple contact regions 37 extend along the wall surfaces of the corresponding first source structures 30 in the corresponding second well regions 36.
  • the multiple contact regions 37 are formed in a one-to-many correspondence with each corresponding first source structure 30.
  • the multiple contact regions 37 are formed at intervals in the first direction X along the corresponding first source structures 30.
  • the multiple contact regions 37 are extended to the surface layer of the body region 20 along the wall surfaces of the corresponding first source structures 30 in the corresponding second well regions 36, and are exposed from the first surface portion 8.
  • the multiple contact regions 37 each extend in a band shape in the first direction X in a planar view.
  • the length of the multiple contact regions 37 in the first direction X is preferably equal to or greater than the width of the first source structure 30 in the second direction Y.
  • the length of the multiple contact regions 37 is preferably greater than the distance between two adjacent contact regions 37 in the first direction X.
  • the multiple contact regions 37 along one first source structure 30 face the multiple contact regions 37 along the other first source structures 30 in the second direction Y.
  • the multiple contact regions 37 are arranged in a matrix shape with gaps in between in the first direction X and the second direction Y as a whole when viewed in a plan view.
  • the multiple contact regions 37 along one first source structure 30 may be arranged offset in the first direction X so as to face the second direction Y in the region between the multiple contact regions 37 along the other first source structure 30.
  • the multiple contact regions 37 may be arranged in a staggered manner overall in a plan view with intervals in the first direction X and the second direction Y.
  • Fig. 8 is an enlarged plan view showing a main portion of the first side end region 13.
  • Fig. 9 is a cross-sectional view taken along line IX-IX shown in Fig. 8.
  • Fig. 10 is a cross-sectional view taken along line X-X shown in Fig. 8.
  • Fig. 11 is a cross-sectional view taken along line XI-XI shown in Fig. 8.
  • Fig. 12 is a cross-sectional view taken along line XII-XII shown in Fig. 8.
  • the layout of the second side end region 14 is similar to that of the first side end region 13, a description of the layout of the second side end region 14 is omitted.
  • the layout of the second side end region 14 can be obtained by replacing “first side end region 13" with “second side end region 14" in the description of the first side end region 13, and replacing "third connection surface portion 10C" with “fourth connection surface portion 10D".
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) second source structures 40 formed in the first surface portion 8 (first main surface 3) in the first side end region 13.
  • a source potential is applied to the plurality of second source structures 40.
  • the second source structures 40 may be referred to as a "trench structure,” a “source side end structure,” a “trench source structure,” a “second trench source structure,” or the like.
  • the multiple second source structures 40 are respectively arranged in the periphery of the first surface portion 8 (third connection surface portion 10C) and in the region between the multiple gate structures 25.
  • the multiple second source structures 40 are respectively arranged in the regions between the multiple first source structures 30, and face the multiple first source structures 30 in the second direction Y. In other words, the multiple second source structures 40 are arranged alternately with the multiple first source structures 30 in the second direction Y.
  • the second source structures 40 face the gate structures 25 in a one-to-one correspondence in the first direction X, and together with the gate structures 25 define a plurality of side end mesa portions.
  • the side end mesa portions are arranged in a line in the second direction Y.
  • the side end mesa portions may be arranged offset from each other in one and the other directions of the first direction X so as not to be adjacent to and facing other side end mesa portions in the second direction Y.
  • the multiple second source structures 40 each extend in a band shape in the first direction X in a plan view.
  • the multiple second source structures 40 penetrate the third connection surface portion 10C and are exposed from the third connection surface portion 10C.
  • the multiple second source structures 40 penetrate the body region 20 to reach the second semiconductor region 7.
  • the multiple second source structures 40 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the second source structures 40 are formed substantially perpendicular to the first surface 8.
  • the second source structures 40 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.
  • the sidewalls of the multiple second source structures 40 are each formed by the m-plane of the SiC single crystal.
  • the sidewalls of the multiple second source structures 40 may each be formed by the a-plane of the SiC single crystal depending on the extension direction of the second source structures 40.
  • the sidewalls of the multiple second source structures 40 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the second source structures 40 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the second source structures 40 extend substantially flat along the horizontal direction. Of course, the bottom walls of the second source structures 40 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the sidewall of the second source structure 40 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the second source structure 40 preferably has a width greater than the width of the gate structure 25.
  • the width of the second source structure 40 may be approximately equal to the width of the gate structure 25, or may be less than the width of the gate structure 25.
  • the width of the second source structure 40 is preferably approximately equal to the width of the first source structure 30.
  • the width of the second source structure 40 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the second source structure 40 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the width of the second source structure 40 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the second source structure 40 preferably has a depth greater than the depth of the gate structure 25.
  • the depth of the second source structure 40 may be approximately equal to the depth of the gate structure 25, or may be less than the depth of the gate structure 25.
  • the depth of the second source structure 40 is preferably approximately equal to the depth of the second surface portion 9.
  • the depth of the second source structure 40 may be less than the depth of the second surface portion 9, or may be greater than the depth of the second surface portion 9.
  • the depth of the multiple second source structures 40 is preferably approximately equal to the depth of the multiple first source structures 30.
  • the ratio (depth ratio) of the depth of the second source structure 40 to the depth of the gate structure 25 is preferably 1 or more and 3 or less.
  • the depth ratio may have a value that belongs to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less.
  • the depth ratio is preferably 1.5 or more and 2.5 or less.
  • the depth of the second source structure 40 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second source structure 40 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the second source structure 40 is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the second source structures 40 are arranged at a first interval in the first direction X from the gate structures 25.
  • the first interval is preferably 0.5 to 2 times the width of the second source structures 40.
  • the multiple second source structures 40 are arranged at a second spacing in the second direction Y from the multiple source structures.
  • the second spacing may be approximately equal to the first spacing.
  • the second spacing may be greater than the first spacing or less than the first spacing.
  • the second spacing is preferably greater than or equal to 0.5 times and less than or equal to 2 times the width of the second source structures 40.
  • the first interval (second interval) may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the first interval (second interval) may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less. It is preferable that the first interval (second interval) is 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the second source structure 40 includes a third trench 41, a third insulating film 42, and a third buried electrode 43.
  • the third trench 41 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the second source structure 40.
  • the side walls of the third trench 41 are connected to the third connection surface portion 10C.
  • the bottom wall of the third trench 41 is connected to the second surface portion 9.
  • the third insulating film 42 covers the wall surface of the third trench 41.
  • the third insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the third insulating film 42 includes the same type of insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this form, the third insulating film 42 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the third insulating film 42 includes a silicon oxide film made of an oxide of the chip 2.
  • the third insulating film 42 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the third trench 41 in a film-like manner.
  • the second film portion covers the bottom wall of the third trench 41 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than that of the first film portion.
  • the thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the thickness of the first film portion of the third insulating film 42 may be approximately equal to the thickness of the first film portion of the first insulating film 27.
  • the thickness of the second film portion of the third insulating film 42 may be approximately equal to the thickness of the second film portion of the first insulating film 27.
  • the third insulating film 42 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the third insulating film 42 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the third buried electrode 43 is buried in the third trench 41 with the third insulating film 42 in between.
  • the third buried electrode 43 may contain either one or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the third buried electrode 43 contains the same type of conductive material as the conductive material of the first buried electrode 28 (second buried electrode 33).
  • the third buried electrode 43 faces the second semiconductor region 7 and the body region 20 with the third insulating film 42 in between.
  • the third buried electrode 43 has an electrode surface exposed from the third trench 41.
  • the electrode surface of the third buried electrode 43 is located on the bottom wall side of the third trench 41 with respect to the height position of the first surface portion 8.
  • the electrode surface of the third buried electrode 43 is located on the second main surface 4 with respect to the depth position of the bottom of the body region 20.
  • the electrode surface of the third buried electrode 43 has a recess tapered toward the bottom wall side of the third trench 41 at the inner portion.
  • the semiconductor device 1 includes a plurality of p-type third well regions 44 formed in a region along the plurality of second source structures 40 in the surface layer portion of the first surface portion 8 (first main surface 3) of the first side end region 13.
  • the third well regions 44 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the third well regions 44 may be less than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the third well regions 44 is approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).
  • the multiple third well regions 44 are formed in one-to-one correspondence with the multiple second source structures 40.
  • the multiple third well regions 44 are formed in regions along the corresponding second source structures 40 at intervals from the multiple first well regions 35 and the multiple second well regions 36.
  • the multiple third well regions 44 may be formed integrally with the multiple first well regions 35.
  • the multiple third well regions 44 may be formed integrally with the multiple second well regions 36.
  • the multiple third well regions 44 are formed along the sidewalls and bottom wall of the corresponding second source structures 40, and are each electrically connected to the body region 20 in the surface portion of the first surface portion 8.
  • the multiple third well regions 44 are exposed from the third connection surface portion 10C.
  • the multiple third well regions 44 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the bottoms of the multiple third well regions 44 are located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottoms of the multiple first well regions 35.
  • the bottoms of the multiple third well regions 44 are formed at a depth position approximately equal to the bottoms of the multiple second well regions 36.
  • the multiple third well regions 44 form pn junctions with the second semiconductor region 7.
  • Figure 13 is an enlarged plan view showing a main portion of the first termination region 15.
  • Figure 14 is a cross-sectional view taken along line XIV-XIV shown in Figure 13.
  • the layout of the second termination region 16 is similar to the layout of the first termination region 15, the description of the layout of the second termination region 16 is omitted.
  • the layout of the second termination region 16 can be obtained by replacing “first termination region 15" with “second termination region 16" in the description of the first termination region 15, and replacing "first connection surface portion 10A" with “second connection surface portion 10B".
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) dummy gate structures 50 formed in the first surface portion 8 (first main surface 3) in the first termination region 15.
  • the dummy gate structures 50 may be referred to as “trench structures,” “trench termination structures,” “gate termination structures,” “dummy trench structures,” or “dummy trench gate structures.”
  • a source potential is applied to the plurality of dummy gate structures 50. In other words, the plurality of dummy gate structures 50 do not contribute to inversion or non-inversion of the channel.
  • the multiple dummy gate structures 50 are formed in a region on the first connection surface portion 10A side of the active region 12.
  • the multiple dummy gate structures 50 each extend in a band shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. In other words, the multiple dummy gate structures 50 are arranged in stripes extending in the first direction X in a plan view.
  • the multiple dummy gate structures 50 face the multiple gate structures 25 and the multiple first source structures 30 in the second direction Y.
  • the multiple dummy gate structures 50 are extended in the second direction Y to a region facing either or both of the first side end region 13 and the second side end region 14 (both in this embodiment), and face the multiple second source structures 40 in the second direction Y.
  • the multiple dummy gate structures 50 are exposed from at least one of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple dummy gate structures 50 penetrate both the third connection surface portion 10C and the fourth connection surface portion 10D and are exposed from both the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple dummy gate structures 50 penetrate the body region 20 to reach the second semiconductor region 7.
  • the multiple dummy gate structures 50 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the multiple dummy gate structures 50 are formed substantially perpendicular to the first surface portion 8.
  • the multiple dummy gate structures 50 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.
  • the sidewalls of the multiple dummy gate structures 50 are each formed by the m-plane of the SiC single crystal.
  • the sidewalls of the multiple dummy gate structures 50 may each be formed by the a-plane of the SiC single crystal depending on the extension direction of the dummy gate structures 50.
  • the sidewalls of the multiple dummy gate structures 50 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the multiple dummy gate structures 50 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple dummy gate structures 50 extend almost flat along the horizontal direction. Of course, the bottom walls of the multiple dummy gate structures 50 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the sidewall of the dummy gate structure 50 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the dummy gate structure 50 preferably has a width approximately equal to that of the gate structure 25.
  • the width of the dummy gate structure 50 may be greater than or less than the width of the gate structure 25.
  • the width of the dummy gate structure 50 is preferably less than the width of the first source structure 30 (second source structure 40).
  • the dummy gate structure 50 may be approximately equal to or greater than the width of the first source structure 30 (second source structure 40).
  • the width of the dummy gate structure 50 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the dummy gate structure 50 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the width of the dummy gate structure 50 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the depth of the dummy gate structure 50 is preferably less than the depth of the second surface portion 9.
  • the depth of the dummy gate structure 50 may be approximately equal to the depth of the second surface portion 9, or may be greater than the depth of the second surface portion 9.
  • the dummy gate structure 50 has a depth approximately equal to the depth of the gate structure 25.
  • the depth of the dummy gate structure 50 may be greater than the depth of the gate structure 25, or may be less than the depth of the gate structure 25.
  • the depth of the dummy gate structure 50 is preferably less than the depth of the first source structure 30 (second source structure 40).
  • the depth of the dummy gate structure 50 may be approximately equal to the depth of the first source structure 30 (second source structure 40), or may be greater than the depth of the first source structure 30 (second source structure 40).
  • the depth of the dummy gate structure 50 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the dummy gate structure 50 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the dummy gate structure 50 is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the dummy gate structure 50 includes a fourth trench 51, a fourth insulating film 52, and a fourth buried electrode 53.
  • the fourth trench 51 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the dummy gate structure 50.
  • the fourth insulating film 52 covers the wall surface of the fourth trench 51.
  • the fourth insulating film 52 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the fourth insulating film 52 includes the same type of insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the fourth insulating film 52 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the fourth insulating film 52 includes a silicon oxide film made of an oxide of the chip 2.
  • the fourth insulating film 52 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the fourth trench 51 in a film-like manner.
  • the second film portion covers the bottom wall of the fourth trench 51 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than that of the first film portion.
  • the thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the thickness of the first film portion of the fourth insulating film 52 may be approximately equal to the thickness of the first film portion of the first insulating film 27.
  • the thickness of the second film portion of the fourth insulating film 52 may be approximately equal to the thickness of the second film portion of the first insulating film 27.
  • the fourth insulating film 52 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the fourth insulating film 52 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the fourth buried electrode 53 is buried in the fourth trench 51 with the fourth insulating film 52 sandwiched therebetween.
  • the fourth buried electrode 53 may contain either one or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the fourth buried electrode 53 contains the same type of conductive material as the conductive material of the first buried electrode 28 (second buried electrode 33).
  • the fourth buried electrode 53 faces the second semiconductor region 7 and the body region 20 with the fourth insulating film 52 sandwiched therebetween.
  • the fourth buried electrode 53 has an electrode surface exposed from the fourth trench 51.
  • the electrode surface of the fourth buried electrode 53 is located on the bottom wall side of the fourth trench 51 with respect to the height position of the first surface portion 8.
  • the electrode surface of the fourth buried electrode 53 is located on the first main surface 3 with respect to the depth position of the bottom of the body region 20.
  • the electrode surface of the fourth buried electrode 53 has a recess tapered toward the bottom wall side of the fourth trench 51 at its inner portion.
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) third source structures 55 formed in the first surface portion 8 (first main surface 3) in the first termination region 15. A source potential is applied to the plurality of third source structures 55.
  • the third source structures 55 may be referred to as a "trench structure,” a “source termination structure,” a “trench source structure,” a “third trench source structure,” or the like.
  • the multiple third source structures 55 are formed in a region on the first connection surface portion 10A side with respect to the active region 12.
  • the multiple third source structures 55 are formed in the first surface portion 8 so as to be adjacent to the multiple dummy gate structures 50 in the second direction Y in the first termination region 15.
  • the multiple third source structures 55 are respectively disposed in regions between the multiple dummy gate structures 50 and face the multiple dummy gate structures 50 in the second direction Y.
  • the multiple third source structures 55 are arranged alternately with the multiple dummy gate structures 50 in the second direction Y.
  • the multiple third source structures 55 each extend in a strip shape in the first direction X in a plan view.
  • the multiple third source structures 55 face the multiple gate structures 25 and the multiple first source structures 30 in the second direction Y.
  • the multiple third source structures 55 are extended to a region facing either one or both (in this embodiment, both) of the first side end region 13 and the second side end region 14 in the second direction Y, and face the multiple second source structures 40 in the second direction Y.
  • the multiple third source structures 55 face the multiple second source structures 40 in the second direction Y, sandwiching the multiple dummy gate structures 50 therebetween.
  • the multiple third source structures 55 are exposed from at least one of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple third source structures 55 penetrate both the third connection surface portion 10C and the fourth connection surface portion 10D and are exposed from both the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple third source structures 55 penetrate the body region 20 to reach the second semiconductor region 7.
  • the multiple third source structures 55 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the multiple third source structures 55 are formed approximately perpendicular to the first surface portion 8.
  • the multiple third source structures 55 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.
  • the sidewalls of the multiple third source structures 55 are each formed by the m-plane of the SiC single crystal.
  • the sidewalls of the multiple third source structures 55 may each be formed by the a-plane of the SiC single crystal depending on the extension direction of the third source structures 55.
  • the sidewalls of the multiple third source structures 55 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the multiple third source structures 55 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple third source structures 55 extend almost flat along the horizontal direction. Of course, the bottom walls of the multiple third source structures 55 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the sidewall of the third source structure 55 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the third source structure 55 preferably has a width greater than that of the dummy gate structure 50.
  • the width of the third source structure 55 may be approximately equal to the width of the dummy gate structure 50, or may be less than the width of the dummy gate structure 50.
  • the width of the third source structure 55 preferably is approximately equal to the width of the first source structure 30 (second source structure 40).
  • the width of the third source structure 55 may be greater than the width of the first source structure 30 (second source structure 40), or may be less than the width of the first source structure 30 (second source structure 40).
  • the width of the third source structure 55 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the third source structure 55 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the width of the third source structure 55 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the third source structure 55 preferably has a depth greater than the depth of the dummy gate structure 50 (gate structure 25).
  • the depth of the third source structure 55 may be approximately equal to the depth of the dummy gate structure 50 (gate structure 25), or may be less than the depth of the dummy gate structure 50 (gate structure 25).
  • the depth of the third source structure 55 is preferably approximately equal to the depth of the first source structure 30 (second source structure 40).
  • the depth of the third source structure 55 may be less than the depth of the first source structure 30 (second source structure 40) or may be greater than the depth of the first source structure 30 (second source structure 40).
  • the depth of the third source structure 55 is preferably approximately equal to the depth of the second surface portion 9.
  • the depth of the third source structure 55 may be less than the depth of the second surface portion 9 or may be greater than the depth of the second surface portion 9.
  • the ratio of the depth of the third source structure 55 to the depth of the gate structure 25 (dummy gate structure 50) is preferably 1 or more and 3 or less.
  • the depth ratio may have a value that belongs to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less.
  • the depth ratio is preferably 1.5 or more and 2.5 or less.
  • the depth of the third source structure 55 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the third source structure 55 may have a value belonging to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the third source structure 55 is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the third source structure 55 includes a fifth trench 56, a fifth insulating film 57, and a fifth buried electrode 58.
  • the fifth trench 56 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the third source structure 55.
  • the side walls of the fifth trench 56 are connected to either one or both (both in this embodiment) of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the bottom wall of the fifth trench 56 is connected to the second surface portion 9.
  • the fifth insulating film 57 covers the wall surface of the fifth trench 56.
  • the fifth insulating film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the fifth insulating film 57 includes the same type of insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the fifth insulating film 57 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the fifth insulating film 57 includes a silicon oxide film made of an oxide of the chip 2.
  • the fifth insulating film 57 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the fifth trench 56 in a film-like manner.
  • the second film portion covers the bottom wall of the fifth trench 56 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than that of the first film portion.
  • the thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the thickness of the first film portion of the fifth insulating film 57 may be approximately equal to the thickness of the first film portion of the first insulating film 27.
  • the thickness of the second film portion of the fifth insulating film 57 may be approximately equal to the thickness of the second film portion of the first insulating film 27.
  • the fifth insulating film 57 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the fifth insulating film 57 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the fifth buried electrode 58 is buried in the fifth trench 56 with a fifth insulating film 57 in between.
  • the fifth buried electrode 58 may contain either one or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the fifth buried electrode 58 contains the same type of conductive material as the first buried electrode 28 (second buried electrode 33).
  • the fifth buried electrode 58 faces the second semiconductor region 7 and the body region 20 with the fifth insulating film 57 in between.
  • the fifth buried electrode 58 has an electrode surface exposed from the fifth trench 56.
  • the electrode surface of the fifth buried electrode 58 is located on the bottom wall side of the fifth trench 56 with respect to the height position of the first surface portion 8.
  • the electrode surface of the fifth buried electrode 58 is located on the second main surface 4 with respect to the depth position of the bottom of the body region 20.
  • the electrode surface of the fifth buried electrode 58 has a recess in an inner portion that tapers toward the bottom wall side of the fifth trench 56.
  • the semiconductor device 1 includes a plurality of p-type fourth well regions 59 formed in a region along the plurality of dummy gate structures 50 in the surface layer portion of the first surface portion 8 (first main surface 3) of the first termination region 15.
  • the fourth well regions 59 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the fourth well regions 59 may be less than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the fourth well regions 59 is approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).
  • the multiple fourth well regions 59 are formed in one-to-one correspondence with the multiple dummy gate structures 50.
  • the multiple fourth well regions 59 are formed in regions along the corresponding dummy gate structures 50 at intervals from the multiple third source structures 55.
  • the multiple fourth well regions 59 are formed along the side walls and bottom walls of the corresponding dummy gate structures 50, and are each electrically connected to the body region 20 in the surface layer portion of the first surface portion 8.
  • the multiple fourth well regions 59 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the bottoms of the multiple fourth well regions 59 are located on the first surface portion 8 side relative to the depth positions of the bottoms of the multiple second well regions 36.
  • the multiple fourth well regions 59 are exposed from either or both (in this embodiment, both) of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple fourth well regions 59 form pn junctions with the second semiconductor region 7.
  • the semiconductor device 1 includes a plurality of p-type fifth well regions 60 formed in a region along the plurality of third source structures 55 in the surface layer portion of the first surface portion 8 (first main surface 3) of the first termination region 15.
  • the fifth well region 60 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the fifth well region 60 may be less than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the fifth well region 60 is approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).
  • the plurality of fifth well regions 60 are formed in one-to-one correspondence with the plurality of third source structures 55.
  • the plurality of fifth well regions 60 are formed in regions along the corresponding third source structures 55 at intervals from the plurality of dummy gate structures 50.
  • the plurality of fifth well regions 60 are formed along the side walls and bottom walls of the corresponding third source structures 55, and are each electrically connected to the body region 20 in the surface portion of the first surface portion 8.
  • the multiple fifth well regions 60 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the bottoms of the multiple fifth well regions 60 are located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottoms of the multiple fourth well regions 59.
  • the bottoms of the plurality of fifth well regions 60 are formed at a depth position approximately equal to that of the bottoms of the plurality of second well regions 36.
  • the plurality of fifth well regions 60 are exposed from either or both (in this embodiment, both) of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the plurality of fifth well regions 60 form pn junctions with the second semiconductor region 7.
  • Figure 15 is an enlarged plan view showing a main portion of the third termination region 17.
  • Figure 16 is a cross-sectional view taken along line XVI-XVI shown in Figure 15.
  • the layout of the fourth termination region 18 is similar to that of the third termination region 17, so a description of the layout of the fourth termination region 18 is omitted.
  • the layout of the fourth termination region 18 can be obtained by replacing "third termination region 17" with “fourth termination region 18", “first termination region 15" with “second termination region 16", and "first connection surface portion 10A” with “second connection surface portion 10B” in the description of the third termination region 17.
  • the semiconductor device 1 includes a plurality of trench-type (trench electrode-type) fourth source structures 65 formed in the first surface portion 8 (first main surface 3) in the third termination region 17. A source potential is applied to the plurality of fourth source structures 65.
  • the fourth source structures 65 may be referred to as a "trench structure,” a “source termination structure,” a “trench source structure,” a “fourth trench source structure,” etc.
  • the multiple fourth source structures 65 are formed in a region on the first connection surface portion 10A side with respect to the active region 12 (first termination region 15).
  • the multiple fourth source structures 65 each extend in a band shape in the first direction X in a planar view, and are arranged at intervals in the second direction Y. In other words, the multiple fourth source structures 65 are arranged in stripes extending in the first direction X in a planar view.
  • the multiple fourth source structures 65 are adjacent to each other without any intervening trench structures.
  • the multiple fourth source structures 65 face the active region 12 (multiple gate structures 25 and multiple first source structures 30) across the first termination region 15 (multiple dummy gate structures 50 and multiple third source structures 55) in the second direction Y.
  • the multiple fourth source structures 65 are extended to a region facing either one or both (in this embodiment, both) of the first side end region 13 and the second side end region 14 in the second direction Y, and face the multiple second source structures 40 in the second direction Y. In this embodiment, the multiple fourth source structures 65 face the multiple second source structures 40 across the first termination region 15 (the multiple dummy gate structures 50 and the multiple third source structures 55).
  • the multiple fourth source structures 65 are exposed from at least one of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple fourth source structures 65 penetrate both the third connection surface portion 10C and the fourth connection surface portion 10D and are exposed from both the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple fourth source structures 65 penetrate the body region 20 to reach the second semiconductor region 7.
  • the multiple fourth source structures 65 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the multiple fourth source structures 65 are formed approximately perpendicular to the first surface portion 8.
  • the multiple fourth source structures 65 may also be formed in a tapered shape toward the bottom of the second semiconductor region 7.
  • the sidewalls of the multiple fourth source structures 65 are each formed by the m-plane of the SiC single crystal. Of course, the sidewalls of the multiple fourth source structures 65 may each be formed by the a-plane of the SiC single crystal depending on the extension direction of the fourth source structures 65. The sidewalls of the multiple fourth source structures 65 are formed approximately perpendicular to the first main surface 3.
  • the bottom walls of the multiple fourth source structures 65 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple fourth source structures 65 extend almost flat along the horizontal direction. Of course, the bottom walls of the multiple fourth source structures 65 may be curved in an arc shape toward the second main surface 4.
  • the inclination angle (absolute value) of the sidewall of the fourth source structure 65 relative to the vertical line may be 85° or more and 95° or less.
  • the inclination angle may have a value that belongs to at least one of the following ranges: 85° or more and 87.5° or less, 87.5° or more and 90° or less, 90° or more and 92.5° or less, and 92.5° or more and 95° or less.
  • the inclination angle is preferably 87° or more and 93° or less.
  • the fourth source structure 65 preferably has a width greater than that of the gate structure 25.
  • the width of the fourth source structure 65 may be approximately equal to the width of the gate structure 25, or may be less than the width of the gate structure 25.
  • the width of the fourth source structure 65 preferably is approximately equal to the width of the first source structure 30 (second source structure 40).
  • the width of the fourth source structure 65 may be greater than the width of the first source structure 30 (second source structure 40), or may be less than the width of the first source structure 30 (second source structure 40).
  • the width of the fourth source structure 65 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width of the fourth source structure 65 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the width of the fourth source structure 65 is preferably 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the fourth source structure 65 preferably has a depth greater than the depth of the gate structure 25.
  • the depth of the fourth source structure 65 may be approximately equal to the depth of the gate structure 25, or may be less than the depth of the gate structure 25.
  • the depth of the fourth source structure 65 is preferably approximately equal to the depth of the first source structure 30 (second source structure 40). Of course, the depth of the fourth source structure 65 may be less than the depth of the first source structure 30 (second source structure 40) or may be greater than the depth of the first source structure 30 (second source structure 40). The depth of the fourth source structure 65 is preferably approximately equal to the depth of the second surface portion 9. Of course, the depth of the fourth source structure 65 may be less than the depth of the second surface portion 9 or may be greater than the depth of the second surface portion 9.
  • the ratio (depth ratio) of the depth of the fourth source structure 65 to the depth of the gate structure 25 (dummy gate structure 50) is preferably 1 or more and 3 or less.
  • the depth ratio may have a value that belongs to at least one of the following ranges: 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, 1.75 or more and 2 or less, 2 or more and 2.25 or less, 2.25 or more and 2.5 or less, 2.5 or more and 2.75 or less, and 2.75 or more and 2.5 or less.
  • the depth ratio is preferably 1.5 or more and 2.5 or less.
  • the depth of the fourth source structure 65 may be 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the fourth source structure 65 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the depth of the fourth source structure 65 is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the ratio of the spacing between the multiple fourth source structures 65 to the spacing between the gate structure 25 and the first source structure 30 is preferably 0.5 or more and 2 or less.
  • the spacing ratio may have a value that belongs to at least one of the following ranges: 0.5 or more and 0.75 or less, 0.75 or more and 1 or less, 1 or more and 1.25 or less, 1.25 or more and 1.5 or less, 1.5 or more and 1.75 or less, and 1.75 or more and 2 or less.
  • the spacing ratio is preferably 0.75 or more and 1.25 or less.
  • the fourth source structure 65 includes a sixth trench 66, a sixth insulating film 67, and a sixth buried electrode 68.
  • the sixth trench 66 is formed in the first surface portion 8, and defines the walls (side walls and bottom wall) of the fourth source structure 65.
  • the side walls of the sixth trench 66 are connected to either one or both (both in this embodiment) of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the bottom wall of the sixth trench 66 is connected to the second surface portion 9.
  • the sixth insulating film 67 covers the wall surface of the sixth trench 66.
  • the sixth insulating film 67 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is preferable that the sixth insulating film 67 includes the same type of insulating material as the insulating material of the first insulating film 27 (second insulating film 32). In this embodiment, the sixth insulating film 67 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the sixth insulating film 67 includes a silicon oxide film made of an oxide of the chip 2.
  • the sixth insulating film 67 includes a first film portion and a second film portion.
  • the first film portion covers the sidewall of the sixth trench 66 in a film-like manner.
  • the second film portion covers the bottom wall of the sixth trench 66 in a film-like manner and is connected to the first film portion.
  • the second film portion has a thickness greater than that of the first film portion.
  • the thickness of the second film portion may be approximately equal to the thickness of the first film portion.
  • the thickness of the first film portion of the sixth insulating film 67 may be approximately equal to the thickness of the first film portion of the first insulating film 27.
  • the thickness of the second film portion of the sixth insulating film 67 may be approximately equal to the thickness of the second film portion of the first insulating film 27.
  • the sixth insulating film 67 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the sixth insulating film 67 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the sixth buried electrode 68 is buried in the sixth trench 66 with a sixth insulating film 67 in between.
  • the sixth buried electrode 68 may contain either one or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the sixth buried electrode 68 contains the same type of conductive material as the first buried electrode 28 (second buried electrode 33).
  • the sixth buried electrode 68 faces the second semiconductor region 7 and the body region 20 with the sixth insulating film 67 in between.
  • the sixth buried electrode 68 has an electrode surface exposed from the sixth trench 66.
  • the electrode surface of the sixth buried electrode 68 is located on the bottom wall side of the sixth trench 66 relative to the height position of the first surface portion 8.
  • the electrode surface of the sixth buried electrode 68 is located on the second main surface 4 side relative to the depth position of the bottom of the body region 20.
  • the electrode surface of the sixth buried electrode 68 has a recess tapered toward the bottom wall side of the sixth trench 66 at its inner portion.
  • the semiconductor device 1 includes a plurality of sixth well regions 69 of p-type formed in a region along the plurality of fourth source structures 65 in the surface layer portion of the first surface portion 8 (first main surface 3) of the third termination region 17.
  • the sixth well regions 69 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the sixth well regions 69 may be less than the p-type impurity concentration of the body region 20. It is preferable that the p-type impurity concentration of the sixth well regions 69 is approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).
  • the sixth well regions 69 are formed in one-to-one correspondence with the fourth source structures 65.
  • the sixth well regions 69 are formed in regions along the corresponding fourth source structures 65 with spaces between each other.
  • the sixth well regions 69 are formed along the side walls and bottom walls of the corresponding fourth source structures 65, and are each electrically connected to the body region 20 in the surface portion of the first surface portion 8.
  • the multiple sixth well regions 69 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the bottoms of the multiple sixth well regions 69 are positioned on the bottom side of the second semiconductor region 7 relative to the depth positions of the bottoms of the multiple first well regions 35.
  • the multiple sixth well regions 69 are exposed from either or both (in this embodiment, both) of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the multiple sixth well regions 69 form pn junctions with the second semiconductor region 7.
  • FIG. 17 is a cross-sectional view taken along line XVII-XVII shown in FIG. 1.
  • FIG. 18 is a cross-sectional view taken along line XVIII-XVIII shown in FIG. 1.
  • the semiconductor device 1 includes a p-type outer well region 70 formed in the surface layer of the second surface portion 9 in the peripheral region 19. A source potential is applied to the outer well region 70.
  • the outer well region 70 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 37.
  • the p-type impurity concentration of the outer well region 70 is higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the outer well region 70 may be lower than the p-type impurity concentration of the body region 20. It is preferable that the outer well region 70 has a p-type impurity concentration approximately equal to that of the first well region 35 (second well region 36).
  • the outer well region 70 is formed at a distance from the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D) toward the first surface portion 8 in a plan view.
  • the outer well region 70 extends in a band shape along the first surface portion 8 in a plan view.
  • the outer well region 70 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first surface portion 8.
  • the outer well region 70 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).
  • the outer well region 70 extends from the surface portion of the second surface portion 9 toward the surface portions of the first to fourth connection surface portions 10A to 10D, and has a portion extending in the vertical direction Z along the first to fourth connection surface portions 10A to 10D.
  • the outer well region 70 is electrically connected to the body region 20 at the surface portion of the first surface portion 8.
  • the outer well region 70 is connected to the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, and the sixth well region 69 at the third connection surface portion 10C (fourth connection surface portion 10D).
  • the outer well region 70 is formed at a distance from the bottom of the second semiconductor region 7 toward the second surface portion 9, and faces the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the bottom of the outer well region 70 is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom wall of the gate structure 25.
  • the bottom of the outer well region 70 is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom wall of the first source structure 30 (second source structure 40).
  • the bottom of the outer well region 70 is located on the bottom side of the second semiconductor region 7 relative to the depth position of the contact region 37. It is preferable that the bottom of the outer well region 70 is formed at a depth position approximately equal to the bottom of the second well region 36 (third well region 44).
  • the outer well region 70 forms a pn junction with the second semiconductor region 7.
  • the outer well region 70 spreads the depletion layer into the second semiconductor region 7 when a reverse bias voltage is applied.
  • the depletion layer in the outer well region 70 spreads horizontally and in the thickness direction, and merges with the depletion layer spreading from the active region 12.
  • the outer well region 70 expands the depletion layer spreading from the active region 12 toward the periphery of the second surface 9, and reduces the electric field intensity (electric field concentration) on the periphery of the first surface 8 (first to fourth connection surfaces 10A to 10D).
  • the semiconductor device 1 includes a p-type outer contact region 71 formed in the surface layer of the second surface portion 9 in the peripheral region 19.
  • the outer contact region 71 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the outer contact region 71 is higher than the p-type impurity concentration of the outer well region 70. It is preferable that the p-type impurity concentration of the outer contact region 71 is approximately equal to the p-type impurity concentration of the contact region 37.
  • the outer contact region 71 is formed in the surface layer of the second surface portion 9 at a distance from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) and the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D) in a plan view. Specifically, the outer contact region 71 is formed in the surface layer of the outer well region 70. The outer contact region 71 is formed at a distance from the bottom of the outer well region 70 toward the second surface portion 9, and faces the second semiconductor region 7 across a portion of the outer well region 70.
  • the outer contact region 71 extends in a band shape along the first surface portion 8 in a plan view.
  • the outer contact region 71 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first surface portion 8.
  • the outer contact region 71 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).
  • the bottom of the outer well region 70 is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom wall of the gate structure 25.
  • the bottom of the outer well region 70 is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom wall of the first source structure 30 (second source structure 40). It is preferable that the bottom of the outer contact region 71 is formed at a depth position approximately equal to the bottom of the contact region 37.
  • the semiconductor device 1 includes at least one p-type field region 72 formed in the surface layer of the second surface portion 9 in the peripheral region 19.
  • the multiple field regions 72 may be formed in an electrically floating state or may be fixed to the source potential.
  • the multiple field regions 72 reduce the electric field within the chip 2 in the peripheral region 19.
  • the number of field regions 72 is arbitrary.
  • the number of field regions 72 may be 1 or more and 20 or less.
  • the number of field regions 72 may have a value that belongs to at least one of the following ranges: 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less.
  • the number of field regions 72 is typically 1 or more and 8 or less.
  • the semiconductor device 1 includes four field regions 72.
  • the multiple field regions 72 are formed in the surface layer of the second surface portion 9 at intervals from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) and the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D) in a plan view. Specifically, the multiple field regions 72 are formed in the region between the periphery of the second surface portion 9 and the outer well region 70, at intervals from the outer well region 70 toward the periphery of the second surface portion 9.
  • the multiple field regions 72 are formed at intervals from the bottom of the second semiconductor region 7 toward the second surface portion 9, and face the first semiconductor region 6 across a portion of the second semiconductor region 7.
  • the multiple field regions 72 each extend in a band shape along the first surface portion 8 in a plan view.
  • the multiple field regions 72 are each formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surround the first surface portion 8.
  • the multiple field regions 72 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).
  • the multiple field regions 72 each form a pn junction with the second semiconductor region 7.
  • the multiple field regions 72 expand the depletion layer toward the second semiconductor region 7 when a reverse bias voltage is applied.
  • the depletion layer of the multiple field regions 72 spreads horizontally and in the thickness direction, integrating with the depletion layer of the outer well region 70.
  • the multiple field regions 72 expand the depletion layer spreading from the active region 12 toward the periphery of the second surface portion 9, and reduce the electric field strength (electric field concentration) on the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D).
  • the width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 72 are arbitrary and can take various values depending on the electric field to be relaxed.
  • the width of the multiple field regions 72 may be approximately constant or may be non-uniform.
  • the width of the multiple field regions 72 may gradually increase toward the peripheral edge side of the second surface portion 9.
  • the width of the multiple field regions 72 may gradually decrease toward the peripheral edge side of the second surface portion 9.
  • the depth of the multiple field regions 72 may be approximately constant or may be non-uniform.
  • the depth of the multiple field regions 72 may gradually increase toward the peripheral edge of the second surface portion 9.
  • the depth of the multiple field regions 72 may gradually decrease toward the peripheral edge of the second surface portion 9.
  • the spacing between the multiple field regions 72 may be approximately constant or may be non-uniform.
  • the spacing between the multiple field regions 72 may gradually increase toward the peripheral edge of the second surface portion 9.
  • the spacing between the multiple field regions 72 may gradually decrease toward the peripheral edge of the second surface portion 9.
  • the p-type impurity concentration of the multiple field regions 72 may be approximately constant or may be non-uniform.
  • the p-type impurity concentration of the multiple field regions 72 may gradually increase toward the peripheral edge side of the second surface portion 9.
  • the p-type impurity concentration of the multiple field regions 72 may gradually decrease toward the peripheral edge side of the second surface portion 9.
  • the p-type impurity concentration of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the multiple field regions 72 may be higher than the p-type impurity concentration of the body region 20, or may be lower than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the first well region 35 (second well region 36).
  • the p-type impurity concentration of the multiple field regions 72 may be higher than the p-type impurity concentration of the first well region 35 (second well region 36), or may be lower than the p-type impurity concentration of the first well region 35 (second well region 36).
  • the p-type impurity concentration of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the outer well region 70.
  • the p-type impurity concentration of the multiple field regions 72 may be higher than the p-type impurity concentration of the outer well region 70, or may be lower than the p-type impurity concentration of the outer well region 70.
  • the p-type impurity concentration of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the contact region 37 (outer contact region 71).
  • the p-type impurity concentration of the multiple field regions 72 may be higher than the p-type impurity concentration of the contact region 37 (outer contact region 71), or may be lower than the p-type impurity concentration of the contact region 37 (outer contact region 71).
  • the semiconductor device 1 includes an insulating first inorganic film 75 that selectively covers the first main surface 3.
  • the first inorganic film 75 is an example of a "subject to be covered.”
  • the first inorganic film 75 may be referred to as an "inorganic insulating film (first inorganic insulating film)" or the like.
  • the first inorganic film 75 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D.
  • the first inorganic film 75 is continuous with the periphery of the second surface portion 9 (the first to fourth side surfaces 5A to 5D). In other words, the first inorganic film 75 is formed flush with the periphery of the second surface portion 9 (the first to fourth side surfaces 5A to 5D).
  • the first inorganic film 75 has a layered structure including a lower inorganic film 76 and an upper inorganic film 77.
  • the lower inorganic film 76 may be referred to as a "base insulating film”, a “main surface insulating film”, etc.
  • the upper inorganic film 77 may be referred to as an "upper insulating film”, an “interlayer insulating film”, an “intermediate insulating film”, etc.
  • the lower inorganic film 76 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D.
  • the lower inorganic film 76 is connected to the first insulating film 27, the second insulating film 32, the third insulating film 42, the fourth insulating film 52, the fifth insulating film 57, and the sixth insulating film 67 on the first surface portion 8, exposing the first buried electrode 28, the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.
  • the lower inorganic film 76 covers the outer well region 70, the outer contact region 71, and the multiple field regions 72 on the second surface portion 9.
  • the lower inorganic film 76 is connected to the second insulating film 32, the third insulating film 42, the fourth insulating film 52, the fifth insulating film 57, and the sixth insulating film 67 on the first to fourth connection surface portions 10A to 10D, and exposes the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.
  • the lower inorganic film 76 covers the body region 20, the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, the sixth well region 69 and the outer well region 70 in the first to fourth connection surface portions 10A to 10D.
  • the upper inorganic film 77 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the upper inorganic film 77 preferably includes a silicon oxide film.
  • the upper inorganic film 77 preferably includes an insulating material having properties different from the insulating material of the lower inorganic film 76.
  • the upper inorganic film 77 preferably has a single layer structure or a laminated structure including at least one of a silicon oxide film containing phosphorus (PSG film), a silicon oxide film containing phosphorus and boron (BPSG film), a silicon oxide film without added impurities (NSG film), and a tetraethyl orthosilicate film (TEOS film).
  • the upper inorganic film 77 may have a laminated structure including an NSG film laminated on the lower inorganic film 76, and a PSG film (or BPSG film) laminated on the NSG film.
  • the upper inorganic film 77 is laminated on the lower inorganic film 76, and selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D with the lower inorganic film 76 in between.
  • the upper inorganic film 77 covers the multiple gate structures 25 (first buried electrode 28), the multiple first source structures 30 (second buried electrode 33), the multiple second source structures 40 (third buried electrode 43), the multiple dummy gate structures 50 (fourth buried electrode 53), the multiple third source structures 55 (fifth buried electrode 58), and the multiple fourth source structures 65 (sixth buried electrode 68) on the first surface portion 8.
  • the upper inorganic film 77 covers the outer well region 70, outer contact region 71 and multiple field regions 72 on the second surface portion 9, sandwiching the lower inorganic film 76.
  • the upper inorganic film 77 covers the multiple first source structures 30 (second buried electrodes 33), multiple second source structures 40 (third buried electrodes 43), multiple dummy gate structures 50 (fourth buried electrodes 53), multiple third source structures 55 (fifth buried electrodes 58) and multiple fourth source structures 65 (sixth buried electrodes 68) on the first to fourth connection surface portions 10A to 10D.
  • the semiconductor device 1 includes a plurality of gate connection electrodes 78 that selectively cover a plurality of gate structures 25 in the active region 12.
  • the gate connection electrodes 78 may also be referred to as “connection electrodes,” “connection electrode films,” “gate connection electrode films,” etc.
  • the gate connection electrode 78 may be considered as one component of the gate structure 25.
  • the multiple gate connection electrodes 78 include either p-type conductive polysilicon or n-type conductive polysilicon, or both.
  • the multiple gate connection electrodes 78 preferably include the same type of conductive material as the conductive material of the first buried electrode 28.
  • the multiple gate connection electrodes 78 are respectively interposed between the multiple gate structures 25 and the upper inorganic film 77. In other words, the multiple gate connection electrodes 78 are respectively disposed on the multiple gate structures 25 and are covered by the upper inorganic film 77.
  • the multiple gate connection electrodes 78 are formed in a one-to-many correspondence with the multiple gate structures 25.
  • the multiple gate connection electrodes 78 each cover both ends of the corresponding gate structure 25 in a film-like manner, and each extend in a band-like manner in the first direction X.
  • the multiple gate connection electrodes 78 are formed at intervals in the second direction Y from the multiple first source structures 30 in a plan view, and are formed at intervals in the first direction X from the multiple second source structures 40.
  • the multiple gate connection electrodes 78 expose the multiple first source structures 30 and the multiple second source structures 40, and are electrically isolated from the multiple first source structures 30 and the multiple second source structures 40.
  • the multiple gate connection electrodes 78 are arranged alternately with the multiple first source structures 30 in the second direction Y in a plan view, and do not face the multiple second source structures 40 in the second direction Y.
  • the multiple gate connection electrodes 78 are connected to the first buried electrode 28 in the portion covering the corresponding gate structure 25, and each has a portion that is extended from above the first buried electrode 28 onto the lower inorganic film 76.
  • the multiple gate connection electrodes 78 have a portion that faces the gate structure 25 corresponding to the vertical direction Z, and a portion that faces the body region 20 in the vertical direction Z.
  • the multiple gate connection electrodes 78 are formed integrally with the first buried electrodes 28 of the corresponding gate structures 25.
  • the multiple gate connection electrodes 78 are each formed from the lead-out portion of the corresponding first buried electrodes 28.
  • the gate connection electrodes 78 may be formed separately from the first buried electrodes 28.
  • the multiple gate connection electrodes 78 each have an electrode surface that extends along the first surface portion 8.
  • the multiple gate connection electrodes 78 are formed in a tapered shape (quadratic pyramid shape) toward the electrode surface in a cross-sectional view. It is preferable that the electrode surface is formed to be wider than the gate structure 25 in the second direction Y.
  • the thickness of the gate connection electrode 78 may be less than the depth of the first source structure 30 or may be greater than the depth of the first source structure 30.
  • the thickness of the gate connection electrode 78 may be less than the depth of the second surface portion 9 or may be greater than the depth of the second surface portion 9.
  • the thickness of the gate connection electrode 78 may be less than the depth of the gate structure 25 or may be greater than the depth of the gate structure 25.
  • the thickness of the gate connection electrode 78 may be 0.05 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the gate connection electrode 78 may have a value belonging to at least one of the following ranges: 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, and 2.5 ⁇ m or more and 3 ⁇ m or less.
  • the thickness of the gate connection electrode 78 is preferably 1.5 ⁇ m or more and 2.5 ⁇ m or less.
  • the semiconductor device 1 includes a sidewall wiring 79 that covers at least one of the first to fourth connection surface portions 10A to 10D on the second surface portion 9.
  • the sidewall wiring 79 is interposed between the lower inorganic film 76 and the upper inorganic film 77.
  • the sidewall wiring 79 is disposed on the lower inorganic film 76 and is covered by the upper inorganic film 77.
  • the sidewall wiring 79 also functions as a "sidewall structure" that reduces the step between the first surface portion 8 and the second surface portion 9.
  • the sidewall wiring 79 preferably extends in a strip shape along at least one of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the sidewall wiring 79 is formed in a polygonal ring shape (specifically, a square ring shape) extending along the first to fourth connection surface portions 10A to 10D in a plan view, and surrounds the first surface portion 8.
  • the sidewall wiring 79 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).
  • the sidewall wiring 79 includes a portion that extends in a film-like manner along the second surface portion 9, and a portion that extends in a film-like manner along the first to fourth connection surface portions 10A to 10D.
  • the portion of the sidewall wiring 79 located above the second surface portion 9 may cover the second surface portion 9 in a film-like manner in the region on the second surface portion 9 side relative to the height position of the first surface portion 8.
  • the portion of the sidewall wiring 79 located above the second surface portion 9 may have a thickness less than the depth of the second surface portion 9.
  • the sidewall wiring 79 is formed at intervals from the multiple field regions 72 toward the first surface portion 8, and faces the outer well region 70 across the lower inorganic film 76.
  • the sidewall wiring 79 is formed at intervals from the outer edge of the outer well region 70 toward the first surface portion 8.
  • the sidewall wiring 79 is formed at a distance from the outer edge of the outer contact region 71 toward the first surface 8, and has a portion that faces the outer contact region 71 across the lower inorganic film 76.
  • the sidewall wiring 79 may also be formed at a distance from the inner edge of the outer contact region 71 toward the first surface 8.
  • the sidewall wiring 79 covers the first to fourth connection surface portions 10A to 10D, sandwiching the lower inorganic film 76.
  • the sidewall wiring 79 covers the body region 20, the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, the sixth well region 69 and the outer well region 70, sandwiching the lower inorganic film 76 in the first to fourth connection surface portions 10A to 10D.
  • the sidewall wiring 79 is electrically connected to the multiple first source structures 30 (second buried electrodes 33), the multiple second source structures 40 (third buried electrodes 43), the multiple dummy gate structures 50 (fourth buried electrodes 53), the multiple third source structures 55 (fifth buried electrodes 58) and the multiple fourth source structures 65 (sixth buried electrodes 68) in the first to fourth connection surface portions 10A to 10D.
  • the sidewall wiring 79 has an overlapping portion 79a that rides up from at least one of the first to fourth connection surface portions 10A to 10D onto the edge of the first surface portion 8.
  • the overlapping portion 79a rides up from all of the first to fourth connection surface portions 10A to 10D onto the first surface portion 8, and is formed in a ring shape (specifically, a square ring shape) that surrounds the inner portion of the first surface portion 8.
  • the overlapping portion 79a covers the first surface portion 8 in a film-like manner, and extends in a band shape along the edge of the first surface portion 8.
  • the overlapping portion 79a covers the peripheral portion of the first surface portion 8 at a distance from the multiple gate structures 25.
  • the overlapping portion 79a is electrically connected to the multiple first source structures 30 (second buried electrodes 33), multiple second source structures 40 (third buried electrodes 43), multiple dummy gate structures 50 (fourth buried electrodes 53), multiple third source structures 55 (fifth buried electrodes 58), and multiple fourth source structures 65 (sixth buried electrodes 68) at the peripheral portion of the first surface portion 8.
  • the sidewall wiring 79 includes either p-type conductive polysilicon or n-type conductive polysilicon, or both. It is preferable that the sidewall wiring 79 includes the same type of conductive material as the conductive material of the first buried electrode 28, etc.
  • the sidewall wiring 79 is formed integrally with the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.
  • the sidewall wiring 79 may be formed separately from the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.
  • the semiconductor device 1 includes a plurality of source openings 80 formed in the first inorganic film 75 in the active region 12.
  • the plurality of source openings 80 penetrate the first inorganic film 75 and selectively expose the plurality of first source structures 30.
  • the plurality of source openings 80 are formed in one-to-one correspondence with the plurality of source structures, respectively, and each extends in a strip shape along the corresponding first source structure 30.
  • the multiple source openings 80 may be formed in a one-to-many correspondence with the corresponding first source structures 30. In this case, the multiple source openings 80 may be formed at intervals in the second direction Y along the corresponding first source structures 30. The multiple source openings 80 each expose a corresponding one first source structure 30, a source region 21, and multiple contact regions 37.
  • the semiconductor device 1 includes at least one outer opening 81 (one in this embodiment) formed in the first inorganic film 75 in the peripheral region 19.
  • the outer opening 81 penetrates the first inorganic film 75 and exposes both the outer contact region 71 and the sidewall wiring 79.
  • the outer opening 81 penetrates the upper inorganic film 77, exposing the sidewall wiring 79.
  • the outer opening 81 also penetrates both the lower inorganic film 76 and the upper inorganic film 77, exposing the outer contact region 71.
  • the outer opening 81 extends in a band shape along the outer contact region 71 and the sidewall wiring 79 in a plan view.
  • the outer opening 81 is formed in a polygonal ring shape (specifically, a square ring shape) that surrounds the first surface portion 8 in a plan view.
  • the semiconductor device 1 may have multiple outer openings 81.
  • the multiple outer openings 81 may be formed at intervals along the outer contact region 71 so as to surround the first surface portion 8.
  • the semiconductor device 1 includes a plurality of gate openings 82 formed in the first inorganic film 75 in the active region 12.
  • the plurality of gate openings 82 penetrate the first inorganic film 75 and selectively expose a plurality of gate structures 25.
  • the multiple gate openings 82 are formed in portions of the first inorganic film 75 that cover the multiple gate connection electrodes 78, exposing each of the multiple gate connection electrodes 78.
  • the multiple gate openings 82 are formed in a one-to-one correspondence with the multiple gate connection electrodes 78, and each extends in a band shape in the first direction X in a plan view.
  • the semiconductor device 1 includes at least one anchor opening 83 (one in this embodiment) formed in the first inorganic film 75 in the peripheral region 19.
  • the anchor opening 83 is selectively formed in a portion of the first inorganic film 75 that covers the peripheral portion of the second surface portion 9.
  • the anchor opening 83 is formed in the region between the first surface portion 8 and the second surface portion 9. Specifically, the anchor opening 83 is formed in the region between the periphery of the second surface portion 9 and the outer well region 70. More specifically, the anchor opening 83 is formed in the region between the periphery of the second surface portion 9 and the multiple field regions 72 (the outermost field regions 72).
  • the anchor opening 83 penetrates the first inorganic film 75 and exposes the second surface portion 9. Specifically, the anchor opening 83 exposes the second semiconductor region 7.
  • the anchor opening 83 may be dug down toward the bottom of the second semiconductor region 7 relative to the height position of the second surface portion 9. In other words, the bottom wall of the anchor opening 83 may be located on the bottom side of the second semiconductor region 7 relative to the height position of the second surface portion 9.
  • the anchor opening 83 extends in a band shape along the first surface portion 8 in a plan view.
  • the anchor opening 83 is formed in a polygonal ring shape (specifically, a square ring shape) that surrounds the first surface portion 8 in a plan view.
  • the semiconductor device 1 may have multiple anchor openings 83.
  • the multiple anchor openings 83 may be formed at intervals along the first surface portion 8 so as to surround the first surface portion 8.
  • the multiple anchor openings 83 may be formed in a matrix or staggered pattern at intervals in the first direction X and the second direction Y so as to surround the first surface portion 8.
  • the multiple anchor openings 83 may be formed in a stripe or lattice pattern so as to surround the first surface portion 8.
  • the multiple annular anchor openings 83 may be formed in a concentric pattern so as to surround the first surface portion 8.
  • FIG. 19 is a plan view showing an example layout of the main electrodes (source electrode 85, source wiring 90, gate electrode 95, and gate wiring 100) arranged on the first main surface 3.
  • FIG. 20 is a plan view showing a first example layout of the second inorganic film 110.
  • FIG. 21 is an enlarged plan view showing a main portion of the second inorganic film 110.
  • the semiconductor device 1 includes a source electrode 85 disposed on the first inorganic film 75.
  • the source electrode 85 is a terminal electrode to which a source potential is applied from the outside.
  • the source electrode 85 may also be referred to as an "electrode”, a “first electrode”, a “first pad electrode”, a “first main surface electrode”, a “first terminal electrode”, a “source pad electrode”, etc.
  • the source electrode 85 has a thickness greater than the depth of the gate structure 25.
  • the thickness of the source electrode 85 is preferably greater than the depth of the first source structure 30.
  • the thickness of the source electrode 85 is preferably greater than the depth of the second surface portion 9.
  • the thickness of the source electrode 85 is preferably greater than the thickness (total thickness) of the first inorganic film 75.
  • the thickness of the source electrode 85 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the source electrode 85 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the source electrode 85 is disposed on the covering portion of the first inorganic film 75 that covers the first surface portion 8.
  • the source electrode 85 covers at least the active region 12 in a plan view.
  • the source electrode 85 covers the active region 12 with a gap from the first side end region 13 and the second side end region 14.
  • the source electrode 85 covers the first surface portion 8 with a gap from both ends of the multiple gate structures 25.
  • the source electrode 85 is formed with a gap inward from the multiple gate connection electrodes 78.
  • the source electrode 85 may cover either one or both of the first termination region 15 and the third termination region 17. That is, the source electrode 85 may face a plurality of dummy gate structures 50 and a plurality of third source structures 55 on the first termination region 15 side, with the first inorganic film 75 in between. The source electrode 85 may face a plurality of fourth source structures 65 on the third termination region 17 side. Of course, the source electrode 85 may cover the active region 12 at a distance from either one or both of the first termination region 15 and the third termination region 17.
  • the source electrode 85 has a first pad portion 85a, a second pad portion 85b, and a third pad portion 85c.
  • the first pad portion 85a has a relatively large planar area and forms the main body of the source electrode 85.
  • the first pad portion 85a is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the second side surface 5B (second connection surface portion 10B) relative to the first side surface 5A (first connection surface portion 10A).
  • the second pad portion 85b has a planar area less than that of the first pad portion 85a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 85a in the first direction X (the end on the third connection surface portion 10C side) toward the first connection surface portion 10A.
  • the third pad portion 85c has a planar area less than that of the first pad portion 85a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 85a in the first direction X (the end on the fourth connection surface portion 10D side) toward the first connection surface portion 10A, and faces the second pad portion 85b in the second direction Y.
  • the plane area of the third pad portion 85c may be approximately equal to the plane area of the second pad portion 85b. Of course, the plane area of the third pad portion 85c may be greater than the plane area of the second pad portion 85b, or may be less than the plane area of the second pad portion 85b. Either or both of the second pad portion 85b and the third pad portion 85c may be used as a terminal portion for monitoring a current.
  • the proportion of the source electrode 85 in the first surface portion 8 is preferably 50% or more and less than 100%.
  • the proportion of the source electrode 85 may be in any one of the following ranges: 50% or more and 60% or more, 60% or more and 70% or more, 70% or more and 80% or more, 80% or more and 90% or more, and 90% or more and less than 100%.
  • the source electrode 85 does not necessarily have to have both the second pad portion 85b and the third pad portion 85c at the same time.
  • the source electrode 85 may have only one of the second pad portion 85b and the third pad portion 85c.
  • the source electrode 85 may be composed of only the first pad portion 85a and may not have both the second pad portion 85b and the third pad portion 85c.
  • the source electrode 85 extends into the multiple source openings 80 from above the first inorganic film 75, and is electrically connected to the multiple first source structures 30, the source region 21, and the multiple contact regions 37 within the multiple source openings 80.
  • the source electrode 85 includes a first electrode surface 86 and a first electrode sidewall 87.
  • the first electrode surface 86 extends along the first inorganic film 75.
  • the first electrode surface 86 may have a plurality of recesses recessed toward the first surface portion 8 in a portion covering the plurality of source openings 80.
  • the first electrode sidewall 87 is located on the first inorganic film 75.
  • the first electrode sidewall 87 slopes obliquely downward from the first electrode surface 86 toward the first inorganic film 75. In this embodiment, the first electrode sidewall 87 slopes obliquely downward in a curved manner from the first electrode surface 86 toward the first inorganic film 75.
  • the source electrode 85 has a laminated structure including a first lower electrode film 88 and a first upper electrode film 89 laminated in this order from the first inorganic film 75 side.
  • the first lower electrode film 88 is laminated in a film form on the first inorganic film 75 as a base film (barrier film) of the source electrode 85, and forms the lower layer portion of the first electrode side wall 87 of the source electrode 85.
  • the first lower electrode film 88 has a layered structure including a Ti film and a TiN film layered in this order from the first inorganic film 75 side.
  • the first lower electrode film 88 may have a single layer structure made of a Ti film or a TiN film.
  • the first lower electrode film 88 has a thickness (total thickness) less than the thickness (total thickness) of the first inorganic film 75.
  • the thickness (total thickness) of the first lower electrode film 88 may be 0.01 ⁇ m or more and 1 ⁇ m or less.
  • the thickness (total thickness) of the first lower electrode film 88 may be 0.75 ⁇ m or less, 0.5 ⁇ m or less, 0.25 ⁇ m or less, or 0.1 ⁇ m or less.
  • the first lower electrode film 88 collectively covers the area of the first inorganic film 75 where the multiple source openings 80 are formed, and extends from above the first inorganic film 75 into the multiple source openings 80.
  • the first lower electrode film 88 has a portion that covers the insulating main surface of the first inorganic film 75 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 80 in a film-like manner, and a portion that covers the first surface portion 8 in the multiple source openings 80 in a film-like manner.
  • the first lower electrode film 88 directly covers the insulating main surface of the first inorganic film 75 and faces the multiple gate structures 25 across the first inorganic film 75.
  • the first lower electrode film 88 penetrates into the multiple source openings 80 from above the insulating main surface of the first inorganic film 75 and covers the wall surfaces of the multiple source openings 80 in a film-like manner.
  • the first lower electrode film 88 covers the first surface portion 8 in the form of a film within the multiple source openings 80.
  • the first lower electrode film 88 is mechanically and electrically connected to the multiple first source structures 30, the source regions 21, and the multiple contact regions 37 within the multiple source openings 80.
  • the first upper electrode film 89 is laminated in the form of a film on the first lower electrode film 88 as the main body of the source electrode 85, and forms the upper layer of the first electrode surface 86 and the first electrode sidewall 87 of the source electrode 85.
  • the first upper electrode film 89 contains a conductive material different from that of the first lower electrode film 88.
  • the first upper electrode film 89 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the first upper electrode film 89 has a thickness greater than the thickness (total thickness) of the first lower electrode film 88.
  • the thickness of the first upper electrode film 89 is preferably greater than the thickness of the first inorganic film 75.
  • the thickness of the first upper electrode film 89 is preferably greater than the depth of the gate structure 25.
  • the thickness of the first upper electrode film 89 is preferably greater than the depth of the first source structure 30.
  • the thickness of the first upper electrode film 89 is preferably greater than the depth of the second surface portion 9.
  • the thickness of the first upper electrode film 89 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the first upper electrode film 89 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first upper electrode film 89 collectively covers the area of the first inorganic film 75 where the multiple source openings 80 are formed, backfilling the multiple source openings 80.
  • the first upper electrode film 89 has a portion that covers the insulating main surface of the first inorganic film 75 with the first lower electrode film 88 in between, a portion that covers the wall surfaces of the multiple source openings 80 with the first lower electrode film 88 in between, and a portion that covers the first surface portion 8 with the first lower electrode film 88 in between.
  • the first upper electrode film 89 covers the insulating main surface of the first inorganic film 75 with the first lower electrode film 88 in between, and faces the multiple gate structures 25 with the first inorganic film 75 and the first lower electrode film 88 in between.
  • the first upper electrode film 89 penetrates into the multiple source openings 80 from above the first inorganic film 75, and covers the wall surfaces of the multiple source openings 80 in a film-like manner with the first lower electrode film 88 in between.
  • the first upper electrode film 89 covers the first surface portion 8 in a film-like manner, sandwiching the first lower electrode film 88 within the multiple source openings 80.
  • the first upper electrode film 89 is electrically connected to the multiple first source structures 30, source regions 21, and multiple contact regions 37 via the first lower electrode film 88 within the multiple source openings 80.
  • the semiconductor device 1 includes a source wiring 90 arranged around the source electrode 85 on the first inorganic film 75.
  • the source wiring 90 is applied with the same potential (source potential) as the potential (source potential) applied to the source electrode 85.
  • the source wiring 90 may also be referred to as a "wiring", a "first wiring”, a “finger electrode”, a “source finger”, etc.
  • the source wiring 90 has a thickness greater than the depth of the gate structure 25.
  • the thickness of the source wiring 90 is preferably greater than the depth of the first source structure 30.
  • the thickness of the source wiring 90 is preferably greater than the depth of the second surface portion 9.
  • the thickness of the source wiring 90 is preferably approximately equal to the thickness of the source electrode 85.
  • the thickness of the source wiring 90 may be greater than the thickness of the source electrode 85, or may be less than the thickness of the source electrode 85. It is preferable that the thickness of the source electrode 85 is greater than the thickness (total thickness) of the first inorganic film 75.
  • the thickness of the source wiring 90 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the source wiring 90 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the source wiring 90 has a wiring width smaller than the electrode width of the source electrode 85, and is selectively routed over the first inorganic film 75.
  • the source wiring 90 extends in a strip shape along the first electrode sidewall 87 of the source electrode 85 at a distance from the first electrode sidewall 87.
  • the source wiring 90 preferably extends in a strip shape along at least one of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the source wiring 90 is formed in a polygonal ring shape (specifically, a square ring shape) that extends along the first to fourth connection surface portions 10A to 10D in a plan view, and surrounds the source electrode 85.
  • the source wiring 90 is disposed on the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18 in a plan view, and surrounds the active region 12.
  • the source wiring 90 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).
  • the source wiring 90 is electrically connected to the source electrode 85 on the first surface portion 8. Specifically, the source wiring 90 has a portion that extends in a strip shape in the second direction Y toward the source electrode 85 (first pad portion 85a) in the portion extending along the second connection surface portion 10B, and is connected to the end of the source electrode 85 (first pad portion 85a). In other words, the source wiring 90 is formed as an extraction wiring that is extracted from the source electrode 85.
  • the source wiring 90 covers the second termination region 16 and the fourth termination region 18 at the connection portion with the source electrode 85.
  • the source wiring 90 faces the second termination region 16 (the multiple dummy gate structures 50 and the multiple third source structures 55) at the connection portion with the source electrode 85, sandwiching the first inorganic film 75 therebetween.
  • the source wiring 90 faces the fourth termination region 18 (multiple fourth source structures 65) at the connection portion with the source electrode 85, sandwiching the first inorganic film 75 therebetween.
  • the connection portion between the source electrode 85 and the source wiring 90 may be considered as part of the source electrode 85.
  • the source wiring 90 is drawn out from the first surface 8 across at least one (in this embodiment, all) of the first to fourth connection surface portions 10A to 10D onto the second surface 9.
  • the source wiring 90 is formed as the outermost wiring on the second surface 9.
  • the source wiring 90 does not face other electrodes in the horizontal direction along the insulating main surface of the first inorganic film 75 in the outer peripheral region 19.
  • other electrodes are not interposed between the periphery of the second surface 9 and the region between the source wiring 90.
  • the source wiring 90 covers the sidewall wiring 79 on the first to fourth connection surface portions 10A to 10D, sandwiching the first inorganic film 75 (upper inorganic film 77).
  • the film formability of the source wiring 90 is improved by the sidewall wiring 79.
  • the source wiring 90 enters the outer opening 81 from above the first inorganic film 75, and is connected to both the outer contact region 71 and the sidewall wiring 79 within the outer opening 81.
  • the source wiring 90 is electrically connected to the outer contact region 71 and the sidewall wiring 79.
  • the source wiring 90 transmits the source potential applied to the source electrode 85 to the outer contact region 71 and the sidewall wiring 79.
  • the source wiring 90 transmits the source potential to the first source structure 30, the second source structure 40, the dummy gate structure 50, the third source structure 55, and the fourth source structure 65 via the sidewall wiring 79.
  • the source wiring 90 is spaced apart from the multiple field regions 72 toward the first surface portion 8, and faces the outer well region 70 across the first inorganic film 75. In this embodiment, the source wiring 90 is spaced apart from the outer edge of the outer well region 70 toward the first surface portion 8, and covers the entire outer contact region 71.
  • the source wiring 90 may cross the outer edge of the outer well region 70. In other words, the source wiring 90 may cover the entire outer well region 70. In this case, it is preferable that the source wiring 90 is formed at a distance from the multiple field regions 72 toward the first surface portion 8. Of course, the source wiring 90 may cover at least one of the multiple field regions 72.
  • the source wiring 90 includes a first wiring surface 91, a first inner side wall 92 on the inner side (the source electrode 85 side), and a first outer side wall 93 on the outer side (the peripheral edge side of the chip 2).
  • the first inner side wall 92 may be referred to as the "first wiring sidewall”
  • the second inner side wall 102 may be referred to as the "second wiring sidewall”.
  • the first wiring surface 91 has a portion located on the first surface 8 and a portion located on the second surface 9. The portion of the first wiring surface 91 located on the first surface 8 is located at a height position approximately equal to that of the first electrode surface 86 of the source wiring 90.
  • the portion of the first wiring surface 91 located on the second surface 9 is recessed toward the second surface 9 side more than the portion of the first wiring surface 91 located on the first surface 8. It is preferable that the portion of the first wiring surface 91 located on the second surface 9 is located above the height position of the first surface 8 (toward the portion of the first wiring surface 91 located on the first surface 8). Of course, the portion of the first wiring surface 91 located on the second surface 9 may be located below the height position of the first surface 8 (toward the second surface 9 side).
  • the first inner wall 92 is positioned on the covering portion of the first inorganic film 75 that covers the first surface portion 8, spaced apart from the first electrode side wall 87 of the source electrode 85.
  • the first inner wall 92 slopes obliquely downward from the first wiring surface 91 toward the first inorganic film 75.
  • the first inner wall 92 slopes obliquely downward in a curved shape from the first wiring surface 91 toward the first inorganic film 75.
  • the first outer wall 93 is positioned on the covering portion of the first inorganic film 75 that covers the second surface portion 9.
  • the first inner wall 92 slopes obliquely downward from the first wiring surface 91 toward the first inorganic film 75.
  • the first inner wall 92 slopes obliquely downward in a curved shape from the first wiring surface 91 toward the first inorganic film 75.
  • the first outer wall 93 faces the outer well region 70 across the first inorganic film 75.
  • the first outer wall 93 may face the outer contact region 71 across the first inorganic film 75.
  • the first outer wall 93 may face the second semiconductor region 7 across the first inorganic film 75.
  • the first outer wall 93 may face at least one of the multiple field regions 72 across the first inorganic film 75.
  • the source wiring 90 like the source electrode 85, has a laminated structure including a first lower electrode film 88 and a first upper electrode film 89.
  • the first lower electrode film 88 is laminated in the form of a film on the first inorganic film 75 as a base film (barrier film) for the source wiring 90, and forms the lower layer of the first inner wall 92 and the first outer wall 93 of the source wiring 90.
  • the first lower electrode film 88 covers the entire area of the first inorganic film 75 where the outer opening 81 is formed, and extends into the outer opening 81 from above the first inorganic film 75.
  • the first lower electrode film 88 is mechanically and electrically connected to the outer contact region 71 and the sidewall wiring 79 within the outer opening 81.
  • the first upper electrode film 89 is laminated in the form of a film on the first lower electrode film 88 as the main body of the source wiring 90, and forms the first wiring surface 91 of the source wiring 90, the upper layer of the first inner wall 92, and the upper layer of the first outer wall 93.
  • the first upper electrode film 89 collectively covers the region of the first inorganic film 75 in which the outer opening 81 is formed, and backfills the outer opening 81.
  • the first upper electrode film 89 is electrically connected to the outer contact region 71 and the sidewall wiring 79 via the first lower electrode film 88 within the outer opening 81.
  • first surface 8 side active region 12 side
  • second surface 9 side peripheral region 19 side
  • an almost uniform electric field distribution is formed along the first main surface 3.
  • an end portion of the electric field distribution formed on the first surface 8 side is formed, and the electric field is more likely to concentrate there than on the first surface 8.
  • the source electrode 85 is disposed on the active region 12 (first region) which has a relatively low first electric field.
  • the source wiring 90 is disposed on the peripheral region 19 (second region) which has a second electric field which is higher than the first electric field.
  • the second electric field for the source wiring 90 may be locally higher than the first electric field for the source electrode 85.
  • the electric field within the chip 2 leaks from the inside of the chip 2 to the outside outside the source wiring 90. Therefore, the second electric field on the outer periphery region 19 side may be locally higher near the first outer wall 93 of the source wiring 90.
  • the semiconductor device 1 includes a gate electrode 95 disposed on the first inorganic film 75.
  • the gate electrode 95 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate electrode 95 may be referred to as an "electrode,” a “second electrode,” a “second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” a “gate pad electrode,” etc.
  • the gate electrode 95 has a thickness greater than the depth of the gate structure 25.
  • the thickness of the gate electrode 95 is preferably greater than the depth of the first source structure 30.
  • the thickness of the gate electrode 95 is preferably greater than the depth of the second surface portion 9.
  • the thickness of the gate electrode 95 is preferably approximately equal to the thickness of the source electrode 85.
  • the thickness of the gate electrode 95 is preferably greater than the thickness (total thickness) of the first inorganic film 75.
  • the thickness of the gate electrode 95 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the gate electrode 95 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the gate electrode 95 is disposed on the first inorganic film 75 at a distance from the source electrode 85. Specifically, the gate electrode 95 is disposed on the portion of the first inorganic film 75 that covers the first surface portion 8.
  • the gate electrode 95 is disposed in a region on the first connection surface portion 10A side of the first pad portion 85a, and is interposed in a region between the second pad portion 85b and the third pad portion 85c.
  • the gate electrode 95 faces the first pad portion 85a in the second direction Y, and faces both the second pad portion 85b and the third pad portion 85c in the first direction X.
  • the gate electrode 95 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate electrode 95 has a planar area less than the planar area of the source electrode 85.
  • the gate electrode 95 has a planar area less than the planar area of the first pad portion 85a.
  • the gate electrode 95 may have a planar area less than the planar area of the second pad portion 85b (third pad portion 85c).
  • the proportion of the gate electrode 95 in the first surface portion 8 is preferably 1% or more and 25% or less.
  • the proportion of the gate electrode 95 may have a value that falls within any one of the following ranges: 1% or more and 5% or more, 5% or more and 10% or less, 10% or more and 15% or less, 15% or more and 20% or less, and 20% or more and 25% or less.
  • the proportion of the gate electrode 95 is preferably 10% or less.
  • the gate electrode 95 covers at least the active region 12 in a plan view. In other words, the gate electrode 95 partially faces the multiple gate structures 25 and the multiple first source structures 30 with the first inorganic film 75 in between. The gate electrode 95 also faces the body region 20, the source region 21, the multiple first well regions 35, the multiple second well regions 36, and the multiple contact regions 37 with the first inorganic film 75 in between.
  • the gate electrode 95 preferably covers the active region 12 with a gap therebetween from the first side end region 13 and the second side end region 14. In other words, the gate electrode 95 preferably covers the first surface portion 8 with a gap therebetween from both ends of the plurality of gate structures 25. Specifically, the gate electrode 95 is preferably formed with a gap therebetween inward from the plurality of gate connection electrodes 78.
  • the gate electrode 95 does not have a direct electrical connection to the multiple gate structures 25.
  • the gate electrode 95 may be electrically connected to the multiple gate structures 25 via the multiple gate openings 82.
  • the portions of the multiple gate structures 25 located directly below the gate electrode 95 may be removed.
  • the gate electrode 95 may cover either or both of the first termination region 15 and the third termination region 17. That is, the gate electrode 95 may face a plurality of dummy gate structures 50 and a plurality of third source structures 55 on the first termination region 15 side, sandwiching the first inorganic film 75 therebetween. The gate electrode 95 may also face a plurality of fourth source structures 65 on the third termination region 17 side. Of course, the gate electrode 95 may cover the active region 12 with a space between it and both the first termination region 15 and the third termination region 17.
  • the gate electrode 95 includes a second electrode surface 96 and a second electrode sidewall 97.
  • the second electrode surface 96 extends along the first inorganic film 75.
  • the second electrode surface 96 is positioned at a height position approximately equal to that of the first electrode surface 86 of the source electrode 85.
  • the second electrode surface 96 may be positioned below the first electrode surface 86, or may be positioned above the first electrode surface 86.
  • the second electrode sidewall 97 is located on the first inorganic film 75.
  • the second electrode sidewall 97 slopes obliquely downward from the second electrode surface 96 toward the first inorganic film 75.
  • the second electrode sidewall 97 slopes obliquely downward in a curved shape from the second electrode surface 96 toward the first inorganic film 75.
  • the gate electrode 95 has a laminated structure including a second lower electrode film 98 and a second upper electrode film 99 laminated in this order from the first inorganic film 75 side.
  • the second lower electrode film 98 is laminated in a film form on the first inorganic film 75 as a base film (barrier film) of the gate electrode 95, and forms the lower layer portion of the second electrode sidewall 97 of the gate electrode 95.
  • the second lower electrode film 98 has a layered structure including a Ti film and a TiN film layered in this order from the first inorganic film 75 side, similar to the first lower electrode film 88 of the source electrode 85.
  • the second lower electrode film 98 may have a single layer structure made of a Ti film or a TiN film.
  • the second lower electrode film 98 has a thickness less than the thickness (total thickness) of the first inorganic film 75. It is preferable that the thickness of the second lower electrode film 98 is approximately equal to the thickness of the first lower electrode film 88.
  • the thickness (total thickness) of the second lower electrode film 98 may be 0.01 ⁇ m or more and 1 ⁇ m or less.
  • the thickness (total thickness) of the second lower electrode film 98 may be 0.75 ⁇ m or less, 0.5 ⁇ m or less, 0.25 ⁇ m or less, or 0.1 ⁇ m or less.
  • the second upper electrode film 99 is laminated in the form of a film on the second lower electrode film 98 as the main body of the gate electrode 95, and forms the upper layer of the second electrode surface 96 and the second electrode sidewall 97 of the gate electrode 95.
  • the second upper electrode film 99 contains a conductive material different from that of the second lower electrode film 98.
  • the second upper electrode film 99 may contain at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may contain at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the second upper electrode film 99 has a thickness greater than the thickness (total thickness) of the second lower electrode film 98.
  • the thickness of the second upper electrode film 99 is preferably greater than the thickness of the first inorganic film 75.
  • the thickness of the second upper electrode film 99 is preferably greater than the depth of the gate structure 25.
  • the thickness of the second upper electrode film 99 is preferably greater than the depth of the first source structure 30.
  • the thickness of the second upper electrode film 99 is preferably greater than the depth of the second surface portion 9.
  • the thickness of the second upper electrode film 99 is preferably approximately equal to the thickness of the first upper electrode film 89.
  • the thickness of the second upper electrode film 99 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the second upper electrode film 99 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the semiconductor device 1 includes a gate wiring 100 arranged around the source electrode 85 on the first inorganic film 75.
  • the gate wiring 100 is applied with the same potential (gate potential) as the potential (gate potential) applied to the gate electrode 95.
  • the gate wiring 100 may also be referred to as a "wiring", a "second wiring”, a “finger electrode”, a “gate finger”, etc.
  • the gate wiring 100 has a thickness greater than the depth of the gate structure 25.
  • the thickness of the gate wiring 100 is preferably greater than the depth of the first source structure 30.
  • the thickness of the gate wiring 100 is preferably greater than the depth of the second surface portion 9.
  • the thickness of the gate wiring 100 is preferably approximately equal to the thickness of the source electrode 85 (gate electrode 95).
  • the thickness of the gate wiring 100 may be greater than the thickness of the source electrode 85 (gate electrode 95) or less than the thickness of the source electrode 85 (gate electrode 95). It is preferable that the thickness of the gate electrode 95 is greater than the thickness (total thickness) of the first inorganic film 75.
  • the thickness of the gate wiring 100 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the gate wiring 100 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the gate wiring 100 has a wiring width smaller than the electrode width of the gate electrode 95, and is selectively routed over the first inorganic film 75.
  • the gate wiring 100 is disposed at a distance inward from the periphery of the first surface portion 8. Therefore, the gate wiring 100 is not positioned over the second surface portion 9.
  • the gate wiring 100 is electrically connected to the gate electrode 95 on the first surface 8. Specifically, the gate wiring 100 is connected to the end of the gate electrode 95 on the first connection surface 10A side. In other words, the gate wiring 100 is formed as an extraction wiring that is extracted from the gate electrode 95.
  • the connection portion of the gate electrode 95 and the gate wiring 100 may be regarded as part of the gate electrode 95.
  • the gate wiring 100 is routed on the first inorganic film 75 to the region between the source electrode 85 and the source wiring 90 at a distance from the source electrode 85 and the source wiring 90.
  • the gate wiring 100 extends in a strip shape along the first electrode sidewall 87 of the source electrode 85 at a distance from the first electrode sidewall 87.
  • the gate wiring 100 preferably extends in a strip shape along at least one of the third connection surface portion 10C and the fourth connection surface portion 10D.
  • the gate wiring 100 is formed in a ring shape with ends (specifically, a square ring with ends) that extends along the first to fourth connection surface portions 10A to 10D so as to surround the gate electrode 95.
  • the gate wiring 100 has a portion extending in the first direction X along the first connection surface portion 10A in a plan view, a portion extending in the second direction Y along the second connection surface portion 10B, a portion extending in the second direction Y along the third connection surface portion 10C, and a portion extending in the second direction Y along the fourth connection surface portion 10D.
  • the gate wiring 100 has a pair of open ends that allow the source wiring 90 to pass through in the portion along the second connection surface portion 10B.
  • the gate wiring 100 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).
  • the gate wiring 100 intersects (specifically, perpendicular to) both ends of the multiple gate structures 25 in the portion along the third connection surface portion 10C and the portion along the fourth connection surface portion 10D.
  • the gate wiring 100 enters the multiple gate openings 82 from above the first inorganic film 75, and is electrically connected to the ends (both ends) of the multiple gate structures 25 within the multiple gate openings 82.
  • the gate wiring 100 is mechanically and electrically connected to the multiple gate connection electrodes 78 within the multiple gate openings 82, and is electrically connected to the multiple gate structures 25 via the multiple gate connection electrodes 78.
  • the gate potential applied to the gate electrode 95 is applied to the multiple gate structures 25 via the gate wiring 100.
  • the gate wiring 100 may cover the active region 12 at a distance from the first side end region 13 and the second side end region 14. In other words, the gate wiring 100 may be formed at a distance from the second source structures 40. Of course, the gate wiring 100 may have a portion that faces the second source structures 40 with the first inorganic film 75 interposed therebetween.
  • the gate wiring 100 may cover at least one of the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18.
  • the gate electrode 95 may face the multiple dummy gate structures 50 and the multiple third source structures 55 on the first termination region 15 (second termination region 16) side, with the first inorganic film 75 in between.
  • the gate electrode 95 may face the multiple fourth source structures 65 on the third termination region 17 (fourth termination region 18) side, sandwiching the first inorganic film 75 therebetween.
  • the gate electrode 95 may cover the active region 12 at a distance from the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18.
  • the gate wiring 100 includes a second wiring surface 101, a second inner side wall 102 on the inner side (the source electrode 85 side), and a second outer side wall 103 on the outer side (the peripheral edge side of the chip 2).
  • the second inner side wall 102 may be referred to as the "first wiring sidewall”, and the second inner side wall 102 may be referred to as the "second wiring sidewall”.
  • the second wiring surface 101 is located at a height position approximately equal to that of the first electrode surface 86 of the source electrode 85.
  • the second wiring surface 101 is located at a height position approximately equal to that of the portion of the first wiring surface 91 of the source wiring 90 that is located on the first surface portion 8.
  • the second inner wall 102 is positioned on the covering portion of the first inorganic film 75 that covers the first surface portion 8, spaced apart from the first electrode side wall 87 of the source electrode 85.
  • the second inner wall 102 slopes obliquely downward from the second wiring surface 101 toward the first inorganic film 75.
  • the second inner wall 102 slopes obliquely downward in a curved shape from the second wiring surface 101 toward the first inorganic film 75.
  • the second outer wall 103 is spaced apart from the first inner wall 92 of the source wiring 90 and is positioned on the covering portion of the first inorganic film 75 that covers the first surface portion 8.
  • the second outer wall 103 slopes obliquely downward from the second wiring surface 101 toward the first inorganic film 75.
  • the second outer wall 103 slopes obliquely downward in a curved shape from the second wiring surface 101 toward the first inorganic film 75.
  • the gate wiring 100 like the gate electrode 95, has a laminated structure including a second lower electrode film 98 and a second upper electrode film 99.
  • the second lower electrode film 98 is laminated in a film form on the first inorganic film 75 as a base film (barrier film) of the gate wiring 100, and forms the lower layer of the second inner wall 102 and the second outer wall 103 of the gate wiring 100.
  • the second lower electrode film 98 collectively covers the area of the first inorganic film 75 in which the multiple gate openings 82 are formed, and extends into the multiple gate openings 82 from above the first inorganic film 75.
  • the second lower electrode film 98 is mechanically and electrically connected to the multiple gate structures 25 (multiple gate connection electrodes 78) within the multiple gate openings 82.
  • the second upper electrode film 99 is laminated in the form of a film on the second lower electrode film 98 as the main body of the gate wiring 100, and forms the second wiring surface 101 of the gate wiring 100, the upper layer of the second inner wall 102, and the upper layer of the second outer wall 103.
  • the second upper electrode film 99 collectively covers the area of the first inorganic film 75 in which the multiple gate openings 82 are formed, backfilling the multiple gate openings 82.
  • the second upper electrode film 99 is electrically connected to the multiple gate structures 25 (multiple gate connection electrodes 78) via the second lower electrode film 98 within the multiple gate openings 82.
  • the semiconductor device 1 includes an insulating second inorganic film 110 that selectively covers the first inorganic film 75.
  • the second inorganic film 110 may be referred to as an "inorganic insulating film (second inorganic insulating film)", an “upper insulating film”, a “passivation film”, etc.
  • the second inorganic film 110 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the second inorganic film 110 preferably contains an insulating material different from the insulating material of the first inorganic film 75. Specifically, the second inorganic film 110 preferably contains an insulating material different from the insulating material of the upper inorganic film 77. In this embodiment, the second inorganic film 110 has a single-layer structure made of a silicon nitride film.
  • the second inorganic film 110 preferably has a thickness less than the thickness of the source electrode 85 (gate electrode 95).
  • the thickness of the second inorganic film 110 is preferably greater than the thickness of the lower inorganic film 76.
  • the thickness of the second inorganic film 110 is preferably greater than the thickness of the upper inorganic film 77.
  • the thickness of the second inorganic film 110 is preferably greater than the thickness (total thickness) of the first inorganic film 75.
  • the thickness of the second inorganic film 110 may be less than the thickness (total thickness) of the first inorganic film 75.
  • the thickness of the second inorganic film 110 may be less than the thickness of the upper inorganic film 77.
  • the thickness of the second inorganic film 110 may be less than the thickness of the lower inorganic film 76.
  • the thickness of the second inorganic film 110 may be greater than the depth of the second surface portion 9 or less than the depth of the second surface portion 9.
  • the thickness of the second inorganic film 110 may be greater than the depth of the gate structure 25 or less than the depth of the gate structure 25.
  • the thickness of the second inorganic film 110 may be greater than the depth of the first source structure 30 or less than the depth of the first source structure 30.
  • the thickness of the second inorganic film 110 may be 0.01 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the second inorganic film 110 may have a value belonging to at least one of the following ranges: 0.01 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the second inorganic film 110 is preferably 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the second inorganic film 110 selectively covers the source electrode 85, the source wiring 90, the gate electrode 95, and the gate wiring 100 on the first inorganic film 75.
  • the second inorganic film 110 has a first inner coating portion 111, a second inner coating portion 112, an outer coating portion 113, and a removed portion 114.
  • the first inner covering portion 111 selectively covers the source electrode 85. Specifically, the first inner covering portion 111 covers the first electrode surface 86 of the source electrode 85 in a film-like manner so as to expose at least a portion of the first electrode sidewall 87 of the source electrode 85. In this embodiment, the first inner covering portion 111 exposes the entire area of the first electrode sidewall 87. Specifically, the first inner covering portion 111 covers the first electrode surface 86 at a distance from the first electrode sidewall 87, exposing the peripheral portion of the first electrode surface 86 in addition to the first electrode sidewall 87.
  • the first inner covering portion 111 extends flatly on the first electrode surface 86.
  • the first inner covering portion 111 covers the peripheral edge of the first electrode surface 86 (source electrode 85) and exposes the inside of the first electrode surface 86 (source electrode 85).
  • the first inner covering portion 111 extends in a strip shape along the first electrode side wall 87 at the peripheral edge of the first electrode surface 86.
  • the first inner covering portion 111 has a portion extending along the first pad portion 85a, a portion extending along the second pad portion 85b, and a portion extending along the third pad portion 85c.
  • the first inner covering portion 111 has an extension portion 115 that is drawn from above the source electrode 85 to above the connection portion of the source electrode 85 and the source wiring 90.
  • the extension portion 115 is formed to be wider than the other portions.
  • the extension portion 115 may have a width that is approximately equal to the other portions.
  • the extension 115 covers the connection portion of the source electrode 85 and the source wiring 90, with a gap between the first electrode sidewall 87 of the source electrode 85 and the first outer wall 93 of the source wiring 90. It is preferable that the extension 115 covers the connection portion of the source electrode 85 and the source wiring 90, with a gap between the second surface 9 and the first surface 8. Of course, the extension 115 may have a portion that crosses the second connection surface 10B and covers the source wiring 90.
  • the first inner covering portion 111 is formed in a ring shape that surrounds the inner portion of the first electrode surface 86 in a plan view.
  • the first inner covering portion 111 is formed in a polygonal ring shape having four sides that are parallel to the periphery of the chip 2 in a plan view.
  • the first inner covering portion 111 is formed in a polygonal ring shape (U-shaped ring) that matches the planar shape of the first electrode surface 86 in a plan view.
  • the first inner covering portion 111 defines a first pad opening 116 that exposes the inner portion of the first electrode surface 86.
  • the first pad opening 116 is defined in a polygonal shape having four sides parallel to the periphery of the chip 2 in a plan view.
  • the first pad opening 116 is defined in a polygonal shape (U-shape) that matches the planar shape of the first electrode surface 86 in a plan view.
  • the first inner coating portion 111 may face the active region 12 across the first inorganic film 75 and the source electrode 85. In other words, the first inner coating portion 111 may face one or more gate structures 25 and/or one or more first source structures 30 across the first inorganic film 75 and the source electrode 85.
  • the first inner covering portion 111 may face either one or both of the first termination region 15 and the second termination region 16, with the first inorganic film 75 and the source electrode 85 in between.
  • the first inner covering portion 111 may face one or more dummy gate structures 50 and/or one or more third source structures 55, with the first inorganic film 75 and the source electrode 85 in between.
  • the first inner coating portion 111 may face either one or both of the third termination region 17 and the fourth termination region 18, with the first inorganic film 75 and the source electrode 85 in between. In other words, the first inner coating portion 111 may face one or more fourth source structures 65, with the first inorganic film 75 and the source electrode 85 in between.
  • the first inner coating portion 111 preferably has a width greater than the thickness of the source electrode 85.
  • the width of the first inner coating portion 111 may be less than the thickness of the source electrode 85.
  • the width of the first inner coating portion 111 may be 1 ⁇ m or more and 100 ⁇ m or less.
  • the width of the first inner coating portion 111 may have a value that falls within at least one of the following ranges: 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 40 ⁇ m or less, 40 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 60 ⁇ m or less, 60 ⁇ m or more and 70 ⁇ m or less, 70 ⁇ m or more and 80 ⁇ m or less, 80 ⁇ m or more and 90 ⁇ m or less, and 90 ⁇ m or more and 100 ⁇ m or less.
  • the first inner coating portion 111 is preferably formed at a distance from the first electrode sidewall 87 that is greater than the thickness of the source electrode 85.
  • the distance between the first inner coating portion 111 may be less than the thickness of the source electrode 85.
  • the distance between the first inner coating portion 111 may be greater than or equal to 0.1 ⁇ m and less than or equal to 100 ⁇ m.
  • the spacing of the first inner coating portion 111 may have a value that falls within at least one of the following ranges: 0.1 ⁇ m to 1 ⁇ m, 1 ⁇ m to 5 ⁇ m, 5 ⁇ m to 10 ⁇ m, 10 ⁇ m to 20 ⁇ m, 20 ⁇ m to 30 ⁇ m, 30 ⁇ m to 40 ⁇ m, 40 ⁇ m to 50 ⁇ m, 50 ⁇ m to 60 ⁇ m, 60 ⁇ m to 70 ⁇ m, 70 ⁇ m to 80 ⁇ m, 80 ⁇ m to 90 ⁇ m, and 90 ⁇ m to 100 ⁇ m.
  • the second inner covering portion 112 selectively covers the gate electrode 95. Specifically, the second inner covering portion 112 covers the second electrode surface 96 of the gate electrode 95 in a film-like manner so as to expose at least a portion of the second electrode sidewall 97 of the gate electrode 95. In this embodiment, the second inner covering portion 112 exposes the entire area of the second electrode sidewall 97. Specifically, the second inner covering portion 112 covers the second electrode surface 96 at a distance from the second electrode sidewall 97, exposing the peripheral portion of the second electrode surface 96 in addition to the second electrode sidewall 97.
  • the second inner covering portion 112 extends flatly over the second electrode surface 96.
  • the second inner covering portion 112 covers the peripheral portion of the second electrode surface 96 (gate electrode 95) and exposes the inside of the second electrode surface 96 (gate electrode 95).
  • the second inner covering portion 112 extends in a band shape along the second electrode side wall 97 at the peripheral portion of the second electrode surface 96.
  • the second inner covering portion 112 is formed in a ring shape that surrounds the inner portion of the second electrode surface 96 in a plan view.
  • the second inner covering portion 112 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides that are parallel to the periphery of the chip 2 in a plan view.
  • the second inner covering portion 112 is formed in a polygonal ring shape (specifically a square ring shape) that matches the planar shape of the second electrode surface 96 in a plan view.
  • the second inner covering portion 112 defines a second pad opening 117 that exposes the inner portion of the second electrode surface 96.
  • the second pad opening 117 is defined in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the second inner coating portion 112 may face the active region 12 across the first inorganic film 75 and the gate electrode 95. In other words, the second inner coating portion 112 may face one or more gate structures 25 and/or one or more first source structures 30 across the first inorganic film 75 and the gate electrode 95.
  • the second inner coating portion 112 may face the first termination region 15 across the first inorganic film 75 and the gate electrode 95. In other words, the second inner coating portion 112 may face one or more dummy gate structures 50 and/or one or more third source structures 55 across the first inorganic film 75 and the gate electrode 95.
  • the second inner coating portion 112 may face the third termination region 17 across the first inorganic film 75 and the gate electrode 95. In other words, the second inner coating portion 112 may face one or more fourth source structures 65 across the first inorganic film 75 and the gate electrode 95.
  • the second inner coating portion 112 preferably has a width greater than the thickness of the gate electrode 95.
  • the width of the second inner coating portion 112 may be less than the thickness of the gate electrode 95.
  • the width of the second inner coating portion 112 may be approximately equal to the width of the first inner coating portion 111.
  • the width of the second inner coating portion 112 may be less than the width of the first inner coating portion 111 or greater than the width of the first inner coating portion 111.
  • the width of the second inner coating portion 112 may be greater than or equal to 1 ⁇ m and less than or equal to 100 ⁇ m.
  • the width of the second inner coating portion 112 may have a value that falls within at least one of the following ranges: 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 40 ⁇ m or less, 40 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 60 ⁇ m or less, 60 ⁇ m or more and 70 ⁇ m or less, 70 ⁇ m or more and 80 ⁇ m or less, 80 ⁇ m or more and 90 ⁇ m or less, and 90 ⁇ m or more and 100 ⁇ m or less.
  • the second inner coating portion 112 is preferably formed at a distance from the second electrode sidewall 97 that is greater than the thickness of the gate electrode 95.
  • the distance between the second inner coating portions 112 may be less than the thickness of the gate electrode 95.
  • the distance between the second inner coating portions 112 may be approximately equal to the distance between the first inner coating portions 111.
  • the distance between the second inner coating portions 112 may be less than the distance between the first inner coating portions 111, or may be greater than the distance between the first inner coating portions 111.
  • the distance between the second inner coating portions 112 may be greater than or equal to 0.1 ⁇ m and less than or equal to 100 ⁇ m.
  • the spacing of the second inner coating portion 112 may have a value that falls within at least one of the following ranges: 0.1 ⁇ m to 1 ⁇ m, 1 ⁇ m to 5 ⁇ m, 5 ⁇ m to 10 ⁇ m, 10 ⁇ m to 20 ⁇ m, 20 ⁇ m to 30 ⁇ m, 30 ⁇ m to 40 ⁇ m, 40 ⁇ m to 50 ⁇ m, 50 ⁇ m to 60 ⁇ m, 60 ⁇ m to 70 ⁇ m, 70 ⁇ m to 80 ⁇ m, 80 ⁇ m to 90 ⁇ m, and 90 ⁇ m to 100 ⁇ m.
  • the outer coating portion 113 selectively coats the first inorganic film 75 at a distance from the first inner coating portion 111 and the second inner coating portion 112. Specifically, the outer coating portion 113 is formed on the coating portion of the first inorganic film 75 that covers the second surface portion 9. The outer coating portion 113 extends in a band shape along the first surface portion 8 in a plan view. The outer coating portion 113 is formed in a ring shape (a square ring shape in this embodiment) that surrounds the first surface portion 8 in a plan view.
  • the outer coating portion 113 covers the outer well region 70 and the multiple field regions 72 on the second surface portion 9 side, sandwiching the first inorganic film 75 therebetween.
  • the outer coating portion 113 enters the anchor opening 83 from above the first inorganic film 75 on the second surface portion 9 side, and is mechanically connected to the second surface portion 9 (second semiconductor region 7) within the anchor opening 83.
  • the outer coating portion 113 extends in a film-like shape along the second surface portion 9 within the anchor opening 83.
  • the outer coating portion 113 defines an anchor recess 118 that is recessed toward the anchor opening 83 in the coating portion that corresponds to the anchor opening 83.
  • the outer coating portion 113 defines multiple anchor recesses 118.
  • the anchor recesses 118 have a planar shape that is approximately similar to the planar shape of the anchor openings 83.
  • the anchor recesses 118 extend in a band shape (annular in this form) along the anchor openings 83 in a planar view.
  • the outer coating portion 113 is pulled out from the anchor opening 83 toward the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D).
  • the outer coating portion 113 is formed at a distance inward from the periphery of the second surface portion 9, exposing the first inorganic film 75 from the periphery of the second surface portion 9.
  • the outer coating portion 113 covers at least a portion of the source wiring 90 on the second surface portion 9 side. It is preferable that the outer coating portion 113 covers at least a portion of the first outer wall 93 of the source wiring 90. In this embodiment, the outer coating portion 113 covers the entire area of the source wiring 90 in a cross-sectional view.
  • the outer coating portion 113 coats the first wiring surface 91 of the source wiring 90 in a film-like manner, and extends flat over the first wiring surface 91 following the slope of the first wiring surface 91.
  • the outer coating portion 113 coats the first inner side wall 92 of the source wiring 90 in a film-like manner, and has an inclined surface that extends following the slope of the first inner side wall 92.
  • the outer coating portion 113 coats the first outer side wall 93 of the source wiring 90 in a film-like manner, and has an inclined surface that extends following the slope of the first outer side wall 93.
  • the outer coating portion 113 covers the entire source wiring 90 in a plan view, except for the connection portion of the source electrode 85 and the source wiring 90.
  • the outer coating portion 113 exposes the first outer wall 93 of the source wiring 90 at the connection portion of the source electrode 85 and the source wiring 90. This prevents stress generated in the source electrode 85 from being applied to the second inorganic film 110 via the source wiring 90.
  • the outer coating portion 113 is pulled out from the second surface portion 9 side to the first surface portion 8 side via the source wiring 90.
  • the outer coating portion 113 has a portion that faces the outer opening 81 with the source wiring 90 in between.
  • the outer coating portion 113 also has a portion that faces the sidewall wiring 79 with the first inorganic film 75 (upper inorganic film 77) and the source wiring 90 in between.
  • the outer covering portion 113 covers at least a portion of the gate wiring 100 on the first surface portion 8 side. It is preferable that the outer covering portion 113 covers at least a portion of the second outer wall 103 of the gate wiring 100. In this embodiment, the outer covering portion 113 covers the entire area of the gate wiring 100 in a cross-sectional view.
  • the outer covering portion 113 covers the second wiring surface 101 of the gate wiring 100 in a film-like manner, and extends flat over the second wiring surface 101 following the slope of the second wiring surface 101.
  • the outer covering portion 113 covers the second inner side wall 102 of the gate wiring 100 in a film-like manner, and has an inclined surface that extends following the slope of the second inner side wall 102.
  • the outer covering portion 113 covers the second outer side wall 103 of the gate wiring 100 in a film-like manner, and has an inclined surface that extends following the slope of the second outer side wall 103.
  • the outer coating portion 113 covers the entire gate wiring 100 in a plan view, except for the connection portion of the gate electrode 95 and the gate wiring 100.
  • the outer coating portion 113 exposes the second outer wall 103 of the gate wiring 100 at the connection portion of the gate electrode 95 and the gate wiring 100. This prevents stress generated in the gate electrode 95 from being applied to the second inorganic film 110 via the gate wiring 100.
  • the outer coating portion 113 covers the first inorganic film 75 at a distance from the first inner coating portion 111 and the second inner coating portion 112 on the first surface portion 8 side.
  • the outer coating portion 113 covers the first inorganic film 75 so as to expose at least a portion of the first electrode side wall 87 of the source electrode 85.
  • the outer covering portion 113 covers the first inorganic film 75 at a distance from the first electrode sidewall 87, exposing the entire area of the first electrode sidewall 87.
  • the outer covering portion 113 has an inner edge portion positioned between the first electrode sidewall 87 of the source electrode 85 and the second inner sidewall 102 of the gate wiring 100. The inner edge portion of the outer covering portion 113 extends along the first electrode sidewall 87 at a distance from the first electrode sidewall 87.
  • the outer coating portion 113 covers the first inorganic film 75 so as to expose at least a portion of the second electrode sidewall 97 of the gate electrode 95. In this embodiment, the outer coating portion 113 covers the first inorganic film 75 at a distance from the second electrode sidewall 97, exposing the entire area of the second electrode sidewall 97.
  • the outer covering portion 113 surrounds both the source electrode 85 and the gate electrode 95 collectively, with a gap therebetween in plan view.
  • the inner edge of the outer covering portion 113 is positioned between the first inner side wall 92 of the source wiring 90 and the second electrode side wall 97 of the gate electrode 95.
  • the inner edge of the outer covering portion 113 extends along the second electrode side wall 97, with a gap therebetween.
  • the outer coating portion 113 may face the active region 12 across the first inorganic film 75. In other words, the outer coating portion 113 may face one or more gate structures 25 and/or one or more first source structures 30 across the first inorganic film 75.
  • the outer coating portion 113 may face either one or both of the first side end region 13 and the second side end region 14 across the first inorganic film 75. In other words, the outer coating portion 113 may face one or more first source structures 30 and/or one or more second source structures 40 across the first inorganic film 75.
  • the outer coating portion 113 may face either one or both of the first termination region 15 and the second termination region 16 across the first inorganic film 75. In other words, the outer coating portion 113 may face one or more dummy gate structures 50 and/or one or more third source structures 55 across the first inorganic film 75.
  • the outer coating portion 113 may face either one or both of the third termination region 17 and the fourth termination region 18 across the first inorganic film 75. In other words, the outer coating portion 113 may face one or more fourth source structures 65 across the first inorganic film 75.
  • the removal portion 114 includes a first removal portion 114a, a second removal portion 114b, and a third removal portion 114c.
  • the first removal portion 114a is partitioned into an area between the first inner covering portion 111 and the outer covering portion 113, and exposes the first electrode sidewall 87 of the source electrode 85.
  • the first removal portion 114a extends in a strip shape along the first electrode sidewall 87, and exposes the peripheral portion of the first electrode surface 86, the first electrode sidewall 87, and the first inorganic film 75 between the source electrode 85 and the gate wiring 100.
  • the second removed portion 114b is defined in the region between the second inner covering portion 112 and the outer covering portion 113, and is connected to the first removed portion 114a.
  • the second removed portion 114b exposes the second electrode sidewall 97 of the gate electrode 95.
  • the second removed portion 114b extends in a strip shape along the second electrode sidewall 97, exposing the peripheral portion of the second electrode surface 96, the second electrode sidewall 97, and the first inorganic film 75 between the source wiring 90 and the gate electrode 95.
  • the third removed portion 114c is defined in the region between the first inner coating portion 111 and the second inner coating portion 112, and is connected to the first removed portion 114a and the second removed portion 114b.
  • the third removed portion 114c exposes the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95.
  • the third removed portion 114c extends in a band shape along the first electrode sidewall 87 and the second electrode sidewall 97, exposing the peripheral portion of the first electrode surface 86, the first electrode sidewall 87, the peripheral portion of the second electrode surface 96, the second electrode sidewall 97, and the first inorganic film 75 between the gate electrode 95 and the source electrode 85.
  • the semiconductor device 1 includes an insulating organic film 120 that selectively covers the second inorganic film 110.
  • the organic film 120 may be referred to as an "organic insulating film,” a "resin film,” or the like.
  • the organic film 120 preferably includes a transparent resin or a resin having translucency.
  • the organic film 120 preferably contains a photosensitive resin.
  • the photosensitive resin may be a negative type or a positive type.
  • the organic film 120 may contain at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.
  • the organic film 120 may have a thickness greater than the depth of the gate structure 25.
  • the thickness of the organic film 120 may be greater than the depth of the first source structure 30.
  • the thickness of the organic film 120 may be greater than the thickness (total thickness) of the first inorganic film 75.
  • the thickness of the organic film 120 may be greater than the thickness of the source electrode 85 (gate electrode 95).
  • the thickness of the organic film 120 may be greater than the thickness of the second inorganic film 110.
  • the thickness of the organic film 120 is preferably less than the thickness of the chip 2.
  • the thickness of the organic film 120 may be greater than the thickness of the second semiconductor region 7 or less than the thickness of the second semiconductor region 7.
  • the thickness of the organic film 120 may be 1 ⁇ m or more and 25 ⁇ m or less.
  • the thickness of the organic film 120 may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, and 20 ⁇ m or more and 25 ⁇ m or less.
  • the organic film 120 covers the second surface 9 from above the first surface 8 across the first to fourth connection surface sections 10A to 10D.
  • the organic film 120 fills in the removed portion 114 of the second inorganic film 110 on the first surface 8 side, and directly covers the first inner coating portion 111, the second inner coating portion 112, and the outer coating portion 113 of the second inorganic film 110.
  • the organic film 120 spans the first inner coating portion 111 and the outer coating portion 113, and has a portion that fills the area between the first inner coating portion 111 and the outer coating portion 113 (i.e., the first removed portion 114a).
  • the organic film 120 directly covers the first electrode side wall 87 of the source electrode 85 in the first removed portion 114a.
  • the organic film 120 directly covers the peripheral portion of the first electrode surface 86 and the first electrode sidewall 87 in the first removed portion 114a.
  • the organic film 120 directly covers the portion of the first inorganic film 75 exposed between the first electrode sidewall 87 of the source electrode 85 and the outer covering portion 113 (gate wiring 100) in the first removed portion 114a.
  • the organic film 120 spans the second inner coating portion 112 and the outer coating portion 113, and has a portion that fills the area between the second inner coating portion 112 and the outer coating portion 113 (i.e., the second removed portion 114b).
  • the organic film 120 directly covers the second electrode sidewall 97 of the gate electrode 95 in the second removed portion 114b.
  • the organic film 120 directly covers the peripheral portion of the second electrode surface 96 and the second electrode sidewall 97 in the second removed portion 114b.
  • the organic film 120 directly covers the portion of the first inorganic film 75 exposed between the second electrode sidewall 97 of the gate electrode 95 and the outer covering portion 113 (source wiring 90) in the second removed portion 114b.
  • the organic film 120 spans the first inner coating portion 111 and the second inner coating portion 112, and has a portion that fills the area between the first inner coating portion 111 and the second inner coating portion 112 (i.e., the third removed portion 114c).
  • the organic film 120 directly covers both the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95 in the third removed portion 114c.
  • the organic film 120 directly covers the peripheral portion of the first electrode surface 86, the first electrode sidewall 87, the peripheral portion of the second electrode surface 96, and the second electrode sidewall 97 in the third removed portion 114c.
  • the organic film 120 directly covers the portion of the first inorganic film 75 exposed between the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95 in the third removed portion 114c.
  • the organic film 120 covers the entire circumference of the first inner covering portion 111 and defines a first upper pad opening 121 that exposes the inner portion of the first electrode surface 86 (see Figures 1 to 3). Specifically, the organic film 120 covers the first inner covering portion 111 with a gap from the inner edge (inner wall) of the first inner covering portion 111 to the outer edge (outer wall) side, exposing the inner edge of the first inner covering portion 111. In other words, the wall surface of the first upper pad opening 121 is positioned closer to the first electrode side wall 87 than the wall surface of the first pad opening 116, and faces the first electrode surface 86 across the first inner covering portion 111.
  • the organic film 120 covers the entire periphery of the second inner covering portion 112 and defines a second upper pad opening 122 that exposes the inner portion of the second electrode surface 96 (see Figures 1 to 3). Specifically, the organic film 120 covers the second inner covering portion 112 with a gap from the inner edge (inner wall) of the second inner covering portion 112 toward the outer edge (outer wall) side, exposing the inner edge of the second inner covering portion 112. In other words, the wall surface of the second upper pad opening 122 is positioned closer to the second electrode side wall 97 than the wall surface of the second pad opening 117, and faces the second electrode surface 96 across the second inner covering portion 112.
  • the organic film 120 is extended from above the source electrode 85 and the gate electrode 95 toward the gate wiring 100, and covers at least a portion of the gate wiring 100 with the outer coating portion 113 in between. It is preferable that the organic film 120 covers the second outer wall 103 of the gate wiring 100 with the outer coating portion 113 in between.
  • the organic film 120 covers the entire gate wiring 100 with the outer coating portion 113 in between in a cross-sectional view. That is, the organic film 120 has a portion that covers the second wiring surface 101 with the outer coating portion 113 in between, a portion that covers the second inner side wall 102 with the outer coating portion 113 in between, and a portion that covers the second outer side wall 103 with the outer coating portion 113 in between.
  • the organic film 120 has a portion that directly covers the portion of the second outer wall 103 of the gate wiring 100 that is exposed from the second inner coating portion 112 and the outer coating portion 113 at the connection portion of the gate electrode 95 and the gate wiring 100.
  • the organic film 120 also covers the second wiring surface 101 of the gate wiring 100 at the connection portion of the gate electrode 95 and the gate wiring 100.
  • the organic film 120 is extended from above the gate wiring 100 toward the source wiring 90, and covers at least a portion of the source wiring 90 with the outer coating portion 113 in between.
  • the organic film 120 has a portion that directly covers the outer coating portion 113 in the region between the source wiring 90 and the gate wiring 100.
  • the organic film 120 preferably covers the first outer wall 93 of the source wiring 90, sandwiching the outer coating portion 113.
  • the organic film 120 covers the entire area of the source wiring 90, sandwiching the outer coating portion 113, in a cross-sectional view. That is, the organic film 120 has a portion that covers the first wiring surface 91, sandwiching the outer coating portion 113, a portion that covers the first inner wall 92, sandwiching the outer coating portion 113, and a portion that covers the first outer wall 93, sandwiching the outer coating portion 113, in a cross-sectional view.
  • the organic film 120 has a portion that directly covers the portion of the first outer wall 93 of the source wiring 90 that is exposed from the first inner coating portion 111 and the outer coating portion 113 at the connection portion of the source electrode 85 and the source wiring 90. In this embodiment, the organic film 120 also covers the first wiring surface 91 of the source wiring 90 at the connection portion of the source electrode 85 and the source wiring 90.
  • the organic film 120 is drawn from the first surface 8 side to the second surface 9 side via the source wiring 90.
  • the organic film 120 has a portion that faces the outer opening 81 with the source wiring 90 in between.
  • the organic film 120 also has a portion that faces the sidewall wiring 79 with the source wiring 90 in between.
  • the organic film 120 covers the outer well region 70 and the multiple field regions 72 on the second surface 9 side, sandwiching the first inorganic film 75 and the second inorganic film 110.
  • the organic film 120 covers the anchor opening 83 on the periphery of the second surface 9, sandwiching the second inorganic film 110.
  • the organic film 120 engages with the anchor recess 118 of the second inorganic film 110 (anchor opening 83 of the first inorganic film 75).
  • the organic film 120 is pulled out from the anchor opening 83 toward the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D).
  • the organic film 120 is formed at a distance inward from the periphery of the second surface portion 9, exposing the first inorganic film 75 from the periphery of the second surface portion 9.
  • the organic film 120 covers the outer coating portion 113 at a distance inward from the outer edge (outer wall) of the outer coating portion 113, exposing the outer edge of the outer coating portion 113.
  • the semiconductor device 1 includes a drain electrode 125 covering the second main surface 4.
  • the drain electrode 125 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain electrode 125 may be referred to as an "electrode”, a “third electrode”, a “third pad electrode”, a “third main surface electrode”, a “third terminal electrode”, a “drain pad electrode”, etc.
  • the drain electrode 125 is electrically connected to the first semiconductor region 6.
  • the drain electrode 125 may cover the entire second major surface 4 so as to be continuous with the periphery of the second major surface 4 (the first to fourth side surfaces 5A to 5D).
  • the drain electrode 125 may partially cover the second major surface 4 so as to expose the periphery of the second major surface 4.
  • the breakdown voltage that can be applied between the source electrode 85 and the drain electrode 125 (between the first major surface 3 and the second major surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that falls within at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • the semiconductor device 1 includes the insulating first inorganic film 75 (subject to be covered), the source electrode 85 (electrode), the source wiring 90 (wiring), the insulating second inorganic film 110 (inorganic film), and the insulating organic film 120.
  • the source electrode 85 is disposed on the first inorganic film 75, and has a first electrode sidewall 87 on the first inorganic film 75.
  • the source wiring 90 is disposed around the source electrode 85 on the first inorganic film 75.
  • the second inorganic film 110 has a first inner coating portion 111 that covers the source electrode 85 so as to expose the first electrode sidewall 87, and an outer coating portion 113 that covers the source wiring 90 at a distance from the first inner coating portion 111.
  • the organic film 120 spans the first inner coating portion 111 and the outer coating portion 113, and covers the source electrode 85 between the first inner coating portion 111 and the outer coating portion 113.
  • This configuration provides a semiconductor device 1 with a novel layout. Since the semiconductor device 1 is used in various environments depending on the application, the semiconductor device 1 is required to have durability suitable for various environmental conditions.
  • the semiconductor device 1 when the semiconductor device 1 is mounted on a vehicle that uses a motor as a drive source, such as a hybrid vehicle, an electric vehicle, or a fuel cell vehicle, excellent durability that is compatible with the environmental conditions under which the semiconductor device 1 is used is required.
  • the durability of the semiconductor device 1 is evaluated, for example, by a high-temperature, high-humidity bias test. In the high-temperature, high-humidity bias test, the electrical operation of the semiconductor device 1 is evaluated while exposed to a high-temperature, high-humidity environment.
  • the first inner coating portion 111 of the second inorganic film 110 exposes the first electrode sidewall 87, and the outer coating portion 113 of the second inorganic film 110 is formed at a distance from the first inner coating portion 111. This reduces the starting points for peeling of the second inorganic film 110 caused by stress of the source electrode 85, and suppresses peeling of the second inorganic film 110.
  • the organic film 120 covers the exposed portion of the source electrode 85 in the region between the first inner coating portion 111 and the outer coating portion 113.
  • the organic film 120 has a hardness lower than that of the second inorganic film 110. Therefore, even if stress due to thermal expansion occurs in the source electrode 85, the organic film 120 elastically absorbs the stress. This prevents the organic film 120 from peeling off from the first electrode sidewall 87, and the source electrode 85 is protected by the organic film 120.
  • an electric field higher than the electric field on the source electrode 85 side may be concentrated near the source wiring 90. If moisture (water) reaches the source wiring 90 from the peeled portion in a high-temperature environment, the oxidation reaction of the moisture (water) and the source wiring 90 may be accelerated due to the high electric field near the source wiring 90.
  • the source wiring 90 is protected by the outer coating portion 113, which prevents moisture (water) from coming into contact with the source wiring 90. This prevents oxidation of the source wiring 90. As a result, a decrease in the adhesion of the organic film 120 caused by the oxidized portion and a decrease in the wiring resistance of the source wiring 90 are prevented.
  • the source wiring 90 has a first outer wall 93 (wiring side wall) on the opposite side to the source electrode 85 in a cross-sectional view.
  • the outer coating portion 113 of the second inorganic film 110 covers the first outer wall 93 of the source wiring 90 in a cross-sectional view.
  • the organic film 120 covers the first outer side wall 93 of the source wiring 90 with the outer coating portion 113 sandwiched therebetween in a cross-sectional view.
  • the outer coating portion 113 may cover the entire area of the source wiring 90 in a cross-sectional view.
  • the organic film 120 may cover the entire area of the source wiring 90, sandwiching the outer coating portion 113 in a cross-sectional view.
  • the first inner coating portion 111 preferably covers the source electrode 85 at a distance from the first electrode sidewall 87. With this configuration, peeling of the first inner coating portion 111 due to thermal expansion of the source electrode 85 is appropriately suppressed.
  • the outer coating portion 113 preferably exposes the first electrode sidewall 87. With this configuration, peeling of the outer coating portion 113 caused by thermal expansion of the source electrode 85 is appropriately suppressed.
  • the outer coating portion 113 preferably covers the first inorganic film 75 at a distance from the first electrode sidewall 87.
  • the organic film 120 preferably has a portion that directly covers the first electrode sidewall 87. With this configuration, the first electrode sidewall 87 is appropriately protected by the organic film 120.
  • the first inner covering portion 111 preferably exposes the peripheral portion of the source electrode 85.
  • the organic film 120 preferably has a portion that directly covers the first electrode sidewall 87 of the source electrode 85 and the peripheral portion of the source electrode 85.
  • the organic film 120 has a portion that directly covers the exposed portion of the first inorganic film 75 between the source electrode 85 and the outer covering portion 113 in the region between the source electrode 85 and the source wiring 90 . It is preferable that the organic film 120 has a portion that directly covers the exposed portion of the first inorganic film 75 between the source electrode 85 and the outer covering portion 113.
  • the first inner covering part 111 preferably exposes the inner part of the source electrode 85.
  • the inner part of the source electrode 85 is used as an end for applying a potential.
  • the organic film 120 may expose the edge of the first inner covering part 111 on the inner side of the source electrode 85.
  • the source wiring 90 may be electrically connected to the source electrode 85.
  • the source wiring 90 may be drawn out from the source electrode 85.
  • the source wiring 90 may be the outermost wiring.
  • the semiconductor device 1 may include a gate wiring 100 (second wiring) disposed in a region between the source electrode 85 and the source wiring 90 on the first inorganic film 75.
  • the gate wiring 100 is electrically separated from the source wiring 90.
  • the organic film 120 may cover the gate wiring 100. With this configuration, the gate wiring 100 is protected by the organic film 120.
  • the outer coating portion 113 may cover the gate wiring 100.
  • the organic film 120 may cover the gate wiring 100 with the outer coating portion 113 in between.
  • the outer coating portion 113 prevents moisture (water) from coming into contact with the gate wiring 100. This prevents oxidation of the gate wiring 100.
  • the outer coating portion 113 may cover the entire area of the gate wiring 100 in a cross-sectional view.
  • the organic film 120 may cover the entire area of the gate wiring 100, sandwiching the outer coating portion 113 in a cross-sectional view.
  • the first inorganic film 75 may have an anchor opening 83.
  • the second inorganic film 110 may have a portion located within the anchor opening 83.
  • the adhesion of the second inorganic film 110 to the first inorganic film 75 is increased by the anchor opening 83. This prevents the second inorganic film 110 from peeling off from the first inorganic film 75.
  • the creeping distance is increased by the anchor opening 83, which prevents moisture (water) from entering.
  • the organic film 120 may cover a portion of the second inorganic film 110 that covers the anchor opening 83. With this configuration, the adhesion of the organic film 120 to the second inorganic film 110 is increased by the unevenness of the second inorganic film 110 caused by the anchor opening 83. This suppresses peeling of the organic film 120 from the second inorganic film 110.
  • the semiconductor device 1 may include a chip 2.
  • the first inorganic film 75 may be formed on the chip 2.
  • the semiconductor device 1 may include an active region 12 provided in the inner part of the chip 2, and an outer periphery region 19 provided on the periphery of the chip 2.
  • the first inorganic film 75 may cover both the active region 12 and the outer periphery region 19.
  • the source electrode 85 may be disposed on the active region 12.
  • the source wiring 90 may be disposed on the outer periphery region 19.
  • the electric field on the peripheral region 19 side is likely to be higher than the electric field on the active region 12 side. Therefore, an electric field higher than the electric field on the source electrode 85 side may concentrate on the source wiring 90 on the peripheral region 19 side. Therefore, if moisture (water) enters from the peripheral region 19 side, the risk of oxidation is higher for the source wiring 90 than for the source electrode 85. Therefore, a configuration in which the source wiring 90 is protected by the outer coating portion 113 is particularly effective in a configuration in which the source wiring 90 is disposed in the peripheral region 19.
  • the chip 2 preferably contains SiC.
  • the semiconductor device 1 is provided as a SiC semiconductor device.
  • a SiC semiconductor device exhibits excellent electrical characteristics and durability in harsh operating environments.
  • the semiconductor device 1 includes a source electrode 85 (terminal electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120.
  • the source wiring 90 is disposed around the source electrode 85.
  • the second inorganic film 110 covers the source wiring 90 with a gap between it and the source electrode 85.
  • the organic film 120 has a portion that directly covers the source electrode 85, and a portion that covers the source wiring 90 with the second inorganic film 110 in between.
  • This configuration provides a semiconductor device 1 with a novel layout.
  • the semiconductor device 1 suppresses peeling of the second inorganic film 110 caused by stress in the source electrode 85, and the second inorganic film 110 suppresses oxidation of the source wiring 90.
  • both the source electrode 85 and the source wiring 90 are protected by the organic film 120.
  • the semiconductor device 1 includes a first region (12), a second region (19), a source electrode 85 (terminal electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120.
  • the first region (12) has a first electric field.
  • the second region (19) has a second electric field around the first region (12) that is higher than the first electric field.
  • the active region 12 is exemplified as one aspect of the first region (12)
  • the peripheral region 19 is exemplified as one aspect of the second region (19).
  • the source electrode 85 is disposed in the first region (12).
  • the source wiring 90 is disposed in the second region (19) around the source wiring 90.
  • the second inorganic film 110 exposes the source electrode 85 and covers the source wiring 90.
  • the organic film 120 has a portion that directly covers the source electrode 85 and a portion that covers the source wiring 90 with the second inorganic film 110 in between.
  • This configuration provides a semiconductor device 1 with a novel layout.
  • the semiconductor device 1 suppresses peeling of the second inorganic film 110 caused by stress in the source electrode 85, and the second inorganic film 110 suppresses oxidation of the source wiring 90.
  • the semiconductor device 1 suppresses moisture (moisture) and oxidation reactions of the source wiring 90 caused by the second electric field near the source wiring 90.
  • both the source electrode 85 and the source wiring 90 are protected by the organic film 120.
  • the semiconductor device 1 includes a chip 2, an active region 12, a peripheral region 19, a transistor structure Tr (device structure), an outer well region 70 (impurity region), a source electrode 85 (electrode), a source wiring 90 (wiring), an insulating second inorganic film 110, and an insulating organic film 120.
  • the chip 2 has a first main surface 3.
  • the active region 12 is provided in the inner portion of the first main surface 3.
  • the peripheral region 19 is provided in the peripheral portion of the first main surface 3.
  • the transistor structure Tr is formed in the first main surface 3 in the active region 12.
  • the outer well region 70 is formed in the surface layer portion of the first main surface 3 in the peripheral region 19.
  • the source electrode 85 is disposed on the first main surface 3 in the active region 12 and is electrically connected to the transistor structure Tr.
  • the source wiring 90 is disposed on the first main surface 3 in the peripheral region 19 and is electrically connected to the outer well region 70.
  • the second inorganic film 110 exposes the source electrode 85 and covers the source wiring 90.
  • the organic film 120 has a portion that directly covers the source electrode 85 and a portion that covers the source wiring 90 with the second inorganic film 110 in between.
  • This configuration provides a semiconductor device 1 with a novel layout.
  • the semiconductor device 1 suppresses peeling of the second inorganic film 110 caused by stress in the source electrode 85, and the second inorganic film 110 suppresses oxidation of the source wiring 90.
  • the semiconductor device 1 suppresses moisture (moisture) and oxidation reactions of the source wiring 90 caused by the electric field near the source wiring 90.
  • both the source electrode 85 and the source wiring 90 are protected by the organic film 120.
  • the source electrode 85 may be replaced with a gate electrode 95, and the source wiring 90 may be replaced with a gate wiring 100.
  • the semiconductor device 1 includes an insulating first inorganic film 75 (subject to be covered), a gate electrode 95 (electrode), a gate wiring 100 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120.
  • the gate electrode 95 is disposed on the first inorganic film 75, and has a second electrode sidewall 97 on the first inorganic film 75.
  • the gate wiring 100 is disposed around the gate electrode 95 on the first inorganic film 75.
  • the second inorganic film 110 has a second inner coating portion 112 that covers the gate electrode 95 so as to expose the second electrode sidewall 97, and an outer coating portion 113 that covers the gate wiring 100 at a distance from the second inner coating portion 112.
  • the organic film 120 spans the second inner coating portion 112 and the outer coating portion 113, and covers the gate electrode 95 between the second inner coating portion 112 and the outer coating portion 113.
  • This configuration provides a semiconductor device 1 with a novel layout.
  • the semiconductor device 1 suppresses peeling of the second inorganic film 110 caused by stress in the gate electrode 95, and the second inorganic film 110 suppresses oxidation of the gate wiring 100.
  • both the gate electrode 95 and the gate wiring 100 are protected by the organic film 120.
  • the semiconductor device 1 (electronic component) includes an insulating first inorganic film 75 (subject to be covered), a source electrode 85 (electrode), a gate wiring 100 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120.
  • the source electrode 85 is disposed on the first inorganic film 75, and has a first electrode sidewall 87 on the first inorganic film 75.
  • the gate wiring 100 is disposed around the source electrode 85 on the first inorganic film 75.
  • the second inorganic film 110 has a first inner coating portion 111 that covers the source electrode 85 so as to expose the first electrode sidewall 87, and an outer coating portion 113 that covers the gate wiring 100 at a distance from the first inner coating portion 111.
  • the organic film 120 spans the first inner coating portion 111 and the outer coating portion 113, and covers the source electrode 85 between the first inner coating portion 111 and the outer coating portion 113.
  • This configuration provides a semiconductor device 1 with a novel layout.
  • the semiconductor device 1 suppresses peeling of the second inorganic film 110 caused by stress in the source electrode 85, and the second inorganic film 110 suppresses oxidation of the gate wiring 100.
  • both the source electrode 85 and the gate wiring 100 are protected by the organic film 120.
  • the semiconductor device 1 (electronic component) includes an insulating first inorganic film 75 (subject to be covered), a gate electrode 95 (electrode), a source wiring 90 (wiring), an insulating second inorganic film 110 (inorganic film), and an insulating organic film 120.
  • the gate electrode 95 is disposed on the first inorganic film 75, and has a second electrode sidewall 97 on the first inorganic film 75.
  • the source wiring 90 is disposed around the gate electrode 95 on the first inorganic film 75.
  • the second inorganic film 110 has a second inner coating portion 112 that covers the gate electrode 95 so as to expose the second electrode sidewall 97, and an outer coating portion 113 that covers the source wiring 90 at a distance from the second inner coating portion 112.
  • the organic film 120 spans the second inner coating portion 112 and the outer coating portion 113, and covers the gate electrode 95 between the second inner coating portion 112 and the outer coating portion 113.
  • This configuration provides a semiconductor device 1 with a novel layout.
  • the semiconductor device 1 suppresses peeling of the second inorganic film 110 caused by stress in the gate electrode 95, and the second inorganic film 110 suppresses oxidation of the source wiring 90.
  • both the gate electrode 95 and the source wiring 90 are protected by the organic film 120.
  • Figures 22A to 22R are cross-sectional views showing second to sixth layout examples of the second inorganic film 110.
  • Figures 22F to 22H are enlarged plan views showing seventh to ninth layout examples of the second inorganic film 110.
  • Figures 22I to 22R are cross-sectional views showing tenth to nineteenth layout examples of the second inorganic film 110.
  • the semiconductor device 1 can include the features of any one of the second inorganic films 110 according to the first to nineteenth layout examples.
  • the features of the second inorganic films 110 according to the first to nineteenth layout examples can be appropriately combined.
  • the semiconductor device 1 can include at least two of the features of the second inorganic films 110 according to the first to nineteenth layout examples simultaneously in the same or different regions.
  • the second inorganic film 110 may have an outer covering portion 113 that exposes the second inner side wall 102 of the gate wiring 100 and covers the second wiring surface 101 of the gate wiring 100 and the second outer side wall 103 of the gate wiring 100.
  • the outer covering portion 113 may have an inner edge portion positioned on the second wiring surface 101 of the gate wiring 100.
  • the organic film 120 has a portion that directly covers the first inorganic film 75 in the region (first removed portion 114a) between the source electrode 85 and the gate wiring 100.
  • the organic film 120 directly covers the second inner side wall 102 of the gate wiring 100, and covers the second outer side wall 103 of the gate wiring 100 with the outer coating portion 113 in between.
  • the organic film 120 has a portion that directly covers the second wiring surface 101 of the gate wiring 100, and a portion that covers the second wiring surface 101 of the gate wiring 100 with the outer coating portion 113 in between.
  • the second inorganic film 110 may have an outer covering portion 113 that exposes the entire gate wiring 100.
  • the outer covering portion 113 may have an inner edge portion located in the region between the source wiring 90 and the gate wiring 100.
  • the inner edge portion of the outer covering portion 113 may cover the first inorganic film 75 with a gap from the second outer wall 103 of the gate wiring 100 toward the source wiring 90.
  • the organic film 120 has a portion in the first removed portion 114a that directly covers the second wiring surface 101, the second inner wall 102, and the second outer wall 103 of the gate wiring 100. In this embodiment, the organic film 120 has a portion in the region between the source wiring 90 and the gate wiring 100 that directly covers the first inorganic film 75, and a portion that covers the first inorganic film 75 with the second inorganic film 110 sandwiched therebetween.
  • the second inorganic film 110 may have an outer coating portion 113 that exposes the first inner side wall 92 of the source wiring 90 and covers the first wiring surface 91 of the source wiring 90 and the first outer side wall 93 of the source wiring 90.
  • the outer coating portion 113 may have an inner edge portion positioned on the first wiring surface 91 of the source wiring 90.
  • the inner edge portion of the outer coating portion 113 may face the first surface portion 8 across the source wiring 90.
  • the organic film 120 directly covers the second wiring surface 101, the second inner wall 102, and the second outer wall 103 of the gate wiring 100 in the first removed portion 114a.
  • the organic film 120 directly covers the first inorganic film 75 in the region between the source wiring 90 and the gate wiring 100.
  • the organic film 120 directly covers the first inner side wall 92 of the source wiring 90, and covers the first outer side wall 93 of the source wiring 90 with the outer coating portion 113 in between.
  • the organic film 120 has a portion that directly covers the first wiring surface 91 of the source wiring 90, and a portion that covers the first wiring surface 91 of the gate wiring 100 with the outer coating portion 113 in between.
  • the second inorganic film 110 may have an outer coating portion 113 that exposes the first inner sidewall 92 of the source wiring 90 and covers the first wiring surface 91 of the source wiring 90 and the first outer sidewall 93 of the source wiring 90.
  • the outer coating portion 113 may have an inner edge portion located on the first wiring surface 91 of the source wiring 90.
  • the inner edge portion of the outer coating portion 113 may face the second surface portion 9 across the source wiring 90.
  • the inner edge portion of the outer coating portion 113 may be located closer to the first outer side wall 93 than the outer opening 81, or may be located closer to the first inner side wall 92 than the outer opening 81.
  • the organic film 120 directly covers the second wiring surface 101, the second inner wall 102, and the second outer wall 103 of the gate wiring 100 in the first removed portion 114a.
  • the organic film 120 directly covers the first inorganic film 75 in the region between the source wiring 90 and the gate wiring 100.
  • the organic film 120 directly covers the first inner side wall 92 of the source wiring 90, and covers the first outer side wall 93 of the source wiring 90 with the outer coating portion 113 in between.
  • the organic film 120 has a portion that directly covers the first wiring surface 91 of the source wiring 90, and a portion that covers the first wiring surface 91 of the gate wiring 100 with the outer coating portion 113 in between.
  • the second inorganic film 110 may have an outer coating portion 113 that is spaced apart from the first inner coating portion 111 and covers the first electrode side wall 87 of the source electrode 85.
  • the outer coating portion 113 may have an inner edge portion located on the peripheral portion of the first electrode surface 86 of the source electrode 85.
  • the outer coating portion 113 may expose the peripheral portion of the first electrode surface 86 of the source electrode 85 together with the first inner coating portion 111.
  • the first removed portion 114a may expose only the peripheral portion of the first electrode surface 86 of the source electrode 85.
  • the organic film 120 covers the first electrode sidewall 87 of the source electrode 85 with the outer covering portion 113 in between.
  • the organic film 120 has a portion that covers the peripheral portion of the first electrode surface 86 of the source electrode 85 with the outer covering portion 113 in between.
  • the organic film 120 has a portion that directly covers the portion of the peripheral portion of the first electrode surface 86 that is exposed from the first inner covering portion 111 and the outer covering portion 113.
  • the organic film 120 may directly cover only the peripheral portion of the first electrode surface 86 in the first removed portion 114a.
  • the second inorganic film 110 may have one or more first openings 131 formed in the first inner covering portion 111 so as to expose the first electrode surface 86 of the source electrode 85.
  • the multiple first openings 131 may be formed at intervals along the extension direction of the first inner covering portion 111.
  • the multiple first openings 131 may be partitioned into a strip shape, a square shape, a rectangular shape, a polygonal shape, a circle shape, etc. in a plan view.
  • the second inorganic film 110 may have one or more second openings 132 formed in the second inner covering portion 112 so as to expose the second electrode surface 96 of the gate electrode 95.
  • the multiple second openings 132 may be formed at intervals along the extension direction of the second inner covering portion 112.
  • the multiple second openings 132 may be partitioned into a strip shape, a square shape, a rectangular shape, a polygonal shape, a circle shape, etc. in a plan view.
  • the organic film 120 penetrates the first inner coating portion 111 through the first openings 131 and is connected to the first electrode surface 86 of the source electrode 85 within the first openings 131.
  • the adhesion of the organic film 120 to the first inner coating portion 111 (second inorganic film 110) is increased by the first openings 131.
  • the organic film 120 penetrates the second openings 132 from above the second inner coating portion 112 and is connected to the second electrode surface 96 of the gate electrode 95 within the second openings 132.
  • the adhesion of the organic film 120 to the second inner coating portion 112 (second inorganic film 110) is increased by the second openings 132.
  • the second inorganic film 110 may have a plurality of first inner coating portions 111 arranged at intervals from the first electrode sidewall 87 side of the source electrode 85 to the inner side of the source electrode 85.
  • the first inner covering portion 111 arranged on the inner side of the source electrode 85 defines the first pad opening 116.
  • the multiple first inner covering portions 111 may each be formed in a band shape with ends or a band shape without ends extending along the first electrode side wall 87 of the source electrode 85.
  • the multiple first inner covering portions 111 may each be formed in a ring shape surrounding the inner portion of the source electrode 85.
  • the second inorganic film 110 may have a plurality of second inner covering portions 112 arranged at intervals from the second electrode sidewall 97 side of the gate electrode 95 to the inner side of the gate electrode 95.
  • the second inner covering portion 112 arranged on the inner side of the source electrode 85 defines a second pad opening 117.
  • the plurality of second inner covering portions 112 may each be formed in a band shape with ends or a band shape without ends extending along the second electrode sidewall 97 of the gate electrode 95.
  • the plurality of second inner covering portions 112 may each be formed in a ring shape surrounding the inner portion of the gate electrode 95.
  • the organic film 120 penetrates from above the multiple first inner coating portions 111 into the region (opening) between the multiple first inner coating portions 111, and is connected to the first electrode surface 86 of the source electrode 85 in the region between the multiple first inner coating portions 111.
  • the adhesion of the organic film 120 to the first inner coating portion 111 (second inorganic film 110) is increased by the multiple first inner coating portions 111.
  • the organic film 120 penetrates from above the multiple second inner coating portions 112 into the region (opening) between the multiple second inner coating portions 112, and is connected to the second electrode surface 96 of the gate electrode 95 in the region between the multiple second inner coating portions 112.
  • the adhesion of the organic film 120 to the second inner coating portion 112 (second inorganic film 110) is enhanced by the multiple second inner coating portions 112.
  • the second inorganic film 110 may have a plurality of first inner covering portions 111 arranged at intervals along the first electrode side wall 87 of the source electrode 85.
  • the plurality of first inner covering portions 111 may be formed in a strip shape, a square shape, a rectangular shape, a polygonal shape, a circle shape, etc. in a plan view.
  • the second inorganic film 110 may have a plurality of second inner coating portions 112 arranged at intervals along the second electrode sidewall 97 of the gate electrode 95.
  • the plurality of second inner coating portions 112 may be formed in a strip shape, a square shape, a rectangular shape, a polygonal shape, a circle shape, etc. in a plan view.
  • the organic film 120 penetrates from above the multiple first inner coating portions 111 into the region (opening) between the multiple first inner coating portions 111, and is connected to the first electrode surface 86 of the source electrode 85 in the region between the multiple first inner coating portions 111.
  • the adhesion of the organic film 120 to the first inner coating portion 111 (second inorganic film 110) is increased by the multiple first inner coating portions 111.
  • the organic film 120 penetrates from above the multiple second inner coating portions 112 into the region (opening) between the multiple second inner coating portions 112, and is connected to the second electrode surface 96 of the gate electrode 95 in the region between the multiple second inner coating portions 112.
  • the adhesion of the organic film 120 to the second inner coating portion 112 (second inorganic film 110) is enhanced by the multiple second inner coating portions 112.
  • the second inorganic film 110 may have an outer coating portion 113 exposed from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.
  • the outer coating portion 113 may be formed flush with at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.
  • the second inorganic film 110 may have an outer coating portion 113 that is positioned inward from the outer edge of the organic film 120.
  • the organic film 120 may protrude outward from the outer edge of the outer coating portion 113.
  • the second inorganic film 110 may have an outer coating portion 113 positioned inside the organic film 120.
  • the organic film 120 may cover the outer edge of the outer coating portion 113.
  • the first inorganic film 75 may have a cutout portion 133 formed at a distance inward from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D, exposing the peripheral portion of the second surface portion 9 (second semiconductor region 7).
  • the second inorganic film 110 may have an outer coating portion 113 having an outer edge portion disposed on the first inorganic film 75 at a distance inward from the cutout portion 133.
  • the first inorganic film 75 may have a cutout portion 133, as in the 13th layout example.
  • the second inorganic film 110 may have an outer covering portion 113 that enters the cutout portion 133 from above the first inorganic film 75 and has a portion that directly covers the peripheral portion of the second surface portion 9 within the cutout portion 133.
  • the outer covering portion 113 may be formed at a distance inward from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.
  • the second inorganic film 110 may have an outer coating portion 113 positioned within the cutout portion 133, as in the 14th layout example.
  • the outer coating portion 113 may be exposed from at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.
  • the outer coating portion 113 may be formed flush with at least one (e.g., all) of the first to fourth side surfaces 5A to 5D.
  • the second inorganic film 110 may have a first inner covering portion 111 positioned inward from the inner edge of the organic film 120.
  • the organic film 120 may extend inward from the source electrode 85 (first electrode surface 86) beyond the inner edge of the first inner covering portion 111.
  • the wall surface of the first upper pad opening 121 may be located closer to the inside of the first electrode surface 86 than the wall surface of the first pad opening 116.
  • the wall surface of the first upper pad opening 121 may be formed at a distance from the first electrode surface 86 in the stacking direction.
  • the second inorganic film 110 may have a second inner coating portion 112 positioned inward from the inner edge of the organic film 120.
  • the organic film 120 may extend inward from the gate electrode 95 (second electrode surface 96) beyond the inner edge of the second inner coating portion 112.
  • the wall surface of the second upper pad opening 122 may be located closer to the inside of the second electrode surface 96 than the wall surface of the second pad opening 117.
  • the wall surface of the second upper pad opening 122 may be formed at a distance from the second electrode surface 96 in the stacking direction.
  • the second inorganic film 110 may have a first inner coating portion 111 located inside the organic film 120.
  • the organic film 120 may cover the inner edge portion of the first inner coating portion 111.
  • the organic film 120 may cover the entire area of the first inner coating portion 111.
  • the organic film 120 may directly cover the source electrode 85 (first electrode surface 86) in a region that is more inward than the inner edge of the first inner covering portion 111.
  • the wall surface of the first upper pad opening 121 may be located more inward of the first electrode surface 86 than the wall surface of the first pad opening 116.
  • the wall surface of the first upper pad opening 121 may directly cover the first electrode surface 86 in a region that is more inward than the inner edge of the first inner covering portion 111.
  • the second inorganic film 110 may have a second inner coating portion 112 positioned inside the organic film 120.
  • the organic film 120 may cover the inner edge portion of the second inner coating portion 112.
  • the organic film 120 may cover the entire area of the second inner coating portion 112.
  • the organic film 120 may directly cover the gate electrode 95 (second electrode surface 96) in a region that is more inward than the inner edge of the second inner covering portion 112.
  • the wall surface of the second upper pad opening 122 may be located more inward of the second electrode surface 96 than the wall surface of the second pad opening 117.
  • the wall surface of the second upper pad opening 122 may directly cover the second electrode surface 96 in a region that is more inward than the inner edge of the second inner covering portion 112.
  • the second inorganic film 110 does not necessarily have to have the first inner covering portion 111, and the entire area of the source electrode 85 may be exposed. In this case, it is sufficient that the second inorganic film 110 has at least the outer covering portion 113.
  • the second inorganic film 110 may have the second inner covering portion 112, or may not have the second inner covering portion 112.
  • the organic film 120 directly covers the peripheral portion of the first electrode surface 86 and the first electrode sidewall 87 at the peripheral portion of the source electrode 85 without going through the first inner covering portion 111.
  • the wall surface of the first upper pad opening 121 may directly cover the peripheral portion of the first electrode surface 86.
  • the second inorganic film 110 does not necessarily have to have the second inner coating portion 112, and the entire area of the gate electrode 95 may be exposed. In this case, it is sufficient that the second inorganic film 110 has at least the outer coating portion 113.
  • the second inorganic film 110 may have the first inner coating portion 111, or may not have the first inner coating portion 111.
  • the organic film 120 directly covers the peripheral portion of the second electrode surface 96 and the second electrode side wall 97 at the peripheral portion of the source electrode 85 without going through the second inner covering portion 112.
  • the wall surface of the second upper pad opening 122 may directly cover the peripheral portion of the second electrode surface 96.
  • the above-mentioned embodiment (including modified examples) can be implemented in other embodiments.
  • the above-mentioned embodiment shows an example in which the first main surface 3 is partitioned into mesas 11 (first surface portion 8, second surface portion 9, and first to fourth connection surface portions 10A to 10D).
  • the first main surface 3 does not necessarily have to have mesas 11, and may be formed flat.
  • the outer well region 70 defines the active region 12 and the peripheral region 19. Also, in this case, the first side end region 13, the second side end region 14, the first termination region 15, the second termination region 16, the third termination region 17, and the fourth termination region 18 may be removed.
  • the anchor opening 83 was formed in the first inorganic film 75.
  • a first inorganic film 75 that does not have an anchor opening 83 may also be used.
  • the source wiring 90 is connected to the source electrode 85.
  • the source wiring 90 may be electrically separated from the source electrode 85.
  • the source wiring 90 may be formed in an electrically floating state as a floating wiring or a field wiring (a so-called field preplate).
  • a structure may be adopted in which the conductivity type of the "n-type” semiconductor region is inverted to "p-type” and the conductivity type of the "p-type” semiconductor region is inverted to "n-type".
  • a specific configuration in this case can be obtained by replacing “n-type” with “p-type” and at the same time replacing "p-type” with “n-type” in the above description and the attached drawings.
  • the chip 2 including a SiC single crystal is used.
  • the chip 2 may include a silicon single crystal.
  • the first semiconductor region 6 may include a silicon single crystal.
  • the second semiconductor region 7 may include a silicon single crystal.
  • a p-type collector region may be formed in the surface layer of the second main surface 4 of the chip 2.
  • the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of a MISFET structure.
  • IGBT Insulated Gate Bipolar Transistor
  • a specific configuration in this case is obtained by replacing the "source” of the MISFET structure with the "emitter” of the IGBT structure, and replacing the "drain” of the MISFET structure with the "collector” of the IGBT structure in the above description.
  • the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.
  • the first semiconductor region 6 (second semiconductor region 7) may be formed as part or all of the cathode region of the semiconductor rectifier device (diode), and the body region 20 may be formed as part or all of the anode region of the semiconductor rectifier device (diode).
  • the source electrode 85 is formed as an anode electrode
  • the drain electrode 125 is formed as a cathode electrode.
  • a Schottky electrode anode electrode
  • An electronic component (1) including electrodes (85, 95) arranged in a first region (12) having a first electric field, wiring (90) arranged in a second region (19) having a second electric field higher than the first electric field around the electrodes (85, 95), an insulating inorganic film (110) exposing the electrodes (85, 95) and covering the wiring (90), and an insulating organic film (120) having a portion that directly covers the electrodes (85, 95) and a portion that covers the wiring (90) with the inorganic film (110) sandwiched therebetween.
  • An electronic component (1) according to any one of B1 to B7, further comprising a chip (2), the first region (12) being formed in the chip (2), the second region (19) being formed around the first region (12) in the chip (2), the electrodes (85, 95) being disposed on the first region (12), and the wiring (90) being disposed on the second region (19).
  • a chip (2) having a main surface (3), an active region (12) provided in an inner portion of the main surface (3), an outer peripheral region (19) provided on the periphery of the main surface (3), a device structure (Tr) formed on the main surface (3) in the active region (12), an impurity region (70) formed on the surface layer of the main surface (3) in the outer peripheral region (19), and a semiconductor device (10) disposed on the main surface (3) in the active region (12) and configured to include the device structure (Tr).
  • An electronic component (1) including an electrode (85) electrically connected to the impurity region (70), a wiring (90) disposed on the main surface (3) in the peripheral region (19) and electrically connected to the impurity region (70), an insulating inorganic film (110) that exposes the electrode (85) and covers the wiring (90), and an insulating organic film (120) having a portion that directly covers the electrode (85) and a portion that covers the wiring (90) with the inorganic film (110) sandwiched therebetween.
  • An electronic component (1) including a terminal electrode, wiring arranged around the terminal electrode, an insulating inorganic film covering the wiring at a distance from the terminal electrode, and an insulating organic film having a portion that directly covers the terminal electrode and a portion that covers the wiring with the inorganic film sandwiched therebetween.
  • An electronic component (1) including: an object to be covered (75); a gate electrode (95) arranged on the object to be covered (75) and having an electrode sidewall (97) on the object to be covered (75); a gate wiring (100) arranged around the gate electrode (95) on the object to be covered (75); an inner coating portion (112) that covers the gate electrode (95) so as to expose the electrode sidewall (97); an insulating inorganic film (110) having an outer coating portion (113) that covers the gate wiring (100) at a distance from the inner coating portion (112); and an insulating organic film (120) that spans the inner coating portion (112) and the outer coating portion (113) and covers the gate electrode (95) between the inner coating portion (112) and the outer coating portion (113).
  • An electronic component (1) including: an object to be coated (75); a source electrode (85) arranged on the object to be coated (75) and having an electrode sidewall (87) on the object to be coated (75); a gate wiring (100) arranged around the source electrode (85) on the object to be coated (75); an insulating inorganic film (110) having an inner coating portion (112) that covers the source electrode (85) so as to expose the electrode sidewall (87) and an outer coating portion (113) that covers the gate wiring (100) at a distance from the inner coating portion (112); and an insulating organic film (120) that spans the inner coating portion (112) and the outer coating portion (113) and covers the source electrode (85) between the inner coating portion (112) and the outer coating portion (113).
  • An electronic component (1) including: an object to be covered (75); a gate electrode (95) arranged on the object to be covered (75) and having an electrode sidewall (97) on the object to be covered (75); a source wiring (90) arranged around the gate electrode (95) on the object to be covered (75); an insulating inorganic film (110) having an inner coating portion (111) that covers the gate electrode (95) so as to expose the electrode sidewall (97), and an outer coating portion (113) that covers the source wiring (90) at a distance from the inner coating portion (111); and an insulating organic film (120) that spans the inner coating portion (111) and the outer coating portion (113) and covers the gate electrode (95) between the inner coating portion (111) and the outer coating portion (113).

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Publication number Priority date Publication date Assignee Title
WO2020213603A1 (ja) * 2019-04-19 2020-10-22 ローム株式会社 ＳｉＣ半導体装置
WO2021261102A1 (ja) * 2020-06-26 2021-12-30 ローム株式会社 電子部品
JP2023044581A (ja) * 2021-09-17 2023-03-30 株式会社東芝 半導体装置

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JP6846687B2 (ja) 2017-09-12 2021-03-24 パナソニックＩｐマネジメント株式会社 半導体装置およびその製造方法
JP7280938B1 (ja) 2021-12-21 2023-05-24 楽天グループ株式会社 情報処理装置、コンテンツ提供方法、及びプログラム

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2020213603A1 (ja) * 2019-04-19 2020-10-22 ローム株式会社 ＳｉＣ半導体装置
WO2021261102A1 (ja) * 2020-06-26 2021-12-30 ローム株式会社 電子部品
JP2023044581A (ja) * 2021-09-17 2023-03-30 株式会社東芝 半導体装置

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