WO2024247502A1 - 電源装置 - Google Patents

電源装置 Download PDF

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Publication number
WO2024247502A1
WO2024247502A1 PCT/JP2024/014538 JP2024014538W WO2024247502A1 WO 2024247502 A1 WO2024247502 A1 WO 2024247502A1 JP 2024014538 W JP2024014538 W JP 2024014538W WO 2024247502 A1 WO2024247502 A1 WO 2024247502A1
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WO
WIPO (PCT)
Prior art keywords
switching element
voltage
node
converter
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/014538
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English (en)
French (fr)
Japanese (ja)
Inventor
貴嗣 和智
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Rohm Co Ltd
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Rohm Co Ltd
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Filing date
Publication date
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Priority to JP2025523320A priority Critical patent/JPWO2024247502A1/ja
Publication of WO2024247502A1 publication Critical patent/WO2024247502A1/ja
Priority to US19/396,591 priority patent/US20260081528A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0095—Hybrid converter topologies, e.g. NPC mixed with flying capacitor, thyristor converter mixed with MMC or charge pump mixed with buck
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of AC power input into DC power output; Conversion of DC power input into AC power output
    • H02M7/42—Conversion of DC power input into AC power output without possibility of reversal
    • H02M7/44—Conversion of DC power input into AC power output without possibility of reversal by static converters
    • H02M7/48—Conversion of DC power input into AC power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/483—Converters with outputs that each can have more than two voltages levels
    • H02M7/4837—Flying capacitor converters

Definitions

  • This disclosure relates to a power supply device.
  • a type of power supply device that uses switching elements is the multiphase converter.
  • Multiphase converters can provide high output power and low output ripple.
  • the objective of this disclosure is to provide a good power supply device capable of performing multi-phase operation.
  • the power supply device is a power supply device configured to generate an output voltage lower than an input voltage from an input voltage, and includes a first converter, a second converter, and a control circuit
  • the first converter includes a first switching element provided between a reference node having a potential lower than the input voltage and a first node, a second switching element provided between the first node and a second node, a third switching element provided between the second node and a third node, a fourth switching element provided between the third node and a power supply node receiving the input voltage, a flying capacitor provided between the first node and the third node, an intermediate capacitor provided between the second node and the reference node, and a first inductor provided between the first node and an output node to which the output voltage is applied
  • the second converter includes a switching output stage connected to the second node, and a second inductor provided between the switching output stage and the output node
  • the control circuit generates the output voltage at the output node by controlling the states of the first switching element
  • This disclosure makes it possible to provide a good power supply device capable of performing multi-phase operation.
  • FIG. 1 is a configuration diagram of a power supply device according to a first embodiment of the present disclosure.
  • FIG. 2 is a diagram illustrating the operation of the hybrid buck converter in the power supply device according to the first embodiment of the present disclosure.
  • FIG. 3 is a diagram illustrating the operation of the power supply device according to the first embodiment of the present disclosure (state ST1).
  • FIG. 4 is a diagram illustrating the operation of the power supply device according to the first embodiment of the present disclosure (state ST2).
  • FIG. 5 is a diagram illustrating the operation of the power supply device according to the first embodiment of the present disclosure (state ST3).
  • FIG. 6 is a diagram illustrating the operation of the power supply device according to the first embodiment of the present disclosure (state ST4).
  • FIG. 1 is a configuration diagram of a power supply device according to a first embodiment of the present disclosure.
  • FIG. 2 is a diagram illustrating the operation of the hybrid buck converter in the power supply device according to the first embodiment of the present disclosure.
  • FIG. 3 is a
  • FIG. 7 is a diagram showing an internal configuration of a control circuit according to the first embodiment of the present disclosure.
  • FIG. 8 is a first example of a timing chart of the power supply device according to the first embodiment of the present disclosure.
  • FIG. 9 is a second example of a timing chart of the power supply device according to the first embodiment of the present disclosure.
  • FIG. 10 is a configuration diagram of a power supply device according to the second embodiment of the present disclosure.
  • FIG. 11 is a diagram showing the relationship between a control circuit and a plurality of converters according to the second embodiment of the present disclosure.
  • FIG. 12 is a relationship diagram of a plurality of clock signals in a power supply device according to the second embodiment of the present disclosure.
  • Ground refers to a reference conductive part having a reference potential of 0V (zero volts) or the reference potential of 0V itself.
  • 0V zero volts
  • ground When a certain component, electrode, or node is connected to ground, it means that the component, electrode, or node is connected to a reference node having a reference potential of 0V.
  • the reference node and ground can be read as interchangeable terms.
  • Level refers to the level of potential, and for any given signal or voltage, a high level has a higher potential than a low level.
  • a high level signal or voltage strictly means that the signal or voltage level is at a high level
  • a low level signal or voltage strictly means that the signal or voltage level is at a low level.
  • the switch from low level to high level is called a rising edge
  • the switch from high level to low level is called a falling edge.
  • Any switching element can be composed of a transistor.
  • a transistor configured as a FET (field effect transistor), including a MOSFET
  • the on state refers to a state in which the drain and source of the transistor are conductive
  • the off state refers to a state in which the drain and source of the transistor are non-conductive (cut-off state).
  • MOSFET is understood to be an enhancement-type MOSFET.
  • MOSFET is an abbreviation for "metal-oxide-semiconductor field-effect transistor.”
  • the backgate of any MOSFET can be considered to be shorted to the source.
  • the on and off states of any switching element may be simply expressed as on and off.
  • switching from the off state to the on state will be expressed as turning on
  • switching from the on state to the off state will be expressed as turning off.
  • the period during which the switching element is in the on state will be referred to as the on period
  • the period during which the switching element is in the off state will be referred to as the off period.
  • the period during which the signal is at a high level is called a high-level period
  • the period during which the signal is at a low level is called a low-level period.
  • connections between multiple parts that form a circuit can be understood to refer to electrical connections.
  • FIG. 1 shows the configuration of a power supply device 1A according to the first embodiment of the present disclosure.
  • converters 10 and 20 for two channels form a two-phase multi-phase converter.
  • the power supply device 1A receives a positive input voltage V IN from a voltage source (not shown) and generates a positive output voltage V OUT by stepping down the input voltage V IN .
  • the output voltage V OUT is lower than the input voltage V IN .
  • the power supply device 1A stabilizes the output voltage V OUT at a predetermined target voltage. That is, in a steady state, the output voltage V OUT substantially coincides with the target voltage.
  • the target voltage is referred to by the symbol "V TG ".
  • An intermediate voltage V MID is generated in the power supply device 1A.
  • the output voltage V OUT is lower than the intermediate voltage V MID .
  • the intermediate voltage V MID is substantially 1/2 of the input voltage V IN .
  • V IN > 2 x V OUT is established.
  • the values of the input voltage V IN and the output voltage V OUT are arbitrary.
  • the values of the input voltage V IN and the target voltage V TG are arbitrary.
  • the input voltage V IN is 48 V
  • the target voltage V TG i.e., the output voltage V OUT in the steady state
  • the steady state refers to a state in which the output voltage VOUT rises from 0 V following startup of the power supply device 1A, reaches the target voltage VTG , and then the output voltage VOUT is stabilized at the target voltage VTG .
  • the power supply device 1A includes a converter 10, a converter 20, and a control circuit 30.
  • the converter 10 functions as a reference converter
  • the converter 20 functions as an additional converter (a converter added to the reference converter).
  • the converters 10 and 20 each supply a current to an output node ND OUT , thereby generating an output voltage V OUT having a desired voltage value at the output node ND OUT .
  • the power supply device 1A includes switching elements M1 to M4, ML, and MH, capacitors C FLY , C MID , and C OUT , and inductors L1 and L2.
  • the capacitor C FLY may be referred to as a flying capacitor.
  • the capacitor C MID may be referred to as a middle capacitor.
  • the capacitor C OUT may be referred to as an output capacitor.
  • the converter 10 is a first channel converter.
  • the components of the converter 10 include switching elements M1 to M4, capacitors C FLY and C MID , and an inductor L1.
  • the converter 20 is a second channel converter.
  • the components of the converter 20 include switching elements MH and ML, and an inductor L2.
  • the capacitor C OUT is shared by both the converters 10 and 20. That is, the capacitor C OUT is a component of each of the converters 10 and 20, and is shared by the converters 10 and 20.
  • the converter 10 includes a buck converter and a stacked converter.
  • the buck converter in the converter 10 includes switching elements M1 and M2 and an inductor L1, and operates in cooperation with a capacitor COUT to step down an intermediate voltage V MID to generate an output voltage V OUT at an output node ND OUT .
  • the switching elements M1 and M2 function as a low-side switching element and a high-side switching element in the buck converter in the converter 10.
  • the stacked converter in the converter 10 includes switching elements M3 and M4 and a capacitor C FLY , and generates an intermediate voltage V MID from an input voltage V IN . It may be understood that the capacitor C MID is also included as a component of the stacked converter.
  • the converter 20 is a buck converter itself.
  • the converter 20 generates an output voltage V OUT at an output node ND OUT by stepping down an intermediate voltage V MID in cooperation with a capacitor C OUT .
  • the switching elements ML and MH function as a low-side switching element and a high-side switching element in the converter 20.
  • the switching elements M1 to M4, ML, and MH are each configured with an N-channel MOSFET.
  • the switching elements M1 to M4, ML, and MH may be referred to as transistors M1 to M4, ML, and MH.
  • the transistors M1 to M4 are connected in series between the ground and a node ND4.
  • the transistor M1 is provided between the ground and the node ND1
  • the transistor M2 is provided between the nodes ND1 and ND2
  • the transistor M3 is provided between the nodes ND2 and ND3
  • the transistor M4 is provided between the nodes ND3 and ND4. More specifically, the source of the transistor M1 is connected to the ground.
  • the drain of the transistor M1 and the source of the transistor M2 are connected to the node ND1.
  • the drain of the transistor M2 and the source of the transistor M3 are connected to the node ND2.
  • the drain of the transistor M3 and the source of the transistor M4 are connected to the node ND3.
  • the drain of the transistor M4 is connected to the node ND4.
  • the node ND4 is a power supply node that receives the input voltage V IN . That is, the input voltage V IN is supplied to the node ND4.
  • the signals supplied to the gates of the transistors M1 to M4 are called gate signals G1 to G4, respectively.
  • the capacitor CFLY is provided between the nodes ND3 and ND1, that is, a first end of the capacitor CFLY is connected to the node ND3, and a second end of the capacitor CFLY is connected to the node ND1.
  • the capacitor C MID is provided between the node ND2 and the ground. That is, a first end of the capacitor C MID is connected to the node ND2, and a second end of the capacitor C MID is connected to the ground. The first end of the capacitor C MID corresponds to the positive electrode of the capacitor C MID .
  • the voltage at the node ND2 is the intermediate voltage V MID . That is, a charge equivalent to the intermediate voltage V MID is stored in the capacitor C MID .
  • the inductor L1 is provided between the node ND1 and the output node ND OUT , that is, a first end of the inductor L1 is connected to the node ND1, and a second end of the inductor L1 is connected to the output node ND OUT .
  • the capacitor COUT is provided between the output node NDOUT and the ground. That is, a first end of the capacitor COUT is connected to the output node NDOUT , and a second end of the capacitor COUT is connected to the ground. The first end of the capacitor COUT corresponds to the positive electrode of the capacitor COUT .
  • the voltage at the output node NDOUT is the output voltage VOUT . That is, a charge equivalent to the output voltage VOUT is stored in the capacitor COUT .
  • the transistor MH is provided between the nodes ND2 and ND SW , and the transistor ML is provided between the node ND SW and ground. More specifically, the source of the transistor ML is connected to ground. The drain of the transistor ML and the source of the transistor MH are connected to the node ND SW (switch node). The drain of the transistor MH is connected to the node ND2.
  • the signals supplied to the gates of the transistors ML and MH are referred to as gate signals GL and GH, respectively.
  • the inductor L2 is provided between the node ND SW and the output node ND OUT . That is, a first end of the inductor L2 is connected to the node ND SW , and a second end of the inductor L2 is connected to the output node ND OUT .
  • the control circuit 30 is connected to the gates of the transistors M1 to M4, ML, and MH, and controls the states (on/off states) of the transistors M1 to M4, ML, and MH individually by supplying gate signals G1 to G4, GL, and GH to the transistors M1 to M4, ML, and MH.
  • a desired output voltage V OUT lower than the input voltage V IN is generated at the output node ND OUT .
  • the control circuit 30 may be formed of a semiconductor integrated circuit.
  • any of the gate signals G1 to G4, GL, and GH is referred to as the gate signal Gx.
  • the transistor Mx When the gate signal Gx has a high level, the transistor Mx is on, and when the gate signal Gx has a low level, the transistor Mx is off. Therefore, during the high level period of the gate signal G1, the transistor M1 is on, and during the low level period of the gate signal G1, the transistor M1 is off. Similarly, during the high level period of the gate signal G2, the transistor M2 is on, and during the low level period of the gate signal G2, the transistor M2 is off.
  • a high level gate signal Gx has a potential higher than the potential that is higher than the gate threshold voltage of the transistor Mx when viewed from the source potential of the transistor Mx.
  • a low level gate signal Gx may have a potential equivalent to the source potential of the transistor Mx.
  • the transistors M1 and M2 form a switching output stage 11 in the converter 10.
  • the transistors ML and MH form a switching output stage 21 in the converter 20.
  • the switching output stages 11 and 21 are each connected to a node ND2, and under the control of the control circuit 30, perform a step-down operation of the intermediate voltage VMID .
  • the control circuit 30 performs switching control on the switching output stage 11 to alternately switch on and off the transistors M1 and M2, thereby causing the converter 10 to perform a step-down operation of the intermediate voltage V MID .
  • the control circuit 30 performs switching control on the switching output stage 21 to alternately switch on and off the transistors ML and MH, thereby causing the converter 20 to perform a step-down operation of the intermediate voltage V MID .
  • an output voltage V OUT is generated at the output node ND OUT due to the step-down operation of the intermediate voltage V MID by the converter 10 and the step-down operation of the intermediate voltage V MID by the converter 20.
  • the output node ND OUT is connected to a load (not shown).
  • the load is any load that is driven based on the output voltage V OUT .
  • the current supplied from the output node ND OUT to the load is called the load current I LD .
  • the load current I LD corresponds to the output current of the power supply device 1A.
  • the current flowing through the inductor L1 is called the inductor current I L1
  • the current flowing through the inductor L2 is called the inductor current I L2 .
  • the power supply device 1A is operating in a continuous current mode. In the continuous current mode, a current always flows from the first end to the second end of each of the inductors L1 and L2, that is, a current always flows through the inductors L1 and L2 in the direction in which the capacitor C OUT is charged.
  • a current flowing in a direction that increases the potential of the first end of the capacitor C FLY (i.e., the potential of the node ND3) based on the potential of the second end of the capacitor C FLY (i.e., the potential of the node ND1) is the charging current of the capacitor C FLY
  • a current flowing in the opposite direction is the discharging current of the capacitor C FLY
  • a current flowing in a direction that increases the intermediate voltage V MID is the charging current
  • a current flowing in a direction that decreases the intermediate voltage V MID is the discharging current.
  • the control circuit 30 alternates between states STa and STb for the states of transistors M1 to M4.
  • state STa transistors M1 and M3 are off and transistors M2 and M4 are on.
  • state STb transistors M1 and M3 are on and transistors M2 and M4 are off.
  • currents 811 and 813 are generated.
  • the current 811 flows from the capacitor C_MID through the transistor M2 and the inductor L1 to the output node ND_OUT , and is generated by discharging the capacitor C_MID .
  • the current 813 flows from the node ND4, which is the application terminal of the input voltage VIN , to the capacitor C_FLY through the transistor M4, and the capacitor C_FLY is charged by the current 813.
  • currents 812 and 814 are generated.
  • the current 812 flows from the ground to the output node ND OUT through the transistor M1 and the inductor L1.
  • the current 814 flows from the capacitor C FLY to the positive electrode of the capacitor C MID through the transistor M3.
  • the current 814 is generated by discharging the capacitor C FLY and contributes to charging the capacitor C MID .
  • state STa since the transistors M2 and M4 are on, state STa is equivalent to a state in which the capacitors C FLY and C MID are connected in series for the capacitors C FLY and C MID .
  • state STb the capacitors C FLY and C MID are connected in parallel through the switching elements M1 and M3.
  • a switched capacitor circuit is formed by the transistors M1 to M4 and the capacitors C FLY and C MID . Therefore, in the steady state, the intermediate voltage V MID , which is the voltage of the positive electrode of the capacitor C MID , is approximately the voltage (V IN /2).
  • the converter 10 generates the intermediate voltage V MID , which is equivalent to a divided voltage of the input voltage V IN .
  • a synchronous buck converter that steps down the intermediate voltage V MID is formed by the transistors M1 and M2 and the inductor L1. Therefore, the converter 10 can be called a hybrid buck converter that combines a switched capacitor circuit and a synchronous buck converter.
  • High efficiency can be achieved by using a switched capacitor circuit to reduce the input voltage V IN by half and then further stepping down the resulting intermediate voltage V MID using a synchronous buck converter.
  • an output voltage VOUT of 12V is generated from an input voltage V IN of 48V.
  • a square wave voltage (a square wave voltage that fluctuates between approximately 0V and 48V) is generated by switching the input voltage V IN of 48V, and the square wave voltage is rectified and smoothed to obtain an output voltage of 12V.
  • a square wave voltage (a square wave voltage that fluctuates between approximately 0V and 24V) is generated by switching a voltage (V IN /2), and the square wave voltage is rectified and smoothed to obtain an output voltage of 12V. Therefore, the power supply device 1A can suppress switching loss to a lower level than the power supply device according to the reference method.
  • the switching duty is relatively small.
  • the impact of losses during periods when the instantaneous value of the square wave voltage rises and falls is relatively large.
  • the input voltage to the synchronous buck converter is voltage (V IN /2), so the switching duty is relatively large compared to the reference method, leading to an improvement in switching loss.
  • the input voltage to the synchronous buck converter is voltage (V IN /2), so that the loss associated with charging and discharging the parasitic capacitances can be kept relatively low compared to the reference method.
  • a synchronous buck converter (20) that performs step-down operation of the intermediate voltage V MID is provided in addition to the synchronous buck converter in the hybrid buck converter (10), and these are operated in multiphase to achieve high output power and low output ripple.
  • the reference method of operating multiple hybrid buck converters in multiphase can also achieve increased output power and low output ripple, the reference method increases the number of parts by the number of hybrid buck converters.
  • the power supply device 1A also achieves the effect of reducing the number of parts compared to the reference method.
  • the states of transistors M1 to M4 are switched between states STa and STb, while the states of transistors ML and MH are switched between a state in which transistor ML is on and transistor MH is off, and a state in which transistor ML is off and transistor MH is on. Therefore, the states of transistors M1 to M4, ML, and MH are in one of states ST1 to ST4 shown in Figures 3 to 6.
  • the control circuit 30 can set the states of transistors M1 to M4, ML, and MH to one of states ST1 to ST4.
  • state ST1 the transistors M1, M3, and ML are in the off state, and the transistors M2, M4, and MH are in the on state.
  • state ST1 the state of the transistors M1 to M4 is state STa (see Fig. 2). Therefore, in state ST1, the above-mentioned currents 811 and 813 are generated in the converter 10.
  • a current 821 is generated in the converter 20. The current 821 is a current flowing from the capacitor C_MID through the transistor MH and the inductor L2 toward the output node ND_OUT , and is generated by discharging the capacitor C_MID .
  • the transistors M1, M3 and MH are in the off state, and the transistors M2, M4 and ML are in the on state.
  • the state of the transistors M1 to M4 is state STa (see Fig. 2). Therefore, in state ST2, the above-mentioned currents 811 and 813 are generated in the converter 10.
  • a current 822 is generated in the converter 20. The current 822 flows from the ground to the output node ND OUT through the transistor ML and the inductor L2.
  • transistors M2, M4, and ML are in the off state, and transistors M1, M3, and MH are in the on state.
  • the state of transistors M1 to M4 is state STb (see FIG. 2). Therefore, in state ST3, the above currents 812 and 814 are generated in converter 10. On the other hand, in state ST3, the above current 821 is generated in converter 20.
  • transistors M2, M4, and MH are in the off state, and transistors M1, M3, and ML are in the on state.
  • the state of transistors M1 to M4 is state STb (see FIG. 2). Therefore, in state ST4, the above currents 812 and 814 are generated in converter 10. On the other hand, in state ST4, the above current 822 is generated in converter 20.
  • FIG. 7 shows the internal configuration of the control circuit 30.
  • FIG. 8 and FIG. 9 show timing charts relating to the first and second operation examples of the control circuit 30.
  • the waveforms of signals CLK1, CMPOUT1, CLK2, CMPOUT2, G1 to G4, GH, and GL are shown from top to bottom.
  • the control circuit 30 includes an error amplifier 31, ramp circuits 32_1 and 32_2, current information acquisition circuits 33_1 and 33_2, adders 34_1 and 34_2, PWM comparators 35_1 and 35_2, and controllers 36_1 and 36_2.
  • the power supply device 1A includes resistors R1 and R2. The first end of the resistor R1 is connected to the output node ND OUT , the second end of the resistor R1 is connected to the first end of the resistor R2, and the second end of the resistor R2 is connected to the ground. A feedback voltage V FB corresponding to the output voltage V OUT is generated at the connection node between the resistors R1 and R2.
  • the feedback voltage V FB is a divided voltage of the output voltage V OUT , and is therefore proportional to the output voltage V OUT .
  • the resistors R1 and R2 form a feedback voltage generation circuit that generates the feedback voltage V FB .
  • the feedback voltage V FB is supplied to the control circuit 30.
  • the feedback voltage generating circuit may be understood as being included in the components of the control circuit 30.
  • the output voltage VOUT itself may be used as the feedback voltage VFB .
  • the feedback voltage VFB is information on the output voltage VOUT (more specifically, information indicating the value of the output voltage VOUT ).
  • the error amplifier 31 is a current output type transconductance amplifier.
  • the error amplifier 31 has an inverting input terminal, a non-inverting input terminal, and an output terminal.
  • a feedback voltage VFB is supplied to the inverting input terminal of the error amplifier 31.
  • a predetermined reference voltage VREF is supplied to the non-inverting input terminal of the error amplifier 31.
  • the reference voltage VREF is a DC voltage having a predetermined positive voltage value, and is generated by a reference voltage generating circuit (not shown) in the control circuit 30.
  • the output terminal of the error amplifier 31 is connected to a wiring WR_ERR . Note that, when starting up the power supply device 1A, soft start control may be performed to gradually increase the value of the reference voltage VREF from 0V to a predetermined positive voltage value, but the existence of the soft start control will be ignored below.
  • the error amplifier 31 generates an error voltage V ERR corresponding to the difference between the feedback voltage V FB and the reference voltage V REF on the wiring WR ERR by outputting a current signal corresponding to the difference between the feedback voltage V FB and the reference voltage V REF from its output terminal. Specifically, when the feedback voltage V FB is lower than the reference voltage V REF , the error amplifier 31 outputs a current from its output terminal to the wiring WR ERR so that the error voltage V ERR increases, and when the feedback voltage V FB is higher than the reference voltage V REF , the error amplifier 31 draws a current from the wiring WR ERR to its output terminal so that the error voltage V ERR decreases.
  • a phase compensation circuit including a capacitor may be connected between the wiring WR ERR and ground.
  • the ramp circuit 32_1 generates a ramp voltage V RAMP1 that monotonically rises at a predetermined rate from a predetermined initial voltage V INT during an on-period of the transistor M2.
  • the initial voltage V INT is, for example, 0 V, but may be different from 0 V.
  • the ramp voltage V RAMP1 is fixed at the initial voltage V INT .
  • the current information acquisition circuit 33_1 acquires current information of the inductor L1, and generates a sense voltage VIL1 indicating the current information of the inductor L1.
  • the current information of the inductor L1 is information indicating the value of the inductor current IL1 .
  • the sense voltage VIL1 has a voltage value proportional to the value of the inductor current IL1 with a positive proportionality coefficient. Therefore, the sense voltage VIL1 increases as the inductor current IL1 increases, and the sense voltage VIL1 decreases as the inductor current IL1 decreases.
  • VIL1 kIV x IL1 ", where kIV is a predetermined positive coefficient.
  • the sense voltage VIL1 may be generated in any manner.
  • the sense voltage VIL1 may be generated by directly detecting the inductor current IL1 with a current sensor.
  • the current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L1 and the node ND1.
  • the sense voltage VIL1 may be generated by detecting the current (hence the inductor current IL1 ) flowing through the transistor M2 during the on-period of the transistor M2, or by detecting the current (hence the inductor current IL1 ) flowing through the transistor M1 during the on-period of the transistor M1 .
  • the sense voltage VIL1 may be generated by detecting the voltage at any point where a voltage corresponding to the inductor current IL1 is generated.
  • the PWM comparator 35_1 compares the error voltage V ERR and the slope voltage V SLP1 , and generates and outputs a signal CMPOUT1 indicating the comparison result.
  • the error voltage V ERR is input to the inverting input terminal of the PWM comparator 35_1
  • the slope voltage V SLP1 is input to the non-inverting input terminal of the PWM comparator 35_1.
  • the PWM comparator 35_1 outputs a low-level signal CMPOUT1 when "V SLP1 ⁇ V ERR " is satisfied, and outputs a high-level signal CMPOUT1 when "V SLP1 >V ERR " is satisfied.
  • a signal CMPOUT1 and a reference clock signal CLK1 are input to the controller 36_1.
  • the reference clock signal CLK1 is generated by an internal clock generating circuit (not shown) provided in the control circuit 30.
  • the reference clock signal CLK1 is a rectangular wave signal having a predetermined frequency f PWM , and alternates between high and low signal levels.
  • the duty of the reference clock signal CLK1 is arbitrary.
  • the reference clock signal CLK1 has a low level in principle, and has a high level for a very short time at intervals of the reciprocal of the frequency f PWM (see FIGS. 8 and 9).
  • the controller 36_1 When a predetermined level change occurs in the reference clock signal CLK1, the controller 36_1 turns on the transistors M2 and M4 by generating a rising edge in the gate signals G2 and G4 (i.e., by switching the levels of the gate signals G2 and G4 from low to high), and turns off the transistors M1 and M3 by generating a falling edge in the gate signals G1 and G3 (i.e., by switching the levels of the gate signals G1 and G3 from high to low).
  • the predetermined level change (first predetermined level change) in the reference clock signal CLK1 here is a change in the reference clock signal CLK1 from low to high, but it may also be a change in the reference clock signal CLK1 from high to low.
  • the slope voltage V SLP1 rises monotonically and transitions from a state where "V SLP1 ⁇ V ERR " is satisfied to a state where "V SLP1 >V ERR " is satisfied, causing a rising edge in the signal CMPOUT1.
  • the controller 36_1 turns off the transistors M2 and M4 by causing a falling edge in the gate signals G2 and G4, and turns on the transistors M1 and M3 by causing a rising edge in the gate signals G1 and G3.
  • the ramp voltage V RAMP1 drops to the sufficiently low initial voltage V INT , returning to a state where "V SLP1 ⁇ V ERR " is satisfied, and a falling edge occurs quickly in the signal CMPOUT1.
  • the time from when the transistors M2 and M4 are turned on and the transistors M1 and M3 are turned off to when the transistors M2 and M4 are turned off and the transistors M1 and M3 are turned on is referred to as time t ON1 .
  • the ramp circuit 32_2 generates a ramp voltage VRAMP2 that monotonically rises at a predetermined rate of change from a predetermined initial voltage VINT during the on-period of the transistor MH.
  • the initial voltage VINT is, for example, 0V, but may be different from 0V.
  • the ramp voltage VRAMP2 is fixed at the initial voltage VINT .
  • the ramp circuit 32_2 has the same configuration as the ramp circuit 32_1. Therefore, the rate of change of the ramp voltage VRAMP2 during the on-period of the transistor MH is equal to the rate of change of the ramp voltage VRAMP1 during the on-period of the transistor M2.
  • the current information acquisition circuit 33_2 acquires current information of the inductor L2 and generates a sense voltage VIL2 indicating the current information of the inductor L2.
  • the current information of the inductor L2 is information indicating the value of the inductor current IL2 .
  • the sense voltage VIL2 has a voltage value proportional to the value of the inductor current IL2 with a positive proportionality coefficient. Therefore, the sense voltage VIL2 increases as the inductor current IL2 increases, and the sense voltage VIL2 decreases as the inductor current IL2 decreases.
  • VIL2 kIV x IL2
  • the method of generating the sense voltage VIL2 is arbitrary.
  • the sense voltage VIL2 may be generated by directly detecting the inductor current IL2 with a current sensor.
  • the current sensor here may be a shunt resistor (not shown) inserted in series between the inductor L2 and the node NDSW .
  • the sense voltage VIL2 may be generated by detecting the current (hence the inductor current IL2 ) flowing through the transistor MH during the on-period of the transistor MH, or by detecting the current (hence the inductor current IL2 ) flowing through the transistor ML during the on-period of the transistor ML.
  • the sense voltage VIL2 may be generated by detecting the voltage at any point where a voltage corresponding to the inductor current IL2 is generated.
  • the PWM comparator 35_2 compares the error voltage V ERR and the slope voltage V SLP2 , and generates and outputs a signal CMPOUT2 indicating the comparison result.
  • the error voltage V ERR is input to the inverting input terminal of the PWM comparator 35_2, and the slope voltage V SLP2 is input to the non-inverting input terminal of the PWM comparator 35_2.
  • the PWM comparator 35_2 outputs a low-level signal CMPOUT2 when "V SLP2 ⁇ V ERR " is satisfied, and outputs a high-level signal CMPOUT2 when "V SLP2 >V ERR " is satisfied.
  • a signal CMPOUT2 and a shift clock signal CLK2 are input to the controller 36_2.
  • the shift clock signal CLK2 is a signal obtained by shifting the phase of the reference clock CLK1. Therefore, the reference clock signal CLK1 and the shift clock signal CLK2 have the same frequency f PWM and different phases.
  • the shift clock signal CLK2 has a low level in principle and has a high level for a short time at an interval of the reciprocal of the frequency f PWM (see FIG. 8 and FIG. 9).
  • the shift clock signal CLK2 may be generated in the control circuit 30 based on the reference clock CLK1.
  • the shift clock signal CLK2 is assumed to be a signal whose phase is delayed by 180° from the reference clock signal CLK1.
  • the phase difference between the clock signals CLK1 and CLK2 is 180°.
  • Setting the delay amount to 180° is optimal for minimizing the ripple of the output voltage V OUT .
  • the amount of delay in phase of the shift clock signal CLK2 with respect to the phase of the reference clock signal CLK1 may be other than 180° (for example, it may be 170° or 190°).
  • the controller 36_2 When a predetermined level change occurs in the shift clock signal CLK2, the controller 36_2 generates a rising edge in the gate signal GH to turn on the transistor MH and generates a falling edge in the gate signal GL to turn off the transistor ML.
  • the predetermined level change (second predetermined level change) in the shift clock signal CLK2 is a change from a low level to a high level in the shift clock signal CLK2, but it may also be a change from a high level to a low level in the shift clock signal CLK2.
  • the slope voltage V SLP2 rises monotonically and transitions from a state where "V SLP2 ⁇ V ERR " is satisfied to a state where "V SLP2 >V ERR " is satisfied, causing a rising edge in the signal CMPOUT2.
  • the controller 36_2 When the rising edge occurs in the signal CMPOUT2, the controller 36_2 generates a falling edge in the gate signal GH to turn off the transistor MH, and generates a rising edge in the gate signal GL to turn on the transistor ML.
  • the ramp voltage V RAMP2 drops to the sufficiently low initial voltage V INT , returning to a state where "V SLP2 ⁇ V ERR " is satisfied, and a falling edge occurs quickly in the signal CMPOUT2.
  • the time from when the transistor MH is turned on and the transistor ML is turned off to when the transistor MH is turned off and the transistor ML is turned on is referred to as time t ON2 .
  • controllers 36_1 and 36_2 causes the states of transistors M1 to M4, ML, and MH to switch among states ST1 to ST4, as shown in Figures 8 and 9.
  • the on-duty of the transistor M2 and the on-duty of the transistor MH are both smaller than 50%.
  • the on-duty of the transistor M2 and the on-duty of the transistor MH are both larger than 50%.
  • the on-duty of the transistor M2 indicates the ratio of the on-period of the transistor M2 to the sum of the on-period of the transistor M2 and the off-period of the transistor M2.
  • the on-duty of the transistor MH indicates the ratio of the on-period of the transistor MH to the sum of the on-period of the transistor MH and the off-period of the transistor MH.
  • the operation of Fig. 8 or the operation of Fig. 9 appears depending on various operating conditions related to the output voltage V OUT (the above on-duty, times t ON1 and t ON2 ).
  • state ST4 immediately before the rising edge of reference clock signal CLK1 is state ST4.
  • state ST4 immediately before the rising edge of reference clock signal CLK1 is considered to be the initial state.
  • the states of transistors M1 to M4, ML and MH are switched from state ST4, which is the initial state, to state ST2, triggered by the rising edge of reference clock signal CLK1, then switched from state ST2 to state ST4, triggered by the rising edge of signal CMPOUT1, further switched from state ST4 to state ST3, triggered by the rising edge of shift clock signal CLK2, and further switched from state ST3 back to state ST4, which is the initial state, triggered by the rising edge of signal CMPOUT2. Thereafter, the same operation is repeated.
  • the state immediately before the rising edge of the reference clock signal CLK1 is state ST3.
  • state ST3 immediately before the rising edge of the reference clock signal CLK1 is considered to be the initial state.
  • the states of transistors M1-M4, ML, and MH are switched from state ST3, which is the initial state, to state ST1 at the rising edge of the reference clock signal CLK1, then from state ST1 to state ST2 at the rising edge of the signal CMPOUT2, and then from state ST2 to state ST1 at the rising edge of the shift clock signal CLK2, and then from state ST1 back to state ST3, which is the initial state, at the rising edge of the signal CMPOUT1. Thereafter, the same operation is repeated.
  • the above-mentioned time t ON1 depends on the error voltage V ERR (and therefore on the information of the output voltage V OUT ) and on the sense voltage V IL1 (and therefore on the current information of the inductor L1). That is, the controller 36_1 controls the switching of the transistors M1 to M4 in synchronization with the reference clock signal CLK1 based on the information of the output voltage V OUT and the current information of the inductor L1.
  • the controller 36_1 After the controller 36_1 turns on the transistors M2 and M4 and turns off the transistors M1 and M3 in response to a predetermined level change in the reference clock signal CLK1, when the time t ON1 according to the information of the output voltage V OUT and the current information of the inductor L1 has elapsed, the controller 36_1 turns off the transistors M2 and M4 and turns on the transistors M1 and M3.
  • the above-mentioned time t ON2 depends on the error voltage V ERR (and therefore on the information of the output voltage V OUT ) and on the sense voltage V IL2 (and therefore on the current information of the inductor L2). That is, the controller 36_2 controls the switching of the transistors ML and MH in synchronization with the shift clock signal CLK2 based on the information of the output voltage V OUT and the current information of the inductor L2.
  • the controller 36_2 After turning on the transistor MH and turning off the transistor ML in response to a predetermined level change in the shift clock signal CLK2, the controller 36_2 turns off the transistor MH and turns on the transistor ML after the time t ON2 according to the information of the output voltage V OUT and the current information of the inductor L2 has elapsed.
  • the pair of the switching output stage 11 and the inductor L1 in the converter 10 and the pair of the switching output stage 21 and the inductor L2 in the converter 20 have the same configuration.
  • the switching output stages 11 and 21 perform a step-down operation of a common intermediate voltage V MID .
  • the switching control of the transistors M1 and M2 based on the current information of the inductor L1 is equivalent to the switching control of the transistors ML and MH based on the current information of the inductor L2. Therefore, a multi-phase operation is realized in a state where the output current of the converter 10 and the output current of the converter 20 are balanced.
  • the inductor current IL1 corresponds to the output current of the converter 10
  • the inductor current IL2 corresponds to the output current of the converter 20.
  • the instantaneous values of the inductor currents IL1 and IL2 differ from each other at each timing, the average of the inductor current IL1 and the average of the inductor current IL2 are substantially equal.
  • the output current of the converter 10 and the output current of the converter 20 are each a pulsating current, and the two output currents have different phases from each other.
  • the power supply device 1A is a two-phase multiphase converter (a multiphase DC/DC converter).
  • the circuit configuration in Fig. 7 is an example, and as long as the above-mentioned balance regarding currents is achieved, the configuration of the control circuit 30 can be modified in various ways. For example, a modification may be applied in which the adders 34_1 and 34_2 are deleted from the control circuit 30 in Fig. 7, and instead, current information of the inductors L1 and L2 is fed back to the error amplifier 31 side.
  • V SLP1 V RAMP1
  • V SLP2 V RAMP2
  • a voltage (V ERR - V IL1 ) is input to the inverting input terminal of the PWM comparator 35_1
  • a voltage (V ERR - V IL2 ) is input to the inverting input terminal of the PWM comparator 35_2.
  • FIG. 10 shows the configuration of a power supply device 1B according to a second embodiment of the present disclosure.
  • Power supply device 1B has a converter 10 for one channel and a converter 20 for n channels, which together form a multi-phase converter with (n+1) phases.
  • n will hereinafter represent any integer equal to or greater than 2.
  • the power supply device 1B in FIG. 10 is obtained by modifying the power supply device 1A in FIG. 1 by adding (n-1) converters 20.
  • the power supply device 1B includes a converter 10, n converters 20, and a control circuit 30.
  • the control circuit 30 of the power supply device 1B controls the states of the transistors ML and MH of each converter 20 in addition to controlling the states of the transistors M1 to M4.
  • the converter 10 and the n converters 20 each supply a current to the output node ND OUT , thereby generating an output voltage V OUT having a desired voltage value at the output node ND OUT .
  • the configuration and operation of the converter 10 are as shown in the first embodiment. Therefore, the converter 10 includes transistors M1 to M4, capacitors C FLY and C MID , and an inductor L1.
  • the converter 10 generates an intermediate voltage V MID from an input voltage V IN , and works together with the capacitor C OUT to step down the intermediate voltage V MID , thereby generating an output voltage V OUT at an output node ND OUT .
  • each converter 20 includes transistors ML and MH and an inductor L2. Each converter 20 works in conjunction with a capacitor C OUT to step down an intermediate voltage V MID , thereby generating an output voltage V OUT at an output node ND OUT .
  • converters 20[1] to 20[n] are referred to as converters 20[1] to 20[n].
  • Converter 10 can be considered to be the first channel converter, and in this case, converters 20[1] to 20[n] are the second to (n+1)th channel converters.
  • Capacitor COUT is shared by converters 10 and 20[1] to 20[n]. That is, capacitor COUT is a component of each of converters 10 and 20[1] to 20[n], and is shared by converters 10 and 20[1] to 20[n].
  • the drains of all the transistors MH in the converters 20[1] to 20[n] are commonly connected to a node ND2 and are supplied with an intermediate voltage V MID .
  • the source of the transistor MH and the drain of the transistor ML are connected to a node ND SW , and the source of the transistor ML is connected to ground.
  • the first end of the inductor L2 is connected to the node ND SW .
  • the second ends of all the inductors L2 in the converters 20[1] to 20[n] are commonly connected to an output node ND OUT .
  • the control circuit 30 is connected to the gates of the transistors M1 to M4, and is also connected to the gates of the transistors ML and MH in each of the converters 20[1] to 20[n].
  • the control circuit 30 controls the states (on/off states) of the transistors M1 to M4 individually by supplying gate signals G1 to G4 to the transistors M1 to M4.
  • the control circuit 30 controls the states (on/off states) of the transistors ML and MH individually by supplying gate signals GL and GH to the gates of the transistors ML and MH in each of the converters 20[1] to 20[n].
  • the control circuit 30 includes the components shown in FIG. 7. That is, the control circuit 30 in the power supply unit 1B includes an error amplifier 31, ramp circuits 32_1 and 32_2, current information acquisition circuits 33_1 and 33_2, adders 34_1 and 34_2, PWM comparators 35_1 and 35_2, and controllers 36_1 and 36_2. However, the control circuit 30 in the power supply unit 1A includes a control block consisting of the ramp circuit 32_2, current information acquisition circuit 33_2, adder 34_2, PWM comparator 35_2, and controller 36_2 for one channel, whereas the control circuit 30 in the power supply unit 1B includes the above control block for n channels.
  • control blocks BLK[1] to BLK[n] are referred to as control blocks BLK[1] to BLK[n].
  • the operation of each of the control blocks BLK[1] to BLK[n] is similar to that of the control blocks in the first embodiment.
  • the control blocks BLK[1] to BLK[n] execute switching control for the switching output stage 21 of the converters 20[1] to 20[n].
  • the control block BLK[i] executes switching control for the switching output stage 21 of the converter 20[i]. That is, the control block BLK[i] supplies gate signals GH and GL to the transistors MH and ML of the converter 20[i]. i represents any natural number.
  • the switching control for the switching output stage 21 of the converter 20[i] is similar to the switching control for the switching output stage 21 in the first embodiment.
  • Each shift clock signal CLK2 in the control blocks BLK[1] to BLK[n] is a signal obtained by shifting the phase of the reference clock CLK1. Therefore, the reference clock signal CLK1 and all the shift clock signals CLK2 have the same frequency f PWM , and the reference clock signal CLK1 and each shift clock signal CLK2 have different phases.
  • the control circuit 30 makes the phase of the shift clock signal CLK2 in the control block BLK[1], the phase of the shift clock signal CLK2 in the control block BLK[2], ..., the phase of the shift clock signal CLK2 in the control block BLK[n] different from each other.
  • the shift clock signal CLK2 in the control block BLK[i] will be referred to specifically with the symbol "CLK2[i]". Then, as shown in FIG. 12, the control circuit 30 makes the phase of the reference clock signal CLK1 and the phases of the (n+1) clock signals consisting of the shift clock signals CLK2[1] to CLK2[n] different from each other.
  • the shift clock signal CLK2[1] is a signal obtained by delaying the phase of the reference clock signal CLK1 by a predetermined amount ⁇ .
  • the shift clock signal CLK2[i+1] is a signal obtained by delaying the phase of the shift clock signal CLK2[i] by a predetermined amount ⁇ .
  • the amount of phase delay of the shift clock signal CLK2[n] from the perspective of the reference clock signal CLK1 is less than 360°.
  • the predetermined amount ⁇ is 90°.
  • the power supply device 1A or 1B can be applied to any device or system that requires a stable DC voltage.
  • the power supply device 1A or 1B may be applied to a power supply system for a data center.
  • the output voltage V OUT in the power supply device 1A or 1B may be 48V, and the power supply device 1A or 1B supplies the output voltage V OUT to a 48V power bus.
  • reducing power consumption in data centers has become an important issue, and a transition from a 12V power bus to a 48V power bus is progressing.
  • the power supply device 1A or 1B may be applied to a primary power supply in a vehicle such as an automobile.
  • the power supply device 1A or 1B may directly receive an input voltage V IN from a battery mounted on the vehicle to generate an output voltage V OUT , and the output voltage V OUT may function as a driving voltage for any system (e.g., an autonomous driving system of level 3 or higher) mounted on the vehicle.
  • the power supply device 1A or 1B may be applied to a power supply for a charging system.
  • the charging system may charge a battery of an electric vehicle.
  • the power supply device 1A or 1B may be applied to a power supply for a base station.
  • the channel types of the FETs (field effect transistors) shown in each embodiment are examples.
  • the channel type of any FET can be changed between P-channel type and N-channel type without compromising the above-mentioned gist. Therefore, for example, transistors M1 to M4, ML, and MH may be formed of P-channel type MOSFETs, or N-channel type MOSFETs and P-channel type MOSFETs may be mixed among transistors M1 to M4, ML, and MH.
  • any of the transistors described above may be any type of transistor, provided that no disadvantage arises.
  • any of the transistors described above as MOSFETs may be replaced with junction FETs, IGBTs (Insulated Gate Bipolar Transistors), or bipolar transistors, provided that no disadvantage arises.
  • Any of the transistors has a first electrode, a second electrode, and a control electrode.
  • a FET one of the first and second electrodes is the drain, the other is the source, and the control electrode is the gate.
  • IGBT In an IGBT, one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the gate.
  • a bipolar transistor that does not belong to an IGBT one of the first and second electrodes is the collector, the other is the emitter, and the control electrode is the base.
  • a power supply device is a power supply device (1A, 1B) configured to generate an output voltage (V OUT ) lower than an input voltage (V IN ) from an input voltage (V IN ), the power supply device comprising a first converter (10), a second converter (20) and a control circuit (30), the first converter including a first switching element (M1) provided between a reference node having a potential lower than the input voltage and a first node, a second switching element (M2) provided between the first node and a second node, a third switching element (M3) provided between the second node and a third node, a fourth switching element (M4) provided between the third node and a power supply node receiving the input voltage, a flying capacitor (C FLY ) provided between the first node and the third node, and an intermediate capacitor (C MID ) provided between the second node and the reference node.
  • M1 first switching element
  • M2 second switching element
  • M3 provided between the first node and a second node
  • M3 provided
  • the second converter has a switching output stage (21) connected to the second node, and a second inductor (L2) provided between the switching output stage and the output node, and the control circuit generates the output voltage at the output node by controlling the states of the first switching element to the fourth switching element and the switching output stage (first configuration).
  • the control circuit may be configured (second configuration) to generate an intermediate voltage (V MID ) equivalent to a division of the input voltage at the second node by controlling the states of the first switching element to the fourth switching element, cause the first converter to perform a step-down operation of the intermediate voltage through switching control of the first switching element and the second switching element, and cause the second converter to perform a step-down operation of the intermediate voltage by performing switching control of the switching output stage in a phase different from the switching control of the first switching element and the second switching element, and generate the output voltage at the output node by the step-down operation of the first converter and the step-down operation of the second converter.
  • V MID intermediate voltage
  • the switching output stage may have a high-side switching element (MH) provided between the second node and a switch node, and a low-side switching element (ML) provided between the switch node and the reference node, the second inductor is provided between the switch node and the output node, and the control circuit may be configured to cause the second converter to step down the intermediate voltage by controlling the switching of the high-side switching element and the low-side switching element in a phase different from that of the switching control of the first switching element and the second switching element (third configuration).
  • MH high-side switching element
  • ML low-side switching element
  • the control circuit may have a first controller (36_1 ) configured to alternately turn on or off the set of the first switching element and the third switching element and the set of the second switching element and the fourth switching element in synchronization with a reference clock signal (CLK1) based on the output voltage information (V FB ) and the first inductor current information (V IL1 ), and a second controller (36_2) configured to alternately control the high-side switching element and the low-side switching element in synchronization with a shift clock signal (CLK2) based on the output voltage information and the second inductor current information (V IL2 ), and the shift clock signal may be a signal obtained by shifting the phase of the reference clock signal (fourth configuration).
  • the first controller may be configured to turn on the second switching element and the fourth switching element and turn off the first switching element and the third switching element in response to a predetermined level change in the reference clock signal, and then turn off the second switching element and the fourth switching element and turn on the first switching element and the third switching element after a time (t ON1 ) corresponding to the output voltage information and the current information of the first inductor has elapsed
  • the second controller may be configured to turn on the high-side switching element and turn off the low-side switching element in response to a predetermined level change in the shift clock signal, and then turn off the high-side switching element and turn on the low-side switching element after a time (t ON2 ) corresponding to the output voltage information and the current information of the second inductor has elapsed (fifth configuration).
  • a sixth configuration may be adopted in which an output capacitor (C OUT ) is provided between the output node and the reference node.
  • the power supply device may have a configuration (seventh configuration) that includes multiple second converters.
  • the control circuit may perform switching control of the switching output stage of each second converter in a phase different from the switching control of the first switching element and the second switching element, and for each combination of two second converters included in the plurality of second converters, the control circuit may perform switching control of the switching output stage of one second converter and switching control of the switching output stage of the other second converter in mutually different phases (eighth configuration).
  • a power supply device includes a first converter (10) configured to generate an intermediate voltage (V MID ) which is a divided voltage of an input voltage (V IN ) and to perform a step-down operation of the intermediate voltage, a second converter (20) configured to perform a step-down operation of the intermediate voltage separately from the first converter, and a control circuit (30), and generates an output voltage (V OUT ) lower than the intermediate voltage based on the step-down operation of the first converter and the step-down operation of the second converter, and the control circuit is configured (ninth configuration) to cause the step-down operation of the first converter and the step-down operation of the second converter to be performed in different phases from each other.

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PCT/JP2024/014538 2023-05-31 2024-04-10 電源装置 Ceased WO2024247502A1 (ja)

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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010110106A (ja) * 2008-10-30 2010-05-13 Rohm Co Ltd マルチフェーズ型ｄｃ／ｄｃコンバータ
JP2015015785A (ja) * 2013-07-03 2015-01-22 株式会社ソニー・コンピュータエンタテインメント 降圧ｄｃ／ｄｃコンバータ、そのコントローラおよび制御方法、ならびにそれを用いた電子機器

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010110106A (ja) * 2008-10-30 2010-05-13 Rohm Co Ltd マルチフェーズ型ｄｃ／ｄｃコンバータ
JP2015015785A (ja) * 2013-07-03 2015-01-22 株式会社ソニー・コンピュータエンタテインメント 降圧ｄｃ／ｄｃコンバータ、そのコントローラおよび制御方法、ならびにそれを用いた電子機器

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