Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
  • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
  • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/01—Manufacture or treatment
  • H10D84/02—Manufacture or treatment characterised by using material-based technologies
  • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
  • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
  • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
  • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
  • H10D84/85—Complementary IGFETs, e.g. CMOS

Definitions

• This disclosure relates to semiconductor integrated circuit devices, and in particular to the layout structure of input/output circuits.
• IO cells input/output cells
• signals are input/output from/to the outside of the semiconductor integrated circuit device and power is supplied via the IO cells.
• Patent Document 1 discloses that, for a semiconductor integrated circuit device, a resistive element formed in the back end of line (BEOL: wiring process) is used as a protective resistor for an IO cell.
• BEOL back end of line
• Patent Document 2 proposes providing wiring directly under transistors to increase the integration density of semiconductor integrated circuit devices.
• Patent document 3 proposes using a vertical diode as a protection circuit for a semiconductor integrated circuit device.
• Patent Document 1 a resistive element is formed by the BEOL, but as semiconductor integrated circuit devices become finer, the area occupied by the resistive element becomes relatively larger. This reduces the area in which power supply wiring and the like can be laid, and the resistance value of the power supply wiring increases. This causes problems such as the ESD protection circuit not working effectively and a large power supply voltage drop.
• This disclosure provides a layout structure that enables higher performance for input/output circuits in semiconductor integrated circuit devices.
• a semiconductor integrated circuit device includes a first output transistor section including a first transistor of a first conductivity type connected between a first power supply that supplies a first power supply voltage and an output terminal, a first resistor connected in series with the first transistor between the first power supply and the output terminal, and a first power supply wiring that supplies the first power supply voltage, the first output transistor section forming the channel, source, and drain of the first transistor, including a first active region of the first conductivity type having a nanosheet as a channel, the first resistor being disposed on the back side of the first transistor so as to overlap the first output transistor section in a planar view, and connected to the first active region through a first via that overlaps with the first active region in a planar view, and the first power supply wiring being disposed in a wiring layer on the back side of the first transistor so as to overlap with the first active region in a planar view, and connected to the first active region through a second via that overlaps with the first active region in a planar view
• the first output transistor section includes a first transistor connected between a first power supply and an output terminal.
• the first resistor is connected in series with the first transistor between the first power supply and the output terminal.
• the first power supply wiring supplies a first power supply voltage.
• the first output transistor section includes a first active area that constitutes a channel, a source, and a drain of the first transistor.
• the first resistor is disposed on the back side of the first transistor so as to overlap with the first output transistor section in a planar view, and is connected to the first active area through a first via that overlaps with the first active area in a planar view.
• the first power supply wiring is disposed in a wiring layer on the back side of the first transistor so as to overlap with the first active area in a planar view, and is connected to the first active area through a second via that overlaps with the first active area in a planar view. This allows the resistance value between the first resistor and the first power supply for the first transistor to be reduced, allowing a large current to flow.
• a semiconductor integrated circuit device includes an ESD (Electrostatic Discharge) protection diode connected between a first power supply that supplies a first power supply voltage and an input/output terminal, a first power supply wiring that supplies the first power supply voltage, and an input/output wiring connected to the input/output terminal, the ESD protection diode comprising one terminal of the anode or cathode, a first active region of a first conductivity type having a first nanosheet, and a second active region of a second conductivity type having a second nanosheet that constitutes the other terminal of the anode or cathode, the first power supply wiring is arranged in a wiring layer on the back side of the first and second active regions so as to overlap the first active region in a planar view, and is connected to the first active region through a first via that overlaps the first active region in a planar view, and the input/output wiring is arranged in the same wiring layer as the first power supply wiring so as to overlap the second
• ESD Electrostatic Discharge
• the ESD protection diode connected between the first power supply and the input/output terminal includes a first active region of a first conductivity type constituting one of the anode and cathode terminals, and a second active region of a second conductivity type constituting the other of the anode and cathode terminals.
• the first and second active regions have nanosheets.
• the first power supply wiring and the input/output wiring are arranged in a wiring layer on the rear side of the first and second active regions.
• the first power supply wiring is arranged so as to overlap the first active region in a planar view, and is connected to the first active region through a first via that overlaps the first active region in a planar view.
• the input/output wiring is arranged so as to overlap the second active region in a planar view, and is connected to the second active region through a second via that overlaps the second active region in a planar view. This makes it possible to improve the characteristics and capabilities of the ESD protection diode without expanding the layout area.
• a semiconductor integrated circuit device includes an ESD (ElectroStatic Discharge) protection diode connected between a first power supply that supplies a first power supply voltage and a first node, an input/output terminal, a protective resistor connected between the first node, and a first power supply wiring that supplies the first power supply voltage, the ESD protection diode constituting one of the anode and cathode terminals, a first active region of a first conductivity type having a first nanosheet, and a second active region of a second conductivity type that constitutes the other of the anode and cathode terminals and is formed under the first active region.
• ESD ElectroStatic Discharge
• the first active region is connected to a first via formed on the back side of the first active region through wiring formed in an upper layer of the first active region
• the first well region is connected to a second via formed on the back side of the first well region so as to overlap the first well region in a planar view
• the first power supply wiring is disposed in a wiring layer on the back side of the first active region and is connected to one of the first and second vias
• the protective resistor is formed on the back side of the first active region and is connected to the other of the first and second vias.
• the ESD protection diode connected between the first power supply and the first node comprises a first active region of a first conductivity type having a first nanosheet, which constitutes one of the anode and cathode terminals, and a first well region of a second conductivity type formed under the first active region, which constitutes the other of the anode and cathode terminals.
• the first power supply wiring and the protective resistor are formed on the back side of the first active region.
• the first active region is connected to a first via formed on the back side of the first active region through wiring formed in an upper layer of the first active region, and the first well region is connected to a second via formed on the back side of the first well region so as to overlap the first well region in a planar view.
• the first power supply wiring is connected to one of the first and second vias, and the protective resistor is connected to the other of the first and second vias.
• This disclosure provides a layout structure that can achieve higher performance for input/output circuits in a semiconductor integrated circuit device.
• FIG. 1 is a plan view showing details of the layout of an output transistor N1 in the first embodiment
• FIG. 1 is a plan view showing details of the layout of an output transistor N1 in the first embodiment
• 5A and 5B are cross-sectional views of the layouts of FIG. 5 and FIG. 6.
• FIG. 2 is a plan view showing details of the layout of an output transistor P1 in the first embodiment
• FIG. 2 is a plan view showing details of the layout of an output transistor P1 in the first embodiment
• FIG. 2 is a plan view showing details of the layout of the ESD protection diode 1 a according to the first embodiment
• FIG. 2 is a plan view showing details of the layout of the ESD protection diode 1 a according to the first embodiment
• 10 and 11 are cross-sectional views of the layouts of FIG.
• FIG. 2 is a plan view showing details of the layout of the ESD protection diode 1b according to the first embodiment
• FIG. 2 is a plan view showing details of the layout of the ESD protection diode 1b according to the first embodiment
• 1A and 1B are plan views showing details of an ESD protection diode cdm1a in the first embodiment.
• FIG. 13 is a schematic cross-sectional view of a layout according to a modification of the first embodiment
• 11 is a schematic cross-sectional view of a layout according to a second embodiment
• FIG. 11 is a plan view showing details of the layout of an ESD protection diode 1 a according to a second embodiment
• FIG. 11 is a plan view showing details of the layout of an ESD protection diode 1 a according to a second embodiment.
• 21 and 22. (a) and (b) are cross-sectional views of the layouts of FIG.
• FIG. 11 is a plan view showing details of the layout of an ESD protection diode 1b according to a second embodiment
• FIG. 11 is a plan view showing details of the layout of an ESD protection diode 1b according to a second embodiment
• 1A and 1B are plan views showing details of an ESD protection diode cdm1a according to a second embodiment
• 1A and 1B are plan views showing details of an ESD protection diode cdm1b in a second embodiment.
• FIG. 13 is a schematic cross-sectional view of a layout according to a first modified example of the second embodiment
• FIG. 13 is a schematic cross-sectional view of a layout according to a second modification of the second embodiment;
• FIG. 13 is a schematic cross-sectional view of a layout according to a second modification of the second embodiment
• FIG. 13 is a plan view showing details of the layout of an ESD protection diode 1 a according to a second modification of the second embodiment;
• FIG. 13 is a plan view showing details of the layout of an ESD protection diode 1 a according to a second modification of the second embodiment; 30 and 31.
• FIG. 13 is a schematic cross-sectional view of a layout according to a third modification of the second embodiment;
• VDDIO and “VSS” refer to the power supply voltage or the power supply itself.
• First Embodiment Fig. 1 shows an example of the configuration of a semiconductor integrated circuit device according to an embodiment.
• the semiconductor integrated circuit device 100 shown in Fig. 1 is configured by stacking a first semiconductor chip 100A (chip AA) and a second semiconductor chip 100B (chip BB). IO cells and the like are arranged on chip AA.
• Chip BB has power supply wiring, input/output wiring, and resistance elements formed in a wiring layer provided on the surface.
• Chip BB is attached to the back side of chip AA using bumps or the like.
• the semiconductor integrated circuit device 100 includes an internal core circuit and an interface circuit (IO circuit) in which IO cells are arranged.
• the IO cells include signal IO cells and power IO cells.
• the signal IO cells include circuits required for transmitting signals between the outside of the semiconductor integrated circuit device 100 or between the internal core circuit, such as a level shifter circuit, an output buffer circuit, and an ESD protection circuit.
• the power IO cells supply each power source supplied to the external connection pads to the inside of the semiconductor integrated circuit device 100, and include an ESD protection circuit, etc.
• Chips AA and BB can be manufactured using different manufacturing processes. In particular, by manufacturing chip AA using a finer manufacturing process than chip BB, high integration can be achieved, while chip BB can be manufactured using a low-cost manufacturing process. Therefore, the semiconductor integrated circuit device as a whole can achieve high integration at low cost.
• Figure 2 shows an example of the circuit configuration of an input/output circuit included in an IO cell. Note that an actual input/output circuit includes circuit elements other than those shown in Figure 2, but these are not shown in Figure 2.
• the input/output circuit shown in FIG. 2 includes an external input/output terminal PAD, output transistors P1 and N1, ESD (Electrostatic Discharge) protection diodes 1a and 1b, protection resistors Rsn and Rsp, a protection resistor Rin, and protection diodes cdm1a and cdm1b.
• the output transistor P1 is a P-conductivity type transistor
• the output transistor N1 is an N-conductivity type transistor.
• the output transistors P1 and N1 output an output signal to the external input/output terminal PAD in accordance with a signal received at their gates.
• the source of the output transistor P1 is connected to VDDIO, and the drain is connected to the external input/output terminal PAD via a protective resistor Rsp.
• the source of the output transistor N1 is connected to VSS, and the drain is connected to the external input/output terminal PAD via a protective resistor Rsn.
• the node between the output transistor N1 and the protective resistor Rsn is referred to as node A, and the node between the output transistor P1 and the protective resistor Rsp is referred to as node B.
• the anode of the protection diode cdm1a is connected to the source of the output transistor N1, and the cathode of the protection diode cdm1b is connected to the source of the output transistor P1.
• the cathode of the protection diode cdm1a and the anode of the protection diode cdm1b are connected, and this connection node is referred to as node C.
• Node C is connected to the external input/output terminal PAD via the protection resistor Rin, and is also connected to an input circuit (not shown).
• a current flows to VDDIO and VSS via the ESD protection diodes cdm1a and cdm1b, thereby protecting the input circuit.
• ESD protection diode 1a is provided between VSS and the external input/output terminal PAD, with its anode connected to VSS and its cathode connected to the external input/output terminal PAD.
• ESD protection diode 1b is provided between VDDIO and the external input/output terminal PAD, with its anode connected to the external input/output terminal PAD and its cathode connected to VDDIO.
• the transistor and ESD protection diode are configured on chip AA, and the protection resistor is configured from multiple resistive elements formed in the wiring layer of chip BB.
• the resistive elements In order to form the resistive elements on chip BB, a process that is not as fine as that of chip AA is used for manufacturing chip BB, thereby making it possible to reduce the area of the resistive elements. This allows the area in which power supply wiring etc. is laid to be larger, and the resistance value of the power supply wiring can be reduced, allowing the ESD protection circuit to function effectively and also reducing the power supply voltage drop.
• Figure 3 is an example of an outline of the layout of an IO cell, and the input/output circuit of Figure 2 is configured.
• output transistor N1 ESD protection diode 1a
• ESD protection diodes cdm1a, cdm1b ESD protection diode 1b
• output transistor P1 ESD protection diode 1b
• Resistance elements RU are arranged in an array in the XY direction at positions overlapping with output transistor N1, ESD protection diodes cdm1a, cdm1b, and output transistor P1 in a planar view.
• Protection resistor Rsn is configured by connecting together resistance elements RU arranged at positions overlapping with output transistor N1 in a planar view.
• Protection resistor Rin is configured by connecting together resistance elements RU arranged at positions overlapping with ESD protection diodes cdm1a, cdm1b in a planar view.
• Protection resistor Rsp is configured by connecting together resistance elements RU arranged at positions overlapping with output transistor P1 in a planar view.
• the connection form of the resistance element RU may be a series connection, a parallel connection, or a combination of a series connection and a parallel connection.
• the resistive element RU is not disposed on the back surface of the ESD protection diodes 1a and 1b, the area for laying the power supply wiring and the output signal wiring can be made large. This allows the ESD protection circuit to function effectively and also reduces the power supply voltage drop.
• the protective resistors Rsn, Rsp, and Rin may partially overlap the ESD protection diodes 1a and 1b in a plan view.
• FIG. 4 is a schematic cross-sectional view of the layout in this embodiment.
• FIG. 4 shows the cross-sectional structure in the X direction for the unit structure of each component. The overall configuration of the layout will be described later.
• the transistors are formed on a P-type substrate and an N-type well. However, the transistors may be formed on a P-type well or on an N-type substrate.
• an active region including a nanosheet and gate wiring are formed on chip AA.
• the active region constitutes the channel, source, and drain of a transistor.
• the active region that constitutes a nanosheet FET has a nanosheet as a channel.
• the portions of the active region that become the source and drain on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet. Note that, as will be described later, there are cases where the active region does not constitute a transistor.
• Chip BB has the following metal wiring layers: BM0 (Backside Metal 0), BM1 (Backside Metal 1), and BM2 (Backside Metal 2).
• the BM1 layer is located below BM0, i.e., farther from the transistors
• the BM2 layer is located below the BM1 layer, i.e., farther from the transistors.
• a resistive element formation layer (BR layer) is provided below the BM2 layer.
• Resistive elements RU that form the protective resistors Rsn, Rsp, and Rin are formed in the BR layer.
• Each protective resistor Rsn, Rsp, and Rin is connected to the external input/output terminal PAD via wiring formed in the BM3 layer and other layers below.
• One terminal of the output transistor P1 is connected to the power supply VDDIO, and the other terminal is connected to the protective resistor Rsp via node B. That is, the output transistor P1 has a P-type conductive active region 301, and the protective resistor Rsp is arranged on the back side of the output transistor P1 so as to overlap with the output transistor P1 in a planar view.
• the protective resistor Rsp is connected to the active region 301 via a via that overlaps with the active region 301 in a planar view.
• the protective resistor Rsp is connected to the external input/output terminal PAD.
• One terminal of the output transistor N1 is connected to the power supply VSS, and the other terminal is connected to the protective resistor Rsn via node A. That is, the output transistor N1 has an N-conductivity type active region 302, and the protective resistor Rsn is arranged on the back side of the output transistor N1 so as to overlap with the output transistor N1 in a planar view.
• the protective resistor Rsn is connected to the active region 302 via a via that overlaps with the active region 302 in a planar view.
• the protective resistor Rsn is connected to the external input/output terminal PAD.
• Protection diode 1b is formed between N-conductivity type active region 1 connected to power supply VDDIO and P-conductivity type active region 2 connected to external input/output terminal PAD. Protection diode 1a is formed between P-conductivity type active region 3 connected to power supply VSS and N-conductivity type active region 4 connected to external input/output terminal PAD.
• the protection diode cdm1b is formed between an N-conductivity type active region 5 connected to a power supply VDDIO and a P-conductivity type active region 6 connected to a protection resistor Rin via a node C.
• the protection diode cdm1a is formed between a P-conductivity type active region 7 connected to a power supply VSS and an N-conductivity type active region 8 connected to a protection resistor Rin via a node C.
• the protection resistor Rin is connected to an external input/output terminal PAD.
• Figures 5 and 6 are plan views showing details of the layout of the output transistor N1 in Figure 3.
• Figure 5 shows the structure of the BM0 layer, BM1 layer, and BM2 layer, which are wiring layers provided on chip BB.
• Figure 6 shows the structure of the BM0 layer and its upper layers.
• Figure 7 is a cross-sectional view of the layout of Figures 5 and 6, where (a) shows the cross-sectional structure along line X1-X1' and (b) shows the cross-sectional structure along line Y1-Y1'. The direction perpendicular to the substrate surface is taken as the Z direction.
• an output transistor section 30N is formed in the center of the figure, and a guard ring section 40A is formed in a ring shape around it.
• power supply wiring 21 and input/output wiring 22 extending in the Y direction are arranged in the BM2 layer.
• the input/output wiring 22 is connected to a protective resistor Rsn formed in the BR layer through a via.
• the power supply wiring 21 supplies a power supply voltage VSS.
• the input/output wiring 22 is connected to node A.
• the power supply wiring 21 and the input/output wiring 22 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• power supply wiring 23 and input/output wiring 24 are arranged to extend in the X-direction.
• the power supply wiring 23 is connected to the power supply wiring 21 in the BM2 layer through a via.
• the input/output wiring 24 is connected to the input/output wiring 22 in the BM2 layer through a via.
• the power supply wiring 23 and the input/output wiring 24 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• power supply wiring 25 and input/output wiring 26 are arranged, extending in the Y direction.
• the power supply wiring 25 is connected to the power supply wiring 23 in the BM1 layer through a via.
• the power supply wiring 25 is formed in the guard ring section 40A, and is also formed so as to pass through the output transistor section 30N.
• the input/output wiring 26 is connected to the input/output wiring 24 in the BM1 layer through a via.
• the input/output wiring 26 is formed in the output transistor section 30N.
• an N-type active region 31 extending in the X direction is formed.
• five active regions 31 are arranged in the Y direction, and each active region 31 includes six nanosheets 32.
• Each nanosheet 32 is made up of a three-sheet structure that overlaps in a plan view, and extends in the X direction.
• the portion that becomes the source of the transistor overlaps with the power supply wiring 25 in the BM0 layer in a planar view, and is connected to the power supply wiring 25 through a via.
• the via that connects the active region 31 to the power supply wiring 25 overlaps with the active region 31 in a planar view.
• the portion that becomes the drain of the transistor overlaps with the input/output wiring 26 in the BM0 layer in a planar view, and is connected to the input/output wiring 26 through a via.
• the via that connects the active region 31 to the input/output wiring 26 overlaps with the active region 31 in a planar view.
• a gate wiring 33 is formed extending in the Y direction across the five active regions 31.
• the gate wiring 33 surrounds the outer periphery of the nanosheet 32 in the Y and Z directions via a gate insulating film (not shown).
• the gate wiring 33 corresponds to the gate of transistor N1.
• a signal wiring 34 extending in the X direction is arranged.
• the signal wiring 34 is connected to the gate wiring 33 in the output transistor section 30N through a via.
• the signal wiring 34 supplies a signal INN to the gate of transistor N1.
• a P-type active region 41 is formed in the guard ring portion 40A.
• the active region 41 includes nanosheets 42.
• Each nanosheet 42 is made up of three overlapping sheets in a plan view and extends in the X direction. However, the active region 41 does not function as a transistor.
• the portions sandwiching the nanosheet 42 overlap with the power supply wiring 25 in the BM0 layer in a plan view, and are connected to the power supply wiring 25 through vias.
• the active region 41 supplies the power supply voltage VSS supplied from the power supply wiring 25 to the P-type substrate or P-type well.
• the guard ring portion 40A suppresses noise propagation and latch-up between the output transistor portion 30N and the surrounding transistors, etc.
• a gate wiring 43 extending in the Y direction is formed in the active region 41.
• the gate wiring 43 surrounds the outer periphery of the nanosheet 42 in the Y direction and Z direction via a gate insulating film (not shown).
• the gate wiring 43 does not function as a gate of a transistor.
• Local wiring (LI) 44 is arranged extending in the Y direction.
• the local wiring 44 is formed on the upper surface of the active region 41.
• power supply wiring 45 is arranged extending in the X direction.
• the power supply wiring 45 is connected to the local wiring 44, and is also connected to the gate wiring 43. As a result, the power supply voltage VSS is supplied to the gate wiring 43 in the guard ring portion 40A.
• the above-mentioned configuration provides the following effects.
• the only wiring placed on the back of the transistor is the power supply wiring that supplies VSS, and the input/output wiring that is connected to the external input/output terminal PAD.
• the power supply wiring and input/output wiring are laid out to the maximum extent possible. This allows a large current to flow while also suppressing wiring resistance.
• the power supply wiring and input/output wiring in the BM0 layer are connected to the active region 31 that constitutes the output transistor N1 only through vias. This allows the resistance value to be reduced and allows a large current to flow.
• the power supply wiring 21, 23, 25 and the input/output wiring 22, 24, 26 are formed in a wiring layer provided on the chip BB, this is not limiting.
• the BM0 layer and the wiring layer (including the BR layer) below it may be provided on the same semiconductor chip as the semiconductor chip on which the transistor (active region) is formed.
• the power supply wiring and the input/output wiring may be formed on the back side of the transistor (active region).
• the back side of the transistor (active region) refers to the side opposite to the side on which the local wiring, metal wiring, etc. connected to the transistor are stacked.
• the top side of the transistor (active region) refers to the side on which the local wiring, metal wiring, etc. connected to the transistor are stacked.
• the power supply wiring 21, 23, and 25 and the input/output wiring 22, 24, and 26 may be formed in multiple wiring layers.
• a wiring layer may be provided even lower than the BM2 layer to form the back wiring.
• Figures 8 and 9 are plan views showing details of the layout of the output transistor P1 in Figure 3.
• Figure 8 shows the structure of the BM0-BM2 layer
• Figure 9 shows the structure of the BM0 layer and the layers above it.
• the layouts of Figures 8 and 9 have a P-type conductivity for the active region 36 in the output transistor section 30P, and an N-type conductivity for the active region 46 in the guard ring section 40B.
• the power supply voltage supplied to the portion of the active region 36 that becomes the source of transistor P1 is VDDIO, and the signal supplied to the gate of transistor P1 is INP.
• the layouts of Figures 8 and 9 can be easily understood from the explanation of the layouts of Figures 5 and 6, so a detailed explanation will be omitted here.
• the output transistor section 30P which includes a transistor P1 connected between a power supply VDDIO and an external input/output terminal PAD, includes an active region 36 that constitutes the channel, source, and drain of the transistor P1.
• the active region 36 has a nanosheet as a channel.
• the power supply wiring 28 and the input/output wiring 29 are arranged in the wiring layer on the rear side of the transistor P1 so as to overlap the active region 36 in a planar view.
• the power supply wiring 28 is connected through a via to the underside of the portion of the active region 36 that serves as the source of the transistor P1
• the input/output wiring 29 is connected through a via to the underside of the portion of the active region 36 that serves as the drain of the transistor P1. This makes it possible to pass a large current through the output terminal without expanding the layout area.
• Figures 10 and 11 are plan views showing details of the layout of the ESD protection diode 1a in Figure 3.
• Figure 10 shows the structure of the BM0-BM2 layers.
• Figure 11 shows the structure of the BM0 layer and the layers above it.
• Figure 12 is a cross-sectional view of the layout of Figures 10 and 11, where (a) shows the cross-sectional structure along line X1-X1' and (b) shows the cross-sectional structure along line Y1-Y1'.
• a cathode portion 60 is formed at the top, center, and bottom of the figure, and an anode portion 70 is formed surrounding the cathode portion 60.
• power supply wiring 51 and input/output wiring 52 extending in the Y direction are arranged in the BM2 layer.
• Power supply wiring 51 supplies a power supply voltage VSS.
• Input/output wiring 52 is connected to an external input/output terminal PAD.
• Power supply wiring 51 and input/output wiring 52 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• power supply wiring 53 and input/output wiring 54 are arranged to extend in the X-direction.
• Power supply wiring 53 is connected to power supply wiring 51 in the BM2 layer through a via.
• Input/output wiring 54 is connected to input/output wiring 52 in the BM2 layer through a via.
• Power supply wiring 53 and input/output wiring 54 are arranged with the minimum spacing allowed by the constraints of the manufacturing process.
• power supply wiring 55 and input/output wiring 56 extending in the Y direction are arranged.
• the power supply wiring 55 is connected to the power supply wiring 53 in the BM1 layer through a via.
• the power supply wiring 55 is formed in the anode section 70.
• the input/output wiring 56 is connected to the input/output wiring 54 in the BM1 layer through a via.
• the input/output wiring 56 is formed in the cathode section 60.
• an N-type active region 61 extending in the X direction is formed.
• Each active region 61 includes six nanosheets 62.
• Each nanosheet 62 is made up of three overlapping sheets in a plan view and extends in the X direction. However, the active region 61 does not function as a transistor.
• the portions sandwiching the nanosheet 62 overlap with the input/output wiring 56 in the BM0 layer in a planar view, and are connected to the input/output wiring 56 through vias.
• the vias connecting the input/output wiring 56 and the active region 61 overlap with the active region 61 in a planar view.
• a gate wiring 63 extending in the Y direction is formed in the active region 61.
• the gate wiring 63 surrounds the outer periphery of the nanosheet 62 in the Y direction and Z direction via a gate insulating film (not shown). However, the gate wiring 63 does not function as a gate of a transistor.
• the gate wiring 63 is connected to the active region 61 via a local wiring 64 and an M0 wiring 65.
• each active region 71 includes a nanosheet 72.
• Each nanosheet 72 is made up of three overlapping sheets in a plan view and extends in the X direction. However, the active region 71 does not function as a transistor.
• the portion sandwiching the nanosheet 72 overlaps with the power supply wiring 55 in the BM0 layer in a planar view, and is connected to the power supply wiring 55 through a via.
• the via connecting the power supply wiring 55 and the active region 71 overlaps with the active region 71 in a planar view.
• a gate wiring 73 extending in the Y direction is formed in the active region 71.
• the gate wiring 73 surrounds the outer periphery of the nanosheet 72 in the Y and Z directions via a gate insulating film (not shown). However, the gate wiring 73 is not the gate of a transistor.
• the gate wiring 73 is connected to the active region 71 via a local wiring 74 and an M0 wiring 75. In other words, the potential of the gate wiring 73 is fixed to VSS.
• the above-mentioned configuration provides the following effects.
• the only wiring arranged on the back surface of the active regions 61, 71 that make up the ESD protection diode 1a is the power supply wiring that supplies VSS and the input/output wiring that is connected to the external input/output terminal PAD.
• the power supply wiring and input/output wiring are laid out to the maximum extent possible. This makes it possible to reduce the wiring resistance and improve the characteristics and capabilities of the ESD protection diode 1a.
• the power supply wiring and input/output wiring in the BM0 layer are connected to the active regions 61 and 71 that constitute the ESD protection diode 1a only through vias. This allows the resistance value to be reduced, improving the characteristics and capabilities of the ESD protection diode 1a.
• the power supply wiring 51, 53, and 55 and the input/output wiring 52, 54, and 56 may be formed in multiple wiring layers.
• a wiring layer may be provided even lower than the BM2 layer to form the back wiring.
• Figures 13 and 14 are plan views showing details of the layout of the ESD protection diode 1b in Figure 3.
• Figure 13 shows the structure of the BM0-BM2 layers
• Figure 14 shows the structure of the BM0 layer and the layers thereover.
• the positions of the anode and cathode parts are swapped compared to the layouts of Figures 10 and 11. That is, the anode parts 70A are formed at the top, center, and bottom of the figures, and the cathode parts 60A are formed so as to surround the anode parts 70A.
• the conductivity type of the active region 77 in the anode part 70A is P type
• the conductivity type of the active region 67 in the cathode part 60A is N type.
• the power supply voltage supplied to the part of the active region 67 of the cathode part 60A that sandwiches the nanosheet is VDDIO.
• the input/output wiring 57 in the BM2 layer is continuous with the input/output wiring 52 in the BM2 layer of the ESD protection diode 1a.
• the ESD protection diode 1b connected between the power supply VDDIO and the external input/output terminal PAD has an N-type active region 67 constituting the cathode section 60A, and a P-type active region 77 constituting the anode section 70A.
• the power supply wiring 58 and the input/output wiring 59 are arranged in a wiring layer on the rear side of the active regions 67, 77.
• the power supply wiring 58 is connected via a via to the underside of the portion of the active region 67 that sandwiches the nanosheet
• the input/output wiring 59 is connected via a via to the underside of the portion of the active region 77 that sandwiches the nanosheet. This makes it possible to improve the characteristics and capabilities of the ESD protection diode 1b without expanding the layout area.
• FIG. 15A and 15B are plan views showing the details of the layout of the ESD protection diode cdm1a.
• Fig. 15A shows the structures of the BM0 layer, the BM1 layer, and the BM2 layer.
• Fig. 15B shows the structures of the BM0 layer and the layers above it.
• the layouts shown in Figures 15(a) and (b) have the same basic configuration as the layout of the ESD protection diode 1a shown in Figures 10 and 11. However, the ESD protection diode cdm1a has a smaller planar size than the ESD protection diode 1a.
• the input/output wiring 81 in the BM2 layer corresponds to node C. As shown in Figure 4, node C is connected to the resistive element Rin formed in the BR layer below it.
• the wiring in the M0 wiring layer that corresponds to node C is connected to transistors of an input/output circuit (not shown), etc.
• ⁇ ESD protection diode cdm1b> 16 is a plan view showing the details of the layout of the ESD protection diode cdm1b.
• Fig. 16(a) shows the structures of the BM0 layer, the BM1 layer, and the BM2 layer.
• Fig. 16(b) shows the structures of the BM0 layer and the layers above it.
• the layouts shown in Figures 16(a) and (b) have a basic configuration similar to that of the ESD protection diode 1b shown in Figures 13 and 14. However, the ESD protection diode cdm1b has a smaller planar size than the ESD protection diode 1b.
• the input/output wiring 82 in the BM2 layer corresponds to node C. As shown in Figure 4, node C is connected to the resistive element Rin formed in the BR layer below it.
• the wiring in the M0 wiring layer corresponding to node C is connected to transistors of an input/output circuit (not shown), etc.
• Fig. 17 is a circuit diagram of an input/output circuit according to a modified example of the first embodiment.
• the circuit configuration of Fig. 17 is almost the same as the circuit configuration of Fig. 2 in the first embodiment, but the position of the protective resistor is different. That is, in the input/output circuit of Fig. 17, a protective resistor Rs is provided instead of the protective resistors Rsn and Rsp in Fig. 2.
• the drains of the output transistors P1 and N1 are connected to each other, and the protective resistor Rs is provided between the external input/output terminal PAD and the drains of the output transistors P1 and N1.
• the node between the drains of the output transistors P1 and N1 and the protective resistor Rs is referred to as node D.
• FIG. 18 is an example of an outline of an IO cell layout according to this modified example, in which the input/output circuit of FIG. 17 is configured. From the bottom of the drawing, ESD protection diodes 1a, cdm1a, output transistors N1, P1, and ESD protection diodes cdm1b, 1b are arranged. Resistance elements RU are arranged in an array in the XY direction at positions overlapping the ESD protection diode cdm1a and the output transistors N1, P1 in a planar view. The resistance elements RU arranged at positions overlapping the output transistors N1, P1 in a planar view are connected to each other to configure a protection resistor Rs.
• the resistance elements RU arranged at positions overlapping the ESD protection diode cdm1a in a planar view are connected to each other to configure a protection resistor Rin.
• the connection form of the resistance elements RU may be any of series connection, parallel connection, or a combination of series connection and parallel connection.
• the protection resistor Rin may also be arranged at a position overlapping the ESD protection diode cdm1b in a planar view.
• the resistive element RU is not disposed on the back surface of the ESD protection diodes 1a and 1b, the area for laying the power supply wiring and the output signal wiring can be made large. This allows the ESD protection circuit to function effectively and also reduces the power supply voltage drop.
• the protective resistors Rs and Rin may partially overlap the ESD protection diodes 1a and 1b in a plan view.
• FIG. 19 is a schematic cross-sectional view of the layout according to this modified example. As with FIG. 4, FIG. 19 shows the cross-sectional structure in the X direction for the unit structure of each component.
• one terminal of the output transistor P1 is connected to a power supply VDDIO, and one terminal of the output transistor N1 is connected to a power supply VSS.
• the other terminals of the output transistors P1 and N1 are connected to each other via wiring formed in the BM2 layer, and are also connected to the protective resistor Rs via node D.
• the protection diode cdm1a has an N-conductivity type active region 8 connected to the protection resistor Rin via node C.
• the protection diode cdm1b has a P-conductivity type active region 6 connected to the protection resistor Rin via wiring formed in the BM3 layer. Note that the connection to the protection resistor Rin may be made via wiring formed in a layer other than the BM3 layer.
• the circuit diagram of the input/output circuit is the same as that shown in FIG. 2 in the first embodiment, and the layout plan view is the same as that shown in FIG.
• FIG. 20 is a schematic cross-sectional view of the layout in the second embodiment. As with FIG. 4, FIG. 20 shows the cross-sectional structure in the X direction for the unit structure of each component. The overall configuration of the layout will be described later.
• an active region including a nanosheet and gate wiring are formed on chip AA.
• BM0 layer, BM1 layer, and BM2 layer are formed as metal wiring layers.
• a resistive element formation layer (BR layer) is provided below the BM2 layer.
• Resistive elements RU constituting protective resistors Rsn, Rsp, and Rin are formed in the BR layer.
• Each protective resistor Rsn, Rsp, and Rin is connected to an external input/output terminal PAD via wiring formed in the BM3 layer and the like below.
• One terminal of the output transistor P1 is connected to the power supply VDDIO, and the other terminal is connected to the protective resistor Rsp via node B.
• the protective resistor Rsp is connected to the external input/output terminal PAD.
• One terminal of the output transistor N1 is connected to the power supply VSS, and the other terminal is connected to the protective resistor Rsn via node A.
• the protective resistor Rsn is connected to the external input/output terminal PAD.
• the power supply VDDIO is raised to the upper wiring layer via the active area and local wiring (LI) of the output transistor P1.
• the power supply VDDIO is supplied to the active areas 101 and 102 of the ESD protection diodes 1b and cdm1b via wiring in the upper wiring layer.
• the power supply VSS is raised to the upper wiring layer via the active area and local wiring (LI) of the output transistor N1.
• the power supply VSS is supplied to the active areas 103 and 104 of the ESD protection diodes 1a and cdm1a via wiring in the upper wiring layer.
• ESD protection diode 1b is formed between N-conductivity type active region 101 connected to power supply VDDIO and P-type well 105 connected to external input/output terminal PAD.
• ESD protection diode 1a is formed between P-conductivity type active region 103 connected to power supply VSS and N-type well 107 connected to external input/output terminal PAD.
• the ESD protection diode cdm1b is formed between the N-conductivity type active region 102 connected to the power supply VDDIO and the P-type well 106 connected to the protection resistor Rin via node C.
• the ESD protection diode cdm1a is formed between the P-conductivity type active region 104 connected to the power supply VSS and the N-type well 108 connected to the protection resistor Rin via node C.
• the protection resistor Rin is connected to the external input/output terminal PAD.
• the ESD protection diode is formed vertically.
• vertical means perpendicular to the substrate.
• Output transistors P1, N1> The layout of the output transistors P1 and N1 is the same as that of the first embodiment, and illustration and description thereof will be omitted here. However, as described above, the active area of the output transistor P1 connected to the power supply VDDIO is connected to the upper layer wiring via a local wiring. Also, the active area of the output transistor N1 connected to the power supply VSS is connected to the upper layer wiring via a local wiring.
• Figures 21 and 22 are plan views showing details of the layout of the ESD protection diode 1a.
• Figure 21 shows the structures of the BM0 layer, the BM1 layer, and the BM2 layer.
• Figure 22 shows the structure of the BM0 layer and the layers above it.
• Figure 23 is a cross-sectional view of the layout of Figures 21 and 22, where (a) shows the cross-sectional structure along line X1-X1' and (b) shows the cross-sectional structure along line Y1-Y1'.
• input/output wiring 111 extending in the Y direction is arranged.
• the input/output wiring 111 is connected to an external input/output terminal PAD.
• the input/output wiring 111 is arranged at the minimum interval given by the constraints of the manufacturing process.
• input/output wiring 112 extending in the X direction is arranged.
• the input/output wiring 112 is connected to the input/output wiring 111 in the BM2 layer via a via.
• the input/output wiring 112 is arranged at the minimum interval given by the constraints of the manufacturing process.
• input/output wiring 113 extending in the Y direction is arranged.
• the input/output wiring 113 is connected to the output wiring 112 in the BM1 layer via a via.
• a P-type active region 131 extending in the X-direction is formed in an N-type well 121.
• Each active region 131 includes ten nanosheets 132.
• Each nanosheet 132 is made up of three overlapping sheets in a plan view, and extends in the X-direction.
• the active region 131 does not function as a transistor.
• the N-type well 121 is connected to the input/output wiring 113 in the BM0 layer below it through a via.
• the N-type well 121 forms the cathode of the diode.
• the portion sandwiching the nanosheet 132 (the portion corresponding to the source and drain of the transistor) is connected to a local wiring 141 formed on the upper layer and extending in the Y direction.
• Power supply wiring 151 extending in the X direction is formed in the M0 wiring layer.
• the power supply wiring 151 supplies VSS.
• the power supply wiring 151 is connected to the local wiring 141 through a via.
• the portion of the active region 131 that sandwiches the nanosheet 132 forms the anode of the diode.
• a gate wiring 135 extending in the Y direction is formed.
• the gate wiring 135 surrounds the outer periphery of the nanosheet 132 in the Y direction and Z direction via a gate insulating film (not shown). However, the gate wiring 135 does not function as the gate of a transistor.
• the gate wiring 135 is connected to the power supply wiring 151 through a via.
• the above-mentioned configuration provides the following effects.
• the only wiring arranged on the back surface of the active region 131 that constitutes the ESD protection diode 1a is the input/output wiring connected to the external input/output terminal PAD. Furthermore, the input/output wiring is laid out to the maximum extent possible in the BM1 and BM2 layers. This makes it possible to reduce the wiring resistance and improve the characteristics and capabilities of the ESD protection diode 1a.
• the input/output wiring 113 in the BM0 layer is connected to the N-type well 121 that constitutes the cathode of the ESD protection diode 1a only through vias. This makes it possible to reduce the resistance value and improve the characteristics and capabilities of the ESD protection diode 1a.
• ⁇ ESD Protection Diode 1b> 24 and 25 are plan views showing the details of the layout of the ESD protection diode 1b.
• Fig. 24 shows the structure of the BM0 layer, the BM1 layer and the BM2 layer.
• Fig. 25 shows the structure of the BM0 layer and the layers above it.
• the layout in FIG. 24 is the same as the layout in FIG. 21.
• input/output wiring 114 extending in the Y direction is arranged.
• the input/output wiring 114 is connected to an external input/output terminal PAD.
• input/output wiring 115 extending in the X direction is arranged.
• the input/output wiring 115 is connected to the input/output wiring 114 in the BM2 layer via a via.
• input/output wiring 116 extending in the Y direction is arranged.
• the input/output wiring 116 is connected to the input/output wiring 115 in the BM1 layer via a via.
• an N-type active region 133 extending in the X-direction is formed in a P-type well 122.
• Each active region 133 includes ten nanosheets 134.
• Each nanosheet 134 is made up of three overlapping sheets in a plan view, and extends in the X-direction.
• the active region 133 does not function as a transistor.
• the P-type well 122 is connected to the input/output wiring 116 of the BM0 layer below it through a via.
• the P-type well 122 forms the anode of the diode.
• the portion sandwiching the nanosheet 134 (the portion corresponding to the source and drain of the transistor) is connected to a local wiring 142 formed on the upper layer and extending in the Y direction.
• Power supply wiring 152 extending in the X direction is formed in the M0 wiring layer.
• the power supply wiring 152 supplies VDDIO.
• the power supply wiring 152 is connected to the local wiring 142 through a via.
• the portion of the active region 133 that sandwiches the nanosheet 134 forms the cathode of the diode.
• a gate wiring 136 extending in the Y direction is formed.
• the gate wiring 136 surrounds the outer periphery of the nanosheet 134 in the Y direction and the Z direction with a gate insulating film (not shown) interposed therebetween. However, the gate wiring 136 does not function as the gate of a transistor.
• the gate wiring 136 is connected to the power supply wiring 152 through a via.
• the above-mentioned configuration provides the following effects.
• the only wiring arranged on the back surface of the active region 133 that constitutes the ESD protection diode 1b is the input/output wiring connected to the external input/output terminal PAD. Furthermore, the input/output wiring is laid out to the maximum extent possible in the BM1 and BM2 layers. This makes it possible to reduce the wiring resistance and improve the characteristics and capabilities of the ESD protection diode 1b.
• the input/output wiring 116 in the BM0 layer is connected to the P-type well 122 that constitutes the anode of the ESD protection diode 1b only through vias. This makes it possible to reduce the resistance value and improve the characteristics and capabilities of the ESD protection diode 1b.
• 26A and 26B are plan views showing the details of the layout of the ESD protection diode cdm1a.
• Fig. 26A shows the structures of the BM0 layer, the BM1 layer, and the BM2 layer.
• Fig. 26B shows the structures of the BM0 layer and the layers above it.
• the layout shown in Figures 26(a) and (b) has a basic configuration similar to that of the ESD protection diode 1a shown in Figures 21 and 22.
• the ESD protection diode cdm1a has a smaller planar size than the ESD protection diode 1a.
• the input/output wiring 117 of the BM2 layer is connected to node C. Note that node C is connected to the resistive element Rin formed in the BR layer below it, as shown in Figure 20.
• VSS is supplied to the active region constituting the anode of the ESD protection diode cdm1a via the power supply wiring 151 formed in the M0 wiring layer of the ESD protection diode 1a and upper layer wiring (details not shown).
• the power supply wiring 151 that supplies VSS is arranged in the M0 wiring layer of the ESD protection diode 1a. This makes it possible to reduce the resistance value and improve the characteristics and capabilities of the ESD protection diode cdm1a.
• FIG. 27A and 27B are plan views showing the details of the layout of the ESD protection diode cdm1b.
• Fig. 27A shows the structures of the BM0 layer, the BM1 layer, and the BM2 layer.
• Fig. 27B shows the structure of the BM0 wiring layer and the layers above it.
• the layout shown in Figures 27(a) and (b) has a basic configuration similar to that of the layout of ESD protection diode 1b shown in Figures 24 and 25.
• the ESD protection diode cdm1b has a smaller planar size than the ESD protection diode 1b.
• the input/output wiring 118 of the BM2 layer is connected to node C. Note that node C is connected to the resistive element Rin formed in the BR layer below it, as shown in Figure 20.
• the active region constituting the anode of the ESD protection diode cdm1b is supplied with VDDIO via the power supply wiring 152 formed in the M0 wiring layer of the ESD protection diode 1b and upper layer wiring (details not shown).
• the power supply wiring 152 that supplies VDDIO is arranged in the M0 wiring layer of the ESD protection diode 1b. This makes it possible to reduce the resistance value and improve the characteristics and capabilities of the ESD protection diode cdm1b.
• the first modification of the second embodiment is the same as the first modification in terms of the circuit configuration of the input/output circuit and the planar layout of the IO cells. That is, in this modification, the input/output circuit having the circuit configuration shown in Fig. 17 is configured as shown in the planar layout of Fig. 18.
• a protective resistor Rs is provided instead of the protective resistors Rsn and Rsp.
• the drains of the output transistors P1 and N1 are connected to each other, and the protective resistor Rs is provided between the external input/output terminal PAD and the drains of the output transistors P1 and N1.
• FIG. 28 is a schematic cross-sectional view of the layout according to this modified example. As with FIG. 4 etc., FIG. 28 shows the cross-sectional structure in the X direction for the unit structure of each component.
• one terminal of the output transistor P1 is connected to the power supply VDDIO, and one terminal of the output transistor N1 is connected to the power supply VSS.
• the other terminals of the output transistors P1 and N1 are connected to each other via wiring formed in the BM2 layer, and are also connected to the protective resistor Rs via node D.
• the protection diode cdm1a has an N-type well 108 connected to the protection resistor Rin via node C.
• the protection diode cdm1b has a P-type well 106 connected to the protection resistor Rin via wiring formed in the BM3 layer. Note that the connection may also be made via wiring formed in a layer other than the BM3 layer.
• the second modification of the second embodiment is the same as the second embodiment in terms of the circuit configuration of the input/output circuit and the planar layout of the IO cells.
• FIG. 29 is a schematic cross-sectional view of the layout according to this modified example. As with FIG. 4 and others, FIG. 29 shows the cross-sectional structure in the X direction for the unit structure of each component. Here, detailed explanations of the same configuration as FIG. 20 shown in the second embodiment may be omitted.
• the configuration of the output transistors P1 and N1 is the same as that shown in FIG. 20. However, there is no local wiring or the like for raising the power supplies VDDIO and VSS to the upper wiring layer.
• the anode and cathode positions of the ESD protection diodes 1a, 1b, cdm1a, and cdm1b are configured upside down compared to the second embodiment.
• a configuration has been added to provide a connection node with the external input/output terminal PAD on the upper side of the active area.
• the ESD protection diode 1b is formed between an N-type well 201 connected to a power supply VDDIO and a P-type active region 205. Also, an active region 211 connected to an external input/output terminal PAD is provided. The P-type active region 205 is connected to the active region 211 via local wiring and upper layer wiring formed on its upper surface.
• the ESD protection diode 1a is formed between a P-type well 202 connected to a power supply VSS and an N-type active region 206.
• an active region 212 connected to an external input/output terminal PAD is provided.
• the N-type active region 206 is connected to the active region 212 via local wiring and upper layer wiring formed on its upper surface.
• the ESD protection diode cdm1b is formed between the N-type well 203 connected to the power supply VDDIO and the P-type active region 207.
• the protection diode cdm1a is formed between the P-type well 204 connected to the power supply VSS and the N-type active region 208.
• an active region 213 connected to a protection resistor Rin is provided.
• the P-type active region 207 and the N-type active region 208 are connected to the active region 213 via local wiring and upper layer wiring formed on their upper surfaces.
• FIGS. 30 and 31 are plan views showing the details of the layout of ESD protection diode 1a.
• FIG. 30 shows the structures of the BM0, BM1 and BM2 layers.
• FIG. 31 shows the structure of the BM0 layer and the layers above it.
• FIG. 32 is a cross-sectional view of the layout of FIGS. 30 and 31, showing the cross-sectional structure along line Y1-Y1'.
• the area AR1 in which the top row of active areas 231 are arranged is an area for providing a connection node with the external input/output terminal PAD on the upper surface side of the active area.
• the area AR2 below the area AR1 forms a diode.
• Six rows of N-type active areas 235 are arranged in area AR2.
• input/output wiring 211, 212, 213 connected to the external input/output terminal PAD are formed on the BM0 to BM2 layers.
• the N-conductivity type active region 231 is connected through a via to the input/output wiring 213 on the BM0 layer provided below it.
• the portion sandwiching the nanosheet 232 is connected to a local wiring 241 formed on the layer above it, extending in the Y direction.
• power supply wiring 214, 215, 216 connected to the power supply VSS are formed in the BM0 to BM2 layers.
• the P-type well 221 is connected through a via to the power supply wiring 216 in the BM0 layer provided below it.
• the P-type well 221 forms the anode of the diode.
• the portion sandwiching the nanosheet 236 is connected to the local wiring 241.
• the active region 235 is connected to the external input/output terminal PAD through the local wiring 241 and the active region 231, and forms the cathode of the diode.
• the above-mentioned configuration provides the following effects.
• Most of the wiring arranged on the back surface of the active region 235 that constitutes the ESD protection diode 1a is power wiring that supplies VSS.
• the power wiring is laid out to the maximum extent. This makes it possible to reduce the wiring resistance and improve the characteristics and capabilities of the ESD protection diode 1a.
• the power supply wiring in the BM0 layer is connected to the P-type well 221 that constitutes the anode of the ESD protection diode 1a only through vias. This makes it possible to reduce the resistance value and improve the characteristics and capabilities of the ESD protection diode 1a.
• the active region 235 that constitutes the cathode of the ESD protection diode 1a is connected to the external input/output terminal PAD via the local wiring 241 and the active region 231.
• the local wiring layer only the local wiring 241 that is connected to the external input/output terminal PAD is arranged. This makes it possible to reduce the resistance value and improve the characteristics and capabilities of the ESD protection diode 1a.
• the input/output wirings 211, 212, and 213 and the power supply wirings 214, 215, and 216 may be formed in a plurality of wiring layers.
• a wiring layer may be provided even lower than the BM2 layer to form the back wiring.
• the layout of the ESD protection diode 1b is not shown, but is almost the same as that of the ESD protection diode 1a. That is, in FIG. 30 and FIG. 31, the power supply is changed from VSS to VDDIO, the P-type well is changed to an N-type well, and the conductivity type of the active region that constitutes the diode is changed from N-type to P-type.
• the layout of the ESD protection diode cdm1a is the same as that of the ESD protection diode 1a. However, as in the second embodiment, the planar size of the ESD protection diode cdm1a is smaller than that of the ESD protection diode 1a, and the input/output wiring of the BM2 layer is connected to node C.
• the layout of the ESD protection diode cdm1b is the same as that of the ESD protection diode 1b. However, as in the second embodiment, the planar size of the ESD protection diode cdm1b is smaller than that of the ESD protection diode 1b, and the input/output wiring of the BM2 layer is connected to node C.
• this modification can be realized by changing the circuit configuration of the input/output circuit, similar to modification 1 of the second embodiment.
• the circuit configuration of the input/output circuit and the planar layout of the IO cells are the same as those in the second modification of the second embodiment.
• the protective resistor Rin is provided on the upper surface side of the active region, not on the rear surface side of the active region.
• FIG. 33 is a schematic cross-sectional view of the layout according to this modified example. As with FIG. 4 and others, FIG. 33 shows the cross-sectional structure in the X direction for the unit structure of each component. Here, detailed explanations of the same configuration as FIG. 29 shown in modified example 2 of the second embodiment may be omitted.
• the configuration of the output transistors P1 and N1 and the ESD protection diodes 1a and 1b is the same as that shown in FIG. 29.
• the configuration of the ESD protection diodes cdm1a and cdm1b is the same as that of FIG. 29. However, the active region 213 connected to the protection resistor Rin in FIG. 29 is not provided in the configuration of FIG. 33.
• the N-type active region 208 constituting the ESD protection diode cdm1a and the P-type active region 207 constituting the ESD protection diode cdm1b are connected via local wiring and upper layer wiring. This upper layer wiring becomes node C.
• One end of the protective resistor Rin provided on the upper surface side of the active area is connected to the upper layer wiring that serves as node C, and the other end is connected via the upper layer wiring to the active area 211 connected to the external input/output terminal PAD.
• the other end of the protective resistor Rin may also be connected via the upper layer wiring to the active area 212 connected to the external input/output terminal PAD.
• the protective resistor Rin is provided on the upper surface side of the active area, making the active area 213 in FIG. 29 unnecessary. This makes it possible to further reduce the layout area.
• the present disclosure makes it possible to achieve higher performance for input/output circuits in semiconductor integrated circuit devices, and is therefore useful for improving the performance of, for example, SoCs (System on a Chip).
• SoCs System on a Chip

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  • 2024-05-07 JP JP2025521926A patent/JPWO2024241869A1/ja active Pending
  • 2024-05-07 WO PCT/JP2024/017007 patent/WO2024241869A1/ja not_active Ceased

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