WO2024204492A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2024204492A1
WO2024204492A1 PCT/JP2024/012559 JP2024012559W WO2024204492A1 WO 2024204492 A1 WO2024204492 A1 WO 2024204492A1 JP 2024012559 W JP2024012559 W JP 2024012559W WO 2024204492 A1 WO2024204492 A1 WO 2024204492A1
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Prior art keywords
region
film
body region
electrode
regions
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PCT/JP2024/012559
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English (en)
French (fr)
Japanese (ja)
Inventor
一 和栗
佑紀 中野
誠悟 森
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202480020671.6A priority Critical patent/CN121014270A/zh
Priority to JP2025511113A priority patent/JPWO2024204492A1/ja
Priority to DE112024001516.6T priority patent/DE112024001516T5/de
Publication of WO2024204492A1 publication Critical patent/WO2024204492A1/ja
Priority to US19/342,707 priority patent/US20260032950A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/60—Impurity distributions or concentrations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping

Definitions

  • Patent document 1 discloses a semiconductor device with a body region.
  • the present disclosure provides a semiconductor device having a novel configuration and a manufacturing method thereof.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a drift region of a first conductivity type formed on a surface layer of the main surface, and a body region of a second conductivity type formed in a tapered shape on the surface layer of the drift region such that its horizontal width decreases in the thickness direction and the body region has a peripheral portion that is inclined obliquely relative to the main surface.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a drift region of a first conductivity type formed in a surface layer of the main surface, a body region of a second conductivity type formed in a surface layer of the drift region, and a contact region of the second conductivity type formed in the surface layer of the body region and having an impurity concentration higher than the impurity concentration of the body region, the body region including a high concentration region formed in a thickness range below the contact region, and a low concentration region formed in a region on the peripheral side of the high concentration region within the thickness range.
  • the present disclosure provides a method for manufacturing a semiconductor device, including the steps of preparing a wafer having a drift region of a first conductivity type in a surface layer of a main surface, and injecting impurities of a second conductivity type into the surface layer of the drift region so that the horizontal injection range decreases in the thickness direction, thereby forming a body region of the second conductivity type having a peripheral portion that is inclined obliquely relative to the main surface.
  • FIG. 1 is a plan view showing a semiconductor device according to a first embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing an example of the layout of the first main surface.
  • FIG. 4 is an enlarged plan view showing a main portion of the first main surface.
  • FIG. 5 is an enlarged plan view showing further essential parts of the first main surface.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is an enlarged cross-sectional view showing a main portion of the area shown in FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. FIG.
  • FIG. 10A is an enlarged cross-sectional view showing a body structure according to the first embodiment.
  • FIG. 10B is an enlarged cross-sectional view showing the body structure according to the second embodiment.
  • FIG. 10C is an enlarged cross-sectional view showing a body structure according to the third embodiment.
  • FIG. 10D is an enlarged cross-sectional view showing the body structure according to the fourth embodiment.
  • FIG. 10E is an enlarged cross-sectional view showing the body structure according to the fifth embodiment.
  • FIG. 10F is an enlarged cross-sectional view showing a body structure according to the sixth embodiment.
  • FIG. 11A is a graph showing the concentration gradient within a first region of the body structure.
  • FIG. 11B is a graph showing the concentration gradient within the second region of the body structure.
  • FIG. 12 is a schematic diagram showing a wafer used in the manufacture of semiconductor devices.
  • FIG. 13A is a cross-sectional view showing a method for manufacturing a semiconductor device.
  • FIG. 13B is a cross-sectional view showing a step subsequent to that of FIG. 13A.
  • FIG. 13C is a cross-sectional view showing a step subsequent to FIG. 13B.
  • FIG. 13D is a cross-sectional view showing a step subsequent to FIG. 13C.
  • FIG. 13E is a cross-sectional view showing a step subsequent to FIG. 13D.
  • FIG. 13F is a cross-sectional view showing a step subsequent to FIG. 13E.
  • FIG. 13A is a cross-sectional view showing a method for manufacturing a semiconductor device.
  • FIG. 13B is a cross-sectional view showing a step subsequent to that of FIG. 13A.
  • FIG. 13C
  • FIG. 13G is a cross-sectional view showing a step subsequent to FIG. 13F.
  • FIG. 13H is a cross-sectional view showing a step subsequent to FIG. 13G.
  • FIG. 14 is an enlarged cross-sectional view showing a body structure according to a reference example.
  • FIG. 15A is a graph showing a concentration gradient in a first region of a body structure according to a reference example.
  • FIG. 15B is a graph showing the concentration gradient in the second region of the body structure according to the reference example.
  • FIG. 16 is a cross-sectional view showing a semiconductor device according to the second embodiment.
  • FIG. 17 is a cross-sectional view showing a modified example of the field region.
  • FIG. 18 is a cross-sectional view showing a first modified example of a source pad electrode.
  • FIG. 19 is a cross-sectional view showing a second modified example of the source pad electrode.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1A according to the first embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing an example of the layout of the first main surface 3.
  • FIG. 4 is an enlarged plan view showing a main portion of the first main surface 3.
  • FIG. 5 is an enlarged plan view showing further main portions of the first main surface 3.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5.
  • FIG. 7 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 6.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.
  • FIG. 9 is an enlarged cross-sectional view showing a main portion of the region shown in FIG. 8.
  • semiconductor device 1A is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure.
  • the transistor structure Tr has a vertical structure.
  • Semiconductor device 1A is a SiC semiconductor device having a chip 2 including a SiC single crystal. Chip 2 may be referred to as a "SiC chip” or a "semiconductor chip.”
  • the chip 2 is made of hexagonal SiC single crystal and is formed into a rectangular parallelepiped shape.
  • the hexagonal SiC single crystal has a number of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • the first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • the first direction X may be the a-axis direction of the SiC single crystal
  • the second direction Y may be the m-axis direction of the SiC single crystal.
  • the direction extending along the first main surface 3 may be referred to as the "horizontal direction.”
  • the horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction by the off angle.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the chip 2 has a layered structure including a first semiconductor layer 6 and a second semiconductor layer 7.
  • the first semiconductor layer 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal) and has the off direction and off angle described above.
  • the first semiconductor layer 6 forms the second main surface 4 and forms part of the first to fourth side surfaces 5A to 5D.
  • the first semiconductor layer 6 may have a thickness of 10 ⁇ m or more and 500 ⁇ m or less.
  • the thickness of the first semiconductor layer 6 may have a value that belongs to at least one of the following ranges: 10 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 300 ⁇ m or less, 300 ⁇ m or more and 400 ⁇ m or less, and 400 ⁇ m or more and 500 ⁇ m or less.
  • the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal) and is laminated on the first semiconductor layer 6.
  • the second semiconductor layer 7 has the off direction and off angle described above.
  • the second semiconductor layer 7 forms the first main surface 3 and forms parts of the first to fourth side surfaces 5A to 5D. It is preferable that the second semiconductor layer 7 has a thickness less than that of the first semiconductor layer 6. Of course, the thickness of the second semiconductor layer 7 may be greater than the thickness of the first semiconductor layer 6.
  • the thickness of the second semiconductor layer 7 may be 5 ⁇ m or more and 50 ⁇ m or less.
  • the thickness of the second semiconductor layer 7 may have a value that belongs to at least one of the following ranges: 5 ⁇ m or more and 10 ⁇ m or less, 10 ⁇ m or more and 15 ⁇ m or less, 15 ⁇ m or more and 20 ⁇ m or less, 20 ⁇ m or more and 25 ⁇ m or less, 25 ⁇ m or more and 30 ⁇ m or less, 30 ⁇ m or more and 35 ⁇ m or less, 35 ⁇ m or more and 40 ⁇ m or less, 40 ⁇ m or more and 45 ⁇ m, and 45 ⁇ m or more and 50 ⁇ m or less.
  • the semiconductor device 1A includes an active region 8 set on the chip 2 (first main surface 3).
  • the active region 8 is set on the inner part of the chip 2 (first main surface 3).
  • the active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 8 is set in the inner part of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side faces 5A to 5D) in a plan view.
  • the active region 8 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the semiconductor device 1A includes a peripheral region 9 that is set outside the active region 8 in the chip 2.
  • the peripheral region 9 is a region that does not include a device structure (transistor structure Tr).
  • the peripheral region 9 is set on the periphery of the chip 2 (first main surface 3). In other words, the peripheral region 9 is provided in the region between the periphery of the chip 2 and the active region 8 in a planar view.
  • the peripheral region 9 extends in a band shape along the active region 8 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 8.
  • the semiconductor device 1A includes an n-type drain region 10 formed in a surface layer portion of the second main surface 4 in the active region 8.
  • the drain region 10 may be referred to as a "first region", a “first semiconductor region”, or the like.
  • a drain potential as a high potential (first potential) is applied to the drain region 10.
  • the drain region 10 may be referred to as a "first region”, a “first semiconductor region”, or the like.
  • the drain region 10 may have an impurity concentration of 5 ⁇ 10 17 cm -3 or more and 3 ⁇ 10 19 cm -3 or less.
  • the drain region 10 extends in a layer shape along the second main surface 4.
  • the drain region 10 is formed over the entire active region 8.
  • the drain region 10 is extended from the active region 8 to the peripheral region 9, and has a portion in the peripheral region 9 that is located in the surface layer of the second main surface 4.
  • the drain region 10 is extended from the active region 8 to the peripheral region 9 over the entire circumference.
  • the drain region 10 is exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the drain region 10 is exposed from the entire circumference of the first to fourth side surfaces 5A to 5D.
  • the drain region 10 is formed in the first semiconductor layer 6.
  • the drain region 10 is formed in the entire thickness range between the lower end (second main surface 4) of the first semiconductor layer 6 and the upper end (second semiconductor layer 7) of the first semiconductor layer 6, and is connected to the second semiconductor layer 7.
  • the drain region 10 is formed using the n-type first semiconductor layer 6, and has a thickness corresponding to the thickness of the first semiconductor layer 6.
  • the drain region 10 may also be formed by introducing n-type impurities into the surface layer of the second main surface 4 of the chip 2.
  • the semiconductor device 1A includes an n-type drift region 11 formed in the surface layer of the first main surface 3 in the active region 8.
  • the drift region 11 may also be referred to as a "second region,” a “second semiconductor region,” or the like.
  • the drift region 11 has an impurity concentration lower than the impurity concentration of the drain region 10.
  • the drift region 11 extends in a layer shape along the first main surface 3 and is electrically connected to the drain region 10 inside the chip 2.
  • the drift region 11 is formed throughout the active region 8.
  • the drift region 11 is extended from the active region 8 to the peripheral region 9, and has a portion in the peripheral region 9 that is located in the surface layer of the first main surface 3.
  • the drift region 11 extends from the active region 8 to the peripheral region 9 along the entire periphery. It is preferable that the drift region 11 is exposed from at least one of the first to fourth side surfaces 5A to 5D. In this embodiment, the drift region 11 is exposed from the entire periphery of the first to fourth side surfaces 5A to 5D.
  • the drift region 11 is formed in the second semiconductor layer 7.
  • the drift region 11 is formed over the entire thickness range between the upper end (drain region 10) of the first semiconductor layer 6 and the upper end (first main surface 3) of the second semiconductor layer 7, and is connected to the first semiconductor layer 6 (drain region 10).
  • the drift region 11 is formed using the n-type second semiconductor layer 7, and has a thickness corresponding to the thickness of the second semiconductor layer 7.
  • the drift region 11 may also be formed by introducing n-type impurities into the surface layer of the first main surface 3 of the chip 2 (second semiconductor layer 7).
  • the semiconductor device 1A includes a plurality of body structures 12 formed in the surface layer of the first main surface 3 in the active region 8.
  • the body structures 12 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the body structures 12 are arranged in stripes extending in the second direction Y. Furthermore, the extension direction of the body structures 12 coincides with the off-direction of the SiC single crystal.
  • FIG. 10A is an enlarged cross-sectional view showing a body structure 12 according to a first embodiment.
  • the body structure 12 includes a p-type body region 13 formed in a surface layer portion of the first main surface 3.
  • the body region 13 is formed in the surface layer of the drift region 11 as the main body of the body structure 12.
  • a plurality of body regions 13 are arranged at intervals in the first direction X, and are each formed in a strip extending in the second direction Y.
  • a source potential is applied to the body region 13 as a low potential (second potential) different from a high potential (first potential).
  • the body region 13 forms a pn junction with the drift region 11, and expands a depletion layer in the drift region 11 when a reverse bias voltage is applied.
  • the body region 13 has an upper end on the first main surface 3 side and a lower end on the bottom side of the drift region 11.
  • the lower end of the body region 13 is the bottom of the body region 13.
  • the upper end of the body region 13 is exposed from the first main surface 3.
  • the lower end of the body region 13 is formed at a distance from the bottom of the drift region 11 towards the first main surface 3, and faces the drain region 10 across a part of the drift region 11. It is preferable that the lower end of the body region 13 is formed at a distance from the middle of the drift region 11 towards the first main surface 3.
  • the body region 13 may cross the depth position of the middle part of the drift region 11 in the thickness direction.
  • the body regions 13 each have a body width WB in the horizontal direction (first direction X in this embodiment).
  • the maximum value of the body width WB may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the maximum value of the body width WB may have a value belonging to at least one of the following ranges: 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 7 ⁇ m or less, 7 ⁇ m or more and 8 ⁇ m or less, 8 ⁇ m or more and 9 ⁇ m or less, and 9 ⁇ m or more and 10 ⁇ m or less.
  • the maximum value of the body width WB is preferably 2 ⁇ m or more and 5 ⁇ m or less.
  • the body region 13 may have a body thickness TB of 0.1 ⁇ m or more and 2.5 ⁇ m or less in the vertical direction Z.
  • the body thickness TB is also the depth of the body region 13.
  • the body thickness TB may have a value belonging to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, and 2.25 ⁇ m or more and 2.5 ⁇ m or less.
  • the body thickness TB is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the body region 13 is formed in a tapered shape on the surface layer of the drift region 11 so that the body width WB decreases in the thickness direction, and has a peripheral portion that is inclined obliquely with respect to the first main surface 3.
  • the peripheral portion of the body region 13 is inclined obliquely toward the center of the lower end portion of the body region 13.
  • the body width WB does not necessarily have to decrease monotonically in the thickness direction, and may gradually increase or decrease.
  • the term “inclined diagonally” therefore includes a configuration in which a straight line (diagonal line) connecting two points of the peripheral portion in a specified thickness range in cross-sectional view is inclined with respect to the first main surface 3.
  • the specified thickness range may be a thickness range of 1 ⁇ 4 or more, 1 ⁇ 3 or more, or 1 ⁇ 2 or more of the body thickness TB.
  • the specified thickness range may be the body thickness TB.
  • the term “inclined diagonally” includes a configuration in which a straight line connecting the upper end of the peripheral portion and the lower end of the peripheral portion in cross-sectional view is inclined with respect to the first main surface 3.
  • the horizontal distance between two points of the periphery in a given thickness range is defined as the body gradient GB.
  • the body gradient GB in a given thickness range may be 0.05 ⁇ m or more and 0.5 ⁇ m or less.
  • the body gradient GB may have a value that belongs to at least one of the following ranges: 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.2 ⁇ m or less, 0.2 ⁇ m or more and 0.3 ⁇ m or less, 0.3 ⁇ m or more and 0.4 ⁇ m or less, and 0.4 ⁇ m or more and 0.5 ⁇ m or less.
  • the inclination angle formed by a straight line (diagonal line) connecting two points on the periphery with a vertical line may be 5° or more and 45° or less.
  • the inclination angle may have a value belonging to at least one of the ranges of 5° or more and 10° or less, 10° or more and 15° or less, 15° or more and 20° or less, 20° or more and 25° or less, 25° or more and 30° or less, 30° or more and 35° or less, 35° or more and 40° or less, and 40° or more and 45° or less.
  • the inclination angle is preferably 10° or more and 30° or less. It is particularly preferable that the inclination angle be 15° or more and 25° or less.
  • the body region 13 is formed such that the body width WB decreases in the thickness direction starting from the upper end.
  • the peripheral portion of the body region 13 is inclined obliquely from the upper end toward the lower end. It is preferable that the body width WB decreases at least from the upper end to the middle portion. In other words, it is preferable that the peripheral portion of the body region 13 is inclined obliquely at least from the upper end to the middle portion.
  • the body width WB decreases from the upper end side toward the lower end side throughout the entire thickness range between the upper end and the lower end.
  • the periphery of the body region 13 is inclined obliquely from the upper end side toward the lower end side throughout the entire thickness range between the upper end and the lower end.
  • the body region 13 may have a maximum value of the body width WB at the upper end or a region on the upper end side (e.g., within a 10% thickness range from the upper end).
  • the body region 13 may have a minimum value of the body width WB at the lower end or a region on the lower end side (e.g., within a 10% thickness range from the lower end).
  • the peripheral portion is connected to the lower end in an arc shape (circular arc shape) in a cross-sectional view.
  • the body region 13 has an edge portion that connects the peripheral portion and the lower end in an arc shape (circular arc shape).
  • the periphery of the body region 13 When the upper end of the periphery of the body region 13 is taken as the reference position (0 ⁇ m point), the periphery of the body region 13 is inclined obliquely with respect to the first main surface 3 in a thickness range of 0.5 ⁇ m from the first main surface 3. In other words, the body region 13 does not extend in a direction perpendicular to the first main surface 3 in the thickness range of 0.5 ⁇ m. In other words, the portion of the periphery of the body region 13 located at the 0.5 ⁇ m point is located inside the body region 13 from the upper end of the periphery, and does not overlap with the upper end in the vertical direction Z.
  • the peripheral portion of the body region 13 has a body gradient GB of 0.05 ⁇ m or more and 0.25 ⁇ m or less in thickness range of 0.5 ⁇ m.
  • the body gradient GB in the thickness range of 0.5 ⁇ m is the horizontal change in the peripheral portion at a thickness point of 0.5 ⁇ m when the upper end of the peripheral portion is set as the reference position.
  • Figure 10A illustrates an example of a body gradient GB in a thickness range of 0.5 ⁇ m.
  • the body gradient GB in the 0.5 ⁇ m thickness range may have a value that belongs to at least one of the following ranges: 0.05 ⁇ m to 0.1 ⁇ m, 0.1 ⁇ m to 0.15 ⁇ m, 0.15 ⁇ m to 0.2 ⁇ m, and 0.2 ⁇ m to 0.25 ⁇ m.
  • the body gradient GB is preferably 0.1 ⁇ m to 0.2 ⁇ m. It is particularly preferable that the body gradient GB in the 0.5 ⁇ m thickness range is greater than 0.1 ⁇ m and less than 0.15 ⁇ m.
  • the peripheral portion of the body region 13 has a sub-inclined portion 14 on the upper end side and a main inclined portion 15 on the lower end side.
  • the sub-inclined portion 14 may be referred to as the "first inclined portion” or “upper inclined portion”
  • the main inclined portion 15 may be referred to as the "second inclined portion” or “lower inclined portion”.
  • the sub-inclined portion 14 is formed in a region closer to the first main surface 3 than the middle portion of the body region 13.
  • the sub-inclined portion 14 forms the surface portion of the body region 13 and is exposed from the first main surface 3.
  • the sub-inclined portion 14 is composed of a protruding portion that protrudes horizontally from the periphery along the first main surface 3 at the upper end of the body region 13.
  • the sub-inclined portion 14 is formed by a portion of the body region 13 where the body width WB decreases monotonically, and is inclined obliquely relative to the first main surface 3.
  • the sub-inclined portion 14 protrudes in an arc shape (circular arc shape).
  • the sub-inclined portion 14 has a relatively gentle first inclination angle relative to the first main surface 3.
  • the sub-inclined portion 14 prevents a relatively narrow body width WB from being formed at the upper end of the body region 13, and prevents the upper end of the peripheral portion from recessing inward into the body region 13. In other words, the sub-inclined portion 14 prevents the formation of a short channel portion at the upper end of the body region 13.
  • the sub-inclined portion 14 may have a width (protruding width) in the horizontal direction of 0.01 ⁇ m or more and 0.25 ⁇ m or less.
  • the width of the sub-inclined portion 14 is the horizontal width based on a vertical line that passes through the lower end of the sub-inclined portion 14 in the vertical direction Z.
  • the width of the sub-inclined portion 14 decreases monotonically in the thickness direction.
  • the width of the sub-inclined portion 14 may have a value that falls within at least one of the following ranges: 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.15 ⁇ m or less, 0.15 ⁇ m or more and 0.2 ⁇ m or less, and 0.2 ⁇ m or more and 0.25 ⁇ m or less.
  • the width of the sub-inclined portion 14 is 0.15 ⁇ m or less.
  • the sub-inclined portion 14 may have a thickness in the vertical direction Z of 0.01 ⁇ m or more and 0.25 ⁇ m or less.
  • the thickness of the protruding portion may have a value that belongs to at least one of the ranges of 0.01 ⁇ m or more and 0.05 ⁇ m or less, 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.15 ⁇ m or less, 0.15 ⁇ m or more and 0.2 ⁇ m or less, and 0.2 ⁇ m or more and 0.25 ⁇ m or less.
  • the thickness of the sub-inclined portion 14 is 0.15 ⁇ m or less.
  • the main inclined portion 15 is formed in a region on the lower end side of the sub-inclined portion 14.
  • the main inclined portion 15 has a thickness greater than that of the sub-inclined portion 14, and forms the main part of the body region 13.
  • the main inclined portion 15 forms a body gradient GB together with the sub-inclined portion 14.
  • the main inclined portion 15 forms a body gradient GB in a thickness range of 0.5 ⁇ m together with the sub-inclined portion 14.
  • the main inclined portion 15 is formed by a portion of the body region 13 where the body width WB decreases almost monotonically, and is inclined in an oblique direction with respect to the first main surface 3.
  • the main inclined portion 15 is located on the inner side of the body region 13 with respect to the sub-inclined portion 14, and has a second inclination angle with respect to the first main surface 3 that is steeper than the first inclination angle of the sub-inclined portion 14.
  • the second inclination angle has a value larger than the first inclination angle.
  • the second inclination angle has a value smaller than the first inclination angle.
  • the body structure 12 includes a plurality of n-type source regions 16, 17 formed in a surface layer portion of the body region 13.
  • a source potential is applied to the plurality of source regions 16, 17.
  • the plurality of source regions 16, 17 include a first source region 16 located on one side in the first direction X (the third side surface 5C side) and a second source region 17 located on the other side in the first direction X (the fourth side surface 5D side).
  • one first source region 16 is formed on one end side of the body region 13
  • one second source region 17 is formed on the other end side of the body region 13.
  • the first source region 16 is formed at a distance from one end to the other end of the body region 13.
  • the second source region 17 is formed at a distance from the first source region 16 to the other end of the body region 13.
  • the second source region 17 is formed at a distance from the other end to one end of the body region 13.
  • the configuration of one of the source regions 16, 17 will be specifically described below.
  • the source regions 16, 17 extend in a strip shape along the extension direction of the body region 13.
  • the source regions 16, 17 are formed spaced apart inward from both ends of the body region 13 in the second direction Y. In other words, the source regions 16, 17 expose both ends of the body region 13 from the first main surface 3 (see FIG. 5).
  • the source regions 16 and 17 are formed at a distance from the lower end of the body region 13 toward the first main surface 3, and face the drift region 11 across a portion of the body region 13. Specifically, the source regions 16 and 17 have a thickness that crosses the depth position of the sub-inclined portion 14 in the thickness direction.
  • the source regions 16 and 17 are formed at intervals inward from the sub-inclined portion 14 and have a portion that faces the sub-inclined portion 14 in the horizontal direction.
  • the source regions 16 and 17 are formed at intervals inward from the main inclined portion 15 and have a portion that faces the main inclined portion 15 in the horizontal direction.
  • the middle parts of the source regions 16, 17 are located closer to the main inclined portion 15 than the depth position of the sub-inclined portion 14, and face the main inclined portion 15 in the horizontal direction. In the horizontal direction, the distance between the source regions 16, 17 and the main inclined portion 15 is smaller than the distance between the source regions 16, 17 and the sub-inclined portion 14.
  • the source regions 16 and 17 have peripheral portions that protrude in an arc shape (circular arc shape) toward the peripheral portion of the body region 13.
  • the tips of the source regions 16 and 17 may face the first main surface 3 through a part of the body region 13 in the thickness direction.
  • the peripheral portions of the source regions 16 and 17 may have tips that are exposed from the first main surface 3 in the thickness direction without passing through the body region 13.
  • the peripheral portions of the source regions 16 and 17 may be inclined downward in a straight or curved manner from the first main surface 3 toward the inside of the lower end of the body region 13.
  • the peripheral portions of the source regions 16 and 17 may extend almost perpendicular to the first main surface 3.
  • each first source region 16 may be formed at intervals in the extension direction of the body region 13. In this case, each first source region 16 may be formed in a strip shape extending in the second direction Y.
  • the multiple second source regions 17 may be formed at intervals in the extension direction of the body region 13. In this case, each second source region 17 may be formed in a strip shape extending in the second direction Y.
  • the body structure 12 includes a number of p-type contact regions 18 formed in a region different from the source regions 16, 17 in the surface layer portion of the body region 13.
  • the contact regions 18 may be referred to as "back gate regions.”
  • a source potential is applied to the multiple contact regions 18.
  • one contact region 18 is interposed in the region between the first source region 16 and the second source region 17 in the surface layer portion of the body region 13, and is electrically connected to the body region 13.
  • the contact region 18 extends in a band shape along the extension direction of the body region 13 (source regions 16, 17).
  • the contact region 18 is formed spaced inward from both ends of the body region 13 in the second direction Y. In other words, the contact region 18 exposes both ends of the body region 13 from the first main surface 3 (see FIG. 5).
  • the contact region 18 has a width smaller than the width of the source regions 16, 17.
  • the width of the contact region 18 may be larger than the width of the source regions 16, 17.
  • the contact region 18 is formed at a distance from the lower end of the body region 13 toward the first main surface 3, and faces the drift region 11 across a part of the body region 13.
  • the contact region 18 has a thickness that crosses the depth position of the sub-inclined portion 14 in the thickness direction.
  • the contact region 18 has a portion that faces the sub-inclined portion 14 in the horizontal direction via the source regions 16, 17, and a portion that faces the main inclined portion 15 in the horizontal direction via the source regions 16, 17.
  • the middle portion of the contact region 18 is located closer to the main inclined portion 15 than the depth position of the sub-inclined portion 14, and faces the main inclined portion 15 in the horizontal direction.
  • the contact region 18 has a thickness greater than that of the source regions 16, 17, and has a bottom located closer to the lower end of the body region 13 than the bottoms of the source regions 16, 17. In other words, the bottom of the contact region 18 faces the main inclined portion 15 in the horizontal direction without passing through the source regions 16, 17.
  • the contact region 18 has a peripheral portion that protrudes in an arc shape (circular arc shape) toward the peripheral portion of the body region 13.
  • the tip of the contact region 18 may face the first main surface 3 via a part of the source regions 16, 17 in the thickness direction.
  • the peripheral portion of the contact region 18 may have a tip portion exposed from the first main surface 3 in the thickness direction without passing through the source regions 16, 17.
  • the peripheral portion of the contact region 18 may slope downward in a straight or curved manner from the first main surface 3 toward the inside of the lower end of the body region 13.
  • the peripheral portion of the contact region 18 may extend approximately perpendicular to the first main surface 3.
  • each contact region 18 may be formed at intervals in the extension direction of the body region 13.
  • each contact region 18 may be formed in a strip shape extending in the second direction Y.
  • the body structure 12 may have the configuration shown in Figures 10B to 10F.
  • Figure 10B is an enlarged cross-sectional view of the body structure 12 according to the second embodiment.
  • Figure 10C is an enlarged cross-sectional view of the body structure 12 according to the third embodiment.
  • Figure 10D is an enlarged cross-sectional view of the body structure 12 according to the fourth embodiment.
  • Figure 10E is an enlarged cross-sectional view of the body structure 12 according to the fifth embodiment.
  • Figure 10F is an enlarged cross-sectional view of the body structure 12 according to the sixth embodiment.
  • the body structure 12 according to the second embodiment has a configuration in which the configuration of the body region 13 according to the first embodiment is modified.
  • the body region 13 includes a main inclined portion 15 having undulations.
  • the main inclined portion 15 has multiple (at least two) bulge portions 19 that protrude horizontally in multiple stages in the thickness direction.
  • the multiple bulge portions 19 are regions where the rate of change (amount of reduction) of the body width WB changes in the thickness direction.
  • the multiple bulge portions 19 may protrude in an arc shape (circular arc shape).
  • the bulge portions 19 may be referred to as "protruding portions,” “protruding portions,” “curved portions,” “extending portions,” etc.
  • the body region 13 may include at least one or more bulges 19 formed by portions of the body region 13 where the body width WB decreases almost monotonically.
  • the body region 13 (main inclined portion 15) may include at least one or more bulges 19 formed by portions of the body region 13 where the body width WB increases or decreases gradually.
  • the multiple bulges 19 are formed starting from the lower end of the sub-inclined portion 14 and are set back inwardly of the body region 13 in sequence from the upper end side to the lower end side, forming undulations with repeated protrusions and recesses along the inclination direction.
  • the tip of the lower bulge 19 is positioned further inwardly of the body region 13 than the tip of the upper bulge 19.
  • the multiple bulges 19 may have different thicknesses. That is, the main inclined portion 15 may include one bulge 19 having a relatively small thickness (depth) and the other bulge 19 having a thickness (depth) greater than the first bulge 19. The other bulge 19 may be located closer to the upper end than the first bulge 19, or may be located closer to the lower end than the first bulge 19.
  • each bulge 19 may be 0.05 ⁇ m or more and 0.5 ⁇ m or less.
  • the thickness of each bulge 19 may have a value that falls within at least one of the following ranges: 0.05 ⁇ m or more and 0.1 ⁇ m or less, 0.1 ⁇ m or more and 0.2 ⁇ m or less, 0.2 ⁇ m or more and 0.3 ⁇ m or less, 0.3 ⁇ m or more and 0.4 ⁇ m or less, and 0.4 ⁇ m or more and 0.5 ⁇ m or less.
  • the multiple bulges 19 have a first bulge 19A, a second bulge 19B, and a third bulge 19C formed in this order from the upper end side to the lower end side.
  • the first bulge 19A is formed directly below the sub-inclined portion 14.
  • the first bulge 19A is formed by a portion of the body region 13 where the body width WB decreases almost monotonically, and has an end that is set back inward of the body region 13 with respect to the tip of the sub-inclined portion 14.
  • the end of the first bulge 19A does not face the sub-inclined portion 14 in the thickness direction.
  • the first bulge 19A may be formed by a portion where the body width WB gradually increases and decreases, and may face the sub-inclined portion 14 in the thickness direction.
  • the first bulge 19A has a first thickness that is greater than the thickness of the sub-inclined portion 14.
  • the first thickness may be less than the thickness of the sub-inclined portion 14.
  • the second bulge portion 19B is formed directly below the first bulge portion 19A.
  • the second bulge portion 19B is formed by a portion of the body region 13 where the body width WB decreases almost monotonically, and has an end portion that is set back toward the inside of the body region 13 relative to the end portion of the first bulge portion 19A. In this form, the second bulge portion 19B does not face the first bulge portion 19A in the thickness direction.
  • the second bulge portion 19B may be formed by a portion where the body width WB gradually increases and decreases, and may face the first bulge portion 19A in the thickness direction.
  • the first bulge portion 19A has a second thickness that is less than the first thickness of the first bulge portion 19A.
  • the second thickness may be greater than the first thickness.
  • the third bulge portion 19C is formed directly below the second bulge portion 19B.
  • the third bulge portion 19C is formed by a portion of the body region 13 where the body width WB decreases almost monotonically, and has an end portion that is set back toward the inside of the body region 13 relative to the end portion of the second bulge portion 19B. In this form, the third bulge portion 19C does not face the second bulge portion 19B in the thickness direction.
  • the third bulge portion 19C may be formed by a portion where the body width WB gradually increases and decreases, and may face the second bulge portion 19B in the thickness direction.
  • the third bulge portion 19C forms an edge portion of the body region 13, and is connected to the lower end portion of the body region 13 in an arc shape (circular arc shape).
  • the third bulge portion 19C has a third thickness that is greater than the second thickness of the second bulge portion 19B.
  • the third thickness may be less than the second thickness.
  • the third thickness may be greater than the first thickness or less than the first thickness.
  • the source regions 16, 17 are formed at a distance from the depth position of at least the lowest bulge 19 (i.e., the third bulge 19C) toward the first main surface 3, and face at least one bulge 19 in the horizontal direction.
  • the source regions 16, 17 are formed at a distance from the depth position of the second bulge 19B toward the first main surface 3.
  • the source regions 16 and 17 have a portion that faces the sub-inclined portion 14 in the horizontal direction and a portion that faces the first bulge portion 19A in the horizontal direction.
  • the source regions 16 and 17 may have a thickness that crosses the depth position of the second bulge portion 19B and have a portion that faces the second bulge portion 19B in the horizontal direction.
  • the contact region 18 is formed at a distance from the depth position of at least the lowest bulge 19 (i.e., the third bulge 19C) toward the first main surface 3, and faces at least one bulge 19 in the horizontal direction.
  • the contact region 18 is formed at a distance from the depth position of the second bulge 19B toward the first main surface 3.
  • the contact region 18 has a portion facing the sub-inclined portion 14 across the source regions 16, 17 in the horizontal direction, and a portion facing the first bulge portion 19A across the source regions 16, 17 in the horizontal direction.
  • the contact region 18 may have a thickness that crosses the depth position of the second bulge portion 19B and a portion facing the second bulge portion 19B in the horizontal direction.
  • the body structure 12 according to the third embodiment has multiple bulges 19, similar to the body region 13 according to the second embodiment.
  • the multiple bulges 19 have a first bulge 19A and a second bulge 19B formed in this order from the upper end side to the lower end side.
  • the first bulge 19A is formed directly below the sub-inclined portion 14.
  • the first bulge 19A is formed by a portion of the body region 13 where the body width WB decreases almost monotonically, and has an end portion that is set back toward the inside of the body region 13 relative to the tip end of the sub-inclined portion 14.
  • the first bulge 19A has a first thickness that is greater than the thickness of the sub-inclined portion 14. Of course, the first thickness may be less than the thickness of the sub-inclined portion 14.
  • the second bulge portion 19B is formed directly below the first bulge portion 19A.
  • the second bulge portion 19B is formed by a portion of the body region 13 where the body width WB gradually increases and decreases, and has an end portion that is set back toward the inside of the body region 13 relative to the end portion of the first bulge portion 19A.
  • the second bulge portion 19B forms an edge portion of the body region 13, and is connected to the lower end portion of the body region 13 in an arc shape (circular arc shape).
  • the second bulge portion 19B has a second thickness that is greater than the thickness of the sub-inclined portion 14. The second thickness may be greater than the first thickness or less than the first thickness.
  • the second bulge portion 19B forms a recessed portion 20A that is recessed horizontally toward the inside of the body region 13 at the boundary (connection) with the first bulge portion 19A, and faces the first bulge portion 19A in the thickness direction across the recessed portion 20A.
  • the recessed portion 20A has an end that is recessed toward the inside of the body region 13 relative to the vertical line.
  • a configuration in which the recessed portion 20A is eliminated corresponds to the body region 13 according to the second embodiment.
  • the source regions 16, 17 are preferably formed at least at a distance from the depth position of the recess 20A toward the first main surface 3, and face at least one bulge 19 in the horizontal direction.
  • the source regions 16, 17 are formed at a distance from the depth position of the end of the recess 20A toward the first main surface 3.
  • the source regions 16, 17 have a portion that faces the sub-inclined portion 14 in the horizontal direction, and a portion that faces the first bulge 19A in the horizontal direction.
  • the source regions 16, 17 do not have a portion that faces the recess 20A (second bulge 19B) in the horizontal direction.
  • the contact region 18 is preferably formed at a distance from at least the depth position of the recessed portion 20A toward the first main surface 3, and faces at least one bulge 19 across the source regions 16, 17 in the horizontal direction. In this embodiment, the contact region 18 is formed at a distance from the depth position of the end of the recessed portion 20A toward the first main surface 3.
  • the contact region 18 has a portion facing the sub-inclined portion 14 across the source regions 16, 17 in the horizontal direction, and a portion facing the first bulge portion 19A across the source regions 16, 17 in the horizontal direction.
  • the contact region 18 does not have a portion facing the recess portion 20A (second bulge portion 19B) in the horizontal direction.
  • the body structure 12 according to the fourth embodiment has a configuration in which the first bulge portion 19A is modified in the body region 13 according to the third embodiment.
  • the first bulge portion 19A is formed by a portion of the body region 13 where the body width WB gradually increases and decreases, and has an end portion that is set back toward the inside of the body region 13 relative to the tip end of the sub-inclined portion 14.
  • the end portion of the first bulge portion 19A faces the sub-inclined portion 14 in the thickness direction.
  • the first bulge portion 19A has a first thickness that is greater than the thickness of the sub-inclined portion 14. Of course, the first thickness may be less than the thickness of the sub-inclined portion 14.
  • First bulge 19A forms a horizontally recessed recess 20B toward the inside of body region 13 at the boundary (connection) with sub-inclined portion 14, and faces sub-inclined portion 14 across recess 20B.
  • recess 20B has an end recessed inward of body region 13 from the vertical line.
  • the end of recess 20B is positioned closer to sub-inclined portion 14 than the end of recess 20A in the horizontal direction.
  • a configuration in which recess 20A and recess 20B are eliminated corresponds to body region 13 according to the second embodiment.
  • the source regions 16, 17 have a portion facing the sub-inclined portion 14 in the horizontal direction, and a portion facing the first bulge portion 19A in the horizontal direction. In this embodiment, the source regions 16, 17 face the recessed portion 20B in the horizontal direction.
  • the contact region 18 has a portion facing the sub-inclined portion 14 across the source regions 16, 17 in the horizontal direction, and a portion facing the first bulge portion 19A across the source regions 16, 17 in the horizontal direction. In this embodiment, the contact region 18 faces the recessed portion 20B across the source regions 16, 17 in the horizontal direction.
  • the body structure 12 according to the fifth embodiment has a configuration in which the sub-inclined portion 14 of the body region 13 according to the first embodiment has been modified.
  • the sub-inclined portion 14 is formed by a portion of the body region 13 in which the body width WB decreases almost monotonically, and does not protrude horizontally but is inclined obliquely from the first main surface 3 at a first inclination angle. Even in this configuration, the sub-inclined portion 14 suppresses the formation of a short channel portion at the upper end of the body region 13.
  • the main inclined portion 15 has a second inclination angle that is approximately equal to the first inclination angle, and has a portion that is continuously inclined from the sub inclined portion 14 in an oblique direction along the inclination direction of the sub inclined portion 14.
  • the sub inclined portion 14 of the fifth embodiment is also applicable to the body structures 12 of the first to fourth embodiments.
  • the body structure 12 includes a narrowing portion 21 that forms a short channel portion instead of the sub-inclined portion 14.
  • the narrowing portion 21 is formed at the upper end of the body region 13 by a portion of the body region 13 where the body width WB increases (gradually increases) in the thickness direction.
  • the narrowing portion 21 has a portion that is obliquely inclined with respect to the first main surface 3 in the surface layer portion of the drift region 11, and faces the first main surface 3 across a part of the drift region 11.
  • the main inclined portion 15 is formed by the portion where the body width WB decreases from the tip of the narrowed portion 21, and is inclined in an oblique direction with respect to the first main surface 3.
  • the aforementioned body gradient GB is applied to the main inclined portion 15 with the tip of the narrowed portion 21 as the reference position (0 ⁇ m point).
  • the source regions 16, 17 are formed in the surface layer of the body region 13 at a distance from the base end of the narrowed portion 21.
  • the source regions 16, 17 form a relatively narrow short channel portion between the narrowed portion 21 and the source regions 16, 17, and form a relatively wide channel portion between the main slope portion 15 and the source regions 16, 17.
  • the body structure 12 according to the sixth embodiment may be adopted.
  • the narrowed portion 21 according to the sixth embodiment is also applicable to the body structures 12 according to the first to fifth embodiments.
  • a configuration having a sub-inclined portion 14 is assumed, but the sub-inclined portion 14 can be replaced with the narrowed portion 21.
  • a specific configuration in this case can be obtained by replacing "sub-inclined portion 14" with "narrowed portion 21" as necessary in the following description.
  • FIG. 11A is a graph showing the concentration gradient in the first region of the body structure 12.
  • the first region of the body structure 12 is a region in the body region 13 in the second direction Y where neither the source regions 16, 17 nor the contact region 18 are formed.
  • the second region of the body structure 12 is both ends of the body region 13 in the second direction Y (see also FIG. 5).
  • the vertical axis indicates the impurity concentration
  • the horizontal axis indicates the body width WB.
  • FIG. 11A shows an example where the body width WB is 2.6 ⁇ m.
  • FIG. 11A shows a first concentration distribution A1 (thin line), a second concentration distribution A2 (thin dashed line), a third concentration distribution A3 (thick line), and a fourth concentration distribution A4 (thick dashed line).
  • the first concentration distribution A1 shows the horizontal concentration distribution at a thickness position of 0.15 ⁇ m in the body region 13 (see FIG. 10A).
  • the second concentration distribution A2 shows the horizontal concentration distribution at a thickness position of 0.30 ⁇ m in the body region 13 (see FIG. 10A).
  • the third concentration distribution A3 shows the horizontal concentration distribution at a thickness position of 0.45 ⁇ m in the body region 13 (see FIG. 10A).
  • the fourth concentration distribution A4 shows the horizontal concentration distribution at a thickness position of 0.60 ⁇ m in the body region 13 (see FIG. 10A). In this example, the middle part of the body region 13 is at a thickness position of 0.35 ⁇ m.
  • the first to fourth concentration distributions A1 to A4 show the n-type impurity concentration in the drift region 11 and the p-type impurity concentration in the body region 13.
  • the n-type impurity concentration of drift region 11 may be 1 ⁇ 10 16 cm -3 or more and 5 ⁇ 10 17 cm -3 or less.
  • the body region 13 has a p-type impurity concentration higher than the n-type impurity concentration of drift region 11.
  • the p-type impurity concentration of body region 13 may be 1 ⁇ 10 17 cm -3 or more and 1 ⁇ 10 19 cm -3 or less.
  • the body region 13 preferably contains aluminum as a trivalent element.
  • the body region 13 has a first concentration gradient portion 22 (see the upward arrow portion) and a second concentration gradient portion 23 (see the downward arrow portion) in the thickness direction.
  • the first concentration gradient portion 22 is a region where the p-type impurity concentration gradually increases from the upper end to the middle portion.
  • the second concentration gradient portion 23 is a region where the p-type impurity concentration gradually decreases from the first concentration gradient portion 22 to the lower end.
  • the p-type impurity concentration at the lower end of the body region 13 is lower than the p-type impurity concentration at the upper end.
  • the p-type impurity concentration at the body region 13 in the thickness range greater than 0.15 ⁇ m and equal to or less than 0.60 ⁇ m is higher than the p-type impurity concentration at the upper end in the thickness range equal to or less than 0.15 ⁇ m.
  • the body region 13 has a concentration gradient that gradually decreases from the inner side toward the peripheral edge side in the horizontal direction. Specifically, the body region 13 includes a first high concentration region 24, a low concentration region 25, and a second high concentration region 26 in the horizontal direction.
  • the first high concentration region 24 is formed in the inner part of the body region 13.
  • the first high concentration region 24 forms a convex concentration gradient that curves upward (positive direction), and includes a first maximum value P1 of the p-type impurity concentration.
  • the first high concentration region 24 has a concentration gradient in which the p-type impurity concentration gradually increases and decreases in the thickness direction, following the first concentration gradient section 22 and the second concentration gradient section 23.
  • the first high concentration region 24 has a concentration gradient that gradually increases (monotonically increases) in the region above the intermediate portion and gradually decreases (monotonically decreases) in the region below the intermediate portion.
  • the first high concentration region 24 forms a convex concentration gradient that includes the first maximum value P1 in both the region above the intermediate portion and the region below the intermediate portion.
  • the first high concentration region 24 preferably occupies an area of 1/10 to 1/2 of the body region 13 in the horizontal direction.
  • the area occupied by the first high concentration region 24 may be 1/5 or more.
  • the area occupied by the first high concentration region 24 is preferably 1/4 or more.
  • the low concentration region 25 is formed in a region closer to the peripheral edge of the body region 13 than the first high concentration region 24, and forms a concentration gradient that gradually decreases from the first high concentration region 24.
  • the low concentration region 25 is a region having a p-type impurity concentration lower than the p-type impurity concentration of the first high concentration region 24. Specifically, the p-type impurity concentration of the low concentration region 25 is lower than the first maximum value P1.
  • the low concentration region 25 forms a concave concentration gradient that curves downward (in the negative direction) in the surface portion of the body region 13, and includes a minimum value P2 of the p-type impurity concentration (see the first concentration distribution A1).
  • the low concentration region 25 has a concentration gradient in which the p-type impurity concentration gradually increases and decreases in the thickness direction, following the first concentration gradient section 22 and the second concentration gradient section 23.
  • the low concentration region 25 has a concentration gradient in which the p-type impurity concentration gradually increases (monotonically increases) in the region toward the upper end from the intermediate section, and gradually decreases (monotonically decreases) in the thickness direction in the region toward the lower end from the intermediate section.
  • the low-concentration region 25 has a concave concentration gradient including a minimum value P2 in the region on the upper end side of the intermediate portion (see first concentration distribution A1).
  • the low-concentration region 25 forms a gradual region in the region on the lower end side of the intermediate portion that has a concentration decrease rate that is smaller than the concentration decrease rate in the region on the upper end side, and does not have a concave concentration gradient (minimum value P2).
  • the concentration difference between the first high concentration region 24 and the low concentration region 25 gradually decreases toward the lower end of the body region 13. In other words, the concentration difference on the lower end side is less than the concentration difference on the upper end side.
  • the low concentration region 25 forms the main slope portion 15 and is electrically connected to the drift region 11.
  • the second high concentration region 26 is formed in the peripheral portion of the body region 13 (see the first concentration distribution A1).
  • the second high concentration region 26 is formed closer to the peripheral portion of the body region 13 than the low concentration region 25, and forms a concentration gradient that gradually increases from the low concentration region 25.
  • the second high concentration region 26 has a convex concentration gradient that includes a second maximum value P3 of the p-type impurity concentration.
  • the second maximum value P3 is greater than the minimum value P2.
  • the second maximum value P3 is greater than the first maximum value P1.
  • the second maximum value P3 may be less than the first maximum value P1.
  • the second high concentration region 26 is formed only on the peripheral portion of the body region 13 in the surface portion of the body region 13, and is not formed in the region on the lower end side of the body region 13. Specifically, the second high concentration region 26 forms the sub-inclined portion 14. In other words, the sub-inclined portion 14 is a region that includes the second high concentration region 26 and protrudes outward from the main inclined portion 15.
  • the second high concentration region 26 has a concentration gradient that gradually decreases in the thickness direction.
  • the concentration difference between the low concentration region 25 and the second high concentration region 26 gradually decreases from the sub-slope portion 14 toward the main slope portion 15, and becomes almost zero at the main slope portion 15.
  • the second high concentration region 26 forms almost the entire area of the sub-slope portion 14.
  • the second high concentration region 26 may partially form a part (upper portion) of the main slope portion 15.
  • the second high concentration region 26 may form only the sub-slope portion 14, and may not form the main slope portion 15.
  • the second high concentration region 26 is connected to the drift region 11 in a region that is closer to the upper end than the middle portion.
  • the body region 13 does not necessarily have to have the second high concentration region 26, and the low concentration region 25 may be formed at the upper end of the periphery of the body region 13. In other words, the sub-inclined portion 14 may be formed by the low concentration region 25.
  • FIG. 11B is a graph showing the concentration gradient in the second region of the body structure 12.
  • the second region of the body structure 12 is a region in the body region 13 in the second direction Y where both the source regions 16, 17 and the contact region 18 are formed.
  • the second region of the body structure 12 is the middle part of the body region 13 in the second direction Y.
  • the vertical axis indicates the impurity concentration
  • the horizontal axis indicates the body width WB.
  • FIG. 11B shows a first concentration distribution B1 (thin line), a second concentration distribution B2 (thin dashed line), a third concentration distribution B3 (thick line), and a fourth concentration distribution B4 (thick dashed line).
  • the first concentration distribution B1 has a concentration distribution in which the n-type impurity concentration of the source regions 16, 17 and the p-type impurity concentration of the contact region 18 are added to the first concentration distribution A1.
  • the second concentration distribution B2 has a concentration distribution in which the n-type impurity concentration on the bottom side of the source regions 16, 17 and the p-type impurity concentration on the bottom side of the contact region 18 are added to the second concentration distribution A2.
  • the third and fourth concentration distributions B3 and B4 correspond to the third and fourth concentration distributions A3 and A4, respectively.
  • the source regions 16 and 17 have a higher n-type impurity concentration than the drift region 11.
  • the n-type impurity concentration of the source regions 16 and 17 is higher than the p-type impurity concentration of the body region 13.
  • the n-type impurity concentration of the source regions 16 and 17 is higher than the p-type impurity concentration of the low concentration region 25 (minimum value P2).
  • the n-type impurity concentration of the source regions 16 and 17 is higher than the p-type impurity concentration of the first high concentration region 24 (first maximum value P1).
  • the n-type impurity concentration of the source regions 16 and 17 is higher than the p-type impurity concentration of the second high concentration region 26 (second maximum value P3).
  • the n-type impurity concentration of the source regions 16, 17 may be 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the source regions 16, 17 preferably contain phosphorus as a pentavalent element.
  • the source regions 16, 17 may have a thickness of 0.1 ⁇ m or more and 0.45 ⁇ m or less. The thickness of the source regions 16, 17 is preferably 0.35 ⁇ m or less.
  • the contact region 18 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the contact region 18 is higher than the p-type impurity concentration of the low concentration region 25 (minimum value P2).
  • the p-type impurity concentration of the contact region 18 is higher than the p-type impurity concentration of the first high concentration region 24 (first maximum value P1).
  • the p-type impurity concentration of the contact region 18 is higher than the p-type impurity concentration of the second high concentration region 26 (second maximum value P3).
  • the p-type impurity concentration of the contact region 18 is higher than the n-type impurity concentration of the source regions 16, 17.
  • the p-type impurity concentration of the contact region 18 may be lower than the n-type impurity concentration of the source regions 16, 17.
  • the p-type impurity concentration of the contact region 18 may be 1 ⁇ 10 19 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the contact region 18 preferably contains aluminum as a trivalent element.
  • the contact region 18 may have a thickness of 0.1 ⁇ m or more and 0.45 ⁇ m or less. The thickness of the contact region 18 is preferably 0.4 ⁇ m or less.
  • the source regions 16 and 17 are formed in the low concentration region 25 of the body region 13. Specifically, the source regions 16 and 17 are formed in the low concentration region 25 of the body region 13, shifted inward relative to the first high concentration region 24 and the second high concentration region 26 of the body region 13.
  • Both ends of the source regions 16, 17 may partially overlap the first high concentration region 24 and the second high concentration region 26.
  • both ends of the source regions 16, 17 may be spaced apart inward from the first high concentration region 24 and the second high concentration region 26.
  • the p-type impurity concentration of the low concentration region 25 is lower than in the case of the second concentration distribution A2 because the p-type impurity concentration of the low concentration region 25 is offset by the n-type impurity concentration on the bottom side of the source regions 16, 17.
  • the contact region 18 is formed in the first high concentration region 24 of the body region 13. Specifically, the contact region 18 is formed in the first high concentration region 24 of the body region 13, shifted inward with respect to the low concentration region 25 and the second high concentration region 26 of the body region 13. As a result, the p-type impurity concentration of the contact region 18 is increased by the first high concentration region 24.
  • the first high concentration region 24 enhances the ohmic properties of the contact region 18 with respect to the body region 13.
  • the p-type impurity concentration of the first high concentration region 24 is increased compared to the second concentration distribution A2 because the p-type impurity concentration on the bottom side of the contact region 18 is added to the p-type impurity concentration of the first high concentration region 24.
  • the body region 13 has a first high concentration region 24 in a thickness range below the contact region 18.
  • the first high concentration region 24 has a concentration gradient that gradually decreases in the thickness direction in the thickness range below the contact region 18.
  • the first high concentration region 24 has a concentration gradient that monotonically decreases from the bottom of the contact region 18 toward the lower end of the body region 13.
  • the concentration of the first high concentration region 24 on the lower end side of the body region 13 is less than the concentration of the first high concentration region 24 on the bottom side of the contact region 18.
  • the body region 13 has a low concentration region 25 in a region on the peripheral side of the body region 13 relative to the first high concentration region 24 in a thickness range below the contact region 18. Specifically, the body region 13 has a low concentration region 25 in a thickness range below the source regions 16 and 17.
  • the low concentration region 25 has a concentration gradient in which the impurity concentration gradually decreases in the thickness direction in the thickness range below the source regions 16, 17. Specifically, the low concentration region 25 has a concentration gradient that monotonically decreases from the bottom of the source regions 16, 17 (excluding the offset portion) toward the lower end of the body region 13. The concentration of the low concentration region 25 on the lower end side of the body region 13 is less than the concentration of the low concentration region 25 on the bottom side of the source regions 16, 17.
  • the concentration decrease rate of the low concentration region 25 is smaller than the concentration decrease rate of the high concentration region. Therefore, the concentration difference between the high concentration region and the low concentration region 25 gradually decreases toward the lower end of the body region 13. In other words, in the thickness range below the contact region 18, the concentration difference on the lower end side of the body region 13 is less than the concentration difference on the bottom side of the contact region 18.
  • the semiconductor device 1A includes a plurality of n-type surface drift regions 27 formed in the surface portion of the first main surface 3.
  • the plurality of surface drift regions 27 each consist of a portion of the drift region 11.
  • the plurality of surface drift regions 27 may have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 11, or may have an n-type impurity concentration lower than the n-type impurity concentration of the drift region 11.
  • the multiple surface drift regions 27 are each partitioned into regions between multiple body regions 13 adjacent in the first direction X in the surface portion of the drift region 11.
  • the multiple surface drift regions 27 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y.
  • the multiple surface drift regions 27 are also formed in a stripe shape extending in the second direction Y. The configuration of one surface drift region 27 is described below.
  • the surface drift region 27 has a drift width WD in the horizontal direction (first direction X in this embodiment) of 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the drift width WD is preferably less than the body width.
  • the drift width WD may be greater than the body width WB.
  • the drift width WD is preferably greater than 0.2 ⁇ m or more and 2 ⁇ m or less.
  • the drift width WD may have a value that falls within at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the surface drift region 27 is partitioned into regions between the body regions 13 so that the drift width WD increases in the thickness direction in accordance with the cross-sectional shape of the body regions 13.
  • the surface drift region 27 has a portion partitioned by the multiple bulges 19 (see Figures 10B to 10D).
  • the surface drift region 27 is formed such that the drift width WD increases in the thickness direction starting from the upper end of the body region 13. In other words, the drift width WD increases from the upper end side to the lower end side throughout the entire thickness range between the upper and lower ends of the body region 13.
  • the surface drift region 27 forms an n-type (pnp-type) JFET structure with the multiple body regions 13 located on both sides.
  • the surface drift region 27 forms a current path that spreads in the thickness direction in the region between the multiple body regions 13, reducing the current confinement effect.
  • the JFET resistance component of the JFET structure is reduced due to the cross-sectional shape of the peripheral parts of the multiple body regions 13 (i.e., the cross-sectional shape of the surface drift region 27).
  • the surface drift region 27 reduces the current density in the region between the multiple body regions 13, and alleviates the electric field concentration on the peripheral parts of the multiple body regions 13.
  • the semiconductor device 1A includes a plurality of p-type channel regions 28, 29 formed in a surface layer portion of the first main surface 3.
  • the plurality of channel regions 28, 29 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y.
  • the plurality of channel regions 28, 29 are also arranged in a stripe shape extending in the second direction Y.
  • the multiple channel regions 28, 29 are formed in the surface layer portion of the body region 13 due to the multiple source regions 16, 17.
  • the multiple channel regions 28, 29 include a first channel region 28 on one side in the first direction X and a second channel region 29 on the other side in the first direction X.
  • the first channel region 28 is formed in the surface layer portion of the body region 13 due to the first source region 16.
  • the second channel region 29 is formed in the surface layer portion of the body region 13 due to the second source region 17.
  • the channel regions 28, 29 are formed in the surface portion of the body region 13 in the region between the peripheral portion of the body region 13 (multiple surface drift regions 27) and the source regions 16, 17.
  • the channel regions 28, 29 have a portion formed along the sub-inclined portion 14 and a portion formed along the upper end of the main inclined portion 15.
  • the semiconductor device 1A includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8.
  • the plurality of gate structures 30 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y. Furthermore, the extension direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.
  • Each gate structure 30 covers the periphery of at least one body region 13. Specifically, each gate structure 30 covers at least one sub-tilt portion 14. Each gate structure 30 covers at least one periphery of the body region 13, at least one source region 16, 17, and one surface drift region 27 so as to be positioned above at least one channel region 28, 29.
  • each gate structure 30 is arranged across one surface drift region 27 to straddle the peripheral portions (sub-inclined portions 14) of two adjacent body regions 13, covering multiple channel regions 28, 29. Specifically, each gate structure 30 is arranged across the first source region 16 on one body region 13 side and the second source region 17 on the other body region 13 side, covering the first source region 16, the second source region 17, the surface drift region 27, the first channel region 28, and the second channel region 29.
  • Each gate structure 30 partially covers the first source region 16 with a gap between it and the contact region 18, and exposes a portion of the first source region 16 and the contact region 18 from the first main surface 3.
  • Each gate structure 30 partially covers the second source region 17 with a gap between it and the contact region 18, and exposes a portion of the second source region 17 and the contact region 18 from the first main surface 3.
  • the gate structure 30 has a laminated structure including an insulating film 31 and a gate electrode 32.
  • the insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 includes a silicon oxide film made of an oxide of the chip 2.
  • the insulating film 31 covers the first main surface 3 in a film-like shape.
  • the insulating film 31 covers the peripheral portion of at least one body region 13. Specifically, the insulating film 31 covers at least one sub-inclined portion 14.
  • the insulating film 31 faces the entire area of the sub-inclined portion 14 and the entire area of the main inclined portion 15 in the stacking direction (vertical direction Z).
  • the insulating film 31 covers the periphery of at least one body region 13, at least one source region 16, 17, and one surface drift region 27 so as to be positioned above at least one channel region 28, 29.
  • the insulating film 31 is disposed so as to straddle the periphery (sub-inclined portion 14) of two adjacent body regions 13 across one surface drift region 27, and covers multiple channel regions 28, 29.
  • the insulating film 31 is disposed so as to straddle the first source region 16 on one body region 13 side and the second source region 17 on the other body region 13 side, and covers the first source region 16, the second source region 17, the surface drift region 27, the first channel region 28, and the second channel region 29.
  • the insulating film 31 partially covers the first source region 16 at a distance from the contact region 18, and exposes a part of the first source region 16 and the contact region 18 from the first main surface 3.
  • the insulating film 31 partially covers the second source region 17 at a distance from the contact region 18, and exposes a part of the second source region 17 and the contact region 18 from the first main surface 3.
  • the insulating film 31 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.
  • the gate electrode 32 is disposed on the insulating film 31.
  • a gate potential is applied to the gate electrode 32 as a control potential.
  • the gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved.
  • the gate electrode 32 is formed in a band shape extending in the second direction Y. In this embodiment, the gate electrode 32 is formed spaced inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31.
  • the gate electrode 32 covers the peripheral portion of at least one body region 13 with the insulating film 31 in between. Specifically, the gate electrode 32 covers at least one sub-inclined portion 14 with the insulating film 31 in between.
  • the gate electrode 32 faces the entire area of the sub-inclined portion 14 and the entire area of the main inclined portion 15 with the insulating film 31 in between in the stacking direction (vertical direction Z).
  • the gate electrode 32 is disposed on the insulating film 31 so as to face at least one channel region 28, 29. Specifically, the gate electrode 32 covers the periphery of at least one body region 13, at least one source region 16, 17, and one surface drift region 27, with the insulating film 31 in between. In this embodiment, the gate electrode 32 is disposed so as to straddle the periphery (sub-inclined portion 14) of two adjacent body regions 13 across one surface drift region 27, and faces the multiple channel regions 28, 29 with the insulating film 31 in between.
  • the gate electrode 32 is disposed so as to straddle the first source region 16 on one body region 13 side and the second source region 17 on the other body region 13 side, and covers the first source region 16, the second source region 17, the surface drift region 27, the first channel region 28, and the second channel region 29 with the insulating film 31 in between.
  • the gate electrode 32 controls the inversion and non-inversion of the channel regions 28, 29 in response to the gate potential.
  • a gate potential is applied to the gate electrode 32, the channel regions 28, 29 are turned on, and a drain current flows between the drift region 11 and the source regions 16, 17 via the channel regions 28, 29 (body region 13).
  • a planar gate type transistor structure Tr including the drift region 11 is formed in the inner part (active region 8) of the chip 2.
  • semiconductor device 1A includes a p-type outer body region 35 formed in a surface layer portion of first main surface 3 in peripheral region 9. Outer body region 35 is formed in a surface layer portion of drift region 11. Outer body region 35 has a p-type impurity concentration higher than the n-type impurity concentration of drift region 11. The p-type impurity concentration of outer body region 35 may be not less than 1 ⁇ 10 17 cm ⁇ 3 and not more than 1 ⁇ 10 19 cm ⁇ 3 .
  • the outer body region 35 is preferably formed simultaneously with the body region 13 and has a p-type impurity concentration approximately equal to the p-type impurity concentration of the body region 13.
  • the outer body region 35 preferably has a concentration gradient similar to the concentration gradient of the body region 13.
  • the p-type impurity concentration of the outer body region 35 may be less than the p-type impurity concentration of the body region 13, or may be higher than the p-type impurity concentration of the body region 13.
  • the outer body region 35 is formed on the surface layer of the drift region 11 at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a band shape along the active region 8.
  • the outer body region 35 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the body regions 13 (active regions 8) from multiple directions.
  • the outer body region 35 collectively surrounds the multiple body regions 13 (active regions 8) in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the outer body region 35 forms the boundary between the active regions 8 and the peripheral region 9.
  • the outer body region 35 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the outer body region 35 is exposed from the first main surface 3.
  • the outer body region 35 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a portion of the drift region 11.
  • the outer body region 35 is preferably formed at a distance from the middle of the drift region 11 toward the first main surface 3.
  • the outer body region 35 may cross the depth position of the middle part of the drift region 11 in the thickness direction.
  • the outer body region 35 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the outer body region 35 is connected to the body regions 13 in a portion extending in the first direction X, and defines the body regions 13 and the surface drift regions 27 in the surface portion of the drift region 11.
  • the outer body region 35 is electrically connected to the multiple body regions 13. As a result, a source potential is applied to the outer body region 35 via the multiple body regions 13.
  • the outer body region 35 forms a pn junction with the drift region 11, and expands the depletion layer into the drift region 11 when a reverse bias voltage is applied.
  • the outer body region 35 is connected to the multiple body regions 13 at intervals in the second direction Y from the source regions 16, 17. Therefore, the outer body region 35 does not have the source regions 16, 17 in the surface layer portion. Also, the outer body region 35 is connected to the multiple body regions 13 at intervals in the second direction Y from the contact region 18. Therefore, the outer body region 35 does not have the contact region 18 in the surface layer portion.
  • the outer body region 35 has a width greater than the width of the body region 13.
  • the width of the outer body region 35 is the width in a direction perpendicular to the extension direction.
  • the width of the outer body region 35 may be approximately equal to the width of the body region 13, or may be less than the thickness of the body region 13.
  • the ratio of the width of the outer body region 35 to the width of the body region 13 may be 1 or more and 50 or less.
  • the width ratio may have a value that belongs to at least one of the following ranges: 1 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less. It is preferable that the width ratio is 10 or more. It is preferable that the width ratio is 20 or more and 40 or less.
  • the outer body region 35 has a thickness (depth) approximately equal to the thickness (depth) of the body region 13.
  • the thickness of the outer body region 35 may be less than the thickness of the body region 13, or may be greater than the thickness of the body region 13.
  • the semiconductor device 1A includes a p-type termination region 40 formed on the first main surface 3 in the peripheral region 9.
  • the termination region 40 may be referred to as a "well region", a “termination well region”, or the like.
  • the termination region 40 is formed in a surface layer portion of the drift region 11 in the peripheral region 9.
  • the p-type impurity concentration of the termination region 40 may be not less than 1 ⁇ 10 17 cm -3 and not more than 1 ⁇ 10 20 cm -3 .
  • the termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the termination region 40 may be higher than the p-type impurity concentration of the body region 13, or may be lower than the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the termination region 40 may be approximately equal to the p-type impurity concentration of the body region 13.
  • the termination region 40 may have a p-type impurity concentration different from the p-type impurity concentration of the outer body region 35.
  • the p-type impurity concentration of the termination region 40 may be higher than the p-type impurity concentration of the outer body region 35, or may be lower than the p-type impurity concentration of the outer body region 35.
  • the p-type impurity concentration of the termination region 40 may be approximately equal to the p-type impurity concentration of the outer body region 35.
  • the termination region 40 is spaced inward from the periphery of the first main surface 3 and is formed in the region between the periphery of the first main surface 3 and the outer body region 35.
  • the termination region 40 extends in a band shape along the outer body region 35 in a plan view.
  • the termination region 40 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the termination region 40 surrounds the outer body region 35 (the active region 8 and the body regions 13) in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the termination region 40 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the termination region 40 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a portion of the drift region 11.
  • the termination region 40 is preferably formed at a distance from the middle of the drift region 11 toward the first main surface 3. Of course, the termination region 40 may cross the depth position of the middle of the drift region 11 in the thickness direction.
  • the termination region 40 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 35.
  • the thickness of the termination region 40 may be greater than the thickness of the outer body region 35, or may be less than the thickness of the outer body region 35.
  • the termination region 40 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the termination region 40 is connected to the outer edge of the outer body region 35 at the surface portion of the drift region 11. This electrically connects the termination region 40 to the outer body region 35.
  • the termination region 40 is also electrically connected to the multiple body regions 13 via the outer body region 35.
  • the termination region 40 forms a pn junction with the drift region 11, and expands a depletion layer into the drift region 11 when a reverse bias voltage is applied.
  • the inner edge of the termination region 40 is connected to the outer edge of the outer body region 35 around the entire periphery.
  • the termination region 40 may be considered to be part of the outer body region 35 (the pull-out portion).
  • the termination region 40 (inner edge) has an overlap region 41 that overlaps the outer edge of the outer body region 35 in the surface portion of the drift region 11.
  • the overlap region 41 is a high-concentration region that includes the outer edge of the outer body region 35 and the inner edge of the termination region 40.
  • the overlap region 41 includes both the p-type impurities of the outer body region 35 and the p-type impurities of the termination region 40, and has a p-type impurity concentration that is higher than both the p-type impurity concentration of the outer body region 35 and the p-type impurity concentration of the termination region 40.
  • the p-type impurity concentration of the overlap region 41 is higher than the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the overlap region 41 may be lower than the p-type impurity concentration of the contact region 18.
  • the p-type impurity concentration of the overlap region 41 may be higher than the p-type impurity concentration of the contact region 18.
  • the overlap region 41 extends in a band shape along the outer body region 35 in a plan view.
  • the overlap region 41 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.
  • the overlap region 41 is defined in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the overlap region 41 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a planar view in an arc shape (preferably a quarter arc shape) (see FIG. 4). It is preferable that the width of the overlap region 41 is greater than the width of the body region 13. Of course, the width of the overlap region 41 may be less than the width of the body region 13.
  • the semiconductor device 1A may have a relatively high-concentration p-type well region (46) instead of the overlap region 41.
  • the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 35 and the p-type impurity concentration of the termination region 40.
  • the p-type impurity concentration of the well region (46) is higher than the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the well region (46) may be approximately equal to the p-type impurity concentration of the contact region 18.
  • the p-type impurity concentration of the well region (46) may be lower than the p-type impurity concentration of the contact region 18 or higher than the p-type impurity concentration of the contact region 18.
  • the well region (46) may be formed in either or both of the surface layer of the outer body region 35 and the surface layer of the termination region 40. Such a configuration is effective when the termination region 40 has a p-type impurity concentration approximately equal to the p-type impurity concentration of the outer body region 35 and is formed as part of the outer body region 35 (the pull-out portion).
  • the semiconductor device 1A includes at least one p-type field region 42 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the multiple field regions 42 may be formed in an electrically floating state.
  • the multiple field regions 42 may be fixed to the source potential.
  • the number of field regions 42 is arbitrary.
  • the number of field regions 42 may be 1 or more and 20 or less.
  • the number of field regions 42 may have a value that belongs to at least one of the following ranges: 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less.
  • the number of field regions 42 is typically 1 or more and 8 or less.
  • semiconductor device 1A includes three field regions 42.
  • the multiple field regions 42 are formed in the surface layer of the drift region 11.
  • the multiple field regions 42 are formed in the region between the periphery of the first main surface 3 and the multiple body regions 13 (active regions 8) at intervals inward from the periphery of the first main surface 3.
  • the multiple field regions 42 are formed in the region between the periphery of the first main surface 3 and the outer body region 35. More specifically, the multiple field regions 42 are arranged in the region between the periphery of the first main surface 3 and the termination region 40 at intervals from the outer edge of the termination region 40 toward the periphery of the first main surface 3.
  • the multiple field regions 42 are formed in a band shape extending along the multiple body regions 13 (termination regions 40) in a plan view.
  • the multiple field regions 42 each have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the multiple field regions 42 are formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) surrounding the multiple body regions 13 (termination regions 40) in a plan view.
  • the multiple field regions 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the multiple field regions 42 are formed at intervals from the depth position of the bottom of the drift region 11 toward the first main surface 3. It is preferable that the multiple field regions 42 are formed at intervals from the depth position of the middle part of the drift region 11 toward the first main surface 3. Of course, the multiple field regions 42 may cross the depth position of the middle part of the drift region 11 in the thickness direction.
  • the multiple field regions 42 each form a pn junction with the drift region 11, and expand the depletion layer toward the drift region 11 when a reverse bias voltage is applied.
  • the width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 42 are arbitrary and can take various values depending on the electric field to be relaxed.
  • the width of the multiple field regions 42 may be approximately constant or may be non-uniform.
  • the width of the multiple field regions 42 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the width of the multiple field regions 42 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the depth of the multiple field regions 42 may be approximately constant or may be non-uniform.
  • the depth of the multiple field regions 42 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the depth of the multiple field regions 42 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the multiple field regions 42 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion.
  • the shallow portion may be formed on the inner side, and the deep portion may be formed on the peripheral edge side.
  • the shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inner side.
  • the spacing between the multiple field regions 42 may be approximately constant or may be non-uniform.
  • the spacing between the multiple field regions 42 may gradually increase toward the peripheral edge of the first main surface 3.
  • the spacing between the multiple field regions 42 may gradually decrease toward the peripheral edge of the first main surface 3.
  • the p-type impurity concentration of the multiple field regions 42 may be approximately constant or may be non-uniform.
  • the p-type impurity concentration of the multiple field regions 42 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the p-type impurity concentration of the multiple field regions 42 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the multiple field regions 42 may be formed simultaneously with the body region 13 and have a p-type impurity concentration approximately equal to the p-type impurity concentration of the body region 13. In this case, the multiple field regions 42 may have a concentration gradient similar to the concentration gradient of the body region 13.
  • the p-type impurity concentration of the multiple field regions 42 may be higher than the p-type impurity concentration of the body region 13 (outer body region 35) or lower than the p-type impurity concentration of the body region 13 (outer body region 35).
  • the p-type impurity concentrations of the plurality of field regions 42 may be approximately equal to the p-type impurity concentration of the termination region 40.
  • the p-type impurity concentrations of the plurality of field regions 42 may be higher than the p-type impurity concentration of the termination region 40, or may be lower than the p-type impurity concentration of the termination region 40.
  • the p-type impurity concentrations of the plurality of field regions 42 may be not less than 1 ⁇ 10 17 cm ⁇ 3 and not more than 1 ⁇ 10 20 cm ⁇ 3 .
  • the semiconductor device 1A includes a peripheral insulating film 43 that covers the first main surface 3 in the peripheral region 9.
  • the peripheral insulating film 43 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the peripheral insulating film 43 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 43 includes a silicon oxide film made of an oxide of the chip 2.
  • the peripheral insulating film 43 is preferably made of the same type of insulating material as the insulating film 31.
  • the peripheral insulating film 43 preferably has a thickness approximately equal to that of the insulating film 31.
  • the peripheral insulating film 43 covers the first main surface 3 in the peripheral region 9 in the form of a film.
  • the peripheral insulating film 43 collectively covers the drift region 11, the outer body region 35, the termination region 40, and the multiple field regions 42.
  • the peripheral insulating film 43 is connected to the multiple insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 43 is formed integrally with the multiple insulating films 31, and forms a single insulating film together with the multiple insulating films 31.
  • the semiconductor device 1A includes a gate wiring 44 arranged on the first main surface 3 in the peripheral region 9.
  • the gate wiring 44 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 32.
  • the gate wiring 44 is connected to the multiple gate electrodes 32 and applies a gate signal to the multiple gate electrodes 32.
  • the gate wiring 44 may be referred to as a "second gate electrode" or the like.
  • the gate wiring 44 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the gate wiring 44 has the same conductivity type as the gate electrode 32.
  • the gate wiring 44 is arranged on the peripheral insulating film 43 at a distance from the periphery of the first main surface 3 toward the active region 8 in the peripheral region 9.
  • the gate wiring 44 is arranged at a distance from the termination region 40 toward the active region 8, and is arranged on a portion of the peripheral insulating film 43 that covers the outer body region 35.
  • the gate wiring 44 faces the outer body region 35 across the peripheral insulating film 43.
  • the gate wiring 44 may be arranged at a position facing the termination region 40 in the stacking direction.
  • the gate wiring 44 extends in a band shape along the body regions 13 (active regions 8) in a plan view.
  • the gate wiring 44 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the body regions 13 (active regions 8) from multiple directions.
  • the gate wiring 44 surrounds the body regions 13 (active regions 8) in a plan view and is divided into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the gate wiring 44 may be either ended or endless.
  • the gate wiring 44 extends in a strip shape (ring shape in this embodiment) along the outer body region 35 in a plan view, and faces the outer body region 35 across the outer insulating film 43 over the entire area in the stacking direction.
  • the gate wiring 44 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4).
  • the gate wiring 44 is formed narrower than the outer body region 35 in a plan view, and is disposed above the outer body region 35 at a distance from the inner and outer edges of the outer body region 35.
  • the multiple gate electrodes 32 are extended up to above the outer body region 35, and the gate wiring 44 is connected to the multiple gate electrodes 32 above the outer body region 35.
  • the thickness of the gate wiring 44 is preferably approximately equal to the thickness of the gate electrode 32.
  • the width of the gate wiring 44 is preferably greater than the width of the gate electrode 32.
  • the width of the gate wiring 44 is the width in a direction perpendicular to the extension direction.
  • the ratio of the width of the gate wiring 44 to the width of the gate electrode 32 may be 1 or more and 50 or less.
  • the width ratio may have a value belonging to at least one of the ranges of 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50.
  • the width ratio may be 5 or more.
  • the width ratio may be 20 to 40.
  • the width of the gate wiring 44 may be less than or equal to the width of the gate electrode 32.
  • the width of the gate wiring 44 may be greater than the width of the outer body region 35.
  • the semiconductor device 1A includes an insulating interlayer film 50 that covers the first main surface 3.
  • the interlayer film 50 may also be called an "interlayer insulating film,” “intermediate insulating film,” or the like.
  • the interlayer film 50 has an insulating surface 51 that extends along the first main surface 3.
  • the interlayer film 50 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.
  • the interlayer film 50 covers the multiple gate structures 30 in the active region 8. In the peripheral region 9, the interlayer film 50 collectively covers the drift region 11, the outer body region 35, the termination region 40, and the multiple field regions 42 with the peripheral insulating film 43 in between.
  • the interlayer film 50 covers the gate wiring 44 in the peripheral region 9.
  • the interlayer film 50 is continuous with the first to fourth side surfaces 5A to 5D.
  • the interlayer film 50 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose the peripheral portion of the first main surface 3 (drift region 11).
  • the interlayer film 50 has a layered structure including a first oxide film 52 (first insulating film) and a second oxide film 53 (second insulating film) that are layered in this order from the first main surface 3 side. That is, the interlayer film 50 has an insulating surface 51 formed by the second oxide film 53.
  • the first oxide film 52 has a single layer structure made of a silicon oxide film with no added impurities.
  • the first oxide film 52 may be referred to as an NSG film (Nondoped Silicate Glass film).
  • the first oxide film 52 has a thickness less than the thickness of the gate electrode 32. Of course, the thickness of the first oxide film 52 may be greater than the thickness of the gate electrode 32.
  • the first oxide film 52 collectively covers the active region 8 and the peripheral region 9.
  • the first oxide film 52 collectively covers the multiple gate structures 30 in the active region 8.
  • the first oxide film 52 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.
  • the first oxide film 52 has a portion that covers the insulating film 31 (first main surface 3) in a film-like manner along the horizontal direction.
  • the first oxide film 52 covers the insulating film 31 with a gap from the height position of the electrode surface (upper end) of the gate electrode 32 toward the insulating film 31.
  • the first oxide film 52 has a portion that extends in a film-like manner in the stacking direction along the sidewall of the gate electrode 32.
  • the first oxide film 52 has a portion that covers the electrode surface of the gate electrode 32 in a film-like manner along the horizontal direction.
  • the first oxide film 52 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner portion of the gate electrode 32.
  • the arc corner portion may have a center of curvature on the gate electrode 32 side.
  • the first oxide film 52 collectively covers the drift region 11, the outer body region 35, the termination region 40, and the multiple field regions 42 in the peripheral region 9, sandwiching the peripheral insulating film 43 therebetween.
  • the first oxide film 52 covers the gate wiring 44 in the peripheral region 9.
  • the first oxide film 52 has a portion that covers the peripheral insulating film 43 (first main surface 3) in a film-like manner along the horizontal direction.
  • the first oxide film 52 covers the peripheral insulating film 43 with a gap from the height position of the wiring surface (upper end) of the gate wiring 44 toward the peripheral insulating film 43.
  • the first oxide film 52 has a portion that extends in a film-like manner in the stacking direction along the sidewall of the gate wiring 44.
  • the first oxide film 52 has a portion that covers the wiring surface of the gate wiring 44 in a film-like manner along the horizontal direction.
  • the first oxide film 52 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner portion of the gate wiring 44.
  • the arc corner portion may have a center of curvature on the gate wiring 44 side.
  • the second oxide film 53 may have a single layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus.
  • the silicon oxide film containing phosphorus may contain boron.
  • the silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass film).
  • the silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass film).
  • the second oxide film 53 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 52.
  • the second oxide film 53 may have a layered structure including a PSG film stacked on the first oxide film 52 and a BPSG film stacked on the PSG film.
  • the second oxide film 53 may have a layered structure including a BPSG film stacked on the first oxide film 52 and a PSG film stacked on the BPSG film.
  • the second oxide film 53 has a single-layer structure made of a PSG film, for example.
  • the thickness of the second oxide film 53 may be greater than the thickness of the first oxide film 52.
  • the second oxide film 53 may have a thickness less than the thickness of the first oxide film 52.
  • the thickness of the second oxide film 53 may be greater than the thickness of the gate electrode 32.
  • the second oxide film 53 may have a thickness less than the thickness of the gate electrode 32.
  • the second oxide film 53 covers the first oxide film 52 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 52 in between.
  • the second oxide film 53 collectively covers the multiple gate structures 30 in the active region 8 with the first oxide film 52 in between.
  • the second oxide film 53 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 52 in between.
  • the second oxide film 53 has a portion that covers the insulating film 31 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 extends in the lamination direction along the sidewall of the gate electrode 32 in a film shape, and has a portion that covers the sidewall of the gate electrode 32 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 extends in the horizontal direction along the electrode surface of the gate electrode 32 in a film shape, and has a portion that covers the electrode surface of the gate electrode 32 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner of the gate electrode 32.
  • the arc corner portion may have a center of curvature on the gate electrode 32 side.
  • the second oxide film 53 collectively covers the drift region 11, the outer body region 35, the termination region 40, and the multiple field regions 42 in the peripheral region 9, sandwiching the peripheral insulating film 43 and the first oxide film 52 between them.
  • the second oxide film 53 covers the gate wiring 44 in the peripheral region 9, sandwiching the first oxide film 52 between them.
  • the second oxide film 53 has a portion that covers the outer insulating film 43 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 extends in the lamination direction along the sidewall of the gate wiring 44 in the form of a film, and has a portion that covers the sidewall of the gate wiring 44 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 extends in the horizontal direction along the wiring surface of the gate wiring 44 in the form of a film, and has a portion that covers the wiring surface of the gate wiring 44 with the first oxide film 52 sandwiched between them.
  • the second oxide film 53 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner of the gate wiring 44.
  • the arc corner portion may have a center of curvature on the gate wiring 44 side.
  • the semiconductor device 1A includes a plurality of source openings 54 formed in the interlayer film 50 in the active region 8.
  • the plurality of source openings 54 are formed in regions to the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2). Specifically, the plurality of source openings 54 penetrate the insulating film 31 and the interlayer film 50 in the regions between the plurality of gate electrodes 32.
  • the multiple source openings 54 penetrate both the first oxide film 52 and the second oxide film 53, and have walls defined by both the first oxide film 52 and the second oxide film 53.
  • the multiple source openings 54 each have an opening end defined by an arc corner portion of the interlayer film 50.
  • the multiple source openings 54 each expose a corresponding multiple source region 16, 17 and contact region 18.
  • the multiple source openings 54 are formed at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. That is, the multiple source openings 54 are formed in a stripe shape extending in the second direction Y.
  • the multiple source openings 54 are formed at intervals in the second direction Y from the gate wiring 44. That is, the multiple source openings 54 are formed in a region surrounded by the multiple gate electrodes 32 and the gate wiring 44.
  • the multiple source openings 54 may be formed in a region between two gate structures 30 adjacent in the first direction X. In this case, the multiple source openings 54 may be formed in a line spaced apart in the second direction Y. Furthermore, in this case, each source opening 54 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.
  • the source opening 54 may have a width W of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width W of the source opening 54 may have a value belonging to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, 2.25 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 2.75 ⁇ m or less, and 2.75 ⁇ m or more and 3 ⁇ m or less.
  • the width W of the source opening 54 is preferably 0.2 ⁇ m
  • the source opening 54 may have a depth D of 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the depth D of the source opening 54 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the depth D of the source opening 54 is preferably 0.5 ⁇ m or more and 1 ⁇ m or less.
  • the source opening 54 preferably has an aspect ratio D/W of 0.5 to 3.
  • the aspect ratio D/W is defined by the ratio of the depth D of the source opening 54 to the width W of the source opening 54.
  • the aspect ratio D/W may have a value that falls within at least one of the following ranges: 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.
  • the aspect ratio D/W is preferably greater than 1.
  • the source openings 54 preferably have a depth D greater than their width W, and are each formed in a vertically elongated shape in cross-sectional view. With this configuration, the gate structures 30 are arranged at a narrow pitch.
  • the aspect ratio D/W of the vertically elongated source openings 54 is preferably greater than 1 and equal to or less than 2.
  • the semiconductor device 1A includes a plurality of source recesses 55 formed in the first main surface 3 in the portions exposed from the plurality of source openings 54.
  • the semiconductor device 1A does not necessarily have to have the source recesses 55. Therefore, a configuration that does not have the source recesses 55 may be adopted.
  • the multiple source recesses 55 each have a planar shape that matches the planar shape of the corresponding source opening 54, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple source recesses 55 are formed at intervals from the lower end of the corresponding body region 13 toward the first main surface 3, and each exposes the corresponding multiple source regions 16, 17 and contact region 18.
  • the multiple source recesses 55 are formed at intervals from the bottoms of the multiple corresponding source regions 16, 17 (contact regions 18) toward the first main surface 3.
  • the multiple source recesses 55 face at least the sub-inclined portion 14 in the horizontal direction.
  • the multiple source recesses 55 may face both the sub-inclined portion 14 and the main inclined portion 15 in the horizontal direction.
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) outer openings 56 formed in the interlayer film 50 in the peripheral region 9.
  • the multiple outer openings 56 are formed in a portion of the interlayer film 50 that covers the termination region 40.
  • the multiple outer openings 56 penetrate the interlayer film 50 and expose the termination region 40.
  • the multiple outer openings 56 are formed in a portion of the interlayer film 50 that covers the overlap region 41 of the termination region 40 and expose the overlap region 41.
  • the outer openings 56 may expose the outer body region 35 instead of or in addition to the termination region 40 (overlapping region 41).
  • the outer openings 56 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces defined by both the first oxide film 52 and the second oxide film 53.
  • the outer openings 56 each have an opening end defined by an arc corner portion of the interlayer film 50.
  • the multiple outer openings 56 are formed at intervals along the termination region 40 (overlap region 41) (see Figures 4 and 5).
  • the multiple outer openings 56 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple outer openings 56 may be formed in a band shape extending along the termination region 40 (overlap region 41) in a plan view.
  • the semiconductor device 1A may have a single outer opening 56.
  • the single outer opening 56 may be formed in a band shape extending along the termination region 40 (overlapping region 41).
  • the single outer opening 56 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view.
  • the single outer opening 56 may be formed in a polygonal ring shape (a square ring in this embodiment) with or without ends, having four sides parallel to the periphery of the first main surface 3.
  • the single outer opening 56 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) following the termination region 40 (overlapping region 41) in a plan view (see FIG. 4).
  • the semiconductor device 1A includes a plurality of outer recesses 57 formed in the portions of the first main surface 3 exposed from the plurality of outer openings 56.
  • the semiconductor device 1A does not necessarily have to have the outer recesses 57. Therefore, a configuration that does not have the outer recesses 57 may be adopted.
  • the multiple outer recesses 57 each have a planar shape that matches the planar shape of the corresponding outer opening 56, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple outer recesses 57 are formed at intervals from the bottom of the termination region 40 (overlap region 41) toward the first main surface 3, and each exposes the termination region 40 (overlap region 41).
  • the outer recesses 57 may have a depth approximately equal to the depth of the source recess 55.
  • the semiconductor device 1A includes at least one (in this embodiment, multiple) gate openings 58 formed in the interlayer film 50 in the peripheral region 9.
  • the multiple gate openings 58 are formed in a portion of the interlayer film 50 that covers the gate wiring 44.
  • the multiple gate openings 58 penetrate the interlayer film 50 and expose the gate wiring 44.
  • the multiple gate openings 58 penetrate both the first oxide film 52 and the second oxide film 53, and have wall surfaces that are defined by both the first oxide film 52 and the second oxide film 53.
  • Each of the multiple gate openings 58 has an opening end that is defined by an arc corner portion of the interlayer film 50.
  • the multiple gate openings 58 are formed at intervals along the gate wiring 44 (see Figures 4 and 5).
  • the multiple gate openings 58 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple gate openings 58 may be formed in a strip shape extending along the gate wiring 44 in a plan view.
  • the semiconductor device 1A may have a single gate opening 58.
  • the single gate opening 58 may be formed in a strip shape extending along the gate wiring 44.
  • the single gate opening 58 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.
  • the single gate opening 58 may be formed in a polygonal ring shape (a square ring in this embodiment) with four sides parallel to the periphery of the first main surface 3, either with or without ends.
  • the single gate opening 58 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) in a plan view following the gate wiring 44 (see FIG. 4).
  • the semiconductor device 1A includes a source pad electrode 60 disposed on the interlayer film 50.
  • the source pad electrode 60 is a terminal electrode to which a source potential is applied from the outside.
  • the source pad electrode 60 may also be referred to as a "first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” etc.
  • the source pad electrode 60 is disposed on a portion of the interlayer film 50 that covers the active region 8.
  • the source pad electrode 60 covers the multiple gate electrodes 32 with the interlayer film 50 in between, and is electrically isolated from the multiple gate electrodes 32 by the interlayer film 50.
  • the source pad electrode 60 is electrically connected to the multiple body regions 13, the multiple source regions 16, 17, the contact region 18, etc. via the multiple source openings 54.
  • the source pad electrode 60 has a first pad portion 60a, a second pad portion 60b, and a third pad portion 60c.
  • the first pad portion 60a has a relatively large planar area and forms the main body of the source pad electrode 60.
  • the first pad portion 60a is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the fourth side surface 5D with respect to the center of the active region 8.
  • the first pad portion 60a covers the multiple gate electrodes 32 with the interlayer film 50 in between, and is electrically connected to the multiple body regions 13, etc. via the multiple source openings 54.
  • the second pad portion 60b has a planar area less than that of the first pad portion 60a, and is pulled out in a strip shape (rectangular shape) from one end of the first pad portion 60a in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C.
  • the second pad portion 60b covers the multiple gate electrodes 32 with the interlayer film 50 in between, and is electrically connected to the multiple body regions 13, etc. via the multiple source openings 54.
  • the third pad portion 60c has a planar area less than that of the first pad portion 60a, and is pulled out in a strip shape (rectangular shape) from the other end of the first pad portion 60a in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 60b in the second direction Y.
  • the third pad portion 60c covers the multiple gate electrodes 32 with the interlayer film 50 in between, and is electrically connected to the multiple body regions 13, etc. via the multiple source openings 54.
  • the plane area of the third pad portion 60c may be approximately equal to the plane area of the second pad portion 60b. Of course, the plane area of the third pad portion 60c may be greater than the plane area of the second pad portion 60b, or may be less than the plane area of the second pad portion 60b. Either or both of the second pad portion 60b and the third pad portion 60c may be used as a terminal portion for monitoring a current.
  • the source pad electrode 60 does not necessarily have to have both the second pad portion 60b and the third pad portion 60c at the same time.
  • the source pad electrode 60 may have only one of the second pad portion 60b and the third pad portion 60c.
  • the source pad electrode 60 may be composed of only the first pad portion 60a, and may not have the second pad portion 60b and the third pad portion 60c.
  • the source pad electrode 60 includes a first underlying electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63.
  • the first underlying electrode film 61 may be referred to as a "source underlying electrode film”
  • the first buried electrodes 62 may be referred to as a “source buried electrode”
  • the first main electrode film 63 may be referred to as a "source main electrode film”.
  • the first underlying electrode film 61 forms the lower layer of the source pad electrode 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c) and covers the interlayer film 50 in the active region 8.
  • the first underlying electrode film 61 collectively covers the region of the interlayer film 50 in which the multiple source openings 54 are formed, and penetrates into the multiple source openings 54 from above the insulating surface 51.
  • the first base electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 54 in a film-like manner.
  • the first base electrode film 61 may have a portion that covers the gate wiring 44 with the interlayer film 50 in between.
  • the first base electrode film 61 may be formed at a distance inward from the gate wiring 44 in a plan view.
  • the first underlying electrode film 61 has a layered structure including a first electrode film 64 layered on the interlayer film 50, and a second electrode film 65 layered on the first electrode film 64.
  • the first electrode film 64 includes a Ti film
  • the second electrode film 65 includes a TiN film.
  • the first underlying electrode film 61 does not necessarily have to have a layered structure, and may have a single layer structure consisting of either the first electrode film 64 (Ti film) or the second electrode film 65 (TiN film).
  • the thickness of the first electrode film 64 may be 10 nm or more and 100 nm or less.
  • the thickness of the first electrode film 64 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the thickness of the second electrode film 65 may be 50 nm or more and 200 nm or less.
  • the thickness of the second electrode film 65 may have a value belonging to at least one of the following ranges: 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less. It is preferable that the thickness of the second electrode film 65 is greater than the thickness of the first electrode film 64.
  • the first electrode film 64 collectively covers the region of the interlayer film 50 where the multiple source openings 54 are formed, and penetrates into the multiple source openings 54 from above the insulating surface 51.
  • the first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 54 in a film-like manner.
  • the first electrode film 64 directly covers the insulating surface 51 (second oxide film 53), and faces the multiple gate electrodes 32 across the interlayer film 50.
  • the first electrode film 64 covers the arc corner of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arc corner of the interlayer film 50 (second oxide film 53), and penetrates into the source opening 54.
  • the first electrode film 64 has a portion that extends in an arc shape at the arc corner. This improves the film-forming property of the first electrode film 64 on the interlayer film 50 (the wall surface of the source opening 54).
  • the first electrode film 64 extends along the wall surface of the source opening 54 and covers the insulating film 31, the first oxide film 52 and the second oxide film 53.
  • the first electrode film 64 faces the side wall of the gate electrode 32 across the interlayer film 50.
  • the first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the first main surface 3.
  • the first electrode film 64 has a portion that covers the source recess 55 in a film-like manner at the bottom of each source opening 54 and is electrically connected to the body region 13, the multiple source regions 16, 17 and the contact region 18.
  • the first electrode film 64 may cover the source recess 55 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the source recess 55.
  • the first electrode film 64 may have a portion located on the bottom side of the source recess 55 with respect to the height position of the first main surface 3, and a portion located on the insulating film 31 side with respect to the height position of the first main surface 3.
  • the second electrode film 65 covers the area of the interlayer film 50 where the multiple source openings 54 are formed on the first electrode film 64 in a film-like manner.
  • the second electrode film 65 has a portion that covers the insulating surface 51 in a film-like manner with the first electrode film 64 in between, and a portion that covers the wall surfaces of the multiple source openings 54 in a film-like manner with the first electrode film 64 in between.
  • the second electrode film 65 faces the multiple gate electrodes 32 across the first electrode film 64 and the interlayer film 50 in the portion covering the insulating surface 51.
  • the second electrode film 65 covers the arc corner portion of the interlayer film 50 (second oxide film 53) in a film-like manner, following the first electrode film 64, and extends into the source opening 54.
  • the second electrode film 65 has a portion that extends in an arc shape at the arc corner portion of the interlayer film 50. This improves the film formability of the second electrode film 65 on the interlayer film 50 (the wall surface of the source opening 54).
  • the second electrode film 65 extends along the wall surface of the source opening 54, and covers the insulating film 31, the first oxide film 52, and the second oxide film 53 with the first electrode film 64 in between.
  • the second electrode film 65 faces the side wall of the gate electrode 32 with the first electrode film 64 and the interlayer film 50 in between.
  • the second electrode film 65 has a portion that covers the source recess 55 in a film-like manner at the bottom of each source opening 54 with the first electrode film 64 in between, and is electrically connected to the body region 13, the multiple source regions 16, 17, and the contact region 18 via the first electrode film 64.
  • the second electrode film 65 may have a portion located within the source recess 55.
  • the entire second electrode film 65 is located above the source recess 55.
  • the multiple first buried electrodes 62 form a middle layer of the source pad electrode 60 (first pad portion 60a, second pad portion 60b, and third pad portion 60c), and are buried in the multiple source openings 54, respectively.
  • the first buried electrodes 62 include a conductive material different from the conductive material of the first base electrode film 61.
  • the first buried electrodes 62 include at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the first buried electrodes 62 include tungsten.
  • the multiple first buried electrodes 62 are buried in a one-to-one correspondence with the multiple source openings 54 via a single first base electrode film 61.
  • the multiple first buried electrodes 62 are electrically connected to the first main surface 3 (chip 2) within the multiple source openings 54.
  • the first buried electrodes 62 are electrically connected to the multiple source regions 16, 17 and contact region 18 via the first base electrode film 61.
  • the configuration of one first buried electrode 62 is described below.
  • the first buried electrode 62 has a first buried electrode surface 66 exposed from the source opening 54, exposing the insulating surface 51.
  • the first buried electrode surface 66 may be referred to as a "source buried electrode film.”
  • the first buried electrode 62 is embedded in the source opening 54 at a distance from the insulating surface 51 toward the first main surface 3, exposing a portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51.
  • the first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 with the first underlying electrode film 61 in between.
  • the first buried electrode 62 faces the sidewall of the gate electrode 32 in the horizontal direction.
  • the first buried electrode 62 may have a portion located within the source recess 55.
  • the entire first buried electrode 62 is located above the source recess 55.
  • the first buried electrode surface 66 is located closer to the first main surface 3 than the insulating surface 51, and does not have a portion that faces the electrode surface of the gate electrode 32 across the interlayer film 50 in the stacking direction (vertical direction Z). In this embodiment, the first buried electrode surface 66 has a portion that covers the arc corner portion of the interlayer film 50 across the first base electrode film 61.
  • the first buried electrode surface 66 may be located below the arc corner of the interlayer film 50.
  • the first buried electrode surface 66 is located closer to the insulating surface 51 than the height position of the first oxide film 52.
  • the first buried electrode surface 66 is preferably located above the electrode surface of the gate electrode 32.
  • the first buried electrode surface 66 has a recess in the center that is recessed toward the first main surface 3 (chip 2).
  • the bottom of the recess is preferably located on the insulating surface 51 side relative to the height position of the electrode surface of the gate electrode 32.
  • a part (e.g., the recess) or the entire first buried electrode surface 66 may be located below the electrode surface of the gate electrode 32.
  • a part (e.g., the recess) or the entire first buried electrode surface 66 may be located on the insulating surface 51 side relative to the height position of the first oxide film 52.
  • the first main electrode film 63 forms the upper layer of the source pad electrode 60 (the first pad portion 60a, the second pad portion 60b, and the third pad portion 60c) and covers the first base electrode film 61 and the multiple first buried electrodes 62 in a film-like manner.
  • the first main electrode film 63 contains a conductive material different from the conductive material of the first base electrode film 61 and the conductive material of the first buried electrodes 62.
  • the first main electrode film 63 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the first main electrode film 63 has a thickness greater than the thickness (total thickness) of the first underlying electrode film 61.
  • the first main electrode film 63 has a thickness greater than the thickness of the first buried electrode 62.
  • the thickness of the first main electrode film 63 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the first main electrode film 63 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first main electrode film 63 is mechanically and electrically connected to the first underlying electrode film 61 in the portion covering the insulating surface 51, and faces the multiple gate electrodes 32 across the first underlying electrode film 61 and the interlayer film 50.
  • the first main electrode film 63 is mechanically and electrically connected to the multiple first buried electrodes 62 in the portion covering the multiple source openings 54.
  • the first main electrode film 63 is electrically connected to the multiple body regions 13, the multiple source regions 16, 17, the contact region 18, etc. via both the first underlying electrode film 61 and the multiple first buried electrodes 62.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 at a height position on the first main surface 3 side relative to the height position of the insulating surface 51.
  • the first main electrode film 63 has a portion that covers the recess of the first buried electrode surface 66.
  • the first main electrode film 63 may have a portion that covers the circular arc corner portion of the interlayer film 50 with the first base electrode film 61 in between.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 above the height position of the first oxide film 52.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 above the electrode surface of the gate electrode 32.
  • the first main electrode film 63 does not have a portion that faces the gate electrode 32 in the horizontal direction. If the first buried electrode surface 66 is located below the height position of the electrode surface of the gate electrode 32 and the height position of the first oxide film 52, the first main electrode film 63 may have a portion that faces the gate electrode 32 in the horizontal direction.
  • the film formation of the first main electrode film 63 for the multiple source openings 54 is improved by the multiple first buried electrodes 62. This ensures an appropriate current path between the first main surface 3 and the first main electrode film 63. This configuration is effective in suppressing film formation defects caused by the multiple source openings 54 and reducing wiring resistance.
  • the semiconductor device 1A includes a plurality of first silicide portions 67 formed on the surface portions of the first main surface 3 exposed from the plurality of source openings 54.
  • the plurality of first silicide portions 67 are formed in a film shape along the wall surfaces (side walls and bottom walls) of the plurality of source recesses 55, and are mechanically and electrically connected to the first base electrode film 61.
  • the plurality of first silicide portions 67 are formed in the surface layer portions of the plurality of body regions 13, and electrically connect the plurality of first buried electrodes 62 to the plurality of body regions 13 via the first base electrode film 61.
  • the first silicide portion 67 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide.
  • the first silicide portion 67 is preferably made of Ti silicide, Ni silicide, or Co silicide.
  • the semiconductor device 1A includes a source finger electrode 68 that is extended from the source pad electrode 60 onto the peripheral region 9.
  • the source finger electrode 68 transmits the source potential applied to the source pad electrode 60 to the peripheral region 9.
  • the source finger electrode 68 is extended from the portion of the source pad electrode 60 (first pad portion 60a) on the fourth side surface 5D side onto the portion of the interlayer film 50 that covers the peripheral region 9.
  • the source finger electrodes 68 are extended to above the termination region 40 and are electrically connected to the termination region 40 via a plurality of outer openings 56. Specifically, the source finger electrodes 68 are electrically connected to the overlap region 41 of the termination region 40 via a plurality of outer openings 56.
  • the source finger electrode 68 extends in a strip shape along the termination region 40 (overlapping region 41).
  • the source finger electrode 68 has a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.
  • the source finger electrode 68 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 60.
  • the source finger electrode 68 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a plan view in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the source finger electrode 68 like the source pad electrode 60, includes a first underlying electrode film 61, a plurality of first buried electrodes 62, and a first main electrode film 63.
  • the first underlying electrode film 61 forms a lower layer of the source finger electrode 68, and covers the interlayer film 50 in the peripheral region 9.
  • the first underlying electrode film 61 collectively covers the region of the interlayer film 50 in which the plurality of outer openings 56 are formed, and extends into the plurality of outer openings 56 from above the insulating surface 51.
  • the first underlying electrode film 61 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the plurality of outer openings 56 in a film-like manner.
  • the first base electrode film 61 like the source pad electrode 60, has a layered structure including a first electrode film 64 and a second electrode film 65.
  • the first electrode film 64 collectively covers the area of the interlayer film 50 in which the multiple outer openings 56 are formed, and penetrates into the multiple outer openings 56 from above the insulating surface 51.
  • the first electrode film 64 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 56 in a film-like manner.
  • the first electrode film 64 covers the arc corner of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arc corner of the interlayer film 50 (second oxide film 53), and enters the outer opening 56.
  • the first electrode film 64 has a portion that extends in an arc shape at the arc corner. This improves the film-forming ability of the first electrode film 64 on the interlayer film 50 (wall surface of the outer opening 56).
  • the first electrode film 64 extends along the wall surface of the outer opening 56, and covers the peripheral insulating film 43, the first oxide film 52, and the second oxide film 53.
  • the first electrode film 64 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 56, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 64 has a portion that covers the outer recess 57 in a film-like manner at the bottom of each outer opening 56, and is electrically connected to the termination region 40 (overlap region 41) within the outer recess 57.
  • the first electrode film 64 may cover the outer recess 57 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the outer recess 57.
  • the first electrode film 64 may have a portion located on the bottom side of the outer recess 57 relative to the height position of the first main surface 3, and a portion located on the peripheral insulating film 43 side relative to the height position of the first main surface 3.
  • the second electrode film 65 is disposed on the first electrode film 64 and covers the area of the interlayer film 50 in which the multiple outer openings 56 are formed.
  • the second electrode film 65 has a portion that covers the insulating surface 51 in a film-like manner with the first electrode film 64 in between, and a portion that covers the wall surfaces of the multiple outer openings 56 in a film-like manner with the first electrode film 64 in between.
  • the second electrode film 65 covers the arc corners of the interlayer film 50 (second oxide film 53) in a film-like manner and extends into the outer opening 56.
  • the second electrode film 65 has a portion that extends in an arc shape at the arc corners of the interlayer film 50 (second oxide film 53). This improves the film-forming properties of the second electrode film 65 on the interlayer film 50 (wall surface of the outer opening 56).
  • the second electrode film 65 extends along the wall surface of the outer opening 56 and covers the peripheral insulating film 43, first oxide film 52, and second oxide film 53 with the first electrode film 64 in between.
  • the second electrode film 65 has a portion that covers the outer recess 57 in a film-like manner at the bottom of each outer opening 56, sandwiching the first electrode film 64 therebetween, and is electrically connected to the termination region 40 (overlapping region 41) via the first electrode film 64.
  • the second electrode film 65 may have a portion that is located within the outer recess 57.
  • the entire second electrode film 65 is located above the outer recess 57.
  • the multiple first buried electrodes 62 form a middle layer of the source finger electrode 68, and are buried in the multiple outer openings 56, respectively.
  • the multiple first buried electrodes 62 are buried in a one-to-one correspondence with the multiple outer openings 56 via a single first base electrode film 61.
  • the multiple first buried electrodes 62 are electrically connected to the termination region 40 (overlap region 41) via the first base electrode film 61.
  • the first buried electrode 62 has a first buried electrode surface 66 exposed from the outer opening 56, exposing the insulating surface 51. Specifically, the first buried electrode 62 is buried in the outer opening 56 at a distance from the insulating surface 51 toward the first principal surface 3, exposing the portion of the first base electrode film 61 (second electrode film 65) that covers the insulating surface 51. In other words, the first buried electrode surface 66 is located closer to the first principal surface 3 than the insulating surface 51.
  • the first buried electrode 62 covers the first oxide film 52 and the second oxide film 53 with the first base electrode film 61 in between.
  • the first buried electrode 62 has a portion that covers the arc corner portion of the interlayer film 50 with the first base electrode film 61 in between.
  • the first buried electrode 62 is buried at a distance from the arc corner portion of the interlayer film 50 toward the outer insulating film 43, and the entire arc corner portion may be exposed.
  • the first buried electrode surface 66 is located on the insulating surface 51 side of the height position of the first oxide film 52 in the outer opening 56. Of course, the first buried electrode surface 66 may be located on the outer insulating film 43 side of the height position of the first oxide film 52.
  • the first buried electrode 62 may have a portion positioned within the outer recess 57.
  • the entire first buried electrode 62 is positioned above the outer recess 57.
  • the first main electrode film 63 forms the upper layer of the source finger electrode 68, and covers the first underlying electrode film 61 and the multiple first buried electrodes 62 in a film-like manner.
  • the first main electrode film 63 is mechanically and electrically connected to the first underlying electrode film 61 in the portion covering the insulating surface 51, and is mechanically and electrically connected to the multiple first buried electrodes 62 in the portion covering the multiple outer openings 56.
  • the first main electrode film 63 is electrically connected to the termination region 40 (overlap region 41) via the first underlying electrode film 61 and the multiple first buried electrodes 62.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 at a height position on the first main surface 3 side relative to the height position of the insulating surface 51.
  • the first main electrode film 63 is connected to the first buried electrode surface 66 above the height position of the first oxide film 52.
  • the first main electrode film 63 has a portion that covers the recess of the first buried electrode surface 66.
  • the first main electrode film 63 may have a portion that covers the arc corner portion of the interlayer film 50, sandwiching the first base electrode film 61.
  • the first main electrode film 63 may be connected to the first buried electrode 62 in a region below the first oxide film 52.
  • the deposition properties of the first main electrode film 63 on the multiple outer openings 56 are improved by the multiple first buried electrodes 62. This ensures an appropriate current path between the termination region 40 (overlap region 41) and the first main electrode film 63. This configuration is effective in suppressing deposition defects caused by the multiple outer openings 56 and reducing wiring resistance.
  • the semiconductor device 1A includes a plurality of second silicide portions 69 formed on the surface portions of the first main surface 3 exposed from the plurality of outer openings 56.
  • the plurality of second silicide portions 69 are formed in a film shape along the wall surfaces (side walls and bottom walls) of the plurality of outer recesses 57, and are mechanically and electrically connected to the first base electrode film 61.
  • the plurality of second silicide portions 69 are formed in the surface layer portion of the termination region 40 (overlap region 41), and electrically connect the plurality of first buried electrodes 62 to the termination region 40 (overlap region 41) via the first base electrode film 61.
  • the second silicide portion 69 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide.
  • the second silicide portion 69 is preferably made of Ti silicide, Ni silicide, or Co silicide. It is particularly preferable that the second silicide portion 69 is made of the same type of silicide as the first silicide portion 67.
  • the semiconductor device 1A includes a gate finger electrode 70 selectively routed over the interlayer film 50.
  • the gate finger electrode 70 transmits a gate potential to the gate wiring 44.
  • the gate finger electrode 70 is routed over a portion of the interlayer film 50 that covers the gate wiring 44 (i.e., over the outer peripheral region 9), and is electrically connected to the gate wiring 44 via a plurality of gate openings 58.
  • the gate finger electrode 70 is disposed in the region between the source pad electrode 60 and the source finger electrode 68 and spaced apart from the source pad electrode 60 and the source finger electrode 68.
  • the gate finger electrode 70 extends in a strip shape along the gate wiring 44.
  • the gate finger electrode 70 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view.
  • the gate finger electrode 70 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 60.
  • the gate finger electrode 70 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view (see FIG. 4).
  • the gate finger electrode 70 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 68 passes.
  • the gate finger electrode 70 includes a second underlying electrode film 71, at least one (in this embodiment, multiple) second buried electrodes 72, and a second main electrode film 73.
  • the second underlying electrode film 71 may be referred to as the "gate underlying electrode film”
  • the second buried electrode 72 may be referred to as the “gate buried electrode”
  • the second main electrode film 73 may be referred to as the "gate main electrode film”.
  • the second underlying electrode film 71 forms the lower layer of the gate finger electrode 70, and covers the interlayer film 50 in the peripheral region 9.
  • the second underlying electrode film 71 collectively covers the region of the interlayer film 50 in which the multiple gate openings 58 are formed, and penetrates into the multiple gate openings 58 from above the insulating surface 51.
  • the second underlying electrode film 71 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner.
  • the second base electrode film 71 has a layered structure including a first electrode film 74 layered on the interlayer film 50, and a second electrode film 75 layered on the first electrode film 74. It is preferable that the first electrode film 74 includes the same type of conductive material as the first electrode film 64 on the source side, and the second electrode film 75 includes the same type of conductive material as the second electrode film 65 on the source side. In this embodiment, the first electrode film 74 includes a Ti film, and the second electrode film 75 includes a TiN film.
  • the second base electrode film 71 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 74 (Ti film) or the second electrode film 75 (TiN film).
  • the first electrode film 74 may have a thickness approximately equal to the thickness of the first electrode film 64 on the source side.
  • the second electrode film 75 may have a thickness approximately equal to the thickness of the second electrode film 65 on the source side.
  • the first electrode film 74 collectively covers the region of the interlayer film 50 in which the multiple gate openings 58 are formed, and penetrates into the multiple gate openings 58 from above the insulating surface 51.
  • the first electrode film 74 has a portion that covers the insulating surface 51 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner.
  • the first electrode film 74 covers the arc corner portion of the interlayer film 50 (second oxide film 53) in a film-like manner, following the arc corner portion, and extends into the gate opening 58.
  • the first electrode film 74 has a portion that extends in an arc shape at the arc corner portion. This improves the film-forming property of the first electrode film 74 on the interlayer film 50 (the wall surface of the gate opening 58).
  • the first electrode film 74 extends along the wall surface of the gate opening 58 and covers the first oxide film 52 and the second oxide film 53.
  • the first electrode film 74 covers the gate wiring 44 at the bottom of each gate opening 58 in a film-like manner and is electrically connected to the gate wiring 44.
  • the second electrode film 75 covers the area of the interlayer film 50 on the first electrode film 74 where the multiple gate openings 58 are formed.
  • the second electrode film 75 has a portion that covers the insulating surface 51 in a film-like manner with the first electrode film 74 in between, and a portion that covers the wall surfaces of the multiple gate openings 58 in a film-like manner with the first electrode film 74 in between.
  • the second electrode film 75 covers the arc corners of the interlayer film 50 (second oxide film 53) in a film-like manner and penetrates into the gate opening 58.
  • the second electrode film 75 has a portion that extends in an arc shape at the arc corners of the interlayer film 50 (second oxide film 53). This improves the film-forming properties of the second electrode film 75 on the interlayer film 50 (the wall surface of the gate opening 58).
  • the second electrode film 75 extends along the wall surface of the gate opening 58, and covers the first oxide film 52 and the second oxide film 53 with the first electrode film 74 in between.
  • the second electrode film 75 has a portion that covers the gate wiring 44 in a film-like manner at the bottom of each gate opening 58 with the first electrode film 74 in between, and is electrically connected to the gate wiring 44 via the first electrode film 74.
  • the multiple second buried electrodes 72 form a middle layer of the gate finger electrode 70 and are buried in the multiple gate openings 58, respectively.
  • the second buried electrodes 72 include a conductive material different from the conductive material of the second base electrode film 71.
  • the second buried electrodes 72 include at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy.
  • the second buried electrodes 72 preferably include the same type of conductive material as the conductive material of the first buried electrodes 62. In this embodiment, the second buried electrodes 72 include tungsten.
  • the multiple second buried electrodes 72 are buried in a one-to-one correspondence with the multiple gate openings 58 via a single second base electrode film 71.
  • the multiple second buried electrodes 72 are electrically connected to the gate wiring 44 via the second base electrode film 71 within the multiple gate openings 58.
  • the second buried electrode 72 has a second buried electrode surface 76 exposed from the gate opening 58, exposing the insulating surface 51.
  • the second buried electrode surface 76 may be referred to as a "gate buried electrode surface.”
  • the second buried electrode 72 is buried in the gate opening 58 at a distance from the insulating surface 51 toward the first principal surface 3, exposing a portion of the second base electrode film 71 (second electrode film 75) that covers the insulating surface 51. In other words, the second buried electrode surface 76 is located closer to the first principal surface 3 than the insulating surface 51.
  • the second buried electrode 72 covers the first oxide film 52 and the second oxide film 53 with the second base electrode film 71 in between.
  • the second buried electrode 72 has a portion that covers the arc corner portion of the interlayer film 50 with the second base electrode film 71 in between.
  • the second buried electrode 72 is buried at a distance from the arc corner portion of the interlayer film 50 toward the gate wiring 44 side, and the entire arc corner portion may be exposed.
  • the second buried electrode surface 76 is located closer to the insulating surface 51 than the height position of the first oxide film 52. Of course, the second buried electrode surface 76 may be located closer to the gate wiring 44 than the height position of the first oxide film 52.
  • the second main electrode film 73 forms the upper layer of the gate finger electrode 70, and covers the second base electrode film 71 and the multiple second buried electrodes 72 in a film-like manner.
  • the second main electrode film 73 contains a conductive material different from the conductive material of the second base electrode film 71 and the conductive material of the second buried electrodes 72.
  • the second main electrode film 73 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the second main electrode film 73 preferably includes the same type of conductive material as the conductive material of the first main electrode film 63.
  • the second main electrode film 73 may have a thickness approximately equal to that of the first main electrode film 63.
  • the second main electrode film 73 is mechanically and electrically connected to the second base electrode film 71 in the portion covering the insulating surface 51, and is mechanically and electrically connected to the multiple second buried electrodes 72 in the portion covering the multiple gate openings 58. As a result, the second main electrode film 73 is electrically connected to the gate wiring 44 via the second base electrode film 71 and the multiple second buried electrodes 72.
  • the second main electrode film 73 is connected to the second buried electrode 72 at a height position on the first main surface 3 side relative to the height position of the insulating surface 51.
  • the second main electrode film 73 is connected to the second buried electrode surface 76 above the height position of the first oxide film 52.
  • the second main electrode film 73 has a portion that covers the recess of the second buried electrode surface 76.
  • the second main electrode film 73 may have a portion that covers the arc corner portion of the interlayer film 50, sandwiching the second base electrode film 71.
  • the second main electrode film 73 may be connected to the second buried electrode 72 in a region below the first oxide film 52.
  • the film formation of the second main electrode film 73 for the multiple gate openings 58 is improved by the multiple second buried electrodes 72. This ensures an appropriate current path between the gate wiring 44 and the second main electrode film 73. This configuration is effective in suppressing film formation defects caused by the multiple gate openings 58 and reducing wiring resistance.
  • the semiconductor device 1A includes a gate pad electrode 80 disposed on the interlayer film 50.
  • the gate pad electrode 80 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate pad electrode 80 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the gate pad electrode 80 is disposed in the region between the source pad electrode 60 and the source finger electrodes 68 and spaced apart from the source pad electrode 60 and the source finger electrodes 68.
  • the gate pad electrode 80 is disposed in a region on the third side surface 5C side relative to the first pad portion 60a, and is sandwiched between the second pad portion 60b and the third pad portion 60c. In other words, the gate pad electrode 80 faces the first pad portion 60a in the first direction X, and faces the second pad portion 60b and the third pad portion 60c in the second direction Y.
  • the gate pad electrode 80 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate pad electrode 80 has a planar area less than that of the source pad electrode 60 (first pad portion 60a).
  • the gate pad electrode 80 may have a planar area less than that of the second pad portion 60b (third pad portion 60c).
  • the gate pad electrode 80 is disposed on the portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 70.
  • the gate pad electrode 80 may cover multiple gate electrodes 32 with the interlayer film 50 in between, or may cover the gate wiring 44 with the interlayer film 50 in between.
  • the gate pad electrode 80 like the gate finger electrode 70, includes a second base electrode film 71 and a second main electrode film 73.
  • the second base electrode film 71 forms a lower layer of the gate pad electrode 80 and covers the interlayer film 50 in a film-like manner.
  • the second base electrode film 71 like the gate finger electrode 70, has a layered structure including a first electrode film 74 and a second electrode film 75.
  • the first electrode film 74 covers the interlayer film 50 in a film-like manner
  • the second electrode film 75 covers the first electrode film 74 in a film-like manner.
  • the second main electrode film 73 forms an upper layer of the gate pad electrode 80 and covers the second base electrode film 71 in a film-like manner.
  • the gate pad electrode 80 may have a plurality of second buried electrodes 72, similar to the gate finger electrode 70.
  • the gate pad electrode 80 may be electrically connected to the gate wiring 44 via the plurality of second buried electrodes 72, similar to the gate finger electrode 70.
  • the gate pad electrode 80 may be electrically connected to the multiple gate electrodes 32 via multiple second buried electrodes 72.
  • the gate pad electrode 80 does not have to have multiple second buried electrodes 72.
  • the gate pad electrode 80 does not have to have electrical connection parts to the multiple gate electrodes 32 and to the gate wiring 44 in the area directly below.
  • the gate potential applied to the gate pad electrode 80 is applied to the gate wiring 44 via the gate finger electrode 70.
  • the gate potential is transmitted to the multiple gate electrodes 32 via a wiring path (current path) along the gate wiring 44. This causes the multiple gate electrodes 32 to be turned on, controlling the on/off of the multiple channel regions 28, 29.
  • the semiconductor device 1A includes a drain pad electrode 85 covering the second main surface 4.
  • the drain pad electrode 85 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain pad electrode 85 may be referred to as a "third pad electrode,” a "third main surface electrode,” a “third terminal electrode,” etc.
  • the drain pad electrode 85 is electrically connected to the drain region 10.
  • the drain pad electrode 85 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (the first to fourth side surfaces 5A to 5D).
  • the drain pad electrode 85 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.
  • the breakdown voltage that can be applied between the source pad electrode 60 and the drain pad electrode 85 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 12 is a schematic diagram showing a wafer 100 used in the manufacture of semiconductor device 1A.
  • wafer 100 is a base material for chip 2 and contains SiC single crystal.
  • Wafer 100 is formed in a flat disk shape. Of course, wafer 100 may also be formed in a flat rectangular parallelepiped shape.
  • Wafer 100 has a first wafer main surface 101 on one side, a second wafer main surface 102 on the other side, and a wafer side surface 103 connecting first wafer main surface 101 and second wafer main surface 102.
  • the first wafer main surface 101 corresponds to the first main surface 3 of the chip 2, and the second wafer main surface 102 corresponds to the second main surface 4 of the chip 2.
  • the first wafer main surface 101 and the second wafer main surface 102 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 101 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 102 is formed by the carbon surface of the SiC single crystal.
  • the wafer 100 (the first wafer main surface 101 and the second wafer main surface 102) has the off-direction and off-angle described above.
  • the wafer 100 has a mark 104 on the wafer side surface 103 that indicates the crystal orientation of the SiC single crystal.
  • the mark 104 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 101 in a plan view.
  • the mark 104 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 104 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • the wafer 100 has a layered structure including a first semiconductor layer 6 and a second semiconductor layer 7.
  • the first semiconductor layer 6 is made of a semiconductor wafer (SiC wafer) including a SiC single crystal (semiconductor single crystal), and has the off-direction and off-angle described above.
  • the first semiconductor layer 6 forms the second wafer main surface 102 and the wafer side surface 103.
  • the second semiconductor layer 7 is made of an epitaxial layer (SiC epitaxial layer) containing a SiC single crystal (semiconductor single crystal) and is stacked on the first semiconductor layer 6. That is, in this form, the wafer 100 is made of an epitaxial wafer (so-called epiwafer) having a stacked structure including a semiconductor wafer and an epitaxial layer.
  • the second semiconductor layer 7 has the off direction and off angle described above.
  • the second semiconductor layer 7 forms the first wafer main surface 101 and the wafer side surface 103.
  • the wafer 100 includes a drain region 10 in the region (surface layer) on the second wafer main surface 102 side.
  • the drain region 10 is formed in a layer shape extending along the second wafer main surface 102.
  • the drain region 10 is formed by the first semiconductor layer 6.
  • the wafer 100 includes a drift region 11 in the region (surface layer) on the first wafer main surface 101 side.
  • the drift region 11 is formed in a layer extending along the first wafer main surface 101, and is electrically connected to the drain region 10.
  • the drift region 11 is formed by the second semiconductor layer 7.
  • the wafer 100 includes a plurality of device regions 105 and a plurality of cutting lines 106.
  • the plurality of device regions 105 and the plurality of cutting lines 106 are defined by alignment marks or the like formed on the first wafer main surface 101 side.
  • Each device region 105 is a region corresponding to the semiconductor device 1A.
  • the plurality of device regions 105 are each set to have a rectangular shape in a plan view.
  • the multiple device regions 105 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 105 are each set at intervals inward from the periphery of the first wafer main surface 101 in a plan view.
  • the multiple cutting lines 106 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 105.
  • 13A to 13H are cross-sectional views showing a manufacturing method for semiconductor device 1A.
  • 13A to 13H show a cross section of a portion of active region 8 (the portion where body structure 12 is formed) in one device region 105.
  • the aforementioned wafer 100 preparation process is performed.
  • a process of forming a first mask 111 having a predetermined layout is performed.
  • the first mask 111 is formed on the first wafer main surface 101.
  • the first mask 111 has a number of openings 112 that expose the areas where a number of body regions 13 are to be formed.
  • the first mask 111 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask).
  • the first mask 111 may have a single layer structure made of an inorganic mask or an organic mask.
  • the first mask 111 may have a layered structure including an inorganic mask and an organic mask layered in this order on the first wafer main surface 101 side.
  • the first mask 111 may include at least one of a silicon oxide film, a silicon nitride film, and a polysilicon film as an inorganic mask.
  • the first mask 111 may include a positive or negative type photosensitive resin film (i.e., a resist film) as an organic mask.
  • a process for forming the body region 13 is carried out.
  • a p-type impurity (trivalent element) is implanted into the surface layer of the drift region 11 by ion implantation through the opening 112 (first mask 111).
  • the p-type impurity (trivalent element) is preferably aluminum.
  • the p-type impurity is implanted into the surface layer of the drift region 11 so that the horizontal implantation range decreases in the thickness direction. This forms the body region 13 having a peripheral portion that is inclined obliquely relative to the first wafer main surface 101.
  • the p-type impurities are implanted into the surface layer of the drift region 11 by oblique ion implantation at an implantation angle that is oblique to the first wafer main surface 101.
  • the implantation angle is the irradiation angle of the p-type impurities with respect to a vertical line extending along the vertical direction Z, when the vertical line is set as the reference angle (0°).
  • p-type impurities are implanted at positive and negative implantation angles relative to the vertical line.
  • Positive and negative implantation angles are defined relatively. Therefore, if one side of the horizontal direction (first direction X in this embodiment) relative to the vertical line is defined as a positive implantation angle, the other side of the horizontal direction (first direction X in this embodiment) relative to the vertical line is defined as a negative implantation angle.
  • the p-type impurity is also introduced into the region of the drift region 11 directly below the first mask 111. Some of the p-type impurity may pass through the lower end of the first mask 111 and be implanted into the surface layer of the drift region 11. The p-type impurity is implanted in an arc shape (circular arc shape) starting from the lower end of the opening 112 of the first mask 111.
  • the body region 13 having an obliquely inclined peripheral portion i.e., the sub-inclined portion 14 and the main inclined portion 15
  • the p-type impurity at positive and negative implantation angles, a duplicated implantation site of the p-type impurity is created in the inner portion (middle portion) of the opening 112, and a first high concentration region 24, a low concentration region 25, and a second high concentration region 26 are formed.
  • the p-type impurity may be implanted in a single step at a target depth position in the surface layer of the drift region 11.
  • the p-type impurity is preferably implanted in multiple steps at different target depth positions in the surface layer of the drift region 11 at different implantation angles.
  • the p-type impurity injection process may include a step of injecting the p-type impurity multiple times at the same target depth position in the drift region 11 under the same or different process conditions.
  • the “single-stage injection process” refers to a process in which p-type impurities are injected once or multiple times into the same target depth position to form body region 13.
  • the “multi-stage injection process” refers to a process in which p-type impurities are injected once or multiple times into multiple target depth positions to form body region 13.
  • the number of injection stages (number of target depth positions) of p-type impurities in the multistage injection process may be 2, 3, 4, 5, 6, 7, 8, 9 or 10.
  • the number of injection stages is preferably 2 to 5.
  • p-type impurities are injected into different target depth positions so that the injection sites of the p-type impurities overlap in the thickness direction. This forms a body region 13 having a concentration gradient (first concentration gradient portion 22 and second concentration gradient portion 23) that gradually increases and decreases in the thickness direction.
  • the dose (impurity concentration) of p-type impurities in the drift region 11 is adjusted to increase as the implantation location becomes deeper. The dose is adjusted appropriately according to the p-type impurity concentration of the body region 13 to be formed.
  • the implantation energy of the p-type impurities into the drift region 11 is adjusted so that it increases as the implantation location becomes deeper.
  • the implantation energy is 50 KeV or more and 1000 KeV or less, and is appropriately adjusted according to the target depth position at which the p-type impurity concentration is to be implanted.
  • the injection range of the p-type impurities can expand horizontally due to process conditions (dose amount and injection energy). Therefore, in the multi-stage injection process, the injection angle of the p-type impurities into the drift region 11 is adjusted to become smaller as the injection location becomes deeper. In other words, in the multi-stage injection process, the injection angle of the p-type impurities into the drift region 11 is adjusted to become larger as the injection location becomes shallower.
  • the body region 13 is appropriately formed to have a tapered shape in the thickness direction.
  • the body region 13 can have a maximum body width WB at the upper end or the region on the upper end side.
  • the body region 13 can have a minimum body width WB at the lower end or the region on the lower end side.
  • the implantation angle of the p-type impurity is preferably set to 0° or more and 45° or less, taking into consideration shadowing by the first mask 111.
  • the p-type impurity may be implanted in one step or in multiple steps at a first implantation angle to a first target depth position where a region below the middle of the body region 13 is to be formed.
  • the first implantation angle is adjusted so that it becomes smaller as the implantation location becomes deeper.
  • the first injection angle may be 0° or more and 20° or less.
  • the first injection angle may be set to a value belonging to at least one of the following ranges: 0° or more and 2.5° or less, 2.5° or more and 5° or less, 5° or more and 7.5° or less, 7.5° or more and 10° or less, 10° or more and 12.5° or less, 12.5° or more and 15° or less, 15° or more and 17.5° or less, and 17.5° or more and 20° or less. It is preferable that the first injection angle is greater than 0° and less than 10°.
  • the first implantation angle for the deepest portion may be greater than 0° and less than 5°.
  • the first implantation angle for regions other than the deepest portion may be greater than 0° and less than 10°.
  • the first implantation angle allows the main inclined portion 15 of the body region 13 to be appropriately formed.
  • the p-type impurity may be implanted in a single step or multiple steps at a second implantation angle less than or equal to the first implantation angle at a second target depth position where a region above the middle of the body region 13 is to be formed.
  • the second implantation angle is preferably less than the first implantation angle.
  • the second implantation angle may be 10° or more and 45° or less.
  • the second implantation angle may be set to a value belonging to at least one of the following ranges: 10° or more and 15° or less, 15° or more and 20° or less, 20° or more and 25° or less, 25° or more and 30° or less, 30° or more and 35° or less, 35° or more and 40° or less, 40° or more and 45° or less, and 45° or more and 50° or less.
  • the second implantation angle is preferably 5° or more and 30° or less. It is particularly preferable that the second implantation angle is 10° or more and 25° or less. According to the second implantation angle, the sub-inclined portion 14 of the body region 13 is appropriately formed.
  • the implantation angle of the p-type impurity may be 5° or more and 30° or less. In this case, the implantation angle is preferably 10° or more and 25° or less.
  • the body region 13 according to the first to sixth embodiment examples (see Figures 10A to 10F) and the concentration profile of the body region 13 (see Figures 11A and 11B) can be obtained by appropriately adjusting the process conditions described above.
  • the process of forming the body region 13 may include a process of forming the outer body region 35.
  • the opening 112 of the first mask 111 may expose the region where the outer body region 35 is to be formed in addition to the region where the body region 13 is to be formed.
  • the p-type impurity process includes a process of implanting p-type impurities through the opening 112 into the region in which the outer body region 35 is to be formed. This process forms the outer body region 35 having a concentration gradient similar to that of the body region 13.
  • a process for forming a second mask 113 having a predetermined layout is carried out.
  • the second mask 113 is used in conjunction with the first mask 111, and is placed on the first wafer main surface 101 within the opening 112 of the first mask 111.
  • the second mask 113 together with the first mask 111, defines a plurality of inner openings 114 within the opening 112.
  • the plurality of inner openings 114 expose regions in which a plurality of source regions 16, 17 are to be formed.
  • the second mask 113 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask).
  • the second mask 113 may have a single layer structure made of an inorganic mask or an organic mask.
  • the second mask 113 may have a layered structure including an inorganic mask and an organic mask layered in this order on the second wafer main surface 102 side.
  • the second mask 113 may include at least one of a silicon oxide film, a silicon nitride film, and a polysilicon film as an inorganic mask.
  • the second mask 113 may include a positive or negative type photosensitive resin film (i.e., a resist film) as an organic mask.
  • the second mask 113 preferably contains a mask material different from the mask material of the first mask 111.
  • the second mask 113 may have a thickness greater than the thickness of the first mask 111.
  • the second mask 113 may have a thickness less than the thickness of the first mask 111.
  • n-type impurities are implanted into the surface layer of the body region 13 by ion implantation through the plurality of inner openings 114 (first mask 111 and second mask 113).
  • the n-type impurities (pentavalent element) are preferably phosphorus.
  • the n-type impurities are introduced substantially perpendicular to the first wafer main surface 101 by vertical ion implantation. This forms a plurality of source regions 16, 17.
  • the first mask 111 and the second mask 113 are removed.
  • the first mask 111 may be removed after the process of forming the body region 13 and before the process of forming the source regions 16, 17.
  • a second mask 113 is formed having a plurality of inner openings 114 that expose the regions in which the source regions 16, 17 are to be formed.
  • a process for forming a third mask 115 having a predetermined layout is performed.
  • the third mask 115 is placed on the first wafer main surface 101.
  • the third mask 115 has a plurality of openings 116 that expose the regions in which the plurality of contact regions 18 are to be formed.
  • the third mask 115 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask).
  • the third mask 115 may be formed from the same mask material as the second mask 113.
  • the contact region 18 formation process is carried out.
  • p-type impurities (trivalent elements) are implanted into the surface layer of the body region 13 by ion implantation through a plurality of openings 116 (third mask 115).
  • the p-type impurities are preferably aluminum.
  • the p-type impurities are introduced substantially perpendicular to the first wafer main surface 101 by vertical ion implantation. This forms the contact region 18.
  • the third mask 115 is removed. Through the above-mentioned fixing process, the body structure 12 is formed.
  • the insulating film 31 is formed in the form of a film on the first wafer main surface 101.
  • the insulating film 31 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation process (e.g., a thermal oxidation process).
  • the base electrode 117 is formed in the form of a film on the insulating film 31.
  • the base electrode 117 may be formed by a CVD method.
  • a step of forming a fourth mask 118 having a predetermined layout is performed.
  • the fourth mask 118 is disposed on the base electrode 117, and has an opening 119 that exposes areas other than the area where the gate electrode 32 is to be formed.
  • the fourth mask 118 may include either or both of an inorganic mask (a so-called hard mask) and an organic mask (a so-called soft mask).
  • the fourth mask 118 may be formed from the same mask material as the second mask 113, etc.
  • etching method may be either or both of a wet etching method and a dry etching method.
  • the gate electrode 32 is formed on the insulating film 31.
  • the remaining steps of forming the structure are carried out in sequence, and the wafer 100 is cut along the cutting lines 106. In this way, multiple semiconductor devices 1A are cut out from one wafer 100.
  • the semiconductor device 1A is manufactured through the steps including those described above.
  • FIG. 14 is an enlarged cross-sectional view showing a body structure 120 (hereinafter simply referred to as "body structure 120") according to a reference example.
  • the body structure 120 includes a body region 121 (hereinafter simply referred to as “body region 121”) according to a reference example instead of the body region 13.
  • the body region 121 is formed by single-stage or multi-stage (multi-stage in this embodiment) implantation of p-type impurities at different depth positions in the surface layer of the drift region 11 by vertical ion implantation through a first mask 111 in the p-type impurity implantation step shown in FIG. 13C.
  • the body region 121 is formed in the surface layer of the drift region 11 so that the body width WB does not decrease in the thickness direction, and does not have a peripheral portion that is inclined in an oblique direction (i.e., a body gradient GB).
  • the peripheral portion of the body region 121 extends along a direction perpendicular to the first main surface 3 (i.e., the vertical direction Z), and does not have either a sub-inclined portion 14 or a main inclined portion 15.
  • the body region 121 has an area other than the area near the lower end that is located on the vertical line Lz.
  • the body region 121 has multiple bulges 122 that jut out horizontally, similar to the bulges 19 of the body region 13 in the second to fourth embodiments (see Figures 10B to 10C).
  • p-type impurities are implanted with greater implantation energy and at a relatively high concentration compared to the region on the upper end side.
  • the implantation range of the p-type impurities is not controlled. Therefore, the implantation range of the p-type impurities expands horizontally as the implantation location becomes deeper due to the process conditions.
  • the multiple bulges 122 are formed in multiple stages so that they protrude outward in sequence from the upper end side to the lower end side, forming undulations with repeated projections and recesses.
  • the body region 121 is formed in a tapered shape so that the body width WB increases in the thickness direction. Even when p-type impurities are implanted in one stage using vertical ion implantation, the implantation range of the p-type impurities is expanded horizontally in the region on the lower end side of the body region 121 for the same reason as the lowest bulge 122.
  • FIG. 15A is a graph showing the concentration gradient in a first region of a body structure 120 according to a reference example.
  • the graph in FIG. 15A corresponds to the graph in FIG. 11A.
  • the first region of the body structure 120 is a region in the body region 121 in the second direction Y where neither the source regions 16, 17 nor the contact region 18 are formed.
  • the second region of the body structure 120 is both ends of the body region 121 in the second direction Y.
  • the vertical axis indicates the impurity concentration
  • the horizontal axis indicates the body width WB.
  • FIG. 15A shows a first reference concentration distribution RA1 (thin line), a second reference concentration distribution RA2 (thin dashed line), a third reference concentration distribution RA3 (thick line), and a fourth reference concentration distribution RA4 (thick dashed line).
  • the first to fourth reference concentration distributions RA1 to RA4 are to be contrasted with the above-mentioned first to fourth concentration distributions A1 to A4, respectively (see FIG. 11A).
  • the body region 121 has a nearly constant p-type impurity concentration in both the thickness direction and the horizontal direction, and has no concentration gradient. In other words, the body region 121 does not have a first concentration gradient portion 22 or a second concentration gradient portion 23. In addition, the body region 121 does not have a first high concentration region 24, a low concentration region 25, or a second high concentration region 26.
  • the periphery of the body region 121 is located on the same line.
  • the periphery of the body region 121 is located on a vertical line Lz that extends perpendicular to the first main surface 3 in the thickness direction, and does not have a body gradient GB.
  • FIG. 15B is a graph showing the concentration gradient in the second region of the body structure 120 according to the reference example.
  • the graph in FIG. 15B corresponds to the graph in FIG. 11B.
  • the second region of the body structure 120 is a region in the second direction Y in which both the source regions 16, 17 and the contact region 18 are formed in the body region 121.
  • the second region of the body structure 120 is the middle part of the body region 121 in the second direction Y.
  • the vertical axis indicates the impurity concentration
  • the horizontal axis indicates the body width WB.
  • FIG. 15B shows a first reference concentration distribution RB1 (thin line), a second reference concentration distribution RB2 (thin dashed line), a third reference concentration distribution RB3 (thick line), and a fourth reference concentration distribution RB4 (thick dashed line).
  • the first reference concentration distribution RB1 has a concentration distribution in which the n-type impurity concentration of the source regions 16, 17 and the p-type impurity concentration of the contact region 18 are added to the first reference concentration distribution RA1.
  • the second reference concentration distribution RB2 has a concentration distribution in which the n-type impurity concentration on the bottom side of the source regions 16, 17 and the p-type impurity concentration on the bottom side of the contact region 18 are added to the second reference concentration distribution RA2.
  • the third and fourth reference concentration distributions RB3 to RB4 correspond to the third and fourth reference concentration distributions RA3 to RA4, respectively.
  • the first to fourth reference concentration distributions RB1 to RB4 are contrasted with the above-mentioned first to fourth concentration distributions B1 to B4, respectively (see FIG. 11B).
  • the body region 121 has a nearly constant p-type impurity concentration in both the thickness direction and the horizontal direction, even in the second region, and does not have a concentration gradient. In other words, the body region 121 does not have the first concentration gradient portion 22 and the second concentration gradient portion 23 in the second region. Furthermore, the body region 121 does not have the first high concentration region 24, the low concentration region 25, and the second high concentration region 26 in the second region.
  • the periphery of the body region 121 is also located on the same line in the second region.
  • the periphery of the body region 121 is located on a vertical line Lz that extends perpendicular to the first main surface 3 in the thickness direction in the second region, and does not have a body gradient GB.
  • the surface drift region 27 is formed so that the drift width WD decreases in the thickness direction following the periphery of the body regions 121 (see FIG. 14). Therefore, the surface drift region 27 forms a current path that narrows in the thickness direction in the region between the body regions 121, and exhibits a current confinement effect. As a result, the JFET resistance component increases. Also, the current density in the region between the body regions 121 increases, and the electric field concentrates on the periphery of the body regions 121.
  • the semiconductor device 1A includes a chip 2, an n-type drift region 11, and a p-type body region 13.
  • the chip 2 has a first main surface 3.
  • the drift region 11 is formed in a surface layer portion of the first main surface 3.
  • the body region 13 is formed in a tapered shape in the surface layer portion of the drift region 11 so that its horizontal width (WB) decreases in the thickness direction, and has a peripheral portion that is inclined obliquely relative to the first main surface 3.
  • This configuration provides a semiconductor device 1A having a new configuration for the body region 13.
  • the current path near the body region 13 in the surface layer of the drift region 11 is horizontally extended by the peripheral portion of the body region 13.
  • the chip 2 preferably includes a SiC single crystal. This configuration provides a SiC semiconductor device having a novel configuration for the body region 13.
  • the body region 13 is preferably formed so that its width decreases in the thickness direction starting from the upper end on the first main surface 3 side.
  • the body region 13 preferably has a peripheral portion that is inclined obliquely starting from the upper end.
  • the body region 13 preferably has a thickness of 0.5 ⁇ m or more, and has a gradient (GB) such that, when the upper end of the periphery is taken as the reference position, the horizontal change in the periphery at the thickness position of 0.5 ⁇ m is 0.05 ⁇ m or more.
  • the body region 13 may have a concentration gradient that gradually decreases in the thickness direction.
  • the body region 13 may have a first high concentration region 24 on the inner side and a low concentration region 25 on the peripheral side in the horizontal direction, and may have a concentration gradient that gradually decreases from the first high concentration region 24 to the low concentration region 25.
  • the first high concentration region 24 may have a portion formed in a region below the middle part of the body region 13.
  • the low concentration region 25 may have a portion formed in a region below the middle part of the body region 13.
  • the first high concentration region 24 may have a concentration gradient that gradually decreases in the thickness direction.
  • the low concentration region 25 may have a concentration gradient that gradually decreases in the thickness direction.
  • the concentration difference between the first high concentration region 24 and the low concentration region 25 may gradually decrease toward the bottom of the body region 13.
  • the peripheral portion of the body region 13 may have multiple bulges 19 that protrude horizontally in multiple stages in the thickness direction.
  • the semiconductor device 1A may include a plurality of body regions 13 formed at intervals in the surface layer portion of the drift region 11.
  • the semiconductor device 1A may include an n-type surface drift region 27 partitioned in a region between the plurality of body regions 13 in the surface layer portion of the drift region 11.
  • the surface drift region 27 is partitioned so that its horizontal width (WD) gradually increases in the thickness direction, and forms a JFET structure with the plurality of body regions 13.
  • the surface drift region 27 forms a current path that spreads in the thickness direction in the region between the multiple body regions 13, reducing current constriction. This reduces the JFET resistance component of the JFET structure.
  • the surface drift region 27 also reduces the current density in the region between the multiple body regions 13, mitigating electric field concentration on the periphery of the multiple body regions 13.
  • the semiconductor device 1A may include n-type source regions 16, 17.
  • the source regions 16, 17 may have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 11, and may be formed in the surface layer of the body region 13.
  • the semiconductor device 1A may include a p-type contact region 18.
  • the contact region 18 may have a p-type impurity concentration higher than the p-type impurity concentration of the body region 13, and may be formed in the surface layer of the body region 13.
  • the semiconductor device 1A may include a chip 2, an n-type drift region 11, a p-type body region 13, and a p-type contact region 18.
  • the chip 2 has a first main surface 3.
  • the drift region 11 is formed in a surface layer portion of the first main surface 3.
  • the body region 13 is formed in a surface layer portion of the drift region 11.
  • the contact region 18 has a p-type impurity concentration higher than the p-type impurity concentration of the body region 13, and is formed in the surface layer portion of the body region 13.
  • the body region 13 includes a first high concentration region 24 in a thickness range below the contact region 18.
  • the body region 13 includes a low concentration region 25 formed in a region on the peripheral side of the first high concentration region 24 in a thickness range below the contact region 18.
  • the first high concentration region 24 preferably has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 18.
  • the low concentration region 25 preferably has a p-type impurity concentration lower than the p-type impurity concentration of the first high concentration region 24.
  • the semiconductor device 1A may include n-type source regions 16, 17 formed in the surface layer of the body region 13.
  • the low concentration region 25 is formed in a thickness range below the source regions 16, 17. This configuration prevents the n-type impurity concentration of the source regions 16, 17 from being offset by the p-type impurity concentration of the first high concentration region 24. Therefore, the function of the source regions 16, 17 is properly ensured.
  • the body region 13 may have a peripheral portion that is inclined obliquely with respect to the first main surface 3. With this configuration, the current path near the body region 13 in the surface layer of the drift region 11 is expanded horizontally by the peripheral portion of the body region 13. This suppresses an increase in the resistance value near the body region 13.
  • FIG. 16 is a cross-sectional view showing a semiconductor device 1B according to the second embodiment.
  • the semiconductor device 1B includes a plurality of p-type column regions 130 formed in the drift region 11 within a thickness range below a plurality of body regions 13.
  • the plurality of column regions 130 have a p-type impurity concentration lower than the p-type impurity concentration of the contact region 18.
  • the p-type impurity concentration of the plurality of column regions 130 may be lower than the p-type impurity concentration of the body region 13.
  • the p-type impurity concentration of the plurality of column regions 130 may be not less than 1 ⁇ 10 16 cm ⁇ 3 and not more than 5 ⁇ 10 17 cm ⁇ 3 .
  • the multiple column regions 130 are arranged at intervals in the first direction X, and are each formed in a strip shape extending in the second direction Y. In other words, the multiple column regions 130 are formed in stripes extending in the second direction Y along the multiple body regions 13. In addition, the extension direction of the multiple body structures 12 coincides with the off-direction of the SiC single crystal.
  • the multiple column regions 130 are formed in a columnar shape extending in the thickness direction in a cross-sectional view, and overlap the multiple body regions 13 in a one-to-one correspondence.
  • the multiple column regions 130 may have a single-layer structure consisting of a single p-type impurity region, or may have a layered structure in which multiple p-type impurity regions are layered in the thickness direction.
  • the configuration of one column region 130 will be specifically described below.
  • the column region 130 has a column width WC less than the body width WB of the body region 13, and is formed with a space inward from the peripheral portion (main inclined portion 15) of the body region 13 (see also Figures 7, 10A, etc.). This suppresses electrical interference of the column region 130 with the peripheral portion of the body region 13.
  • the column width WC is greater than the width of the contact region 18.
  • the column width WC is adjusted appropriately according to the body width WB.
  • the column region 130 has a column thickness TC that is greater than the body thickness TB of the body region 13 (see also Figures 7, 10A, etc.).
  • the column thickness TC is less than the thickness of the drift region 11.
  • the column thickness TC is adjusted appropriately depending on the thickness of the drift region 11.
  • the column region 130 crosses the middle part of the drift region 11 in the thickness direction.
  • the column region 130 has a lower end and an upper end.
  • the lower end of the column region 130 is located on the bottom side of the drift region 11 with respect to the middle part of the drift region 11.
  • the lower end of the column region 130 may be formed with a gap from the bottom of the drift region 11 toward the body region 13.
  • the lower end of the column region 130 may cross the bottom of the drift region 11 and be located in the surface part of the drain region 10.
  • the upper end of the column region 130 is located on the bottom (lower end) side of the body region 13 with respect to the middle part of the drift region 11.
  • the upper end of the column region 130 is preferably connected to the bottom of the body region 13.
  • the column region 130 is preferably electrically connected to the body region 13.
  • the upper end of the column region 130 may be formed with a gap from the bottom of the body region 13 to the bottom side of the drift region 11, and may face the body region 13 with a part of the drift region 11 in between.
  • the semiconductor device 1B includes a plurality of n-type intermediate drift regions 131 formed within the drift region 11.
  • Each of the plurality of intermediate drift regions 131 is composed of an area partitioned by a plurality of column regions 130 in the drift region 11.
  • the intermediate drift region 131 may have an n-type impurity concentration higher than the n-type impurity concentration of the drift region 11, or may have an n-type impurity concentration lower than the n-type impurity concentration of the drift region 11.
  • the intermediate drift region 131 may have an n-type impurity concentration higher than the n-type impurity concentration of the surface drift region 27, or may have an n-type impurity concentration lower than the n-type impurity concentration of the surface drift region 27.
  • the intermediate drift regions 131 are arranged alternately with the column regions 130 in the first direction X, and are each formed in a strip shape extending in the second direction Y. In other words, the intermediate drift regions 131 are formed in a strip shape extending in the second direction Y along the column regions 130.
  • the extension direction of the intermediate drift regions 131 coincides with the off-direction of the SiC single crystal.
  • the intermediate drift regions 131 are formed in a columnar shape extending in the thickness direction in a cross-sectional view, and are connected to the surface drift regions 27 in a one-to-one correspondence.
  • Each of the intermediate drift regions 131 has an intermediate drift width WDM that is larger than the drift width WD of the surface drift regions 27, and has both ends connected to two body regions 13 adjacent to each other in the first direction X.
  • the intermediate drift regions 131 form multiple pn junctions having charge balance together with the column regions 130 in the thickness range below the body region 13.
  • the state of having charge balance means that for adjacent column regions 130, the depletion layer extending from one pn junction and the depletion layer extending from the other pn junction are connected within the intermediate drift regions 131.
  • the intermediate drift regions 131 form a superjunction structure with the column regions 130 in the region below the body region 13.
  • the process of forming the multiple column regions 130 includes a mask formation process and a p-type impurity injection process.
  • a mask formation process a mask having openings that expose the regions in which the multiple column regions 130 are to be formed is formed on the first wafer main surface 101.
  • p-type impurity injection process p-type impurities are injected into the drift region 11 by ion implantation through the mask.
  • the ion implantation method is preferably a channeling ion implantation method.
  • p-type impurities are implanted along a channel axis (e.g., the c-axis) in which the atomic rows are sparse among the crystal axes of the chip 2 (second semiconductor layer 7).
  • the p-type impurities are implanted deep into the drift region 11 while repeatedly undergoing small-angle scattering due to the channeling effect.
  • the probability of collision of trivalent elements with the atomic rows of the SiC single crystal is reduced. As a result, multiple column regions 130 are formed.
  • the process of forming the column region 130 may be performed after the process of forming the body region 13.
  • the column region 130 is formed inside the drift region 11 so as to be connected to the body region 13 in the thickness direction.
  • the process of forming the column region 130 is preferably performed before the process of forming the body region 13.
  • the body region 13 is formed in the surface layer portion of the drift region 11 so as to be connected to the column region 130 in the thickness direction.
  • the process of forming the body region 13 is carried out after the process of forming the column region 130, so deformation of the body region 13 (particularly deformation of the peripheral portion of the body region 13) caused by the process of injecting the p-type impurity into the column region 130 is suppressed.
  • concentration changes in the body region 13 caused by the process of injecting the p-type impurity into the column region 130 are suppressed.
  • semiconductor device 1B includes a p-type column region 130 in addition to the configuration of semiconductor device 1A.
  • the column region 130 is formed in the drift region 11 in a thickness range below the body region 13.
  • This configuration provides a superjunction type semiconductor device 1B in which an increase in resistance value near the body region 13 is suppressed.
  • chip 2 includes SiC single crystal, a superjunction type SiC semiconductor device having a novel configuration for the body region 13 is provided.
  • the multiple column regions 130 are formed in stripes extending in the second direction Y along the multiple body regions 13.
  • the multiple column regions 130 may also be formed in stripes extending in the first direction X and arranged at intervals in the second direction Y.
  • the extension direction of the multiple column regions 130 may intersect (specifically, perpendicular to) the off-direction of the SiC single crystal.
  • the multiple column regions 130 intersect (specifically, perpendicular to) the multiple body regions 13.
  • the multiple column regions 130 may be arranged at intervals in an intersecting direction that intersects both the first direction X and the second direction Y, and may each be formed in a strip shape extending in an orthogonal direction that is perpendicular to the intersecting direction.
  • the extension direction of the multiple column regions 130 may intersect with the off-direction of the SiC single crystal.
  • the multiple column regions 130 intersect with the multiple body regions 13.
  • the multiple body regions 13 are formed in stripes extending in the second direction Y.
  • the multiple body regions 13 may each be formed in a band extending in the first direction X and arranged at intervals in the second direction Y.
  • the multiple body regions 13 may be formed in stripes extending in the first direction X.
  • the extension direction of the multiple body regions 13 may intersect (specifically, perpendicular to) the off-direction of the SiC single crystal.
  • the multiple column regions 130 may be formed in stripes extending in the first direction X and arranged at intervals in the second direction Y.
  • the multiple column regions 130 may be formed in stripes extending in the first direction X along the multiple body regions 13.
  • the multiple column regions 130 may be arranged at intervals in the first direction X and each formed in a band shape extending in the second direction Y. In other words, the multiple column regions 130 may be formed in a stripe shape extending in the second direction Y. Furthermore, the extension direction of the multiple column regions 130 may coincide with the off-direction of the SiC single crystal.
  • the multiple column regions 130 intersect (specifically, perpendicular to) the multiple body regions 13.
  • the multiple column regions 130 may be arranged at intervals in a cross direction that intersects both the first direction X and the second direction Y, and each may be formed in a band shape extending in a perpendicular direction perpendicular to the cross direction.
  • FIG. 17 is a cross-sectional view showing a modified example of the field region 42.
  • FIG. 17 illustrates a configuration in which the field region 42 according to the modified example is applied to the semiconductor device 1A.
  • the field region 42 according to the modified example can also be applied to the semiconductor device 1B.
  • the single field region 42 is formed in a region between the periphery of the first main surface 3 and the plurality of body regions 13 (active regions 8), spaced inward from the periphery of the first main surface 3. Specifically, the single field region 42 is formed in the region between the periphery of the first main surface 3 and the outer body region 35. More specifically, the single field region 42 is formed in the region between the periphery of the first main surface 3 and the termination region 40.
  • the single field region 42 is formed in a band shape extending along the multiple body regions 13 (termination regions 40) in a plan view.
  • the single field region 42 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the single field region 42 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) surrounding the multiple body regions 13 (termination regions 40) in a plan view.
  • the single field region 42 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the ratio of the width of a single field region 42 to the perimeter width may be 0.1 or more and less than 1.
  • the perimeter width is the width of the perimeter region 9.
  • the width of the perimeter region 9 may be defined by the width between the periphery of the first major surface 3 and the active region 8 (e.g., the inner edge of the outer body region 35).
  • the width ratio may have a value that falls within at least one of the following ranges: 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or more and 0.6 or more and 0.8 or less, and 0.8 or more and less than 1.
  • the single field region 42 is formed at a distance from the bottom of the drift region 11 toward the first main surface 3, and faces the drain region 10 across a portion of the drift region 11. It is preferable that the single field region 42 is formed at a distance from the depth position of the middle part of the drift region 11 toward the first main surface 3. Of course, the single field region 42 may cross the depth position of the middle part of the drift region 11 in the thickness direction.
  • the single field region 42 has an inner edge on the termination region 40 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the single field region 42 is connected to the outer edge of the termination region 40.
  • the single field region 42 is electrically connected to the termination region 40.
  • the inner edge of the single field region 42 is connected to the outer edge of the termination region 40 around the entire periphery.
  • the p-type impurity concentration of the single field region 42 is the same as that of the semiconductor device 1A.
  • the single field region 42 may be extended from the termination region 40 to the surface portion of the drift region 11 as an extension portion of the termination region 40.
  • the termination region 40 may have a single field region 42 as an extension portion.
  • the p-type impurity concentration of the single field region 42 may be different from the p-type impurity concentration of the termination region 40.
  • the single field region 42 may be formed at a distance from the termination region 40.
  • FIG. 18 is a cross-sectional view showing a first modified example of a source pad electrode 60.
  • FIG. 18 illustrates a configuration in which the modified source pad electrode 60 is applied to a semiconductor device 1A.
  • the modified field region 42 can be applied to a semiconductor device 1B.
  • the multiple first buried electrodes 62 are buried in the multiple source openings 54 so as to expose the insulating surface 51.
  • the source pad electrode 60 may have multiple first buried electrodes 62 that are pulled out from the multiple source openings 54 onto the insulating surface 51 and cover the insulating surface 51.
  • the multiple first buried electrodes 62 cover the first base electrode film 61 on the insulating surface 51, and have a portion that covers the insulating surface 51 with the first base electrode film 61 in between.
  • the multiple first buried electrodes 62 each have a first buried electrode surface 66 that is exposed from the multiple source openings 54 above the insulating surface 51.
  • the multiple first buried electrodes 62 have a portion that faces the gate electrode 32 with the first base electrode film 61 and interlayer film 50 in between in the stacking direction (vertical direction Z).
  • the multiple first buried electrodes 62 are integrated on the insulating surface 51 to form a single intermediate electrode 135.
  • the intermediate electrode 135 (multiple first buried electrodes 62) covers the entire area of the first base electrode film 61.
  • the electrode surface (first buried electrode surface 66) of the intermediate electrode 135 is positioned above the insulating surface 51.
  • the first main electrode film 63 is mechanically and electrically connected to the first buried electrode surfaces 66 of the multiple first buried electrodes 62 (intermediate electrodes 135) above the insulating surface 51.
  • the first main electrode film 63 has a portion that faces the insulating surface 51, sandwiching the multiple first buried electrodes 62 (intermediate electrodes 135).
  • the first main electrode film 63 does not have a mechanical connection to the first base electrode film 61.
  • the configuration of the multiple first buried electrodes 62 (intermediate electrodes 135) in the modified example can also be applied to the multiple first buried electrodes 62 of the source finger electrodes 68.
  • the configuration of the multiple first buried electrodes 62 (intermediate electrodes 135) in the modified example can also be applied to the multiple second buried electrodes 72 of the gate finger electrodes 70.
  • FIG. 19 is a cross-sectional view showing a second modified example of a source pad electrode 60.
  • FIG. 19 illustrates a configuration in which the modified source pad electrode 60 is applied to a semiconductor device 1A.
  • the modified field region 42 can be applied to a semiconductor device 1B.
  • the source pad electrode 60 has a plurality of first buried electrodes 62.
  • the source pad electrode 60 does not necessarily have to have the first buried electrodes 62.
  • the first main electrode film 63 of the source pad electrode 60 penetrates into the plurality of source openings 54 from above the interlayer film 50, and is electrically connected to the body region 13, etc. within the plurality of source openings 54.
  • the source finger electrode 68 does not necessarily have to have the first buried electrode 62.
  • the first main electrode film 63 of the source finger electrode 68 enters the multiple outer openings 56 from above the interlayer film 50 and is electrically connected to the termination region 40 (overlap region 41) within the multiple outer openings 56.
  • the gate finger electrode 70 does not necessarily have to have the second buried electrode 72.
  • the second main electrode film 73 of the gate finger electrode 70 penetrates into the multiple gate openings 58 from above the interlayer film 50 and is electrically connected to the gate wiring 44 within the multiple gate openings 58.
  • Semiconductor devices 1A and 1B may have a first buried electrode 62 associated with a source pad electrode 60, but may not have a first buried electrode 62 associated with a source finger electrode 68. Semiconductor devices 1A and 1B may have a first buried electrode 62 associated with a source finger electrode 68, but may not have a first buried electrode 62 associated with a source pad electrode 60.
  • Semiconductor devices 1A and 1B may have a first buried electrode 62 associated with the source pad electrode 60, but may not have a second buried electrode 72.
  • Semiconductor devices 1A and 1B may have a second buried electrode 72, but may not have a first buried electrode 62 associated with the source pad electrode 60.
  • Semiconductor devices 1A and 1B may have a first buried electrode 62 associated with the source finger electrode 68, but may not have a second buried electrode 72.
  • Semiconductor devices 1A and 1B may have a second buried electrode 72, but may not have a first buried electrode 62 associated with the source finger electrode 68.
  • the chip 2 including a SiC single crystal is used.
  • the chip 2 may include a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • a wide band gap semiconductor is a semiconductor that has a band gap larger than the band gap of silicon. Examples of single crystals of wide band gap semiconductors include gallium nitride, gallium oxide, and diamond.
  • the chip 2 may also include a silicon single crystal.
  • the first semiconductor layer 6 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • the first semiconductor layer 6 may contain gallium nitride, gallium oxide, diamond, etc.
  • the first semiconductor layer 6 may contain a silicon single crystal.
  • the second semiconductor layer 7 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • the second semiconductor layer 7 may contain gallium nitride, gallium oxide, diamond, etc.
  • the second semiconductor layer 7 may also contain a silicon single crystal.
  • an n-type drain region 10 is shown.
  • a p-type collector region (10) may be used instead of the n-type drain region 10.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type collector region (10) may be an impurity region containing p-type impurities implanted into the surface layer of the second main surface 4 of the n-type chip 2 (n-type chip 2) by ion implantation.
  • a semiconductor device (1A, 1B) including: a chip (2) having a main surface (3); a drift region (11) of a first conductivity type (n-type) formed on a surface layer of the main surface (3); and a body region (13) of a second conductivity type (p-type) formed in a tapered shape on the surface layer of the drift region (11) such that its horizontal width (WB) decreases in the thickness direction, and having a peripheral portion inclined obliquely with respect to the main surface (3).
  • WB horizontal width
  • A3 The semiconductor device (1A, 1B) described in A1 or A2, in which the body region (13) is formed such that the width (WB) decreases in the thickness direction starting from the upper end on the main surface (3) side, and has a peripheral portion that is inclined obliquely starting from the upper end.
  • A4 The semiconductor device (1A, 1B) described in A3, in which the body region (13) has a thickness (TB) of 0.5 ⁇ m or more, and has a gradient (GB) in which the horizontal change in the peripheral portion at a thickness position of 0.5 ⁇ m is 0.05 ⁇ m or more when the upper end of the peripheral portion is taken as a reference position.
  • TB thickness
  • GB gradient
  • a semiconductor device (1A, 1B) according to any one of A1 to A9, further comprising: a plurality of body regions (13) formed at intervals in the surface layer portion of the drift region (11); and a surface drift region (27) of a first conductivity type (n-type) that is partitioned into regions between the plurality of body regions (13) such that the horizontal width (WD) increases in the thickness direction in the surface layer portion of the drift region (11), and forms a JFET structure with the plurality of body regions (13).
  • n-type first conductivity type
  • n-type impurity region (16, 17) formed in a surface layer portion of the body region (13) and having a higher impurity concentration than the impurity concentration of the drift region (11)
  • p-type second conductivity type
  • p-type second conductivity type
  • a semiconductor device (1A, 1B) including a chip (2) having a main surface (3), a drift region (11) of a first conductivity type (n-type) formed in a surface layer of the main surface (3), a body region (13) of a second conductivity type (p-type) formed in a surface layer of the drift region (11), and a contact region (18) of the second conductivity type (p-type) formed in the surface layer of the body region (13) and having an impurity concentration higher than the impurity concentration of the body region (13), the body region (13) including a high concentration region (24) formed in a thickness range below the contact region (18) and a low concentration region (25) formed in a region on the peripheral side of the high concentration region (24) in the thickness range.
  • a method for manufacturing a semiconductor device (1A, 1B) including the steps of: preparing a wafer (100) having a drift region (11) of a first conductivity type (n-type) in the surface layer of a main surface (101); and injecting impurities of a second conductivity type (p-type) into the surface layer of the drift region (11) so that the horizontal injection range decreases in the thickness direction, thereby forming a body region (13) of a second conductivity type (p-type) having a peripheral portion inclined obliquely with respect to the main surface (101).

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11274173A (ja) * 1998-03-20 1999-10-08 Denso Corp 炭化珪素半導体装置の製造方法
JP2004040088A (ja) * 2002-05-01 2004-02-05 Internatl Rectifier Corp 傾斜ボディーダイオード接合を備え抵抗を低減させた放射線耐久型ｍｏｓｆｅｔ
JP2004319964A (ja) * 2003-03-28 2004-11-11 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2016039263A (ja) * 2014-08-07 2016-03-22 株式会社東芝 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11274173A (ja) * 1998-03-20 1999-10-08 Denso Corp 炭化珪素半導体装置の製造方法
JP2004040088A (ja) * 2002-05-01 2004-02-05 Internatl Rectifier Corp 傾斜ボディーダイオード接合を備え抵抗を低減させた放射線耐久型ｍｏｓｆｅｔ
JP2004319964A (ja) * 2003-03-28 2004-11-11 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2016039263A (ja) * 2014-08-07 2016-03-22 株式会社東芝 半導体装置の製造方法

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