CN121014270A - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法Info
- Publication number
- CN121014270A CN121014270A CN202480020671.6A CN202480020671A CN121014270A CN 121014270 A CN121014270 A CN 121014270A CN 202480020671 A CN202480020671 A CN 202480020671A CN 121014270 A CN121014270 A CN 121014270A
- Authority
- CN
- China
- Prior art keywords
- region
- film
- main
- concentration
- electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
- H10D62/107—Buried supplementary regions, e.g. buried guard rings
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/40—Crystalline structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/60—Impurity distributions or concentrations
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
- H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
- H10D62/8325—Silicon carbide
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10P30/00—Ion implantation into wafers, substrates or parts of devices
- H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
Landscapes
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2023056619 | 2023-03-30 | ||
| JP2023-056619 | 2023-03-30 | ||
| PCT/JP2024/012559 WO2024204492A1 (ja) | 2023-03-30 | 2024-03-28 | 半導体装置およびその製造方法 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN121014270A true CN121014270A (zh) | 2025-11-25 |
Family
ID=92905813
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202480020671.6A Pending CN121014270A (zh) | 2023-03-30 | 2024-03-28 | 半导体装置及其制造方法 |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US20260032950A1 (https=) |
| JP (1) | JPWO2024204492A1 (https=) |
| CN (1) | CN121014270A (https=) |
| DE (1) | DE112024001516T5 (https=) |
| WO (1) | WO2024204492A1 (https=) |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3968860B2 (ja) * | 1998-03-20 | 2007-08-29 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
| US6747312B2 (en) * | 2002-05-01 | 2004-06-08 | International Rectifier Corporation | Rad hard MOSFET with graded body diode junction and reduced on resistance |
| JP2004319964A (ja) * | 2003-03-28 | 2004-11-11 | Mitsubishi Electric Corp | 半導体装置及びその製造方法 |
| JP2016039263A (ja) * | 2014-08-07 | 2016-03-22 | 株式会社東芝 | 半導体装置の製造方法 |
-
2024
- 2024-03-28 DE DE112024001516.6T patent/DE112024001516T5/de active Pending
- 2024-03-28 CN CN202480020671.6A patent/CN121014270A/zh active Pending
- 2024-03-28 JP JP2025511113A patent/JPWO2024204492A1/ja active Pending
- 2024-03-28 WO PCT/JP2024/012559 patent/WO2024204492A1/ja not_active Ceased
-
2025
- 2025-09-29 US US19/342,707 patent/US20260032950A1/en active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US20260032950A1 (en) | 2026-01-29 |
| DE112024001516T5 (de) | 2026-01-29 |
| JPWO2024204492A1 (https=) | 2024-10-03 |
| WO2024204492A1 (ja) | 2024-10-03 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |