WO2024204084A1 - 積層セラミック電子部品 - Google Patents

積層セラミック電子部品 Download PDF

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Publication number
WO2024204084A1
WO2024204084A1 PCT/JP2024/011734 JP2024011734W WO2024204084A1 WO 2024204084 A1 WO2024204084 A1 WO 2024204084A1 JP 2024011734 W JP2024011734 W JP 2024011734W WO 2024204084 A1 WO2024204084 A1 WO 2024204084A1
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WO
WIPO (PCT)
Prior art keywords
spacer
multilayer ceramic
electronic component
ceramic electronic
component according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/011734
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English (en)
French (fr)
Japanese (ja)
Inventor
孝太 善哉
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to CN202480021993.2A priority Critical patent/CN121014090A/zh
Priority to JP2025510869A priority patent/JPWO2024204084A1/ja
Priority to KR1020257023887A priority patent/KR20250121127A/ko
Publication of WO2024204084A1 publication Critical patent/WO2024204084A1/ja
Priority to US19/339,678 priority patent/US20260024699A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H01G2/065—Mountings specially adapted for mounting on a printed-circuit support for surface mounting, e.g. chip capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/24—Distinguishing marks, e.g. colour coding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/224—Housing; Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H01G4/2325—Terminals electrically connecting two or more layers of a stacked or rolled capacitor characterised by the material of the terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors

Definitions

  • the present invention relates to multilayer ceramic electronic components such as multilayer ceramic capacitors.
  • a multilayer ceramic capacitor has an inner layer in which dielectric layers and internal electrodes are alternately stacked. Dielectric layers are then placed on the top and bottom of the inner layer as outer layers to form a rectangular parallelepiped laminate, and external electrodes are provided on both longitudinal end faces of the laminate to form the capacitor body.
  • a multilayer ceramic capacitor that includes a spacer formed on the side of the capacitor body that is mounted on the board so as to cover part of the external electrode.
  • the spacer may peel off, and the durability of the capacitor when mounted is insufficient.
  • the objective of the present invention is to provide a multilayer ceramic capacitor that has improved adhesion between the capacitor body and the spacer, and has excellent durability when mounted.
  • spacers containing phenolic resin have strong adhesion to the capacitor body and are highly durable when mounted, which led to the completion of this invention.
  • the present invention provides a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, the laminate having two main faces opposing each other in a lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side faces opposing each other in a width direction intersecting the lamination direction and the length direction; two external electrodes connected to the internal electrode layers at each of the two end faces, and covering the end faces and subsequent thereto, a portion of the two opposing main faces, a portion of the two opposing side faces, or a portion of the main faces and a portion of the side faces; two spacers arranged on one of the two main surfaces or one of the two side surfaces of the laminate;
  • the spacer is a multilayer ceramic electronic component that contains metal powder and phenolic resin.
  • the present invention makes it possible to increase the adhesive strength between the capacitor body and the spacer, thereby providing a multilayer ceramic capacitor with excellent durability when mounted.
  • FIG. 1 is a diagram showing the external appearance of a multilayer ceramic capacitor 1.
  • FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line II-II shown in FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 taken along line III-III shown in FIG. 3 is an enlarged cross-sectional view of the spacer 4 shown in FIG. 2.
  • 2 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 1.
  • 3A to 3C are diagrams illustrating a laminate manufacturing step S1, a base electrode layer forming step S2, and a first plating layer forming step S3.
  • 11A to 11C are diagrams illustrating a spacer arrangement step S4 and a second plating layer formation step S5.
  • FIG. 1 is a cross-sectional view showing a multilayer ceramic capacitor 1 in which a second plating layer 32 is not disposed.
  • 1 is a cross-sectional view of a multilayer ceramic capacitor 1 in which a reinforcing material 50 is disposed.
  • FIG. 11 is a diagram illustrating a reinforcing material placement step S6.
  • a multilayer ceramic capacitor 1 will be described as an embodiment of a multilayer ceramic electronic component of the present invention, but the present invention is not limited thereto.
  • the drawings may be drawn in a schematic and simplified manner in order to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match those dimensional ratios described in the specification.
  • components described in the specification may be omitted in the drawings, or may be drawn with the number of components omitted.
  • FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 1 according to an embodiment.
  • FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to an embodiment taken along line II-II in FIG. 1.
  • FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to an embodiment taken along line III-III in FIG. 1.
  • the multilayer ceramic capacitor 1 is substantially rectangular and includes a capacitor body 1A having a laminate 2 and a pair of external electrodes 3 provided at both ends of the laminate 2, and a spacer 4 attached to the capacitor body 1A.
  • the laminate 2 also includes an inner layer 11 in which a dielectric layer 14 and an internal electrode layer 15 are laminated.
  • the terms used to indicate the orientation of the multilayer ceramic capacitor 1 are the length direction L, which is the direction in which the pair of external electrodes 3 are provided in the multilayer ceramic capacitor 1.
  • the direction in which the dielectric layers 14 and the internal electrode layers 15 are stacked is the stacking direction T.
  • the direction that intersects both the length direction L and the stacking direction T is the width direction W. Note that in this embodiment, the width direction W is perpendicular to both the length direction L and the stacking direction T.
  • Outer surface of laminate 2 Among the six outer surfaces of the laminate 2, a pair of outer surfaces facing each other in the stacking direction T is referred to as a first main surface A1 and a second main surface A2, a pair of outer surfaces facing each other in the width direction W is referred to as a first side surface B1 and a second side surface B2, and a pair of outer surfaces facing each other in the length direction L is referred to as a first end surface C1 and a second end surface C2.
  • first main surface A1 and the second main surface A2 When it is not necessary to particularly distinguish between the first main surface A1 and the second main surface A2, they will be collectively referred to as a main surface A, when it is not necessary to particularly distinguish between the first side surface B1 and the second side surface B2, they will be collectively referred to as a side surface B, and when it is not necessary to particularly distinguish between the first end surface C1 and the second end surface C2, they will be collectively referred to as an end surface C.
  • the laminate 2 preferably has rounded ridges R1, including the corners.
  • the ridges R1 are the intersections of two surfaces of the laminate 2, i.e., the main surface A and the side surface B, the main surface A and the end surface C, or the side surface B and the end surface C.
  • the laminate 2 comprises an inner layer portion 11 that forms a capacitance, an outer layer portion 12 that is arranged to sandwich the inner layer portion 11 in the stacking direction T, and a side gap portion 16 that is arranged to sandwich the inner layer portion 11 and the outer layer portion 12 in the width direction W.
  • the inner layer portion 11 includes dielectric layers 14 and internal electrode layers 15 that are alternately stacked along a stacking direction T.
  • the dielectric layer 14 is made of a ceramic material, such as a dielectric ceramic containing BaTiO3 as a main component.
  • the internal electrode layer 15 includes a plurality of first internal electrode layers 15a and a plurality of second internal electrode layers 15b.
  • the first internal electrode layers 15a and the second internal electrode layers 15b are alternately arranged.
  • the first internal electrode layer 15a includes a first opposing portion 152a facing the second internal electrode layer 15b, and a first lead portion 151a drawn from the first opposing portion 152a to the first end face C1 side. An end of the first lead portion 151a is exposed to the first end face C1 and is electrically connected to the first external electrode 3a described later.
  • the second internal electrode layer 15b includes a second opposing portion 152b facing the first internal electrode layer 15a, and a second lead portion 151b drawn from the second opposing portion 152b to the second end face C2. An end of the second lead portion 151b is electrically connected to the second external electrode 3b described later. Charges are stored in the first opposing portions 152a of the first internal electrode layers 15a and the second opposing portions 152b of the second internal electrode layers 15b.
  • the internal electrode layer 15 is preferably formed from a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), a silver-palladium (Ag-Pd) alloy, or gold (Au).
  • a metal material such as nickel (Ni), copper (Cu), silver (Ag), palladium (Pd), a silver-palladium (Ag-Pd) alloy, or gold (Au).
  • the outer layer portion 12 can be formed of the same material as the dielectric layer 14 of the inner layer portion 11 .
  • the multilayer ceramic capacitor 1 includes a first side gap portion 16a that is disposed so as to sandwich the inner layer portion 11 and the outer layer portion 12 in the width direction W and that forms a first side surface B1 of the multilayer ceramic capacitor 1, and a second side gap portion 16b that forms a second side surface B2 of the multilayer ceramic capacitor 1.
  • the side gap portion 16 can be formed of the same material as the dielectric layer 14.
  • the external electrode 3 includes a first external electrode 3a provided on the first end face C1 and a second external electrode 3b provided on the second end face C2.
  • the external electrode 3 covers not only the end face C but also a part of the main face A and the side face B continuing from the end face C.
  • the end of the first extension portion 151a of the first internal electrode layer 15a is exposed to the first end face C1 and is electrically connected to the first external electrode 3a.
  • the end of the second extension portion 151b of the second internal electrode layer 15b is exposed to the second end face C2 and is electrically connected to the second external electrode 3b.
  • the external electrode 3 also includes, for example, a base electrode layer 30 and a first plating layer 31. However, it is not necessarily required that the external electrode 3 has such a layered structure.
  • the base electrode layer 30 is formed, for example, by applying and baking a conductive paste containing copper (Cu).
  • the base electrode layer 30 may also contain glass or ceramic materials.
  • the first plating layer 31 includes a first nickel (Ni) plating layer 31a disposed on the surface of the base electrode layer 30, and a first tin (Sn) plating layer 31b disposed on the surface of the first nickel (Ni) plating layer 31a. Note that the configuration of the first plating layer 31 is not limited to this.
  • the spacer 4 includes a pair of a first spacer 4a and a second spacer 4b.
  • the first spacer 4a is disposed on one end face C1 side in the length direction L on the second main surface A2 side, which is the substrate mounting surface of the capacitor body 1A
  • the second spacer 4b is disposed on the other end face C2 side.
  • the substrate mounting surface of the capacitor body 1A is the first side face B1
  • the first spacer 4a is disposed on one end face C1 side in the length direction L on the first side face B1 side, which is the substrate mounting surface of the capacitor body 1A
  • the second spacer 4b is disposed on the other end face C2 side.
  • the spacer 4 is disposed on the external electrode 3 of the capacitor body 1A and on the surface of the second main surface A2 of the laminate 2 on which the subsequent external electrode 3 is not disposed.
  • the spacer 4 is disposed on the external electrode 3 of the capacitor body 1A and on the surface of the first side surface B1 of the laminate 2 on which the subsequent external electrode 3 is not disposed.
  • the second plating layer 32 is disposed so as to cover the spacer 4 and the external electrode 3, but is not limited thereto, and the second plating layer 32 does not have to be disposed on the spacer 4 and the external electrode 3 ( FIG. 8 ).
  • the second plating layer 32 includes a second nickel (Ni) plating layer 32a and a second tin (Sn) plating layer 32b disposed on the surface of the second nickel (Ni) plating layer 32a.
  • the second plating layer 32 is disposed on the outer surface of the first tin (Sn) plating layer 31b of the first plating layer 31 in the portion where the spacer 4 is not disposed, and is disposed on the outer surface of the spacer 4 in the portion where the spacer 4 is disposed. Note that the configuration of the second plating layer 32 is not limited to this. By disposing the second plating layer 32, the adhesive strength between the spacer 4 and the capacitor body 1A is improved.
  • the external electrode 3 is composed of the base electrode layer 30 and the first plating layer 31 covering it, and the spacer 4 is disposed on the surface of the first plating layer 31, but the first plating layer 31 is not necessarily required.
  • the spacer 4 may be disposed on the surface of the base electrode layer 30, and the second plating layer 32 may be disposed so as to cover the spacer 4 and the base electrode layer 30.
  • the spacer 4 contains either copper (Cu) or nickel (Ni) and tin (Sn) as metal powder.
  • the copper (Cu) and nickel (Ni) may be coated with silver (Ag).
  • the intermetallic compound formed by adding either copper (Cu) or nickel (Ni) and tin (Sn) does not deform due to heat even when soldering is performed when mounting the multilayer ceramic capacitor 1 on a wiring board, and can reliably maintain the shape of the spacer 4.
  • the intermetallic compound formed by adding tin (Sn) to an alloy of copper (Cu) and nickel (Ni) is preferable as a component for forming the spacer 4.
  • Phenol resin is contained in the metal region MP formed by the metal powder.
  • the phenol resin coats the particles of the intermetallic compound and is scattered so as to fill the gaps between the particles.
  • the phenol resin may not completely coat the particles of the intermetallic compound.
  • the amount of gas generated during the heat treatment for forming the spacer 4 can be reduced, and therefore the voids P within the spacer 4 can be reduced.
  • the phenol resin may be exposed on the surface of the spacer 4 and cover at least a portion of the surface of the spacer 4. By coating the surface of the spacer 4 with the phenol resin, the smoothness of the surface of the spacer 4 is improved, and the mechanical strength of the spacer 4 can be increased.
  • phenolic resins include novolac-type phenolic resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, tert-butylphenol novolac resin, and nonylphenol novolac resin, resol-type phenolic resin, and polyoxystyrene such as polyparaoxystyrene.
  • the area ratio of the phenolic resin in the spacer 4 is preferably 1% to 20% in the LT cross section perpendicular to the width direction W of the spacer 4, and more preferably 5% to 15%. If it is less than 1%, the effect of the phenolic resin cannot be fully exerted, and if it exceeds 20%, the adhesive strength of the spacer to the external electrode may decrease.
  • the percentage (%) of the area occupied by the phenolic resin in the spacer 4 can be calculated, for example, by polishing the spacer 4 in the width direction W up to the center of the width direction W, enlarging the polished surface with a microscope (BX-51) at a total magnification of 50 times, and photographing it with a digital camera for microscopes (Olympus DP22).
  • the photographed image obtained is binarized to separate it into metal regions MP and resin regions RP, and the percentage (%) of the area occupied by the phenolic resin can be calculated from the areas of the metal regions MP, metal powder MF, resin regions RP, and voids P using the formula: Area of resin regions RP/(Area of metal regions MP+Area of metal powder MF+Area of resin regions RP+Area of voids P) x 100.
  • metal powder MF may be included in the resin region RP formed by the phenolic resin.
  • the metal powder MF can inhibit the shrinkage of the phenolic resin, thereby reducing the shrinkage stress caused by the phenolic resin.
  • the spacer 4 preferably has a porosity of 20% or less in the region Z up to 5 ⁇ m from the interface with the external electrode 3. By keeping the porosity low, the bonding area of the spacer 4 that is bonded to the external electrode 3 increases, improving the bonding strength with the external electrode 3.
  • the maximum diameter of the void P formed inside the spacer 4 is preferably 1/2 or less of the maximum dimension of the thickness of the spacer 4 in the stacking direction T. If it is greater than 1/2, cracks are more likely to occur starting from the void P, reducing the strength of the spacer 4.
  • the maximum diameter of the void P formed inside the spacer 4 is preferably 1/2 or less of the maximum dimension of the thickness of the spacer 4 in the width direction W.
  • Example 1 31.5 wt% Cu-10 wt% Ni powder with a D50 of 5 ⁇ m, 58.5 wt% solder powder with a composition of Sn-3 wt% Ag-0.5 wt% Cu with a D50 of 5 ⁇ m, and 10 wt% phenolic resin, solvent, and additives were used.
  • Comparative Example 1 31.5 wt% Cu-10 wt% Ni powder with a D50 of 5 ⁇ m, 58.5 wt% solder powder with a composition of Sn-3 wt% Ag-0.5 wt% Cu with a D50 of 5 ⁇ m, and 10 wt% rosin, solvent, and additives were used.
  • Example 1 and Comparative Example 1 were evaluated based on the following criteria of 1 to 3.
  • a sample is mounted on a board with solder, and the adhesion strength is measured using DAGE5000 (Nordson Advanced Technology Co., Ltd.). At this time, the item is pushed from a direction connecting the side surfaces of the first spacer and the second spacer, and the strength with which the item is removed from the substrate is compared. Ten samples were measured, and an average strength of less than 8N was rated x (fail), 8N or more but less than 11N was rated ⁇ (acceptable), 11N or more but less than 13N was ⁇ (pass), and 13N or more was ⁇ (pass).
  • TGDTA6300 (Hitachi High-Tech Science Corporation) the resin is heated from room temperature at 3° C./min in a nitrogen gas atmosphere, and the mass is measured at 250° C. A mass loss rate of 5% or more from the start of the test is rated as ⁇ (fail), and a loss of less than 5% is rated as ⁇ (pass).
  • the spacer is ground in the width direction W to the center in the width direction W. Then, using a microscope (BX-51) connected to a digital camera for a microscope (DP22, manufactured by Olympus), a cross section of the spacer is photographed at a total magnification of 50 times. The captured image is binarized, and the areas of the metal regions MP, metal powder MF, resin regions RP, and voids P of the spacer are determined, and the void ratio is calculated using the following formula.
  • porosity at the interface between the spacer and the plating layer was more than 20%, it was rated as ⁇ (fail), and if the porosity was 20% or less, it was rated as ⁇ (pass).
  • Porosity (%) area of void P/(area of metal region MP+area of metal powder MF+area of resin region RP+area of void P) ⁇ 100
  • Example 1 containing a phenolic resin was superior in adhesive strength to Comparative Example 1 containing a rosin.
  • the amount of vaporization of phenolic resin is smaller than that of rosin, and therefore the porosity within the spacer could be reduced.
  • the spacer has a denser structure, the bonding area between the external electrode and the spacer can be increased, and the bonding strength between the external electrode and the spacer is improved.
  • Comparative Example 1, which used rosin had many and large voids, and therefore the spacer was prone to breakage.
  • the direction discrimination means indicates the direction so that the second main surface A2 or the first side surface B1 on which the spacer 4 is arranged faces the wiring board when the multilayer ceramic capacitor 1 is mounted on the wiring board, and can be a means for coloring the spacer 4 in a color different from the external electrode 3, a means for printing a mark for discriminating the direction such as a QR code (registered trademark), or a means for providing a recess in a part of the laminate 2.
  • the phenolic resin contained in the spacer 4 may be exposed on the surface of the spacer 4 so that it has a color different from that of the external electrode 3. Even if the spacer 4 is larger than the external electrode 3, a direction discrimination means may be provided.
  • a reinforcing material 50 can be arranged between the first spacer 4a and the second spacer 4b so as to cover at least a portion of at least one of the first spacer 4a and the second spacer 4b and at least a portion of the second main surface A2 or the first side surface B1 of the laminate 2.
  • the reinforcing material 50 can be arranged continuously between the first spacer 4a and the second spacer 4b, but does not necessarily have to be arranged continuously.
  • the reinforcing material 50 may be arranged in two parts: one covering a part of the first spacer 4a and a part of the second main surface A2 or the first side surface B1 of the laminate 2, and the other covering a part of the second spacer 4b and a part of the second main surface A2 or the first side surface B1 of the laminate 2.
  • the reinforcing material 50 can be formed from an insulating resin.
  • the surface of the insulating resin may be coated with an insulating water-repellent agent.
  • an insulating water-repellent agent By forming the reinforcing material from an insulating resin, the flexural strength is improved, and by further coating it with an insulating water-repellent agent, the moisture resistance is improved.
  • the insulating resin may contain ceramics, glass, etc. It may be formed from only the water-repellent agent.
  • the material of the reinforcing material 50 is mainly epoxy resin, which can be combined with phenolic resin as a hardener.
  • Other hardeners that can be used include acid anhydride-based, amine-based, and ester-based hardeners.
  • a hardening accelerator may also be added to the epoxy resin.
  • the reinforcing material 50 can be arranged so as to cover the side surface SW of the spacer 4.
  • the reinforcing material 50 covers the side surface SW of the spacer 4 to a height of 5% or more of the length of the spacer 4 in the stacking direction T, while covering the second main surface A2 or the first side surface B1 of the laminate 2.
  • FIG. 5 is a flow chart for explaining the method for manufacturing the multilayer ceramic capacitor 1.
  • the method for manufacturing the multilayer ceramic capacitor 1 includes a laminate manufacturing step S1, a base electrode layer forming step S2, a first plating layer forming step S3, a spacer arranging step S4, and a second plating layer forming step S5.
  • the multilayer ceramic capacitor 1 is provided with a reinforcing material 50 by going through a reinforcing material arranging step S6.
  • FIG. 6 is a diagram for explaining the laminate manufacturing step S1, the base electrode layer forming step S2, and the first plating layer forming step S3.
  • FIG. 7 is a diagram for explaining the spacer arranging step S4 and the second plating layer forming step S5.
  • FIG. 10 is a diagram for explaining the reinforcing material arranging step S6.
  • a ceramic slurry containing ceramic powder, a binder, and a solvent is formed into a sheet shape on the surface of a carrier film using a die coater, a gravure coater, a microgravure coater, or the like to prepare a laminated ceramic green sheet 101 that will become the dielectric layer 14.
  • a conductive paste is printed in stripes on the laminated ceramic green sheet 101 by screen printing, inkjet printing, gravure printing, or the like, and a conductive pattern 102 that will become the internal electrode layer 15 is printed on the surface of the laminated ceramic green sheet 101 to prepare a material sheet 103.
  • multiple material sheets 103 are stacked so that the conductive patterns 102 face the same direction and are offset, for example, by half a pitch in the length direction between adjacent material sheets 103. Furthermore, outer layer ceramic green sheets 112 that will become the outer layer 12 are stacked on both sides of the multiple stacked material sheets 103.
  • the stacked material sheets 103 and the outer layer ceramic green sheets 112 are pressed together using a hydrostatic press or the like to create the mother block 110 shown in Figure 6(b).
  • the mother block 110 is cut along the cutting line X shown in FIG. 6(b) and along the cutting line Y that intersects with the cutting line X to produce a plurality of laminates 2 shown in FIG. 6(c).
  • Base electrode layer formation step S2 Next, a conductive paste containing copper (Cu) is applied to the end faces C of the laminate 2 and baked to form the base electrode layer 30.
  • the base electrode layer 30 is formed not only on the end faces C on both sides of the laminate 2 but also on the other end faces C on both sides of the laminate 2.
  • the insulating layer 2 is formed so as to extend to the main surface A and the side surface B of the laminate 2 and to cover a part of the end surface C of the main surface A.
  • the insulating layer 2 is not limited to this, and may contain other metals and other components.
  • two base electrode layers may be provided.
  • Spacer placement step S4 A spacer manufacturing paste 41 used for manufacturing the spacers is prepared.
  • the spacer manufacturing paste 41 contains metals made of copper (Cu), nickel (NI), tin (Sn), and silver (Ag), a phenol resin, a solvent, and an additive.
  • phenolic resins include novolac-type phenolic resins such as phenol novolac resin, phenol aralkyl resin, cresol novolac resin, tert-butylphenol novolac resin, and nonylphenol novolac resin, resol-type phenolic resin, and polyoxystyrene such as polyparaoxystyrene.
  • a holding substrate 40 as shown in FIG. 7 is used.
  • a spacer manufacturing paste 41 is placed on a holding substrate 40 by a screen printing method, a dispense method or the like.
  • the capacitor body 1A is mounted on the upper surface of the holding substrate 40 with the second main surface A2 facing the holding substrate 40. At this time, the external electrodes 3 of the capacitor body 1A and the spacer manufacturing paste 41 are aligned, and the spacer manufacturing paste 41 adheres to the capacitor body 1A.
  • the heating process is carried out.
  • the metal in the paste produces an intermetallic compound and the metal region MP is formed
  • some of the phenolic resin is taken into the metal region MP and some is expelled from the metal region MP, while hardening, forming a spacer 4 bonded to the capacitor body 1A.
  • the capacitor body 1A is separated from the holding substrate 40 together with the spacer 4, resulting in the state shown in FIG. 7(c).
  • the manufacturing method is not limited to this, and the spacer may be formed by placing a spacer manufacturing paste in a desired shape directly on the surface of the capacitor body 1A and performing a heat treatment.
  • a second nickel (Ni) plating layer 32a is formed on the exposed portion of the first tin (Sn) plating layer 31b in the capacitor body 1A and on the surface of the spacer 4, and a second tin (Sn) plating layer 32b may further be formed on the surface of the second nickel (Ni) plating layer 32a.
  • FIG. 10A and 10B are diagrams illustrating the reinforcing material arranging step S6.
  • the spacer arranging step S4 the surface of the capacitor body 1A on which the spacers 4 are arranged is cleaned with a solvent. As shown in FIG. After cleaning is completed, the capacitor body 1A with the spacers 4 disposed thereon is aligned so that the spacers 4 face upward.
  • a dispenser or squeegee printing is used to form an insulating resin layer that will become the central portion 51 of the reinforcing material 50 between the first spacer 4a and the second spacer 4b on the capacitor body 1A on which the spacer 4 is disposed.
  • the amount of insulating resin that wets onto the side surface of the spacer 4 can be adjusted by adjusting the amount of insulating resin.
  • the insulating resin can penetrate into the interface between the spacer 4 and the laminate 2, you can do so by suctioning the vacuum after placing the insulating resin.
  • the amount of penetration can be controlled by changing the vacuuming time and pressure.
  • an insulating resin may be applied so as to cover the outer periphery of the capacitor body 1 A and the outer periphery of the spacer 4 .
  • the applied insulating resin is then heated at 100 to 200° C. for 20 to 80 minutes, whereby the insulating resin hardens and forms a covering made of the reinforcing material 50 on the outer periphery of the capacitor body 1A and on the side surface SW of the spacer 4.
  • the multilayer ceramic capacitor 1 is manufactured.
  • the reinforcing material 50 directly covers the surface of the spacer 4, but this is not necessarily limited to this.
  • the second plating layer 32 may be formed on the surface of the spacer 4, and the reinforcing material 50 may be disposed so as to cover the surface of the second plating layer 32 with the side surface SW of the spacer 4.
  • the above describes an embodiment of the present invention, but the present invention is not limited to the embodiment, and can be implemented in various forms without departing from the gist of the present invention.
  • the present invention includes the following combinations.
  • ⁇ 1> a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, the laminate having two main faces opposing each other in a lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side faces opposing each other in a width direction intersecting the lamination direction and the length direction;
  • Two external electrodes are connected to the internal electrode layers at the two end faces, respectively, and cover the end faces and parts of two opposing main faces.
  • the multilayer ceramic electronic component according to ⁇ 1> wherein the phenol resin occupies an area of 1% or more and 20% or less in a cross section perpendicular to the width direction of the spacer.
  • ⁇ 3> 3 The multilayer ceramic electronic component according to claim 1, wherein at least a part of a surface of the spacer is covered with the phenol resin.
  • ⁇ 4> The multilayer ceramic electronic component according to any one of ⁇ 1> to ⁇ 3>, wherein the metal powder is contained in a resin region formed by the phenol resin.
  • ⁇ 5> The multilayer ceramic electronic component according to any one of ⁇ 1> to ⁇ 4>, wherein the spacer has a porosity of 20% or less in a region extending from the interface with the external electrode to a depth of 5 ⁇ m.
  • ⁇ 6> The multilayer ceramic electronic component according to any one of ⁇ 1> to ⁇ 5>, wherein the spacer includes a gap, and the maximum diameter of the gap is equal to or less than half of the maximum dimension of the thickness of the spacer in the stacking direction.
  • ⁇ 7> The multilayer ceramic electronic component according to any one of ⁇ 1> to ⁇ 6>, wherein a direction determining means is provided on at least a part of the spacer.
  • ⁇ 8> The multilayer ceramic electronic component according to any one of ⁇ 1> to ⁇ 7>, wherein a reinforcing material is disposed between the two spacers, the reinforcing material covering at least a portion of the two spacers and at least a portion of the main surface of the laminate.
  • ⁇ 9> The multilayer ceramic electronic component according to ⁇ 8>, wherein the reinforcing material covers side peripheral surfaces of the two spacers.
  • a laminate including an inner layer portion in which dielectric layers and internal electrode layers are alternately laminated, the laminate having two main faces opposing each other in a lamination direction, two end faces opposing each other in a length direction intersecting the lamination direction, and two side faces opposing each other in a width direction intersecting the lamination direction and the length direction; two external electrodes connected to the internal electrode layers at the two end faces, respectively, and covering the end faces and parts of the two side faces adjacent thereto; two spacers disposed on one of the two side surfaces of the stack;
  • the spacer comprises metal powder and a phenolic resin.
  • ⁇ 11> The multilayer ceramic electronic component according to ⁇ 10>, wherein in a cross section of the spacer perpendicular to the stacking direction, an area occupied by the phenol resin is 1% to 20% of an area occupied by the metal powder.
  • ⁇ 12> The multilayer ceramic electronic component according to ⁇ 10> or ⁇ 11>, wherein at least a part of a surface of the spacer is covered with the phenol resin.
  • ⁇ 13> The multilayer ceramic electronic component according to any one of ⁇ 10> to ⁇ 12>, wherein the metal powder is contained in a resin region formed by the phenol resin.
  • ⁇ 14> The multilayer ceramic electronic component according to any one of ⁇ 10> to ⁇ 13>, wherein the spacer has a porosity of 20% or less in a region extending from the interface with the external electrode to a depth of 5 ⁇ m.
  • ⁇ 15> The multilayer ceramic electronic component according to any one of ⁇ 10> to ⁇ 14>, wherein the spacer includes a gap, and the maximum diameter of the gap is equal to or less than half of the maximum dimension of the thickness of the spacer in the width direction.
  • ⁇ 16> The multilayer ceramic electronic component according to any one of ⁇ 10> to ⁇ 15>, wherein a direction determining means is provided on at least a part of the spacer.
  • ⁇ 17> The multilayer ceramic electronic component according to any one of ⁇ 10> to ⁇ 16>, wherein a reinforcing material is disposed between the two spacers, the reinforcing material covering at least a portion of the two spacers and at least a portion of the side surface of the laminate.
  • a reinforcing material is disposed between the two spacers, the reinforcing material covering at least a portion of the two spacers and at least a portion of the side surface of the laminate.
  • the reinforcing material covers side peripheral surfaces of the two spacers.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Ceramic Capacitors (AREA)
PCT/JP2024/011734 2023-03-30 2024-03-25 積層セラミック電子部品 Ceased WO2024204084A1 (ja)

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Publication number Priority date Publication date Assignee Title
WO2025192599A1 (ja) * 2024-03-13 2025-09-18 株式会社村田製作所 積層セラミック電子部品

Citations (5)

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Publication number Priority date Publication date Assignee Title
JP2015216337A (ja) * 2014-05-08 2015-12-03 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層セラミックキャパシター、アレイ型積層セラミックキャパシター、その製造方法、及びその実装基板
JP2017228759A (ja) * 2016-06-20 2017-12-28 サムソン エレクトロ−メカニックス カンパニーリミテッド． キャパシター部品
JP2018049999A (ja) * 2016-09-23 2018-03-29 Tdk株式会社 電子部品及び電子部品装置
JP2019047092A (ja) * 2017-09-07 2019-03-22 Tdk株式会社 電子部品
JP2022099069A (ja) * 2020-12-22 2022-07-04 株式会社村田製作所 積層セラミックコンデンサ及び積層セラミックコンデンサの製造方法

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Publication number Priority date Publication date Assignee Title
JP2015216337A (ja) * 2014-05-08 2015-12-03 サムソン エレクトロ−メカニックス カンパニーリミテッド． 積層セラミックキャパシター、アレイ型積層セラミックキャパシター、その製造方法、及びその実装基板
JP2017228759A (ja) * 2016-06-20 2017-12-28 サムソン エレクトロ−メカニックス カンパニーリミテッド． キャパシター部品
JP2018049999A (ja) * 2016-09-23 2018-03-29 Tdk株式会社 電子部品及び電子部品装置
JP2019047092A (ja) * 2017-09-07 2019-03-22 Tdk株式会社 電子部品
JP2022099069A (ja) * 2020-12-22 2022-07-04 株式会社村田製作所 積層セラミックコンデンサ及び積層セラミックコンデンサの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025192599A1 (ja) * 2024-03-13 2025-09-18 株式会社村田製作所 積層セラミック電子部品

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