WO2024203338A1 - 半導体装置およびその製造方法 - Google Patents

半導体装置およびその製造方法 Download PDF

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Publication number
WO2024203338A1
WO2024203338A1 PCT/JP2024/009793 JP2024009793W WO2024203338A1 WO 2024203338 A1 WO2024203338 A1 WO 2024203338A1 JP 2024009793 W JP2024009793 W JP 2024009793W WO 2024203338 A1 WO2024203338 A1 WO 2024203338A1
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Prior art keywords
electrode
film
gate
wiring
silicide
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Ceased
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PCT/JP2024/009793
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to CN202480020754.5A priority Critical patent/CN121003026A/zh
Priority to DE112024001488.7T priority patent/DE112024001488T5/de
Priority to JP2025510438A priority patent/JPWO2024203338A1/ja
Publication of WO2024203338A1 publication Critical patent/WO2024203338A1/ja
Priority to US19/342,952 priority patent/US20260032949A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/661—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation
    • H10D64/662—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures
    • H10D64/663—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation the conductor further comprising additional layers, e.g. multiple silicon layers having different crystal structures the additional layers comprising a silicide layer contacting the layer of silicon, e.g. polycide gates

Definitions

  • Patent Document 1 discloses a semiconductor device having a gate electrode. This gate electrode has a layered structure including a semiconductor layer and a metal semiconductor compound layer (silicide).
  • the present disclosure provides a semiconductor device having a novel configuration and a manufacturing method thereof.
  • the present disclosure provides a semiconductor device including a chip including SiC and having a main surface, a gate electrode including polysilicon and arranged on the main surface and having an electrode surface, a silicide portion partially formed on a surface portion of the electrode surface, and a polysilicon portion formed on a portion of the surface portion of the electrode surface other than the silicide portion.
  • the present disclosure provides a semiconductor device including a chip including SiC and having a main surface, a gate electrode disposed on the main surface, an interlayer film covering the gate electrode and having an insulating surface, an opening formed in the interlayer film spaced apart from the gate electrode and exposing the main surface, a buried electrode embedded in the opening, having an electrode surface exposed from the opening, and electrically connected to the chip, and a main electrode mechanically and electrically connected to the electrode surface of the buried electrode.
  • the present disclosure provides a method for manufacturing a semiconductor device, including the steps of forming a base electrode containing polysilicon on a wafer containing SiC, forming a metal film partially covering an electrode surface of the base electrode, reacting the polysilicon with the metal film to partially form a silicide portion on the surface portion of the electrode surface, removing the unreacted portion of the metal film from the electrode surface, and removing the base electrode in the thickness direction from the polysilicon portion outside the silicide portion to form a gate electrode having both the silicide portion and the polysilicon portion on the surface portion of the electrode surface.
  • the present disclosure provides a method for manufacturing a semiconductor device, including the steps of forming a gate electrode on a wafer, forming an interlayer film on the wafer that covers the gate electrode, forming an opening in the interlayer film that exposes the wafer at a position spaced apart from the gate electrode, embedding an electrode in the opening so as to be electrically connected to the wafer, forming a buried electrode having an electrode surface exposed from the opening, and forming a main electrode that directly covers the electrode surface of the buried electrode.
  • FIG. 1 is a plan view showing a semiconductor device according to a specific embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing an example of the layout of the first main surface.
  • FIG. 4 is an enlarged plan view showing a main portion of the first main surface.
  • FIG. 5 is an enlarged plan view showing further essential parts of the first main surface.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is an enlarged cross-sectional view showing the main part of FIG. 6 together with the gate electrode according to the first example and the source pad electrode according to the first example.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. FIG.
  • FIG. 9 is an enlarged cross-sectional view showing the main part of FIG. 8 together with the gate wiring according to the first example.
  • FIG. 10A is an enlarged cross-sectional view showing a gate electrode according to the second example.
  • FIG. 10B is an enlarged cross-sectional view showing a gate electrode according to the third example.
  • FIG. 10C is an enlarged cross-sectional view showing a gate electrode according to the fourth example.
  • FIG. 11A is an enlarged cross-sectional view showing a gate wiring according to the second example.
  • FIG. 11B is an enlarged cross-sectional view showing the gate wiring according to the third example.
  • FIG. 11C is an enlarged cross-sectional view showing a gate wiring according to the fourth example.
  • FIG. 11A is an enlarged cross-sectional view showing a gate wiring according to the second example.
  • FIG. 11B is an enlarged cross-sectional view showing the gate wiring according to the third example.
  • FIG. 11C is an enlarged cross-sectional view showing
  • FIG. 12A is an enlarged cross-sectional view showing a source pad electrode according to the second example.
  • FIG. 12B is an enlarged cross-sectional view showing a source pad electrode according to the third example.
  • FIG. 12C is an enlarged cross-sectional view showing a source pad electrode according to the fourth example.
  • FIG. 12D is an enlarged cross-sectional view showing a source pad electrode according to the fifth example.
  • FIG. 13 is a schematic diagram showing a wafer.
  • FIG. 14A is a cross-sectional view showing a method for manufacturing a semiconductor device.
  • FIG. 14B is a cross-sectional view showing a step subsequent to FIG. 14A.
  • FIG. 14C is a cross-sectional view showing a step subsequent to FIG. 14B.
  • FIG. 14A is a cross-sectional view showing a method for manufacturing a semiconductor device.
  • FIG. 14B is a cross-sectional view showing a step subsequent to FIG. 14A.
  • FIG. 14C is
  • FIG. 14D is a cross-sectional view showing a step subsequent to FIG. 14C.
  • FIG. 14E is a cross-sectional view showing a step subsequent to FIG. 14D.
  • FIG. 14F is a cross-sectional view showing a step subsequent to FIG. 14E.
  • FIG. 14G is a cross-sectional view showing a step subsequent to FIG. 14F.
  • FIG. 14H is a cross-sectional view showing a step subsequent to FIG. 14G.
  • FIG. 14I is a cross-sectional view showing a step subsequent to FIG. 14H.
  • FIG. 14J is a cross-sectional view showing a step subsequent to FIG. 14I.
  • FIG. 14K is a cross-sectional view showing a step subsequent to FIG. 14J.
  • FIG. 14L is a cross-sectional view showing a step subsequent to FIG. 14K.
  • FIG. 14M is a cross-sectional view showing a step subsequent to FIG. 14L.
  • FIG. 14N is a cross-sectional view showing a step subsequent to FIG. 14M.
  • FIG. 14O is a cross-sectional view showing a step subsequent to FIG. 14N.
  • FIG. 14P is a cross-sectional view showing a step subsequent to that shown in FIG. 14O.
  • FIG. 14Q is a cross-sectional view showing a step subsequent to FIG. 14P.
  • FIG. 14R is a cross-sectional view showing a step subsequent to FIG. 14Q.
  • FIG. 15 is a cross-sectional view showing a first modified example of a semiconductor device.
  • FIG. 16 is a cross-sectional view showing a second modified example of a semiconductor device.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1 according to a specific embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing an example of the layout of the first main surface 3.
  • FIG. 4 is an enlarged plan view showing a main portion of the first main surface 3.
  • FIG. 5 is an enlarged plan view showing further main portions of the first main surface 3.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5.
  • FIG. 7 is an enlarged cross-sectional view showing the main part of FIG. 6 together with the gate electrode 32 according to the first example and the source pad electrode 95 according to the first example.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.
  • FIG. 9 is an enlarged cross-sectional view showing the main part of FIG. 8 together with the gate wiring 52 according to the first example.
  • the semiconductor device 1 is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure.
  • the transistor structure Tr has a vertical structure.
  • the semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal.
  • the chip 2 may be referred to as a "SiC chip” or a "semiconductor chip.”
  • the chip 2 is made of hexagonal SiC single crystal and is formed into a rectangular parallelepiped shape.
  • the hexagonal SiC single crystal has a number of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • first direction X refers to the third side surface 5C side
  • second direction Y refers to the first side surface 5A side
  • second side of the second direction Y refers to the second side surface 5B side.
  • first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • first direction X may be the a-axis direction of the SiC single crystal
  • second direction Y may be the m-axis direction of the SiC single crystal.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction by the off angle.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side in the chip 2.
  • the first semiconductor region 6 may be referred to as a "drift region,” “drain drift region,” “drain region,” etc.
  • a drain potential is applied to the first semiconductor region 6 as a high potential (first potential).
  • the first semiconductor region 6 is formed in a layer extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).
  • the semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side in the chip 2. A drain potential is applied to the second semiconductor region 7.
  • the second semiconductor region 7 may be referred to as a "drain region” or the like.
  • the second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 in the chip 2.
  • the second semiconductor region 7 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC substrate).
  • the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer.
  • the second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.
  • the semiconductor device 1 includes an active region 8 set in the chip 2.
  • the active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 8 is set in the inner part of the chip 2 at a distance from the periphery (first to fourth side faces 5A to 5D) of the chip 2 in a plan view.
  • the active region 8 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the semiconductor device 1 includes a peripheral region 9 that is set outside the active region 8 in the chip 2.
  • the peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a planar view.
  • the peripheral region 9 extends in a band shape along the active region 8 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 8.
  • the semiconductor device 1 includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 in the active region 8.
  • a source potential is applied to the plurality of body regions 20 as a low potential (second potential) different from a high potential (first potential).
  • the plurality of body regions 20 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of body regions 20 are arranged in a stripe shape extending in the second direction Y.
  • the multiple body regions 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the multiple body regions 20 are formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3. The multiple body regions 20 are exposed from the first main surface 3.
  • the body regions 20 may each have a width of 1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the body regions 20 may have a value that belongs to at least one of the following ranges: 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 7 ⁇ m or less, 7 ⁇ m or more and 8 ⁇ m or less, 8 ⁇ m or more and 9 ⁇ m or less, and 9 ⁇ m or more and 10 ⁇ m or less.
  • the width of the body regions 20 is preferably 2 ⁇ m or more and 5 ⁇ m or less.
  • the body regions 20 may each have a thickness (depth) of 0.1 ⁇ m or more and 2.5 ⁇ m or less.
  • the thickness of the body regions 20 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, and 2 ⁇ m or more and 2.5 ⁇ m or less.
  • the thickness of the body regions 20 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the semiconductor device 1 includes a p-type outer body region 21 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the outer body region 21 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the outer body region 21 may be less than the p-type impurity concentration of the body region 20, or may be higher than the p-type impurity concentration of the body region 20.
  • the outer body region 21 is formed at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a band along the active region 8.
  • the outer body region 21 has a portion that extends in a band in the first direction X and a portion that extends in a band in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the outer body region 21 surrounds the active region 8 in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the outer body region 21 forms the boundary between the active region 8 and the peripheral region 9.
  • the outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the outer body region 21 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the outer body region 21 is connected to the multiple body regions 20 in a portion extending in the first direction X. In this way, the outer body region 21 is electrically connected to the multiple body regions 20.
  • the outer body region 21 preferably has a width greater than the width of the body region 20.
  • the width of the body region 20 is the width in a direction perpendicular to the extension direction (i.e., the first direction X).
  • the width of the outer body region 21 is the width in a direction perpendicular to the extension direction.
  • the width of the outer body region 21 may be approximately equal to the width of the body region 20, or may be less than the thickness of the body region 20.
  • the ratio of the width of the outer body region 21 to the width of the body region 20 may be 1 or more and 50 or less.
  • the width ratio may have a value that belongs to at least one of the following ranges: 1 or more and 10 or less, 10 or more and 20 or less, 20 or more and 30 or less, 30 or more and 40 or less, and 40 or more and 50 or less. It is preferable that the width ratio is 10 or more. It is preferable that the width ratio is 20 or more and 40 or less.
  • the outer body region 21 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the outer body region 21 is formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.
  • the outer body region 21 has a thickness (depth) that is approximately equal to the thickness (depth) of the body region 20.
  • the thickness of the outer body region 21 may be less than the thickness of the body region 20, or may be greater than the thickness of the body region 20.
  • the semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed in the surface portion of the first main surface 3.
  • each of the surface drift regions 22 is made up of a portion of the first semiconductor region 6.
  • the surface drift regions 22 may have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6, or may have an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6.
  • the multiple surface drift regions 22 are each defined in a region between multiple body regions 20 adjacent to each other in the first direction X. Specifically, the multiple surface drift regions 22 are each defined by multiple body regions 20 and outer body regions 21 in the surface portion of the first main surface 3.
  • the multiple surface drift regions 22 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the multiple surface drift regions 22 are formed in a stripe shape extending in the second direction Y.
  • the surface drift region 22 forms an n-type (pnp-type) JFET structure together with the multiple body regions 20 located on both sides.
  • the multiple surface drift regions 22 may have a width of 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the width of the surface drift regions 22 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the semiconductor device 1 includes a plurality of n-type source regions 23, 24 formed in the surface layer of each of the body regions 20.
  • the source regions 23, 24 have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6.
  • a source potential is applied to the source regions 23, 24.
  • the multiple source regions 23, 24 include a first source region 23 located on one side of the first direction X and a second source region 24 located on the other side of the first direction X in the surface layer portion of each body region 20.
  • one first source region 23 is formed on one end side of the body region 20 in the first direction X
  • one second source region 24 is formed on the other end side of the body region 20.
  • the first source region 23 is formed at a distance from one end of the body region 20 to the other end, and extends in a band shape along the extension direction of the body region 20.
  • the first source region 23 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the first source region 23 is not formed in the outer body region 21.
  • the first source region 23 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the body region 20.
  • the second source region 24 is formed at a distance from the first source region 23 to the other end side of the body region 20.
  • the second source region 24 is formed at a distance from the other end side of the body region 20 to one end side, and extends in a band shape along the extension direction of the body region 20.
  • the second source region 24 is formed at a distance from the outer body region 21 in the second direction Y.
  • the second source region 24 is not formed in the outer body region 21.
  • the second source region 24 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 across a portion of the body region 20.
  • each first source region 23 may be formed at intervals in the extension direction of the body region 20. In this case, each first source region 23 may be formed in a strip extending in the second direction Y.
  • the multiple second source regions 24 may be formed at intervals in the extension direction of the body region 20. In this case, each second source region 24 may be formed in a strip extending in the second direction Y.
  • the semiconductor device 1 includes a plurality of p-type contact regions 25 formed in the surface layer of each of the body regions 20 in the active region 8.
  • the contact regions 25 may be referred to as "backgate regions.”
  • a source potential is applied to the contact regions 25.
  • the contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the body regions 20.
  • one contact region 25 is interposed in the region between the first source region 23 and the second source region 24 in the surface portion of the corresponding body region 20.
  • the contact region 25 extends in a strip shape along the extension direction of the body region 20 (source regions 23, 24).
  • the contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the contact region 25 is not formed in the outer body region 21.
  • the contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 across a portion of the body region 20.
  • each contact region 25 may be formed at intervals in the extension direction of the body region 20.
  • each contact region 25 may be formed in a strip shape extending in the second direction Y.
  • the semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed in a surface layer portion of the first main surface 3.
  • the plurality of channel regions 26, 27 are defined in the surface layer portions of the plurality of body regions 20 in regions between ends of the plurality of body regions 20 (a plurality of surface drift regions 22) and peripheries of the plurality of source regions 23, 24, respectively.
  • the multiple channel regions 26, 27 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y. In other words, the multiple channel regions 26, 27 are arranged in stripes extending in the second direction Y.
  • the multiple channel regions 26, 27 include multiple first channel regions 26 and multiple second channel regions 27.
  • the multiple first channel regions 26 are each partitioned into a region between one end of the multiple body regions 20 (surface drift region 22) and the multiple first source regions 23, forming a current path that extends horizontally.
  • the multiple second channel regions 27 are each partitioned into a region between the other end of the multiple body regions 20 (surface drift region 22) and the multiple second source regions 24, forming a current path that extends horizontally.
  • the semiconductor device 1 includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8.
  • the plurality of gate structures 30 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y.
  • the extension direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.
  • Each gate structure 30 is disposed over at least one channel region 26, 27. In this embodiment, each gate structure 30 is disposed across one surface drift region 22 and across two adjacent body regions 20, covering multiple channel regions 26, 27.
  • each gate structure 30 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.
  • the gate structure 30 has a layered structure including an insulating film 31 and a gate electrode 32.
  • the gate structure 30 does not have a sidewall structure (spacer) made of an insulator (such as silicon oxide and/or silicon nitride) on the side of the gate electrode 32.
  • the gate structure 30 has a configuration that allows for a narrow pitch arrangement.
  • the insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 31 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 includes a silicon oxide film made of an oxide of the chip 2.
  • the insulating film 31 covers the first main surface 3 in a film-like shape and is disposed on at least one of the channel regions 26, 27. In this embodiment, the insulating film 31 is disposed so as to cross one surface drift region 22 and straddle two adjacent body regions 20, covering the multiple channel regions 26, 27.
  • the insulating film 31 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.
  • the insulating film 31 partially covers the first source region 23 at a distance from the contact region 25, and exposes a part of the first source region 23 and the contact region 25 from the first main surface 3.
  • the insulating film 31 partially covers the second source region 24 at a distance from the contact region 25, and exposes a part of the second source region 24 and the contact region 25 from the first main surface 3.
  • the insulating film 31 may have a thickness of 10 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.
  • the gate electrode 32 is disposed on the insulating film 31 and faces at least one of the channel regions 26, 27 across the insulating film 31.
  • a gate potential is applied to the gate electrode 32 as a control potential.
  • the gate electrode 32 controls the inversion and non-inversion of at least one of the channel regions 26, 27 in response to the gate potential.
  • the gate electrode 32 includes a conductive semiconductor polycrystal.
  • the gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved.
  • the gate electrode 32 may be referred to as a "polysilicon gate", a “poly gate”, etc.
  • the gate electrode 32 is formed in a strip shape extending in the second direction Y. In other words, the extension direction of the gate electrode 32 coincides with the off-direction of the SiC single crystal. In this embodiment, the gate electrode 32 is formed spaced inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 is disposed on the insulating film 31 so as to straddle two adjacent body regions 20 across one surface drift region 22, and faces multiple channel regions 26, 27 across the insulating film 31.
  • the gate electrode 32 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 across the insulating film 31.
  • the gate electrode 32 has an electrode surface 33, a first sidewall 34 on one side in the first direction X, and a second sidewall 35 on the other side in the first direction X.
  • the electrode surface 33 extends along the insulating film 31 (first main surface 3).
  • the electrode surface 33 may extend approximately parallel to the insulating film 31 (first main surface 3).
  • the first side wall 34 is formed at a distance from one end of the insulating film 31 to the other end in the first direction X, and extends in the vertical direction Z.
  • the second side wall 35 is formed at a distance from the other end of the insulating film 31 to the one end in the first direction X, and extends in the vertical direction Z.
  • the first sidewall 34 and the second sidewall 35 may extend perpendicularly to the insulating film 31. That is, the gate electrode 32 may be formed in a quadrangular shape (flattened rectangular shape) in cross-sectional view. The first sidewall 34 and the second sidewall 35 may be inclined obliquely toward the electrode surface 33. That is, the gate electrode 32 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in cross-sectional view.
  • the gate electrode 32 may have a width of 1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the gate electrode 32 is the width in a direction perpendicular to the extension direction (i.e., the first direction X).
  • the width of the gate electrode 32 may have a value belonging to at least one of the ranges of 1 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 5 ⁇ m or less, 5 ⁇ m or more and 7.5 ⁇ m or less, and 7.5 ⁇ m or more and 10 ⁇ m or less.
  • the width of the gate electrode 32 is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the gate electrode 32 may have a thickness of 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the thickness of the gate electrode 32 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the thickness of the gate electrode 32 is preferably 0.2 ⁇ m or more and 1 ⁇ m or less.
  • the gate structure 30 includes a first silicide portion 40 partially formed on the surface portion of the electrode surface 33 of each gate electrode 32. That is, each gate electrode 32 has a first silicide portion 40 formed on the surface portion of the electrode surface 33.
  • the first silicide portion 40 is a polycide portion formed by silicidizing the polysilicon of the gate electrode 32.
  • the first silicide portion 40 may be referred to as a "first metal semiconductor compound layer,” a "first silicide layer (polycide layer),” a "first silicide region (polycide region),” etc.
  • the first silicide portion 40 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide.
  • the first silicide portion 40 is preferably made of Ti silicide, Ni silicide, or Co silicide.
  • the configuration (layout) of the first silicide portion 40 in one gate electrode 32 is described below.
  • the first silicide portion 40 is formed at a distance inward from at least one of the first sidewall 34 and the second sidewall 35 of the gate electrode 32, and at least one of the peripheral portions on the first sidewall 34 side and the second sidewall 35 side is exposed on the electrode surface 33.
  • the first silicide portion 40 is formed at a distance inward from both the first sidewall 34 and the second sidewall 35, and at least one of the peripheral portions on the first sidewall 34 side and the second sidewall 35 side is exposed on the electrode surface 33.
  • the first silicide portion 40 is formed at a distance from the insulating film 31 toward the electrode surface 33 in the thickness direction, and faces the insulating film 31 across a part of the gate electrode 32 (polysilicon).
  • the first silicide portion 40 is preferably formed at a distance from the middle of the gate electrode 32 toward the electrode surface 33 in the thickness direction.
  • the first silicide portion 40 may have a bottom portion located on the insulating film 31 side relative to the middle portion of the gate electrode 32.
  • the first silicide portion 40 is formed in a band shape extending along the gate electrode 32 in a plan view. In other words, the extension direction of the first silicide portion 40 coincides with the off-direction of the SiC single crystal.
  • the first silicide portion 40 faces one surface drift region 22 in the stacking direction.
  • the first silicide portion 40 may be formed at an interval on the surface drift region 22 side from two adjacent body regions 20 in a plan view, and may face only one surface drift region 22 in the stacking direction.
  • the first silicide portion 40 may extend across two adjacent body regions 20 across one surface drift region 22 in a plan view.
  • the first silicide portion 40 may be formed at a distance from the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side toward the surface drift region 22, and may face the surface drift region 22, the first channel region 26, and the second channel region 27 in the stacking direction.
  • the first silicide portion 40 is formed to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 in the stacking direction.
  • the first silicide portion 40 faces either one or both (preferably both) of the first channel region 26 and the second channel region 27. It is preferable that the first silicide portion 40 faces the entire first channel region 26 in the stacking direction in a cross-sectional view. It is preferable that the first silicide portion 40 faces the entire second channel region 27 in the stacking direction in a cross-sectional view.
  • the first silicide portions 40 may be formed at intervals of 0.1 ⁇ m to 2.5 ⁇ m from the first sidewall 34 (second sidewall 35) inward.
  • the intervals of the first silicide portions 40 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m to 0.25 ⁇ m, 0.25 ⁇ m to 0.5 ⁇ m, 0.5 ⁇ m to 0.75 ⁇ m, 0.75 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.25 ⁇ m, 1.25 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 1.75 ⁇ m, 1.75 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.25 ⁇ m, and 2.25 ⁇ m to 2.5 ⁇ m.
  • the intervals of the first silicide portions 40 are preferably 0.2 ⁇ m to 1 ⁇ m. It is particularly preferable that the spacing between the first silicide portions 40 be 0.5 ⁇ m or less.
  • the gate structure 30 includes a first polysilicon portion 41 formed on the electrode surface 33 of each gate electrode 32 in a portion other than the first silicide portion 40. That is, each gate electrode 32 has a first silicide portion 40 and a first polysilicon portion 41 formed on the surface portion of the electrode surface 33.
  • the first polysilicon portion 41 may be referred to as a "first polysilicon layer", a “first polysilicon region”, etc.
  • the configuration (layout) of the first polysilicon portion 41 in one gate electrode 32 will be described below.
  • the first polysilicon portion 41 may have various layouts depending on the layout of the first silicide portion 40. When the first silicide portion 40 is formed spaced inward from at least one of the first sidewall 34 and the second sidewall 35 of the gate electrode 32, the first polysilicon portion 41 is formed in an area on at least one side of the first sidewall 34 and the second sidewall 35 on the electrode surface 33.
  • the first silicide portion 40 is formed at a distance inward from both the first sidewall 34 and the second sidewall 35 of the gate electrode 32. Therefore, the first polysilicon portion 41 has one first polysilicon portion 41A defined in an area on the first sidewall 34 side of the first silicide portion 40, and the other first polysilicon portion 41B defined in an area on the second sidewall 35 side of the first silicide portion 40 (see Figures 5 and 7).
  • One of the first polysilicon portions 41A forms the first sidewall 34 of the gate electrode 32 in addition to the peripheral portion on one side of the electrode surface 33.
  • One of the first polysilicon portions 41A extends in a band shape in the second direction Y along the first silicide portion 40.
  • One of the first polysilicon portions 41A forms the first sidewall 34 over the entire area of the gate electrode 32 in a plan view.
  • One of the first polysilicon portions 41A faces the first source region 23 in the stacking direction.
  • One of the first polysilicon portions 41A may face only the first source region 23 in the stacking direction.
  • One of the first polysilicon portions 41A may face the first source region 23 and the first channel region 26 in the stacking direction.
  • One of the first polysilicon portions 41A may face the surface drift region 22, the first source region 23, and the first channel region 26 in the stacking direction.
  • one of the first polysilicon portions 41A is formed at a distance from the first channel region 26 toward the first sidewall 34 in a plan view. In other words, it is preferable that one of the first polysilicon portions 41A does not face the first channel region 26 in the stacking direction in a cross-sectional view.
  • the other first polysilicon portion 41B forms the second sidewall 35 of the gate electrode 32 in addition to the peripheral portion on the other side of the electrode surface 33.
  • the other first polysilicon portion 41B faces the one first polysilicon portion 41A in the first direction X across the first silicide portion 40, and extends in a strip shape in the second direction Y along the first silicide portion 40. In other words, the other first polysilicon portion 41B extends approximately parallel to the one first polysilicon portion 41A.
  • the other first polysilicon portion 41B forms the second sidewall 35 over the entire area of the gate electrode 32 in a plan view.
  • the other first polysilicon portion 41B faces the second source region 24 in the stacking direction.
  • the other first polysilicon portion 41B may face only the second source region 24 in the stacking direction.
  • the other first polysilicon portion 41B may face the second source region 24 and the second channel region 27 in the stacking direction.
  • the other first polysilicon portion 41B may face the surface drift region 22, the second source region 24, and the second channel region 27 in the stacking direction.
  • the other first polysilicon portion 41B is formed at a distance from the second channel region 27 toward the second sidewall 35 in a plan view. In other words, it is preferable that the other first polysilicon portion 41B does not face the second channel region 27 in the stacking direction in a cross-sectional view.
  • the first polysilicon portion 41 has a flat surface with respect to the electrode surface 33.
  • the first polysilicon portion 41 forms the flat electrode surface 33 together with the first silicide portion 40.
  • the width of the first polysilicon portion 41 corresponds to the spacing between the first silicide portions 40 described above.
  • the gate electrode 32 (first silicide portion 40 and first polysilicon portion 41) may have the layout shown in Figures 10A to 10C.
  • Figures 10A to 10C are enlarged cross-sectional views showing the gate electrode 32 according to the second, third and fourth examples.
  • the gate electrode 32 does not necessarily have to have any one of the configurations of the first to fourth examples ( Figure 7, Figures 10A to 10C).
  • the gate electrode 32 may simultaneously include features of at least two of the configurations of the first to fourth examples.
  • the gate electrodes 32 of the first to fourth examples are all forms that can be obtained by adjusting process conditions during the manufacturing process.
  • the first silicide portion 40 may have a portion that protrudes upward (opposite the first main surface 3) with respect to the electrode surface 33.
  • the first silicide portion 40 may protrude upward over the entire area of the electrode surface 33.
  • the first polysilicon portion 41 may have a portion that is located on the first main surface 3 (insulating film 31) side with respect to the upper end of the first silicide portion 40.
  • the first polysilicon portion 41 may be located on the first main surface 3 (insulating film 31) side with respect to the upper end of the first silicide portion 40 over the entire area of the electrode surface 33.
  • the first silicide portion 40 may have a portion recessed toward the first main surface 3 (insulating film 31) side from the electrode surface 33.
  • the first silicide portion 40 may be recessed toward the first main surface 3 (insulating film 31) side from the electrode surface 33 over the entire area of the electrode surface 33.
  • the first polysilicon portion 41 may have a portion protruding upward (opposite the first main surface 3) from the first silicide portion 40.
  • the first polysilicon portion 41 may protrude upward from the first silicide portion 40 over the entire area of the electrode surface 33.
  • the gate electrode 32 may include at least one (in this embodiment, both) of the first electrode recess 42 and the second electrode recess 43.
  • FIG. 10C shows an example in which the first electrode recess 42 and the second electrode recess 43 are applied to the gate electrode 32 of the first example (see FIG. 7).
  • either or both of the first electrode recess 42 and the second electrode recess 43 may be applied to the gate electrode 32 of the second example (see FIG. 10A) or the gate electrode 32 of the third example (see FIG. 10B).
  • the first electrode recess 42 is recessed toward the first main surface 3 (insulating film 31) at the corner connecting the electrode surface 33 and the first sidewall 34.
  • the first electrode recess 42 is formed in a strip shape extending along the gate electrode 32 (first sidewall 34).
  • the bottom of the first electrode recess 42 is preferably formed with a gap from the middle part of the gate electrode 32 toward the electrode surface 33.
  • the bottom of the first electrode recess 42 may have a bottom located on the insulating film 31 side relative to the middle part of the gate electrode 32.
  • the second electrode recess 43 is recessed toward the first main surface 3 (insulating film 31) at the corner connecting the electrode surface 33 and the second sidewall 35.
  • the second electrode recess 43 is formed in a strip shape extending along the gate electrode 32 (second sidewall 35). It is preferable that the bottom of the second electrode recess 43 is formed with a gap from the middle of the gate electrode 32 toward the electrode surface 33.
  • the bottom of the second electrode recess 43 may have a bottom located on the insulating film 31 side relative to the middle part of the gate electrode 32. It is preferable that the depth of the second electrode recess 43 is approximately equal to the depth of the first electrode recess 42.
  • the first silicide portion 40 is formed on the surface portion of the electrode surface 33 at a distance inward from the first electrode recess 42 and the second electrode recess 43, exposing both the first electrode recess 42 and the second electrode recess 43.
  • the bottom of the first silicide portion 40 may be located on the electrode surface 33 side with respect to the depth position of the bottom of the first electrode recess 42 (second electrode recess 43).
  • the bottom of the first silicide portion 40 may be located on the first main surface 3 (insulating film 31) side with respect to the depth position of the bottom of the first electrode recess 42 (second electrode recess 43).
  • the distance between the first silicide portion 40 and the first electrode recess 42 (second electrode recess 43) is preferably greater than the width of the first electrode recess 42 (second electrode recess 43).
  • the distance between the first silicide portion 40 and the first electrode recess 42 (second electrode recess 43) may be less than the width of the first electrode recess 42 (second electrode recess 43).
  • One of the first polysilicon portions 41A has a portion exposed from the first electrode recess 42.
  • the one of the first polysilicon portions 41A is formed over the entire area of the first electrode recess 42.
  • the one of the first polysilicon portions 41A has a portion located in the area between the first silicide portion 40 and the first electrode recess 42.
  • the other first polysilicon portion 41B has a portion exposed from the second electrode recess 43.
  • the other first polysilicon portion 41B is formed over the entire area of the second electrode recess 43.
  • the other first polysilicon portion 41B has a portion located in the area between the first silicide portion 40 and the second electrode recess 43.
  • the gate electrode 32 does not necessarily have to include both the first electrode recess 42 and the second electrode recess 43 at the same time.
  • the gate electrode 32 may have only the first electrode recess 42 and not the second electrode recess 43.
  • the gate electrode 32 may have only the second electrode recess 43 and not the first electrode recess 42.
  • the semiconductor device 1 includes a p-type termination region 45 formed on the first main surface 3 in the peripheral region 9.
  • the termination region 45 may also be referred to as a "well region”, a “termination well region”, etc.
  • the termination region 45 may have a p-type impurity concentration different from the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the termination region 45 may be lower than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the termination region 45 may be approximately equal to the p-type impurity concentration of the body region 20.
  • the termination region 45 may have a p-type impurity concentration different from the p-type impurity concentration of the outer body region 21.
  • the p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the outer body region 21.
  • the p-type impurity concentration of the termination region 45 may be lower than the p-type impurity concentration of the outer body region 21.
  • the p-type impurity concentration of the termination region 45 may be approximately equal to the p-type impurity concentration of the outer body region 21.
  • the termination region 45 is spaced inward from the periphery of the first main surface 3 and is formed in the region between the periphery of the first main surface 3 and the outer body region 21.
  • the termination region 45 extends in a band shape along the outer body region 21 in a plan view.
  • the termination region 45 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the terminal region 45 surrounds the outer body region 21 in a plan view and is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the terminal region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the termination region 45 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the termination region 45 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3.
  • the termination region 45 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21.
  • the thickness of the termination region 45 may be greater than the thickness of the outer body region 21, or may be less than the thickness of the outer body region 21.
  • the termination region 45 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21. This means that the termination region 45 is electrically connected to the outer body region 21. That is, in this embodiment, the termination region 45 is electrically connected to the multiple body regions 20 via the outer body region 21. In this embodiment, the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21 around the entire periphery.
  • the termination region 45 (inner edge) has an overlap region 46 that overlaps the outer edge of the outer body region 21.
  • the overlap region 46 is a high-concentration region that includes the outer edge of the outer body region 21 and the inner edge of the termination region 45.
  • the overlap region 46 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the termination region 45, and has a p-type impurity concentration that is higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45.
  • the p-type impurity concentration of the overlap region 46 is higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the overlap region 46 may be lower than the p-type impurity concentration of the contact region 25.
  • the p-type impurity concentration of the overlap region 46 may be higher than the p-type impurity concentration of the contact region 25.
  • the overlap region 46 extends in a band shape along the outer body region 21 in a plan view.
  • the overlap region 46 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and defines the active region 8 from multiple directions.
  • the overlap region 46 is defined in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the overlap region 46 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a planar view in an arc shape (preferably a quarter arc shape) (see FIG. 4). It is preferable that the width of the overlap region 46 is greater than the width of the body region 20. Of course, the width of the overlap region 46 may be less than the width of the body region 20.
  • the semiconductor device 1 may have a relatively high-concentration p-type well region (46) instead of the overlap region 46.
  • the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45.
  • the p-type impurity concentration of the well region (46) is higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the well region (46) may be approximately equal to the p-type impurity concentration of the contact region 25.
  • the p-type impurity concentration of the well region (46) may be less than the p-type impurity concentration of the contact region 25, or may be higher than the p-type impurity concentration of the contact region 25.
  • the well region (46) may be formed in either or both of the surface layer of the outer body region 21 and the surface layer of the termination region 45. Such a configuration is effective when the termination region 45 has a p-type impurity concentration approximately equal to the p-type impurity concentration of the outer body region 21 and is formed as part of the outer body region 21 (the pull-out portion).
  • the semiconductor device 1 includes at least one p-type field region 47 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the multiple field regions 47 may be formed in an electrically floating state.
  • the multiple field regions 47 may be fixed to the source potential.
  • the number of field regions 47 is arbitrary.
  • the number of field regions 47 may be 1 or more and 20 or less.
  • the number of field regions 47 may have a value that belongs to at least one of the following ranges: 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less.
  • the number of field regions 47 is typically 1 or more and 8 or less.
  • the semiconductor device 1 includes three field regions 47.
  • the multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the active region 8, with a gap inward from the periphery of the first main surface 3. Specifically, the multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the outer body region 21. More specifically, the multiple field regions 47 are arranged in the region between the periphery of the first main surface 3 and the termination region 45, with a gap from the termination region 45 to the periphery side of the first main surface 3.
  • the multiple field regions 47 are formed in a band shape extending along the active region 8 (termination region 45) in a plan view.
  • Each of the multiple field regions 47 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the multiple field regions 47 are formed in a polygonal ring shape (a square ring shape in this embodiment) surrounding the active region 8 (termination region 45) in a plan view.
  • the multiple field regions 47 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the multiple field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the multiple field regions 47 are formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3.
  • the width, depth, spacing, p-type impurity concentration, etc. of the multiple field regions 47 are arbitrary and can take various values depending on the electric field to be relaxed.
  • the width of the multiple field regions 47 may be approximately constant or may be non-uniform.
  • the width of the multiple field regions 47 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the width of the multiple field regions 47 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the depth of the multiple field regions 47 may be approximately constant or may be non-uniform.
  • the depth of the multiple field regions 47 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the depth of the multiple field regions 47 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the multiple field regions 47 may have a relatively shallow portion and a deep portion that is deeper than the shallow portion.
  • the shallow portion may be formed on the inner side, and the deep portion may be formed on the peripheral edge side.
  • the shallow portion may be formed on the peripheral edge side, and the deep portion may be formed on the inner side.
  • the spacing between the multiple field regions 47 may be approximately constant or may be non-uniform.
  • the spacing between the multiple field regions 47 may gradually increase toward the peripheral edge of the first main surface 3.
  • the spacing between the multiple field regions 47 may gradually decrease toward the peripheral edge of the first main surface 3.
  • the p-type impurity concentration of the multiple field regions 47 may be approximately constant or may be non-uniform.
  • the p-type impurity concentration of the multiple field regions 47 may gradually increase toward the peripheral edge side of the first main surface 3.
  • the p-type impurity concentration of the multiple field regions 47 may gradually decrease toward the peripheral edge side of the first main surface 3.
  • the p-type impurity concentration of the multiple field regions 47 may be approximately equal to the p-type impurity concentration of the body region 20 (outer body region 21).
  • the p-type impurity concentration of the multiple field regions 47 may be higher than the p-type impurity concentration of the body region 20 (outer body region 21), or may be lower than the p-type impurity concentration of the body region 20 (outer body region 21).
  • the p-type impurity concentration of the multiple field regions 47 may be approximately equal to the p-type impurity concentration of the termination region 45.
  • the p-type impurity concentration of the multiple field regions 47 may be higher than the p-type impurity concentration of the termination region 45, or may be lower than the p-type impurity concentration of the termination region 45.
  • the semiconductor device 1 includes a peripheral insulating film 51 that covers the first main surface 3 in the peripheral region 9.
  • the peripheral insulating film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the peripheral insulating film 51 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 51 includes a silicon oxide film made of an oxide of the chip 2.
  • the peripheral insulating film 51 is preferably made of the same type of insulating material as the insulating film 31.
  • the peripheral insulating film 51 preferably has a thickness approximately equal to that of the insulating film 31.
  • the peripheral insulating film 51 covers the first main surface 3 in the peripheral region 9 in the form of a film.
  • the peripheral insulating film 51 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47.
  • the peripheral insulating film 51 is connected to the multiple insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 51 is formed integrally with the multiple insulating films 31, and forms one insulating film together with the multiple insulating films 31.
  • the semiconductor device 1 includes a gate wiring 52 disposed on the first main surface 3 in the peripheral region 9.
  • the semiconductor device 1 does not have a sidewall structure (spacer) made of an insulator (e.g., silicon oxide and/or silicon nitride, etc.) on the side of the gate wiring 52.
  • an insulator e.g., silicon oxide and/or silicon nitride, etc.
  • the gate wiring 52 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 32.
  • the gate wiring 52 is connected to the multiple gate electrodes 32 and applies gate signals to the multiple gate electrodes 32.
  • the gate wiring 52 may be referred to as a "polysilicon gate wiring", a "poly gate wiring”, a "second gate electrode”, etc.
  • the gate wiring 52 includes a conductive semiconductor polycrystal.
  • the gate wiring 52 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the gate wiring 52 has the same conductivity type as the gate electrode 32. The conductivity type of the gate wiring 52 is adjusted according to the conductivity type of the gate electrode 32.
  • the gate wiring 52 is disposed on the peripheral insulating film 51 in the peripheral region 9. Specifically, the gate wiring 52 is disposed on a portion of the peripheral insulating film 51 that covers the outer body region 21, and faces the outer body region 21 across the peripheral insulating film 51.
  • the gate wiring 52 is formed at a distance from the periphery of the first main surface 3 toward the active region 8, and extends in a strip along the active region 8.
  • the gate wiring 52 has a portion that extends in a strip in the first direction X and a portion that extends in a strip in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the gate wiring 52 surrounds the active region 8 in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the gate wiring 52 may be either ended or endless.
  • the gate wiring 52 is formed narrower than the outer body region 21 in a plan view, and is disposed above the outer body region 21 at a distance from the inner and outer edges of the outer body region 21.
  • the multiple gate electrodes 32 are extended up to above the outer body region 21, and the gate wiring 52 is connected to the multiple gate electrodes 32 above the outer body region 21.
  • the thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32.
  • the width of the gate wiring 52 is preferably greater than the width of the gate electrode 32.
  • the width of the gate wiring 52 is the width in a direction perpendicular to the extension direction.
  • the ratio of the width of the gate wiring 52 to the width of the gate electrode 32 may be 1 or more and 50 or less.
  • the width ratio may have a value belonging to at least one of the ranges of 1 to 10, 10 to 20, 20 to 30, 30 to 40, and 40 to 50.
  • the width ratio may be 5 or more.
  • the width ratio may be 20 to 40.
  • the width of the gate wiring 52 may be less than or equal to the width of the gate electrode 32.
  • the width of the gate wiring 52 may be greater than the width of the outer body region 21.
  • the gate wiring 52 has a wiring surface 53, a first wiring sidewall 54 on the inner edge side, and a second wiring sidewall 55 on the outer edge side.
  • the wiring surface 53 extends along the peripheral insulating film 51 (first main surface 3).
  • the wiring surface 53 may extend approximately parallel to the peripheral insulating film 51 (first main surface 3).
  • the first wiring sidewall 54 extends in the vertical direction Z on the peripheral insulating film 51, and the second wiring sidewall 55 extends in the vertical direction Z on the peripheral insulating film 51.
  • the first wiring sidewall 54 is connected to the multiple gate electrodes 32 (the first sidewall 34 and the second sidewall 35) in the portion extending in the first direction X.
  • the gate wiring 52 has multiple portions connected to the multiple gate electrodes 32 in a T-shape. As a result, the gate wiring 52 is electrically connected to the multiple gate electrodes 32.
  • the first wiring sidewall 54 and the second wiring sidewall 55 may extend perpendicular to the peripheral insulating film 51. That is, the gate wiring 52 may be formed in a quadrangular shape (flattened rectangular shape) in cross section. The first wiring sidewall 54 and the second wiring sidewall 55 may be inclined obliquely toward the wiring surface 53. That is, the gate wiring 52 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in cross section.
  • the semiconductor device 1 includes a second silicide portion 60 partially formed on the surface portion of the wiring surface 53 of the gate wiring 52. That is, the gate wiring 52 has a second silicide portion 60 on the surface portion of the wiring surface 53.
  • the second silicide portion 60 is a polycide portion formed by silicidizing the polysilicon of the gate wiring 52.
  • the second silicide portion 60 may be referred to as a "second metal semiconductor compound layer," a "second silicide layer (polycide layer),” a “second silicide region (polycide region),” etc.
  • the second silicide portion 60 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide.
  • the second silicide portion 60 is preferably made of Ti silicide, Ni silicide, or Co silicide. It is particularly preferable that the second silicide portion 60 is made of the same type of silicide as the first silicide portion 40.
  • the second silicide portion 60 is formed at a distance inward from at least one of the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52, and exposes at least one of the peripheral portion on the first wiring sidewall 54 side and the peripheral portion on the second wiring sidewall 55 side on the wiring surface 53.
  • the second silicide portion 60 is formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55, and exposes both the peripheral portion on the first wiring sidewall 54 side and the peripheral portion on the second wiring sidewall 55 side on the wiring surface 53.
  • the second silicide portion 60 is not exposed from either the first wiring sidewall 54 or the second wiring sidewall 55.
  • the second silicide portion 60 is formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55 over the entire surface portion of the wiring surface 53 in a plan view.
  • the second silicide portion 60 is formed at a distance from the peripheral insulating film 51 toward the wiring surface 53 in the thickness direction, and faces the peripheral insulating film 51 across a part of the gate wiring 52 (polysilicon).
  • the second silicide portion 60 is preferably formed at a distance from the middle of the gate wiring 52 toward the wiring surface 53 in the thickness direction.
  • the second silicide portion 60 may have a bottom portion located on the peripheral insulating film 51 side relative to the middle part of the gate wiring 52.
  • the second silicide portion 60 extends in a strip shape along the gate wiring 52 on the wiring surface 53, and faces the outer body region 21 in the stacking direction.
  • the second silicide portion 60 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y.
  • the second silicide portion 60 surrounds the active region 8 in a plan view, and is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the second silicide portion 60 may be either ended or endless.
  • the second silicide portion 60 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.
  • the second silicide portion 60 is connected to the first silicide portions 40 at the connection portion of the gate electrodes 32 and the gate wiring 52.
  • the second silicide portion 60 is formed integrally with the first silicide portions 40, and has a plurality of portions connected in a T-shape to the first silicide portions 40 (see FIG. 5).
  • the second silicide portion 60 has a surface that is flat relative to the wiring surface 53. It is preferable that the second silicide portion 60 forms a single flat surface together with the multiple first silicide portions 40 at the connection portion of the multiple gate electrodes 32 and the gate wiring 52. In other words, it is preferable that the second silicide portion 60 is formed approximately flush with the multiple first silicide portions 40.
  • the second silicide portions 60 may be formed at intervals of 0.1 ⁇ m or more and 5 ⁇ m or less inward from the first wiring sidewall 54 (second wiring sidewall 55).
  • the intervals of the second silicide portions 60 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the spacing between the second silicide portions 60 is preferably 0.2 ⁇ m or more and 1 ⁇ m or less. It is particularly preferable that the spacing between the second silicide portions 60 is 0.5 ⁇ m or less.
  • the spacing between the second silicide portions 60 may be approximately equal to the spacing between the first silicide portions 40.
  • the spacing between the second silicide portions 60 may be greater than the spacing between the first silicide portions 40.
  • the spacing between the second silicide portions 60 may be smaller than the spacing between the first silicide portions 40.
  • the semiconductor device 1 includes a second polysilicon portion 61 formed on the wiring surface 53 of each gate wiring 52 in a portion other than the second silicide portion 60. That is, each gate wiring 52 has a second silicide portion 60 and a second polysilicon portion 61 formed on the surface portion of the wiring surface 53.
  • the second polysilicon portion 61 may be referred to as a "second polysilicon layer", a "second polysilicon region”, etc.
  • the second polysilicon portion 61 may have various layouts depending on the layout of the second silicide portion 60.
  • the second silicide portion 60 is formed spaced inward from at least one of the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52, the second polysilicon portion 61 is formed in an area on at least one side of the first wiring sidewall 54 and the second wiring sidewall 55 on the wiring surface 53.
  • the second silicide portion 60 is formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52. Therefore, the second polysilicon portion 61 has one second polysilicon portion 61A defined in an area on the first wiring sidewall 54 side with respect to the second silicide portion 60, and the other second polysilicon portion 61B defined in an area on the second wiring sidewall 55 side with respect to the second silicide portion 60 (see Figures 5 and 9).
  • One of the second polysilicon portions 61A forms the first wiring sidewall 54 of the gate wiring 52 in addition to the peripheral portion on one side of the wiring surface 53.
  • One of the second polysilicon portions 61A extends in a strip shape along the second silicide portion 60.
  • one of the second polysilicon portions 61A forms the first wiring sidewall 54 over the entire area of the gate wiring 52.
  • One of the second polysilicon portions 61A faces the outer body region 21 in the stacking direction.
  • the other second polysilicon portion 61B forms the second wiring sidewall 55 of the gate wiring 52 in addition to the peripheral portion on the other side of the wiring surface 53.
  • the other second polysilicon portion 61B faces the second polysilicon portion 61B on one side across the second silicide portion 60, and extends in a strip shape along the second silicide portion 60.
  • the other second polysilicon portion 61B extends approximately parallel to the one second polysilicon portion 61A.
  • the other second polysilicon portion 61B forms the second wiring sidewall 55 over the entire area of the gate wiring 52.
  • the other second polysilicon portion 61A faces the outer body region 21 in the stacking direction.
  • the second polysilicon portion 61 (one of the second polysilicon portions 61A) is connected to the first polysilicon portions 41 at the connection portion of the gate electrodes 32 and the gate wiring 52. In other words, the second polysilicon portion 61 is formed integrally with the first polysilicon portions 41.
  • the second polysilicon portion 61 has a plurality of portions that are connected in an L-shape to the first polysilicon portions 41 at the connection corners of the gate electrodes 32 and the gate wiring 52 (see FIG. 5).
  • the second polysilicon portion 61 has a flat surface relative to the wiring surface 53.
  • the second polysilicon portion 61 forms the flat wiring surface 53 together with the second silicide portion 60.
  • the second polysilicon portion 61 preferably forms a single flat surface together with the multiple first polysilicon portions 41 at the connection portion of the multiple gate electrodes 32 and the gate wiring 52.
  • the second polysilicon portion 61 is preferably formed to be approximately flush with the multiple first polysilicon portions 41.
  • the width of the second silicide portion 60 corresponds to the spacing between the second silicide portions 60 described above.
  • the gate wiring 52 (second silicide portion 60 and second polysilicon portion 61) may have the layout shown in Figures 11A to 11C.
  • Figures 11A to 11C are enlarged cross-sectional views showing gate wiring 52 according to the second, third and fourth examples.
  • the gate wiring 52 does not necessarily have to have any one of the configurations of the first to fourth examples (FIG. 9, FIG. 11A to FIG. 11C).
  • the gate wiring 52 may simultaneously include the features of at least two of the configurations of the first to fourth examples.
  • the gate wiring 52 of the first to fourth examples is a form that can be obtained by adjusting the process conditions during the manufacturing process.
  • the second silicide portion 60 may have a portion that protrudes upward (the side opposite to the first main surface 3) relative to the wiring surface 53.
  • the second silicide portion 60 may protrude upward over the entire area of the wiring surface 53.
  • the second polysilicon portion 61 may have a portion located on the first main surface 3 (peripheral insulating film 51) side relative to the upper end of the second silicide portion 60.
  • the second polysilicon portion 61 may be located on the first main surface 3 (peripheral insulating film 51) side relative to the upper end of the second silicide portion 60 over the entire area of the wiring surface 53.
  • the protrusion of the second silicide portion 60 may be connected to the protrusion of the first silicide portion 40.
  • the second polysilicon portion 61 may be connected to the first polysilicon portion 41 in a region below the protrusions of the first silicide portion 40 and the protrusions of the second silicide portion 60.
  • the second silicide portion 60 may have a portion recessed toward the first main surface 3 (peripheral insulating film 51) side from the wiring surface 53.
  • the second silicide portion 60 may be recessed toward the first main surface 3 (peripheral insulating film 51) side from the wiring surface 53 over the entire area of the wiring surface 53.
  • the second polysilicon portion 61 may have a portion that protrudes upward (the side opposite to the first main surface 3) from the second silicide portion 60.
  • the second polysilicon portion 61 may protrude upward from the second silicide portion 60 over the entire area of the wiring surface 53.
  • the recess of the second silicide portion 60 may be connected to the recess of the first silicide portion 40.
  • the second polysilicon portion 61 may be connected to the first polysilicon portion 41 in a region above the recess of the first silicide portion 40 and the recess of the second silicide portion 60.
  • the gate wiring 52 may include at least one (in this embodiment, both) of the first wiring recess 62 and the second wiring recess 63.
  • FIG. 11C shows an example in which the first wiring recess 62 and the second wiring recess 63 are applied to the gate wiring 52 according to the first example (see FIG. 9).
  • first wiring recess 62 and the second wiring recess 63 may be applied to the gate wiring 52 of the second example (see FIG. 11A) or the gate wiring 52 of the third example (see FIG. 11B).
  • the first wiring recess 62 is recessed toward the first main surface 3 (peripheral insulating film 51) at the corner that connects the wiring surface 53 and the first wiring sidewall 54.
  • the first wiring recess 62 is formed in a strip shape that extends along the gate wiring 52 (first wiring sidewall 54).
  • the bottom of the first wiring recess 62 is preferably formed at a distance from the middle of the gate wiring 52 toward the wiring surface 53 in the thickness direction. If the gate wiring 52 has a relatively small thickness, the bottom of the first wiring recess 62 may have a bottom located on the outer insulating film 51 side relative to the middle of the gate wiring 52.
  • the second wiring recess 63 is recessed toward the first main surface 3 (peripheral insulating film 51) at the corner connecting the wiring surface 53 and the second wiring sidewall 55.
  • the second wiring recess 63 is formed in a band shape extending along the gate wiring 52 (second wiring sidewall 55). It is preferable that the bottom of the second wiring recess 63 is formed with a gap from the middle of the gate wiring 52 toward the wiring surface 53 in the thickness direction.
  • the bottom of the second wiring recess 63 may have a bottom located on the peripheral insulating film 51 side relative to the middle part of the gate wiring 52. It is preferable that the depth of the second wiring recess 63 is approximately equal to the depth of the first wiring recess 62.
  • the second silicide portion 60 is formed on the surface portion of the wiring surface 53 at a distance inward from the first wiring recess 62 and the second wiring recess 63, exposing both the first wiring recess 62 and the second wiring recess 63.
  • the bottom of the second silicide portion 60 may be located on the wiring surface 53 side relative to the depth position of the bottom of the first wiring recess 62 (second wiring recess 63).
  • the bottom of the second silicide portion 60 may be located on the first main surface 3 (peripheral insulating film 51) side relative to the depth position of the bottom of the first wiring recess 62 (second wiring recess 63).
  • the distance between the second silicide portion 60 and the first wiring recess 62 (second wiring recess 63) is preferably greater than the width of the first wiring recess 62 (second wiring recess 63).
  • the distance between the second silicide portion 60 and the first wiring recess 62 (second wiring recess 63) may be less than the width of the first wiring recess 62 (second wiring recess 63).
  • One of the second polysilicon portions 61A has a portion exposed from the first wiring recess 62. In this embodiment, one of the second polysilicon portions 61A is formed over the entire area of the first wiring recess 62. One of the second polysilicon portions 61A has a portion located in the area between the second silicide portion 60 and the first wiring recess 62.
  • the other second polysilicon portion 61B in this embodiment, has a portion exposed from the second wiring recess 63.
  • the other second polysilicon portion 61B in this embodiment, is formed over the entire area of the second wiring recess 63.
  • the other second polysilicon portion 61B has a portion located in the area between the second silicide portion 60 and the second wiring recess 63.
  • the first wiring recess 62 of the gate wiring 52 may be connected to both the first electrode recess 42 and the second electrode recess 43.
  • the first wiring recess 62 may have a plurality of portions connected in an L-shape to the plurality of first electrode recesses 42 at the connection corner of the plurality of gate electrodes 32 and the gate wiring 52.
  • the first wiring recess 62 may also have a plurality of portions connected in an L-shape to the plurality of second electrode recesses 43 at the connection corner.
  • the gate wiring 52 does not necessarily have to include both the first wiring recess 62 and the second wiring recess 63 at the same time.
  • the gate wiring 52 may have only the first wiring recess 62 and not the second wiring recess 63.
  • the gate wiring 52 may have only the second wiring recess 63 and not the first wiring recess 62.
  • At least one of the gate wirings 52 according to the first to fourth examples can be combined with at least one of the gate electrodes 32 according to the first to fourth examples (see FIG. 7, FIG. 10A to FIG. 10C). From the viewpoint of uniformity of the layout of the gate electrodes 32 and the layout of the gate wirings 52, it is preferable that the gate wiring 52 according to the first example (see FIG. 9) be combined with the gate electrode 32 according to the first example (see FIG. 7).
  • the gate wiring 52 of the second example is preferably combined with the gate electrode 32 of the second example (see FIG. 11A).
  • the gate wiring 52 of the third example is preferably combined with the gate electrode 32 of the third example (see FIG. 11B).
  • the gate wiring 52 of the fourth example is preferably combined with the gate electrode 32 of the fourth example (see FIG. 11C).
  • the semiconductor device 1 includes an insulating interlayer film 70 that covers the first main surface 3.
  • the interlayer film 70 may also be called an "interlayer insulating film", an “intermediate insulating film”, etc.
  • the interlayer film 70 has an insulating surface 71 that extends along the first main surface 3.
  • the interlayer film 70 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.
  • the interlayer film 70 covers the multiple gate structures 30 in the active region 8. For each gate structure 30, the interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32. In other words, the interlayer film 70 has a portion that directly covers the electrode surface 33, the first sidewall 34, and the second sidewall 35 of the gate electrode 32.
  • the interlayer film 70 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 between them.
  • the interlayer film 70 directly covers both the peripheral insulating film 51 and the gate wiring 52.
  • the interlayer film 70 has a portion that directly covers the wiring surface 53, the first wiring sidewall 54, and the second wiring sidewall 55 of the gate wiring 52.
  • the interlayer film 70 is continuous with the first to fourth side surfaces 5A to 5D.
  • the interlayer film 70 is formed at a distance inward from the first to fourth side surfaces 5A to 5D, and may expose the peripheral portion of the first main surface 3 (first semiconductor region 6).
  • the interlayer film 70 has a layered structure including a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film) that are layered in this order from the first main surface 3 side.
  • the interlayer film 70 has an insulating surface 71 formed by the second oxide film 73.
  • the first oxide film 72 has a single layer structure made of a silicon oxide film with no added impurities.
  • the first oxide film 72 may be referred to as an NSG film (Nondoped Silicate Glass film).
  • the first oxide film 72 collectively covers the active region 8 and the peripheral region 9.
  • the first oxide film 72 collectively covers the multiple gate structures 30 in the active region 8.
  • the first oxide film 72 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.
  • the first oxide film 72 has a first covering portion 74, a second covering portion 75, and a third covering portion 76.
  • the first covering portion 74 extends horizontally in a film shape along the insulating film 31 (first main surface 3), and has a portion that contacts the first sidewall 34 (second sidewall 35) of the gate electrode 32.
  • the first covering portion 74 (first oxide film 72) has a thickness less than the thickness of the gate electrode 32, and covers the insulating film 31 with a gap from the height position of the electrode surface 33 of the gate electrode 32 toward the insulating film 31.
  • the second covering portion 75 is pulled out from the first covering portion 74 toward the electrode surface 33 in the stacking direction, and directly covers the first side wall 34 (second side wall 35) in a film-like manner.
  • the second covering portion 75 (interlayer film 70) directly covers the first polysilicon portion 41 over the entire area of the first side wall 34 (second side wall 35).
  • the third covering portion 76 is pulled out from the second covering portion 75 onto the electrode surface 33 and extends horizontally along the electrode surface 33 in the form of a film.
  • the third covering portion 76 directly covers the entire electrode surface 33 between the first side wall 34 and the second side wall 35.
  • the third covering portion 76 (interlayer film 70) has a portion that directly covers the first silicide portion 40 on the electrode surface 33, and a portion that directly covers the first polysilicon portion 41. It is preferable that the third covering portion 76 forms an arc corner portion that is curved in an arc shape together with the second covering portion 75 in the portion that covers the corner portion of the gate electrode 32.
  • the arc corner portion may have a center of curvature on the gate electrode 32 side.
  • the first oxide film 72 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 therebetween.
  • the first oxide film 72 covers the gate wiring 52 in the peripheral region 9.
  • the first oxide film 72 has a first wiring covering portion 77, a second wiring covering portion 78, and a third wiring covering portion 79.
  • the first wiring covering portion 77 extends horizontally in a film shape along the peripheral insulating film 51 (first main surface 3), and has a portion that contacts the first wiring sidewall 54 (second wiring sidewall 55) of the gate wiring 52.
  • the first wiring covering portion 77 (first oxide film 72) has a thickness less than the thickness of the gate wiring 52, and covers the peripheral insulating film 51 with a gap from the height position of the wiring surface 53 of the gate wiring 52 toward the peripheral insulating film 51.
  • the second wiring covering portion 78 is pulled out from the first wiring covering portion 77 toward the wiring surface 53 in the stacking direction, and directly covers the first sidewall 34 (second sidewall 35) in a film-like manner.
  • the second wiring covering portion 78 (interlayer film 70) directly covers the second polysilicon portion 61 over the entire area of the first wiring sidewall 54 (second wiring sidewall 55).
  • the third wiring covering portion 79 is pulled out from the second wiring covering portion 78 onto the wiring surface 53 and extends horizontally along the wiring surface 53 in the form of a film.
  • the third wiring covering portion 79 directly covers the entire wiring surface 53 between the first wiring sidewall 54 and the second wiring sidewall 55.
  • the third wiring covering portion 79 (interlayer film 70) has a portion that directly covers the second silicide portion 60 on the wiring surface 53, and a portion that directly covers the second polysilicon portion 61. It is preferable that the third wiring covering portion 79 forms an arc corner portion that is curved in an arc shape together with the second wiring covering portion 78 in the portion that covers the corner portion of the gate wiring 52.
  • the arc corner portion may have a center of curvature on the gate wiring 52 side.
  • the second oxide film 73 may have a single layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus.
  • the silicon oxide film containing phosphorus may contain boron.
  • the silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass film).
  • the silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass film).
  • the second oxide film 73 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 72.
  • the second oxide film 73 may have a layered structure including a PSG film stacked on the first oxide film 72 and a BPSG film stacked on the PSG film.
  • the second oxide film 73 may have a layered structure including a BPSG film stacked on the first oxide film 72 and a PSG film stacked on the BPSG film.
  • the second oxide film 73 has a single layer structure made of a PSG film, as an example.
  • the second oxide film 73 covers the first oxide film 72 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 72 in between.
  • the second oxide film 73 collectively covers the multiple gate structures 30 in the active region 8 with the first oxide film 72 in between.
  • the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 72 in between.
  • the second oxide film 73 includes a first upper coating portion 80 and a second upper coating portion 81.
  • the first upper coating portion 80 covers the first coating portion 74 and the second coating portion 75 of the first oxide film 72.
  • the first upper coating portion 80 covers the insulating film 31 in the portion located above the first coating portion 74, sandwiching the first coating portion 74.
  • the first upper covering portion 80 extends in a film-like manner from above the first covering portion 74 along the second covering portion 75 in the stacking direction, and covers the first sidewall 34 (second sidewall 35) of the gate structure 30 with the second covering portion 75 in between.
  • the first upper covering portion 80 has a portion that covers the first polysilicon portion 41 with the second covering portion 75 in between.
  • the second upper covering portion 81 covers the third covering portion 76 of the first oxide film 72.
  • the second upper covering portion 81 extends horizontally in a film shape from the first upper covering portion 80 along the third covering portion 76, and covers the electrode surface 33 of the gate structure 30 with the third covering portion 76 in between.
  • the second upper covering portion 81 covers the entire electrode surface 33 with the third covering portion 76 in between the first sidewall 34 and the second sidewall 35.
  • the second upper covering portion 81 has a portion covering the first silicide portion 40 with the first oxide film 72 (third covering portion 76) in between, and a portion covering the first polysilicon portion 41 with the first oxide film 72 (third covering portion 76) in between. It is preferable that the second upper covering portion 81 forms an arc corner portion curved in an arc shape together with the first upper covering portion 80 in the portion covering the corner portion of the gate wiring 52.
  • the arc corner portion may have a center of curvature on the gate wiring 52 side.
  • the variation in the electrical characteristics of the gate electrode 32 (first silicide portion 40 and first polysilicon portion 41) caused by the diffusion of impurities in the second oxide film 73 is suppressed by the first oxide film 72 to which no impurities are added.
  • the variation in the insulating characteristics of the second oxide film 73 caused by the diffusion of impurities in the gate electrode 32 is suppressed by the first oxide film 72 to which no impurities are added.
  • the second oxide film 73 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 and the first oxide film 72 between them.
  • the second oxide film 73 covers the gate wiring 52 in the peripheral region 9, sandwiching the first oxide film 72 between them.
  • the second oxide film 73 includes a first upper wiring coating portion 82 and a second upper wiring coating portion 83.
  • the first upper wiring coating portion 82 covers the first wiring coating portion 77 and the second wiring coating portion 78 of the first oxide film 72.
  • the first upper wiring coating portion 82 covers the peripheral insulating film 51 in a portion located above the first wiring coating portion 77, sandwiching the first wiring coating portion 77.
  • the first upper wiring covering portion 82 extends in a film-like shape in the stacking direction from above the first wiring covering portion 77 along the second wiring covering portion 78, and covers the first wiring sidewall 54 (second wiring sidewall 55) with the second wiring covering portion 78 in between.
  • the first upper wiring covering portion 82 has a portion that covers the second polysilicon portion 61 with the second wiring covering portion 78 in between.
  • the second upper wiring covering portion 83 covers the third wiring covering portion 79 of the first oxide film 72.
  • the second upper wiring covering portion 83 extends horizontally in a film shape from the first upper wiring covering portion 82 along the third wiring covering portion 79, and covers the wiring surface 53 by sandwiching the third wiring covering portion 79.
  • the second upper wiring covering portion 83 covers the entire wiring surface 53 by sandwiching the third wiring covering portion 79 between the first wiring sidewall 54 and the second wiring sidewall 55.
  • the second upper wiring covering portion 83 has a portion covering the second silicide portion 60 with the first oxide film 72 (third wiring covering portion 79) in between, and a portion covering the second polysilicon portion 61 with the first oxide film 72 (third wiring covering portion 79) in between. It is preferable that the second upper wiring covering portion 83 forms an arc corner portion curved in an arc shape together with the first upper wiring covering portion 82 in the portion covering the corner portion of the gate wiring 52.
  • the arc corner portion may have a center of curvature on the gate wiring 52 side.
  • the variation in the electrical characteristics of the gate wiring 52 (second silicide portion 60 and second polysilicon portion 61) caused by the diffusion of impurities in the second oxide film 73 is suppressed by the first oxide film 72, which contains no impurities.
  • the variation in the insulating characteristics of the second oxide film 73 caused by the diffusion of impurities in the gate wiring 52 is suppressed by the first oxide film 72, which contains no impurities.
  • the semiconductor device 1 includes a plurality of source openings 90 formed in the interlayer film 70 in the active region 8.
  • the plurality of source openings 90 are formed in regions to the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2).
  • the plurality of source openings 90 are formed in regions between the plurality of gate electrodes 32, respectively, and penetrate the insulating film 31 and the interlayer film 70.
  • the multiple source openings 90 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73.
  • the multiple source openings 90 each have an opening end defined by an arc corner portion of the interlayer film 70.
  • the multiple source openings 90 each expose a corresponding multiple source region 23, 24 and contact region 25.
  • the multiple source openings 90 are formed at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. That is, the multiple source openings 90 are formed in a stripe shape extending in the second direction Y.
  • the multiple source openings 90 are formed at intervals in the second direction Y from the gate wiring 52. That is, the multiple source openings 90 are formed in a region surrounded by the multiple gate electrodes 32 and the gate wiring 52.
  • a plurality of source openings 90 may be formed in a region between two gate structures 30 adjacent in the first direction X.
  • the plurality of source openings 90 may be formed in a line in the second direction Y with a space therebetween.
  • each source opening 90 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.
  • the source opening 90 may have a width W of 0.1 ⁇ m or more and 3 ⁇ m or less.
  • the width W of the source opening 90 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, 1.75 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.25 ⁇ m or less, 2.25 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 2.75 ⁇ m or less, and 2.75 ⁇ m or more and 3 ⁇ m or less.
  • the width W of the source opening 90 is preferably 0.2 ⁇
  • the source opening 90 may have a depth D of 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the depth D of the source opening 90 may have a value that belongs to at least one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the depth D of the source opening 90 is preferably 0.5 ⁇ m or more and 1 ⁇ m or less.
  • the source opening 90 preferably has an aspect ratio D/W of 0.5 or more and 3 or less.
  • the aspect ratio D/W is defined as the ratio of the depth D of the source opening 90 to the width W of the source opening 90.
  • the aspect ratio D/W may have a value belonging to at least one of the following ranges: 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.
  • the aspect ratio D/W is preferably greater than 1.
  • the source opening 90 preferably has a depth D greater than its width W.
  • the semiconductor device 1 includes a plurality of source recesses 91 formed in the first main surface 3 in the portions exposed from the plurality of source openings 90.
  • the semiconductor device 1 does not necessarily have to have the source recesses 91. Therefore, a configuration that does not have the source recesses 91 may be adopted.
  • the multiple source recesses 91 each have a planar shape that matches the planar shape of the corresponding source opening 90, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple source recesses 91 are formed at intervals from the bottoms of the corresponding body regions 20 toward the first main surface 3, exposing the corresponding multiple source regions 23, 24 and contact regions 25.
  • the multiple source recesses 91 are formed at intervals from the bottoms of the corresponding multiple source regions 23, 24 (contact regions 25) toward the first main surface 3.
  • the semiconductor device 1 includes at least one (in this embodiment, multiple) outer openings 92 formed in the interlayer film 70 in the peripheral region 9.
  • the multiple outer openings 92 are formed in a portion of the interlayer film 70 that covers the termination region 45.
  • the multiple outer openings 92 penetrate the interlayer film 70 and expose the termination region 45.
  • the multiple outer openings 92 are formed in a portion of the interlayer film 70 that covers the overlap region 46 of the termination region 45 and expose the overlap region 46.
  • the outer openings 92 may expose the outer body region 21 instead of or in addition to the termination region 45 (overlapping region 46).
  • the outer openings 92 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73.
  • the outer openings 92 each have an opening end defined by an arc corner portion of the interlayer film 70.
  • the outer openings 92 are spaced apart along the termination region 45 (overlap region 46) (see Figures 4 and 5).
  • the outer openings 92 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the outer openings 92 may be formed in a band shape extending along the termination region 45 (overlap region 46) in a plan view.
  • the semiconductor device 1 may have a single outer opening 92.
  • the single outer opening 92 may be formed in a band shape extending along the termination region 45 (overlap region 46).
  • the single outer opening 92 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view.
  • the single outer opening 92 may be formed in a polygonal ring shape (a square ring in this embodiment) with or without ends, having four sides parallel to the periphery of the first main surface 3.
  • the single outer opening 92 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) following the termination region 45 (overlapping region 46) in a plan view (see FIG. 4).
  • the semiconductor device 1 includes a plurality of outer recesses 93 formed in the first main surface 3 in the portions exposed from the plurality of outer openings 92.
  • the semiconductor device 1 does not necessarily have to have the outer recesses 93. Therefore, a configuration that does not have the outer recesses 93 may be adopted.
  • the multiple outer recesses 93 each have a planar shape that matches the planar shape of the corresponding outer opening 92, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple outer recesses 93 are formed at intervals from the bottom of the termination region 45 (overlap region 46) toward the first main surface 3, and each exposes the termination region 45 (overlap region 46).
  • the outer recess 93 may have a depth approximately equal to the depth of the source recess 91.
  • a single outer recess 93 is formed that matches the planar shape of the single outer opening 92.
  • the semiconductor device 1 includes at least one (in this embodiment, multiple) gate openings 94 formed in the interlayer film 70 in the peripheral region 9.
  • the multiple gate openings 94 are formed in a portion of the interlayer film 70 that covers the gate wiring 52.
  • the multiple gate openings 94 penetrate the interlayer film 70 and expose the wiring surface 53 of the gate wiring 52.
  • the multiple gate openings 94 expose the second silicide portion 60 of the gate wiring 52. More specifically, the multiple gate openings 94 expose the second silicide portion 60 at intervals inward from the second polysilicon portion 61. The multiple gate openings 94 expose only the second silicide portion 60, and do not expose the second polysilicon portion 61. Of course, one or more gate openings 94 that expose the second polysilicon portion 61 may be formed.
  • the multiple gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73.
  • the multiple gate openings 94 each have an opening end defined by an arc corner portion of the interlayer film 70.
  • the multiple gate openings 94 are formed at intervals along the gate wiring 52 (second silicide portion 60) (see Figures 4 and 5).
  • the multiple gate openings 94 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple gate openings 94 may be formed in a strip shape extending along the gate wiring 52 in a plan view.
  • the semiconductor device 1 may have a single gate opening 94.
  • the single gate opening 94 may be formed in a strip shape extending along the gate wiring 52.
  • the single gate opening 94 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.
  • the single gate opening 94 may be formed in a polygonal ring shape (a square ring in this embodiment) with or without ends, having four sides parallel to the periphery of the first main surface 3.
  • the single gate opening 94 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) following the gate wiring 52 (second silicide portion 60) in a plan view (see FIG. 4).
  • the semiconductor device 1 includes a source pad electrode 95 disposed on the interlayer film 70.
  • the source pad electrode 95 is a terminal electrode to which a source potential is applied from the outside.
  • the source pad electrode 95 may also be referred to as a "first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” etc.
  • the source pad electrode 95 is disposed on a portion of the interlayer film 70 that covers the active region 8.
  • the source pad electrode 95 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically isolated from the multiple gate electrodes 32 by the interlayer film 70.
  • the source pad electrode 95 is electrically connected to the multiple body regions 20, the outer body region 21, the multiple source regions 23 and 24, the contact region 25, etc. via the multiple source openings 90.
  • the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98.
  • the first pad portion 96 has a relatively large planar area and forms the main body of the source pad electrode 95.
  • the first pad portion 96 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the fourth side surface 5D relative to the center of the active region 8.
  • the first pad portion 96 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 90.
  • the second pad portion 97 has a planar area less than that of the first pad portion 96, and is pulled out in a strip shape (rectangular shape) from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C.
  • the second pad portion 97 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 90.
  • the third pad portion 98 has a planar area less than that of the first pad portion 96, and is pulled out in a strip shape (rectangular shape) from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 97 in the second direction Y.
  • the third pad portion 98 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 90.
  • the plane area of the third pad portion 98 may be approximately equal to the plane area of the second pad portion 97. Of course, the plane area of the third pad portion 98 may be greater than the plane area of the second pad portion 97, or may be less than the plane area of the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 may be used as a terminal portion for monitoring a current.
  • the source pad electrode 95 does not necessarily have to have both the second pad portion 97 and the third pad portion 98 at the same time.
  • the source pad electrode 95 may have only one of the second pad portion 97 and the third pad portion 98.
  • the source pad electrode 95 may be composed of only the first pad portion 96, and may not have the second pad portion 97 or the third pad portion 98.
  • the source pad electrode 95 includes a first underlying electrode film 100, a plurality of first buried electrodes 101, and a first main electrode film 102.
  • the first underlying electrode film 100 may be referred to as a "source underlying electrode film”
  • the first buried electrodes 101 may be referred to as a “source buried electrode”
  • the first main electrode film 102 may be referred to as a "source main electrode film”.
  • the first underlying electrode film 100 forms the lower layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the interlayer film 70 in the active region 8.
  • the first underlying electrode film 100 collectively covers the region of the interlayer film 70 in which the multiple source openings 90 are formed. In other words, the first underlying electrode film 100 penetrates into the multiple source openings 90 from above the insulating surface 71.
  • the first underlying electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner.
  • the first underlying electrode film 100 defines recesses in each of the multiple source openings 90.
  • the first underlying electrode film 100 may have a portion that partially covers the gate wiring 52 with the interlayer film 70 in between.
  • the first underlying electrode film 100 may be formed spaced inward from the gate wiring 52 in a plan view.
  • the first underlying electrode film 100 has a layered structure including a first electrode film 103 layered on the interlayer film 70, and a second electrode film 104 layered on the first electrode film 103.
  • the first electrode film 103 includes a Ti film
  • the second electrode film 104 includes a TiN film.
  • the first underlying electrode film 100 does not necessarily have to have a layered structure, and may have a single layer structure consisting of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film).
  • the thickness of the first electrode film 103 may be 10 nm or more and 100 nm or less.
  • the thickness of the first electrode film 103 may have a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the thickness of the second electrode film 104 may be 50 nm or more and 200 nm or less.
  • the thickness of the second electrode film 104 may have a value belonging to at least one of the following ranges: 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.
  • the thickness of the second electrode film 104 is preferably greater than the thickness of the first electrode film 103.
  • the first electrode film 103 collectively covers the region of the interlayer film 70 in which the multiple source openings 90 are formed, and extends into the multiple source openings 90 from above the insulating surface 71.
  • the first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner.
  • the first electrode film 103 directly covers the insulating surface 71.
  • the first electrode film 103 directly covers the second oxide film 73 on the insulating surface 71.
  • the first oxide film 72 faces the multiple gate electrodes 32 across the interlayer film 70 in the portion covering the insulating surface 71.
  • the first electrode film 103 faces the first silicide portion 40 and the first polysilicon portion 41 of each gate electrode 32 across the interlayer film 70.
  • the first electrode film 103 covers the arc corner of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arc corner of the interlayer film 70 (second oxide film 73), and extends into the source opening 90.
  • the first electrode film 103 has a portion that extends in an arc shape at the arc corner. This improves the film-forming property of the first electrode film 103 on the interlayer film 70 (the wall surface of the source opening 90).
  • the first electrode film 103 extends along the wall surface of the source opening 90, and covers the insulating film 31, the first oxide film 72, and the second oxide film 73.
  • the first electrode film 103 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 across the interlayer film 70. In other words, the first electrode film 103 faces the first polysilicon portion 41 of the gate electrode 32 across the first oxide film 72 and the second oxide film 73.
  • the first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each source opening 90, and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion that covers the source recess 91 in a film-like manner at the bottom of each source opening 90, and is electrically connected to the multiple source regions 23, 24 and the contact region 25.
  • the first electrode film 103 may cover the source recess 91 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the source recess 91.
  • the first electrode film 103 may have a portion located on the bottom side of the source recess 91 with respect to the height position of the first main surface 3, and a portion located on the insulating film 31 side with respect to the height position of the first main surface 3.
  • the second electrode film 104 covers the area of the interlayer film 70 on the first electrode film 103 where the multiple source openings 90 are formed.
  • the second electrode film 104 has a portion that covers the insulating surface 71 of the interlayer film 70 with the first electrode film 103 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 with the first electrode film 103 in a film-like manner.
  • the second electrode film 104 faces the multiple gate electrodes 32 across the first electrode film 103 and the interlayer film 70 in the portion covering the insulating surface 71. In other words, the second electrode film 104 faces the first silicide portion 40 and the first polysilicon portion 41 of each gate electrode 32 across the first electrode film 103 and the interlayer film 70.
  • the second electrode film 104 covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the source opening 90.
  • the second electrode film 104 has a portion that extends in an arc shape at the arc corners of the interlayer film 70. This improves the film-forming properties of the second electrode film 104 on the interlayer film 70 (the wall surface of the source opening 90).
  • the second electrode film 104 extends along the wall surface of the source opening 90, and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 in between.
  • the second electrode film 104 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 with the first electrode film 103 and the interlayer film 70 in between.
  • the second electrode film 104 faces the first polysilicon portion 41 of the gate electrode 32 with the first oxide film 72, the second oxide film 73, and the first electrode film 103 in between.
  • the second electrode film 104 has a portion that covers the source recess 91 in a film-like manner at the bottom of each source opening 90, sandwiching the first electrode film 103 therebetween, and is electrically connected to the multiple source regions 23, 24 and the contact region 25 via the first electrode film 103.
  • the second electrode film 104 may have a portion that is located within the source recess 91.
  • the entire second electrode film 104 is located above the source recess 91.
  • the multiple first buried electrodes 101 form a middle layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and are buried in the multiple source openings 90, respectively.
  • the first buried electrodes 101 include a conductive material different from the conductive material of the first base electrode film 100.
  • the first buried electrodes 101 include at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy. In this embodiment, the first buried electrodes 101 include tungsten.
  • the multiple first buried electrodes 101 are buried in a one-to-one correspondence with the multiple source openings 90 via a single first base electrode film 100.
  • the multiple first buried electrodes 101 are electrically connected to the first main surface 3 (chip 2) within the multiple source openings 90.
  • the first buried electrode 101 is electrically connected to the multiple source regions 23, 24 and contact region 25 via the first base electrode film 100.
  • the configuration of one first buried electrode 101 is described below.
  • the first buried electrode 101 has a first buried electrode surface 105 exposed from the source opening 90, exposing the insulating surface 71.
  • the first buried electrode surface 105 may be referred to as a "source buried electrode film.”
  • the first buried electrode 101 is buried in the source opening 90 at a distance from the insulating surface 71 toward the first principal surface 3, exposing a portion of the first base electrode film 100 (second electrode film 104) that covers the insulating surface 71. In other words, the first buried electrode surface 105 is located closer to the first principal surface 3 than the insulating surface 71.
  • the first buried electrode 101 does not have a portion that faces the electrode surface 33 of the gate electrode 32 across the interlayer film 70 in the stacking direction (vertical direction Z). In other words, the first buried electrode 101 does not face the first silicide portion 40 and the first polysilicon portion 41 across the interlayer film 70 in the stacking direction (vertical direction Z).
  • the first buried electrode 101 covers the first oxide film 72 and the second oxide film 73 with the first base electrode film 100 sandwiched therebetween.
  • the first buried electrode 101 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 in the horizontal direction. In other words, the first buried electrode 101 faces the first polysilicon portion 41 in the horizontal direction.
  • the first buried electrode 101 may have a portion located within the source recess 91.
  • the entire first buried electrode 101 is located above the source recess 91.
  • the first buried electrode surface 105 of the first buried electrode 101 is located closer to the insulating surface 71 than the height position of the first oxide film 72. In this embodiment, the first buried electrode surface 105 is located above the electrode surface 33 of the gate electrode 32.
  • the first buried electrode surface 105 has a recess 106 in the center that is recessed toward the first main surface 3 (chip 2).
  • the bottom of the recess 106 is located on the insulating surface 71 side relative to the height position of the electrode surface 33.
  • the entire first buried electrode surface 105 is located above the electrode surface 33.
  • the first buried electrode surface 105 has a portion that covers the arc corner portion of the interlayer film 70 with the first base electrode film 100 in between.
  • the first main electrode film 102 forms the upper layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the first underlying electrode film 100 and the multiple first buried electrodes 101 in a film-like manner.
  • the first main electrode film 102 contains a conductive material different from the conductive material of the first underlying electrode film 100 and the conductive material of the first buried electrodes 101.
  • the first main electrode film 102 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first underlying electrode film 100.
  • the first main electrode film 102 has a thickness greater than the thickness of the first buried electrode 101.
  • the thickness of the first main electrode film 102 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the first main electrode film 102 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first main electrode film 102 is mechanically and electrically connected to the first underlying electrode film 100 in the portion covering the insulating surface 71.
  • the first main electrode film 102 faces the multiple gate electrodes 32 with the first underlying electrode film 100 and the interlayer film 70 in between.
  • the first main electrode film 102 faces the first silicide portion 40 and the first polysilicon portion 41 of each gate electrode 32 with the first underlying electrode film 100 and the interlayer film 70 in between.
  • the first main electrode film 102 is mechanically and electrically connected to the multiple first buried electrodes 101 in the portion covering the multiple source openings 90.
  • the first main electrode film 102 is electrically connected to the multiple body regions 20, the outer body region 21, the multiple source regions 23, 24, the contact region 25, etc. via both the first base electrode film 100 and the multiple first buried electrodes 101.
  • the first main electrode film 102 is directly connected to the first buried electrode surface 105 of the first buried electrode 101.
  • the first main electrode film 102 has a portion that is connected to the first buried electrode surface 105 at a height position on the first main surface 3 side relative to the height position of the insulating surface 71.
  • the first main electrode film 102 is connected to the first buried electrode surface 105 above the height position of the first oxide film 72.
  • the first main electrode film 102 is connected to the first buried electrode surface 105 above the electrode surface 33 of the gate electrode 32. In other words, the first main electrode film 102 does not have a portion that faces the gate electrode 32 in the horizontal direction.
  • the first main electrode film 102 has a portion that covers the recess 106 of the first buried electrode surface 105.
  • the first main electrode film 102 may have a portion that covers the arc corner portion of the interlayer film 70 with the first base electrode film 100 in between.
  • the film formation of the first main electrode film 102 for the multiple source openings 90 is improved by the multiple first buried electrodes 101. This ensures an appropriate current path between the first main surface 3 and the first main electrode film 102. This configuration is effective in suppressing film formation defects caused by the multiple source openings 90 and reducing wiring resistance.
  • the source pad electrode 95 may have the layout shown in Figures 12A to 12D.
  • Figures 12A to 12D are enlarged cross-sectional views showing source pad electrodes 95 according to second, third, fourth and fifth examples.
  • the source pad electrode 95 does not necessarily have to have any one of the configurations of the first to fifth examples (FIG. 7, FIG. 12A to FIG. 12D).
  • the source pad electrode 95 may simultaneously include features of at least two of the configurations of the first to fifth examples.
  • the source pad electrodes 95 of the first to fifth examples are all forms that can be obtained by adjusting process conditions during the manufacturing process.
  • FIGS. 10A to 10C show an example in which the source pad electrodes 95 according to the first to fifth examples are formed together with the gate electrode 32 according to the first example.
  • the source pad electrodes 95 according to the first to fifth examples can be formed together with at least one of the gate electrodes 32 according to the first to fourth examples (FIG. 7, FIGS. 10A to 10C).
  • the source pad electrode 95 may include a plurality of first buried electrodes 101 that extend in a vertically elongated columnar shape in a cross-sectional view. That is, the plurality of first buried electrodes 101 may be buried in a plurality of vertically elongated source openings 90 each having an aspect ratio D/W greater than 1. In this case, each of the first buried electrodes 101 has an aspect ratio D/W greater than 1 in a cross-sectional view, corresponding to the aspect ratio D/W of the corresponding source opening 90.
  • the aspect ratio D/W of the vertically elongated first buried electrode 101 (source opening 90) is preferably greater than 1 and less than or equal to 3.
  • the aspect ratio D/W may have a value that falls within at least one of the following ranges: greater than 1 and less than or equal to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, and 2.75 to 3.
  • the aspect ratio D/W is preferably less than or equal to 2.
  • the first main electrode film 102 is mechanically and electrically connected to a plurality of first buried electrodes 101 extending in a vertically elongated columnar shape.
  • a plurality of gate electrodes 32 are arranged at a narrow pitch by a plurality of first buried electrodes 101 (a plurality of source openings 90) extending in a vertically elongated columnar shape.
  • the semiconductor device 1 does not have a sidewall structure (spacer) on the sides of the gate electrodes 32, the narrow pitch of the plurality of gate electrodes 32 each having a first silicide portion 40 is not hindered by the sidewall structure (spacer).
  • the source pad electrode 95 may include a plurality of first buried electrodes 101 having portions positioned closer to the first main surface 3 than the electrode surface 33 of the gate electrode 32.
  • the multiple first buried electrodes 101 each have a portion on the first buried electrode surface 105 that is located closer to the first principal surface 3 than the electrode surface 33, and a portion that is located closer to the insulating surface 71 than the electrode surface 33.
  • the bottom of the recess 106 is located closer to the first principal surface 3 than the electrode surface 33, and the portion outside the recess 106 is located closer to the insulating surface 71 than the electrode surface 33.
  • the first main electrode film 102 has a portion connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the first main surface 3 than the electrode surface 33, and a portion connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the insulating surface 71 than the electrode surface 33.
  • the first main electrode film 102 is covered by the interlayer film 70 across a portion of the first base electrode film 100 that covers the wall surface of the source opening 90, and has a portion that faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 in the horizontal direction.
  • the first main electrode film 102 has a portion that faces the first polysilicon portion 41 in the horizontal direction.
  • the source pad electrode 95 may include a plurality of first buried electrodes 101 positioned on the first main surface 3 side relative to the height position of the electrode surface 33 of the gate electrode 32. In other words, the entire first buried electrode surface 105 may be positioned on the first main surface 3 side relative to the electrode surface 33.
  • At least a part or all of the first buried electrode surface 105 may be located closer to the insulating surface 71 than the first oxide film 72.
  • the bottom of the recess 106 may be located closer to the insulating surface 71 than the first oxide film 72.
  • the bottom of the recess 106 may be located closer to the first main surface 3 than the first oxide film 72, and the portion outside the recess 106 may be located closer to the insulating surface 71 than the first oxide film 72.
  • a configuration in which the entire first buried electrode 101 is located closer to the first main surface 3 than the first oxide film 72 may be adopted.
  • the first main electrode film 102 is connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the first main surface 3 than the electrode surface 33, and does not have a portion connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the insulating surface 71 than the electrode surface 33.
  • the first main electrode film 102 is connected to the first buried electrode surface 105 (first buried electrode 101) in a region above the first oxide film 72.
  • the first main electrode film 102 has a portion that faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 in the horizontal direction. In other words, the first main electrode film 102 faces the first polysilicon portion 41 in the horizontal direction.
  • the first main electrode film 102 covers the interlayer film 70, sandwiching the portion of the first base electrode film 100 that covers the wall surface of the source opening 90.
  • the first main electrode film 102 may be connected to the first buried electrode surface 105 (first buried electrode 101) in a region closer to the first main surface 3 than the first oxide film 72.
  • the source pad electrode 95 may have a plurality of first buried electrodes 101 that are drawn out onto the insulating surface 71 from a plurality of source openings 90 and cover the insulating surface 71.
  • the plurality of first buried electrodes 101 cover the first underlying electrode film 100 on the insulating surface 71, and have a portion that covers the insulating surface 71 with the first underlying electrode film 100 sandwiched therebetween.
  • each of the multiple first buried electrodes 101 has a first buried electrode surface 105 exposed from the multiple source openings 90 above the insulating surface 71.
  • the multiple first buried electrodes 101 have a portion that faces the gate electrode 32 in the stacking direction (vertical direction Z) with the first base electrode film 100 and interlayer film 70 sandwiched therebetween.
  • the multiple first base electrode films 100 have a portion that faces the first silicide portion 40 and first polysilicon portion 41 of the gate electrode 32 in the stacking direction (vertical direction Z).
  • the multiple first buried electrodes 101 are integrated on the insulating surface 71 to form one source intermediate electrode 107.
  • the source intermediate electrode 107 (multiple first buried electrodes 101) covers the entire area of the first base electrode film 100.
  • the electrode surface (first buried electrode surface 105) of the source intermediate electrode 107 is located above the insulating surface 71.
  • the first main electrode film 102 is mechanically and electrically connected to the first buried electrode surfaces 105 of the multiple first buried electrodes 101 (source intermediate electrodes 107) above the insulating surface 71.
  • the first main electrode film 102 has a portion that faces the insulating surface 71, sandwiching the multiple first buried electrodes 101 (source intermediate electrodes 107).
  • the first main electrode film 102 does not have a mechanical connection to the first base electrode film 100.
  • the semiconductor device 1 includes a plurality of first source silicide portions 108 formed on the surface of the first main surface 3 in the portions exposed from the plurality of source openings 90.
  • the plurality of first source silicide portions 108 are formed in a film shape along the wall surfaces (side walls and bottom walls) of the plurality of source recesses 91, and are mechanically and electrically connected to the first underlying electrode film 100.
  • the multiple first source silicide portions 108 are formed in the surface layer portions of the multiple body regions 20, and the multiple first buried electrodes 101 are electrically connected to the multiple body regions 20 via the first base electrode film 100.
  • the first source silicide portion 108 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide.
  • the first source silicide portion 108 is preferably made of Ti silicide, Ni silicide, or Co silicide.
  • the semiconductor device 1 includes a source finger electrode 110 that is extended from the source pad electrode 95 onto the peripheral region 9.
  • the source finger electrode 110 transmits the source potential applied to the source pad electrode 95 to the peripheral region 9.
  • the source finger electrode 110 is extended from the portion of the source pad electrode 95 (first pad portion 96) on the fourth side surface 5D side onto the portion of the interlayer film 70 that covers the peripheral region 9.
  • the source finger electrodes 110 are extended up to above the termination region 45 and are electrically connected to the termination region 45 via a plurality of outer openings 92. Specifically, the source finger electrodes 110 are electrically connected to the overlap region 46 of the termination region 45 via a plurality of outer openings 92.
  • the source finger electrodes 110 extend in a strip shape along the termination region 45 (overlap region 46).
  • the source finger electrodes 110 have a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view.
  • the source finger electrode 110 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95.
  • the source finger electrode 110 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the source finger electrode 110 like the source pad electrode 95, includes a first underlying electrode film 100, a plurality of first buried electrodes 101, and a first main electrode film 102.
  • the first underlying electrode film 100 forms the lower layer of the source finger electrode 110, and covers the interlayer film 70 in the peripheral region 9.
  • the first underlying electrode film 100 collectively covers the area of the interlayer film 70 where the multiple outer openings 92 are formed. In other words, the first underlying electrode film 100 extends into the multiple outer openings 92 from above the insulating surface 71.
  • the first underlying electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner.
  • the first underlying electrode film 100 defines recesses within each of the multiple outer openings 92.
  • the first base electrode film 100 has a layered structure including a first electrode film 103 and a second electrode film 104, similar to the source pad electrode 95.
  • the first electrode film 103 collectively covers the area of the interlayer film 70 in which the multiple outer openings 92 are formed, and penetrates into the multiple outer openings 92 from above the insulating surface 71.
  • the first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner.
  • the first electrode film 103 covers the arc corner of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arc corner of the interlayer film 70 (second oxide film 73), and enters the outer opening 92.
  • the first electrode film 103 has a portion that extends in an arc shape at the arc corner. This improves the film-forming property of the first electrode film 103 on the interlayer film 70 (wall surface of the outer opening 92).
  • the first electrode film 103 extends along the wall surface of the outer opening 92, and covers the peripheral insulating film 51, the first oxide film 72, and the second oxide film 73.
  • the first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 103 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the termination region 45 (overlap region 46) within the outer recess 93.
  • the first electrode film 103 may cover the outer recess 93 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the outer recess 93.
  • the first electrode film 103 may have a portion located on the bottom side of the outer recess 93 with respect to the height position of the first main surface 3, and a portion located on the peripheral insulating film 51 side with respect to the height position of the first main surface 3.
  • the second electrode film 104 is disposed on the first electrode film 103 and covers the area of the interlayer film 70 in which the multiple outer openings 92 are formed.
  • the second electrode film 104 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner with the first electrode film 103 in between, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner with the first electrode film 103 in between.
  • the second electrode film 104 covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and penetrates into the outer opening 92.
  • the second electrode film 104 has a portion that extends in an arc shape at the arc corners of the interlayer film 70 (second oxide film 73).
  • the second electrode film 104 extends along the wall surface of the outer opening 92, and covers the peripheral insulating film 51, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 in between.
  • the second electrode film 104 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, sandwiching the first electrode film 103 therebetween, and is electrically connected to the termination region 45 (overlap region 46) via the first electrode film 103.
  • the second electrode film 104 may have a portion located within the outer recess 93.
  • the entire second electrode film 104 is located above the outer recess 93.
  • the multiple first buried electrodes 101 form a middle layer of the source finger electrode 110 and are buried in the multiple outer openings 92, respectively.
  • the multiple first buried electrodes 101 are buried in the multiple outer openings 92 in a one-to-one correspondence via a single first base electrode film 100.
  • the multiple first buried electrodes 101 are electrically connected to the termination region 45 (overlap region 46) via the first base electrode film 100.
  • the first buried electrode 101 has a first buried electrode surface 105 exposed from the outer opening 92, exposing the insulating surface 71. Specifically, the first buried electrode 101 is buried in the outer opening 92 at a distance from the insulating surface 71 toward the first principal surface 3, exposing a portion of the first base electrode film 100 (second electrode film 104) that covers the insulating surface 71. In other words, the first buried electrode surface 105 is located closer to the first principal surface 3 than the insulating surface 71.
  • the first buried electrode 101 covers the first oxide film 72 and the second oxide film 73 with the first base electrode film 100 in between.
  • the first buried electrode surface 105 is located closer to the insulating surface 71 than the height position of the first oxide film 72 in the outer opening 92.
  • the first buried electrode 101 has a portion that covers the arc corner portion of the interlayer film 70 with the first base electrode film 100 in between.
  • the first buried electrode 101 may be buried at a distance from the arc corner of the interlayer film 70 toward the outer insulating film 51, with the entire arc corner exposed.
  • the first buried electrode surface 105 may be located closer to the insulating surface 71 than the height position of the first oxide film 72.
  • the first buried electrode surface 105 may be located closer to the outer insulating film 51 than the height position of the first oxide film 72.
  • the first buried electrode 101 may have a portion located within the outer recess 93.
  • the entire first buried electrode 101 is located above the outer recess 93.
  • the first main electrode film 102 forms an upper layer of the source finger electrode 110, and covers the first underlying electrode film 100 and the multiple first buried electrodes 101 in a film-like manner.
  • the first main electrode film 102 is mechanically and electrically connected to the first underlying electrode film 100 in the portion covering the insulating surface 71, and is mechanically and electrically connected to the multiple first buried electrodes 101 in the portion covering the multiple outer openings 92.
  • the first main electrode film 102 is electrically connected to the termination region 45 (overlap region 46) via the first underlying electrode film 100 and the multiple first buried electrodes 101.
  • the first main electrode film 102 is also directly connected to the first buried electrode surface 105 of the first buried electrode 101 on the source finger electrode 110 side.
  • the first main electrode film 102 has a portion that is connected to the first buried electrode surface 105 at a height position on the first main surface 3 side relative to the height position of the insulating surface 71.
  • the first main electrode film 102 is connected to the first buried electrode surface 105 above the height position of the first oxide film 72.
  • the first main electrode film 102 has a portion that covers the depression 106 of the first buried electrode surface 105.
  • the first main electrode film 102 may have a portion that covers the arc corner portion of the interlayer film 70 with the first base electrode film 100 in between.
  • the film formation of the first main electrode film 102 for the multiple outer openings 92 is improved by the multiple first buried electrodes 101. This ensures an appropriate current path between the termination region 45 (overlap region 46) and the first main electrode film 102. This configuration is effective in suppressing film formation defects caused by the multiple outer openings 92 and reducing wiring resistance.
  • connection form of the first main electrode film 102 of the source finger electrode 110 to the first buried electrode 101 of the source finger electrode 110 is similar to the connection form of the first main electrode film 102 of the source pad electrode 95 to the first buried electrode 101 of the source pad electrode 95.
  • the semiconductor device 1 includes a plurality of second source silicide portions 111 formed on the surface of the first main surface 3 in the portions exposed from the plurality of outer openings 92.
  • the plurality of second source silicide portions 111 are formed in a film shape along the wall surfaces (side walls and bottom walls) of the plurality of outer recesses 93, and are mechanically and electrically connected to the first base electrode film 100.
  • the multiple second source silicide portions 111 are formed in the surface layer of the termination region 45 (overlap region 46), and the multiple first buried electrodes 101 are electrically connected to the termination region 45 (overlap region 46) via the first base electrode film 100.
  • the second source silicide portion 111 may include at least one of Ti silicide, Ni silicide, Co silicide, Mo silicide, and W silicide.
  • the second source silicide portion 111 is preferably made of Ti silicide, Ni silicide, or Co silicide. It is particularly preferable that the second source silicide portion 111 is made of the same type of silicide as the first source silicide portion 108.
  • the semiconductor device 1 includes a gate finger electrode 115 selectively routed over the interlayer film 70.
  • the gate finger electrode 115 transmits a gate potential to the gate wiring 52.
  • the gate finger electrode 115 is routed over a portion of the interlayer film 70 that covers the gate wiring 52 (i.e., over the outer peripheral region 9), and is electrically connected to the gate wiring 52 through a plurality of gate openings 94.
  • the gate finger electrode 115 is disposed in the region between the source pad electrode 95 and the source finger electrode 110 and spaced apart from the source pad electrode 95 and the source finger electrode 110.
  • the gate finger electrode 115 is disposed on the gate wiring 52 and extends in a strip along the gate wiring 52.
  • the gate finger electrode 115 has a portion that extends in a strip in the first direction X and a portion that extends in a strip in the second direction Y in a plan view.
  • the gate finger electrode 115 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95.
  • the gate finger electrode 115 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the gate finger electrode 115 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 110 passes.
  • the gate finger electrode 115 includes a second underlying electrode film 120, at least one (in this embodiment, multiple) second buried electrodes 121, and a second main electrode film 122.
  • the second underlying electrode film 120 may be referred to as the "gate underlying electrode film”
  • the second buried electrode 121 may be referred to as the “gate buried electrode”
  • the second main electrode film 122 may be referred to as the "gate main electrode film”.
  • the second underlying electrode film 120 forms the lower layer of the gate finger electrode 115 and covers the interlayer film 70 in the peripheral region 9.
  • the second underlying electrode film 120 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed.
  • the second base electrode film 120 extends from above the insulating surface 71 into the multiple gate openings 94.
  • the second base electrode film 120 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner.
  • the second base electrode film 120 defines multiple recesses within each of the multiple gate openings 94.
  • the second base electrode film 120 has a layered structure including a first electrode film 123 layered on the interlayer film 70, and a second electrode film 124 layered on the first electrode film 123. It is preferable that the first electrode film 123 contains the same type of conductive material as the first electrode film 103 on the source side, and the second electrode film 124 contains the same type of conductive material as the second electrode film 104 on the source side. In this embodiment, the first electrode film 123 contains a Ti film, and the second electrode film 124 contains a TiN film.
  • the second base electrode film 120 does not necessarily have to have a laminated structure, and may have a single layer structure consisting of either the first electrode film 123 (Ti film) or the second electrode film 124 (TiN film).
  • the first electrode film 123 may have a thickness approximately equal to the thickness of the first electrode film 103 on the source side.
  • the second electrode film 124 may have a thickness approximately equal to the thickness of the second electrode film 104 on the source side.
  • the first electrode film 123 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed, and penetrates into the multiple gate openings 94 from above the insulating surface 71.
  • the first electrode film 123 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner.
  • the first electrode film 123 covers the arc corner of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arc corner of the interlayer film 70 (second oxide film 73), and enters the gate opening 94.
  • the first electrode film 123 has a portion that extends in an arc shape at the arc corner. This improves the film-forming ability of the first electrode film 123 on the interlayer film 70 (wall surface of the gate opening 94).
  • the first electrode film 123 extends along the wall surface of the gate opening 94, and covers the first oxide film 72 and the second oxide film 73.
  • the first electrode film 123 covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, and is electrically connected to the gate wiring 52. Specifically, the first electrode film 123 has a portion that covers the second silicide portion 60 of the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, and is mechanically and electrically connected to the second silicide portion 60.
  • the first electrode film 123 is mechanically connected to the second silicide portion 60 with a gap inward from the second polysilicon portion 61. In other words, the first electrode film 123 is mechanically connected only to the second silicide portion 60, and is not mechanically connected to the second polysilicon portion 61. The first electrode film 123 is electrically connected to the second polysilicon portion 61 via the second silicide portion 60. Of course, the first electrode film 123 (second base electrode film 120) may have a portion connected to the second polysilicon portion 61.
  • the second electrode film 124 covers the area of the interlayer film 70 on the first electrode film 123 where the multiple gate openings 94 are formed.
  • the second electrode film 124 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner with the first electrode film 123 in between, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner with the first electrode film 123 in between.
  • the second electrode film 124 covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and penetrates into the gate opening 94.
  • the second electrode film 124 has a portion that extends in an arc shape at the arc corners of the interlayer film 70 (second oxide film 73). This improves the film-forming properties of the second electrode film 124 on the interlayer film 70 (wall surface of the gate opening 94).
  • the second electrode film 124 extends along the wall surface of the gate opening 94 and covers the first oxide film 72 and the second oxide film 73 with the first electrode film 123 in between.
  • the second electrode film 124 has a portion that covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, sandwiching the first electrode film 123 therebetween, and is electrically connected to the gate wiring 52 via the first electrode film 123.
  • the second electrode film 124 has a portion that covers the second silicide portion 60 of the gate wiring 52 in a film-like manner, sandwiching the first electrode film 123 therebetween, and is electrically connected to the second silicide portion 60 via the first electrode film 123.
  • the second electrode film 124 is located on the second silicide portion 60 with a space inward from the second polysilicon portion 61. In other words, the second electrode film 124 faces only the second silicide portion 60 across the first electrode film 123, and does not face the second polysilicon portion 61.
  • the second electrode film 124 is electrically connected to the second polysilicon portion 61 via the first electrode film 123 and the second silicide portion 60.
  • the second electrode film 124 may have a portion that faces the second polysilicon portion 61 across the first electrode film 123.
  • the multiple second buried electrodes 121 form a middle layer of the gate finger electrode 115 and are buried in the multiple gate openings 94, respectively.
  • the second buried electrodes 121 include a conductive material different from the conductive material of the second base electrode film 120.
  • the second buried electrodes 121 include at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy.
  • the second buried electrodes 121 preferably include the same type of conductive material as the conductive material of the first buried electrodes 101. In this embodiment, the second buried electrodes 121 include tungsten.
  • the multiple second buried electrodes 121 are buried in one-to-one correspondence with the multiple gate openings 94 via a single second base electrode film 120.
  • the multiple second buried electrodes 121 are electrically connected to the second silicide portion 60 of the gate wiring 52 via the second base electrode film 120 within the multiple gate openings 94.
  • the multiple second buried electrodes 121 are positioned above the second silicide portion 60 with a space inward from the second polysilicon portion 61. In other words, the multiple second buried electrodes 121 face only the second silicide portion 60 across the first electrode film 123, and do not face the second polysilicon portion 61.
  • the multiple second buried electrodes 121 are electrically connected to the second polysilicon portion 61 via the second base electrode film 120.
  • the multiple second buried electrodes 121 may have a portion that faces the second polysilicon portion 61 across the second base electrode film 120.
  • the second buried electrode 121 has a second buried electrode surface 125 exposed from the gate opening 94, exposing the insulating surface 71.
  • the second buried electrode surface 125 may be referred to as a "gate buried electrode surface.”
  • the second buried electrode 121 is buried in the gate opening 94 at a distance from the insulating surface 71 toward the first principal surface 3, exposing a portion of the second base electrode film 120 (second electrode film 124) that covers the insulating surface 71. In other words, the second buried electrode surface 125 is located closer to the first principal surface 3 than the insulating surface 71.
  • the second buried electrode 121 covers the first oxide film 72 and the second oxide film 73 with the second base electrode film 120 in between.
  • the second buried electrode surface 125 is positioned closer to the insulating surface 71 than the height position of the first oxide film 72.
  • the second buried electrode 121 has a portion that covers the arc corner portion of the interlayer film 70 with the second base electrode film 120 in between.
  • the second buried electrode 121 may be buried at a distance from the arc corner of the interlayer film 70 toward the gate wiring 52, with the entire arc corner exposed.
  • the second buried electrode surface 125 may be located closer to the insulating surface 71 than the height position of the first oxide film 72.
  • the second buried electrode surface 125 may be located closer to the gate wiring 52 than the height position of the first oxide film 72.
  • the second main electrode film 122 forms an upper layer of the gate finger electrode 115, and covers the second base electrode film 120 and the multiple second buried electrodes 121 in a film-like manner.
  • the second main electrode film 122 contains a conductive material different from the conductive material of the second base electrode film 120 and the conductive material of the second buried electrodes 121.
  • the second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the second main electrode film 122 preferably includes the same type of conductive material as the conductive material of the first main electrode film 102.
  • the second main electrode film 122 may have a thickness approximately equal to that of the first main electrode film 102.
  • the second main electrode film 122 is mechanically and electrically connected to the second base electrode film 120 in the portion covering the insulating surface 71, and is mechanically and electrically connected to the multiple second buried electrodes 121 in the portion covering the multiple gate openings 94. As a result, the second main electrode film 122 is electrically connected to the second silicide portion 60 via the second base electrode film 120 and the multiple second buried electrodes 121.
  • the second main electrode film 122 has a portion connected to the second buried electrode 121 at a height position on the first main surface 3 side with respect to the height position of the insulating surface 71.
  • the second main electrode film 122 is connected to the second buried electrode surface 125 above the height position of the first oxide film 72.
  • the second main electrode film 122 has a portion that covers the arc corner portion of the interlayer film 70 with the second base electrode film 120 in between.
  • the second main electrode film 122 may be connected to the second buried electrode 121 in a region below the first oxide film 72.
  • the film formation of the second main electrode film 122 for the multiple gate openings 94 is improved by the multiple second buried electrodes 121. This ensures an appropriate current path between the gate wiring 52 (second silicide portion 60) and the second main electrode film 122. This configuration is effective in suppressing film formation defects caused by the multiple gate openings 94 and reducing wiring resistance.
  • the semiconductor device 1 includes a gate pad electrode 130 disposed on the interlayer film 70.
  • the gate pad electrode 130 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate pad electrode 130 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the gate pad electrode 130 is disposed in a region between the source pad electrode 95 and the source finger electrode 110 and spaced apart from the source pad electrode 95 and the source finger electrode 110.
  • the gate pad electrode 130 is disposed in a region on the third side surface 5C side relative to the first pad portion 96, and is sandwiched between the second pad portion 97 and the third pad portion 98. In other words, the gate pad electrode 130 faces the first pad portion 96 in the first direction X, and faces the second pad portion 97 and the third pad portion 98 in the second direction Y.
  • the gate pad electrode 130 is formed in a polygonal shape (a square shape in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate pad electrode 130 has a planar area less than that of the source pad electrode 95 (first pad portion 96).
  • the gate pad electrode 130 may have a planar area less than that of the second pad portion 97 (third pad portion 98).
  • the gate pad electrode 130 is disposed on the portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 115.
  • the gate pad electrode 130 may cover multiple gate electrodes 32 with the interlayer film 70 in between, or may cover the gate wiring 52 with the interlayer film 70 in between.
  • the gate pad electrode 130 like the gate finger electrode 115, includes a second base electrode film 120 and a second main electrode film 122.
  • the second base electrode film 120 forms the lower layer of the gate pad electrode 130 and covers the interlayer film 70 in a film-like manner.
  • the second base electrode film 120 like the gate finger electrode 115, has a layered structure including a first electrode film 123 and a second electrode film 124.
  • the first electrode film 123 covers the interlayer film 70 in a film-like manner
  • the second electrode film 124 covers the first electrode film 123 in a film-like manner.
  • the second main electrode film 122 forms the upper layer of the gate pad electrode 130, and covers the second base electrode film 120 in a film-like manner.
  • the gate pad electrode 130 may have a plurality of second buried electrodes 121, similar to the gate finger electrode 115.
  • the gate pad electrode 130 may be electrically connected to the gate wiring 52 (second silicide portion 60) via the plurality of second buried electrodes 121, similar to the gate finger electrode 115.
  • the gate pad electrode 130 may be electrically connected to the multiple gate electrodes 32 (first silicide portion 40) via multiple second buried electrodes 121.
  • the gate pad electrode 130 does not have to have multiple second buried electrodes 121.
  • the gate pad electrode 130 does not have to have an electrical connection to the multiple gate electrodes 32 and an electrical connection to the gate wiring 52 in the area directly below.
  • the gate potential applied to the gate pad electrode 130 is applied to the second silicide portion 60 of the gate wiring 52 via the gate finger electrode 115.
  • the gate potential is transmitted from the second silicide portion 60 to the first silicide portions 40 of the multiple gate electrodes 32 via a wiring path (current path) along the gate wiring 52.
  • the multiple gate electrodes 32 are turned on, and the on/off of the multiple channel regions 26, 27 is controlled.
  • the wiring resistance (gate resistance) caused by the polysilicon of the gate electrode 32 is reduced by the first silicide portion 40.
  • the wiring resistance (gate resistance) caused by the polysilicon of the gate wiring 52 is reduced by the second silicide portion 60.
  • the semiconductor device 1 includes a drain pad electrode 140 covering the second main surface 4.
  • the drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain pad electrode 140 may also be referred to as a "third pad electrode,” a "third main surface electrode,” a “third terminal electrode,” etc.
  • the drain pad electrode 140 is electrically connected to the second semiconductor region 7.
  • the drain pad electrode 140 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D).
  • the drain pad electrode 140 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.
  • the breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • the semiconductor device 1 includes the chip 2, the gate electrode 32, the first silicide portion 40, and the first polysilicon portion 41.
  • the chip 2 has a first main surface 3.
  • the gate electrode 32 is disposed on the first main surface 3.
  • the gate electrode 32 includes polysilicon and has an electrode surface 33.
  • the first silicide portion 40 is partially formed on the surface portion of the electrode surface 33.
  • the first polysilicon portion 41 is formed on the surface portion of the electrode surface 33 in a portion other than the first silicide portion 40. With this configuration, the wiring resistance (gate resistance) of the gate electrode 32 is reduced by the first silicide portion 40.
  • the gate electrode 32 has a first sidewall 34 and a second sidewall 35.
  • the first silicide portion 40 is preferably formed at a distance inward from at least one of the first sidewall 34 and the second sidewall 35.
  • the first polysilicon portion 41 is preferably exposed from at least one of the first sidewall 34 and the second sidewall 35.
  • the first silicide portion 40 is not removed from at least one of the first sidewall 34 and the second sidewall 35 during the manufacturing process of the gate electrode 32 (polysilicon etching process). This suppresses metal contamination (metal particle contamination) of other structures on the first main surface 3 and metal contamination (metal particle contamination) of the manufacturing equipment caused by etching the first silicide portion 40.
  • the configuration of the semiconductor device 1 is effective in suppressing metal contamination in the regions to the sides of the gate electrodes 32 (relatively narrow regions between the multiple gate electrodes 32) when multiple gate electrodes 32 are arranged with a narrow pitch.
  • the first silicide portion 40 is preferably formed at a distance inward from both the first sidewall 34 and the second sidewall 35.
  • the first polysilicon portion 41 is preferably exposed from both the first sidewall 34 and the second sidewall 35.
  • the first silicide portion 40 is preferably formed at a distance inward from both the first sidewall 34 and the second sidewall 35 over the entire surface area of the electrode surface 33.
  • the first polysilicon portion 41 is preferably exposed from both the first sidewall 34 and the second sidewall 35 over the entire surface area of the electrode surface 33.
  • the first polysilicon portion 41 may form a flat electrode surface 33 together with the first silicide portion 40 (see FIG. 7).
  • the first polysilicon portion 41 may be recessed toward the first main surface 3 side from the first silicide portion 40 (see FIG. 10A).
  • the first polysilicon portion 41 may protrude upward from the first silicide portion 40 (see FIG. 10B).
  • the first silicide portion 40 may be formed on the surface portion of the electrode surface 33 with a gap from the middle portion of the gate electrode 32 toward the electrode surface 33 in the thickness direction.
  • the semiconductor device 1 may include a gate wiring 52 selectively routed on the first main surface 3 so as to be connected to the gate electrode 32.
  • the gate wiring 52 includes polysilicon and has a wiring surface 53.
  • the semiconductor device 1 may include a second silicide portion 60 and a second polysilicon portion 61.
  • the second silicide portion 60 is formed on the surface portion of the wiring surface 53.
  • the second polysilicon portion 61 is formed on a portion of the surface portion of the wiring surface 53 outside the second silicide portion 60.
  • the second silicide portion 60 is preferably connected to the first silicide portion 40 at the connection portion of the gate electrode 32 and the gate wiring 52.
  • the second polysilicon portion 61 is preferably connected to the first polysilicon portion 41 at the connection portion of the gate electrode 32 and the gate wiring 52. With this configuration, a wiring path is formed that reaches the first silicide portion 40 via the second silicide portion 60. This appropriately reduces the wiring resistance in both the gate electrode 32 and the gate wiring 52.
  • the gate wiring 52 has a first wiring sidewall 54 and a second wiring sidewall 55.
  • the second silicide portion 60 is preferably formed at a distance inward from at least one of the first wiring sidewall 54 and the second wiring sidewall 55.
  • the second polysilicon portion 61 is preferably exposed from at least one of the first wiring sidewall 54 and the second wiring sidewall 55.
  • the second silicide portion 60 is not removed from at least one of the first wiring sidewall 54 and the second wiring sidewall 55 during the manufacturing process of the gate wiring 52 (polysilicon etching process). This suppresses metal contamination (metal particle contamination) of other structures on the first main surface 3 and metal contamination (metal particle contamination) of the manufacturing equipment caused by etching the second silicide portion 60. Therefore, a semiconductor device 1 having appropriate electrical characteristics is provided.
  • the second silicide portion 60 is preferably formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55.
  • the second polysilicon portion 61 is preferably exposed from both the first wiring sidewall 54 and the second wiring sidewall 55.
  • the second silicide portion 60 is preferably formed at a distance inward from both the first wiring sidewall 54 and the second wiring sidewall 55 over the entire surface area of the wiring surface 53.
  • the second polysilicon portion 61 is preferably exposed from both the first wiring sidewall 54 and the second wiring sidewall 55 over the entire surface area of the wiring surface 53.
  • the gate electrode 32 may extend in the second direction Y (one direction).
  • the gate wiring 52 may have a portion extending in the first direction X (intersecting direction) intersecting the second direction Y (one direction). That is, the gate wiring 52 may be connected to the gate electrode 32 in a T-shape (see FIG. 5).
  • the second silicide portion 60 may be connected to the first silicide portion 40 in a T-shape (see FIG. 5).
  • the second polysilicon portion 61 may be connected to the first polysilicon portion 41 in an L-shape at the connection corner of the gate electrode 32 and the gate wiring 52 (see FIG. 5).
  • the semiconductor device 1 may include an interlayer film 70.
  • the interlayer film 70 may cover the gate electrode 32 and have a portion in contact with the first silicide portion 40 and a portion in contact with the first polysilicon portion 41.
  • the semiconductor device 1 does not have an insulating sidewall structure (spacer) that covers the first sidewall 34 and the second sidewall 35 of the gate electrode 32.
  • the interlayer film 70 directly covers the first sidewall 34 and the second sidewall 35 of the gate electrode 32.
  • the interlayer film 70 may cover the gate wiring 52 and have a portion in contact with the second silicide portion 60 and a portion in contact with the second polysilicon portion 61.
  • the semiconductor device 1 does not have an insulating sidewall structure (spacer) that covers the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52.
  • the interlayer film 70 directly covers the first wiring sidewall 54 and the second wiring sidewall 55 of the gate wiring 52.
  • the interlayer film 70 may have a laminated structure including a first oxide film 72 and a second oxide film 73.
  • the first oxide film 72 may be an oxide film with no added impurities.
  • the first oxide film 72 may have a portion in contact with the first silicide portion 40 and a portion in contact with the first polysilicon portion 41.
  • the second oxide film 73 may be an oxide film containing phosphorus.
  • the second oxide film 73 may have a portion covering the first silicide portion 40 and the first polysilicon portion 41 with the first oxide film 72 in between.
  • the first oxide film 72 may have a portion in contact with the second silicide portion 60 and a portion in contact with the second polysilicon portion 61.
  • the second oxide film 73 may be an oxide film containing phosphorus.
  • the second oxide film 73 may have portions that cover the second silicide portion 60 and the second polysilicon portion 61 with the first oxide film 72 in between.
  • the semiconductor device 1 may include an n-type first semiconductor region 6, a p-type body region 20, n-type source regions 23, 24 (impurity regions), channel regions 26, 27 (channels), and an insulating film 31.
  • the first semiconductor region 6 may be formed in a surface layer portion of the first main surface 3.
  • the body region 20 may be formed in a surface layer portion of the first semiconductor region 6.
  • the source regions 23, 24 may be formed in a surface layer portion of the body region 20.
  • the channel regions 26, 27 may be formed in the surface portion of the body region 20 in a region between the first semiconductor region 6 and the source regions 23, 24.
  • the insulating film 31 may cover the channel regions 26, 27 on the first main surface 3.
  • the gate electrode 32 may face the channel regions 26, 27 with the insulating film 31 in between.
  • the semiconductor device 1 includes a chip 2, a gate electrode 32, an interlayer film 70, a source opening 90, a first buried electrode 101, and a first main electrode film 102.
  • the chip 2 has a first main surface 3.
  • the gate electrode 32 is disposed on the first main surface 3.
  • the interlayer film 70 covers the gate electrode 32 and has an insulating surface 71.
  • the source opening 90 is formed in the interlayer film 70 at a distance from the gate electrode 32, exposing the first main surface 3.
  • the first buried electrode 101 is buried in the source opening 90 and is electrically connected to the first principal surface 3.
  • the first buried electrode 101 has a first buried electrode surface 105 exposed from the source opening 90.
  • the first main electrode film 102 is mechanically and electrically connected to the first buried electrode surface 105 of the first buried electrode 101. With this configuration, the first buried electrode 101 improves the film-forming property of the first main electrode film 102 with respect to the source opening 90.
  • the first buried electrode 101 is preferably buried in the source opening 90 so as to expose the insulating surface 71.
  • the first main electrode film 102 is preferably disposed on the insulating surface 71 of the interlayer film 70 and the first buried electrode surface 105 of the first buried electrode 101.
  • the step between the insulating surface 71 and the source opening 90 is reduced by the first buried electrode 101. This improves the film formation property of the first main electrode film 102 on the insulating surface 71 of the interlayer film 70 and the first buried electrode surface 105 of the first buried electrode 101.
  • the first buried electrode surface 105 of the first buried electrode 101 may be located closer to the first principal surface 3 than the insulating surface 71. With this configuration, the first buried electrode 101 can be appropriately prevented from protruding above the insulating surface 71. In this case, the first principal electrode film 102 may be connected to the first buried electrode surface 105 of the first buried electrode 101 on the first principal surface 3 side closer to the insulating surface 71.
  • the first buried electrode surface 105 of the first buried electrode 101 is preferably positioned above the electrode surface 33 of the gate electrode 32. With this configuration, the step between the insulating surface 71 and the source opening 90 is reduced by the first buried electrode 101 to a height position above the electrode surface 33. This allows the connection portion of the source main electrode to the first buried electrode 101 to be positioned above the electrode surface 33.
  • the first buried electrode surface 105 of the first buried electrode 101 may have a recess 106 facing the chip 2.
  • the bottom of the recess 106 is positioned above the height position of the gate electrode 32 (electrode surface 33).
  • the source opening 90 has an aspect ratio D/W that is vertically elongated along the stacking direction.
  • the first buried electrode 101 is buried in the narrow source opening 90. This improves the film-forming properties of the first main electrode film 102 for the narrow source opening 90 by the first buried electrode 101. In addition, with this configuration, the size of the device caused by the aspect ratio D/W of the source opening 90 is suppressed.
  • the first buried electrode 101 preferably contains tungsten. With this configuration, the first buried electrode 101 is appropriately buried in the source opening 90 by utilizing the physical properties of tungsten.
  • the first main electrode film 102 may contain aluminum.
  • the first buried electrode 101 may contain tungsten, while the first main electrode film 102 may contain aluminum.
  • Such a configuration is effective in improving the film formability of the first main electrode film 102 for the narrow source opening 90 when a relatively narrow source opening 90 is formed.
  • the interlayer film 70 may have a laminated structure including a first oxide film 72 and a second oxide film 73.
  • the first oxide film 72 may be an oxide film without doping with impurities.
  • the second oxide film 73 may be an oxide film containing phosphorus. In this case, the source opening 90 may penetrate the first oxide film 72 and the second oxide film 73.
  • the interlayer film 70 preferably has an arc corner portion that is curved in an arc shape in the portion that covers the corner portion of the gate electrode 32.
  • the source opening 90 preferably has an opening end that is defined by the arc corner portion.
  • the multiple gate electrodes 32 may be arranged at intervals on the first main surface 3.
  • the source opening 90 may be defined in a region between the multiple gate electrodes 32.
  • the first buried electrode 101 improves the film formation property of the first main electrode film 102 for the source opening 90 defined in a region between the multiple gate electrodes 32.
  • the semiconductor device 1 may include a first underlying electrode film 100.
  • the first underlying electrode film 100 may cover the wall surface of the source opening 90 and have a portion electrically connected to the chip 2 within the source opening 90.
  • the first buried electrode 101 may be buried in the source opening 90 via the first underlying electrode film 100.
  • the first buried electrode 101 can be buried in the source opening 90 with the first underlying electrode film 100 as a barrier film against the chip 2.
  • the first underlying electrode film 100 may include at least one of a Ti film and a TiN film.
  • the first underlying electrode film 100 may be mechanically and electrically connected to the chip 2.
  • the first buried electrode 101 may be electrically connected to the chip 2 via the first underlying electrode film 100.
  • the first underlying electrode film 100 may have a portion that covers the insulating surface 71 outside the source opening 90.
  • the first main electrode film 102 may cover the insulating surface 71 with the first underlying electrode film 100 sandwiched therebetween.
  • the first main electrode film 102 can be formed on the interlayer film 70 with the first underlying electrode film 100 serving as a barrier film for the interlayer film 70.
  • the semiconductor device 1 may include a first source silicide portion 108 formed in the surface layer of the portion of the first main surface 3 exposed from the source opening 90.
  • the first source silicide portion 108 may be mechanically and electrically connected to the first underlying electrode film 100. This configuration improves the ohmic properties between the chip 2 and the first underlying electrode film 100 (first buried electrode 101).
  • the semiconductor device 1 may include a source recess 91 formed in a portion of the first main surface 3 exposed from the source opening 90.
  • the first base electrode film 100 may have a portion located within the source recess 91.
  • the semiconductor device 1 may include a gate wiring 52 that is selectively routed over the first main surface 3 and connected to the gate electrode 32. With this configuration, the wiring path to the gate electrode 32 is formed by the gate wiring 52.
  • the semiconductor device 1 may include a gate opening 94, a second buried electrode 121, and a second main electrode film 122.
  • the gate opening 94 may be formed in the interlayer film 70 so as to expose the gate wiring 52.
  • the second buried electrode 121 may be buried in the gate opening 94 and electrically connected to the gate wiring 52.
  • the second buried electrode 121 may have a second buried electrode surface 125 exposed from the interlayer film 70.
  • the second main electrode film 122 may be mechanically and electrically connected to the second buried electrode surface 125. With this configuration, the second buried electrode 121 improves the film-forming properties of the second main electrode film 122 relative to the gate opening 94.
  • the semiconductor device 1 may include an n-type first semiconductor region 6, a p-type body region 20, n-type source regions 23, 24 (first impurity regions), a p-type contact region 25 (second impurity region), channel regions 26, 27 (channels), and an insulating film 31.
  • the first semiconductor region 6 may be formed in a surface layer portion of the first major surface 3.
  • the body region 20 may be formed in a surface layer portion of the first semiconductor region 6.
  • the source regions 23, 24 may be formed in a surface layer portion of the body region 20.
  • the contact region 25 may be formed in a region of the surface layer portion of the body region 20 that is different from the source regions 23, 24.
  • the channel regions 26, 27 may be formed in the surface portion of the body region 20 in a region between the first semiconductor region 6 and the source regions 23, 24.
  • the insulating film 31 may cover the channel regions 26, 27 on the first main surface 3.
  • the gate electrode 32 may face the channel regions 26, 27 with the insulating film 31 in between.
  • the source opening 90 may expose the source regions 23, 24 and the contact region 25.
  • the first buried electrode 101 may be electrically connected to the source regions 23, 24 and the contact region 25 within the source opening 90.
  • the semiconductor device 1 may include a first silicide portion 40 and a first polysilicon portion 41.
  • the first silicide portion 40 may be partially formed on the surface portion of the gate electrode 32.
  • the first polysilicon portion 41 may be formed on the surface portion of the gate electrode 32 in a portion other than the silicide portion. With this configuration, the wiring resistance (gate resistance) of the gate electrode 32 is reduced by the first silicide portion 40.
  • FIG. 13 is a schematic diagram showing a wafer 150 used in the manufacture of a semiconductor device 1.
  • the wafer 150 is a base material for the chip 2 and contains a SiC single crystal.
  • the wafer 150 is formed in a flat disk shape. Of course, the wafer 150 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.
  • the first wafer main surface 151 corresponds to the first main surface 3 of the chip 2
  • the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2.
  • the first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 151 is formed by the silicon surface of the SiC single crystal
  • the second wafer main surface 152 is formed by the carbon surface of the SiC single crystal.
  • the wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has the off-direction and off-angle described above.
  • the wafer 150 has a mark 154 on the wafer side surface 153 that indicates the crystal orientation of the SiC single crystal.
  • the mark 154 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat is a cutout that is cut in a straight line in a plan view.
  • the orientation notch is a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 151 in a plan view.
  • the mark 154 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 154 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • the wafer 150 includes a first semiconductor region 6 in a region (surface layer) on the first wafer main surface 151 side.
  • the first semiconductor region 6 is formed in a layer extending along the first wafer main surface 151.
  • the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).
  • the wafer 150 includes a second semiconductor region 7 in the region (surface layer) on the second wafer main surface 152 side.
  • the second semiconductor region 7 is formed in a layer extending along the second wafer main surface 152 and is electrically connected to the first semiconductor region 6.
  • the second semiconductor region 7 is made of the wafer main body (specifically, a SiC wafer). That is, in this embodiment, the wafer 150 is made of an epitaxial wafer (so-called epiwafer) having a layered structure including the wafer main body and an epitaxial layer.
  • a plurality of device regions 155 and a plurality of cutting lines 156 are set on the wafer 150 by alignment marks or the like.
  • Each device region 155 is an area corresponding to a semiconductor device 1.
  • Each of the plurality of device regions 155 is set to have a rectangular shape in a plan view.
  • the multiple device regions 155 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 155 are each set at intervals inward from the periphery of the first wafer main surface 151 in a plan view.
  • the multiple cutting lines 156 are set in a lattice shape extending along the first direction X and the second direction Y to partition the multiple device regions 155.
  • FIGS. 14A to 14R are cross-sectional views showing a method for manufacturing a semiconductor device 1.
  • FIG. 14A to FIG. 14R a cross section of a portion of an active region 8 of one device region 155 is shown.
  • the aforementioned wafer 150 is prepared.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of body regions 20.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation using a mask (not shown), forming the outer body region 21.
  • n-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation using a mask (not shown), forming a plurality of source regions 23, 24.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of contact regions 25.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a termination region 45.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of field regions 47.
  • the order of the process of forming the body region 20, the process of forming the outer body region 21, the process of forming the source regions 23 and 24, the process of forming the contact region 25, the process of forming the termination region 45, and the process of forming the field region 47 may be arbitrary.
  • the process of forming the outer body region 21 may be performed simultaneously with the process of forming the body region 20.
  • the process of forming the termination region 45 may be performed simultaneously with the process of forming the body region 20 or the process of forming the outer body region 21.
  • the process of forming the field region 47 may be performed simultaneously with the process of forming the body region 20, the process of forming the outer body region 21, or the process of forming the termination region 45.
  • a base insulating film 160 is formed to cover the first wafer main surface 151.
  • the base insulating film 160 is the base of the insulating film 31 and the peripheral insulating film 51.
  • the base insulating film 160 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation process (e.g., a thermal oxidation process).
  • a base electrode 161 is formed on the base insulating film 160.
  • the base electrode 161 is the base of the gate electrode 32 and the gate wiring 52.
  • the base electrode 161 includes conductive polysilicon.
  • the base electrode 161 may be formed by a CVD method.
  • the base electrode 161 has a base electrode surface 162 that extends along the base insulating film 160.
  • a first mask 163 is formed on the base electrode 161 (base electrode surface 162).
  • the first mask 163 is preferably an inorganic mask (i.e., a hard mask).
  • the first mask 163 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the first mask 163 is made of a silicon oxide film (insulating film).
  • the first mask 163 may be formed by a CVD method.
  • the first mask 163 may be formed by an oxidation treatment method (e.g., a thermal oxidation treatment method) for the base electrode 161.
  • a second mask 164 having a predetermined layout is formed on the first mask 163.
  • the second mask 164 exposes regions of the base electrode surface 162 where a plurality of first silicide portions 40 are to be formed, and covers regions of the base electrode surface 162 where a plurality of first polysilicon portions 41 are to be formed.
  • the second mask 164 also exposes regions of the base electrode surface 162 where a plurality of second silicide portions 60 are to be formed, and covers regions of the base electrode surface 162 where a plurality of second polysilicon portions 61 are to be formed.
  • the etching may be wet etching and/or dry etching.
  • the first mask 163 having a predetermined layout that selectively exposes the base electrode 161 is formed on the base electrode 161.
  • the first mask 163 exposes the regions of the base electrode 161 (base electrode surface 162) in which the multiple first silicide portions 40 and the second silicide portions 60 are to be formed, and covers the regions in which the multiple first polysilicon portions 41 and the second polysilicon portions 61 are to be formed.
  • a portion (surface portion) of the base electrode 161 may be partially removed.
  • recesses corresponding to the first electrode recess 42 and the second electrode recess 43 (see FIG. 10C) of the gate electrode 32 are formed in the base electrode surface 162.
  • recesses corresponding to the first wiring recess 62 and the second wiring recess 63 (see FIG. 11C) of the gate wiring 52 are formed in the base electrode surface 162.
  • the material of the first mask 163, the type of etching process, process conditions, etc. may be adjusted so that a portion of the base electrode surface 162 is not removed.
  • the second mask 164 is removed after the removal process of the first mask 163.
  • the first mask 163 may be made of an organic mask (i.e., a soft mask) instead of an inorganic mask.
  • the first mask 163 may be a resist mask. In these cases, the first mask 163 may be shaped into a predetermined layout through an exposure process and a development process.
  • a metal film 165 is formed to partially cover the base electrode surface 162 of the base electrode 161.
  • the metal film 165 may include at least one of a Ti film, a Ni film, a Co film, a Mo film, and a W film.
  • the metal film 165 may be formed by a sputtering method, a vapor deposition method, or the like.
  • the metal film 165 covers both the base electrode 161 and the first mask 163.
  • the metal film 165 covers a plurality of portions of the base electrode surface 162 of the base electrode 161 that are exposed from the first mask 163.
  • the metal film 165 reacts with the polysilicon of the base electrode 161 (silicide reaction), and multiple portions of the base electrode surface 162 that contact the metal film 165 are silicided.
  • first silicide portions 40 and second silicide portions 60 are partially formed on the base electrode surface 162. Portions of the base electrode surface 162 other than the first silicide portions 40 and the second silicide portions 60 are formed as polysilicon portions 166.
  • the silicide reaction may be carried out by an annealing method such as a rapid thermal anneal (RTA) method.
  • RTA rapid thermal anneal
  • the first silicide portions 40 may be formed flat with respect to the base electrode surface 162 (polysilicon portion 166) (see FIG. 7). In this process, the first silicide portions 40 may be formed so as to protrude above the base electrode surface 162 (polysilicon portion 166) (see FIG. 10A).
  • the second silicide portion 60 may be formed flat with respect to the base electrode surface 162 (polysilicon portion 166) (see FIG. 9). In this process, the second silicide portion 60 may be formed so as to protrude above the base electrode surface 162 (polysilicon portion 166) (see FIG. 11A).
  • the metal film 165 may be removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the first mask 163 may be removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method. If the first mask 163 is an organic mask, the first mask 163 may be removed by an ashing method.
  • the first silicide portions 40 may be partially removed. In this case, the first silicide portions 40 may be removed until they are positioned on the base insulating film 160 side relative to the height position of the base electrode surface 162 (polysilicon portion 166) (see FIG. 10B).
  • the second silicide portion 60 may be partially removed. In this case, the second silicide portion 60 may be removed until it is positioned on the base insulating film 160 side relative to the height position of the base electrode surface 162 (polysilicon portion 166) (see FIG. 11B).
  • a third mask 167 having a predetermined layout is formed on the base electrode 161 (base electrode surface 162).
  • the third mask 167 may be an organic mask (e.g., a resist mask).
  • the third mask 167 has a plurality of mask portions 168 that cover the regions where the plurality of gate electrodes 32 are to be formed, and has a plurality of openings 169 that expose the regions other than the plurality of mask portions 168.
  • Each mask portion 168 is formed wider than the corresponding first silicide portion 40, and partially covers the polysilicon portion 166 on both sides of the first silicide portion 40.
  • each mask portion 168 has a first covering portion 171, a second covering portion 172, and a third covering portion 173.
  • the first covering portion 171 covers the entire area of the corresponding first silicide portion 40.
  • the second covering portion 172 extends from the first covering portion 171 to one side and covers a portion of the polysilicon portion 166 as the area where the first polysilicon portion 41 (41A) is to be formed.
  • the third covering portion 173 extends from the first covering portion 171 to the other side and covers a portion of the polysilicon portion 166 as the area where the first polysilicon portion 41 (41B) is to be formed.
  • the third mask 167 has a mask portion 168 that covers the region where the gate wiring 52 is to be formed.
  • the mask portion 168 relating to the gate wiring 52 is formed wider than the corresponding second silicide portion 60, and partially covers the polysilicon portion 166 on both sides of the second silicide portion 60.
  • the mask portion 168 relating to the gate wiring 52 has a first covering portion 171, a second covering portion 172, and a third covering portion 173, similar to the mask portion 168 relating to the gate electrode 32.
  • the first covering portion 171 covers the entire second silicide portion 60.
  • the second covering portion 172 extends from the first covering portion 171 to one side and covers a portion of the polysilicon portion 166 as the region where the second polysilicon portion 61 (61A) is to be formed.
  • the third covering portion 173 extends from the first covering portion 171 to the other side and covers a portion of the polysilicon portion 166 as the region where the second polysilicon portion 61 (61B) is to be formed.
  • the multiple openings 169 are defined in the regions between the multiple mask portions 168.
  • the multiple openings 169 are formed at intervals from the multiple first silicide portions 40 and the multiple second silicide portions 60, and each exposes a portion of the polysilicon portion 166. In other words, the multiple openings 169 expose only the polysilicon portion 166, and do not expose the multiple first silicide portions 40 and the multiple second silicide portions 60.
  • the base electrode 161 is removed by an etching method using a third mask 167.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the base electrode 161 is removed in the thickness direction from the portion of the base electrode surface 162 where the polysilicon portion 166 is exposed.
  • a plurality of gate electrodes 32 are formed, each having a first silicide portion 40 and a first polysilicon portion 41 as part of the polysilicon portion 166.
  • a gate wiring 52 is formed, each having a second silicide portion 60 and a second polysilicon portion 61 as part of the polysilicon portion 166.
  • the first silicide portion 40 and the second silicide portion 60 are protected from the etchant by the third mask 167 and are not etched. In other words, in this process, only the polysilicon portion 166 is removed, and the first silicide portion 40 and the second silicide portion 60 are not removed.
  • the process of removing the base electrode 161 may include an over-etching process for the base electrode 161.
  • the base electrode 161 is removed until the lower surface of the third mask 167 (mask portion 168) is exposed.
  • the over-etching process is completed before the first silicide portion 40 and the second silicide portion 60 are exposed.
  • the etched surface (etching sidewall) of the base electrode 161 is maintained facing the first silicide portion 40 and the second silicide portion 60 with a portion of the polysilicon sandwiched therebetween.
  • an interlayer film 70 is formed on the first wafer main surface 151.
  • an interlayer film 70 is formed having a portion that directly covers the electrode surface 33, the first sidewall 34, and the second sidewall 35 of the gate electrode 32.
  • an interlayer film 70 is formed having a portion that directly covers the wiring surface 53, the first wiring sidewall 54, and the second wiring sidewall 55 of the gate wiring 52.
  • the interlayer film 70 has a laminated structure including a first oxide film 72 and a second oxide film 73.
  • the first oxide film 72 includes a silicon oxide film with no added impurities.
  • the second oxide film 73 includes a silicon oxide film containing phosphorus.
  • the first oxide film 72 may be formed by a CVD method.
  • the second oxide film 73 may be formed by a CVD method. After the process of forming the second oxide film 73, a reflow process (heat treatment process) is performed on the interlayer film 70. This smoothes the corners and rough surfaces of the interlayer film 70.
  • a fourth mask 174 having a predetermined layout is placed on the interlayer film 70.
  • the fourth mask 174 exposes areas where the source openings 90, the outer openings 92, and the gate openings 94 are to be formed, and covers the other areas.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the etching method is preferably an anisotropic dry etching method (e.g., RIE (Reactive Ion Etching) method).
  • a plurality of source openings 90, a plurality of outer openings 92, and a plurality of gate openings 94 are formed in the interlayer film 70.
  • an insulating film 31 and a peripheral insulating film 51 are formed. This process may include a process of forming a plurality of source recesses 91 and a process of forming a plurality of outer recesses 93.
  • a process is performed in which the portions of the first wafer main surface 151 exposed from the multiple source openings 90 and the multiple outer openings 92 are further dug down toward the second wafer main surface 152.
  • the fourth mask 174 is then removed.
  • the reflow process (heat treatment process) for the interlayer film 70 described above may be performed after the process of forming the multiple source openings 90, etc.
  • a base underlying electrode film 175 is formed on the interlayer film 70.
  • the base underlying electrode film 175 is the base of the first underlying electrode film 100 and the second underlying electrode film 120.
  • the base underlying electrode film 175 has a laminated structure including a first base electrode film 176 and a second base electrode film 177.
  • the first base electrode film 176 is the base of the first electrode film 103 and the first electrode film 123.
  • the second base electrode film 177 is the base of the second electrode film 104 and the second electrode film 124.
  • the first base electrode film 176 includes a Ti film.
  • the first base electrode film 176 may be formed by a sputtering method or a vapor deposition method.
  • the first base electrode film 176 is formed in the form of a film along the insulating surface 71 of the interlayer film 70, the wall surfaces of the multiple source openings 90, the wall surfaces of the multiple outer openings 92, and the wall surfaces of the multiple gate openings 94.
  • the second base electrode film 177 includes a TiN film.
  • the second base electrode film 177 may be formed by a sputtering method or a vapor deposition method.
  • the second base electrode film 177 is formed in the form of a film along the insulating surface 71 of the interlayer film 70, the wall surfaces of the multiple source openings 90, the wall surfaces of the multiple outer openings 92, and the wall surfaces of the multiple gate openings 94.
  • the first base electrode film 176 reacts (silicide reaction) with the SiC of the first wafer main surface 151 to form a plurality of first source silicide portions 108 and a plurality of second source silicide portions 111.
  • the silicide reaction may be performed by an annealing method such as an RTA method.
  • the process of forming the first source silicide portion 108 may be performed prior to the process of forming the second electrode film 104 (second electrode film 124).
  • the process of forming the first source silicide portion 108 (second source silicide portion 111) may be performed after the process of forming the second electrode film 104 (second electrode film 124).
  • the first source silicide portion 108 (second source silicide portion 111) may be formed containing a silicide other than Ti silicide.
  • a process of silicidizing the wafer 150 with a metal film (not shown) is carried out prior to the process of forming the first base electrode film 176.
  • the metal film may contain at least one of a Ni film, a Co film, a Mo film, and a W film.
  • the metal film may be formed by a sputtering method or a vapor deposition method.
  • a base intermediate electrode film 178 is formed on the base undercoat electrode film 175.
  • the base intermediate electrode film 178 includes at least one of tungsten, molybdenum, a tungsten alloy, and a molybdenum alloy.
  • the base intermediate electrode film 178 includes tungsten.
  • the base intermediate electrode film 178 may be formed by a CVD method (e.g., a reduced pressure CVD method).
  • the base intermediate electrode film 178 backfills the source openings 90, the outer openings 92, and the gate openings 94, and coats the insulating surface 71 of the interlayer film 70 in a film-like manner.
  • etching method may be a wet etching method and/or a dry etching method.
  • Unnecessary portions of the base intermediate electrode film 178 are removed until the base undercoat electrode film 175 is exposed.
  • a plurality of first buried electrodes 101 are buried in the plurality of source openings 90.
  • a plurality of first buried electrodes 101 are also buried in the plurality of outer openings 92.
  • a plurality of second buried electrodes 121 are also buried in the plurality of gate openings 94.
  • the first buried electrode 101 in the first to fifth examples is formed by adjusting the amount of etching for the base intermediate electrode film 178 in this process.
  • the source intermediate electrode 107 in the fifth example is formed by omitting the etching process for the base intermediate electrode film 178.
  • the source intermediate electrode 107 in the fifth example can also be formed by ending the etching process for the base intermediate electrode film 178 before the base undercoat electrode film 175 is exposed.
  • a base main electrode film 179 is formed on the base undercoat electrode film 175, the plurality of first buried electrodes 101, and the plurality of second buried electrodes 121.
  • the base main electrode film 179 is the base of the first main electrode film 102 and the second main electrode film 122.
  • the base main electrode film 179 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the base main electrode film 179 may be formed by a sputtering method or a vapor deposition method.
  • the base main electrode film 179 is divided into the source pad electrode 95, the source finger electrode 110, the gate finger electrode 115, and the gate pad electrode 130.
  • a mask (not shown) having a predetermined layout is formed on the base main electrode film 179.
  • the mask covers the areas where the source pad electrode 95, the source finger electrode 110, the gate finger electrode 115, and the gate pad electrode 130 are to be formed, and exposes areas other than these areas.
  • the unnecessary portions of the base main electrode film 179 are removed by an etching method through a mask (not shown).
  • the unnecessary portions of the base main electrode film 179 are removed until the base undercoat electrode film 175 is exposed.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the mask (not shown) is removed after the etching process of the base main electrode film 179.
  • the process of removing the base underlying electrode film 175 includes a process of removing the second base electrode film 177 by an etching method, and a process of removing the first base electrode film 176 by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • unnecessary portions of the base underlayer electrode film 175 may be removed by an etching method using a mask (not shown) in the etching process of the base main electrode film 179.
  • the source pad electrode 95, the source finger electrode 110, the gate finger electrode 115, and the gate pad electrode 130 are formed on the interlayer film 70.
  • a drain pad electrode 140 is formed on the second wafer main surface 152.
  • the drain pad electrode 140 may be formed by a sputtering method or a vapor deposition method.
  • the wafer 150 is then cut along the intended cutting lines 156, and multiple semiconductor devices 1 are cut out. Through the steps including those described above, the semiconductor device 1 is manufactured.
  • FIG. 15 is a cross-sectional view showing a first modified example of the semiconductor device 1.
  • FIG. 16 is a cross-sectional view showing a second modified example of the semiconductor device 1.
  • the semiconductor device 1 does not necessarily have to have the first silicide portion 40 (first polysilicon portion 41) in the gate electrode 32. Similarly, the semiconductor device 1 does not necessarily have to have the second silicide portion 60 (second polysilicon portion 61) in the gate wiring 52.
  • the semiconductor device 1 may have a first silicide portion 40 (first polysilicon portion 41) but may not have a second silicide portion 60 (second polysilicon portion 61).
  • the semiconductor device 1 may have a second silicide portion 60 (second polysilicon portion 61) but may not have a first silicide portion 40 (first polysilicon portion 41).
  • the semiconductor device 1 does not necessarily have to have the first buried electrode 101.
  • the first main electrode film 102 associated with the source pad electrode 95 enters the multiple source openings 90 from above the interlayer film 70, and is electrically connected to the body region 20 and the like within the multiple source openings 90.
  • the first main electrode film 102 associated with the source finger electrode 110 enters the multiple outer openings 92 from above the interlayer film 70, and is electrically connected to the termination region 45 (overlap region 46) within the multiple outer openings 92.
  • the semiconductor device 1 does not necessarily have to have the second buried electrode 121.
  • the gate finger electrode 115 penetrates the multiple gate openings 94 from above the interlayer film 70 and is electrically connected to the gate wiring 52 within the multiple gate openings 94.
  • the semiconductor device 1 may have a first buried electrode 101 associated with the source pad electrode 95, but may not have a first buried electrode 101 associated with the source finger electrode 110.
  • the semiconductor device 1 may have a first buried electrode 101 associated with the source finger electrode 110, but may not have a first buried electrode 101 associated with the source pad electrode 95.
  • the semiconductor device 1 may have a first buried electrode 101 associated with the source pad electrode 95, but may not have a second buried electrode 121.
  • the semiconductor device 1 may have a second buried electrode 121, but may not have a first buried electrode 101 associated with the source pad electrode 95.
  • the semiconductor device 1 may have a first buried electrode 101 associated with the source finger electrode 110, but may not have a second buried electrode 121.
  • the semiconductor device 1 may have a second buried electrode 121, but may not have a first buried electrode 101 associated with the source finger electrode 110.
  • a structure may be adopted in which the conductivity type of the "n-type” semiconductor region is inverted to "p-type” and the conductivity type of the "p-type” semiconductor region is inverted to "n-type".
  • a specific configuration in this case can be obtained by replacing “n-type” with “p-type” and at the same time replacing "p-type” with “n-type” in the above description and the attached drawings.
  • the chip 2 including single crystal SiC is used.
  • the chip 2 may include single crystal of a wide band gap semiconductor other than single crystal SiC.
  • a wide band gap semiconductor is a semiconductor having a band gap larger than the band gap of silicon. Examples of single crystal of a wide band gap semiconductor include gallium nitride, gallium oxide, diamond, etc.
  • the chip 2 may include single crystal silicon.
  • the first semiconductor region 6 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • the first semiconductor region 6 may contain gallium nitride, gallium oxide, diamond, etc.
  • the first semiconductor region 6 may also contain a silicon single crystal.
  • the second semiconductor region 7 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • the second semiconductor region 7 may contain gallium nitride, gallium oxide, diamond, etc.
  • the second semiconductor region 7 may also contain a silicon single crystal.
  • an n-type second semiconductor region 7 is shown.
  • a p-type second semiconductor region 7 may be used instead of the n-type second semiconductor region 7.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 (n-type chip 2) by ion implantation.
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a gate electrode (32) arranged on the main surface (3), including polysilicon, and having an electrode surface (33); a silicide portion (40) partially formed on a surface portion of the electrode surface (33); and a polysilicon portion (41) formed on a portion of the surface portion of the electrode surface (33) other than the silicide portion (40).
  • the sidewalls (34, 35) include a first sidewall (34) on one side and a second sidewall (35) on the other side, the silicide portion (40) is formed at a distance inward from both the first sidewall (34) and the second sidewall (35), and the polysilicon portion (41) is exposed from both the first sidewall (34) and the second sidewall (35), in the semiconductor device (1) described in A2.
  • a semiconductor device (1) according to any one of A1 to A8, further comprising: a gate wiring (52) selectively routed over the main surface (3) to be connected to the gate electrode (32), containing polysilicon, and having a wiring surface (53); a second silicide portion (60) formed on the surface portion of the wiring surface (53); and a second polysilicon portion (61) formed on a portion of the surface portion of the wiring surface (53) outside the second silicide portion (60).
  • the wiring sidewalls (54, 55) include a first wiring sidewall (54) on one side and a second wiring sidewall (55) on the other side
  • the second silicide portion (60) is formed at a distance inward from both the first wiring sidewall (54) and the second wiring sidewall (55)
  • the second polysilicon portion (61) is exposed from both the first wiring sidewall (54) and the second wiring sidewall (55).
  • the interlayer film (70) includes a first oxide film (72) containing no impurities and having a portion in contact with the silicide portion (40) and a portion in contact with the polysilicon portion (41), and a second oxide film (73) containing phosphorus and covering the first oxide film (72).
  • a semiconductor device (1) according to any one of A1 to A15, further comprising: a semiconductor region (6) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (3); a body region (20) of a second conductivity type (p-type) formed in a surface layer portion of the semiconductor region (6); an impurity region (23, 24) of a first conductivity type (n-type) formed in a surface layer portion of the body region (20); a channel (26, 27) formed in a region between the semiconductor region (6) and the impurity region (23, 24) in the surface layer portion of the body region (20); and an insulating film (31) covering the channel (26, 27) on the main surface (3), wherein the gate electrode (32) faces the channel (26, 27) across the insulating film (31).
  • a method for manufacturing a semiconductor device (1) comprising the steps of: forming a base electrode (161) containing polysilicon on a wafer (150); forming a metal film (165) partially covering an electrode surface (162) of the base electrode (161); reacting the polysilicon with the metal film (165) to partially form a silicide portion (40) on the surface of the electrode surface (162); removing unreacted portions of the metal film (165) from the electrode surface (162); and removing the base electrode (161) in the thickness direction from the polysilicon portion (166) outside the silicide portion (40) to form a gate electrode (32) having both the silicide portion (40) and the polysilicon portion (41, 166) on the surface of the electrode surface (33, 162).
  • the method for manufacturing a semiconductor device (1) according to A18 further includes, prior to the step of forming the metal film (165), a step of forming a base mask (163) on the base electrode (161) to selectively expose the base electrode (161), the step of forming the metal film (165) includes a step of forming the metal film (165) to cover both the base electrode (161) and the base mask (163), and the step of forming the silicide portion (40) includes a step of reacting the portion of the polysilicon exposed from the base mask (163) with the metal film (165).
  • a semiconductor device (1) including: a chip (2) having a principal surface (3); a gate electrode (32) arranged on the principal surface (3); an interlayer film (70) covering the gate electrode (32) and having an insulating surface (71); an opening (90) formed in the interlayer film (70) spaced apart from the gate electrode (32) and exposing the principal surface (3); a buried electrode (101) buried in the opening (90), having an electrode surface (105) exposed from the opening (90), and electrically connected to the principal surface (3); and a main electrode (102) mechanically and electrically connected to the electrode surface (105) of the buried electrode (101).
  • the interlayer film (70) includes a first oxide film (72) containing no impurities that covers the gate electrode (32), and a second oxide film (73) that contains phosphorus and covers the first oxide film (72), and the opening (90) penetrates both the first oxide film (72) and the second oxide film (73).
  • the semiconductor device (1) described in B11 or 12 further includes a surface silicide portion (108) formed on the surface portion of the main surface (3) exposed from the opening (90) and mechanically and electrically connected to the base electrode film (100).
  • the semiconductor device (1) described in B16 further includes a gate opening (94) formed in the interlayer film (70) so as to expose the gate wiring (52), a gate buried electrode (121) that is buried in the gate opening (94) and has a gate buried electrode surface (125) exposed from the gate opening (94) and is electrically connected to the gate wiring (52), and a gate main electrode (122) that is mechanically and electrically connected to the gate buried electrode surface (125) of the gate buried electrode (121).
  • the semiconductor device (1) according to any one of B1 to B17 further includes a gate electrode (32) facing the channel (26, 27) across the insulating film (31) and covering the channel (26, 27) on the main surface (3), the gate electrode (32) facing the channel (26, 27) across the insulating film (31), the opening (90) exposing the impurity region (23, 24), and the buried electrode (101) electrically connected to the impurity region (23, 24) within the opening (90).
  • the semiconductor device (1) described in B18 further includes a second impurity region (25) of a second conductivity type (p-type) formed in a region different from the impurity regions (23, 24) in the surface layer portion of the body region (20), the opening (90) exposes the second impurity region (25), and the buried electrode (101) is electrically connected to the second impurity region (25) within the opening (90).
  • a second impurity region (25) of a second conductivity type (p-type) formed in a region different from the impurity regions (23, 24) in the surface layer portion of the body region (20)
  • the opening (90) exposes the second impurity region (25)
  • the buried electrode (101) is electrically connected to the second impurity region (25) within the opening (90).
  • a method for manufacturing a semiconductor device (1) comprising the steps of forming a gate electrode (32) on a wafer (150), forming an interlayer film (70) on the wafer (150) to cover the gate electrode (32), forming an opening (90) in the interlayer film (70) to expose the wafer (150) at a position spaced apart from the gate electrode (32), embedding an electrode (178) in the opening (90) so as to be electrically connected to the wafer (150), and forming a buried electrode (101) having an electrode surface (105) exposed from the opening (90), and forming a main electrode (102) that directly covers the electrode surface (105) of the buried electrode (101).
  • [B23] A method for manufacturing a semiconductor device (1) according to B22, in which the wafer (150) includes a wide band gap semiconductor.

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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005072519A (ja) * 2003-08-28 2005-03-17 Sanken Electric Co Ltd 絶縁ゲート型半導体素子およびこれを備えた半導体集積回路装置
WO2009019837A1 (ja) * 2007-08-07 2009-02-12 Panasonic Corporation 炭化珪素半導体素子およびその製造方法
JP2009164183A (ja) * 2007-12-28 2009-07-23 Toshiba Corp 半導体装置及びその製造方法
JP2014514756A (ja) * 2011-03-28 2014-06-19 ゼネラル・エレクトリック・カンパニイ ゲート電極を有する炭化ケイ素半導体デバイス
JP2017028219A (ja) * 2015-07-28 2017-02-02 三菱電機株式会社 炭化珪素半導体装置およびその製造方法
WO2020235629A1 (ja) * 2019-05-22 2020-11-26 ローム株式会社 ＳｉＣ半導体装置
JP2020198425A (ja) * 2019-05-30 2020-12-10 ローム株式会社 半導体装置

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5646527B2 (ja) 2012-03-02 2014-12-24 株式会社東芝 半導体装置および半導体装置の製造方法
JP7785497B2 (ja) 2021-10-08 2025-12-15 Tdk株式会社 ガスセンサ

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005072519A (ja) * 2003-08-28 2005-03-17 Sanken Electric Co Ltd 絶縁ゲート型半導体素子およびこれを備えた半導体集積回路装置
WO2009019837A1 (ja) * 2007-08-07 2009-02-12 Panasonic Corporation 炭化珪素半導体素子およびその製造方法
JP2009164183A (ja) * 2007-12-28 2009-07-23 Toshiba Corp 半導体装置及びその製造方法
JP2014514756A (ja) * 2011-03-28 2014-06-19 ゼネラル・エレクトリック・カンパニイ ゲート電極を有する炭化ケイ素半導体デバイス
JP2017028219A (ja) * 2015-07-28 2017-02-02 三菱電機株式会社 炭化珪素半導体装置およびその製造方法
WO2020235629A1 (ja) * 2019-05-22 2020-11-26 ローム株式会社 ＳｉＣ半導体装置
JP2020198425A (ja) * 2019-05-30 2020-12-10 ローム株式会社 半導体装置

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