WO2024202942A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024202942A1
WO2024202942A1 PCT/JP2024/007836 JP2024007836W WO2024202942A1 WO 2024202942 A1 WO2024202942 A1 WO 2024202942A1 JP 2024007836 W JP2024007836 W JP 2024007836W WO 2024202942 A1 WO2024202942 A1 WO 2024202942A1
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Prior art keywords
region
mesa
contact portion
film
electrode
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Ceased
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PCT/JP2024/007836
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to DE112024001445.3T priority Critical patent/DE112024001445T5/de
Priority to JP2025510079A priority patent/JPWO2024202942A1/ja
Priority to CN202480020269.8A priority patent/CN120937524A/zh
Publication of WO2024202942A1 publication Critical patent/WO2024202942A1/ja
Priority to US19/329,885 priority patent/US20260020303A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H10D62/107—Buried supplementary regions, e.g. buried guard rings 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/154—Dispositions
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/155—Shapes 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
    • H10D64/251—Source or drain electrodes for field-effect devices
    • H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes

Definitions

  • This disclosure relates to a semiconductor device.
  • Patent Document 1 discloses a SiC semiconductor device including a plurality of p-type body regions formed on the surface portion of an n - type SiC semiconductor layer, each of which constitutes a unit cell, an n-type source region formed inside the p-type body region, a gate electrode facing the p-type body region via a gate insulating film, an n + type drain region and a p + type collector region formed adjacent to each other on the back surface portion of the SiC semiconductor layer, and an n - type drift region between the p-type body region and the n + type drain region, and the p + type collector region is formed so as to cover a region including at least two unit cells in the X-axis along the surface of the SiC semiconductor layer.
  • One embodiment of the present disclosure provides a semiconductor device that can reduce the contact resistance on the side of a gate electrode.
  • One embodiment of the present disclosure provides a semiconductor device including a chip having a main surface, a gate electrode formed on the main surface, an interlayer film covering the gate electrode, an opening formed in the interlayer film spaced apart from the gate electrode in a lateral direction along the main surface and exposing a part of the chip as a contact portion, and a surface electrode formed on the interlayer film and mechanically and electrically connected to the contact portion within the opening, the contact portion including a mesa contact portion protruding from the main surface and having a mesa side portion and a mesa top portion, and the surface electrode covering the mesa side portion and the mesa top portion.
  • a semiconductor device can be provided that can reduce the contact resistance on the side of the gate electrode.
  • FIG. 1 is a plan view showing a semiconductor device according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing an example of the layout of the first main surface.
  • FIG. 4 is an enlarged plan view showing a main portion of the first main surface.
  • FIG. 5 is an enlarged plan view showing further essential parts of the first main surface.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is an enlarged cross-sectional view showing a main part of FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG.
  • FIG. 9 is an enlarged cross-sectional view showing a main part of FIG. FIG.
  • FIG. 10 is a schematic perspective view for explaining the structure of the mesa contact portion in detail.
  • FIG. 11 is a schematic diagram showing a wafer.
  • FIG. 12A is a cross-sectional view showing a method for manufacturing a semiconductor device.
  • FIG. 12B is a cross-sectional view showing a step subsequent to that of FIG. 12A.
  • FIG. 12C is a cross-sectional view showing a step subsequent to FIG. 12B.
  • FIG. 12D is a cross-sectional view showing a step subsequent to FIG. 12C.
  • FIG. 12E is a cross-sectional view showing a step subsequent to FIG. 12D.
  • FIG. 12F is a cross-sectional view showing a step subsequent to FIG. 12E.
  • FIG. 12A is a cross-sectional view showing a method for manufacturing a semiconductor device.
  • FIG. 12B is a cross-sectional view showing a step subsequent to that of FIG. 12A.
  • FIG. 12C is a cross-
  • FIG. 12G is a cross-sectional view showing a step subsequent to FIG. 12F.
  • FIG. 12H is a cross-sectional view showing a step subsequent to FIG. 12G.
  • FIG. 12I is a cross-sectional view showing a step subsequent to FIG. 12H.
  • FIG. 12J is a cross-sectional view showing a step subsequent to FIG. 12I.
  • FIG. 12K is a cross-sectional view showing a step subsequent to FIG. 12J.
  • FIG. 12L is a cross-sectional view showing a step subsequent to FIG. 12K.
  • FIG. 12M is a cross-sectional view showing a step subsequent to FIG. 12L.
  • FIG. 12N is a cross-sectional view showing a step subsequent to FIG. 12M.
  • FIG. 12G is a cross-sectional view showing a step subsequent to FIG. 12F.
  • FIG. 12H is a cross-sectional view showing a step subsequent to FIG. 12G.
  • FIG. 12I
  • FIG. 12O is a cross-sectional view showing a step subsequent to FIG. 12N.
  • FIG. 13 is a cross-sectional view showing a first modified example (second contact portion) of the mesa contact portion.
  • FIG. 14 is a perspective view of a mesa contact portion including the second contact portion of FIG. 15A is a diagram showing steps involved in forming the second contact portion of FIG.
  • FIG. 15B is a cross-sectional view showing a step subsequent to that of FIG. 15A.
  • FIG. 15C is a cross-sectional view showing a step subsequent to FIG. 15B.
  • FIG. 15D is a cross-sectional view showing a step subsequent to FIG. 15C.
  • FIG. 16 is a cross-sectional view showing a second modified example (third contact portion) of the mesa contact portion.
  • FIG. 17 is a perspective view of a mesa contact portion including the third contact portion of FIG.
  • FIG. 18A is a diagram showing steps involved in forming the third contact portion of FIG.
  • FIG. 18B is a cross-sectional view showing a step subsequent to that of FIG. 18A.
  • FIG. 18C is a cross-sectional view showing a step subsequent to FIG. 18B.
  • FIG. 18D is a cross-sectional view showing a step subsequent to FIG. 18C.
  • FIG. 19 is a cross-sectional view showing a fourth modified example of the mesa contact portion.
  • FIG. 20 is a cross-sectional view showing a fifth modified example of the mesa contact portion.
  • FIG. 21 is a cross-sectional view showing a sixth modified example of the mesa contact portion.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing an example layout of a first main surface 3.
  • FIG. 4 is an enlarged plan view showing a main portion of the first main surface 3.
  • FIG. 5 is an enlarged plan view showing further main portions of the first main surface 3.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5.
  • FIG. 7 is an enlarged cross-sectional view showing the main part of FIG. 6.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.
  • FIG. 9 is an enlarged cross-sectional view showing the main part of FIG. 8.
  • the semiconductor device 1 is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure.
  • the transistor structure Tr has a vertical structure.
  • the semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal.
  • the chip 2 may be referred to as a "SiC chip” or a "semiconductor chip.”
  • the chip 2 is made of hexagonal SiC single crystal and is formed into a rectangular parallelepiped shape.
  • the hexagonal SiC single crystal has a number of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • first direction X refers to the third side surface 5C side
  • second direction Y refers to the first side surface 5A side
  • second side of the second direction Y refers to the second side surface 5B side.
  • first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • first direction X may be the a-axis direction of the SiC single crystal
  • second direction Y may be the m-axis direction of the SiC single crystal.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction by the off angle.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side in the chip 2.
  • the first semiconductor region 6 may be referred to as a "drift region,” “drain drift region,” “drain region,” etc.
  • a drain potential is applied to the first semiconductor region 6 as a high potential (first potential).
  • the first semiconductor region 6 is formed in a layer extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).
  • the semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side in the chip 2. A drain potential is applied to the second semiconductor region 7.
  • the second semiconductor region 7 may be referred to as a "drain region” or the like.
  • the second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 in the chip 2.
  • the second semiconductor region 7 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC substrate).
  • the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer.
  • the second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.
  • the semiconductor device 1 includes an active region 8 set in the chip 2.
  • the active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 8 is set in the inner part of the chip 2 at a distance from the periphery (first to fourth side faces 5A to 5D) of the chip 2 in a plan view.
  • the active region 8 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the semiconductor device 1 includes a peripheral region 9 that is set outside the active region 8 in the chip 2.
  • the peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a planar view.
  • the peripheral region 9 extends in a band shape along the active region 8 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 8.
  • the semiconductor device 1 includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 in the active region 8.
  • a source potential is applied to the plurality of body regions 20 as a low potential (second potential) different from a high potential (first potential).
  • the plurality of body regions 20 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of body regions 20 are arranged in a stripe shape extending in the second direction Y.
  • the multiple body regions 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the multiple body regions 20 are formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3. The multiple body regions 20 are exposed from the first main surface 3.
  • the semiconductor device 1 includes a p-type outer body region 21 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the outer body region 21 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the outer body region 21 may be less than the p-type impurity concentration of the body region 20, or may be higher than the p-type impurity concentration of the body region 20.
  • the outer body region 21 is formed at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a band along the active region 8.
  • the outer body region 21 has a portion that extends in a band in the first direction X and a portion that extends in a band in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the outer body region 21 surrounds the active region 8 in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the outer body region 21 forms the boundary between the active region 8 and the peripheral region 9.
  • the outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the outer body region 21 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the outer body region 21 is connected to the multiple body regions 20 in a portion extending in the first direction X. As a result, the outer body region 21 is fixed to the same potential as the multiple body regions 20.
  • the outer body region 21 preferably has a width greater than the width of the body region 20.
  • the width of the body region 20 is the width in a direction perpendicular to the extension direction (i.e., the first direction X).
  • the width of the outer body region 21 is the width in a direction perpendicular to the extension direction.
  • the width of the outer body region 21 may be approximately equal to the width of the body region 20, or may be less than the thickness of the body region 20.
  • the ratio of the width of the outer body region 21 to the width of the body region 20 may be greater than or equal to 10 and less than or equal to 50. It is preferable that the width ratio be greater than or equal to 20 and less than or equal to 40.
  • the outer body region 21 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the outer body region 21 is formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.
  • the outer body region 21 has a thickness (depth) that is approximately equal to the thickness (depth) of the body region 20.
  • the thickness of the outer body region 21 may be less than the thickness of the body region 20, or may be greater than the thickness of the body region 20.
  • the semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed in the surface portion of the first main surface 3.
  • each of the surface drift regions 22 is made up of a portion of the first semiconductor region 6.
  • the surface drift regions 22 may have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6, or may have an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6.
  • the multiple surface drift regions 22 are each defined in a region between multiple adjacent body regions 20 in the first direction X. Specifically, the multiple surface drift regions 22 are each defined by multiple body regions 20 and outer body regions 21 in the surface portion of the first main surface 3. The multiple surface drift regions 22 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the multiple surface drift regions 22 are formed in a stripe shape extending in the second direction Y.
  • the semiconductor device 1 includes a plurality of n-type source regions 23, 24 formed in the surface layer of each of the body regions 20.
  • the source regions 23, 24 have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6.
  • a source potential is applied to the source regions 23, 24.
  • the multiple source regions 23, 24 include a first source region 23 located on one side of the first direction X and a second source region 24 located on the other side of the first direction X in the surface layer portion of each body region 20.
  • one first source region 23 is formed on one end side of the body region 20 in the first direction X
  • one second source region 24 is formed on the other end side of the body region 20.
  • the first source region 23 is formed at a distance from one end of the body region 20 to the other end, and extends in a band shape along the extension direction of the body region 20.
  • the first source region 23 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the first source region 23 is not formed in the outer body region 21.
  • the first source region 23 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the body region 20.
  • the second source region 24 is formed at a distance from the first source region 23 to the other end side of the body region 20.
  • the second source region 24 is formed at a distance from the other end to one end side of the body region 20, and extends in a band shape along the extension direction of the body region 20.
  • the second source region 24 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the second source region 24 is not formed in the outer body region 21.
  • the second source region 24 is formed at a distance from the bottom of the body region 20 to the first main surface 3 side, and faces the first semiconductor region 6 across a part of the body region 20.
  • each first source region 23 may be formed at intervals in the extension direction of the body region 20. In this case, each first source region 23 may be formed in a strip extending in the second direction Y.
  • the multiple second source regions 24 may be formed at intervals in the extension direction of the body region 20. In this case, each second source region 24 may be formed in a strip extending in the second direction Y.
  • the semiconductor device 1 includes a plurality of p-type contact regions 25 formed in the surface layer of each of the body regions 20 in the active region 8.
  • the contact regions 25 may be referred to as "backgate regions.”
  • a source potential is applied to the contact regions 25.
  • the contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the body regions 20.
  • one contact region 25 is interposed in the region between the first source region 23 and the second source region 24 in the surface layer portion of the corresponding body region 20.
  • the contact region 25 extends in a band shape along the extension direction of the body region 20 (source regions 23, 24).
  • the contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the contact region 25 is not formed in the outer body region 21.
  • the contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the body region 20.
  • each contact region 25 may be formed at intervals in the extension direction of the body region 20.
  • each contact region 25 may be formed in a strip shape extending in the second direction Y.
  • the semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed in a surface portion of the first main surface 3.
  • the plurality of channel regions 26, 27 are partitioned in the surface portion of the plurality of body regions 20 between the ends of the plurality of body regions 20 (the plurality of surface drift regions 22) and the peripheries of the plurality of source regions 23, 24.
  • the plurality of channel regions 26, 27 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y.
  • the plurality of channel regions 26, 27 are arranged in stripes extending in the second direction Y.
  • the multiple channel regions 26, 27 include multiple first channel regions 26 and multiple second channel regions 27.
  • the multiple first channel regions 26 are each partitioned into a region between one end of the multiple body regions 20 (surface drift region 22) and the multiple first source regions 23, forming a current path that extends horizontally.
  • the multiple second channel regions 27 are each partitioned into a region between the other end of the multiple body regions 20 (surface drift region 22) and the multiple second source regions 24, forming a current path that extends horizontally.
  • the semiconductor device 1 includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8.
  • the plurality of gate structures 30 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y.
  • the extension direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.
  • Each gate structure 30 is disposed on at least one channel region 26, 27.
  • each gate structure 30 is disposed across one surface drift region 22 and straddles two adjacent body regions 20, covering a plurality of channel regions 26, 27.
  • each gate structure 30 is disposed across the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, covering the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.
  • the gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32.
  • the gate structure 30 does not have an insulating sidewall structure (spacer) on the side of the gate electrode 32.
  • the insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 31 has a single layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 includes a silicon oxide film made of an oxide of the chip 2.
  • the insulating film 31 covers the first main surface 3 in a film-like shape and is disposed on at least one of the channel regions 26, 27. In this embodiment, the insulating film 31 is disposed so as to cross one surface drift region 22 and straddle two adjacent body regions 20, covering the multiple channel regions 26, 27.
  • the insulating film 31 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.
  • the insulating film 31 partially covers the first source region 23 at a distance from the contact region 25, and exposes a part of the first source region 23 and the contact region 25 from the first main surface 3.
  • the insulating film 31 partially covers the second source region 24 at a distance from the contact region 25, and exposes a part of the second source region 24 and the contact region 25 from the first main surface 3.
  • the thickness of the insulating film 31 may be 10 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 may be a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.
  • the gate electrode 32 is disposed on the insulating film 31 and faces at least one of the channel regions 26, 27 across the insulating film 31.
  • a gate potential is applied to the gate electrode 32 as a control potential.
  • the gate electrode 32 controls the inversion and non-inversion of at least one of the channel regions 26, 27 in response to the gate potential.
  • the gate electrode 32 includes a conductive semiconductor polycrystal.
  • the gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved.
  • the gate electrode 32 may be referred to as a "polysilicon gate", a “poly gate”, etc.
  • the gate electrode 32 is formed in a strip shape extending in the second direction Y. In other words, the extension direction of the gate electrode 32 coincides with the off-direction of the SiC single crystal. In this embodiment, the gate electrode 32 is formed spaced inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 is disposed on the insulating film 31 so as to straddle two adjacent body regions 20 across one surface drift region 22, and faces multiple channel regions 26, 27 across the insulating film 31.
  • the gate electrode 32 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 across the insulating film 31.
  • the gate electrode 32 has an electrode surface 33, a first sidewall 34 on one side in the first direction X, and a second sidewall 35 on the other side in the first direction X.
  • the electrode surface 33 extends along the insulating film 31 (first main surface 3).
  • the electrode surface 33 may extend approximately parallel to the insulating film 31 (first main surface 3).
  • the first side wall 34 is formed at a distance from one end of the insulating film 31 to the other end in the first direction X, and extends in the vertical direction Z.
  • the second side wall 35 is formed at a distance from the other end of the insulating film 31 to the one end in the first direction X, and extends in the vertical direction Z.
  • the first sidewall 34 and the second sidewall 35 may extend perpendicularly to the insulating film 31. That is, the gate electrode 32 may be formed in a quadrangular shape (flattened rectangular shape) in cross-sectional view. The first sidewall 34 and the second sidewall 35 may be inclined obliquely toward the electrode surface 33. That is, the gate electrode 32 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in cross-sectional view.
  • the width of the gate structure 30 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the gate structure 30 is the width in a direction perpendicular to the extension direction (i.e., the first direction X).
  • the width of the gate structure 30 is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the gate structure 30 may be 0.1 ⁇ m or more and 2.0 ⁇ m or less.
  • the thickness of the gate structure 30 is preferably 0.2 ⁇ m or more and 1.0 ⁇ m or less.
  • the semiconductor device 1 includes a p-type termination region 45 formed on the first main surface 3 in the peripheral region 9.
  • the termination region 45 may also be referred to as a "well region", a “termination well region”, etc.
  • the termination region 45 may have a p-type impurity concentration approximately equal to the p-type impurity concentration of the outer body region 21.
  • the p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the outer body region 21, or may be lower than the p-type impurity concentration of the outer body region 21.
  • the termination region 45 is spaced inward from the periphery of the first main surface 3 and is formed in the region between the periphery of the first main surface 3 and the outer body region 21.
  • the termination region 45 extends in a band shape along the outer body region 21 in a plan view.
  • the termination region 45 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the terminal region 45 surrounds the outer body region 21 in a plan view and is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the terminal region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the termination region 45 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the termination region 45 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3.
  • the termination region 45 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21.
  • the thickness of the termination region 45 may be greater than the thickness of the outer body region 21, or may be less than the thickness of the outer body region 21.
  • the termination region 45 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21.
  • the termination region 45 is fixed to the same potential as the outer body region 21, and is electrically connected to the multiple body regions 20 via the outer body region 21.
  • the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21 around the entire periphery.
  • the termination region 45 (inner edge) has an overlap region 46 that overlaps the outer edge of the outer body region 21.
  • the overlap region 46 is a high-concentration region that includes the outer edge of the outer body region 21 and the inner edge of the termination region 45.
  • the overlap region 46 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the termination region 45, and has a p-type impurity concentration that is higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45.
  • the overlap region 46 extends in a band shape along the outer body region 21 in a plan view.
  • the overlap region 46 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the overlap region 46 is divided into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the width of the overlap region 46 is preferably greater than the width of the body region 20.
  • the width of the overlap region 46 may be less than or equal to the width of the body region 20.
  • the semiconductor device 1 may have a relatively high-concentration p-type well region (46) instead of the overlap region 46.
  • the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45.
  • the well region (46) may be formed in either or both of the surface layer of the outer body region 21 and the surface layer of the termination region 45.
  • the semiconductor device 1 includes at least one (preferably 2 to 20) p-type field region 47 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the number of the multiple field regions 47 is typically 3 to 8.
  • the semiconductor device 1 includes three field regions 47.
  • the multiple field regions 47 are formed in an electrically floating state and relieve the electric field in the chip 2 at the periphery of the first main surface 3.
  • the number, spacing, width, depth, p-type impurity concentration, etc. of the field regions 47 are arbitrary and can take various values depending on the electric field to be relieved.
  • the field region 47 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20 (termination region 45).
  • the p-type impurity concentration of the field region 47 may be higher than the p-type impurity concentration of the body region 20 (termination region 45), or may be lower than the p-type impurity concentration of the body region 20 (termination region 45).
  • the multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the active region 8, with a gap inward from the periphery of the first main surface 3. Specifically, the multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the outer body region 21. More specifically, the multiple field regions 47 are arranged in the region between the periphery of the first main surface 3 and the termination region 45, with a gap from the termination region 45 to the periphery side of the first main surface 3.
  • the multiple field regions 47 are formed in a band shape extending along the active region 8 (termination region 45) in a plan view.
  • Each of the multiple field regions 47 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the multiple field regions 47 are formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) surrounding the active region 8 (termination region 45) in a plan view.
  • the multiple field regions 47 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the multiple field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the multiple field regions 47 are formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3.
  • the semiconductor device 1 includes a peripheral insulating film 51 that covers the first main surface 3 in the peripheral region 9.
  • the peripheral insulating film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the peripheral insulating film 51 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 51 includes a silicon oxide film made of an oxide of the chip 2.
  • the peripheral insulating film 51 is preferably made of the same type of insulating material as the insulating film 31.
  • the peripheral insulating film 51 preferably has a thickness approximately equal to that of the insulating film 31.
  • the peripheral insulating film 51 covers the first main surface 3 in the peripheral region 9 in the form of a film.
  • the peripheral insulating film 51 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47.
  • the peripheral insulating film 51 is connected to the multiple insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 51 is formed integrally with the multiple insulating films 31, and forms one insulating film together with the multiple insulating films 31.
  • the semiconductor device 1 includes a gate wiring 52 arranged on the first main surface 3 in the peripheral region 9.
  • the semiconductor device 1 does not have an insulating sidewall structure (spacer) on the side of the gate wiring 52.
  • the gate wiring 52 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 32.
  • the gate wiring 52 is connected to the multiple gate electrodes 32 and applies a gate signal to the multiple gate electrodes 32.
  • the gate wiring 52 may be referred to as a "polysilicon gate wiring", a "poly gate wiring", a "second gate electrode”, etc.
  • the gate wiring 52 includes a conductive semiconductor polycrystal.
  • the gate wiring 52 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the gate wiring 52 has the same conductivity type as the gate electrode 32. The conductivity type of the gate wiring 52 is adjusted according to the conductivity type of the gate electrode 32.
  • the gate wiring 52 is disposed on the peripheral insulating film 51 in the peripheral region 9. Specifically, the gate wiring 52 is disposed on a portion of the peripheral insulating film 51 that covers the outer body region 21, and faces the outer body region 21 across the peripheral insulating film 51.
  • the gate wiring 52 is formed at a distance from the periphery of the first main surface 3 toward the active region 8, and extends in a strip along the active region 8.
  • the gate wiring 52 has a portion that extends in a strip in the first direction X and a portion that extends in a strip in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the gate wiring 52 surrounds the active region 8 in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the gate wiring 52 may be end-shaped or endless.
  • the gate wiring 52 extends in a strip shape (ring shape in this embodiment) along the outer body region 21 in a plan view and faces the outer body region 21 across the outer insulating film 51 over the entire area in the stacking direction.
  • the gate wiring 52 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a plan view in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the gate wiring 52 is formed narrower than the outer body region 21 in a plan view, and is disposed above the outer body region 21 at a distance from the inner and outer edges of the outer body region 21.
  • the multiple gate electrodes 32 are extended up to above the outer body region 21, and the gate wiring 52 is connected to the multiple gate electrodes 32 above the outer body region 21.
  • the width of the gate wiring 52 is preferably greater than the width of the gate wiring 52.
  • the width of the gate wiring 52 is the width in a direction perpendicular to the extension direction.
  • the width of the gate wiring 52 may be less than or equal to the width of the gate electrode 32.
  • the width of the gate wiring 52 may be greater than the width of the outer body region 21.
  • the thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32.
  • the gate wiring 52 has a wiring surface 53, a first wiring sidewall 54 on the inner edge side, and a second wiring sidewall 55 on the outer edge side.
  • the wiring surface 53 extends along the peripheral insulating film 51 (first main surface 3).
  • the wiring surface 53 may extend approximately parallel to the peripheral insulating film 51 (first main surface 3).
  • the first wiring sidewall 54 extends in the vertical direction Z on the peripheral insulating film 51, and the second wiring sidewall 55 extends in the vertical direction Z on the peripheral insulating film 51.
  • the first wiring sidewall 54 is connected to the multiple gate electrodes 32 (the first sidewall 34 and the second sidewall 35) in the portion extending in the first direction X.
  • the gate wiring 52 has multiple portions connected in a T-shape to the multiple gate electrodes 32. As a result, the gate wiring 52 is fixed to the same potential as the multiple gate electrodes 32.
  • the first wiring sidewall 54 and the second wiring sidewall 55 may extend perpendicular to the peripheral insulating film 51. That is, the gate wiring 52 may be formed in a quadrangular shape (flattened rectangular shape) in cross section. The first wiring sidewall 54 and the second wiring sidewall 55 may be inclined obliquely toward the wiring surface 53. That is, the gate wiring 52 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in cross section.
  • the semiconductor device 1 includes an insulating interlayer film 70 that covers the first main surface 3.
  • the interlayer film 70 may also be called an "interlayer insulating film,” an “intermediate insulating film,” or the like.
  • the interlayer film 70 has an insulating surface 71 that extends along the first main surface 3.
  • the interlayer film 70 collectively covers the active region 8 and the peripheral region 9 on the first main surface 3.
  • the interlayer film 70 covers the multiple gate structures 30 in the active region 8. For each gate structure 30, the interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32. In other words, the interlayer film 70 has a portion that directly covers the electrode surface 33, the first sidewall 34, and the second sidewall 35 of the gate electrode 32.
  • the interlayer film 70 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 therebetween.
  • the interlayer film 70 directly covers both the peripheral insulating film 51 and the gate wiring 52. That is, the interlayer film 70 has a portion that directly covers the wiring surface 53, the first wiring sidewall 54, and the second wiring sidewall 55 of the gate wiring 52.
  • the interlayer film 70 is continuous with the first to fourth side surfaces 5A to 5D.
  • the interlayer film 70 may be formed at a distance inward from the first to fourth side surfaces 5A to 5D, exposing the peripheral portion of the first main surface 3 (first semiconductor region 6).
  • the interlayer film 70 has a layered structure including a first oxide film 72 (first insulating film) and a second oxide film 73 (second insulating film) that are layered in this order from the first main surface 3 side.
  • the interlayer film 70 has an insulating surface 71 formed by the second oxide film 73.
  • the first oxide film 72 has a single layer structure made of a silicon oxide film with no added impurities.
  • the first oxide film 72 may be referred to as an NSG film (Nondoped Silicate Glass film).
  • the first oxide film 72 collectively covers the active region 8 and the peripheral region 9.
  • the first oxide film 72 collectively covers the multiple gate structures 30 in the active region 8.
  • the first oxide film 72 covers both the insulating film 31 and the gate electrode 32 of each gate structure 30 in a film-like manner.
  • the first oxide film 72 has a first covering portion 74, a second covering portion 75, and a third covering portion 76.
  • the first covering portion 74 extends horizontally in a film shape along the insulating film 31 (first main surface 3), and has a portion that contacts the first sidewall 34 (second sidewall 35) of the gate electrode 32.
  • the first covering portion 74 (first oxide film 72) has a thickness less than the thickness of the gate electrode 32, and covers the insulating film 31 with a gap from the height position of the electrode surface 33 of the gate electrode 32 toward the insulating film 31.
  • the second covering portion 75 is extended from the first covering portion 74 toward the electrode surface 33 in the stacking direction, and directly covers the first side wall 34 (second side wall 35) in a film-like manner.
  • the third covering portion 76 is pulled out from the second covering portion 75 toward the electrode surface 33 and extends horizontally along the electrode surface 33 in the form of a film.
  • the third covering portion 76 directly covers the entire area of the electrode surface 33 between the first side wall 34 and the second side wall 35. It is preferable that the third covering portion 76 forms an arc corner portion curved in an arc shape together with the second covering portion 75 in the portion covering the corner portion of the gate electrode 32.
  • the arc corner portion may have a center of curvature on the gate electrode 32 side.
  • the first oxide film 72 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 therebetween.
  • the first oxide film 72 covers the gate wiring 52 in the peripheral region 9.
  • the first oxide film 72 has a first wiring covering portion 77, a second wiring covering portion 78, and a third wiring covering portion 79.
  • the first wiring covering portion 77 extends horizontally in a film shape along the peripheral insulating film 51 (first main surface 3), and has a portion that contacts the first wiring sidewall 54 (second wiring sidewall 55) of the gate wiring 52.
  • the first wiring covering portion 77 (first oxide film 72) has a thickness less than the thickness of the gate wiring 52, and covers the peripheral insulating film 51 with a gap from the height position of the wiring surface 53 of the gate wiring 52 toward the peripheral insulating film 51.
  • the second wiring covering portion 78 is pulled out from the first wiring covering portion 77 toward the wiring surface 53 in the stacking direction, and directly covers the first side wall 34 (second side wall 35) in a film-like manner.
  • the third wiring covering portion 79 is pulled out from the second wiring covering portion 78 toward the wiring surface 53 and extends horizontally along the wiring surface 53 in the form of a film.
  • the third wiring covering portion 79 directly covers the entire wiring surface 53 between the first wiring sidewall 54 and the second wiring sidewall 55. It is preferable that the third wiring covering portion 79 forms an arc corner portion curved in an arc shape together with the second wiring covering portion 78 in the portion covering the corner portion of the gate wiring 52.
  • the arc corner portion may have a center of curvature on the gate wiring 52 side.
  • the second oxide film 73 may have a single layer structure made of a silicon oxide film containing phosphorus, or a multilayer structure including a silicon oxide film containing phosphorus.
  • the silicon oxide film containing phosphorus may contain boron.
  • the silicon oxide film containing phosphorus may be called a PSG film (Phosphorus Silicon Glass film).
  • the silicon oxide film containing both phosphorus and boron may be called a BPSG film (Boron Phosphorus Silicon Glass film).
  • the second oxide film 73 may have a single layer structure made of a PSG film or a BPSG film stacked on the first oxide film 72.
  • the second oxide film 73 may have a layered structure including a PSG film stacked on the first oxide film 72 and a BPSG film stacked on the PSG film.
  • the second oxide film 73 may have a layered structure including a BPSG film stacked on the first oxide film 72 and a PSG film stacked on the BPSG film.
  • the second oxide film 73 has a single layer structure made of a PSG film, as an example.
  • the second oxide film 73 covers the first oxide film 72 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 72 in between.
  • the second oxide film 73 collectively covers the multiple gate structures 30 in the active region 8 with the first oxide film 72 in between.
  • the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 72 in between.
  • the second oxide film 73 includes a first upper coating portion 80 and a second upper coating portion 81.
  • the first upper coating portion 80 covers the first coating portion 74 and the second coating portion 75 of the first oxide film 72.
  • the first upper coating portion 80 covers the insulating film 31 in the portion located above the first coating portion 74, sandwiching the first coating portion 74.
  • the first upper covering portion 80 extends in a film-like manner from above the first covering portion 74 along the second covering portion 75 in the stacking direction, and covers the first side wall 34 (second side wall 35) of the gate structure 30 with the second covering portion 75 in between.
  • the second upper covering portion 81 covers the third covering portion 76 of the first oxide film 72.
  • the second upper covering portion 81 extends horizontally in a film shape from the first upper covering portion 80 along the third covering portion 76, and covers the electrode surface 33 of the gate structure 30 with the third covering portion 76 in between.
  • the second upper covering portion 81 covers the entire electrode surface 33 with the third covering portion 76 in between the first side wall 34 and the second side wall 35. It is preferable that the second upper covering portion 81 forms an arc corner portion curved in an arc shape together with the first upper covering portion 80 in the portion covering the corner portion of the gate wiring 52.
  • the arc corner portion may have a center of curvature on the gate wiring 52 side.
  • the second oxide film 73 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 and the first oxide film 72 between them.
  • the second oxide film 73 covers the gate wiring 52 in the peripheral region 9, sandwiching the first oxide film 72 between them.
  • the second oxide film 73 includes a first upper wiring coating portion 82 and a second upper wiring coating portion 83.
  • the first upper wiring coating portion 82 covers the first wiring coating portion 77 and the second wiring coating portion 78 of the first oxide film 72.
  • the first upper wiring coating portion 82 covers the peripheral insulating film 51 in a portion located above the first wiring coating portion 77, sandwiching the first wiring coating portion 77.
  • the first upper wiring covering portion 82 extends in a film-like shape in the stacking direction from above the first wiring covering portion 77 along the second wiring covering portion 78, and covers the first wiring side wall 54 (second wiring side wall 55) with the second wiring covering portion 78 in between.
  • the second upper wiring coating portion 83 covers the third wiring coating portion 79 of the first oxide film 72.
  • the second upper wiring coating portion 83 extends in a film-like manner horizontally from the first upper wiring coating portion 82 along the third wiring coating portion 79, and covers the wiring surface 53 by sandwiching the third wiring coating portion 79.
  • the second upper wiring coating portion 83 covers the entire wiring surface 53 by sandwiching the third wiring coating portion 79 between the first wiring sidewall 54 and the second wiring sidewall 55. It is preferable that the second upper wiring coating portion 83 forms an arc corner portion curved in an arc shape together with the first upper wiring coating portion 82 in the portion covering the corner portion of the gate wiring 52.
  • the arc corner portion may have a center of curvature on the gate wiring 52 side.
  • the semiconductor device 1 includes a plurality of source openings 90 formed in the interlayer film 70 in the active region 8.
  • the plurality of source openings 90 are formed in regions to the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2).
  • the plurality of source openings 90 are formed in regions between the plurality of gate electrodes 32, respectively, and penetrate the insulating film 31 and the interlayer film 70.
  • the multiple source openings 90 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73.
  • the multiple source openings 90 have opening ends defined by arc corners of the interlayer film 70.
  • the multiple source openings 90 expose the corresponding multiple source regions 23, 24 and contact regions 25, respectively.
  • the multiple source openings 90 are formed at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. That is, the multiple source openings 90 are formed in a stripe shape extending in the second direction Y.
  • the multiple source openings 90 are formed at intervals in the second direction Y from the gate wiring 52. That is, the multiple source openings 90 are formed in a region surrounded by the multiple gate electrodes 32 and the gate wiring 52.
  • a plurality of source openings 90 may be formed in a region between two gate structures 30 adjacent in the first direction X.
  • the plurality of source openings 90 may be formed in a line in the second direction Y with a space therebetween.
  • each source opening 90 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.
  • the source opening 90 may have a width W of 0.2 ⁇ m or more and 3 ⁇ m or less.
  • the width W of the source opening 90 is preferably 0.3 ⁇ m or more and 1 ⁇ m or less.
  • the source opening 90 may have a depth D of 0.2 ⁇ m or more and 2 ⁇ m or less.
  • the depth D of the source opening 90 is preferably 0.5 ⁇ m or more and 1 ⁇ m or less.
  • the source opening 90 preferably has an aspect ratio D/W of 0.3 or more and 3 or less.
  • the aspect ratio D/W is defined by the ratio of the depth D of the source opening 90 to the width W of the source opening 90.
  • the aspect ratio D/W is preferably 0.5 or more and 2 or less. It is particularly preferable that the aspect ratio D/W is greater than 1. With this configuration, the multiple gate structures 30 are arranged at a narrow pitch.
  • the semiconductor device 1 includes at least one (in this embodiment, multiple) outer openings 92 formed in the interlayer film 70 in the peripheral region 9.
  • the multiple outer openings 92 are formed in a portion of the interlayer film 70 that covers the termination region 45.
  • the multiple outer openings 92 penetrate the interlayer film 70 and expose the termination region 45.
  • the multiple outer openings 92 are formed in a portion of the interlayer film 70 that covers the overlap region 46 of the termination region 45 and expose the overlap region 46.
  • the outer openings 92 may expose the outer body region 21 instead of or in addition to the termination region 45 (overlapping region 46).
  • the outer openings 92 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73.
  • the outer openings 92 have opening ends defined by arc corners of the interlayer film 70.
  • the multiple outer openings 92 are formed at intervals along the termination region 45 (overlap region 46) (see Figures 4 and 5).
  • the multiple outer openings 92 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple outer openings 92 may be formed in a band shape extending along the termination region 45 (overlap region 46) in a plan view.
  • the outer openings 92 may have an aspect ratio D/W (preferably greater than 1) similar to the source openings 90.
  • the semiconductor device 1 may have a single outer opening 92.
  • the single outer opening 92 may be formed in a band shape extending along the termination region 45 (overlapping region 46).
  • the single outer opening 92 may have a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y in a plan view.
  • the single outer opening 92 may be formed in a polygonal ring shape (a square ring in this embodiment) with or without ends, having four sides parallel to the periphery of the first main surface 3.
  • the single outer opening 92 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) following the termination region 45 (overlapping region 46) in a plan view (see FIG. 4).
  • the semiconductor device 1 includes a plurality of outer recesses 93 formed in the first main surface 3 in the portions exposed from the plurality of outer openings 92.
  • the semiconductor device 1 does not necessarily have to have the outer recesses 93. Therefore, a configuration that does not have the outer recesses 93 may be adopted.
  • the multiple outer recesses 93 each have a planar shape that matches the planar shape of the corresponding outer opening 92, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple outer recesses 93 are formed at intervals from the bottom of the termination region 45 (overlap region 46) toward the first main surface 3, and each exposes the termination region 45 (overlap region 46).
  • the semiconductor device 1 includes at least one (in this embodiment, multiple) gate openings 94 formed in the interlayer film 70 in the peripheral region 9.
  • the multiple gate openings 94 are formed in a portion of the interlayer film 70 that covers the gate wiring 52.
  • the multiple gate openings 94 penetrate the interlayer film 70 and expose the wiring surface 53 of the gate wiring 52.
  • the multiple gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73, and have wall surfaces defined by both the first oxide film 72 and the second oxide film 73.
  • the multiple gate openings 94 have opening ends defined by arc corners of the interlayer film 70.
  • the multiple gate openings 94 are formed at intervals along the gate wiring 52 (see Figures 4 and 5).
  • the multiple gate openings 94 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple gate openings 94 may be formed in a strip shape extending along the gate wiring 52 in a plan view.
  • the gate openings 94 may have an aspect ratio D/W (preferably greater than 1) similar to the source openings 90.
  • the semiconductor device 1 may have a single gate opening 94.
  • the single gate opening 94 may be formed in a strip shape extending along the gate wiring 52.
  • the single gate opening 94 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.
  • the single gate opening 94 may be formed in a polygonal ring shape (a square ring in this embodiment) with or without ends, having four sides parallel to the periphery of the first main surface 3.
  • the single gate opening 94 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) in a plan view following the gate wiring 52 (see FIG. 4).
  • the semiconductor device 1 includes a source pad electrode 95 disposed on the interlayer film 70.
  • the source pad electrode 95 is a terminal electrode to which a source potential is applied from the outside.
  • the source pad electrode 95 may also be referred to as a "first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” etc.
  • the source pad electrode 95 is disposed on a portion of the interlayer film 70 that covers the active region 8.
  • the source pad electrode 95 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically isolated from the multiple gate electrodes 32 by the interlayer film 70.
  • the source pad electrode 95 is electrically connected to the multiple body regions 20, the outer body region 21, the multiple source regions 23 and 24, the contact region 25, etc. via the multiple source openings 90.
  • the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98.
  • the first pad portion 96 has a relatively large planar area and forms the main body of the source pad electrode 95.
  • the first pad portion 96 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the fourth side surface 5D relative to the center of the active region 8.
  • the first pad portion 96 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 90.
  • the second pad portion 97 has a planar area less than that of the first pad portion 96, and is pulled out in a strip shape (rectangular shape) from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C.
  • the second pad portion 97 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 90.
  • the third pad portion 98 has a planar area less than that of the first pad portion 96, and is pulled out in a strip shape (rectangular shape) from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 97 in the second direction Y.
  • the third pad portion 98 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20 etc. via the multiple source openings 90.
  • the plane area of the third pad portion 98 may be approximately equal to the plane area of the second pad portion 97. Of course, the plane area of the third pad portion 98 may be greater than the plane area of the second pad portion 97, or may be less than the plane area of the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 may be used as a terminal portion for monitoring a current.
  • the source pad electrode 95 does not necessarily have to have both the second pad portion 97 and the third pad portion 98 at the same time.
  • the source pad electrode 95 may have only one of the second pad portion 97 and the third pad portion 98.
  • the source pad electrode 95 may be composed of only the first pad portion 96, and may not have the second pad portion 97 or the third pad portion 98.
  • the source pad electrode 95 includes a first underlying electrode film 100 and a first main electrode film 102.
  • the first underlying electrode film 100 may be referred to as the "source underlying electrode film,” and the first main electrode film 102 may be referred to as the "source main electrode film.”
  • the first underlying electrode film 100 forms the lower layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the interlayer film 70 in the active region 8.
  • the first underlying electrode film 100 collectively covers the region of the interlayer film 70 in which the multiple source openings 90 are formed. In other words, the first underlying electrode film 100 penetrates into the multiple source openings 90 from above the insulating surface 71.
  • the first underlying electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner.
  • the first underlying electrode film 100 defines recesses in each of the multiple source openings 90.
  • the first underlying electrode film 100 may have a portion that partially covers the gate wiring 52 with the interlayer film 70 in between.
  • the first underlying electrode film 100 may be formed spaced inward from the gate wiring 52 in a plan view.
  • the first base electrode film 100 has a layered structure including a first electrode film 103 layered on the interlayer film 70, and a second electrode film 104 layered on the first electrode film 103.
  • the first electrode film 103 includes a Ti film
  • the second electrode film 104 includes a TiN film.
  • the first base electrode film 100 does not necessarily have to have a laminated structure, and may have a single-layer structure consisting of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film).
  • the thickness of the first electrode film 103 may be 10 nm or more and 100 nm or less.
  • the thickness of the second electrode film 104 may be 50 nm or more and 200 nm or less.
  • the first electrode film 103 collectively covers the region of the interlayer film 70 in which the multiple source openings 90 are formed, and extends into the multiple source openings 90 from above the insulating surface 71.
  • the first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner.
  • the first electrode film 103 directly covers the insulating surface 71.
  • the first electrode film 103 directly covers the second oxide film 73 on the insulating surface 71.
  • the first oxide film 72 faces the multiple gate electrodes 32 across the interlayer film 70 in the portion covering the insulating surface 71.
  • the first electrode film 103 covers the arc corner of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arc corner of the interlayer film 70 (second oxide film 73), and extends into the source opening 90.
  • the first electrode film 103 has a portion that extends in an arc shape at the arc corner. This improves the film-forming property of the first electrode film 103 on the interlayer film 70 (the wall surface of the source opening 90).
  • the first electrode film 103 extends along the wall surface of the source opening 90 and covers the insulating film 31, the first oxide film 72, and the second oxide film 73.
  • the first electrode film 103 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 with the interlayer film 70 in between.
  • the first electrode film 103 covers the first main surface 3 at the bottom of each source opening 90 in a film-like manner, and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion that covers the bottom of each source opening 90 in a film-like manner, and is electrically connected to the multiple source regions 23, 24 and the contact region 25.
  • the second electrode film 104 covers the area of the interlayer film 70 on the first electrode film 103 where the multiple source openings 90 are formed.
  • the second electrode film 104 has a portion that covers the insulating surface 71 of the interlayer film 70 with the first electrode film 103 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 with the first electrode film 103 in a film-like manner.
  • the second electrode film 104 faces the multiple gate electrodes 32 across the first electrode film 103 and the interlayer film 70 in the portion covering the insulating surface 71.
  • the second electrode film 104 covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and extends into the source opening 90.
  • the second electrode film 104 has a portion that extends in an arc shape at the arc corners of the interlayer film 70. This improves the film-forming properties of the second electrode film 104 on the interlayer film 70 (the wall surface of the source opening 90).
  • the second electrode film 104 extends along the wall surface of the source opening 90, and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 in between.
  • the second electrode film 104 faces the first sidewall 34 (second sidewall 35) of the gate electrode 32 with the first electrode film 103 and the interlayer film 70 in between.
  • the second electrode film 104 has a portion that covers the bottom of each source opening 90 in a film-like manner, sandwiching the first electrode film 103 therebetween, and is electrically connected to the multiple source regions 23, 24 and the contact region 25 via the first electrode film 103.
  • the first main electrode film 102 forms the upper layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the first base electrode film 100 in a film form.
  • the first main electrode film 102 contains a conductive material different from the conductive material of the first base electrode film 100.
  • the first main electrode film 102 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first base electrode film 100.
  • the thickness of the first main electrode film 102 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the first main electrode film 102 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first main electrode film 102 is mechanically and electrically connected to the first underlying electrode film 100 in the portion covering the insulating surface 71. As a result, the first main electrode film 102 faces the multiple gate electrodes 32 with the first underlying electrode film 100 and the interlayer film 70 in between.
  • the semiconductor device 1 includes a source finger electrode 110 that is extended from the source pad electrode 95 onto the peripheral region 9.
  • the source finger electrode 110 transmits the source potential applied to the source pad electrode 95 to the peripheral region 9.
  • the source finger electrode 110 is extended from the portion of the source pad electrode 95 (first pad portion 96) on the fourth side surface 5D side onto the portion of the interlayer film 70 that covers the peripheral region 9.
  • the source finger electrodes 110 are extended to above the termination region 45 and are electrically connected to the termination region 45 via a plurality of outer openings 92. Specifically, the source finger electrodes 110 are electrically connected to the overlap region 46 of the termination region 45 via a plurality of outer openings 92.
  • the source finger electrode 110 extends in a strip shape along the termination region 45 (overlapping region 46).
  • the source finger electrode 110 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y.
  • the source finger electrode 110 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95.
  • the source finger electrode 110 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a plan view in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the source finger electrode 110 like the source pad electrode 95, includes a first underlying electrode film 100 and a first main electrode film 102.
  • the first underlying electrode film 100 forms the lower layer of the source finger electrode 110 and covers the interlayer film 70 in the peripheral region 9.
  • the first underlying electrode film 100 collectively covers the area of the interlayer film 70 where the multiple outer openings 92 are formed. In other words, the first underlying electrode film 100 extends into the multiple outer openings 92 from above the insulating surface 71.
  • the first underlying electrode film 100 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner.
  • the first underlying electrode film 100 defines recesses within each of the multiple outer openings 92.
  • the first base electrode film 100 has a layered structure including a first electrode film 103 and a second electrode film 104, similar to the source pad electrode 95.
  • the first electrode film 103 collectively covers the area of the interlayer film 70 in which the multiple outer openings 92 are formed, and penetrates into the multiple outer openings 92 from above the insulating surface 71.
  • the first electrode film 103 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner.
  • the first electrode film 103 covers the arc corner of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arc corner of the interlayer film 70 (second oxide film 73), and enters the outer opening 92.
  • the first electrode film 103 has a portion that extends in an arc shape at the arc corner. This improves the film-forming property of the first electrode film 103 on the interlayer film 70 (wall surface of the outer opening 92).
  • the first electrode film 103 extends along the wall surface of the outer opening 92, and covers the peripheral insulating film 51, the first oxide film 72, and the second oxide film 73.
  • the first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 103 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the termination region 45 (overlap region 46) within the outer recess 93.
  • the first electrode film 103 may cover the outer recess 93 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the outer recess 93.
  • the first electrode film 103 may have a portion located on the bottom side of the outer recess 93 with respect to the height position of the first main surface 3, and a portion located on the peripheral insulating film 51 side with respect to the height position of the first main surface 3.
  • the second electrode film 104 is disposed on the first electrode film 103 and covers the area of the interlayer film 70 in which the multiple outer openings 92 are formed.
  • the second electrode film 104 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner with the first electrode film 103 in between, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner with the first electrode film 103 in between.
  • the second electrode film 104 covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and enters the outer opening 92.
  • the second electrode film 104 has a portion that extends in an arc shape at the arc corners of the interlayer film 70 (second oxide film 73). This improves the film-forming properties of the second electrode film 104 on the interlayer film 70 (wall surface of the outer opening 92).
  • the second electrode film 104 extends along the wall surface of the outer opening 92 and covers the peripheral insulating film 51, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 in between.
  • the second electrode film 104 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, sandwiching the first electrode film 103 therebetween, and is electrically connected to the termination region 45 (overlap region 46) via the first electrode film 103.
  • the second electrode film 104 may have a portion that is located within the outer recess 93.
  • the entire second electrode film 104 is located above the outer recess 93.
  • the first main electrode film 102 forms the upper layer of the source finger electrode 110 and covers the first underlying electrode film 100 in a film-like manner.
  • the first main electrode film 102 is mechanically and electrically connected to the first underlying electrode film 100 in the portion covering the insulating surface 71.
  • the first main electrode film 102 is electrically connected to the termination region 45 (overlap region 46) via the first underlying electrode film 100.
  • the semiconductor device 1 includes a gate finger electrode 115 selectively routed over the interlayer film 70.
  • the gate finger electrode 115 transmits a gate potential to the gate wiring 52.
  • the gate finger electrode 115 is routed over a portion of the interlayer film 70 that covers the gate wiring 52 (i.e., over the outer peripheral region 9), and is electrically connected to the gate wiring 52 through a plurality of gate openings 94.
  • the gate finger electrode 115 is disposed in the region between the source pad electrode 95 and the source finger electrode 110 and spaced apart from the source pad electrode 95 and the source finger electrode 110.
  • the gate finger electrode 115 is disposed on the gate wiring 52 and extends in a strip shape along the gate wiring 52.
  • the gate finger electrode 115 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view.
  • the gate finger electrode 115 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95.
  • the gate finger electrode 115 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the gate finger electrode 115 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 110 passes.
  • the gate finger electrode 115 includes a second underlying electrode film 120 and a second main electrode film 122.
  • the second underlying electrode film 120 may be referred to as the "gate underlying electrode film” and the second main electrode film 122 may be referred to as the "gate main electrode film.”
  • the second underlying electrode film 120 forms a lower layer of the gate finger electrode 115, and covers the interlayer film 70 in the peripheral region 9.
  • the second underlying electrode film 120 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed. In other words, the second underlying electrode film 120 penetrates into the multiple gate openings 94 from above the insulating surface 71.
  • the second underlying electrode film 120 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner.
  • the second underlying electrode film 120 defines multiple recesses within the multiple gate openings 94.
  • the second base electrode film 120 has a layered structure including a first electrode film 123 layered on the interlayer film 70, and a second electrode film 124 layered on the first electrode film 123. It is preferable that the first electrode film 123 contains the same type of conductive material as the first electrode film 103 on the source side, and the second electrode film 124 contains the same type of conductive material as the second electrode film 104 on the source side. In this embodiment, the first electrode film 123 contains a Ti film, and the second electrode film 124 contains a TiN film.
  • the second base electrode film 120 does not necessarily have to have a laminated structure, and may have a single layer structure consisting of either the first electrode film 123 (Ti film) or the second electrode film 124 (TiN film).
  • the first electrode film 123 may have a thickness approximately equal to the thickness of the first electrode film 103 on the source side.
  • the second electrode film 124 may have a thickness approximately equal to the thickness of the second electrode film 104 on the source side.
  • the first electrode film 123 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed, and penetrates into the multiple gate openings 94 from above the insulating surface 71.
  • the first electrode film 123 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner.
  • the first electrode film 123 covers the arc corner of the interlayer film 70 (second oxide film 73) in a film-like manner, following the arc corner of the interlayer film 70 (second oxide film 73), and enters the gate opening 94.
  • the first electrode film 123 has a portion that extends in an arc shape at the arc corner. This improves the film-forming property of the first electrode film 123 on the interlayer film 70 (wall surface of the gate opening 94).
  • the first electrode film 123 extends along the wall surface of the gate opening 94, and covers the peripheral insulating film 51, the first oxide film 72, and the second oxide film 73.
  • the first electrode film 123 covers the gate wiring 52 at the bottom of each gate opening 94 in the form of a film and is electrically connected to the gate wiring 52.
  • the second electrode film 124 covers the area of the interlayer film 70 on the first electrode film 123 where the multiple gate openings 94 are formed.
  • the second electrode film 124 has a portion that covers the insulating surface 71 of the interlayer film 70 in a film-like manner with the first electrode film 123 in between, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner with the first electrode film 123 in between.
  • the second electrode film 124 covers the arc corners of the interlayer film 70 (second oxide film 73) in a film-like manner and enters the gate opening 94.
  • the second electrode film 124 has a portion that extends in an arc shape at the arc corners of the interlayer film 70 (second oxide film 73). This improves the film formability of the second electrode film 124 on the interlayer film 70 (wall surface of the gate opening 94).
  • the second electrode film 124 extends along the wall surface of the gate opening 94 and covers the peripheral insulating film 51, the first oxide film 72, and the second oxide film 73 with the first electrode film 123 in between.
  • the second electrode film 124 has a portion that covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, sandwiching the first electrode film 123 therebetween, and is electrically connected to the gate wiring 52 via the first electrode film 123.
  • the second main electrode film 122 forms the upper layer of the gate finger electrode 115 and covers the second base electrode film 120 in a film form.
  • the second main electrode film 122 contains a conductive material different from the conductive material of the second base electrode film 120.
  • the second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the second main electrode film 122 preferably includes the same type of conductive material as the conductive material of the first main electrode film 102.
  • the second main electrode film 122 may have a thickness approximately equal to that of the first main electrode film 102.
  • the second main electrode film 122 is mechanically and electrically connected to the second base electrode film 120 in the portion covering the insulating surface 71.
  • the semiconductor device 1 includes a gate pad electrode 130 disposed on the interlayer film 70.
  • the gate pad electrode 130 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate pad electrode 130 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the gate pad electrode 130 is disposed in a region between the source pad electrode 95 and the source finger electrode 110 and spaced apart from the source pad electrode 95 and the source finger electrode 110.
  • the gate pad electrode 130 is disposed in a region on the third side surface 5C side relative to the first pad portion 96, and is sandwiched between the second pad portion 97 and the third pad portion 98. In other words, the gate pad electrode 130 faces the first pad portion 96 in the first direction X, and faces the second pad portion 97 and the third pad portion 98 in the second direction Y.
  • the gate pad electrode 130 is formed in a polygonal shape (a square shape in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate pad electrode 130 has a planar area less than that of the source pad electrode 95 (first pad portion 96).
  • the gate pad electrode 130 may have a planar area less than that of the second pad portion 97 (third pad portion 98).
  • the gate pad electrode 130 is disposed on the portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 115.
  • the gate pad electrode 130 may cover multiple gate electrodes 32 with the interlayer film 70 in between, or may cover the gate wiring 52 with the interlayer film 70 in between.
  • the gate pad electrode 130 includes a second base electrode film 120 and a second main electrode film 122, similar to the gate finger electrode 115.
  • the second base electrode film 120 forms a lower layer of the gate pad electrode 130 and covers the interlayer film 70 in a film-like manner.
  • the second base electrode film 120 has a layered structure including a first electrode film 123 and a second electrode film 124, similar to the gate finger electrode 115.
  • the first electrode film 123 covers the interlayer film 70 in a film-like manner
  • the second electrode film 124 covers the first electrode film 123 in a film-like manner.
  • the second main electrode film 122 forms an upper layer of the gate pad electrode 130 and covers the second base electrode film 120 in a film-like manner.
  • the gate potential applied to the gate pad electrode 130 is applied to the gate wiring 52 via the gate finger electrode 115.
  • the gate potential is transmitted to the multiple gate electrodes 32 via a wiring path (current path) along the gate wiring 52. This causes the multiple gate electrodes 32 to be turned on, controlling the on/off of the multiple channel regions 26, 27.
  • the semiconductor device 1 includes a drain pad electrode 140 covering the second main surface 4.
  • the drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain pad electrode 140 may be referred to as a "third pad electrode,” a "third main surface electrode,” a “third terminal electrode,” etc.
  • the drain pad electrode 140 is electrically connected to the second semiconductor region 7.
  • the drain pad electrode 140 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D).
  • the drain pad electrode 140 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.
  • the breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • Figure 10 is a schematic perspective view that explains the structure of the mesa contact portion 41 in detail.
  • a portion of the chip 2 is exposed as a contact portion 40 from a source opening 90 between adjacent gate structures 30.
  • the source pad electrode 95 is mechanically and electrically connected to the contact portion 40 within the source opening 90.
  • the contact portion 40 includes a mesa contact portion 41 and a flat contact portion 42.
  • the mesa contact portions 41 are formed at a distance inward from both side walls of the source opening 90.
  • the mesa contact portions 41 extend in a stripe shape along the stripe direction of the gate structure 30.
  • one mesa contact portion 41 is formed in each of the stripe-extending source openings 90, and as a whole, multiple mesa contact portions 41 are arranged in a stripe shape.
  • Each mesa contact portion 41 protrudes from the first main surface 3 and has a mesa upper portion 43 and a mesa side portion 44.
  • the mesa upper portion 43 may extend substantially parallel to the insulating film 31 (first main surface 3).
  • the mesa upper portion 43 may be referred to as a mesa upper wall.
  • the mesa side portion 44 may include a first mesa side portion 44A facing the first sidewall 34 and a second mesa side portion 44B facing the second sidewall 35. Both the first mesa side portion 44A and the second mesa side portion 44B are formed at a distance from the sidewall of the interlayer film 70 in the first direction X and extend in the vertical direction Z. The first mesa side portion 44A and the second mesa side portion 44B may extend perpendicular to the first main surface 3. In other words, the mesa contact portion 41 may be formed in a quadrangular shape (flattened rectangular shape) in a cross-sectional view.
  • first mesa side portion 44A and the second mesa side portion 44B may be inclined obliquely toward the mesa upper portion 43.
  • the mesa contact portion 41 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in a cross-sectional view.
  • the first mesa side portion 44A and the second mesa side portion 44B may be referred to as the first mesa sidewall and the second mesa sidewall, respectively.
  • the flat contact portion 42 is a region formed by a part of the first main surface 3 between the mesa contact portion 41 and the sidewall of the source opening 90.
  • a pair of flat contact portions 42 sandwiching the band-shaped mesa contact portion 41 are formed in a stripe shape next to the mesa contact portion 41.
  • the width W1 of the mesa contact portion 41 may be wider than the width W2 of each flat contact portion 42.
  • the width W1 of the mesa contact portion 41 may be wider than the sum of the widths W2 of the pair of flat contact portions 42.
  • the width W1 of the mesa contact portion 41 may be wider than 1/2 the width W of the source opening 90.
  • the mesa contact portion 41 is formed by the body region 20, the contact region 25, and the source regions 23 and 24.
  • the mesa contact portion 41 includes these three impurity regions by partitioning the body region 20, the contact region 25, and the source regions 23 and 24 in a predetermined pattern.
  • the contact region 25 and at least one of the source regions 23, 24 are exposed from the mesa top 43 and mesa side 44 of the mesa contact portion 41 and are connected to the source pad electrode 95.
  • the mesa contact portion 41 includes an impurity region in the manner of the first contact portion 36.
  • the mesa contact portion 41 in the first contact portion 36, includes a body protrusion 37 formed by a portion of the body region 20 and passing along the side of the source regions 23, 24 toward the mesa upper portion 43, a contact region 25 connected to the body protrusion 37 in the mesa upper portion 43, and source regions 23, 24 formed around the body protrusion 37 and exposed from the mesa side portion 44.
  • the body protrusion 37 has a boundary surface 38 with the source regions 23, 24 at a position spaced inward from each of the first mesa side 44A and the second mesa side 44B. This allows the body protrusion 37 to extend in a strip shape along the strip-shaped mesa contact portion 41.
  • the upper end of the body protrusion 37 (the boundary with the contact region 25) may be less than 1/2 the height of the mesa contact portion 41. Of course, the upper end of the body protrusion 37 may be more than 1/2 the height of the mesa contact portion 41.
  • the contact region 25 is formed continuously in the mesa upper portion 43 along the length of the mesa contact portion 41, and is exposed from three directions: the mesa upper portion 43 and the pair of mesa side portions 44A, 43B. Therefore, the contact region 25 is exposed from the entire upper surface of the mesa contact portion 41.
  • the first source region 23 and the second source region 24 straddle between the mesa contact portion 41 and the gate electrode 32, and have ends on the inner side of the width direction of the mesa contact portion 41.
  • Each source region 23, 24 integrally includes a source flat portion 28 exposed from the flat contact portion 42 and protruding from the flat contact portion 42 into the inside of the mesa contact portion 41, and a source vertical portion 29 rising from the source flat portion 28 along the mesa side portion 44 and exposed from the mesa side portion 44.
  • the source regions 23, 24 are formed in a substantially L-shape in cross section.
  • the source vertical portion 29 of the first source region 23 and the source vertical portion 29 of the second source region 24 face each other with a gap in the first direction X inside the mesa contact portion 41, and a body protrusion 37 is formed between them.
  • first source region 23 and the second source region 24 are integrally exposed from the underside of the mesa contact portion 41 and the flat contact portion 42 along the stripe direction of the mesa contact portion 41.
  • the source pad electrode 95 penetrates into the contact portion 40 and covers the mesa upper portion 43 and the mesa side portion 44.
  • the source pad electrode 95 is mechanically and electrically connected to the contact region 25 at the upper side of the mesa upper portion 43 and the mesa side portion 44, and is mechanically and electrically connected to the source regions 23, 24 at the lower side of the mesa side portion 44 and the flat contact portion 42.
  • the first base electrode film 100 is embedded in the gap 39 between the mesa contact portion 41 and the interlayer film 70, and the first main electrode film 102 is embedded in a region above the mesa contact portion 41 of the source opening 90.
  • multiple gate structures 30 may be arranged with a narrow pitch. Because the distance between adjacent gate structures 30 becomes narrow, the width W of the source opening 90 for source contact becomes very small. Reducing the width W of the source opening 90 reduces the contact area of the source pad electrode 95 with the source regions 23, 24 and the contact region 25. The reduced contact area may increase the contact resistance.
  • the mesa contact portion 41 is formed in the contact portion 40, so that the source pad electrode 95 can be brought into contact with both the mesa upper portion 43 and the mesa side portion 44.
  • This makes it possible to reduce the contact resistance with the source regions 23, 24 and the contact region 25, compared to when the contact portion 40 is formed only on a flat surface. This makes it possible to meet the demand for a narrower pitch in the gate structure 30, and also to reduce the contact resistance.
  • FIG. 11 is a schematic diagram showing a wafer 150 used in the manufacture of a semiconductor device 1.
  • the wafer 150 is a base material for the chip 2 and contains a SiC single crystal.
  • the wafer 150 is formed in a flat disk shape. Of course, the wafer 150 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.
  • the first wafer main surface 151 corresponds to the first main surface 3 of the chip 2
  • the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2.
  • the first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 151 is formed by the silicon surface of the SiC single crystal
  • the second wafer main surface 152 is formed by the carbon surface of the SiC single crystal.
  • the wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has the off-direction and off-angle described above.
  • the wafer 150 has a mark 154 on the wafer side surface 153 that indicates the crystal orientation of the SiC single crystal.
  • the mark 154 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat is a cutout that is cut in a straight line in a plan view.
  • the orientation notch is a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 151 in a plan view.
  • the mark 154 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 154 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • the wafer 150 includes a first semiconductor region 6 in a region (surface layer) on the first wafer main surface 151 side.
  • the first semiconductor region 6 is formed in a layer extending along the first wafer main surface 151.
  • the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).
  • the wafer 150 includes a second semiconductor region 7 in the region (surface layer) on the second wafer main surface 152 side.
  • the second semiconductor region 7 is formed in a layer extending along the second wafer main surface 4, and is electrically connected to the first semiconductor region 6.
  • the second semiconductor region 7 is made of the wafer main body (specifically, a SiC wafer). That is, in this embodiment, the wafer 150 is made of an epitaxial wafer (so-called epiwafer) having a layered structure including the wafer main body and an epitaxial layer.
  • a plurality of device regions 155 and a plurality of cutting lines 156 are set on the wafer 150 by alignment marks or the like.
  • Each device region 155 is an area corresponding to a semiconductor device 1.
  • Each of the plurality of device regions 155 is set to have a rectangular shape in a plan view.
  • the multiple device regions 155 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 155 are each set at intervals inward from the periphery of the first wafer main surface 151 in a plan view.
  • the multiple cutting lines 156 are set in a lattice shape extending along the first direction X and the second direction Y to partition the multiple device regions 155.
  • FIGS. 12A to 12O are cross-sectional views showing a method for manufacturing a semiconductor device 1.
  • FIGS. 12A to 12O a cross section of a portion of an active region 8 of one device region 155 is shown.
  • the aforementioned wafer 150 is prepared.
  • p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of body regions 20.
  • p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming an outer body region 21.
  • n-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of source regions 23, 24.
  • p-type impurities are selectively introduced into the entire surface layer of the first wafer main surface 151 to form contact region 25.
  • a mask 167 having a predetermined layout is formed on the first wafer main surface 151 (contact region 25).
  • the mask 167 may be an organic mask (e.g., a resist mask).
  • the mask 167 covers the regions where the multiple mesa contact portions 41 are to be formed and has multiple openings 166 that expose the other regions.
  • the wafer 150 is removed by an etching method through a mask 167.
  • the etching method may be a wet etching method and/or a dry etching method, but a dry etching method is preferred.
  • the portion of the wafer 150 protected by the mask 167 remains as the mesa contact portion 41, and the other regions are formed as the flat contact portion 42.
  • a base insulating film 160 is formed to cover the first wafer main surface 151.
  • the base insulating film 160 is the base of the insulating film 31 and the peripheral insulating film 51.
  • the base insulating film 160 may be formed by a chemical vapor deposition (CVD) method or an oxidation process (e.g., a thermal oxidation process).
  • a base electrode 161 is formed on the base insulating film 160.
  • the base electrode 161 is the base of the gate electrode 32 and the gate wiring 52.
  • the base electrode 161 includes conductive polysilicon.
  • the base electrode 161 may be formed by a CVD method.
  • the base electrode 161 has a base electrode surface 162 that extends along the base insulating film 160.
  • a mask 168 having a predetermined layout is formed on the base electrode 161 (base electrode surface 162).
  • the mask 168 may be an organic mask (e.g., a resist mask).
  • the mask 168 has a number of openings 169 that expose areas other than a number of mask portions that cover areas where a number of gate electrodes 32 are to be formed.
  • the base electrode 161 is removed by an etching method via a mask 168.
  • the etching method may be a wet etching method and/or a dry etching method.
  • a plurality of gate electrodes 32 and gate wiring 52 are formed.
  • the mask 168 is removed.
  • an interlayer film 70 is formed on the first wafer main surface 151.
  • an interlayer film 70 is formed having a portion that directly covers the gate electrode 32.
  • an interlayer film 70 is formed having a portion that directly covers the gate wiring 52.
  • the interlayer film 70 has a laminated structure including a first oxide film 72 and a second oxide film 73 (see FIG. 7).
  • the first oxide film 72 includes a silicon oxide film with no added impurities.
  • the second oxide film 73 includes a silicon oxide film containing phosphorus.
  • the first oxide film 72 may be formed by a CVD method.
  • the second oxide film 73 may be formed by a CVD method.
  • a reflow step heat treatment step
  • the corners and rough surfaces of the interlayer film 70 are smoothed.
  • a mask 174 having a predetermined layout is placed on the interlayer film 70.
  • the mask 174 exposes areas where the source openings 90, the outer openings 92, and the gate openings 94 are to be formed, and covers the other areas.
  • unnecessary portions of the interlayer film 70 and the base insulating film 160 are removed by etching through a mask 174.
  • unnecessary portions of the second oxide film 73, the first oxide film 72, and the base insulating film 160 are removed in this order.
  • the etching method may be a wet etching method and/or a dry etching method. It is preferable that the etching method is an anisotropic dry etching method (e.g., RIE (Reactive Ion Etching) method).
  • a plurality of source openings 90, a plurality of outer openings 92, and a plurality of gate openings 94 are formed in the interlayer film 70.
  • the insulating film 31 and the peripheral insulating film 51 are formed.
  • the mask 174 is then removed.
  • the upper corners of the interlayer film 70 are shaped into an arc by a reflow process.
  • the reflow conditions There are no particular limitations on the reflow conditions, so long as the conditions are such that the upper corners of the interlayer film 70, which are sharp after the etching in FIG. 12L, become arc-shaped.
  • the reflow conditions may be appropriately determined depending on the film thickness and film quality of the interlayer film 70, the opening width of the source opening 90, etc.
  • the first underlying electrode film 100 and the second underlying electrode film 120 are formed on the interlayer film 70.
  • the first underlying electrode film 100 and the second underlying electrode film 120 may be formed by a sputtering method or a vapor deposition method.
  • the first main electrode film 102 and the second main electrode film 122 are formed on the first base electrode film 100 and the second base electrode film 120, respectively.
  • the first main electrode film 102 and the second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the first main electrode film 102 and the second main electrode film 122 may be formed by a sputtering method or a deposition method.
  • a drain pad electrode 140 is formed on the second wafer main surface 152.
  • the drain pad electrode 140 may be formed by sputtering or vapor deposition.
  • the wafer 150 is then cut along the intended cutting lines 156, and multiple semiconductor devices 1 are cut out. Through the steps including those described above, the semiconductor device 1 is manufactured.
  • FIG. 13 is a cross-sectional view showing a first modified example (second contact portion 50) of the mesa contact portion 41.
  • FIG. 14 is a perspective view of the mesa contact portion 41 including the second contact portion 50 of FIG. 13.
  • the mesa contact portion 41 includes an impurity region in the form of the second contact portion 50 in addition to the form of the first contact portion 36.
  • the first contact portion 36 and the second contact portion 50 are formed separately from each other along the stripe direction of the mesa contact portion 41 (the stripe direction of the gate structure 30).
  • the second contact portion 50 is formed in a strip shape in the mesa contact portion 41, and the first contact portion 36 is formed continuously with the second contact portion 50.
  • one strip-shaped second contact portion 50 and one strip-shaped first contact portion 36 are formed, and the second contact portion 50 is located at the front of the page, but the first contact portion 36 may also be located at the front of the page. Also, multiple second contact portions 50 and multiple first contact portions 36 may be arranged alternately along the stripe direction of the mesa contact portion 41.
  • the mesa contact portion 41 is formed by the source regions 23, 24 from the mesa top portion 43 throughout the thickness direction, and the source regions 23, 24 are exposed from both the mesa top portion 43 and the mesa side portion 44.
  • the first source region 23 and the second source region 24 are integrated inside the mesa contact portion 41 to form a single source region 56, which is formed throughout the mesa contact portion 41 of the second contact portion 50.
  • the source region 56 is formed continuously in the mesa top portion 43 and mesa side portion 44 along the length of the mesa contact portion 41, and is exposed from three directions, the mesa top portion 43 and the pair of mesa side portions 44A, 43B. Therefore, the source region 56 is exposed from the entire surface of the mesa contact portion 41.
  • the source pad electrode 95 can be brought into contact with the entire mesa top 43 and mesa side 44 of the mesa contact portion 41 in the second contact portion 50. This reduces the contact area with the source regions 23, 24, and reduces the contact resistance.
  • FIGS. 15A to 15D are diagrams showing the steps involved in forming the second contact portion 50 in FIG. 13.
  • the second contact portion 50 can be formed in parallel with the first contact portion 36 described above.
  • p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of body regions 20. Also, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming an outer body region 21. Also, n-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of source regions 56.
  • the region in which the second contact portion 50 is to be formed is covered and protected by a mask 165. This prevents the introduction of p-type impurities into the second contact portion 50.
  • a mask 167 having a predetermined layout is formed on the first wafer main surface 151 (contact regions 25 and source regions 56).
  • the mask 167 may be an organic mask (e.g., a resist mask).
  • the mask 167 covers the regions where the multiple mesa contact portions 41 are to be formed and has multiple openings 166 that expose the other regions.
  • the wafer 150 is removed by an etching method through a mask 167.
  • the etching method may be a wet etching method and/or a dry etching method, but a dry etching method is preferred.
  • the portions of the wafer 150 protected by the mask 167 remain as the mesa contact portion 41 (the first contact portion 36 and the second contact portion 50), and the other regions are formed as the flat contact portion 42.
  • FIG. 16 is a cross-sectional view showing a second modified example (third contact portion 84) of the mesa contact portion 41.
  • FIG. 17 is a perspective view of the mesa contact portion 41 including the third contact portion 84 of FIG. 16.
  • the mesa contact portion 41 includes an impurity region in the form of a third contact portion 84 in addition to the form of the second contact portion 50.
  • the second contact portion 50 and the third contact portion 84 are formed separately from each other along the stripe direction of the mesa contact portion 41 (the stripe direction of the gate structure 30).
  • the third contact portion 84 is formed in a strip shape in the mesa contact portion 41, and the second contact portion 50 is formed continuously with the third contact portion 84.
  • one strip-shaped third contact portion 84 and one strip-shaped second contact portion 50 are formed, and the third contact portion 84 is located at the front of the page, but the second contact portion 50 may also be located at the front of the page. Also, multiple third contact portions 84 and multiple second contact portions 50 may be arranged alternately along the stripe direction of the mesa contact portion 41.
  • the mesa contact portion 41 is formed by the contact region 25 from the mesa top portion 43 throughout the thickness direction, and the contact region 25 is exposed from both the mesa top portion 43 and the mesa side portion 44.
  • the contact region 25 penetrates the first source region 23 and the second source region 24, and is connected to the body region 20 at the bottom of the mesa contact portion 41.
  • the contact region 25 integrally includes a base portion 85 formed inside the mesa contact portion 41 and an extension portion 86 extended from the base portion 85 to the flat contact portion 42.
  • the base portion 85 is formed from the mesa upper portion 43 to the base of the mesa contact portion 41 in the depth direction, and from the first mesa side portion 44A to the second mesa side portion 44B in the lateral direction.
  • the base portion 85 is formed to a position deeper than the source regions 23, 24. This exposes the contact region 25 (base portion 85) from three directions: the mesa upper portion 43 and the pair of mesa sides 44A, 43B. Therefore, the contact region 25 is exposed from the entire surface of the mesa contact portion 41.
  • the extension portions 86 of the contact region 25 are extended from the base portion 85 on both lateral sides, and have boundary surfaces 87 with the source regions 23, 24 in the flat contact portion 42.
  • the extension portions 86 are formed in a band shape along the stripe direction of the mesa contact portion 41.
  • a band-shaped extension portion 86 is formed on each lateral side of the mesa contact portion 41, and the mesa contact portion 41 is sandwiched between the pair of extension portions 86.
  • the band-shaped contact region 25 (extension portion 86) and the source regions 23, 24 are formed side by side along the stripe direction of the mesa contact portion 41.
  • the source pad electrode 95 can be brought into contact with the entire mesa upper portion 43 and mesa side portion 44 of the mesa contact portion 41 in the third contact portion 84. This allows the contact area with respect to the contact region 25 to be reduced, and the contact resistance to be reduced.
  • FIGS. 18A to 18D are diagrams showing the steps involved in forming the third contact portion 84 in FIG. 16.
  • the third contact portion 84 can be formed in parallel with the second contact portion 50 described above.
  • p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of body regions 20. Also, p-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming an outer body region 21. Also, n-type impurities are selectively introduced into the surface layer portion of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of source regions 56.
  • a mask 180 having a predetermined layout is formed on the first wafer main surface 151.
  • the mask 180 may be an organic mask (e.g., a resist mask).
  • the mask 180 has openings 181 in areas where a plurality of contact regions 25 are to be formed, and covers other areas. For example, the area where the second contact portion 50 is to be formed is entirely covered by the mask 180.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation via the mask 180, and the contact regions 25 are formed.
  • a mask 167 having a predetermined layout is formed on the first wafer main surface 151 (contact regions 25 and source regions 56).
  • the mask 167 may be an organic mask (e.g., a resist mask).
  • the mask 167 covers the regions where the multiple mesa contact portions 41 are to be formed and has multiple openings 166 that expose the other regions.
  • the wafer 150 is removed by an etching method through a mask 167.
  • the etching method may be a wet etching method and/or a dry etching method, but a dry etching method is preferred.
  • the portions of the wafer 150 protected by the mask 167 remain as the mesa contact portion 41 (the second contact portion 50 and the third contact portion 84), and the other regions are formed as the flat contact portion 42.
  • FIGS. 19 to 21 are cross-sectional views showing fourth to sixth modified examples of the mesa contact portion 41.
  • a plurality of mesa contact portions 41 may be arranged in a dot pattern at intervals along the stripe direction of the gate structure 30.
  • a second flat contact portion 48 may be formed between adjacent mesa contact portions 41.
  • the second flat contact portion 48 straddles a pair of band-shaped flat contact portions 42 that sandwich the mesa contact portion 41.
  • a source region 56 in which the source regions 23, 24 are integrated is exposed from the second flat contact portion 48.
  • a ladder-shaped source region 56 is exposed in plan view.
  • the mesa contact portions 41 arranged in a dot pattern may be unified into any one of the first contact portion 36, the second contact portion 50, and the third contact portion 84 described above, or may be a combination of each other.
  • FIG. 19 all of the mesa contact portions 41 are formed by the first contact portion 36.
  • FIG. 20 shows a combination of a mesa contact portion 41 formed by the second contact portion 50 and a mesa contact portion 41 formed by the first contact portion 36.
  • FIG. 21 shows a combination of a mesa contact portion 41 formed by the third contact portion 84 and a mesa contact portion 41 formed by the second contact portion 50.
  • the chip 2 (first semiconductor region 6 and second semiconductor region 7) containing SiC single crystal is used.
  • the chip 2 (first semiconductor region 6 and second semiconductor region 7) may contain a single crystal of a wide band gap semiconductor other than SiC single crystal.
  • a wide band gap semiconductor is a semiconductor that has a band gap larger than the band gap of silicon. Examples of single crystals of wide band gap semiconductors include gallium nitride, diamond, and gallium oxide.
  • the chip 2 (first semiconductor region 6 and second semiconductor region 7) may contain silicon single crystal.
  • an n-type second semiconductor region 7 is shown.
  • a p-type second semiconductor region 7 may be used instead of the n-type second semiconductor region 7.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.
  • the contact portion (40) includes a mesa contact portion (41) protruding from the main surface (3) and having a mesa side portion (44) and a mesa top portion (43);
  • the surface electrode (95) covers the mesa side (44) and the mesa top (43).
  • the surface electrode (95) can be in contact with both the mesa side portion (44) and the mesa top portion (43). This reduces the contact resistance to the contact portion (40) compared to when the contact portion (40) is formed only on a flat surface.
  • the gate electrode (32) is arranged on the main surface (3) at intervals,
  • the opening (90) is defined in a region between a plurality of the gate electrodes (32),
  • a plurality of the gate electrodes (32) are formed in a stripe pattern,
  • the mesa contact portion (41) is formed in a stripe shape along the stripe direction of the gate electrode (32),
  • the semiconductor device (1) according to appendix 1-2 or appendix 1-3, wherein the impurity region (23, 24) is exposed from at least the mesa side portion (44) and the flat contact portion (42) and is connected to the surface electrode (95).
  • the semiconductor device (1) described in Appendix 1-4 includes a first contact portion (40) including a body protrusion (37) formed by a part of the body region (20) and passing sideways of the impurity regions (23, 24) toward the mesa upper portion (43), a body contact region (25) of a second conductivity type connected to the body protrusion (37) in the mesa upper portion (43), and the impurity regions (23, 24) formed around the body protrusion (37) and exposed from the mesa side portion (44).
  • a first contact portion (40) including a body protrusion (37) formed by a part of the body region (20) and passing sideways of the impurity regions (23, 24) toward the mesa upper portion (43), a body contact region (25) of a second conductivity type connected to the body protrusion (37) in the mesa upper portion (43), and the impurity regions (23, 24) formed around the body protrusion (37) and exposed from the mesa side portion (44).
  • the mesa contact portion (41) is a second contact portion (50) formed by the impurity region (23, 24) from the mesa top portion (43) over the entire thickness direction, the impurity region (23, 24) being exposed from both the mesa top portion (43) and the mesa side portion (44); and a third contact portion (84) formed by a second conductivity type body contact region (25) that is formed from the mesa upper portion (43) throughout the entire thickness direction, is connected to the body region (20) at a lower portion of the mesa contact portion (41), and is exposed from both the mesa upper portion (43) and the mesa side portion (44).
  • a plurality of the gate electrodes (32) are formed in a stripe pattern, A plurality of the mesa contact portions (41) are arranged at intervals along the stripe direction of the gate electrode (32), A pair of the flat contact portions (42) sandwiching the mesa contact portion (41) are formed in a stripe shape next to the mesa contact portion (41),
  • the semiconductor device (1) according to appendix 1-2, wherein the contact portion (40) further includes a second flat contact portion (48) formed between adjacent ones of the plurality of mesa contact portions (41).
  • the semiconductor device (1) described in Appendix 1-11 includes a first contact portion (40) including a body protrusion (37) formed by a part of the body region (20) and passing sideways of the impurity regions (23, 24) toward the mesa upper portion (43), a body contact region (25) of a second conductivity type connected to the body protrusion (37) in the mesa upper portion (43), and the impurity regions (23, 24) formed around the body protrusion (37) and exposed from the mesa side portion (44).
  • a first contact portion (40) including a body protrusion (37) formed by a part of the body region (20) and passing sideways of the impurity regions (23, 24) toward the mesa upper portion (43), a body contact region (25) of a second conductivity type connected to the body protrusion (37) in the mesa upper portion (43), and the impurity regions (23, 24) formed around the body protrusion (37) and exposed from the mesa side portion (44).
  • the mesa contact portion (41) is a second contact portion (50) formed by the impurity region (23, 24) from the mesa top portion (43) over the entire thickness direction, the impurity region (23, 24) being exposed from both the mesa top portion (43) and the mesa side portion (44); and a third contact portion (84) formed by a second conductivity type body contact region (25) that is formed from the mesa upper portion (43) throughout the entire thickness direction, is connected to the body region (20) at a lower portion of the mesa contact portion (41), and is exposed from both the mesa upper portion (43) and the mesa side portion (44).

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  • Electrodes Of Semiconductors (AREA)
PCT/JP2024/007836 2023-03-28 2024-03-01 半導体装置 Ceased WO2024202942A1 (ja)

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CN202480020269.8A CN120937524A (zh) 2023-03-28 2024-03-01 半导体装置
US19/329,885 US20260020303A1 (en) 2023-03-28 2025-09-16 Semiconductor device

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005045123A (ja) * 2003-07-24 2005-02-17 Toyota Motor Corp トレンチゲート型半導体装置およびその製造方法
JP2013239489A (ja) * 2012-05-11 2013-11-28 Rohm Co Ltd 半導体装置および半導体装置の製造方法
JP2015153789A (ja) * 2014-02-10 2015-08-24 トヨタ自動車株式会社 ＳｉＣ基板を利用する半導体装置とその製造方法
JP2019033283A (ja) * 2018-10-31 2019-02-28 富士電機株式会社 半導体装置
JP2022141029A (ja) * 2021-03-15 2022-09-29 株式会社デンソー スイッチングデバイスとその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005045123A (ja) * 2003-07-24 2005-02-17 Toyota Motor Corp トレンチゲート型半導体装置およびその製造方法
JP2013239489A (ja) * 2012-05-11 2013-11-28 Rohm Co Ltd 半導体装置および半導体装置の製造方法
JP2015153789A (ja) * 2014-02-10 2015-08-24 トヨタ自動車株式会社 ＳｉＣ基板を利用する半導体装置とその製造方法
JP2019033283A (ja) * 2018-10-31 2019-02-28 富士電機株式会社 半導体装置
JP2022141029A (ja) * 2021-03-15 2022-09-29 株式会社デンソー スイッチングデバイスとその製造方法

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