WO2024198047A1 - 半导体器件及其制造方法、电子设备 - Google Patents

半导体器件及其制造方法、电子设备 Download PDF

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Publication number
WO2024198047A1
WO2024198047A1 PCT/CN2023/093288 CN2023093288W WO2024198047A1 WO 2024198047 A1 WO2024198047 A1 WO 2024198047A1 CN 2023093288 W CN2023093288 W CN 2023093288W WO 2024198047 A1 WO2024198047 A1 WO 2024198047A1
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Prior art keywords
region
semiconductor device
ion implantation
trench
silicon substrate
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PCT/CN2023/093288
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English (en)
French (fr)
Inventor
李玉科
毛淑娟
王桂磊
赵超
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Beijing Superstring Academy of Memory Technology
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Beijing Superstring Academy of Memory Technology
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions

Definitions

  • the embodiments of the present disclosure relate to, but are not limited to, the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device.
  • the upper and lower regions of the silicon pillar are the source electrode and the drain electrode respectively, and the middle region is the channel.
  • the source electrode on the silicon pillar of the transistor is connected to the metal above it, and the drain electrode on the silicon pillar is in contact with the metal bit line.
  • the contact between the silicon pillar and the metal is a metal-semiconductor contact, which easily forms a Schottky barrier, resulting in relatively high contact resistance.
  • the present disclosure provides a semiconductor device, the semiconductor device comprising: at least one transistor and a bit line arranged on a substrate; the transistor comprising a silicon semiconductor column extending in a direction perpendicular to the substrate, the silicon semiconductor column comprising a first electrode region, a channel region, and a second electrode region in sequence from the top to the direction close to the substrate, the bit line being arranged between the second electrode region and the substrate and connected to the second electrode region; the silicon semiconductor column located in the second electrode region contains an impurity material doped by a self-aligned ion implantation process, the average volume density of the impurity material in the second electrode region being greater than or equal to 5e19 atoms/cubic centimeter; the self-aligned ion implantation process The process is a self-aligned low-energy ion implantation process.
  • the average volume density of the doping material in the second electrode region may be 5e19 atoms/cm3 to 5e20 atoms/cm3.
  • the silicon semiconductor pillar located in the first electrode region contains a doping material doped by a self-aligned ion implantation process; the self-aligned ion implantation process is a self-aligned low-energy ion implantation process.
  • the implantation energy of the self-aligned low-energy ion implantation process of the first electrode region and/or the second electrode region may range from 5 keV to 100 keV.
  • doping may be performed simultaneously in the first electrode region and the second electrode region through a single self-aligned low-energy ion implantation process.
  • an average volume density of the doping material in the first electrode region is greater than or equal to 5e19 atoms/cubic centimeter.
  • the average volume density of the doping material in the first electrode region may be 5e19 atoms/cubic centimeter to 5e20 atoms/cubic centimeter.
  • the semiconductor device may include a plurality of transistors distributed in an array along a first direction and a second direction on the substrate, the first direction intersecting the second direction;
  • the bit lines may extend along the first direction and be arranged at intervals in the second direction, and the second electrode regions of a row of transistors distributed along the first direction may be connected to the same bit line;
  • the transistor may further include: a gate electrode surrounding the channel region and insulated from the channel region; the semiconductor device may further include a plurality of word lines extending along the second direction, the gate electrodes of a column of transistors distributed along the second direction being connected to the same word line, and each of the gate electrodes serving as part of the word line.
  • At least the semiconductor located in the channel region of the silicon semiconductor column is a single crystal silicon semiconductor, and there are no doped ions in a region of the channel region away from the first electrode region and the second electrode region.
  • the present disclosure also provides a method for manufacturing a semiconductor device, wherein the semiconductor device comprises at least one transistor and a bit line; the transistor comprises a silicon semiconductor extending in a direction perpendicular to a silicon substrate; Conductor column;
  • the method for manufacturing the semiconductor device comprises:
  • the trench comprises a bottom wall and a side wall, and from the bottom wall of the trench to the opening direction of the trench, the silicon semiconductor column at least comprises a drain region and a channel region to be formed in sequence;
  • a self-aligned ion implantation process is used to perform low-energy ion implantation on the silicon substrate at the bottom wall of the trench, and annealing and diffusion are performed to form a doped region of the drain region to be formed at least in two adjacent silicon semiconductor pillars;
  • the average volume density of the ion-implanted doping material in the drain region is greater than or equal to 5e19 atoms/cubic centimeter.
  • the self-aligned ion implantation process may be performed before forming the bit line
  • Using a self-aligned ion implantation process to implant ions into the silicon substrate at the bottom wall of the trench, and annealing and diffusing the ions may include:
  • a self-aligned ion implantation process is used to perform low-energy ion implantation only on the silicon substrate but not on the channel region of the silicon semiconductor column, so that doping material is implanted into the silicon substrate exposed by the groove;
  • An annealing process is used to diffuse the doping material from the silicon substrate into the drain region of the transistor on both sides of the trench.
  • the process of forming the bit line may include:
  • the bit line is formed in the bit line groove.
  • the self-aligned ion implantation process may be performed after forming the bit line
  • the bit line forming process may include:
  • the bit line is formed in the bit line groove, and the bit line is exposed by the trench.
  • the self-aligned ion implantation process is used to implant ions into the silicon substrate at the bottom wall of the trench, and the annealing diffusion may include:
  • An annealing process is used to diffuse the doping material from the bit line into the drain region of the silicon semiconductor column.
  • the silicon semiconductor pillar may further include a source region, wherein the source region is located on a side of the channel region away from the silicon substrate;
  • the method for manufacturing the semiconductor device may further include: performing low-energy ion implantation in the source region by a self-aligned ion implantation process, and annealing and diffusion to form a doped region containing a doping material in the source region.
  • the source region and the drain region may be doped simultaneously by a self-aligned ion implantation process, and the doped region of the source region and the doped region of the drain region may be formed simultaneously by an annealing process.
  • the implantation depth of the doping material in the silicon substrate may be 0 to 45 nm.
  • the implantation depth of the doping material in the source region is It can be from 0 to 45 nm.
  • the process conditions of the low-energy ion implantation in the drain region and/or the source region may include: an implantation energy of 5 kev to 100 kev.
  • the process conditions of the annealing may include: an annealing temperature of 850° C. to 1100° C., and an annealing time of 5 s to 30 s.
  • An embodiment of the present disclosure further provides an electronic device, which includes the semiconductor device provided by the above embodiment of the present disclosure.
  • FIG. 1A is a schematic top view of a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG1B is a schematic diagram of a longitudinal cross-sectional structure of a local structure of the semiconductor device shown in FIG1 along the a-a′ direction;
  • FIG. 2 is a process flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure
  • FIG3 is a schematic diagram of a longitudinal cross-sectional structure in the b-b′ direction after forming a first trench in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG4 is a schematic diagram of a longitudinal cross-sectional structure in the b-b′ direction after depositing an insulating layer in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • 5A is a top view of a method for manufacturing a semiconductor device after forming a second trench according to an exemplary embodiment of the present disclosure
  • FIG5B is a schematic diagram of a longitudinal cross-section of the structure shown in FIG5A along the bb'direction;
  • FIG5C is a schematic diagram of a longitudinal cross-sectional structure of the structure shown in FIG5A along the a-a' direction;
  • FIG6 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction after depositing a sacrificial oxide layer in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG7 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction during ion implantation in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG8 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction after forming a doping region in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG9 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction after forming a bit line trench according to a method for manufacturing a semiconductor device of an exemplary embodiment of the present disclosure
  • FIG10 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction after forming a bit line in a method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG11 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction of another method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure after forming a bit line trench;
  • FIG12 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction of another method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure after forming a bit line;
  • FIG13 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction of another method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure after removing a portion of a sacrificial oxide layer;
  • FIG14 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction during ion implantation in another method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG15 is a schematic diagram of a longitudinal cross-sectional structure in the a-a′ direction after forming a doping region in another method for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure
  • FIG16 is a distribution diagram of doping materials of source/drain electrodes in the b-b' direction obtained by TCAD simulation according to an exemplary embodiment of the present disclosure
  • FIG. 17 is a doping concentration curve of a doping material of a silicon semiconductor pillar of a semiconductor device obtained according to an exemplary embodiment of the present disclosure
  • FIG18 is a doping concentration curve of the doping material of the silicon semiconductor pillar of the semiconductor device obtained in Examples 2 and 3 of the present disclosure.
  • FIG. 19 is a doping concentration curve of the doping material of the silicon semiconductor column of the semiconductor device obtained according to the embodiment of the present disclosure in the absence of backscattering and with backscattering.
  • ordinal numbers such as “first” and “second” are provided to avoid confusion among constituent elements and do not indicate any order, quantity or importance.
  • the terms “installed”, “connected”, and “connected” should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • installed should be understood in a broad sense.
  • it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements.
  • a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode.
  • a transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode.
  • a channel region refers to a region where current mainly flows.
  • the first electrode region of the silicon semiconductor column can be used as the source electrode of the transistor and the second electrode region can be used as the drain electrode of the transistor, or the first electrode region of the silicon semiconductor column can be used as the drain electrode of the transistor and the second electrode region can be used as the source electrode of the transistor.
  • the functions of the "source electrode” and the “drain electrode” are sometimes interchanged. Therefore, in the present disclosure, the "source electrode” and the “drain electrode” can be interchanged.
  • electrical connection includes the situation where components are connected together through an element having some kind of electrical function.
  • element having some kind of electrical function includes the situation where components are connected together through an element having some kind of electrical function.
  • electrical function includes not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.
  • parallel means approximately parallel or almost parallel, for example, a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, a state where the angle is greater than -5° and less than 5° is also included.
  • film and “layer” may be interchanged.
  • conductive layer may be replaced with “conductive film” in some cases.
  • insulating film may be replaced with “insulating layer” in some cases.
  • the semiconductor channel is a single crystal silicon column having a source region and a drain region at upper and lower ends and a channel region therebetween.
  • the source region and the drain region are contacted with a metal and led out of the semiconductor.
  • the drain region is connected to a bit line.
  • the bit line is a buried bit line at the bottom of the single crystal silicon.
  • the source region and the drain region are the source electrode and the drain electrode, respectively, referred to as source/drain electrodes.
  • the source/drain electrodes of the transistor can be doped with a high concentration.
  • high-energy ion implantation is used.
  • the high-energy implantation position during implantation is the top of the silicon column.
  • the high-energy doped ions pass through the channel region and enter the drain region to be formed at the bottom of the silicon column. This step forms the doped source.
  • the electrode and drain regions also affect the lattice of the silicon column channel region, affecting device performance.
  • the source electrode is at the top, and high-concentration doping of the source electrode is easy to achieve.
  • the drain electrode is at the bottom.
  • the doping material needs to diffuse from the source region through the channel region to the drain region. It can be understood that when high-concentration doping is performed, the doping material must pass through a silicon column of a certain depth to reach the drain electrode at the bottom. High-energy doping can easily cause damage to single-crystalline silicon, especially lattice damage.
  • choosing arsenic as a doping material can easily cause amorphization of single-crystalline silicon columns, resulting in device performance failure; choosing phosphorus with a smaller radius as a doping material, although the damage to silicon is relatively small, but the diffusion distance is long, it is easy to diffuse to the channel area, resulting in reduced device performance. Therefore, bottom doping of vertical transistors is difficult to achieve.
  • the implantation position is the trench region between the silicon pillars, and the doped ions are diffused by annealing to laterally enter the drain region below the channel, thereby effectively reducing or avoiding the damage to the channel and improving the doping effect.
  • At least the semiconductor located in the channel region of the silicon semiconductor column is a single crystal silicon semiconductor, and there are no doped ions in a region of the channel region away from the first electrode region and the second electrode region.
  • the implantation position is the top of the silicon column. Due to low-energy ion implantation, it is not necessary to implant the ions into the drain region. Therefore, the ion implantation into the silicon column can be controlled to a certain depth without entering the channel region. There are no doping ions mentioned above in the channel region near the center region or away from the source region and the drain region, or in other words, in the cross section of the silicon column, there are no doping ions or very few doping ions near the center region. And the semiconductor in this region is single crystal silicon with a complete lattice, not amorphous silicon.
  • An embodiment of the present disclosure provides a semiconductor device.
  • FIG1A is a schematic diagram of the top view of the semiconductor device provided by an exemplary embodiment of the present disclosure
  • FIG1B is a schematic diagram of the longitudinal cross-sectional structure of the local structure of the semiconductor device shown in FIG1 on the a-a’ cross section.
  • the semiconductor device comprises: at least one transistor 10 and a bit line 20 arranged on a substrate 1′; the transistor 10 comprises a silicon semiconductor column 30 extending in a direction perpendicular to the substrate 1′, the silicon semiconductor column 30 sequentially comprising a first electrode region 31, a channel region 32 and a second electrode region 33 along a direction from the top to a direction close to the substrate 1′, the bit line 20 being arranged between the second electrode region 33 and the substrate 1′ and connected to the second electrode region 33; the second electrode region 3 ...
  • the doping material is doped by the process, and the average volume density of the doping material in the second electrode region 33 is greater than or equal to 5e19 atoms/cubic centimeter.
  • the average volume density can be understood as the average value obtained by testing data at multiple locations.
  • the source/drain electrodes of the transistor of the semiconductor device of the embodiment of the present disclosure have a high doping concentration and can form ohmic contact with the metal layers above and below the source/drain electrodes. Therefore, the contact resistance between the source/drain electrodes of the transistor and the metal layer is small and the device performance is better.
  • the average volume density of the doping material in the second electrode region 33 may be 5e19 atoms/cm 3 to 5e20 atoms/cm 3 .
  • the implantation energy of the self-aligned low-energy ion implantation process may range from 5kev to 100kev.
  • the doping material may also be doped into the first electrode region by a self-aligned ion implantation process, for example, a self-aligned low-energy ion implantation process.
  • an average volume density of the doping material in the first electrode region is greater than or equal to 5e19 atoms/cubic centimeter.
  • doping may be performed simultaneously in the first electrode region and the second electrode region through a single self-aligned low-energy ion implantation process.
  • the average volume density of the doping material in the first electrode region may be 5e19 atoms/cubic centimeter to 5e20 atoms/cubic centimeter.
  • the semiconductor device may include a plurality of transistors 10, and the plurality of transistors 10 may be distributed in an array along a first direction and a second direction on a substrate 1’, wherein the first direction intersects with the second direction, and the first direction and the second direction may be parallel to the substrate 1’.
  • the first direction may be the a-a’ direction as shown in FIG1A
  • the second direction may be the b-b’ direction as shown in FIG1A .
  • a second trench 62 is provided between two adjacent transistors 10 in the first direction
  • a first trench 61 is provided between two adjacent transistors 10 in the second direction.
  • the bit lines 20 may extend along the first direction and be arranged at intervals in the second direction.
  • a The second electrode regions 33 of the row transistors 10 may be connected to the same bit line 20 .
  • the transistor 10 may further include a gate electrode 40 surrounding the channel region 32 and being insulated from the channel region 32 .
  • the surrounding can be understood as partial surrounding or full surrounding.
  • the surrounding can be full surrounding, that is, at least the entire side wall of the channel region 32 is surrounded by the gate electrode 40, and the cross-section of the gate electrode 40 after surrounding is a closed ring. The cross-section is intercepted along the direction perpendicular to the substrate.
  • the surrounding can be partial surrounding, that is, part of the side wall of the channel region 32 is surrounded by the gate electrode 40, and the cross-section of the gate electrode 40 after surrounding is not closed, but presents a ring shape.
  • a ring with an opening or two independent gate electrodes 40 For example, the opposite side surfaces of the channel region 32 are surrounded by the gate electrode 40, and the cross-section of the gate electrode 40 is a ring with two openings.
  • the semiconductor device may further include a plurality of word lines 50 extending along the second direction.
  • the gate electrodes 40 of a column of transistors 10 distributed along the second direction may be connected to the same word line 50 .
  • the gate electrodes 40 of a column of transistors 10 distributed along the second direction may be connected to the same word line 50 and serve as a part of the connected word line 50 .
  • the transistor may be a vertical gate-all-around (VGAA) transistor;
  • the semiconductor device may be a memory device including a transistor, such as a dynamic random access memory (DRAM), a magnetic random access memory (MRAM), etc.
  • DRAM dynamic random access memory
  • MRAM magnetic random access memory
  • the present disclosure also provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes at least one transistor and a bit line; the transistor includes a silicon semiconductor column extending in a direction perpendicular to the silicon substrate.
  • the semiconductor device provided by the above embodiment of the present disclosure can be obtained by the manufacturing method.
  • FIG. 2 is a process flow chart of a method for manufacturing a semiconductor device provided by an exemplary embodiment of the present disclosure.
  • the method for manufacturing the semiconductor device includes:
  • a silicon semiconductor column of each transistor and a trench exposing one side of the silicon semiconductor column are formed on a silicon substrate;
  • the trench comprises a bottom wall and a side wall, and a groove extending from the bottom wall of the trench to the opening of the trench is formed.
  • the silicon semiconductor column at least includes a drain region and a channel region to be formed in sequence, and the conductivity of the drain region to be formed is higher than that of the channel region;
  • a self-aligned ion implantation process is used to perform low-energy ion implantation on the silicon substrate at the bottom wall of the trench, and annealing and diffusion are performed to form a doped region of the drain region to be formed at least in two adjacent silicon semiconductor pillars;
  • the average volume density of the ion-implanted doping material in the drain region is greater than or equal to 5e19 atoms/cubic centimeter.
  • the manufacturing method of the semiconductor device of the embodiment of the present disclosure can achieve high-concentration doping of the drain region of the silicon semiconductor column by low-energy ion implantation, which can avoid damage to the silicon semiconductor column caused by high-energy implantation.
  • a directional self-aligned ion implantation process is used for ion doping, which can avoid the doping material from entering the channel region. Therefore, the performance of the manufactured semiconductor device is better and no photolithography plate is required.
  • the implantation energy of the low-energy ion implantation in the drain region may range from 5 keV to 100 keV.
  • the self-aligned ion implantation process may be performed before forming the bit line
  • Using a self-aligned ion implantation process to implant ions into the silicon substrate at the bottom wall of the trench, and annealing and diffusing the ions may include:
  • a self-aligned ion implantation process is used to perform low-energy ion implantation only on the silicon substrate but not on the channel region of the silicon semiconductor column, so that doping material is implanted into the silicon substrate exposed by the groove;
  • An annealing process is used to diffuse the doping material from the silicon substrate into the drain region of the transistor on both sides of the trench.
  • the process of forming the bit line may include:
  • the exposed silicon substrate is etched so that the trench extends into the silicon substrate and toward the bottom of the drain region, and a row of silicon semi-conductors distributed along a first direction parallel to the silicon substrate is formed.
  • a bit line groove extending along the first direction is formed below the drain region of the conductor column;
  • the bit line is formed in the bit line groove.
  • a method for manufacturing a semiconductor device may include:
  • the trench comprises a bottom wall and a side wall, and from the bottom wall of the trench to the opening direction of the trench, the silicon semiconductor column sequentially comprises a drain region and a channel region to be formed, and the conductivity of the drain region to be formed is higher than that of the channel region;
  • a self-aligned ion implantation process is used to perform low-energy ion implantation only on the silicon substrate but not on the channel region of the silicon semiconductor column, so that doping material is implanted into the silicon substrate exposed by the groove;
  • the average volume density of the ion-implanted doping material in the second electrode region is greater than or equal to 5e19 atoms/cubic centimeter.
  • the self-aligned ion implantation process may be performed after forming the bit line
  • the bit line forming process may include:
  • the bit line is formed in the bit line groove, and the bit line is exposed by the trench.
  • the self-aligned ion implantation process is used to implant ions into the silicon substrate at the bottom wall of the trench, and the annealing diffusion may include:
  • An annealing process is used to diffuse the doping material from the bit line into the drain region of the silicon semiconductor column.
  • a method for manufacturing a semiconductor device may include:
  • the trench comprises a bottom wall and a side wall, and from the bottom wall of the trench to the opening direction of the trench, the silicon semiconductor column sequentially comprises a drain region and a channel region to be formed, and the conductivity of the drain region to be formed is higher than that of the channel region;
  • bit line in the bit line groove, the bit line being exposed by the groove
  • the average volume density of the ion-implanted doping material in the second electrode region is greater than or equal to 5e19 atoms/cubic centimeter.
  • the silicon semiconductor pillar may further include a source region, wherein the source region is located on a side of the channel region away from the silicon substrate;
  • the method for manufacturing the semiconductor device may further include: performing low-energy ion implantation in the source region by a self-aligned ion implantation process, and annealing and diffusion to form a doped region containing a doping material in the source region.
  • the implantation energy of the low-energy ion implantation in the source region may range from 5 keV to 100 keV.
  • the source region and the drain region may be doped simultaneously by a self-aligned ion implantation process, and the doped region of the source region and the doped region of the drain region may be formed simultaneously by an annealing process.
  • the process conditions of the annealing may include: an annealing temperature of 850° C. to 1100° C., and an annealing time of 5 s to 30 s.
  • Deposition can adopt known processes such as sputtering, evaporation, chemical vapor deposition, etc.
  • coating can adopt known coating processes
  • etching can adopt known methods, which are not specifically limited here.
  • FIG3 is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor device manufacturing method of an exemplary embodiment of the present disclosure after forming a first groove
  • FIG4 is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor device manufacturing method of an exemplary embodiment of the present disclosure after depositing an insulating layer in the b-b'direction
  • FIG5A is a top view of a semiconductor device manufacturing method of an exemplary embodiment of the present disclosure after forming a second groove
  • FIG5B is a schematic diagram of the longitudinal cross-sectional structure of the structure shown in FIG5A in the b-b'direction
  • FIG5C is a schematic diagram of the longitudinal cross-sectional structure of the structure shown in FIG5A in the a-a'direction
  • FIG6 is a schematic diagram of the longitudinal cross-sectional structure of a semiconductor device manufacturing method of an exemplary embodiment of the present disclosure FIG.
  • FIG. 7 is a schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a semiconductor device in an exemplary embodiment of the present disclosure during ion implantation in the a-a'direction;
  • FIG. 8 is a schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a semiconductor device in an exemplary embodiment of the present disclosure after forming a doped region;
  • FIG. 9 is a schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a semiconductor device in an exemplary embodiment of the present disclosure after forming a bit line groove;
  • FIG. 10 is a schematic diagram of the longitudinal cross-sectional structure of a method for manufacturing a semiconductor device in an exemplary embodiment of the present disclosure after forming a bit line. Schematic diagram of the surface structure.
  • the method for manufacturing the semiconductor device may include:
  • S10 Provide a silicon substrate 1, deposit a mask plate on the silicon substrate 1, and form a plurality of first grooves 61 extending along a first direction and spaced apart along a second direction on the silicon substrate 1 through a composition process and an etching process, wherein the first direction and the second direction may be perpendicular to each other; the first grooves 61 expose the silicon substrate 1, and the plurality of first grooves 61 space the upper portion of the silicon substrate 1 into a plurality of semiconductor walls extending along the first direction and spaced apart along the second direction, as shown in FIG. 3 .
  • the silicon substrate may be a single crystal silicon substrate, or a silicon-on-insulator substrate, such as a silicon-on-sapphire (SOS) substrate, a silicon-on-glass (SOG) substrate, or an epitaxial layer of silicon on a base semiconductor.
  • the silicon substrate may be doped or undoped.
  • S20 Deposit an insulating layer 70 covering the first groove 61 on the silicon substrate 1, and planarize the insulating layer 70 and remove the insulating layer 70 on the top surface of the semiconductor wall by chemical mechanical polishing (CMP), as shown in FIG. 4 .
  • CMP chemical mechanical polishing
  • the insulating layer may be a silicon oxide (SiOx) layer, or a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant K ⁇ 3.9, such as any one or more of silicon nitride (SiNx), silicon oxynitride (SiON), and silicon carbide (SiC).
  • SiOx silicon oxide
  • SiNx silicon nitride
  • SiON silicon oxynitride
  • SiC silicon carbide
  • the silicon semiconductor pillars 30 sequentially include a second electrode region 33, a channel region 32 and a first electrode region 31, wherein the first electrode region 31 is a source region, and the second electrode region 33 is a drain region, as shown in FIGS. 5A to 5C; here, the longitudinal section in FIG. 5C is perpendicular to the silicon substrate and does not pass through the silicon semiconductor pillars.
  • S40 Depositing a sacrificial oxide layer 80 on the silicon substrate 1 to cover the end surface of the first electrode region 31, the bottom wall and the side wall of the second trench 62, and the side wall of the silicon semiconductor pillar 30 is also covered by the sacrificial oxide layer 80.
  • the cover is shown in Figure 6.
  • the role of the sacrificial oxide layer 80 is to prevent the energetically injected ions from damaging the crystal lattice of the single crystal silicon, etc. below during ion implantation, thereby protecting the crystal lattice.
  • a self-aligned ion implantation process is used to simultaneously perform low-energy ion implantation (implant doping) on the end surface of the first electrode region 31 and the bottom wall of the second groove 62 in a direction perpendicular to the silicon substrate 1, so that the doping material is simultaneously implanted into the silicon substrate 1 below the first electrode region 31 and the second groove 62, as shown in FIG7 .
  • low-energy ion implantation implant doping
  • the arrow in FIG7 indicates the direction of the self-aligned ion implantation, i.e., the direction perpendicular to the silicon substrate 1 (the angle between the silicon semiconductor column 30 and the silicon semiconductor column is 0°), so that ion implantation will not be performed on the channel region of the silicon semiconductor column.
  • the energy of low-energy ion implantation is 5kev to 100kev;
  • the implantation depth of the doping material in the first electrode region 31, that is, the distance between the position of the doping material in the first electrode region 31 and the top surface of the first electrode region 31 after the ion implantation is completed can be 0 to 45nm;
  • the implantation depth of the doping material in the silicon substrate 1, that is, the distance between the position of the doping material in the silicon substrate 1 and the bottom wall of the second trench 62 after the ion implantation is completed can be 0 to 45nm.
  • the solution of this embodiment uses low-energy ion implantation to achieve high-concentration doping of the first electrode region and the second electrode region of the silicon semiconductor column, which can avoid damage to the silicon semiconductor column caused by high-energy implantation.
  • a directional self-aligned ion implantation process is used for ion doping, which can avoid the doping material from entering the channel region. Therefore, the performance of the semiconductor device obtained is better and no photolithography is required.
  • the doping material may include but is not limited to any one or more of phosphorus (P) and arsenic (As); for a P-type metal-oxide-semiconductor (P Metal Oxide Semiconductor, NMOS) transistor, the doping material may include but is not limited to any one or more of boron (B) and gallium (Ga). The doping depth and doping concentration of the doping material can be adjusted according to actual needs.
  • the average volume density of the first electrode region 31 is greater than or equal to 5e19 atoms/cubic centimeter, and the average volume density of the ion-implanted doping material in the second electrode region 33 is greater than or equal to 5e19 atoms/cubic centimeter; the doping material is basically uniformly distributed in the first electrode region 31, and the doping material is basically uniformly distributed in the second electrode region 33.
  • the annealing process may be thermal annealing or spike annealing, and the ions may be activated and the ion diffusion region may be expanded by annealing.
  • the annealing temperature may be 850° C. to 1100° C., and the annealing time may be 5 s to 30 s.
  • S70 etching and removing the sacrificial oxide layer 80 on the bottom wall of the second trench 62, so that the second trench 62 exposes the silicon substrate 1; etching the exposed silicon substrate 1, so that the second trench 62 extends into the silicon substrate 1 and extends toward the bottom end of the second electrode region 33, and forming a bit line groove 21 extending along the first direction below the second electrode region 33 of a row of silicon semiconductor pillars 30 distributed along the first direction, as shown in FIG9 ;
  • the deposition of the conductive layer may include: depositing a first metal layer on the inner wall of the bit line groove 21, then performing rapid thermal annealing (RTA) to react the silicon in the silicon substrate with the first metal in the first metal layer to form a silicide of the first metal, and then using a second metal layer to fill the bit line groove 21.
  • the first metal may include but is not limited to at least one of cobalt (Co) and titanium (Ti), and the second metal may be tungsten (W) or the like.
  • the depth of the first trench 61 is greater than the depth of the second trench 62 , and two adjacent bit lines 20 may be insulated by an insulating layer deposited at the bottom of the first trench 61 .
  • Figure 11 is a schematic diagram of the longitudinal cross-sectional structure of another semiconductor device manufacturing method according to an exemplary embodiment of the present disclosure after forming a bit line groove
  • Figure 12 is a schematic diagram of the longitudinal cross-sectional structure of another semiconductor device manufacturing method according to an exemplary embodiment of the present disclosure after forming a bit line
  • Figure 13 is a schematic diagram of the longitudinal cross-sectional structure of another semiconductor device manufacturing method according to an exemplary embodiment of the present disclosure after removing part of the sacrificial oxide layer
  • Figure 14 is a schematic diagram of the longitudinal cross-sectional structure of another semiconductor device manufacturing method according to an exemplary embodiment of the present disclosure in the a-a’ direction during ion implantation
  • Figure 15 is a schematic diagram of the longitudinal cross-sectional structure of another semiconductor device manufacturing method according to an exemplary embodiment of the present disclosure after forming a doped region.
  • the method for manufacturing the semiconductor device may include:
  • Steps S10' to S40' are basically the same as steps S10 to S40 in the above embodiment, with the only difference being that in step S20', the insulating layer 70 on the top surface of the semiconductor wall is not removed during CMP, and the insulating layer 70 with a thickness of about 5nm to 10nm is retained.
  • the sacrificial oxide layer 80 on the bottom wall of the second trench 62 is etched away to expose the silicon substrate 1 in the second trench 62; the sacrificial oxide layer 80 on the side wall of the second trench 62 is used as a barrier layer to etch the exposed silicon substrate 1 to extend the second trench 62 into the silicon substrate 1 and toward the bottom end of the second electrode region 33, and a bit line groove 21 extending along the first direction is formed below the second electrode region 33 of a row of silicon semiconductor columns 30 distributed along the first direction, as shown in FIG. 11 .
  • the sacrificial oxide layer 80 on the side wall of the second groove 62 is etched and removed.
  • the sacrificial oxide layer 80 on the end surface of the first electrode region 31 of the silicon semiconductor column 30 can be removed together, and then an insulating layer 70 of a suitable material is used as the sacrificial oxide layer, as shown in FIG. 13 .
  • the sacrificial oxide layer 80 on the end surface of the first electrode region 31 of the silicon semiconductor column 30 is retained at a certain thickness.
  • the low-energy ion implantation energy is 5kev to 100kev;
  • the implantation depth of the doping material in the first electrode region 31, i.e., the distance between the position of the doping material in the first electrode region 31 and the top surface of the first electrode region 31 after the ion implantation is completed, can be 0 to 45nm;
  • the implantation depth of the doping material in the silicon substrate 1, i.e., the distance between the position of the doping material in the silicon substrate 1 and the bottom wall of the second trench 62 after the ion implantation is completed, can be 0 to 45nm.
  • methods of forming the first trench and the second trench may be independently selected from any one or more of dry etching and wet etching.
  • the bit line trench may be formed by side-etching the lower portion of the second trench using any one or more of dry etching and wet etching.
  • the method of depositing the insulating layer can be selected from any one of atomic layer deposition (ALD) and chemical vapor deposition (CVD).
  • ALD atomic layer deposition
  • CVD chemical vapor deposition
  • the method of depositing the sacrificial oxide layer may be atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the method for manufacturing the semiconductor device may further include: etching away the insulating layer and the sacrificial oxide layer on the side walls of the channel region of the silicon semiconductor column, sequentially depositing a gate insulating layer and a gate electrode surrounding the side walls of the channel region on the side walls of the channel region, and connecting the gate electrode to the word line.
  • the material of the gate insulating layer may be selected from any one or more of silicon oxide (e.g., SiO 2 ), hafnium oxide (e.g., HfO 2 ), zirconium oxide (e.g., ZrO) and aluminum oxide (e.g., Al 2 O 3 ).
  • the gate insulating layer may be a single-layer structure or a multi-layer structure, for example, it may include a two-layer structure formed of silicon oxide and hafnium oxide, wherein the silicon oxide layer is in contact with the channel region, and the hafnium oxide layer is in contact with the gate.
  • the thickness of the gate insulating layer may be set according to actual electrical requirements, for example, it may be 2 nm to 5 nm.
  • the manufacturing method of the above-mentioned semiconductor device provided in the embodiment of the present disclosure can make the average volume density of the doping material in the first electrode area 31 greater than or equal to 5e19 atoms/cubic centimeter, and the average volume density in the second electrode area 33 is greater than or equal to 5e19 atoms/cubic centimeter. Therefore, the manufacturing method of the above-mentioned semiconductor device provided in the embodiment of the present disclosure is feasible.
  • TCAD is used for simulation
  • the doping material of the channel region is As, the ion implantation energy is 60kev to 180kev, and the average volume density of the doping material in the channel region is 5e12 atoms/cm3 to 8e13 atoms/cm3; the annealing temperature is 850°C to 1100°C, and the annealing time is 5s to 30s;
  • the doping material of the source/drain electrode is As, the energy of low-energy ion implantation is 15kev to 50kev, the doping concentration is 2e14 atoms/cm3 to 3e15 atoms/cm3; the annealing temperature is 850°C to 1100°C, and the annealing time is 5s to 30s.
  • Figure 16 is a distribution diagram of the doping material of the source/drain electrode in the b-b' direction obtained by TCAD simulation according to an exemplary embodiment of the present disclosure
  • Figure 17 is a doping concentration curve of the doping material of the silicon semiconductor column of the semiconductor device obtained by an exemplary embodiment of the present disclosure, wherein the horizontal axis is the depth from the upper surface (source electrode end surface) of the silicon semiconductor column to the inside of the silicon semiconductor column.
  • the doping material of the channel region is As, the energy of ion implantation is 60kev to 180kev, and the doping concentration is 5e12 atoms/cm3 to 8e13 atoms/cm3;
  • the doping material of the source/drain electrode is As, the energy of the low-energy ion implantation is 15kev to 50kev, and the doping concentration is 2e14 atoms/cubic centimeter to 3e15 atoms/cubic centimeter.
  • the doping material of the channel region is As, the energy of ion implantation is 60kev to 180kev, and the doping concentration is 5e12 atoms/cm3 to 8e13 atoms/cm3;
  • the doping material of the source/drain electrode is P
  • the energy of the low-energy ion implantation is 5kev to 20kev
  • the doping concentration is 5e14 atoms/cubic centimeter to 5e15 atoms/cubic centimeter.
  • Examples 18 is a doping concentration curve of the doping material of the silicon semiconductor column of the semiconductor device obtained in Examples 2 and 3 of the present disclosure, wherein the horizontal axis is the depth from the upper surface (source electrode end surface) of the silicon semiconductor column to the inside of the silicon semiconductor column.
  • FIG19 is a doping concentration curve of the doping material of the silicon semiconductor column of the semiconductor device obtained in the embodiment of the present disclosure in the absence of backscattering and with backscattering, wherein the horizontal axis is the depth from the upper surface (source electrode end surface) of the silicon semiconductor column to the inside of the silicon semiconductor column. (Based on FIG19, it can be considered that the backscattering dose can be ignored).
  • the method for manufacturing a semiconductor device provided by the embodiment of the present disclosure can achieve high-concentration doping of the source/drain electrodes of the transistor, so that the doping concentration of the source/drain electrodes is much higher than the doping concentration of the channel region.
  • An embodiment of the present disclosure further provides an electronic device, which includes the semiconductor device provided by the above embodiment of the present disclosure.
  • the electronic device may be: a storage device, a smart phone, a computer, a tablet, an artificial intelligence device, a wearable device, or a mobile power supply, etc.
  • the storage device may include a memory in a computer, etc., which is not limited here.

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Abstract

一种半导体器件及其制造方法、电子设备，涉及半导体技术领域，所述半导体器件包括：设置在衬底(1')上的至少一个晶体管(10)，位线(20)；所述晶体管(10)包括沿垂直于所述衬底(1')的方向延伸的硅半导体柱(30)，所述硅半导体柱(30)沿着靠近所述衬底(1')的方向依次包括第一电极区(31)、沟道区(32)和第二电极区(33)，所述位线(20)设置在所述第二电极区(33)与所述衬底(1')之间并且与所述第二电极区(33)连接；所述第二电极区(33)含有采用自对准离子注入工艺掺杂的掺杂材料，所述掺杂材料在所述第二电极区(33)的平均体密度大于等于5e19原子个数/立方厘米。

Description

半导体器件及其制造方法、电子设备
本公开要求于2023年03月30日提交中国专利局、申请号为202310329995.5、发明名称为“半导体器件及其制造方法、电子设备”的中国专利申请的优先权，其内容应理解为通过引用的方式并入本公开中。
技术领域
本公开实施例涉及但不限于半导体技术领域，尤指一种半导体器件及其制造方法、电子设备。
背景技术
在动态随机存取存储器(Dynamic Random Access Memory，DRAM)领域，硅柱作为沟道的垂直沟道晶体管的制造工艺中，硅柱的上下两个区域分别为源电极和漏电极，中间区域为沟道，晶体管的硅柱上的源电极与其上方的金属连接，以及硅柱上的漏电极与金属位线接触，硅柱与金属之间的接触为金属-半导体接触，容易形成肖特基势垒，造成接触电阻相对较高。一般地需要在硅柱的源电极和漏电极区域进行掺杂降低与金属的接触电阻。
发明内容
以下是对本文详细描述的主题的概述。本概述并非是为了限制本公开的保护范围。
本公开实施例提供了一种半导体器件，所述半导体器件包括：设置在衬底上的至少一个晶体管，位线；所述晶体管包括沿垂直于所述衬底的方向延伸的硅半导体柱，所述硅半导体柱沿着顶端到靠近所述衬底的方向依次包括第一电极区、沟道区和第二电极区，所述位线设置在所述第二电极区与所述衬底之间并且与所述第二电极区连接；位于所述第二电极区的硅半导体柱含有采用自对准离子注入工艺掺杂的掺杂材料，所述掺杂材料在所述第二电极区的平均体密度大于等于5e19原子个数/立方厘米；所述自对准离子注入工 艺为自对准低能离子注入工艺。
在本公开的示例性实施例中，所述掺杂材料在所述第二电极区的平均体密度可以为5e19原子个数/立方厘米至5e20原子个数/立方厘米。
在本公开的示例性实施例中，位于所述第一电极区的硅半导体柱含有采用自对准离子注入工艺掺杂的掺杂材料；所述自对准离子注入工艺为自对准低能离子注入工艺。
在本公开的示例性实施例中，所述第一电极区和/或所述第二电极区的所述自对准低能离子注入工艺的注入能量范围可以为5kev至100kev。
在本公开的示例性实施例中，可以通过一次自对准低能离子注入工艺同时在所述第一电极区和第二电极区进行掺杂。
在本公开的示例性实施例中，所述掺杂材料在所述第一电极区的平均体密度大于等于5e19原子个数/立方厘米。
在本公开的示例性实施例中，所述掺杂材料在所述第一电极区的平均体密度可以为5e19原子个数/立方厘米至5e20原子个数/立方厘米。
在本公开的示例性实施例中，所述半导体器件可以包括在所述衬底上沿第一方向和第二方向阵列分布的多个晶体管，所述第一方向与所述第二方向交叉；
所述位线可以沿所述第一方向延伸且在第二方向间隔排布，沿所述第一方向分布的一行晶体管的第二电极区可以与同一条位线连接；
所述晶体管还可以包括：环绕所述沟道区并且与所述沟道区相绝缘的栅电极；所述半导体器件还可以包括多条沿所述第二方向延伸的字线，沿所述第二方向分布的一列晶体管的所述栅电极与同一条字线连接，并且各所述栅电极作为所述字线的一部分。
在本公开的示例性实施例中，所述硅半导体柱的至少位于所述沟道区的半导体为单晶硅半导体，所述沟道区的远离所述第一电极区和所述第二电极区的区域中无掺杂离子。
本公开实施例还提供一种半导体器件的制造方法，所述半导体器件包括至少一个晶体管，位线；所述晶体管包括沿垂直于硅衬底的方向延伸的硅半 导体柱；
所述半导体器件的制造方法包括：
在所述硅衬底上形成各所述晶体管的硅半导体柱和暴露所述硅半导体柱的一侧的沟槽；所述沟槽包括底壁和侧壁，从所述沟槽的底壁至所述沟槽的开口方向，所述硅半导体柱至少依次包括待形成的漏极区和沟道区；
以所述沟槽的开口为自对准窗口，采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行低能离子注入，并退火扩散，形成至少位于相邻两个硅半导体柱的所述待形成的漏极区的掺杂区；
其中，所述离子注入的掺杂材料在所述漏极区的平均体密度大于等于5e19原子个数/立方厘米。
在本公开的示例性实施例中，所述自对准离子注入工艺可以在形成所述位线之前进行；
采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行离子注入，并退火扩散可以包括：
在所述硅衬底上沉积覆盖所述沟槽的底壁和侧壁的牺牲氧化物层；
沿着垂直于所述硅衬底的方向，采用自对准离子注入工艺仅对所述硅衬底进行低能离子注入而不对所述硅半导体柱的沟道区进行低能离子注入，使掺杂材料被注入被所述沟槽露出的所述硅衬底中；
采用退火工艺使所述掺杂材料由所述硅衬底扩散进入所述沟槽两侧的所述晶体管的漏极区。
在本公开的示例性实施例中，所述位线的形成过程可以包括：
在对所述硅衬底进行离子注入之后，刻蚀去除所述沟槽的底壁上的所述牺牲氧化物层，使得所述沟槽露出所述硅衬底；
对露出的所述硅衬底进行刻蚀，使所述沟槽延伸进入所述硅衬底中并朝向所述漏极区底端延伸，在沿平行于所述硅衬底的第一方向分布的一列硅半导体柱的漏极区下方形成沿所述第一方向延伸的位线槽；
在所述位线槽中形成所述位线。
在本公开的示例性实施例中，所述自对准离子注入工艺可以在形成所述位线之后进行；
所述位线的形成过程可以包括：
在所述硅衬底上沉积覆盖所述沟槽的底壁和侧壁的牺牲氧化物层；
刻蚀去除所述沟槽的底壁上的所述牺牲氧化物层，使得所述沟槽露出所述硅衬底；
对露出的所述硅衬底进行刻蚀，使所述沟槽延伸进入所述硅衬底中并朝向所述漏极区底端延伸，在沿平行于所述硅衬底的第一方向分布的一列硅半导体柱的漏极区下方形成沿所述第一方向延伸的位线槽；
在所述位线槽中形成所述位线，所述位线被所述沟槽露出。
在本公开的示例性实施例中，采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行离子注入，并退火扩散可以包括：
沿着垂直于所述硅衬底的方向，采用自对准离子注入工艺对被所述沟槽露出的所述位线进行离子注入，使掺杂材料被注入所述位线中；
采用退火工艺使所述掺杂材料由所述位线扩散进入所述硅半导体柱的所述漏极区中。
在本公开的示例性实施例中，所述硅半导体柱还可以包括源极区，所述源极区位于所述沟道区远离所述硅衬底的一侧；
所述半导体器件的制造方法还可以包括：采用自对准离子注入工艺在所述源极区进行低能离子注入，并退火扩散，在所述源极区中形成含有掺杂材料的掺杂区。
在本公开的示例性实施例中，可以通过一次自对准离子注入工艺同时在所述源极区和所述漏极区进行掺杂，经退火工艺同时形成所述源极区的掺杂区和所述漏极区的掺杂区。
在本公开的示例性实施例中，所述掺杂材料在所述硅衬底中的注入深度可以为0至45nm。
在本公开的示例性实施例中，所述掺杂材料在所述源极区中的注入深度 可以为0至45nm。
在本公开的示例性实施例中，所述漏极区和/或所述源极区的所述低能离子注入的工艺条件可以包括：注入能量为5kev至100kev。
在本公开的示例性实施例中，所述退火的工艺条件可以包括：退火温度为850℃至1100℃，退火时间为5s至30s。
本公开实施例还提供一种电子设备，所述电子设备包括如上本公开实施例提供的所述半导体器件。
本公开的其它特征和优点将在随后的说明书中阐述，并且，部分地从说明书中变得更加清楚，或者通过实施本公开而了解。本公开的目的和优点可通过在说明书以及附图中所特别指出的结构来实现和获得。
附图说明
附图用来提供对本公开技术方案的理解，并且构成说明书的一部分，与本公开的实施例一起用于解释本公开的技术方案，并不构成对本公开技术方案的限制。
图1A为本公开示例性实施例提供的半导体器件的俯视结构示意图；
图1B为图1所示的半导体器件的局部结构在a-a’方向上的纵截面结构示意图；
图2为本公开示例性实施例提供的一种半导体器件的制造方法的工艺流程图；
图3为本公开示例性实施例的一种半导体器件的制造方法在形成第一沟槽后在b-b’方向上的纵截面结构示意图；
图4为本公开示例性实施例的一种半导体器件的制造方法在沉积绝缘层后在b-b’方向上的纵截面结构示意图；
图5A为本公开示例性实施例的一种半导体器件的制造方法在形成第二沟槽后的俯视图；
图5B为图5A所示在结构在b-b’方向上的纵截面结构示意图；
图5C为图5A所示在结构在在a-a’方向上的纵截面结构示意图；
图6为本公开示例性实施例的一种半导体器件的制造方法在沉积牺牲氧化物层后在a-a’方向上的纵截面结构示意图；
图7为本公开示例性实施例的一种半导体器件的制造方法在进行离子注入时在a-a’方向上的纵截面结构示意图；
图8为本公开示例性实施例的一种半导体器件的制造方法在形成掺杂区后在a-a’方向上的纵截面结构示意图；
图9为本公开示例性实施例的一种半导体器件的制造方法在形成位线槽后在a-a’方向上的纵截面结构示意图；
图10为本公开示例性实施例的一种半导体器件的制造方法在形成位线后在a-a’方向上的纵截面结构示意图；
图11为本公开示例性实施例的另一种半导体器件的制造方法在形成位线槽后在a-a’方向上的纵截面结构示意图；
图12为本公开示例性实施例的另一种半导体器件的制造方法在形成位线后在a-a’方向上的纵截面结构示意图；
图13为本公开示例性实施例的另一种半导体器件的制造方法在去除部分牺牲氧化物层后在a-a’方向上的纵截面结构示意图；
图14为本公开示例性实施例的另一种半导体器件的制造方法在进行离子注入时在a-a’方向上的纵截面结构示意图；
图15为本公开示例性实施例的另一种半导体器件的制造方法在形成掺杂区后在a-a’方向上的纵截面结构示意图；
图16为本公开一个示例性实施例采用TCAD模拟得到的源/漏电极的掺杂材料在b-b’方向上的分布图；
图17为本公开一个示例性实施例得到的半导体器件的硅半导体柱的掺杂材料的掺杂浓度曲线；
图18为本公开实施例2和3得到的半导体器件的硅半导体柱的掺杂材料的掺杂浓度曲线；
图19为本公开实施例得到的半导体器件的硅半导体柱的掺杂材料分别在没有反向散射和有反向散射的情况下的掺杂浓度曲线。
附图中的各标记符号的含义为：
1-硅衬底；1’-衬底；10-晶体管；20-位线；21-位线槽；30-硅半导体柱；
31-第一电极区；32-沟道区；33-第二电极区；34-掺杂区；40-栅电极；50-字线；61-第一沟槽；62-第二沟槽；70-绝缘层；80-牺牲氧化物层。
具体实施方式
为使本公开的目的、技术方案和优点更加清楚明白，下文中将结合附图对本公开的实施例进行详细说明。需要说明的是，在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互任意组合。
本公开的实施方式并不一定限定附图所示尺寸，附图中各部件的形状和大小不反映真实比例。此外，附图示意性地示出了理想的例子，本公开的实施方式不局限于附图所示的形状或数值。
本公开中的“第一”、“第二”等序数词是为了避免构成要素的混同而设置，并不表示任何顺序、数量或者重要性。
在本公开中，为了方便起见，使用“中部”、“上”、“下”、“前”、“后”、“竖直”、“水平”、“顶”、“底”、“内”、“外”等指示方位或位置关系的词句以参照附图说明构成要素的位置关系，仅是为了便于描述本说明书和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。构成要素的位置关系根据描述各构成要素的方向适当地改变。因此，不局限于在公开中说明的词句，根据情况可以适当地更换。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”应做广义理解。例如，可以是固定连接，或可拆卸连接，或一体地连接；可以是机械连接，或电连接；可以是直接相连，或通过中间件间接相连，或两个元件内部的连通。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。
在本公开中，晶体管是指至少包括栅电极、漏电极以及源电极这三个端子的元件。晶体管在漏电极(漏电极端子、漏区域或漏电极)与源电极(源电极端子、源区域或源电极)之间具有沟道区域，并且电流能够流过漏电极、沟道区域以及源电极。在本公开中，沟道区域是指电流主要流过的区域。
在本公开中，可以是硅半导体柱的第一电极区作为晶体管的源电极、第二电极区作为晶体管的漏电极，或者可以是硅半导体柱的第一电极区作为晶体管的漏电极、第二电极区作为晶体管的源电极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况等下，“源电极”及“漏电极”的功能有时互相调换。因此，在本公开中，“源电极”和“漏电极”可以互相调换。
在本公开中，“电连接”包括构成要素通过具有某种电作用的元件连接在一起的情况。“具有某种电作用的元件”只要可以进行连接的构成要素间的电信号的授受，就对其没有特别的限制。“具有某种电作用的元件”的例子不仅包括电极和布线，而且还包括晶体管等开关元件、电阻器、电感器、电容器、其它具有各种功能的元件等。
在本公开中，“平行”是指大约平行或几乎平行，比如，两条直线形成的角度为-10°以上且10°以下的状态，因此，也包括该角度为-5°以上且5°以下的状态。
在本公开中，“膜”和“层”可以相互调换。例如，有时可以将“导电层”换成“导电膜”。与此同样，有时可以将“绝缘膜”换成“绝缘层”。
在以单晶硅为半导体沟道制备垂直晶体管的实施例中，半导体沟道为单晶硅柱，该单晶硅柱上具有上下两端的源极区和漏极区以及二者之间的沟道区。一般地，所述源极区和漏极区与金属接触引出到半导体之外。比如，漏极区与位线连接。一般地，位线为埋入式位线，在单晶硅的底部。源极区和漏极区分别为源电极和漏电极，简称为源/漏电极。为了消除金属与晶体管半导体柱上源/漏电极之间的肖特基势垒，可以对晶体管源/漏电极进行高浓度掺杂。
通常，采用高能离子注入，注入时的高能注入位置为硅柱的顶部，高能掺杂离子经过沟道区进入硅柱底部的待形成的漏极区，此步骤形成掺杂的源 极区和漏极区时同时对硅柱沟道区的晶格造成影响，影响器件性能。
在制造垂直晶体管时，源电极在上部，源电极的高浓度掺杂容易实现。漏电极在底部，进行高能掺杂时掺杂材料需要从源极区穿过沟道区扩散到漏极区，可以理解为高浓度掺杂时掺杂材料要穿过一定深度的硅柱才能到达下部的漏电极，高能掺杂容易对单晶硅造成损伤，尤其是晶格损伤。比如，选择砷作为掺杂材料容易造成单晶硅硅柱的非晶化，导致器件性能失效；选择半径较小的磷作为掺杂材料，虽然对硅的损伤相对小，但扩散距离长，容易扩散到沟道区域，造成器件性能降低。因此，垂直晶体管的底部掺杂是较难实现的。
本公开，采用低能离子注入实现漏极区时，注入位置为硅柱之间的沟槽区域，通过退火扩散使掺杂离子横向进入沟道下方的漏极区。有效降低或避免对沟道破坏作用，提高掺杂效果。
在本公开的示例性实施例中，所述硅半导体柱的至少位于所述沟道区的半导体为单晶硅半导体，所述沟道区的远离所述第一电极区和所述第二电极区的区域中无掺杂离子。
采用低能离子注入实现源极区时，注入位置为硅柱顶部，因低能离子注入，不需要将离子注入到漏极区，因此，可控制离子注入硅柱一定深度而不进入沟道区。沟道区靠近中心区域或背离源极区和漏极区无上述的掺杂离子，或者说，在硅柱横截面上，靠近中心区域无掺杂离子或很少有掺杂离子。且该区域的半导体为晶格完好的单晶硅，不是非晶硅。
本公开实施例提供了一种半导体器件。
图1A为本公开示例性实施例提供的半导体器件的俯视结构示意图；图1B为图1所示的半导体器件的局部结构在a-a’截面上的纵截面结构示意图。
如图1A和图1B所示，所述半导体器件包括：设置在衬底1’上的至少一个晶体管10，位线20；晶体管10包括沿垂直于衬底1’的方向延伸的硅半导体柱30，硅半导体柱30沿着顶端到靠近衬底1’的方向依次包括第一电极区31、沟道区32和第二电极区33，位线20设置在第二电极区33与衬底1’之间并且与第二电极区33连接；第二电极区33含有采用自对准低能离子注入 工艺掺杂的掺杂材料，所述掺杂材料在第二电极区33的平均体密度大于等于5e19原子个数/立方厘米。
平均体密度可以理解为在多个位置测试数据得到的平均值。
本公开实施例的半导体器件的晶体管的源/漏电极的掺杂浓度较高，可以与源/漏电极上下的金属层形成欧姆接触，因此晶体管的源/漏电极与金属层之间的接触电阻较小，器件性能较好。
在本公开的示例性实施例中，所述掺杂材料在第二电极区33的平均体密度可以为5e19原子个数/立方厘米至5e20原子个数/立方厘米。
在本公开的示例性实施例中，所述自对准低能离子注入工艺的注入能量范围可以为5kev至100kev。
在本公开的示例性实施例中，所述掺杂材料还可以通过自对准离子注入工艺，例如，自对准低能离子注入工艺掺入所述第一电极区中。
在本公开的示例性实施例中，所述掺杂材料在所述第一电极区的平均体密度大于等于5e19原子个数/立方厘米。
在本公开的示例性实施例中，可以通过一次自对准低能离子注入工艺同时在所述第一电极区和第二电极区进行掺杂。
在本公开的示例性实施例中，所述掺杂材料在所述第一电极区的平均体密度可以为5e19原子个数/立方厘米至5e20原子个数/立方厘米。
在本公开的示例性实施例中，如图1A所示，所述半导体器件可以包括多个晶体管10，多个晶体管10在衬底1’上可以沿第一方向和第二方向阵列分布，所述第一方向与所述第二方向交叉，所述第一方向与所述第二方向可以平行于衬底1’。所述第一方向可以为如图1A所示的a-a’方向，所述第二方向可以为如图1A所示的b-b’方向。在所述第一方向上相邻的两个晶体管10之间具有第二沟槽62，在所述第二方向上相邻的两个晶体管10之间具有第一沟槽61。
在本公开的示例性实施例中，如图1A所示，位线20可以沿所述第一方向延伸且在所述第二方向间隔排布。
在本公开的示例性实施例中，如图1B所示，沿所述第一方向分布的一 行晶体管10的第二电极区33可以与同一条位线20连接。
在本公开的示例性实施例中，如图1A所示，晶体管10还可以包括：环绕沟道区32并且与沟道区32相绝缘的栅电极40。
其中，环绕可以理解为部分环绕或全部环绕。一些实施例中，所述环绕可以为全部环绕，即至少沟道区32的整个侧壁被栅电极40环绕，环绕后的栅电极40的横截面为闭合环形。所述横截面为沿着垂直于衬底的方向截取。一些实施例中，所述环绕可以为部分环绕，即沟道区32的部分侧壁被栅电极40环绕，环绕后的栅电极40的横截面不是闭合的，但是呈现环形状。比如，具有开口的环形或两个独立的栅电极40。例如，沟道区32的相对的侧表面被栅电极40环绕，此时栅电极40的横截面为具有两个开口的环形。
在本公开的示例性实施例中，如图1A所示，所述半导体器件还可以包括多条沿所述第二方向延伸的字线50。
在本公开的示例性实施例中，沿所述第二方向分布的一列晶体管10的栅电极40可以与同一条字线50连接。
在本公开的示例性实施例中，沿所述第二方向分布的一列晶体管10的栅电极40可以与同一条字线50连接，并且作为所连接的字线50的一部分。
在本公开的示例性实施例中，所述晶体管可以为垂直环栅(Vertical gate-all-around,VGAA)晶体管；所述半导体器件可以为包含晶体管的存储器件，例如，动态随机存取存储器(Dynamic Random Access Memory,DRAM)、磁性随机存取存储器(Magnetic Random Access Memory，MRAM)等。
本公开实施例还提供一种半导体器件的制造方法，所述半导体器件包括至少一个晶体管，位线；所述晶体管包括沿垂直于硅衬底的方向延伸的硅半导体柱。如上本公开实施例提供的所述半导体器件可以通过该制造方法得到。
图2为本公开示例性实施例提供的一种半导体器件的制造方法的工艺流程图。
如图2所示，所述半导体器件的制造方法包括：
在硅衬底上形成各所述晶体管的硅半导体柱和暴露所述硅半导体柱的一侧的沟槽；所述沟槽包括底壁和侧壁，从所述沟槽的底壁至所述沟槽的开口 方向，所述硅半导体柱至少依次包括待形成的漏极区和沟道区，所述待形成的漏极区的导电率高于所述沟道区；
以所述沟槽的开口为自对准窗口，采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行低能离子注入，并退火扩散，形成至少位于相邻两个硅半导体柱的所述待形成的漏极区的掺杂区；
其中，所述离子注入的掺杂材料在所述漏极区的平均体密度大于等于5e19原子个数/立方厘米。
本公开实施例的半导体器件的制造方法采用低能的离子注入即可实现对硅半导体柱的漏极区的高浓度掺杂，可以避免高能注入引起的硅半导体柱损伤，而且采用定向的自对准离子注入工艺进行离子掺杂，可以避免掺杂材料进入沟道区，因此制得的半导体器件的性能较好，而且无需光刻版。
在本公开的示例性实施例中，所述漏极区的低能离子注入的注入能量范围可以为5keV至100keV。
在本公开的示例性实施例中，所述自对准离子注入工艺可以在形成所述位线之前进行；
采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行离子注入，并退火扩散可以包括：
在所述硅衬底上沉积覆盖所述沟槽的底壁和侧壁的牺牲氧化物层；
沿着垂直于所述硅衬底的方向，采用自对准离子注入工艺仅对所述硅衬底进行低能离子注入而不对所述硅半导体柱的沟道区进行低能离子注入，使掺杂材料被注入被所述沟槽露出的所述硅衬底中；
采用退火工艺使所述掺杂材料由所述硅衬底扩散进入所述沟槽两侧的所述晶体管的漏极区。
在本公开的示例性实施例中，所述位线的形成过程可以包括：
在对所述硅衬底进行离子注入之后，刻蚀去除所述沟槽的底壁上的所述牺牲氧化物层，使得所述沟槽露出所述硅衬底；
对露出的所述硅衬底进行刻蚀，使所述沟槽延伸进入所述硅衬底中并朝向所述漏极区底端延伸，在沿平行于所述硅衬底的第一方向分布的一列硅半 导体柱的漏极区下方形成沿所述第一方向延伸的位线槽；
在所述位线槽中形成所述位线。
在本公开的示例性实施例中，所述半导体器件的制造方法可以包括：
在硅衬底上形成各所述晶体管的硅半导体柱和暴露所述硅半导体柱的一侧的沟槽；所述沟槽包括底壁和侧壁，从所述沟槽的底壁至所述沟槽的开口方向，所述硅半导体柱依次包括待形成的漏极区和沟道区，所述待形成的漏极区的导电率高于所述沟道区；
在所述硅衬底上沉积覆盖所述沟槽的底壁和侧壁的牺牲氧化物层；
沿着垂直于所述硅衬底的方向，采用自对准离子注入工艺仅对所述硅衬底进行低能离子注入而不对所述硅半导体柱的沟道区进行低能离子注入，使掺杂材料被注入被所述沟槽露出的所述硅衬底中；
采用退火工艺使所述掺杂材料由所述硅衬底扩散进入所述沟槽两侧的所述晶体管的漏极区；
刻蚀去除所述沟槽的底壁上的所述牺牲氧化物层，使得所述沟槽露出所述硅衬底；
对露出的所述硅衬底进行刻蚀，使所述沟槽延伸进入所述硅衬底中并朝向所述漏极区底端延伸，在沿平行于所述硅衬底的第一方向分布的一列硅半导体柱的漏极区下方形成沿所述第一方向延伸的位线槽；
在所述位线槽中形成所述位线；
其中，离子注入的掺杂材料在第二电极区的平均体密度大于等于5e19原子个数/立方厘米。
在本公开的示例性实施例中，所述自对准离子注入工艺可以在形成所述位线之后进行；
所述位线的形成过程可以包括：
在所述硅衬底上沉积覆盖所述沟槽的底壁和侧壁的牺牲氧化物层；
刻蚀去除所述沟槽的底壁上的所述牺牲氧化物层，使得所述沟槽露出所述硅衬底；
对露出的所述硅衬底进行刻蚀，使所述沟槽延伸进入所述硅衬底中并朝向所述漏极区底端延伸，在沿平行于所述硅衬底的第一方向分布的一列硅半导体柱的漏极区下方形成沿所述第一方向延伸的位线槽；
在所述位线槽中形成所述位线，所述位线被所述沟槽露出。
在本公开的示例性实施例中，采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行离子注入，并退火扩散可以包括：
沿着垂直于所述硅衬底的方向，采用自对准离子注入工艺对被所述沟槽露出的所述位线进行离子注入，使掺杂材料被注入所述位线中；
采用退火工艺使所述掺杂材料由所述位线扩散进入所述硅半导体柱的所述漏极区中。
在本公开的示例性实施例中，所述半导体器件的制造方法可以包括：
在硅衬底上形成各所述晶体管的硅半导体柱和暴露所述硅半导体柱的一侧的沟槽；所述沟槽包括底壁和侧壁，从所述沟槽的底壁至所述沟槽的开口方向，所述硅半导体柱依次包括待形成的漏极区和沟道区，所述待形成的漏极区的导电率高于所述沟道区；
在所述硅衬底上沉积覆盖所述沟槽的底壁和侧壁的牺牲氧化物层；
刻蚀去除所述沟槽的底壁上的所述牺牲氧化物层，使得所述沟槽露出所述硅衬底；
对露出的所述硅衬底进行刻蚀，使所述沟槽延伸进入所述硅衬底中并朝向所述漏极区底端延伸，在沿平行于所述硅衬底的第一方向分布的一列硅半导体柱的漏极区下方形成沿所述第一方向延伸的位线槽；
在所述位线槽中形成所述位线，所述位线被所述沟槽露出；
沿着垂直于所述硅衬底的方向，采用自对准离子注入工艺对被所述沟槽露出的所述位线进行离子注入，使掺杂材料被注入所述位线中；
采用退火工艺使所述掺杂材料由所述位线扩散进入所述硅半导体柱的所述漏极区中；
其中，离子注入的掺杂材料在所述第二电极区的平均体密度大于等于 5e19原子个数/立方厘米。
在本公开的示例性实施例中，所述硅半导体柱还可以包括源极区，所述源极区位于所述沟道区远离所述硅衬底的一侧；
所述半导体器件的制造方法还可以包括：采用自对准离子注入工艺在所述源极区进行低能离子注入，并退火扩散，在所述源极区中形成含有掺杂材料的掺杂区。
在本公开的示例性实施例中，所述源极区的低能离子注入的注入能量范围可以为5keV至100keV。
在本公开的示例性实施例中，可以通过一次自对准离子注入工艺同时在所述源极区和所述漏极区进行掺杂，经退火工艺同时形成所述源极区的掺杂区和所述漏极区的掺杂区。
在本公开的示例性实施例中，所述退火的工艺条件可以包括：退火温度为850℃至1100℃，退火时间为5s至30s。
下面通过本实施例半导体器件的制造过程进一步说明本实施例的技术方案。沉积可采用溅射、蒸镀、化学气相沉积等已知工艺，涂覆可采用已知的涂覆工艺，刻蚀可采用已知的方法，在此不做具体的限定。
图3为本公开示例性实施例的一种半导体器件的制造方法在形成第一沟槽后在b-b’方向上的纵截面结构示意图；图4为本公开示例性实施例的一种半导体器件的制造方法在沉积绝缘层后在b-b’方向上的纵截面结构示意图；图5A为本公开示例性实施例的一种半导体器件的制造方法在形成第二沟槽后的俯视图；图5B为图5A所示在结构在b-b’方向上的纵截面结构示意图；图5C为图5A所示在结构在在a-a’方向上的纵截面结构示意图；图6为本公开示例性实施例的一种半导体器件的制造方法在沉积牺牲氧化物层后在a-a’方向上的纵截面结构示意图；图7为本公开示例性实施例的一种半导体器件的制造方法在进行离子注入时在a-a’方向上的纵截面结构示意图；图8为本公开示例性实施例的一种半导体器件的制造方法在形成掺杂区后在a-a’方向上的纵截面结构示意图；图9为本公开示例性实施例的一种半导体器件的制造方法在形成位线槽后在a-a’方向上的纵截面结构示意图；图10为本公开示例性实施例的一种半导体器件的制造方法在形成位线后在a-a’方向上的纵截 面结构示意图。
如图3至图10所示，在本公开的一个示例性实施例中，所述半导体器件的制造方法可以包括：
S10：提供硅衬底1，在硅衬底1上沉积掩膜板，通过构图工艺和刻蚀工艺在硅衬底1上形成沿第一方向延伸并沿第二方向间隔分布的多个第一沟槽61，所述第一方向与所述第二方向可以相互垂直；第一沟槽61露出硅衬底1，多个第一沟槽61将硅衬底1上部间隔为沿所述第一方向延伸并沿所述第二方向间隔分布的多个半导体壁，如图3所示。
示例性地，所述硅衬底可以为单晶硅衬底，还可以为绝缘体上硅衬底，例如，蓝宝石上硅(Silicon On Sapphire,SOS)衬底、玻璃上硅(Silicon On Glass,SOG)衬底，基底半导体基础上的硅的外延层。所述硅衬底可经掺杂或可未经掺杂。
S20：在硅衬底1上沉积覆盖第一沟槽61的绝缘层70，并通过化学机械抛光(Chemical Mechanical Polishing,CMP)对绝缘层70进行平坦化并去除半导体壁顶面上的绝缘层70，如图4所示。
示例性地，所述绝缘层可以是硅氧化物(SiOx)层，还可以是low-K介质层，即介电常数K<3.9的介质层。比如可以是硅氮化物(SiNx)和氮氧化硅(SiON)、碳化硅(SiC)中的任意一种或多种。
S30：在硅衬底1上刻蚀形成沿第二方向延伸并沿第一方向间隔分布的多个第二沟槽62；多个第二沟槽62将硅衬底1上部间隔为沿所述第一方向和所述第二方向间隔并阵列分布的多个硅半导体柱30，第二沟槽62露出硅衬底1和硅半导体柱30的侧壁；第二沟槽62包括底壁和侧壁，从第二沟槽62的底壁至第二沟槽62的开口方向，硅半导体柱30依次包括第二电极区33、沟道区32和第一电极区31，其中，第一电极区31为源极区，第二电极区33为漏极区，如图5A至图5C所示；这里，图5C中的纵截面垂直于所述硅衬底并且不穿过所述硅半导体柱。
S40：在硅衬底1上沉积覆盖第一电极区31的端面、第二沟槽62的底壁和侧壁的牺牲氧化物层80，硅半导体柱30的侧壁也被牺牲氧化物层80覆 盖，如图6所示。
单晶硅等的晶格中具有空隙，牺牲氧化物层80的作用是在离子注入时防止带能量注入的离子对下面的单晶硅等的晶格造成损伤，起到保护晶格的作用。
S50：分别以第一电极区31的顶面和第二沟槽62的开口作为自对准窗口，沿着垂直于硅衬底1的方向，采用一次自对准离子注入工艺同时对第一电极区31的端面和第二沟槽62底壁的硅衬底进行低能离子注入(implant doping)，使掺杂材料同时被注入第一电极区31和第二沟槽62下方的硅衬底1中，如图7所示。图7中的箭头表示自对准离子注入的方向，即垂直于硅衬底1(与硅半导体柱30之间的夹角为0°)的方向，因此不会对硅半导体柱的沟道区进行离子注入。其中，低能离子注入的能量为5kev至100kev；所述掺杂材料在第一电极区31中的注入深度，即完成离子注入后，掺杂材料在第一电极区31中所处的位置距离第一电极区31的顶面之间的距离，可以为0至45nm；所述掺杂材料在所述硅衬底1中的注入深度，即完成离子注入后，掺杂材料在硅衬底1中所处的位置距离第二沟槽62的底壁之间的距离，可以为0至45nm。
本实施例的方案采用低能的离子注入即可实现对硅半导体柱的第一电极区和第二电极区的高浓度掺杂，可以避免高能注入引起的硅半导体柱损伤，而且采用定向的自对准离子注入工艺进行离子掺杂，可以避免掺杂材料进入沟道区，因此制得的半导体器件的性能较好，而且无需光刻版。
示例性地，对于N型金属-氧化物-半导体(N Metal Oxide Semiconductor,NMOS)晶体管来说，掺杂材料可以包括但不限于磷(P)和砷(As)等中的任意一种或多种；对于P型金属-氧化物-半导体(P Metal Oxide Semiconductor,NMOS)晶体管来说，掺杂材料可以包括但不限于硼(B)和镓(Ga)等中的任意一种或多种。掺杂材料的掺杂深度和掺杂浓度可以根据实际需要进行调整。
S60：采用退火工艺使所述掺杂材料在第一电极区31进行扩散，并且所述掺杂材料由硅衬底1扩散进入第二电极区33，在第一电极区31和第二电极区33形成掺杂区34，如图8所示；其中，所述离子注入的掺杂材料在第 一电极区31的平均体密度大于等于5e19原子个数/立方厘米，所述离子注入的掺杂材料在第二电极区33的平均体密度大于等于5e19原子个数/立方厘米；掺杂材料在第一电极区31中基本是均匀分布，掺杂材料在第二电极区33中基本是均匀分布。
示例性地，退火工艺可以为热退火或尖峰退火，通过退火可以激活离子并扩大离子扩散区。退火温度可以为850℃至1100℃，退火时间可以为5s至30s。
S70：刻蚀去除第二沟槽62底壁上的牺牲氧化物层80，使得第二沟槽62露出硅衬底1；对露出的硅衬底1进行刻蚀，使第二沟槽62延伸进入硅衬底1中并朝向第二电极区33底端延伸，在沿所述第一方向分布的一列硅半导体柱30的第二电极区33下方形成沿所述第一方向延伸的位线槽21，如图9所示；
S80：在位线槽21中沉积导电层，形成位线20，如图10所示。
示例性地，导电层的沉积可以包括：在位线槽21的内壁上沉积第一金属层，接着进行快速热退火(RTA)使硅硅衬底中的硅与第一金属层中的第一金属反应形成第一金属的硅化物，然后采用第二金属层填满位线槽21。所述第一金属可以包括但不限于钴(Co)和钛(Ti)中的至少一种，所述第二金属可以为钨(W)等。
示例性地，第一沟槽61的深度大于第二沟槽62的深度，相邻两条位线20之间可以通过沉积在第一沟槽61底部的绝缘层来绝缘。
图11为本公开示例性实施例的另一种半导体器件的制造方法在形成位线槽后在a-a’方向上的纵截面结构示意图；图12为本公开示例性实施例的另一种半导体器件的制造方法在形成位线后在a-a’方向上的纵截面结构示意图；图13为本公开示例性实施例的另一种半导体器件的制造方法在去除部分牺牲氧化物层后在a-a’方向上的纵截面结构示意图；图14为本公开示例性实施例的另一种半导体器件的制造方法在进行离子注入时在a-a’方向上的纵截面结构示意图；图15为本公开示例性实施例的另一种半导体器件的制造方法在形成掺杂区后在a-a’方向上的纵截面结构示意图。
如图3至图6和图11至图15所示，在本公开的另一个示例性实施例中， 所述半导体器件的制造方法可以包括：
步骤S10’至步骤S40’与如上实施例的步骤S10至步骤S40基本相同，不同之处仅在于：步骤S20’中在进行CMP时不会去除半导体壁顶面上的绝缘层70，保留约5nm至10nm厚度的绝缘层70。
S50’：刻蚀去除第二沟槽62底壁上的牺牲氧化物层80，使得第二沟槽62露出硅衬底1；以第二沟槽62侧壁上的牺牲氧化物层80作为阻挡层，对露出的硅衬底1进行刻蚀，使第二沟槽62延伸进入硅衬底1中并朝向第二电极区33底端延伸，在沿所述第一方向分布的一列硅半导体柱30的第二电极区33下方形成沿所述第一方向延伸的位线槽21，如图11所示。
S60’：在位线槽21中沉积导电层，形成位线20，位线20被第二沟槽62露出，如图12所示。
S70’：刻蚀去除第二沟槽62侧壁上的牺牲氧化物层80，硅半导体柱30的第一电极区31端面上的牺牲氧化物层80可以被一起去除，后续采用合适材料的绝缘层70作为牺牲氧化物层，如图13所示，或者，将硅半导体柱30的第一电极区31端面上的牺牲氧化物层80保留一定厚度。
S80’：分别以第一电极区31的顶面和第二沟槽62的开口作为自对准窗口，沿着垂直于硅衬底1的方向，采用一次自对准低能离子注入工艺同时对第一电极区31的端面和第二沟槽62露出的位线20进行离子注入，使掺杂材料同时被注入第一电极区31和位线20中，如图14所示。图14中的箭头表示自对准离子注入的方向，即垂直于硅衬底1的方向(与硅半导体柱30之间的夹角为0°)。其中，低能离子注入能量为5kev至100kev；所述掺杂材料在第一电极区31中的注入深度，即完成离子注入后，掺杂材料在第一电极区31中所处的位置距离第一电极区31的顶面之间的距离，可以为0至45nm；所述掺杂材料在所述硅衬底1中的注入深度，即完成离子注入后，掺杂材料在硅衬底1中所处的位置距离第二沟槽62的底壁之间的距离，可以为0至45nm。
S90’：采用退火工艺使所述掺杂材料在第一电极区31进行扩散，并且所述掺杂材料由位线20扩散进入第二电极区33，在第一电极区31和第二电极区33形成掺杂区34，如图15所示；其中，所述离子注入的掺杂材料在第一 电极区31和第二电极区33的平均体密度大于等于5e19原子个数/立方厘米。砷(As)等离子可以通过横向离散(lateral straggling)进入第二电极区33。
在本公开的示例性实施例中，形成所述第一沟槽和所述第二沟槽的方法可以各自独立地选自干法刻蚀和湿法刻蚀中的任意一种或多种。
在本公开的示例性实施例中，所述位线槽可以采用干法刻蚀和湿法刻蚀中的任意一种或多种对所述第二沟槽的下部进行侧边刻蚀形成。
在本公开的示例性实施例中，沉积所述绝缘层层的方法可以选自原子层沉积(Atomic Layer Deposition,ALD)和化学气相沉积(Chemical Vapor Deposition,CVD)中的任意一种。
在本公开的示例性实施例中，沉积所述牺牲氧化物层的方法可以为原子层沉积(Atomic Layer Deposition,ALD)。
在本公开的示例性实施例中，所述半导体器件的制造方法还可以包括：刻蚀去除所述硅半导体柱的沟道区侧壁上的绝缘层和牺牲氧化物层，在所述沟道区的侧壁上依次沉积环绕所述沟道区侧壁的栅极绝缘层和栅电极，并将所述栅电极与字线连接。
在本公开的示例性实施例中，所述栅极绝缘层的材料可以选自氧化硅(例如，SiO2)、氧化铪(例如，HfO2)、氧化锆(例如，ZrO)和氧化铝(例如，Al2O3)中的任意一种或多种。所述栅极绝缘层可以为单层结构或多层结构，例如，可以包括由氧化硅和氧化铪形成的两层结构，其中，氧化硅层与沟道区接触，氧化铪层与栅极接触。所述栅极绝缘层的厚度可以根据实际的电性需求来设置，例如，可以为2nm至5nm。
经TCAD(Technology Computer Aided Design)模拟，本公开实施例提供的上述半导体器件的制造方法可以使掺杂材料在所述第一电极区31的平均体密度大于等于5e19原子个数/立方厘米，在所述第二电极区33的平均体密度大于等于5e19原子个数/立方厘米，因此本公开实施例提供的上述半导体器件的制造方法是可行的。
以下通过几个TCAD模拟实例说明本公开方案的可行性。
实施例1
在本公开示例性实施例的半导体器件的制造方法中，在完成对源/漏电极的离子注入后，采用TCAD进行模拟；其中，
沟道区的掺杂材料为As，离子注入的能量为60kev至180kev，掺杂材料在沟道区的平均体密度为5e12原子个数/立方厘米至8e13原子个数/立方厘米；退火温度为850℃至1100℃，退火时间为5s至30s；
源/漏电极的掺杂材料为As，低能离子注入的能量为15kev至50kev，掺杂浓度为2e14原子个数/立方厘米至3e15原子个数/立方厘米；退火温度为850℃至1100℃，退火时间为5s至30s。
模拟结果如图16和图17所示。图16为本公开一个示例性实施例采用TCAD模拟得到的源/漏电极的掺杂材料在b-b’方向上的分布图；图17为本公开一个示例性实施例得到的半导体器件的硅半导体柱的掺杂材料的掺杂浓度曲线，其中横坐标为硅半导体柱的上表面(源电极端面)到硅半导体柱内部的深度。
实施例2
在本公开示例性实施例的半导体器件的制造方法中，沟道区的掺杂材料为As，离子注入的能量为60kev至180kev，掺杂浓度为5e12原子个数/立方厘米至8e13原子个数/立方厘米；
源/漏电极的掺杂材料为As，低能离子注入的能量为15kev至50kev，掺杂浓度为2e14原子个数/立方厘米至3e15原子个数/立方厘米。
实施例3
在本公开示例性实施例的半导体器件的制造方法中，沟道区的掺杂材料为As，离子注入的能量为60kev至180kev，掺杂浓度为5e12原子个数/立方厘米至8e13原子个数/立方厘米；
源/漏电极的掺杂材料为P，低能离子注入的能量为5kev至20kev，掺杂浓度为5e14原子个数/立方厘米至5e15原子个数/立方厘米。
图18为本公开实施例2和3得到的半导体器件的硅半导体柱的掺杂材料的掺杂浓度曲线，其中横坐标为硅半导体柱的上表面(源电极端面)到硅半导体柱内部的深度。
图19为本公开实施例得到的半导体器件的硅半导体柱的掺杂材料分别在没有反向散射和有反向散射的情况下的掺杂浓度曲线，其中横坐标为硅半导体柱的上表面(源电极端面)到硅半导体柱内部的深度。(依据图19均可认为反向散射剂量可以忽略不记)。
可以看出，本公开实施例提供的半导体器件的制造方法可以实现对晶体管源/漏电极的高浓度掺杂，使源/漏电极的掺杂浓度远远高于沟道区的掺杂浓度。
本公开实施例还提供一种电子设备，所述电子设备包括如上本公开实施例提供的所述半导体器件。
在本公开的示例性实施例中，所述电子设备可以为：存储装置、智能电话、计算机、平电脑、人工智能设备、可穿戴设备或移动电源等。存储装置可以包括计算机中的内存等，此处不作限定。
虽然本公开所揭露的实施方式如上，但所述的内容仅为便于理解本公开而采用的实施方式，并非用以限定本公开。任何本公开所属领域内的技术人员，在不脱离本公开所揭露的精神和范围的前提下，可以在实施的形式及细节上进行任何的修改与变化，但本公开的保护范围，仍须以所附的权利要求书所界定的范围为准。

Claims (20)

  1. 一种半导体器件，包括：设置在衬底上的至少一个晶体管，位线；所述晶体管包括沿垂直于所述衬底的方向延伸的硅半导体柱，所述硅半导体柱沿着顶端到靠近所述衬底的方向依次包括第一电极区、沟道区和第二电极区，所述位线设置在所述第二电极区与所述衬底之间并且与所述第二电极区连接；位于所述第二电极区的硅半导体柱含有采用自对准离子注入工艺掺杂的掺杂材料，所述掺杂材料在所述第二电极区的平均体密度大于等于5e19原子个数/立方厘米；所述自对准离子注入工艺为自对准低能离子注入工艺。
  2. 根据权利要求1所述的半导体器件，其中，所述掺杂材料在所述第二电极区的平均体密度为5e19原子个数/立方厘米至5e20原子个数/立方厘米。
  3. 根据权利要求1所述的半导体器件，其中，位于所述第一电极区的硅半导体柱含有采用自对准离子注入工艺掺杂的掺杂材料；所述自对准离子注入工艺为自对准低能离子注入工艺。
  4. 根据权利要求1或3所述的半导体器件，其中，
    所述第一电极区和/或所述第二电极区的所述自对准低能离子注入工艺的注入能量范围为5kev至100kev。
  5. 根据权利要求4所述的半导体器件，其中，通过一次自对准低能离子注入工艺同时在所述第一电极区和第二电极区进行掺杂。
  6. 根据权利要求3所述的半导体器件，其中，所述掺杂材料在所述第一电极区的平均体密度大于等于5e19原子个数/立方厘米。
  7. 根据权利要求6所述的半导体器件，其中，所述掺杂材料在所述第一电极区的平均体密度为5e19原子个数/立方厘米至5e20原子个数/立方厘米。
  8. 根据权利要求1至7中任一项所述的半导体器件，包括在所述衬底上沿第一方向和第二方向阵列分布的多个晶体管，所述第一方向与所述第二方向交叉；
    所述位线沿所述第一方向延伸且在第二方向间隔排布，沿所述第一方向分布的一行晶体管的第二电极区与同一条位线连接；
    所述晶体管还包括：环绕所述沟道区并且与所述沟道区相绝缘的栅电极；所述半导体器件还包括多条沿所述第二方向延伸的字线，沿所述第二方向分布的一列晶体管的所述栅电极与同一条字线连接，并且各所述栅电极作为所述字线的一部分。
  9. 根据权利要求1至8中任一项所述的半导体器件，其中，所述硅半导体柱的至少位于所述沟道区的半导体为单晶硅半导体，所述沟道区的远离所述第一电极区和所述第二电极区的区域中无掺杂离子。
  10. 一种半导体器件的制造方法，其中，所述半导体器件包括至少一个晶体管，位线；所述晶体管包括沿垂直于硅衬底的方向延伸的硅半导体柱；
    所述半导体器件的制造方法包括：
    在所述硅衬底上形成各所述晶体管的硅半导体柱和暴露所述硅半导体柱的一侧的沟槽；所述沟槽包括底壁和侧壁，从所述沟槽的底壁至所述沟槽的开口方向，所述硅半导体柱至少依次包括待形成的漏极区和沟道区；
    以所述沟槽的开口为自对准窗口，采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行低能离子注入，并退火扩散，形成至少位于相邻两个硅半导体柱的所述待形成的漏极区的掺杂区；
    其中，所述离子注入的掺杂材料在所述漏极区的平均体密度大于等于5e19原子个数/立方厘米。
  11. 根据权利要求10所述的半导体器件的制造方法，其中，所述自对准离子注入工艺在形成所述位线之前进行；
    采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行离子注入，并退火扩散包括：
    在所述硅衬底上沉积覆盖所述沟槽的底壁和侧壁的牺牲氧化物层；
    沿着垂直于所述硅衬底的方向，采用自对准离子注入工艺仅对所述硅衬底进行低能离子注入而不对所述硅半导体柱的沟道区进行低能离子注入，使掺杂材料被注入被所述沟槽露出的所述硅衬底中；
    采用退火工艺使所述掺杂材料由所述硅衬底扩散进入所述沟槽两侧的所述晶体管的漏极区。
  12. 根据权利要求11所述的半导体器件的制造方法，其中，所述位线的形成过程包括：
    在对所述硅衬底进行离子注入之后，刻蚀去除所述沟槽的底壁上的所述牺牲氧化物层，使得所述沟槽露出所述硅衬底；
    对露出的所述硅衬底进行刻蚀，使所述沟槽延伸进入所述硅衬底中并朝向所述漏极区底端延伸，在沿平行于所述硅衬底的第一方向分布的一列硅半导体柱的漏极区下方形成沿所述第一方向延伸的位线槽；
    在所述位线槽中形成所述位线。
  13. 根据权利要求10所述的半导体器件的制造方法，其中，所述自对准离子注入工艺在形成所述位线之后进行；
    所述位线的形成过程包括：
    在所述硅衬底上沉积覆盖所述沟槽的底壁和侧壁的牺牲氧化物层；
    刻蚀去除所述沟槽的底壁上的所述牺牲氧化物层，使得所述沟槽露出所述硅衬底；
    对露出的所述硅衬底进行刻蚀，使所述沟槽延伸进入所述硅衬底中并朝向所述漏极区底端延伸，在沿平行于所述硅衬底的第一方向分布的一列硅半导体柱的漏极区下方形成沿所述第一方向延伸的位线槽；
    在所述位线槽中形成所述位线，所述位线被所述沟槽露出。
  14. 根据权利要求13所述的半导体器件的制造方法，其中，采用自对准离子注入工艺对所述沟槽的底壁的硅衬底进行离子注入，并退火扩散包括：
    沿着垂直于所述硅衬底的方向，采用自对准离子注入工艺对被所述沟槽露出的所述位线进行离子注入，使掺杂材料被注入所述位线中；
    采用退火工艺使所述掺杂材料由所述位线扩散进入所述硅半导体柱的所述漏极区中。
  15. 根据权利要求10至14中任一项所述的半导体器件的制造方法，其中，所述硅半导体柱还包括源极区，所述源极区位于所述沟道区远离所述硅衬底的一侧；
    所述半导体器件的制造方法还包括：采用自对准离子注入工艺在所述源极区进行低能离子注入，并退火扩散，在所述源极区中形成含有掺杂材料的掺杂区。
  16. 根据权利要求15所述的半导体器件的制造方法，其中，通过一次自对准离子注入工艺同时在所述源极区和所述漏极区进行掺杂，经退火工艺同时形成所述源极区的掺杂区和所述漏极区的掺杂区。
  17. 根据权利要求15所述的半导体器件的制造方法，其中，所述掺杂材料在所述硅衬底和/或所述源极区中的注入深度为0至45nm。
  18. 根据权利要求10至17中任一项所述的半导体器件的制造方法，其中，所述漏极区和/或所述源极区的所述低能离子注入的工艺条件包括：注入能量为5kev至100kev。
  19. 根据权利要求10至17中任一项所述的半导体器件的制造方法，其中，所述退火的工艺条件包括：退火温度为850℃至1100℃，退火时间为5s至30s。
  20. 一种电子设备，包括根据权利要求1至9中任一所述的半导体器件。
PCT/CN2023/093288 2023-03-30 2023-05-10 半导体器件及其制造方法、电子设备 Ceased WO2024198047A1 (zh)

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CN113594163A (zh) * 2021-07-05 2021-11-02 长鑫存储技术有限公司 存储器及其制造方法
CN114759030A (zh) * 2022-03-21 2022-07-15 长江存储科技有限责任公司 半导体结构及其制作方法
CN115832015A (zh) * 2022-11-23 2023-03-21 北京超弦存储器研究院 一种半导体器件及其制备方法、电子设备

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CN113594163A (zh) * 2021-07-05 2021-11-02 长鑫存储技术有限公司 存储器及其制造方法
CN114759030A (zh) * 2022-03-21 2022-07-15 长江存储科技有限责任公司 半导体结构及其制作方法
CN115832015A (zh) * 2022-11-23 2023-03-21 北京超弦存储器研究院 一种半导体器件及其制备方法、电子设备

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