WO2024195461A1 - 半導体装置および半導体装置の製造方法 - Google Patents

半導体装置および半導体装置の製造方法 Download PDF

Info

Publication number
WO2024195461A1
WO2024195461A1 PCT/JP2024/007383 JP2024007383W WO2024195461A1 WO 2024195461 A1 WO2024195461 A1 WO 2024195461A1 JP 2024007383 W JP2024007383 W JP 2024007383W WO 2024195461 A1 WO2024195461 A1 WO 2024195461A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrode
film
region
main surface
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/JP2024/007383
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to CN202480018646.4A priority Critical patent/CN120958968A/zh
Priority to JP2025508264A priority patent/JPWO2024195461A1/ja
Priority to DE112024001317.1T priority patent/DE112024001317T5/de
Publication of WO2024195461A1 publication Critical patent/WO2024195461A1/ja
Priority to US19/325,873 priority patent/US20260013201A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01324—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T or inverted-T
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/01—Manufacture or treatment
    • H10D12/031—Manufacture or treatment of IGBTs
    • H10D12/032—Manufacture or treatment of IGBTs of vertical IGBTs
    • H10D12/035—Etching a recess in the emitter region 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/415—Insulated-gate bipolar transistors [IGBT] having edge termination structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/411—Insulated-gate bipolar transistors [IGBT]
    • H10D12/441—Vertical IGBTs
    • H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/40—Crystalline structures
    • H10D62/405—Orientations of crystalline planes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide

Definitions

  • This disclosure relates to a semiconductor device and a method for manufacturing the same.
  • Patent Document 1 discloses a SiC semiconductor device including a plurality of p-type body regions formed on the surface portion of an n - type SiC semiconductor layer, each of which constitutes a unit cell, an n-type source region formed inside the p-type body region, a gate electrode facing the p-type body region via a gate insulating film, an n + type drain region and a p + type collector region formed adjacent to each other on the back surface portion of the SiC semiconductor layer, and an n - type drift region between the p-type body region and the n + type drain region, and the p + type collector region is formed so as to cover a region including at least two unit cells in the X-axis along the surface of the SiC semiconductor layer.
  • One embodiment of the present disclosure provides a semiconductor device and a method for manufacturing the same that can improve the breakdown voltage reliability between a gate electrode and a surface electrode.
  • One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including the steps of: forming a base electrode on a main surface of a wafer; selectively isotropically etching the base electrode in the thickness direction, followed by anisotropically etching the base electrode to form a gate electrode having an electrode upper portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion connecting the electrode upper portion and the electrode side portion and including an arc-shaped recess curved inwardly of the base electrode; forming an interlayer film on the main surface so as to cover the gate electrode; forming an opening in the interlayer film that exposes a part of the main surface as a contact surface so as to be spaced apart from the electrode side portion in the lateral direction along the main surface; and forming a surface electrode on the interlayer film so as to be mechanically and electrically connected to the contact surface within the opening.
  • One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including the steps of forming a base electrode on a main surface of a wafer, selectively anisotropically taper etching the base electrode in the thickness direction, followed by anisotropically vertical etching to form a gate electrode having an electrode upper portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion connecting the electrode upper portion and the electrode side portion and including a flat inclined wall that slopes down from the electrode upper portion to the electrode side portion, forming an interlayer film on the main surface so as to cover the gate electrode, forming an opening in the interlayer film that exposes a part of the main surface as a contact surface so as to be spaced apart from the electrode side portion in the lateral direction along the main surface, and forming a surface electrode on the interlayer film so as to be mechanically and electrically connected to the contact surface within the opening.
  • One embodiment of the present disclosure provides a method for manufacturing a semiconductor device, including the steps of: forming a base electrode containing polysilicon on a main surface of a wafer; selectively anisotropically etching the base electrode in a thickness direction to form a gate electrode having an electrode upper portion along the main surface, an electrode side portion rising from the main surface, and an electrode corner portion connecting the electrode upper portion and the electrode side portion; thermally oxidizing the gate electrode to form a rounded portion in an arc shape that curves obliquely upward from the gate electrode at the electrode corner portion; forming an interlayer film on the main surface to cover the gate electrode; forming an opening in the interlayer film that exposes a part of the main surface as a contact surface so as to be spaced apart from the electrode side portion in a lateral direction along the main surface; and forming a surface electrode on the interlayer film so as to be mechanically and electrically connected to the contact surface within the opening.
  • a semiconductor device and a method for manufacturing the same that can improve the breakdown voltage reliability between a gate electrode and a surface electrode.
  • FIG. 1 is a plan view showing a semiconductor device according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a plan view showing an example of the layout of the first main surface.
  • FIG. 4 is an enlarged plan view showing a main portion of the first main surface.
  • FIG. 5 is an enlarged plan view showing further essential parts of the first main surface.
  • FIG. 6 is a cross-sectional view taken along the line VI-VI shown in FIG.
  • FIG. 7 is an enlarged cross-sectional view showing a main part of FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG.
  • FIG. 9 is an enlarged cross-sectional view showing a main part of FIG. FIG.
  • FIG. 10 is an enlarged cross-sectional view showing a main part of FIG.
  • FIG. 11 is a schematic diagram showing a wafer.
  • FIG. 12A is a cross-sectional view showing a method for manufacturing a semiconductor device.
  • FIG. 12B is a cross-sectional view showing a step subsequent to that of FIG. 12A.
  • FIG. 12C is a cross-sectional view showing a step subsequent to FIG. 12B.
  • FIG. 12D is a cross-sectional view showing a step subsequent to FIG. 12C.
  • FIG. 12E is a cross-sectional view showing a step subsequent to FIG. 12D.
  • FIG. 12F is a cross-sectional view showing a step subsequent to FIG. 12E.
  • FIG. 12G is a cross-sectional view showing a step subsequent to FIG.
  • FIG. 12H is a cross-sectional view showing a step subsequent to FIG. 12G.
  • FIG. 12I is a cross-sectional view showing a step subsequent to FIG. 12H.
  • FIG. 12J is a cross-sectional view showing a step subsequent to FIG. 12I.
  • FIG. 12K is a cross-sectional view showing a step subsequent to FIG. 12J.
  • FIG. 12L is a cross-sectional view showing a step subsequent to FIG. 12K.
  • FIG. 12M is a cross-sectional view showing a step subsequent to FIG. 12L.
  • FIG. 13 is a cross-sectional view showing a first modified example of a gate electrode. 14A illustrates the steps involved in forming the gate electrode of FIG. FIG.
  • FIG. 14B is a cross-sectional view showing a step subsequent to FIG. 14A.
  • FIG. 15 is a cross-sectional view showing a second modified example of a gate electrode.
  • 16A illustrates the steps involved in forming the gate electrode of FIG.
  • FIG. 16B is a cross-sectional view showing a step subsequent to that of FIG. 16A.
  • this term includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • FIG. 3 is a plan view showing an example layout of a first main surface 3.
  • FIG. 4 is an enlarged plan view showing a main portion of the first main surface 3.
  • FIG. 5 is an enlarged plan view showing further main portions of the first main surface 3.
  • FIG. 6 is a cross-sectional view taken along line VI-VI shown in FIG. 5.
  • FIG. 7 is an enlarged cross-sectional view showing the main part of FIG. 6.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII shown in FIG. 5.
  • FIG. 9 is an enlarged cross-sectional view showing the main part of FIG. 8.
  • the semiconductor device 1 is a semiconductor switching device having an insulated gate type transistor structure Tr as an example of a device structure.
  • the transistor structure Tr has a vertical structure.
  • the semiconductor device 1 is a SiC semiconductor device having a chip 2 including a SiC single crystal.
  • the chip 2 may be referred to as a "SiC chip” or a "semiconductor chip.”
  • the chip 2 is made of hexagonal SiC single crystal and is formed into a rectangular parallelepiped shape.
  • the hexagonal SiC single crystal has a number of polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • the chip 2 is made of 4H-SiC single crystal, but the chip 2 may be made of other polytypes.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape when viewed in a plan view.
  • the first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal.
  • the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal
  • the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.
  • first direction X refers to the third side surface 5C side
  • second direction Y refers to the first side surface 5A side
  • second side of the second direction Y refers to the second side surface 5B side.
  • first direction X is the m-axis direction ([1-100] direction) of the SiC single crystal
  • the second direction Y is the a-axis direction ([11-20] direction) of the SiC single crystal.
  • first direction X may be the a-axis direction of the SiC single crystal
  • second direction Y may be the m-axis direction of the SiC single crystal.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle that is inclined at a predetermined angle in a predetermined off direction relative to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined from the vertical axis toward the off direction by the off angle.
  • the c-plane of the SiC single crystal is inclined by the off angle relative to the horizontal plane.
  • the off-direction is preferably the a-axis direction of the SiC single crystal (i.e., the second direction Y).
  • the off-angle may be greater than 0° and less than or equal to 10°.
  • the off-angle may have a value that falls within at least one of the following ranges: greater than 0° and less than or equal to 1°, 1° or more and less than or equal to 2.5°, 2.5° or more and less than or equal to 5°, 5° or more and less than or equal to 7.5°, and 7.5° or more and less than or equal to 10°.
  • the off angle is preferably 5° or less. It is particularly preferable that the off angle be 2° or more and 4.5° or less.
  • the off angle is typically set in the range of 4° ⁇ 0.1°. This specification does not exclude a configuration in which the off angle is 0° (i.e., a configuration in which the first main surface 3 is a just plane relative to the c-plane).
  • the semiconductor device 1 includes an n-type first semiconductor region 6 formed in a region (surface layer) on the first main surface 3 side in the chip 2.
  • the first semiconductor region 6 may be referred to as a "drift region,” “drain drift region,” “drain region,” etc.
  • a drain potential is applied to the first semiconductor region 6 as a high potential (first potential).
  • the first semiconductor region 6 is formed in a layer extending along the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).
  • the semiconductor device 1 includes an n-type second semiconductor region 7 formed in a region (surface layer) on the second main surface 4 side in the chip 2. A drain potential is applied to the second semiconductor region 7.
  • the second semiconductor region 7 may be referred to as a "drain region” or the like.
  • the second semiconductor region 7 has a higher n-type impurity concentration than the first semiconductor region 6, and is electrically connected to the first semiconductor region 6 in the chip 2.
  • the second semiconductor region 7 is formed in a layer extending along the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the second semiconductor region 7 is made of a semiconductor substrate (specifically, a SiC substrate).
  • the chip 2 has a layered structure including a semiconductor substrate and an epitaxial layer.
  • the second semiconductor region 7 has a thickness greater than that of the first semiconductor region 6.
  • the semiconductor device 1 includes an active region 8 set in the chip 2.
  • the active region 8 includes a device structure (transistor structure Tr) and is a region where an output current (drain current) is generated.
  • the active region 8 is set in the inner part of the chip 2 at a distance from the periphery (first to fourth side faces 5A to 5D) of the chip 2 in a plan view.
  • the active region 8 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 8 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the semiconductor device 1 includes a peripheral region 9 that is set outside the active region 8 in the chip 2.
  • the peripheral region 9 is provided in a region between the periphery of the chip 2 and the active region 8 in a planar view.
  • the peripheral region 9 extends in a band shape along the active region 8 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 8.
  • the semiconductor device 1 includes a plurality of p-type body regions 20 formed in a surface layer portion of the first main surface 3 in the active region 8.
  • a source potential is applied to the plurality of body regions 20 as a low potential (second potential) different from a high potential (first potential).
  • the plurality of body regions 20 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of body regions 20 are arranged in a stripe shape extending in the second direction Y.
  • the multiple body regions 20 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the multiple body regions 20 are formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3. The multiple body regions 20 are exposed from the first main surface 3.
  • the semiconductor device 1 includes a p-type outer body region 21 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the outer body region 21 preferably has a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the outer body region 21 may be less than the p-type impurity concentration of the body region 20, or may be higher than the p-type impurity concentration of the body region 20.
  • the outer body region 21 is formed at a distance from the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) toward the active region 8, and extends in a band along the active region 8.
  • the outer body region 21 has a portion that extends in a band in the first direction X and a portion that extends in a band in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the outer body region 21 surrounds the active region 8 in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the outer body region 21 forms the boundary between the active region 8 and the peripheral region 9.
  • the outer body region 21 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the outer body region 21 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the outer body region 21 is connected to the multiple body regions 20 in a portion extending in the first direction X. As a result, the outer body region 21 is fixed to the same potential as the multiple body regions 20.
  • the outer body region 21 preferably has a width greater than the width of the body region 20.
  • the width of the body region 20 is the width in a direction perpendicular to the extension direction (i.e., the first direction X).
  • the width of the outer body region 21 is the width in a direction perpendicular to the extension direction.
  • the width of the outer body region 21 may be approximately equal to the width of the body region 20, or may be less than the thickness of the body region 20.
  • the ratio of the width of the outer body region 21 to the width of the body region 20 may be greater than or equal to 10 and less than or equal to 50. It is preferable that the width ratio be greater than or equal to 20 and less than or equal to 40.
  • the outer body region 21 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the outer body region 21 is formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3. The outer body region 21 is exposed from the first main surface 3.
  • the outer body region 21 has a thickness (depth) that is approximately equal to the thickness (depth) of the body region 20.
  • the thickness of the outer body region 21 may be less than the thickness of the body region 20, or may be greater than the thickness of the body region 20.
  • the semiconductor device 1 includes a plurality of n-type surface drift regions 22 formed in the surface portion of the first main surface 3.
  • each of the surface drift regions 22 is made up of a portion of the first semiconductor region 6.
  • the surface drift regions 22 may have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6, or may have an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6.
  • the multiple surface drift regions 22 are each defined in a region between multiple adjacent body regions 20 in the first direction X. Specifically, the multiple surface drift regions 22 are each defined by multiple body regions 20 and outer body regions 21 in the surface portion of the first main surface 3. The multiple surface drift regions 22 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the multiple surface drift regions 22 are formed in a stripe shape extending in the second direction Y.
  • the semiconductor device 1 includes a plurality of n-type source regions 23, 24 formed in the surface layer of each of the body regions 20.
  • the source regions 23, 24 have an n-type impurity concentration higher than the n-type impurity concentration of the first semiconductor region 6.
  • a source potential is applied to the source regions 23, 24.
  • the multiple source regions 23, 24 include a first source region 23 located on one side of the first direction X and a second source region 24 located on the other side of the first direction X in the surface layer portion of each body region 20.
  • one first source region 23 is formed on one end side of the body region 20 in the first direction X
  • one second source region 24 is formed on the other end side of the body region 20.
  • the first source region 23 is formed at a distance from one end of the body region 20 to the other end, and extends in a band shape along the extension direction of the body region 20.
  • the first source region 23 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the first source region 23 is not formed in the outer body region 21.
  • the first source region 23 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the body region 20.
  • the second source region 24 is formed at a distance from the first source region 23 to the other end side of the body region 20.
  • the second source region 24 is formed at a distance from the other end to one end side of the body region 20, and extends in a band shape along the extension direction of the body region 20.
  • the second source region 24 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the second source region 24 is not formed in the outer body region 21.
  • the second source region 24 is formed at a distance from the bottom of the body region 20 to the first main surface 3 side, and faces the first semiconductor region 6 across a part of the body region 20.
  • each first source region 23 may be formed at intervals in the extension direction of the body region 20. In this case, each first source region 23 may be formed in a strip extending in the second direction Y.
  • the multiple second source regions 24 may be formed at intervals in the extension direction of the body region 20. In this case, each second source region 24 may be formed in a strip extending in the second direction Y.
  • the semiconductor device 1 includes a plurality of p-type contact regions 25 formed in the surface layer of each of the body regions 20 in the active region 8.
  • the contact regions 25 may be referred to as "backgate regions.”
  • a source potential is applied to the contact regions 25.
  • the contact regions 25 have a p-type impurity concentration higher than the p-type impurity concentration of the body regions 20.
  • one contact region 25 is interposed in the region between the first source region 23 and the second source region 24 in the surface layer portion of the corresponding body region 20.
  • the contact region 25 extends in a band shape along the extension direction of the body region 20 (source regions 23, 24).
  • the contact region 25 is formed at a distance from the outer body region 21 in the second direction Y. In other words, the contact region 25 is not formed in the outer body region 21.
  • the contact region 25 is formed at a distance from the bottom of the body region 20 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the body region 20.
  • each contact region 25 may be formed at intervals in the extension direction of the body region 20.
  • each contact region 25 may be formed in a strip shape extending in the second direction Y.
  • the semiconductor device 1 includes a plurality of p-type channel regions 26, 27 formed in a surface portion of the first main surface 3.
  • the plurality of channel regions 26, 27 are partitioned in the surface portion of the plurality of body regions 20 between the ends of the plurality of body regions 20 (the plurality of surface drift regions 22) and the peripheries of the plurality of source regions 23, 24.
  • the plurality of channel regions 26, 27 are arranged at intervals in the first direction X and are each formed in a band shape extending in the second direction Y.
  • the plurality of channel regions 26, 27 are arranged in stripes extending in the second direction Y.
  • the multiple channel regions 26, 27 include multiple first channel regions 26 and multiple second channel regions 27.
  • the multiple first channel regions 26 are each partitioned into a region between one end of the multiple body regions 20 (surface drift region 22) and the multiple first source regions 23, forming a current path that extends horizontally.
  • the multiple second channel regions 27 are each partitioned into a region between the other end of the multiple body regions 20 (surface drift region 22) and the multiple second source regions 24, forming a current path that extends horizontally.
  • the semiconductor device 1 includes a plurality of planar electrode type gate structures 30 arranged on the first main surface 3 in the active region 8.
  • the plurality of gate structures 30 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the plurality of gate structures 30 are arranged in stripes extending in the second direction Y.
  • the extension direction of the plurality of gate structures 30 coincides with the off-direction of the SiC single crystal.
  • Each gate structure 30 is disposed on at least one channel region 26, 27.
  • each gate structure 30 is disposed across one surface drift region 22 and straddles two adjacent body regions 20, covering a plurality of channel regions 26, 27.
  • each gate structure 30 is disposed across the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, covering the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.
  • the gate structure 30 has a stacked structure including an insulating film 31 and a gate electrode 32.
  • the gate structure 30 does not have an insulating sidewall structure (spacer) on the side of the gate electrode 32.
  • the insulating film 31 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 31 has a single layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 31 includes a silicon oxide film made of an oxide of the chip 2.
  • the insulating film 31 covers the first main surface 3 in a film-like shape and is disposed on at least one of the channel regions 26, 27. In this embodiment, the insulating film 31 is disposed so as to cross one surface drift region 22 and straddle two adjacent body regions 20, covering the multiple channel regions 26, 27.
  • the insulating film 31 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and covers the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27.
  • the insulating film 31 partially covers the first source region 23 at a distance from the contact region 25, and exposes a part of the first source region 23 and the contact region 25 from the first main surface 3.
  • the insulating film 31 partially covers the second source region 24 at a distance from the contact region 25, and exposes a part of the second source region 24 and the contact region 25 from the first main surface 3.
  • the thickness of the insulating film 31 may be 10 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 may be a value that belongs to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, and 125 nm or more and 150 nm or less.
  • the thickness of the insulating film 31 is preferably 25 nm or more and 75 nm or less.
  • the gate electrode 32 is disposed on the insulating film 31 and faces at least one of the channel regions 26, 27 across the insulating film 31.
  • a gate potential is applied to the gate electrode 32 as a control potential.
  • the gate electrode 32 controls the inversion and non-inversion of at least one of the channel regions 26, 27 in response to the gate potential.
  • the gate electrode 32 includes a conductive semiconductor polycrystal.
  • the gate electrode 32 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.
  • the conductivity type of the gate electrode 32 is adjusted according to the gate threshold voltage to be achieved.
  • the gate electrode 32 may be referred to as a "polysilicon gate", a “poly gate”, etc.
  • the gate electrode 32 is formed in a strip shape extending in the second direction Y. In other words, the extension direction of the gate electrode 32 coincides with the off-direction of the SiC single crystal. In this embodiment, the gate electrode 32 is formed spaced inward from both ends of the insulating film 31 in the first direction X, exposing both ends of the insulating film 31. The gate electrode 32 is disposed on the insulating film 31 so as to straddle two adjacent body regions 20 across one surface drift region 22, and faces multiple channel regions 26, 27 across the insulating film 31.
  • the gate electrode 32 is disposed so as to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 across the insulating film 31.
  • the gate electrode 32 has an electrode upper portion 33, a first electrode side portion 34 on one side in the first direction X, and a second electrode side portion 35 on the other side in the first direction X.
  • the electrode upper portion 33 extends along the insulating film 31 (first main surface 3).
  • the electrode upper portion 33 may extend approximately parallel to the insulating film 31 (first main surface 3).
  • the electrode upper portion 33 may be referred to as an electrode upper wall.
  • the first electrode side portion 34 is formed at a distance from one end of the insulating film 31 to the other end in the first direction X, and extends in the vertical direction Z.
  • the second electrode side portion 35 is formed at a distance from the other end of the insulating film 31 to the one end in the first direction X, and extends in the vertical direction Z.
  • the first electrode side 34 and the second electrode side 35 may extend perpendicularly to the insulating film 31. That is, the gate electrode 32 may be formed in a quadrangular shape (flattened rectangular shape) in cross-sectional view. The first electrode side 34 and the second electrode side 35 may be inclined obliquely toward the electrode upper portion 33. That is, the gate electrode 32 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in cross-sectional view.
  • the first electrode side 34 and the second electrode side 35 may be referred to as a first electrode side wall and a second electrode side wall, respectively.
  • the width of the gate structure 30 may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the width of the gate structure 30 is the width in a direction perpendicular to the extension direction (i.e., the first direction X).
  • the width of the gate structure 30 is preferably 1 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the gate structure 30 may be 0.1 ⁇ m or more and 2.0 ⁇ m or less.
  • the thickness of the gate structure 30 is preferably 0.2 ⁇ m or more and 1.0 ⁇ m or less.
  • the gate electrode 32 includes an electrode corner 41 that connects the electrode upper portion 33 to the first electrode side portion 34 and the second electrode side portion 35.
  • the electrode corner 41 is a portion formed by removing a portion of the material of the gate electrode 32.
  • the electrode corner 41 is formed by a recess that curves inwardly of the gate electrode 32.
  • the electrode upper portion 33 is partially formed on the surface portion of each gate electrode 32 in a plan view.
  • the electrode upper portion 33 is formed spaced inward from at least one of the first electrode side portion 34 and the second electrode side portion 35 of the gate electrode 32, exposing at least one of the peripheral edge portion on the first electrode side portion 34 side and the peripheral edge portion on the second electrode side portion 35 side.
  • the electrode upper portion 33 is formed spaced inward from both the first electrode side portion 34 and the second electrode side portion 35, exposing both the peripheral edge portion on the first electrode side portion 34 side and the peripheral edge portion on the second electrode side portion 35 side in plan view.
  • the upper electrode portion 33 is formed in a band shape extending along the gate electrode 32 in a plan view. In other words, the extension direction of the upper electrode portion 33 coincides with the off-direction of the SiC single crystal.
  • the upper electrode portion 33 faces one surface drift region 22 in the stacking direction.
  • the upper electrode portion 33 may be formed at a distance toward the surface drift region 22 from two adjacent body regions 20 in a plan view, and may face only one surface drift region 22 in the stacking direction.
  • the upper electrode portion 33 may extend across two adjacent body regions 20 across one surface drift region 22 in a plan view.
  • the upper electrode portion 33 may be formed at a distance from the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side toward the surface drift region 22, and may face the surface drift region 22, the first channel region 26, and the second channel region 27 in the stacking direction.
  • the upper electrode portion 33 is formed to straddle the first source region 23 on one body region 20 side and the second source region 24 on the other body region 20 side, and faces the surface drift region 22, the first source region 23, the second source region 24, the first channel region 26, and the second channel region 27 in the stacking direction.
  • the electrode upper part 33 faces either one or both (preferably both) of the first channel region 26 and the second channel region 27. It is preferable that the electrode upper part 33 faces the entire first channel region 26 in the stacking direction in a cross-sectional view. It is preferable that the electrode upper part 33 faces the entire second channel region 27 in the stacking direction in a cross-sectional view.
  • the electrode corners 41 may take on various layouts depending on the layout of the electrode upper portion 33.
  • the electrode corners 41 are formed in an area on at least one side of the first electrode side portion 34 and the second electrode side portion 35.
  • the electrode upper portion 33 is formed spaced inward from both the first electrode side portion 34 and the second electrode side portion 35 of the gate electrode 32. Therefore, the electrode corner portion 41 has one electrode corner portion 41A defined in an area on the first electrode side portion 34 side relative to the electrode upper portion 33, and the other electrode corner portion 41B defined in an area on the second electrode side portion 35 side relative to the electrode upper portion 33 (see Figures 5 and 7).
  • One electrode corner 41A is connected from the peripheral edge on one side of the electrode upper part 33 to the first electrode side part 34.
  • One electrode corner 41A extends in a band shape in the second direction Y along the electrode upper part 33.
  • the other electrode corner 41B is connected from the peripheral edge on the other side of the electrode upper part 33 to the second electrode side part 35.
  • the other electrode corner 41B faces one electrode corner 41A in the first direction X across the electrode upper part 33, and extends in a band shape in the second direction Y along the electrode upper part 33.
  • One electrode corner 41A faces the first source region 23 in the stacking direction.
  • One electrode corner 41A may face only the first source region 23 in the stacking direction.
  • One electrode corner 41A may face the first source region 23 and the first channel region 26 in the stacking direction.
  • One electrode corner 41A may face the surface drift region 22, the first source region 23, and the first channel region 26 in the stacking direction.
  • one of the electrode corners 41A is formed at a distance from the first channel region 26 toward the first electrode side portion 34 in a plan view. In other words, it is preferable that one of the electrode corners 41A does not face the first channel region 26 in the stacking direction in a cross-sectional view.
  • the other electrode corner 41B faces the second source region 24 in the stacking direction.
  • the other electrode corner 41B may face only the second source region 24 in the stacking direction.
  • the other electrode corner 41B may face the second source region 24 and the second channel region 27 in the stacking direction.
  • the other electrode corner 41B may face the surface drift region 22, the second source region 24, and the second channel region 27 in the stacking direction.
  • the other electrode corner 41B is formed at a distance from the second channel region 27 toward the second electrode side portion 35 in a plan view. In other words, it is preferable that the other electrode corner 41B does not face the second channel region 27 in the stacking direction in a cross-sectional view.
  • the semiconductor device 1 includes a p-type termination region 45 formed on the first main surface 3 in the peripheral region 9.
  • the termination region 45 may also be referred to as a "well region", a “termination well region”, etc.
  • the termination region 45 may have a p-type impurity concentration approximately equal to the p-type impurity concentration of the outer body region 21.
  • the p-type impurity concentration of the termination region 45 may be higher than the p-type impurity concentration of the outer body region 21, or may be lower than the p-type impurity concentration of the outer body region 21.
  • the termination region 45 is spaced inward from the periphery of the first main surface 3 and is formed in the region between the periphery of the first main surface 3 and the outer body region 21.
  • the termination region 45 extends in a band shape along the outer body region 21 in a plan view.
  • the termination region 45 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the terminal region 45 surrounds the outer body region 21 in a plan view and is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the terminal region 45 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the termination region 45 is formed at a distance from the bottom of the first semiconductor region 6 toward the first main surface 3, and faces the second semiconductor region 7 across a portion of the first semiconductor region 6.
  • the termination region 45 is preferably formed at a distance from the middle of the first semiconductor region 6 toward the first main surface 3.
  • the termination region 45 may have a thickness (depth) approximately equal to the thickness (depth) of the outer body region 21.
  • the thickness of the termination region 45 may be greater than the thickness of the outer body region 21, or may be less than the thickness of the outer body region 21.
  • the termination region 45 has an inner edge on the active region 8 side and an outer edge on the peripheral side of the first main surface 3.
  • the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21.
  • the termination region 45 is fixed to the same potential as the outer body region 21, and is electrically connected to the multiple body regions 20 via the outer body region 21.
  • the inner edge of the termination region 45 is connected to the outer edge of the outer body region 21 around the entire periphery.
  • the termination region 45 (inner edge) has an overlap region 46 that overlaps the outer edge of the outer body region 21.
  • the overlap region 46 is a high-concentration region that includes the outer edge of the outer body region 21 and the inner edge of the termination region 45.
  • the overlap region 46 includes both the p-type impurities of the outer body region 21 and the p-type impurities of the termination region 45, and has a p-type impurity concentration that is higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45.
  • the overlap region 46 extends in a band shape along the outer body region 21 in a plan view.
  • the overlap region 46 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the overlap region 46 is divided into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the width of the overlap region 46 is preferably greater than the width of the body region 20.
  • the width of the overlap region 46 may be less than or equal to the width of the body region 20.
  • the semiconductor device 1 may have a relatively high-concentration p-type well region (46) instead of the overlap region 46.
  • the well region (46) has a p-type impurity concentration higher than both the p-type impurity concentration of the outer body region 21 and the p-type impurity concentration of the termination region 45.
  • the well region (46) may be formed in either or both of the surface layer of the outer body region 21 and the surface layer of the termination region 45.
  • the semiconductor device 1 includes at least one (preferably 2 to 20) p-type field region 47 formed in the surface layer of the first main surface 3 in the peripheral region 9.
  • the number of the multiple field regions 47 is typically 3 to 8.
  • the semiconductor device 1 includes three field regions 47.
  • the multiple field regions 47 are formed in an electrically floating state and relieve the electric field in the chip 2 at the periphery of the first main surface 3.
  • the number, spacing, width, depth, p-type impurity concentration, etc. of the field regions 47 are arbitrary and can take various values depending on the electric field to be relieved.
  • the field region 47 may have a p-type impurity concentration that is approximately equal to the p-type impurity concentration of the body region 20 (termination region 45).
  • the p-type impurity concentration of the field region 47 may be higher than the p-type impurity concentration of the body region 20 (termination region 45), or may be lower than the p-type impurity concentration of the body region 20 (termination region 45).
  • the multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the active region 8, with a gap inward from the periphery of the first main surface 3. Specifically, the multiple field regions 47 are formed in the region between the periphery of the first main surface 3 and the outer body region 21. More specifically, the multiple field regions 47 are arranged in the region between the periphery of the first main surface 3 and the termination region 45, with a gap from the termination region 45 to the periphery side of the first main surface 3.
  • the multiple field regions 47 are formed in a band shape extending along the active region 8 (termination region 45) in a plan view.
  • Each of the multiple field regions 47 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the multiple field regions 47 are formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) surrounding the active region 8 (termination region 45) in a plan view.
  • the multiple field regions 47 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the multiple field regions 47 are formed at intervals from the bottom of the first semiconductor region 6 toward the first main surface 3, and face the second semiconductor region 7 across a portion of the first semiconductor region 6. It is preferable that the multiple field regions 47 are formed at intervals from the middle of the first semiconductor region 6 toward the first main surface 3.
  • the semiconductor device 1 includes a peripheral insulating film 51 that covers the first main surface 3 in the peripheral region 9.
  • the peripheral insulating film 51 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the peripheral insulating film 51 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the peripheral insulating film 51 includes a silicon oxide film made of an oxide of the chip 2.
  • the peripheral insulating film 51 is preferably made of the same type of insulating material as the insulating film 31.
  • the peripheral insulating film 51 preferably has a thickness approximately equal to that of the insulating film 31.
  • the peripheral insulating film 51 covers the first main surface 3 in the peripheral region 9 in the form of a film.
  • the peripheral insulating film 51 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47.
  • the peripheral insulating film 51 is connected to the multiple insulating films 31 on the active region 8 side. Specifically, the peripheral insulating film 51 is formed integrally with the multiple insulating films 31, and forms one insulating film together with the multiple insulating films 31.
  • the semiconductor device 1 includes a gate wiring 52 arranged on the first main surface 3 in the peripheral region 9.
  • the semiconductor device 1 does not have an insulating sidewall structure (spacer) on the side of the gate wiring 52.
  • the gate wiring 52 is selectively routed on the first main surface 3 and has a portion that extends in a different direction from the multiple gate electrodes 32.
  • the gate wiring 52 is connected to the multiple gate electrodes 32 and applies a gate signal to the multiple gate electrodes 32.
  • the gate wiring 52 may be referred to as a "polysilicon gate wiring", a "poly gate wiring", a "second gate electrode”, etc.
  • the gate wiring 52 includes a conductive semiconductor polycrystal.
  • the gate wiring 52 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon. It is preferable that the gate wiring 52 has the same conductivity type as the gate electrode 32. The conductivity type of the gate wiring 52 is adjusted according to the conductivity type of the gate electrode 32.
  • the gate wiring 52 is disposed on the peripheral insulating film 51 in the peripheral region 9. Specifically, the gate wiring 52 is disposed on a portion of the peripheral insulating film 51 that covers the outer body region 21, and faces the outer body region 21 across the peripheral insulating film 51.
  • the gate wiring 52 is formed at a distance from the periphery of the first main surface 3 toward the active region 8, and extends in a strip along the active region 8.
  • the gate wiring 52 has a portion that extends in a strip in the first direction X and a portion that extends in a strip in the second direction Y in a plan view, and divides the active region 8 from multiple directions.
  • the gate wiring 52 surrounds the active region 8 in a plan view and is partitioned into a polygonal ring (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the gate wiring 52 may be end-shaped or endless.
  • the gate wiring 52 extends in a strip shape (ring shape in this embodiment) along the outer body region 21 in a plan view and faces the outer body region 21 across the outer insulating film 51 over the entire area in the stacking direction.
  • the gate wiring 52 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a plan view in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the gate wiring 52 is formed narrower than the outer body region 21 in a plan view, and is disposed above the outer body region 21 at a distance from the inner and outer edges of the outer body region 21.
  • the multiple gate electrodes 32 are extended up to above the outer body region 21, and the gate wiring 52 is connected to the multiple gate electrodes 32 above the outer body region 21.
  • the width of the gate wiring 52 is preferably greater than the width of the gate electrode 32.
  • the width of the gate wiring 52 is the width in a direction perpendicular to the extension direction.
  • the width of the gate wiring 52 may be less than or equal to the width of the gate electrode 32.
  • the width of the gate wiring 52 may be greater than the width of the outer body region 21.
  • the thickness of the gate wiring 52 is preferably approximately equal to the thickness of the gate electrode 32.
  • the gate wiring 52 has a wiring upper portion 53, a first wiring side portion 54 on the inner edge side, and a second wiring side portion 55 on the outer edge side.
  • the wiring upper portion 53 extends along the peripheral insulating film 51 (first main surface 3).
  • the wiring upper portion 53 may extend approximately parallel to the peripheral insulating film 51 (first main surface 3).
  • the wiring upper portion 53 may be referred to as a wiring upper wall.
  • the first wiring side portion 54 extends in the vertical direction Z on the peripheral insulating film 51, and the second wiring side portion 55 extends in the vertical direction Z on the peripheral insulating film 51.
  • the first wiring side 54 is connected to the multiple gate electrodes 32 (the first electrode side 34 and the second electrode side 35) in the portion extending in the first direction X.
  • the gate wiring 52 has multiple portions connected in a T-shape to the multiple gate electrodes 32. As a result, the gate wiring 52 is fixed to the same potential as the multiple gate electrodes 32.
  • the first wiring side 54 and the second wiring side 55 may extend perpendicularly to the peripheral insulating film 51. That is, the gate wiring 52 may be formed in a quadrangular shape (flattened rectangular shape) in cross section. The first wiring side 54 and the second wiring side 55 may be inclined obliquely toward the wiring upper portion 53. That is, the gate wiring 52 may be formed in a tapered shape (preferably an isosceles trapezoidal shape) in cross section.
  • the first wiring side 54 and the second wiring side 55 may be referred to as a first wiring sidewall and a second wiring sidewall, respectively.
  • the gate wiring 52 includes a wiring corner 61 that connects the wiring upper portion 53 to the first wiring side portion 54 and the second wiring side portion 55.
  • the wiring corner 61 is a portion formed by removing a portion of the material of the gate wiring 52.
  • the wiring corner 61 is formed by a recess that curves inwardly of the gate wiring 52.
  • the wiring upper portion 53 is partially formed on the surface portion of each gate wiring 52 in a plan view.
  • the wiring upper portion 53 is formed spaced inward from at least one of the first wiring side 54 and the second wiring side 55 of the gate wiring 52, and at least one of the peripheral portions on the first wiring side 54 side and the second wiring side 55 side of the wiring upper portion 53 is exposed.
  • the wiring upper portion 53 is formed spaced inward from both the first wiring side 54 and the second wiring side 55, and at least one of the peripheral portions on the first wiring side 54 side and the second wiring side 55 side of the wiring upper portion 53 is exposed.
  • the upper wiring portion 53 extends in a band shape along the gate wiring 52 in a plan view, and faces the outer body region 21 in the stacking direction.
  • the upper wiring portion 53 has a portion that extends in a band shape in the first direction X and a portion that extends in a band shape in the second direction Y in a plan view.
  • the upper wiring portion 53 surrounds the active region 8 in a plan view, and is partitioned into a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3.
  • the upper wiring portion 53 may have ends or may be endless.
  • the upper wiring portion 53 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quarter arc shape) in a plan view.
  • the upper wiring portion 53 is connected to the upper electrode portions 33 at the connection portion between the gate electrodes 32 and the gate wiring 52.
  • the upper wiring portion 53 is formed integrally with the upper electrode portions 33, and has multiple portions connected in a T-shape to the upper electrode portions 33 (see FIG. 5).
  • the wiring corners 61 may take various layouts depending on the layout of the wiring upper portion 53.
  • the wiring corners 61 are formed in the wiring upper portion 53 in an area on at least one side of the first wiring side portion 54 and the second wiring side portion 55.
  • the wiring upper portion 53 is formed with a space inward from both the first wiring side portion 54 and the second wiring side portion 55 of the gate wiring 52. Therefore, the wiring corner portion 61 has one wiring corner portion 61A defined in an area on the first wiring side portion 54 side relative to the wiring upper portion 53, and the other wiring corner portion 61B defined in an area on the second wiring side portion 55 side relative to the wiring upper portion 53 (see Figures 5 and 9).
  • One wiring corner 61A connects from the peripheral portion on one side of the wiring upper portion 53 to the first wiring side portion 54 of the gate wiring 52.
  • One wiring corner 61A extends in a band along the wiring upper portion 53.
  • the other wiring corner 61B connects from the other side of the wiring upper portion 53 to the second wiring side portion 55 of the gate wiring 52.
  • the other wiring corner 61B faces the wiring corner 61B on one side across the wiring upper portion 53, and extends in a band along the wiring upper portion 53.
  • the interlayer film 70 covers the multiple gate structures 30 in the active region 8. For each gate structure 30, the interlayer film 70 directly covers both the insulating film 31 and the gate electrode 32. In other words, the interlayer film 70 has portions that directly cover the electrode top 33, the first electrode side 34, the second electrode side 35, and the electrode corner 41 of the gate electrode 32.
  • the first oxide film 72 has a first covering portion 74, a second covering portion 75, and a third covering portion 76.
  • the first covering portion 74 extends horizontally in a film shape along the insulating film 31 (first main surface 3), and has a portion that contacts the first electrode side portion 34 (second electrode side portion 35) of the gate electrode 32.
  • the first covering portion 74 (first oxide film 72) has a thickness less than the thickness of the gate electrode 32, and covers the insulating film 31 with a gap from the height position of the electrode upper portion 33 of the gate electrode 32 toward the insulating film 31.
  • the second covering portion 75 is pulled out from the first covering portion 74 toward the electrode upper portion 33 in the stacking direction, and directly covers the first electrode side portion 34 (second electrode side portion 35) and the electrode corner portion 41 in a film-like manner.
  • the first oxide film 72 collectively covers the outer body region 21, the termination region 45, and the multiple field regions 47 in the peripheral region 9, sandwiching the peripheral insulating film 51 therebetween.
  • the first oxide film 72 covers the gate wiring 52 in the peripheral region 9.
  • the third wiring covering portion 79 is pulled out from the second wiring covering portion 78 toward the wiring upper portion 53 and extends horizontally in a film-like manner along the wiring upper portion 53.
  • the third wiring covering portion 79 directly covers the entire area of the wiring upper portion 53 between one wiring corner portion 61A and the other wiring corner portion 61B.
  • the second oxide film 73 covers the first oxide film 72 in a film-like manner, and collectively covers the active region 8 and the peripheral region 9 with the first oxide film 72 in between.
  • the second oxide film 73 collectively covers the multiple gate structures 30 in the active region 8 with the first oxide film 72 in between.
  • the second oxide film 73 covers both the insulating film 31 and the gate electrode 32 in a film-like manner with the first oxide film 72 in between.
  • the second upper covering portion 81 covers the third covering portion 76 of the first oxide film 72.
  • the second upper covering portion 81 extends horizontally in a film shape from the first upper covering portion 80 along the third covering portion 76, and covers the upper electrode portion 33 of the gate structure 30 with the third covering portion 76 in between.
  • the second upper covering portion 81 covers the entire upper electrode portion 33 with the third covering portion 76 in between one electrode corner portion 41A and the other electrode corner portion 41B.
  • the second upper covering portion 81 has a portion that covers the upper portion 33 of the electrode by sandwiching the first oxide film 72 (third covering portion 76), and a portion that covers the corner portion 41 of the electrode by sandwiching the first oxide film 72 (second covering portion 75).
  • the second oxide film 73 includes a first upper wiring coating portion 82 and a second upper wiring coating portion 83.
  • the first upper wiring coating portion 82 covers the first wiring coating portion 77 and the second wiring coating portion 78 of the first oxide film 72.
  • the first upper wiring coating portion 82 covers the peripheral insulating film 51 in a portion located above the first wiring coating portion 77, sandwiching the first wiring coating portion 77.
  • the first upper wiring covering portion 82 extends in a film-like shape in the stacking direction from above the first wiring covering portion 77 along the second wiring covering portion 78, and covers the first wiring side portion 54 (second wiring side portion 55) and the wiring corner portion 61 with the second wiring covering portion 78 in between.
  • the first upper wiring covering portion 82 has a portion that covers the first wiring side portion 54 (second wiring side portion 55) and the wiring corner portion 61 with the second wiring covering portion 78 in between.
  • the second upper wiring coating portion 83 covers the third wiring coating portion 79 of the first oxide film 72.
  • the second upper wiring coating portion 83 extends in a film-like manner horizontally from the first upper wiring coating portion 82 along the third wiring coating portion 79, and covers the upper wiring portion 53 by sandwiching the third wiring coating portion 79.
  • the second upper wiring coating portion 83 covers the entire upper wiring portion 53 by sandwiching the third wiring coating portion 79 between one wiring corner portion 61A and the other wiring corner portion 61B.
  • the second upper wiring covering portion 83 has a portion that covers the upper portion 53 of the wiring by sandwiching the first oxide film 72 (third wiring covering portion 79), and a portion that covers the corner portion 61 of the wiring by sandwiching the first oxide film 72 (second wiring covering portion 78).
  • the semiconductor device 1 includes a plurality of source openings 90 formed in the interlayer film 70 in the active region 8.
  • the plurality of source openings 90 are formed in regions to the sides of the plurality of gate electrodes 32 at intervals from the plurality of gate electrodes 32, respectively, and expose the first main surface 3 (chip 2).
  • the plurality of source openings 90 are formed in regions between the plurality of gate electrodes 32, respectively, and penetrate the insulating film 31 and the interlayer film 70.
  • the multiple source openings 90 penetrate both the first oxide film 72 and the second oxide film 73, and have walls that are defined by both the first oxide film 72 and the second oxide film 73.
  • the multiple source openings 90 expose the corresponding multiple source regions 23, 24 and contact regions 25, respectively.
  • the multiple source openings 90 are formed at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. That is, the multiple source openings 90 are formed in a stripe shape extending in the second direction Y.
  • the multiple source openings 90 are formed at intervals in the second direction Y from the gate wiring 52. That is, the multiple source openings 90 are formed in a region surrounded by the multiple gate electrodes 32 and the gate wiring 52.
  • a plurality of source openings 90 may be formed in a region between two gate structures 30 adjacent in the first direction X.
  • the plurality of source openings 90 may be formed in a line in the second direction Y with a space therebetween.
  • each source opening 90 may be formed in a quadrilateral shape (square shape) in a plan view, a rectangular shape extending in the first direction X, a rectangular shape extending in the second direction Y, a hexagonal shape, a circular shape, or the like.
  • the source opening 90 may have a width W of 0.2 ⁇ m or more and 3 ⁇ m or less.
  • the width W of the source opening 90 is preferably 0.3 ⁇ m or more and 1 ⁇ m or less.
  • the source opening 90 may have a depth D of 0.2 ⁇ m or more and 2 ⁇ m or less.
  • the depth D of the source opening 90 is preferably 0.5 ⁇ m or more and 1 ⁇ m or less.
  • the source opening 90 preferably has an aspect ratio D/W of 0.3 or more and 3 or less.
  • the aspect ratio D/W is defined by the ratio of the depth D of the source opening 90 to the width W of the source opening 90.
  • the aspect ratio D/W is preferably 0.5 or more and 2 or less. It is particularly preferable that the aspect ratio D/W is greater than 1. With this configuration, the multiple gate structures 30 are arranged at a narrow pitch.
  • the semiconductor device 1 includes a plurality of source recesses 91 formed in the first main surface 3 in the portions exposed from the plurality of source openings 90.
  • the semiconductor device 1 does not necessarily have to have the source recesses 91. Therefore, a configuration that does not have the source recesses 91 may be adopted.
  • the multiple source recesses 91 each have a planar shape that matches the planar shape of the corresponding source opening 90, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple source recesses 91 are formed at intervals from the bottoms of the corresponding body regions 20 toward the first main surface 3, exposing the corresponding multiple source regions 23, 24 and contact regions 25.
  • the multiple source recesses 91 are formed at intervals from the bottoms of the corresponding multiple source regions 23, 24 (contact regions 25) toward the first main surface 3.
  • the semiconductor device 1 includes at least one (in this embodiment, multiple) outer openings 92 formed in the interlayer film 70 in the peripheral region 9.
  • the multiple outer openings 92 are formed in a portion of the interlayer film 70 that covers the termination region 45.
  • the multiple outer openings 92 penetrate the interlayer film 70 and expose the termination region 45.
  • the multiple outer openings 92 are formed in a portion of the interlayer film 70 that covers the overlap region 46 of the termination region 45 and expose the overlap region 46.
  • the outer openings 92 may expose the outer body region 21 instead of or in addition to the termination region 45 (overlapping region 46).
  • the outer openings 92 penetrate both the first oxide film 72 and the second oxide film 73, and have walls that are defined by both the first oxide film 72 and the second oxide film 73.
  • the multiple outer openings 92 are formed at intervals along the termination region 45 (overlap region 46) (see Figures 4 and 5).
  • the multiple outer openings 92 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple outer openings 92 may be formed in a band shape extending along the termination region 45 (overlap region 46) in a plan view.
  • the outer openings 92 may have an aspect ratio D/W (preferably greater than 1) similar to the source openings 90.
  • the single outer opening 92 may be formed in a polygonal ring shape (a square ring in this embodiment) with ends or without ends, having four sides parallel to the periphery of the first main surface 3.
  • the single outer opening 92 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) following the termination region 45 (overlapping region 46) in a plan view.
  • the semiconductor device 1 includes a plurality of outer recesses 93 formed in the first main surface 3 in the portions exposed from the plurality of outer openings 92.
  • the semiconductor device 1 does not necessarily have to have the outer recesses 93. Therefore, a configuration that does not have the outer recesses 93 may be adopted.
  • the multiple outer recesses 93 each have a planar shape that matches the planar shape of the corresponding outer opening 92, and are recessed from the first main surface 3 toward the second main surface 4.
  • the multiple outer recesses 93 are formed at intervals from the bottom of the termination region 45 (overlap region 46) toward the first main surface 3, and each exposes the termination region 45 (overlap region 46).
  • the semiconductor device 1 includes at least one (in this embodiment, multiple) gate openings 94 formed in the interlayer film 70 in the peripheral region 9.
  • the multiple gate openings 94 are formed in a portion of the interlayer film 70 that covers the gate wiring 52.
  • the multiple gate openings 94 penetrate the interlayer film 70 and expose the upper wiring portion 53 of the gate wiring 52.
  • the multiple gate openings 94 expose the wiring upper portion 53 of the gate wiring 52. More specifically, the multiple gate openings 94 expose the wiring upper portion 53 at intervals inward from the wiring corner portion 61. The multiple gate openings 94 expose only the wiring upper portion 53, and do not expose the wiring corner portion 61. Of course, one or more gate openings 94 that expose the wiring corner portion 61 may be formed.
  • the multiple gate openings 94 penetrate both the first oxide film 72 and the second oxide film 73, and have walls defined by both the first oxide film 72 and the second oxide film 73.
  • the multiple gate openings 94 are formed at intervals along the gate wiring 52 (upper wiring portion 53) (see Figures 4 and 5).
  • the multiple gate openings 94 may be formed in a quadrangular (square), rectangular, hexagonal, circular, or other shape in a plan view.
  • the multiple gate openings 94 may be formed in a strip shape extending along the gate wiring 52 in a plan view.
  • the gate openings 94 may have an aspect ratio D/W (preferably greater than 1) similar to the source openings 90.
  • the semiconductor device 1 may have a single gate opening 94.
  • the single gate opening 94 may be formed in a strip shape extending along the gate wiring 52.
  • the single gate opening 94 may have a portion extending in a strip shape in the first direction X and a portion extending in a strip shape in the second direction Y in a plan view.
  • the single gate opening 94 may be formed in a polygonal ring shape (a square ring in this embodiment) with or without ends, having four sides parallel to the periphery of the first main surface 3.
  • the single gate opening 94 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape) following the gate wiring 52 (wiring upper portion 53) in a plan view.
  • the semiconductor device 1 includes a source pad electrode 95 disposed on the interlayer film 70.
  • the source pad electrode 95 is a terminal electrode to which a source potential is applied from the outside.
  • the source pad electrode 95 may also be referred to as a "first pad electrode,” a “first main surface electrode,” a “first terminal electrode,” etc.
  • the source pad electrode 95 is disposed on a portion of the interlayer film 70 that covers the active region 8.
  • the source pad electrode 95 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically isolated from the multiple gate electrodes 32 by the interlayer film 70.
  • the source pad electrode 95 is electrically connected to the multiple body regions 20, the outer body region 21, the multiple source regions 23 and 24, the contact region 25, etc. via the multiple source openings 90.
  • the source pad electrode 95 has a first pad portion 96, a second pad portion 97, and a third pad portion 98.
  • the first pad portion 96 has a relatively large planar area and forms the main body of the source pad electrode 95.
  • the first pad portion 96 is formed in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is biased toward the fourth side surface 5D relative to the center of the active region 8.
  • the first pad portion 96 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 90.
  • the second pad portion 97 has a planar area less than that of the first pad portion 96, and is pulled out in a strip shape (rectangular shape) from one end of the first pad portion 96 in the second direction Y (the end on the first side surface 5A side) toward the third side surface 5C.
  • the second pad portion 97 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 90.
  • the third pad portion 98 has a planar area less than that of the first pad portion 96, and is pulled out in a strip shape (rectangular shape) from the other end of the first pad portion 96 in the second direction Y (the end on the second side surface 5B side) toward the third side surface 5C, and faces the second pad portion 97 in the second direction Y.
  • the third pad portion 98 covers the multiple gate electrodes 32 with the interlayer film 70 in between, and is electrically connected to the multiple body regions 20, etc. via the multiple source openings 90.
  • the plane area of the third pad portion 98 may be approximately equal to the plane area of the second pad portion 97. Of course, the plane area of the third pad portion 98 may be greater than the plane area of the second pad portion 97, or may be less than the plane area of the second pad portion 97. Either or both of the second pad portion 97 and the third pad portion 98 may be used as a terminal portion for monitoring a current.
  • the source pad electrode 95 does not necessarily have to have both the second pad portion 97 and the third pad portion 98 at the same time.
  • the source pad electrode 95 may have only one of the second pad portion 97 and the third pad portion 98.
  • the source pad electrode 95 may be composed of only the first pad portion 96, and may not have the second pad portion 97 or the third pad portion 98.
  • the source pad electrode 95 includes a first underlying electrode film 100 and a first main electrode film 102.
  • the first underlying electrode film 100 may be referred to as the "source underlying electrode film,” and the first main electrode film 102 may be referred to as the "source main electrode film.”
  • the first underlying electrode film 100 forms the lower layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the interlayer film 70 in the active region 8.
  • the first underlying electrode film 100 collectively covers the region of the interlayer film 70 in which the multiple source openings 90 are formed. In other words, the first underlying electrode film 100 penetrates into the multiple source openings 90 from above the interlayer film 70.
  • the first underlying electrode film 100 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner.
  • the first underlying electrode film 100 defines recesses in each of the multiple source openings 90.
  • the first underlying electrode film 100 may have a portion that partially covers the gate wiring 52 with the interlayer film 70 in between.
  • the first underlying electrode film 100 may be formed spaced inward from the gate wiring 52 in a plan view.
  • the first base electrode film 100 has a layered structure including a first electrode film 103 layered on the interlayer film 70, and a second electrode film 104 layered on the first electrode film 103.
  • the first electrode film 103 includes a Ti film
  • the second electrode film 104 includes a TiN film.
  • the first base electrode film 100 does not necessarily have to have a laminated structure, and may have a single layer structure consisting of either the first electrode film 103 (Ti film) or the second electrode film 104 (TiN film).
  • the thickness of the first electrode film 103 may be 10 nm or more and 100 nm or less.
  • the thickness of the second electrode film 104 may be 50 nm or more and 200 nm or less.
  • the first electrode film 103 collectively covers the region of the interlayer film 70 in which the multiple source openings 90 are formed, and extends from above the interlayer film 70 into the multiple source openings 90.
  • the first electrode film 103 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner.
  • the first electrode film 103 directly covers the interlayer film 70.
  • the first electrode film 103 directly covers the second oxide film 73.
  • the first electrode film 103 faces the multiple gate electrodes 32 with the interlayer film 70 in between.
  • the first electrode film 103 extends along the wall surface of the source opening 90, and covers the insulating film 31, the first oxide film 72, and the second oxide film 73.
  • the first electrode film 103 faces the first electrode side 34 (second electrode side 35) of the gate electrode 32 across the interlayer film 70.
  • the first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each source opening 90, and is electrically connected to the first main surface 3. Specifically, the first electrode film 103 has a portion that covers the source recess 91 in a film-like manner at the bottom of each source opening 90, and is electrically connected to the multiple source regions 23, 24 and the contact region 25.
  • the first electrode film 103 may cover the source recess 91 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the source recess 91.
  • the first electrode film 103 may have a portion located on the bottom side of the source recess 91 with respect to the height position of the first main surface 3, and a portion located on the insulating film 31 side with respect to the height position of the first main surface 3.
  • the second electrode film 104 covers the area of the interlayer film 70 on the first electrode film 103 where the multiple source openings 90 are formed.
  • the second electrode film 104 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, sandwiching the first electrode film 103 therebetween, and a portion that covers the wall surfaces of the multiple source openings 90 in a film-like manner, sandwiching the first electrode film 103 therebetween.
  • the second electrode film 104 faces the multiple gate electrodes 32, sandwiching the first electrode film 103 and the interlayer film 70 therebetween.
  • the second electrode film 104 extends along the wall surface of the source opening 90, and covers the insulating film 31, the first oxide film 72, and the second oxide film 73 with the first electrode film 103 in between.
  • the second electrode film 104 faces the first electrode side 34 (second electrode side 35) of the gate electrode 32 with the first electrode film 103 and the interlayer film 70 in between.
  • the second electrode film 104 has a portion that covers the source recess 91 in a film-like manner at the bottom of each source opening 90, sandwiching the first electrode film 103 therebetween, and is electrically connected to the multiple source regions 23, 24 and the contact region 25 via the first electrode film 103.
  • the second electrode film 104 may have a portion that is located within the source recess 91.
  • the entire second electrode film 104 is located above the source recess 91.
  • the first main electrode film 102 forms the upper layer of the source pad electrode 95 (first pad portion 96, second pad portion 97, and third pad portion 98) and covers the first base electrode film 100 in a film form.
  • the first main electrode film 102 contains a conductive material different from the conductive material of the first base electrode film 100.
  • the first main electrode film 102 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the first main electrode film 102 has a thickness greater than the thickness (total thickness) of the first base electrode film 100.
  • the thickness of the first main electrode film 102 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the thickness of the first main electrode film 102 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first main electrode film 102 penetrates into the multiple source openings 90 from above the interlayer film 70, and is mechanically and electrically connected to the multiple source regions 23, 24 and the contact region 25.
  • the first main electrode film 102 faces the multiple gate electrodes 32, sandwiching the first base electrode film 100 and the interlayer film 70 between them.
  • the first main electrode film 102 faces the electrode upper portion 33 and electrode corner portion 41 of each gate electrode 32, sandwiching the first base electrode film 100 and the interlayer film 70 between them.
  • the semiconductor device 1 includes a source finger electrode 110 that is extended from the source pad electrode 95 onto the peripheral region 9.
  • the source finger electrode 110 transmits the source potential applied to the source pad electrode 95 to the peripheral region 9.
  • the source finger electrode 110 is extended from the portion of the source pad electrode 95 (first pad portion 96) on the fourth side surface 5D side onto the portion of the interlayer film 70 that covers the peripheral region 9.
  • the source finger electrodes 110 are extended to above the termination region 45 and are electrically connected to the termination region 45 via a plurality of outer openings 92. Specifically, the source finger electrodes 110 are electrically connected to the overlap region 46 of the termination region 45 via a plurality of outer openings 92.
  • the source finger electrode 110 extends in a strip shape along the termination region 45 (overlapping region 46).
  • the source finger electrode 110 has a portion extending in a strip shape in the first direction X in a plan view and a portion extending in a strip shape in the second direction Y.
  • the source finger electrode 110 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95.
  • the source finger electrode 110 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a plan view in an arc shape (preferably a quadrant arc shape) (see FIG. 4).
  • the source finger electrode 110 like the source pad electrode 95, includes a first underlying electrode film 100 and a first main electrode film 102.
  • the first underlying electrode film 100 forms the lower layer of the source finger electrode 110 and covers the interlayer film 70 in the peripheral region 9.
  • the first underlying electrode film 100 collectively covers the area of the interlayer film 70 where the multiple outer openings 92 are formed. In other words, the first underlying electrode film 100 extends from above the interlayer film 70 into the multiple outer openings 92.
  • the first underlying electrode film 100 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner.
  • the first underlying electrode film 100 defines recesses within each of the multiple outer openings 92.
  • the first base electrode film 100 has a layered structure including a first electrode film 103 and a second electrode film 104, similar to the source pad electrode 95.
  • the first electrode film 103 collectively covers the area of the interlayer film 70 in which the multiple outer openings 92 are formed, and extends into the multiple outer openings 92 from above the interlayer film 70.
  • the first electrode film 103 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner.
  • the first electrode film 103 covers the first main surface 3 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the first main surface 3 (chip 2). Specifically, the first electrode film 103 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, and is electrically connected to the termination region 45 (overlap region 46) within the outer recess 93.
  • the first electrode film 103 may cover the outer recess 93 in a film-like manner with a gap from the height position of the first main surface 3 to the bottom side of the outer recess 93.
  • the first electrode film 103 may have a portion located on the bottom side of the outer recess 93 with respect to the height position of the first main surface 3, and a portion located on the peripheral insulating film 51 side with respect to the height position of the first main surface 3.
  • the second electrode film 104 is disposed on the first electrode film 103 and covers the entire area of the interlayer film 70 in which the multiple outer openings 92 are formed.
  • the second electrode film 104 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner with the first electrode film 103 in between, and a portion that covers the wall surfaces of the multiple outer openings 92 in a film-like manner with the first electrode film 103 in between.
  • the second electrode film 104 has a portion that covers the outer recess 93 in a film-like manner at the bottom of each outer opening 92, sandwiching the first electrode film 103 therebetween, and is electrically connected to the termination region 45 (overlap region 46) via the first electrode film 103.
  • the second electrode film 104 may have a portion that is located within the outer recess 93.
  • the entire second electrode film 104 is located above the outer recess 93.
  • the first main electrode film 102 forms the upper layer of the source finger electrode 110 and covers the first base electrode film 100 in a film-like shape.
  • the first main electrode film 102 enters the multiple outer openings 92 from above the interlayer film 70 and is mechanically and electrically connected to the termination region 45 (overlap region 46).
  • the semiconductor device 1 includes a gate finger electrode 115 selectively routed over the interlayer film 70.
  • the gate finger electrode 115 transmits a gate potential to the gate wiring 52.
  • the gate finger electrode 115 is routed over a portion of the interlayer film 70 that covers the gate wiring 52 (i.e., over the outer peripheral region 9), and is electrically connected to the gate wiring 52 through a plurality of gate openings 94.
  • the gate finger electrode 115 is disposed in the region between the source pad electrode 95 and the source finger electrode 110 and spaced apart from the source pad electrode 95 and the source finger electrode 110.
  • the gate finger electrode 115 is disposed on the gate wiring 52 and extends in a strip shape along the gate wiring 52.
  • the gate finger electrode 115 has a portion that extends in a strip shape in the first direction X and a portion that extends in a strip shape in the second direction Y in a plan view.
  • the gate finger electrode 115 is formed in a band shape with four sides parallel to the periphery of the first main surface 3, and surrounds the source pad electrode 95.
  • the gate finger electrode 115 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in a circular arc shape (preferably a quadrant arc shape) in a plan view (see FIG. 4).
  • the gate finger electrode 115 has a pair of open ends on the fourth side surface 5D side through which the source finger electrode 110 passes.
  • the gate finger electrode 115 includes a second underlying electrode film 120 and a second main electrode film 122.
  • the second underlying electrode film 120 may be referred to as the "gate underlying electrode film” and the second main electrode film 122 may be referred to as the "gate main electrode film.”
  • the second underlying electrode film 120 forms the lower layer of the gate finger electrode 115, and covers the interlayer film 70 in the peripheral region 9.
  • the second underlying electrode film 120 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed. In other words, the second underlying electrode film 120 penetrates into the multiple gate openings 94 from above the interlayer film 70.
  • the second underlying electrode film 120 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner.
  • the second underlying electrode film 120 defines multiple recesses within the multiple gate openings 94.
  • the second base electrode film 120 has a layered structure including a first electrode film 123 layered on the interlayer film 70, and a second electrode film 124 layered on the first electrode film 123. It is preferable that the first electrode film 123 contains the same type of conductive material as the first electrode film 103 on the source side, and the second electrode film 124 contains the same type of conductive material as the second electrode film 104 on the source side. In this embodiment, the first electrode film 123 contains a Ti film, and the second electrode film 124 contains a TiN film.
  • the second base electrode film 120 does not necessarily have to have a laminated structure, and may have a single layer structure consisting of either the first electrode film 123 (Ti film) or the second electrode film 124 (TiN film).
  • the first electrode film 123 may have a thickness approximately equal to the thickness of the first electrode film 103 on the source side.
  • the second electrode film 124 may have a thickness approximately equal to the thickness of the second electrode film 104 on the source side.
  • the first electrode film 123 collectively covers the region of the interlayer film 70 in which the multiple gate openings 94 are formed, and extends from above the interlayer film 70 into the multiple gate openings 94.
  • the first electrode film 123 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner.
  • the first electrode film 123 covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, and is electrically connected to the gate wiring 52. Specifically, the first electrode film 123 has a portion that covers the upper wiring portion 53 of the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, and is mechanically and electrically connected to the upper wiring portion 53.
  • the first electrode film 123 is mechanically connected to the upper wiring portion 53 with a gap inward from the wiring corner portion 61. In other words, the first electrode film 123 is mechanically connected only to the upper wiring portion 53, and is not mechanically connected to the wiring corner portion 61. The first electrode film 123 is electrically connected to the wiring corner portion 61 via the upper wiring portion 53. Of course, the first electrode film 123 (second base electrode film 120) may have a portion connected to the wiring corner portion 61.
  • the second electrode film 124 covers the area of the interlayer film 70 on the first electrode film 123 where the multiple gate openings 94 are formed.
  • the second electrode film 124 has a portion that covers the upper surface of the interlayer film 70 in a film-like manner, sandwiching the first electrode film 123 therebetween, and a portion that covers the wall surfaces of the multiple gate openings 94 in a film-like manner, sandwiching the first electrode film 123 therebetween.
  • the second electrode film 124 has a portion that covers the gate wiring 52 in a film-like manner at the bottom of each gate opening 94, sandwiching the first electrode film 123 therebetween, and is electrically connected to the gate wiring 52 via the first electrode film 123.
  • the second electrode film 124 has a portion that covers the wiring upper portion 53 of the gate wiring 52 in a film-like manner, sandwiching the first electrode film 123 therebetween, and is electrically connected to the wiring upper portion 53 via the first electrode film 123.
  • the second electrode film 124 is positioned above the wiring upper portion 53 with a space inward from the wiring corner 61. In other words, the second electrode film 124 faces only the wiring upper portion 53 across the first electrode film 123, and does not face the wiring corner 61.
  • the second electrode film 124 is electrically connected to the wiring corner 61 via the first electrode film 123 and the wiring upper portion 53.
  • the second electrode film 124 may have a portion that faces the wiring corner 61 across the first electrode film 123.
  • the second main electrode film 122 forms the upper layer of the gate finger electrode 115 and covers the second base electrode film 120 in a film form.
  • the second main electrode film 122 contains a conductive material different from the conductive material of the second base electrode film 120.
  • the second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the second main electrode film 122 preferably includes the same type of conductive material as the conductive material of the first main electrode film 102.
  • the second main electrode film 122 may have a thickness approximately equal to that of the first main electrode film 102.
  • the second main electrode film 122 penetrates into the multiple gate openings 94 from above the interlayer film 70 and is mechanically and electrically connected to the upper wiring portion 53.
  • the semiconductor device 1 includes a gate pad electrode 130 disposed on the interlayer film 70.
  • the gate pad electrode 130 is a terminal electrode to which a gate potential is applied from the outside.
  • the gate pad electrode 130 may also be referred to as a "second pad electrode,” a “second main surface electrode,” a “second terminal electrode,” etc.
  • the gate pad electrode 130 is disposed in a region between the source pad electrode 95 and the source finger electrode 110 and spaced apart from the source pad electrode 95 and the source finger electrode 110.
  • the gate pad electrode 130 is disposed in a region on the third side surface 5C side relative to the first pad portion 96, and is sandwiched between the second pad portion 97 and the third pad portion 98. In other words, the gate pad electrode 130 faces the first pad portion 96 in the first direction X, and faces the second pad portion 97 and the third pad portion 98 in the second direction Y.
  • the gate pad electrode 130 is formed in a polygonal shape (a square shape in this embodiment) with four sides parallel to the periphery of the chip 2 in a plan view.
  • the gate pad electrode 130 has a planar area less than that of the source pad electrode 95 (first pad portion 96).
  • the gate pad electrode 130 may have a planar area less than that of the second pad portion 97 (third pad portion 98).
  • the gate pad electrode 130 is disposed on the portion covering the active region 8 and the peripheral region 9, and is connected to the gate finger electrode 115.
  • the gate pad electrode 130 may cover multiple gate electrodes 32 with the interlayer film 70 in between, or may cover the gate wiring 52 with the interlayer film 70 in between.
  • the gate pad electrode 130 includes a second base electrode film 120 and a second main electrode film 122, similar to the gate finger electrode 115.
  • the second base electrode film 120 forms a lower layer of the gate pad electrode 130 and covers the interlayer film 70 in a film-like manner.
  • the second base electrode film 120 has a layered structure including a first electrode film 123 and a second electrode film 124, similar to the gate finger electrode 115.
  • the first electrode film 123 covers the interlayer film 70 in a film-like manner
  • the second electrode film 124 covers the first electrode film 123 in a film-like manner.
  • the second main electrode film 122 forms an upper layer of the gate pad electrode 130 and covers the second base electrode film 120 in a film-like manner.
  • the gate potential applied to the gate pad electrode 130 is applied to the gate wiring 52 via the gate finger electrode 115.
  • the gate potential is transmitted to the multiple gate electrodes 32 via a wiring path (current path) along the gate wiring 52. This causes the multiple gate electrodes 32 to be turned on, controlling the on/off of the multiple channel regions 26, 27.
  • the semiconductor device 1 includes a drain pad electrode 140 covering the second main surface 4.
  • the drain pad electrode 140 is a terminal electrode to which a drain potential is applied from the outside.
  • the drain pad electrode 140 may be referred to as a "third pad electrode,” a "third main surface electrode,” a “third terminal electrode,” etc.
  • the drain pad electrode 140 is electrically connected to the second semiconductor region 7.
  • the drain pad electrode 140 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (first to fourth side surfaces 5A to 5D).
  • the drain pad electrode 140 may partially cover the second main surface 4 so as to expose the periphery of the second main surface 4.
  • the breakdown voltage that can be applied between the source pad electrode 95 and the drain pad electrode 140 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to at least one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 10 is an enlarged cross-sectional view showing the main part of FIG. 7, and shows an enlarged view of the vicinity of the electrode corner 41 of the gate electrode 32.
  • FIG. 10 explains the structure in the vicinity of the electrode corner 41B, this structure can also be applied to the structure in the vicinity of the electrode corner 41A and the structure in the vicinity of the wiring corners 61A and 61B.
  • the gate electrode 32 integrally has the electrode upper portion 33, the electrode side portions 34, 35, and the electrode corner portion 41.
  • the gate electrode 32 is formed in a shape having a protrusion portion 37 that partially protrudes upward in a cross-sectional view.
  • the gate electrode 32 may include a base portion 36 from the lower surface (contact surface with the insulating film 31) of the gate electrode 32 to the upper ends of the electrode side portions 34, 35, and a protrusion portion 37 whose width is narrowed by the electrode corner portion 41 and which forms the electrode upper portion 33.
  • the vicinity of the electrode side portions 34, 35 of the base portion 36 is selectively thin in thickness because the upper side is missing due to the electrode corner portion 41, forming a space.
  • the region in which the protrusion portion 37 is formed is a portion of the gate electrode 32 where the thickness is selectively thick.
  • the protrusion 37 overlaps the first source region 23 and the first channel region 26. This allows the thickness of the gate electrode 32 above the first channel region 26 to be increased. Therefore, even if the electrode corner 41 is formed, the resistance value of the gate electrode 32 can be kept small above the first channel region 26, thereby suppressing a decrease in the response of the switching speed.
  • the interlayer film 70 integrally has an insulating upper portion 84 that contacts the electrode upper portion 33, an insulating side portion 85 that contacts the electrode side portions 34 and 35, and an insulating corner portion 86 that contacts the electrode corner portion 41.
  • the insulating upper portion 84 extends horizontally along the electrode upper portion 33 in a film-like manner, covering the electrode upper portion 33.
  • the insulating side portion 85 rises vertically from the insulating film 31 and extends along the electrode side portions 34, 35 in a film-like manner, covering the electrode side portions 34, 35.
  • the insulating corner 86 is embedded in the electrode corner 41 formed by the recess 42 that curves inwardly of the gate electrode 32. More specifically, the insulating corner 86 has a first convex surface 87 that curves inwardly of the gate electrode 32 along the curved surface of the recess 42, and a second convex surface 88 that contacts the source pad electrode 95 on the opposite side of the first convex surface 87 and curves diagonally upwardly of the gate electrode 32. In a cross-sectional view, the insulating corner 86 has the first convex surface 87 and the second convex surface 88 that curve in both directions away from each other. As a result, the thickness of the insulating corner 86 (corner thickness T3) is thicker than the thickness of the insulating upper portion 84 (upper thickness T1) and the thickness of the insulating side portion 85 (side thickness T2).
  • the corner thickness T3 may be, for example, the thickness of the interlayer film 70 in the normal direction n of both the first tangent L1 to the first convex surface 87 and the second tangent L2 parallel to the first tangent L1 to the second convex surface 88.
  • the top thickness T1 and the side thickness T2 are, for example, 1000 ⁇ or more and 5000 ⁇ or less, and the corner thickness T3 is thicker than the top thickness T1 and the side thickness T2. Note that the corner thickness T3 only needs to be thicker than the top thickness T1 and the side thickness T2 in the total thickness of the interlayer film 70 including the first oxide film 72 and the second oxide film 73.
  • FIG. 11 is a schematic diagram showing a wafer 150 used in the manufacture of a semiconductor device 1.
  • the wafer 150 is a base material for the chip 2 and contains a SiC single crystal.
  • the wafer 150 is formed in a flat disk shape. Of course, the wafer 150 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 150 has a first wafer main surface 151 on one side, a second wafer main surface 152 on the other side, and a wafer side surface 153 connecting the first wafer main surface 151 and the second wafer main surface 152.
  • the first wafer main surface 151 corresponds to the first main surface 3 of the chip 2
  • the second wafer main surface 152 corresponds to the second main surface 4 of the chip 2.
  • the first wafer main surface 151 and the second wafer main surface 152 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 151 is formed by the silicon surface of the SiC single crystal
  • the second wafer main surface 152 is formed by the carbon surface of the SiC single crystal.
  • the wafer 150 (the first wafer main surface 151 and the second wafer main surface 152) has the off-direction and off-angle described above.
  • the wafer 150 has a mark 154 on the wafer side surface 153 that indicates the crystal orientation of the SiC single crystal.
  • the mark 154 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat is a cutout that is cut in a straight line in a plan view.
  • the orientation notch is a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 151 in a plan view.
  • the mark 154 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 154 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • the wafer 150 includes a first semiconductor region 6 in a region (surface layer) on the first wafer main surface 151 side.
  • the first semiconductor region 6 is formed in a layer extending along the first wafer main surface 151.
  • the first semiconductor region 6 is made of an epitaxial layer (specifically, a SiC epitaxial layer).
  • the wafer 150 includes a second semiconductor region 7 in the region (surface layer) on the second wafer main surface 152 side.
  • the second semiconductor region 7 is formed in a layer extending along the second wafer main surface 4, and is electrically connected to the first semiconductor region 6.
  • the second semiconductor region 7 is made of the wafer main body (specifically, a SiC wafer). That is, in this embodiment, the wafer 150 is made of an epitaxial wafer (so-called epiwafer) having a layered structure including the wafer main body and an epitaxial layer.
  • a plurality of device regions 155 and a plurality of cutting lines 156 are set on the wafer 150 by alignment marks or the like.
  • Each device region 155 is an area corresponding to a semiconductor device 1.
  • Each of the plurality of device regions 155 is set to have a rectangular shape in a plan view.
  • the multiple device regions 155 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 155 are each set at intervals inward from the periphery of the first wafer main surface 151 in a plan view.
  • the multiple cutting lines 156 are set in a lattice shape extending along the first direction X and the second direction Y to partition the multiple device regions 155.
  • FIGS. 12A to 12M are cross-sectional views showing a method for manufacturing a semiconductor device 1.
  • FIG. 12A to 12M a cross-section of a portion of an active region 8 in one device region 155 is shown.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of contact regions 25.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a termination region 45.
  • p-type impurities are selectively introduced into the surface layer of the first wafer main surface 151 by ion implantation through a mask (not shown), forming a plurality of field regions 47.
  • the order of the process of forming the body region 20, the process of forming the outer body region 21, the process of forming the source regions 23 and 24, the process of forming the contact region 25, the process of forming the termination region 45, and the process of forming the field region 47 may be arbitrary.
  • the process of forming the outer body region 21 may be performed simultaneously with the process of forming the body region 20.
  • the process of forming the field region 47 may be performed simultaneously with the process of forming the body region 20 or the process of forming the termination region 45.
  • a base insulating film 160 is formed to cover the first wafer main surface 151.
  • the base insulating film 160 is the base of the insulating film 31 and the peripheral insulating film 51.
  • the base insulating film 160 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation process (e.g., a thermal oxidation process).
  • a base electrode 161 is formed on the base insulating film 160.
  • the base electrode 161 is the base of the gate electrode 32 and the gate wiring 52.
  • the base electrode 161 includes conductive polysilicon.
  • the base electrode 161 may be formed by a CVD method.
  • the base electrode 161 has a base electrode surface 162 that extends along the base insulating film 160.
  • a mask 168 having a predetermined layout is formed on the base electrode 161 (base electrode surface 162).
  • the mask 168 may be an organic mask (e.g., a resist mask).
  • the mask 168 has a number of openings 169 that expose areas other than a number of mask portions that cover areas where a number of gate electrodes 32 are to be formed.
  • the next step is the etching step of the base electrode 161.
  • isotropic etching is performed using a mask 168, followed by anisotropic etching.
  • the base electrode 161 is isotropically removed in the thickness direction and lateral direction from the base electrode surface 162 by isotropic etching using the mask 168.
  • a recess 163 is formed in the base electrode 161 directly below the opening 169.
  • the recess 163 has recess corners 164 that curve inwardly of the base electrode 161 at both lateral ends along the first wafer main surface 151.
  • the remaining portion of the base electrode 161 is removed in the thickness direction from the bottom surface of the recess 163 to the base insulating film 160 by anisotropic etching through the mask 168.
  • This forms a plurality of gate electrodes 32, each having an electrode upper portion 33, electrode side portions 34, 35, and electrode corner portion 41.
  • the arc-shaped electrode corner portion 41 is formed by the recess corner portion 164.
  • a gate wiring 52 is formed, having a wiring upper portion 53, wiring side portions 54, 55, and wiring corner portion 61.
  • an interlayer film 70 is formed on the first wafer main surface 151.
  • an interlayer film 70 is formed having portions that directly cover the electrode upper portion 33, the first electrode side portion 34, the second electrode side portion 35, and the electrode corner portion 41 of the gate electrode 32.
  • an interlayer film 70 is formed having portions that directly cover the wiring upper portion 53, the first wiring side portion 54, the second wiring side portion 55, and the wiring corner portion 61 of the gate wiring 52.
  • the interlayer film 70 has a laminated structure including a first oxide film 72 and a second oxide film 73 (see FIG. 7).
  • the first oxide film 72 includes a silicon oxide film with no added impurities.
  • the second oxide film 73 includes a silicon oxide film containing phosphorus.
  • the first oxide film 72 may be formed by a CVD method.
  • the second oxide film 73 may be formed by a CVD method.
  • a reflow step heat treatment step
  • the corners and rough surfaces of the interlayer film 70 are smoothed.
  • a mask 174 having a predetermined layout is placed on the interlayer film 70.
  • the mask 174 exposes areas where the source openings 90, the outer openings 92, and the gate openings 94 are to be formed, and covers the other areas.
  • unnecessary portions of the interlayer film 70 and the base insulating film 160 are removed by etching through a mask 174.
  • unnecessary portions of the second oxide film 73, the first oxide film 72, and the base insulating film 160 are removed in this order.
  • the etching method may be a wet etching method and/or a dry etching method. It is preferable that the etching method is an anisotropic dry etching method (e.g., a RIE (Reactive Ion Etching) method).
  • a plurality of source openings 90, a plurality of outer openings 92, and a plurality of gate openings 94 are formed in the interlayer film 70.
  • an insulating film 31 and a peripheral insulating film 51 are formed.
  • This process may include a process of forming a plurality of source recesses 91 and a process of forming a plurality of outer recesses 93.
  • a process is performed in which the portions of the first wafer main surface 151 exposed from the plurality of source openings 90 and the plurality of outer openings 92 are further dug down toward the second wafer main surface 152.
  • the mask 174 is then removed.
  • a reflow process forms a second convex surface 88 at the upper corner of the interlayer film 70, which curves obliquely upward from the gate electrode 32.
  • the reflow conditions may be appropriately determined depending on the film thickness and film quality of the interlayer film 70, the opening width of the source opening 90, etc.
  • the first underlying electrode film 100 and the second underlying electrode film 120 are formed on the interlayer film 70.
  • the first underlying electrode film 100 and the second underlying electrode film 120 may be formed by a sputtering method or a vapor deposition method.
  • the first main electrode film 102 and the second main electrode film 122 are formed on the first base electrode film 100 and the second base electrode film 120, respectively.
  • the first main electrode film 102 and the second main electrode film 122 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film.
  • the Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.
  • the first main electrode film 102 and the second main electrode film 122 may be formed by a sputtering method or a vapor deposition method.
  • a drain pad electrode 140 is formed on the second wafer main surface 152.
  • the drain pad electrode 140 may be formed by sputtering or vapor deposition.
  • the wafer 150 is then cut along the intended cutting lines 156, and multiple semiconductor devices 1 are cut out. Through the steps including those described above, the semiconductor device 1 is manufactured.
  • multiple gate structures 30 may be arranged at a narrow pitch. Since the distance between adjacent gate structures 30 is narrow, if the interlayer film 70 is made uniformly thick to ensure the breakdown voltage, the width W of the source opening 90 for the source contact becomes very small. Reducing the width W of the source opening 90 reduces the embeddability of the metal (source pad electrode 95) in the source opening 90. If the embeddability is reduced, voids are generated at the position of the source opening 90, causing problems such as the inflow of plating solution and wire bonding failure (for example, insufficient strength during wire bonding). On the other hand, if the interlayer film 70 is made thin as a countermeasure to this problem, the thickness of the insulating corner portion 86 cannot be sufficiently secured after reflow of the interlayer film 70, and the insulation reliability between the gate and source is reduced.
  • the corner thickness T3 of the interlayer film 70 can be selectively made thicker than the top thickness T1 and the side thickness T2.
  • the insulating corner 86 is shaped into an arc like the second convex surface 88 by reflow, and even if it becomes thinner than before reflow (see FIG. 12K), a sufficient thickness of the insulating corner 86 can be secured on the electrode corner 41.
  • the side thickness T2 can be formed relatively thin, the occurrence of voids in the source opening 90 can be suppressed.
  • Figure 13 is a cross-sectional view showing a first modified example of the gate electrode 32.
  • the electrode corner 41 of the gate electrode 32 does not necessarily have to be formed in an arc shape.
  • the electrode corner 41 may be formed by a flat inclined wall 43 that slopes downward from the electrode upper portion 33 to the electrode side portions 34, 35.
  • the electrode corner 41 may also be a flat inclined wall 43 that slopes upward from the upper ends of the electrode side portions 34, 35 toward the inside in the width direction of the gate electrode 32.
  • the insulating corner 86 may have a flat surface 44 that contacts the inclined wall 43 and slopes along the inclined wall 43.
  • the thickness of the insulating corner 86 can be made thicker than the thickness of the insulating upper part 84 (upper thickness T1) and the thickness of the insulating side part 85 (side thickness T2).
  • FIGS. 14A-14B show steps involved in forming the gate electrode 32 in FIG. 13.
  • a mask 168 is formed on the base electrode 161 (base electrode surface 162) (see FIG. 12E), and then the base electrode 161 is tapered away from the base electrode surface 162 in the thickness direction by anisotropic taper etching through the mask 168.
  • the dry etching conditions can be appropriately set so that the base electrode 161 is etched obliquely rather than vertically.
  • a recess 165 is formed in the base electrode 161 directly below the opening 169.
  • the recess 165 has recess corners 166 formed by flat inclined walls that incline obliquely upward from the base electrode 161 at both lateral ends along the first wafer main surface 151.
  • the remaining portion of the base electrode 161 is removed in the thickness direction from the bottom surface of the recess 165 to the base insulating film 160 by anisotropic vertical etching using a mask 168.
  • the inclined wall 43 of the electrode corner portion 41 is formed by the recess corner portion 166.
  • FIG. 15 is a cross-sectional view showing a second modified example of a gate electrode.
  • the electrode corner 41 of the gate electrode 32 does not necessarily have to be formed in an arc shape.
  • the electrode corner 41 may be formed by a rounded portion 48 that connects the electrode upper portion 33 and the electrode side portions 34 and 35 in an arc shape that curves diagonally upward of the gate electrode 32.
  • the insulating corner 86 may have a concave surface 49 that is in contact with the rounded portion 48 and is formed in an arc shape along the rounded portion 48.
  • the concave surface 49 is a surface that curves in the same direction as the second convex surface 88 of the insulating corner 86.
  • the thickness of the insulating corner 86 can be made thicker than the thickness of the insulating upper portion 84 (upper thickness T1) and the thickness of the insulating side portion 85 (side thickness T2).
  • FIGS. 16A-16B show steps involved in forming the gate electrode 32 in FIG. 15.
  • a mask 168 is formed on the base electrode 161 (base electrode surface 162) (see FIG. 12E), and then the base electrode 161 is removed in the thickness direction from the base electrode surface 162 to the base insulating film 160 by anisotropic etching through the mask 168. This forms a plurality of gate electrodes 32 with sharp electrode corners 41.
  • a thermal oxidation process forms a thermal oxide film 50 on the surface of the gate electrode 32.
  • the thermal oxidation of the gate electrode 32 progresses vertically (longitudinal) from the electrode top 33 and horizontally (lateral) from the electrode side portions 34 and 35.
  • thermal oxidation progresses from both the vertical and lateral directions, causing the sharp corners of the electrode corner 41 to oxidize and chip, forming an arc-shaped rounded portion 48.
  • a configuration may be adopted in which the relationship between the a-axis direction and the m-axis direction is interchanged.
  • a specific configuration in this case can be obtained by interchanging the "a-axis direction (off direction)" and the "m-axis direction (direction perpendicular to the off direction)" in the above description and the accompanying drawings.
  • the chip 2 (first semiconductor region 6 and second semiconductor region 7) containing SiC single crystal is used.
  • the chip 2 (first semiconductor region 6 and second semiconductor region 7) may contain a single crystal of a wide band gap semiconductor other than SiC single crystal.
  • a wide band gap semiconductor is a semiconductor that has a band gap larger than the band gap of silicon. Examples of single crystals of wide band gap semiconductors include gallium nitride, diamond, and gallium oxide.
  • the chip 2 (first semiconductor region 6 and second semiconductor region 7) may contain silicon single crystal.
  • an n-type second semiconductor region 7 is shown.
  • a p-type second semiconductor region 7 may be used instead of the n-type second semiconductor region 7.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type second semiconductor region 7 may be an impurity region containing p-type impurities introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.
  • the interlayer film (70) includes an insulating upper portion (84) in contact with the electrode upper portion (33), an insulating side portion (85) in contact with the electrode side portions (34, 35), and an
  • multiple gate electrodes (32) may be arranged at a narrow pitch. Since the distance between adjacent gate electrodes (32) is narrow, if the interlayer film (70) is made uniformly thick to ensure voltage resistance, the width of the opening (90) exposing the contact surface becomes very small. Reducing the width of the opening (90) reduces the embeddability of metal into the opening (90). If the embeddability is reduced, voids are generated at the position of the opening (90), causing problems such as the inflow of plating solution and wire bonding defects (for example, insufficient strength during wire bonding). On the other hand, if the interlayer film (70) is made thin to address this issue, the thickness of the insulating corner portion (86) cannot be sufficiently secured after reflow of the interlayer film (70), and the insulation reliability is reduced.
  • the corner thickness (T3) of the interlayer film (70) can be selectively made thicker than the top thickness (T1) and the side thickness (T2).
  • the insulating corners (86) become thinner after the opening (90) is formed than before reflow, a sufficiently thick insulating corner (86) can be secured on the electrode corners (41).
  • the side thickness (T2) can be formed relatively thin, the occurrence of voids in the opening (90) can be suppressed.
  • the insulating corner portion (86) has a first convex surface (87) that curves inwardly of the gate electrode (32) along the curved surface of the recess (42),
  • the semiconductor device (1) according to appendix 1-2, wherein the corner thickness (T3) includes a thickness of the interlayer film (70) in a normal direction (n) of a tangent (L1) to the first convex surface (87).
  • the insulating corner portion (86) has a first convex surface (87) that curves inwardly of the gate electrode (32) along the curved surface of the recess (42), and a second convex surface (88) that contacts the surface electrode (95) on the opposite side of the first convex surface (87) and curves obliquely upwardly of the gate electrode (32);
  • Electrode corner portion (41) includes a round portion (48) that connects the electrode upper portion (33) and the electrode side portions (34, 35) in an arc shape that curves obliquely upward from the gate electrode (32).
  • the gate electrode (32) is arranged on the main surface (3) at intervals, The semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-6, wherein the opening (90) is defined in a region between a plurality of the gate electrodes (32).
  • the opening (90) has a vertical aspect ratio (D/W) along a depth direction of the opening (90),
  • the semiconductor device (1) according to any one of Appendix 1-1 to Appendix 1-7, wherein the corner thickness (T3) is greater than both the top thickness (T1) and the side thickness (T2).
  • Appendix 1-10 The semiconductor device (1) according to any one of Appendix 1-1 to Appendix 1-9, wherein the width of the opening (90) is 0.2 ⁇ m or more and 3 ⁇ m or less, and the depth of the opening (90) is 0.2 ⁇ m or more and 2 ⁇ m or less.
  • the interlayer film (70) includes a first oxide film (72) containing no impurities and covering the gate electrode (32), and a second oxide film (73) containing phosphorus and covering the first oxide film (72);
  • the semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-10, wherein the opening (90) penetrates both the first oxide film (72) and the second oxide film (73).
  • the opening (90) exposes a portion of the impurity region (23, 24) to the contact surface;
  • the semiconductor device (1) according to any one of Supplementary Notes 1-1 to 1-11, wherein the surface electrode (95) is electrically connected to the impurity region (23, 24) within the opening (90).
  • Appendix 1-13 The semiconductor device (1) according to any one of Appendices 1-1 to 1-12, wherein the chip (2) is a SiC chip (2).
  • [Appendix 1-14] forming a base electrode (161) on a major surface (151) of the wafer (150); a step of selectively isotropically etching the base electrode (161) in a thickness direction, followed by anisotropically etching the base electrode (161), thereby forming a gate electrode (32) having an electrode upper portion (33) along the main surface (151), electrode side portions (34, 35) rising from the main surface (151), and an electrode corner portion (41) including an arc-shaped recess (42) that connects the electrode upper portion (33) and the electrode side portions (34, 35) and curves inwardly of the base electrode (161); forming an interlayer film (70) on the main surface (151) so as to cover the gate electrode (32); forming an opening (90) in the interlayer film (70) that exposes a portion of the main surface (151) as a contact surface, the opening (90) being spaced apart from the electrode side portions (34, 35) in a lateral direction along the main surface (151); forming a surface
  • [Appendix 1-15] forming a base electrode (161) on a major surface (151) of the wafer (150); a step of selectively anisotropically taper etching the base electrode (161) in a thickness direction, followed by anisotropically vertical etching, to form a gate electrode (32) having an electrode upper portion (33) along the main surface (151), electrode side portions (34, 35) rising from the main surface (151), and an electrode corner portion (41) including a flat inclined wall (43) connecting the electrode upper portion (33) and the electrode side portions (34, 35) and inclining downward from the electrode upper portion (33) to the electrode side portions (34, 35); forming an interlayer film (70) on the main surface (151) so as to cover the gate electrode (32); forming an opening (90) in the interlayer film (70) that exposes a portion of the main surface (151) as a contact surface, the opening (90) being spaced apart from the electrode side portions (34, 35) in a lateral direction along the main surface (151); forming a
  • a base electrode (161) comprising polysilicon on a main surface (151) of the wafer (150); a step of selectively anisotropically etching the base electrode (161) in a thickness direction to form a gate electrode (32) having an electrode upper portion (33) along the main surface (151), electrode side portions (34, 35) rising from the main surface (151), and electrode corner portions (41) connecting the electrode upper portion (33) and the electrode side portions (34, 35); a step of thermally oxidizing the gate electrode (32) to form a rounded portion (48) having an arc shape curved obliquely upward of the gate electrode (32) at the electrode corner portion (41); forming an interlayer film (70) on the main surface (151) so as to cover the gate electrode (32); forming an opening (90) in the interlayer film (70) that exposes a portion of the main surface (151) as a contact surface, the opening (90) being spaced apart from the electrode side portions (34, 35) in a lateral direction along the
  • Appendix 1-17 A method for manufacturing a semiconductor device (1) according to any one of Appendices 1-14 to 1-16, comprising a step of forming a convex surface (88) curved obliquely upward of the gate electrode (32) at an upper corner of the opening (90) in the interlayer film (70) by reflow processing.

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
PCT/JP2024/007383 2023-03-20 2024-02-28 半導体装置および半導体装置の製造方法 Ceased WO2024195461A1 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN202480018646.4A CN120958968A (zh) 2023-03-20 2024-02-28 半导体装置以及半导体装置的制造方法
JP2025508264A JPWO2024195461A1 (https=) 2023-03-20 2024-02-28
DE112024001317.1T DE112024001317T5 (de) 2023-03-20 2024-02-28 Halbleiterbauteil und herstellungsverfahren für ein halbleiterbauteil
US19/325,873 US20260013201A1 (en) 2023-03-20 2025-09-11 Semiconductor device and semiconductor device production method

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2023-044003 2023-03-20
JP2023044003 2023-03-20

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US19/325,873 Continuation US20260013201A1 (en) 2023-03-20 2025-09-11 Semiconductor device and semiconductor device production method

Publications (1)

Publication Number Publication Date
WO2024195461A1 true WO2024195461A1 (ja) 2024-09-26

Family

ID=92841794

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2024/007383 Ceased WO2024195461A1 (ja) 2023-03-20 2024-02-28 半導体装置および半導体装置の製造方法

Country Status (5)

Country Link
US (1) US20260013201A1 (https=)
JP (1) JPWO2024195461A1 (https=)
CN (1) CN120958968A (https=)
DE (1) DE112024001317T5 (https=)
WO (1) WO2024195461A1 (https=)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175124A (ja) * 1983-03-24 1984-10-03 Toshiba Corp 半導体装置の製造方法
JPS61296740A (ja) * 1985-06-25 1986-12-27 Nec Kansai Ltd 半導体装置
JPH05198589A (ja) * 1992-01-23 1993-08-06 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
JP2005347313A (ja) * 2004-05-31 2005-12-15 Denso Corp 半導体装置の製造方法
JP2011109021A (ja) * 2009-11-20 2011-06-02 Renesas Electronics Corp 半導体装置
JP2016058726A (ja) * 2014-09-04 2016-04-21 パナソニックＩｐマネジメント株式会社 半導体装置およびその製造方法
JP2018174357A (ja) * 2018-08-09 2018-11-08 ローム株式会社 半導体装置
JP2019087730A (ja) * 2017-11-08 2019-06-06 富士電機株式会社 半導体装置

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59175124A (ja) * 1983-03-24 1984-10-03 Toshiba Corp 半導体装置の製造方法
JPS61296740A (ja) * 1985-06-25 1986-12-27 Nec Kansai Ltd 半導体装置
JPH05198589A (ja) * 1992-01-23 1993-08-06 Seiko Epson Corp 半導体装置及び半導体装置の製造方法
JP2005347313A (ja) * 2004-05-31 2005-12-15 Denso Corp 半導体装置の製造方法
JP2011109021A (ja) * 2009-11-20 2011-06-02 Renesas Electronics Corp 半導体装置
JP2016058726A (ja) * 2014-09-04 2016-04-21 パナソニックＩｐマネジメント株式会社 半導体装置およびその製造方法
JP2019087730A (ja) * 2017-11-08 2019-06-06 富士電機株式会社 半導体装置
JP2018174357A (ja) * 2018-08-09 2018-11-08 ローム株式会社 半導体装置

Also Published As

Publication number Publication date
DE112024001317T5 (de) 2025-12-31
CN120958968A (zh) 2025-11-14
JPWO2024195461A1 (https=) 2024-09-26
US20260013201A1 (en) 2026-01-08

Similar Documents

Publication Publication Date Title
JP7796181B2 (ja) 半導体装置
JP2025100881A (ja) 半導体装置の製造方法
TWI838353B (zh) 半導體裝置
JP2022166265A (ja) ＳｉＣ半導体装置
WO2024195461A1 (ja) 半導体装置および半導体装置の製造方法
WO2024202942A1 (ja) 半導体装置
US20260032949A1 (en) Semiconductor device and manufacturing method for semiconductor device
WO2024257527A1 (ja) 半導体装置および半導体装置の製造方法
US20260090057A1 (en) Semiconductor device and method for manufacturing same
WO2025004543A1 (ja) 半導体装置
WO2025018065A1 (ja) 半導体装置
WO2025018064A1 (ja) 半導体装置
WO2025205020A1 (ja) 半導体装置および半導体装置の製造方法
WO2024203339A1 (ja) 半導体装置
WO2024204492A1 (ja) 半導体装置およびその製造方法
WO2026058817A1 (ja) 半導体装置および半導体装置の製造方法
WO2025023129A1 (ja) 半導体装置
WO2025023128A1 (ja) 半導体装置
WO2024204491A1 (ja) 半導体装置
WO2024252971A1 (ja) 半導体装置
JP2024171896A (ja) 半導体装置
WO2025013769A1 (ja) 半導体装置
WO2026034353A1 (ja) 半導体装置
JP2026053873A (ja) 半導体装置
WO2025197728A1 (ja) 半導体装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 24774606

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2025508264

Country of ref document: JP

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 2025508264

Country of ref document: JP

WWE Wipo information: entry into national phase

Ref document number: 112024001317

Country of ref document: DE

WWP Wipo information: published in national office

Ref document number: 112024001317

Country of ref document: DE

122 Ep: pct application non-entry in european phase

Ref document number: 24774606

Country of ref document: EP

Kind code of ref document: A1