WO2024188136A1 - 用于监测电子电路的电源电压的装置、方法和电子电路 - Google Patents

用于监测电子电路的电源电压的装置、方法和电子电路 Download PDF

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Publication number
WO2024188136A1
WO2024188136A1 PCT/CN2024/080407 CN2024080407W WO2024188136A1 WO 2024188136 A1 WO2024188136 A1 WO 2024188136A1 CN 2024080407 W CN2024080407 W CN 2024080407W WO 2024188136 A1 WO2024188136 A1 WO 2024188136A1
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Prior art keywords
signal
frequency
critical timing
generate
control signal
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PCT/CN2024/080407
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English (en)
French (fr)
Inventor
郭俊彦
董威锋
张明明
张闯
张俊谋
卢山
王剑
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Beijing Youzhuju Network Technology Co Ltd
Lemon Inc Cayman Island
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Beijing Youzhuju Network Technology Co Ltd
Lemon Inc Cayman Island
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Publication of WO2024188136A1 publication Critical patent/WO2024188136A1/zh
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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16566—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533
    • G01R19/16576—Circuits and arrangements for comparing voltage or current with one or several thresholds and for indicating the result not covered by subgroups G01R19/16504, G01R19/16528, G01R19/16533 comparing DC or AC voltage with one threshold
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0003—Details of control, feedback or regulation circuits
    • H02M1/0012—Control circuits using digital or numerical techniques
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/165—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values
    • G01R19/16533—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application
    • G01R19/16538—Indicating that current or voltage is either above or below a predetermined value or within or outside a predetermined range of values characterised by the application in AC or DC supplies
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
    • G01R25/005—Circuits for comparing several input signals and for indicating the result of this comparison, e.g. equal, different, greater, smaller, or for passing one of the input signals as output signal
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/40—Testing power supplies
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/00006—Changing the frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00078—Fixed delay

Definitions

  • Example embodiments of the present disclosure generally relate to the field of electronic circuits, and more particularly to an apparatus, method, and electronic circuit for monitoring a power supply voltage of an electronic circuit.
  • clock signals are used to coordinate the actions of various electronic components to ensure that related electronic components can operate synchronously.
  • digital circuits will draw current from the power supply network when working, causing power supply fluctuations. When the drawn current is too large, it may cause a momentary drop in the power supply voltage. If the power supply voltage drops too much, the timing requirements of the digital circuit cannot be met, and timing errors will occur, resulting in digital circuit operation errors and digital circuit lockouts.
  • An object of the present disclosure is to provide an apparatus, a method and an electronic circuit for monitoring the power supply voltage of an electronic circuit to at least partially solve the above problems and other potential problems.
  • a device for monitoring a power supply voltage of an electronic circuit comprising: a voltage regulator configured to process the power supply voltage to generate a preset voltage; a critical timing generation module powered by the preset voltage and configured to A control signal adjustment module is configured to generate a critical timing signal based on an original clock signal and a delay control signal, wherein the critical timing signal is alternately in a first level state and a second level state; a control signal adjustment module is configured to adjust the delay control signal based on the critical timing signal, wherein when the critical timing signal is in the first level state, the delay control signal is increased, and when the critical timing signal is in the second level state, the delay control signal is decreased; and a power drop sensing module is powered by the power supply voltage and is configured to generate a drop indication signal based on the original clock signal and the delay control signal, wherein the drop indication signal indicates whether the power supply voltage drops below the preset voltage.
  • a method for monitoring the power supply voltage of an electronic circuit comprising: processing the power supply voltage to generate a preset voltage; generating a critical timing signal based on an original clock signal and a delay control signal at the preset voltage, the critical timing signal being alternately in a first level state and a second level state; adjusting the delay control signal based on the critical timing signal, wherein when the critical timing signal is in the first level state, the delay control signal is increased, and when the critical timing signal is in the second level state, the delay control signal is decreased; and generating a drop indication signal based on the original clock signal and the delay control signal at the power supply voltage, the drop indication signal indicating whether the power supply voltage drops below the preset voltage.
  • an electronic circuit comprising the apparatus according to the first aspect of the present disclosure.
  • FIG1 shows a block diagram of an apparatus for monitoring a power supply voltage of an electronic circuit according to an embodiment of the present disclosure
  • FIG2 shows a circuit schematic diagram of a device for monitoring a power supply voltage of an electronic circuit according to an embodiment of the present disclosure
  • FIG3 shows curves of a power supply voltage, a preset voltage, a state machine lock signal, a critical timing signal, and a drop indication signal according to an embodiment of the present disclosure
  • FIG. 4 shows a flow chart of a method for monitoring a power supply voltage of an electronic circuit according to an embodiment of the present disclosure.
  • the embodiment of the present disclosure provides a scheme for monitoring the power supply voltage of an electronic circuit, in which the timing of a digital logic circuit is in a critical error state under a stable preset voltage, while another similar digital logic circuit is operated under the power supply voltage to be monitored. When the power supply voltage to be monitored is lower than the preset voltage, the other digital logic circuit will generate a signal indicating that the power supply voltage has dropped. In this way, the drop of the power supply voltage can be accurately monitored so that the electronic circuit can take corresponding countermeasures to avoid timing errors caused by the power drop.
  • the principle of the present disclosure will be described in detail below in conjunction with Figures 1 to 4.
  • Fig. 1 shows a block diagram of a device for monitoring the power supply voltage of an electronic circuit according to an embodiment of the present disclosure
  • Fig. 2 shows a circuit schematic diagram of a device for monitoring the power supply voltage of an electronic circuit according to an embodiment of the present disclosure.
  • the device described herein generally includes a voltage regulator 10, a critical timing generation module 20, a control signal adjustment module 30, and a power drop sensing module 40.
  • the voltage regulator 10 is used to process the power supply voltage vdd to generate a preset voltage vdroop.
  • the preset voltage vdroop can be a voltage preset according to the design requirements of the electronic circuit, which is used as the limit value of the power drop to be monitored. That is, when the power supply voltage vdd is above the preset voltage vdroop, it means that the timing requirements of the electronic circuit can be basically met; and when the power supply voltage vdd drops below the preset voltage vdroop, it means that the timing requirements of the digital circuit cannot be met, and a timing error may occur. Whether the power supply voltage vdd drops below the preset voltage vdroop can be monitored by the critical timing generation module 20, the control signal adjustment module 30 and the power drop sensing module 40, which will be described in detail below.
  • the preset voltage vdroop may be preset to 0.8V.
  • the preset voltage vdroop may also be set to be higher or lower than 0.8V.
  • the voltage regulator 10 may use any appropriate voltage regulation technology to process the power supply voltage vdd.
  • the voltage regulator 10 may include a low dropout linear regulator (LDO), as shown in FIG2 .
  • the LDO includes a low-pass filter 101, an amplifier 102, a transistor 103, and a capacitor 104.
  • the low-pass filter 101 is used to perform low-pass filtering on the power supply voltage vdd to filter out high-frequency components in the power supply voltage vdd, thereby generating a filtered voltage vref.
  • the filtered voltage vref is provided to a first input terminal of the amplifier 102.
  • the transistor 103 and the capacitor 104 are connected in series between the power supply voltage vdd and ground.
  • the transistor 103 may be a metal oxide semiconductor field effect transistor (MOSFET) or other types of switching devices, which is not limited in the embodiments of the present disclosure.
  • the control terminal of the transistor 103 is connected to the output terminal of the amplifier 102.
  • the intermediate node between the transistor 103 and the capacitor 104 is connected to the second input terminal of the amplifier 102.
  • the preset voltage vdroop is provided by the intermediate node between the transistor 103 and the capacitor 104. With this arrangement, the voltage regulator 10 can provide a stable preset voltage vdroop, which is substantially unaffected by fluctuations in the power supply voltage vdd.
  • FIG3 shows a curve 301 of the power supply voltage vdd and a curve 302 of the preset voltage vdroop according to an embodiment of the present disclosure.
  • the power supply voltage vdd fluctuates up and down, while the preset voltage vdroop is at a substantially stable level.
  • the curve 301 of the power supply voltage vdd includes a plurality of drop portions 3011, 3012, 3013 that are lower than the preset voltage vdroop. Each drop wavelength in the plurality of drop portions 3011, 3012, 3013 will be monitored by the critical timing generation module 20, the control signal adjustment module 30, and the power supply drop sensing module 40, which will be described in detail below.
  • the critical timing generation module 20 is connected to the output end of the regulator 10 so as to be powered by a preset voltage vdroop. That is, the critical timing generation module 20 operates at a preset voltage vdroop.
  • the critical timing generation module 20 is used to generate a critical timing signal DIR based on the original clock signal clk and the delay control signal cal_code provided by the control signal adjustment module 30.
  • the original clock signal clk can have any appropriate duty cycle, for example, the duty cycle can be 50%. Of course, it is also feasible that the duty cycle of the original clock signal clk is higher or lower than 50%.
  • the delay control signal cal_code is provided by the control signal adjustment module 30 to control the delay amount of the delay unit in the critical timing generation module 20, for example, to control the delay amount of the first delay unit 202, which will be described in detail below.
  • the critical timing signal DIR generated by the critical timing generation module 20 can be alternately in the first level state and the second level state.
  • the first level state and the second level state are relative level states. In one embodiment, the first level state is a high level state, and the second level state is a low level state. In another embodiment, the first level state is a low level state, and the second level state is a high level state.
  • the critical timing signal DIR alternately being in the first level state and the second level state means that the timing of the critical timing generation module 20 under the preset voltage vdroop is in a critical error state.
  • the timing of the critical timing generation module 20 under the preset voltage vdroop can meet the requirements, but there is no more adjustment margin. If the operating voltage of the critical timing generation module 20 is lower than the preset voltage vdroop, a timing error will occur in the critical timing generation module 20.
  • the principle of the present disclosure is described below by taking the first level state being a high level state and the second level state being a low level state as an example.
  • the critical timing generation module 20 includes a first frequency divider 201 , a first delay unit 202 and a timing determination unit 203 .
  • the first frequency divider 201 is used to divide the original clock signal clk to generate a first frequency-divided signal clk_div1.
  • the first frequency divider 201 may have any appropriate frequency-dividing ratio, such as divide-by-two, divide-by-four, etc.
  • the first frequency-divided signal clk_div1 generated by the first frequency divider 201 will have a duty cycle of 50%.
  • the first delay unit 202 is used to delay the first frequency-divided signal clk_div1 to generate a first delayed signal clk_div_dly1.
  • the delay amount provided by the first delay unit 202 is controlled by the delay control signal cal_code. In theory, when the delay control signal cal_code is 0, the delay amount provided by the first delay unit 202 is 0. The larger the delay control signal cal_code is, the larger the delay amount provided by the first delay unit 202 is. On the contrary, the smaller the delay control signal cal_code is, the smaller the delay amount provided by the first delay unit 202 is.
  • the timing determination unit 203 is used to generate a critical timing signal DIR based on the phase relationship between the first frequency division signal clk_div1 and the first delay signal clk_div_dly1.
  • the timing determination unit 203 may include a first phase detector 2031 and a first inverter. Phase detector 2032.
  • the first phase detector 2031 is used to identify the phase difference between the first frequency division signal clk_div1 and the first delayed signal clk_div_dly1 to generate a first phase detection signal P1 for indicating the phase difference.
  • the first phase detection signal P1 is inverted by the first inverter 2032 to generate a first inverted signal P1_B.
  • the first inverted signal P1_B is used as a critical timing signal DIR.
  • the critical timing signal DIR is in a low level state, that is, a second level state.
  • the critical timing signal DIR is in a high level state, that is, a first level state.
  • the first phase-lock signal P1 can also be used as the critical timing signal DIR.
  • the first level state will be a low level state
  • the second level state will be a high level state.
  • the critical timing signal DIR is in a high level state, that is, the second level state.
  • the critical timing signal DIR is in a low level state, that is, the first level state.
  • a curve 304 of a critical timing signal DIR according to an embodiment of the present disclosure is shown in FIG3.
  • the critical timing signal DIR is alternately in a first level state and a second level state, wherein the first level state is one of a high level state and a low level state, and the second level state is the other of a high level state and a low level state.
  • the control signal adjustment module 30 is used to adjust the delay control signal cal_code based on the critical timing signal DIR to dynamically adjust the delay amount provided by the first delay unit 202.
  • the delay control signal cal_code is increased, and in the case where the critical timing signal DIR is in the second level state, the delay control signal cal_code is reduced.
  • the critical timing signal DIR being in the first level state means that the phases of the first frequency division signal clk_div1 and the first delay signal clk_div_dly1 do not reach a phase difference of half a cycle
  • the critical timing signal DIR being in the second level state means that the phases of the first frequency division signal clk_div1 and the first delay signal clk_div_dly1 differ by half a cycle.
  • increasing the delay control signal cal_code will increase the delay amount provided by the first delay unit 202.
  • the critical timing signal DIR can be alternately in the first level state and the second level state. That is, by dynamically adjusting the delay control signal cal_code according to the critical timing signal DIR, the timing of the critical timing generation module 20 under the preset voltage vdroop can be in a critical error state.
  • the control signal adjustment module 30 includes a digital state machine, which has a first adjustment state for increasing the delay control signal cal_code and a second adjustment state for reducing the delay control signal cal_code.
  • the digital state machine When the critical timing signal DIR is in the first level state, the digital state machine will switch to the first adjustment state to increase the delay amount provided by the first delay unit 202.
  • the critical timing signal DIR When the critical timing signal DIR is in the second level state, the digital state machine will switch to the second adjustment state to reduce the delay amount provided by the first delay unit 202.
  • FIG. 3 also shows a curve 303 of the state machine lock signal. As shown in FIG.
  • the state machine lock signal when the critical timing signal DIR changes alternately, the state machine lock signal will be enabled, so that the digital state machine cyclically switches between the first adjustment state and the second adjustment state.
  • the pulse width of the critical timing signal DIR changes dynamically, because by dynamically adjusting the delay control signal cal_code, the process-voltage-temperature (PVT) deviation of the electronic circuit can be resisted.
  • the power drop sensing module 40 is powered by the power supply voltage vdd. That is, the power drop sensing module 40 operates under the power supply voltage vdd.
  • the drop sensing module 40 is connected to the control signal adjustment module 30 to receive the delayed control signal cal_code generated by the control signal adjustment module 30.
  • the power drop sensing module 40 is used to generate a drop indication signal ERR based on the original clock signal clk and the delayed control signal cal_code.
  • the drop indication signal ERR indicates whether the power supply voltage vdd drops below the preset voltage vdroop.
  • the timing of the critical timing generation module 20 under the preset voltage vdroop can meet the requirements, but there is no more adjustment margin; if the operating voltage of the critical timing generation module 20 is lower than the preset voltage vdroop, the critical timing generation module 20 will have a timing error.
  • the drop indication signal ERR can be used as an alarm signal to instruct the electronic circuit to take corresponding countermeasures to avoid timing errors caused by power drops.
  • the power drop sensing module 40 includes a second frequency divider 401 , a second delay unit 402 and a power drop determining module 403 .
  • the second frequency divider 401 is used to divide the original clock signal clk to generate a second frequency-divided signal clk_div2.
  • the second frequency divider 401 can have any appropriate frequency-dividing ratio, such as two-dividing, four-dividing, etc.
  • the second frequency-dividing signal clk_div2 generated by the second frequency divider 401 will have a duty cycle of 50%.
  • the second frequency divider 401 and the first frequency divider 201 can have the same frequency-dividing ratio.
  • the second delay unit 402 is used to delay the second frequency-divided signal clk_div2 to generate a second delayed signal clk_div_dly2.
  • the delay amount provided by the second delay unit 402 is also controlled by the delay control signal cal_code. Since the same delay control signal cal_code is provided to the first delay unit 202 and the second delay unit 402, the first delay unit 202 and the second delay unit 402 have similar delay characteristics.
  • the larger the delay control signal cal_code the larger the delay amount provided by the second delay unit 402.
  • the smaller the delay control signal cal_code the smaller the delay amount provided by the second delay unit 402.
  • the second delay unit 402 and the first delay unit 202 may have the same circuit structure.
  • the second delay unit 402 The delay amount provided by the first delay unit 202 may vary substantially synchronously with the delay control signal cal_code.
  • the delay amount of the delay unit is also related to its operating voltage. The higher the operating voltage, the smaller the delay amount provided by the delay unit, and the lower the operating voltage, the larger the delay amount provided by the delay unit. Therefore, if the power supply voltage vdd is higher than the preset voltage vdroop at a certain moment, the delay amount provided by the second delay unit 402 will be lower than the delay amount provided by the first delay unit 202. On the contrary, if the power supply voltage vdd is lower than the preset voltage vdroop at a certain moment, the delay amount provided by the second delay unit 402 will be higher than the delay amount provided by the first delay unit 202.
  • the power drop determination module 403 is used to generate a drop indication signal ERR based on the phase relationship between the second frequency division signal clk_div2 and the second delayed signal clk_div_dly2.
  • the power drop determination module 403 may include a second phase detector 4031 and a second inverter 4032.
  • the second phase detector 4031 is used to identify the phase difference between the second frequency division signal clk_div2 and the second delayed signal clk_div_dly2 to generate a second phase detection signal P2 for indicating the phase difference.
  • the second phase detection signal P2 is inverted by the second inverter 4032 to generate a second inverted signal P2_B.
  • the second phase-detection signal P2 will be in a low level state, and the second inverted signal P2_B will be in a high level state.
  • the delay amount provided by the second delay unit 402 will be lower than the delay amount provided by the first delay unit 202, so that the phases of the second frequency-divided signal clk_div2 and the second delayed signal clk_div_dly2 do not differ by half a cycle, and thus the second phase-detection signal P2 will be in a low level state, and the second inverted signal P2_B will be in a high level state.
  • the second phase-detection signal P2 will be in a high level state, and the second inverted signal P2_B will be in a low level state.
  • the delay amount provided by the second delay unit 402 will be higher than the delay amount provided by the first delay unit 202, so that the phase difference between the second frequency-divided signal clk_div2 and the second delayed signal clk_div_dly2 is greater than that between the first delay unit 202 and the second frequency-divided signal clk_div_dly2.
  • the second bit has experienced a phase difference of half a period, so the second phase detection signal P2 will appear in a high level state, and the second inverted signal P2_B will appear in a low level state.
  • the second phase detection signal P2 is used as a drop indication signal ERR.
  • the drop indication signal ERR when the power supply voltage vdd is higher than the preset voltage vdroop, the drop indication signal ERR will be in a low level state, and when the power supply voltage vdd drops below the preset voltage vdroop, the drop indication signal ERR will appear in a high level state. As shown in FIG3 , when the power supply voltage vdd is higher than the preset voltage vdroop, the drop indication signal ERR will be in a low level state.
  • the drop indication signal ERR will appear in multiple abnormal indication portions 3051, 3052, 3053 with a high level state. In this way, the drop of the power supply voltage vdd can be accurately monitored so that the electronic circuit can take corresponding countermeasures to avoid timing errors caused by power drop.
  • the second inverted signal P2_B is used as the drop indication signal ERR.
  • the drop indication signal ERR when the power supply voltage vdd is higher than the preset voltage vdroop, the drop indication signal ERR will be in a high level state, and when the power supply voltage vdd drops below the preset voltage vdroop, the drop indication signal ERR will appear in a low level state. With such an embodiment, the drop of the power supply voltage vdd can also be accurately monitored.
  • the embodiment of the present disclosure also provides a method 400 for monitoring the power supply voltage of an electronic circuit, as shown in FIG4.
  • the method 400 can be performed by the device for monitoring the power supply voltage of an electronic circuit described above in combination with FIG1 to FIG3.
  • the method 400 includes: in box 410, processing the power supply voltage vdd to generate a preset voltage vdroop; in box 420, under the preset voltage vdroop, generating a critical timing signal DIR based on the original clock signal clk and the delay control signal cal_code, and the critical timing signal DIR is alternately in a first level state and a second level state; in box 430, adjusting the delay control signal cal_code based on the critical timing signal DIR, wherein when the critical timing signal DIR is in the first level state, the delay control signal cal_code is increased, and when the critical timing signal DIR is in the second level state, the delay control signal cal_code is reduced; and in box 440, under the power supply voltage vd
  • generating a critical timing signal DIR based on an original clock signal clk and a delay control signal cal_code includes: dividing the original clock signal clk to generate a first divided signal clk_div1; delaying the first divided signal clk_div1 to generate a first delayed signal clk_div_dly1, wherein the delay amount of the first divided signal clk_div1 is controlled by the delay control signal cal_code; and generating the critical timing signal DIR based on a phase relationship between the first divided signal clk_div1 and the first delayed signal clk_div_dly1, wherein when the phase difference between the first divided signal clk_div1 and the first delayed signal clk_div_dly1 is half a cycle, the critical timing signal DIR is in a second level state, and when the phase difference between the first divided signal clk_div1 and the first delayed signal clk_div_dly1 does not reach half a
  • generating the critical timing signal DIR based on the phase relationship between the first frequency-divided signal clk_div1 and the first delayed signal clk_div_dly1 includes: identifying the phase difference between the first frequency-divided signal clk_div1 and the first delayed signal clk_div_dly1 to generate a first phase-lock signal P1 for representing the phase difference, wherein the first phase-lock signal P1 or an inverted signal of the first phase-lock signal P1 is used as the critical timing signal DIR.
  • generating a drop indication signal ERR based on an original clock signal clk and a delay control signal cal_code includes: dividing the original clock signal clk to generate a second divided signal clk_div2; delaying the second divided signal clk_div2 to generate a second delayed signal clk_div_dly2, wherein the delay amount of the second divided signal clk_div2 is controlled by the delay control signal cal_code; and generating the drop indication signal ERR based on a phase relationship between the second divided signal clk_div2 and the second delayed signal clk_div_dly2.
  • generating the drop indication signal ERR based on the phase relationship between the second frequency division signal clk_div2 and the second delayed signal clk_div_dly2 includes: identifying the phase difference between the second frequency division signal clk_div2 and the second delayed signal clk_div_dly2 to generate a second phase detection signal P2 for indicating the phase difference, wherein the second phase detection signal P2 Or the inverted signal of the second phase detection signal P2 is used as the drop indication signal ERR.
  • the adjustment of the delay control signal cal_code is implemented by a digital state machine, which includes a first adjustment state for increasing the delay control signal cal_code and a second adjustment state for reducing the delay control signal cal_code, wherein when the critical timing signal DIR is in a first level state, the digital state machine switches to the first adjustment state, and when the critical timing signal DIR is in a second level state, the digital state machine switches to the second adjustment state.
  • Embodiments of the present disclosure are also embodied in the following examples.
  • Example 1 An apparatus for monitoring a power supply voltage of an electronic circuit, comprising:
  • a voltage regulator configured to process the power supply voltage to generate a preset voltage
  • a critical timing generation module powered by the preset voltage and configured to generate a critical timing signal based on the original clock signal and the delay control signal, wherein the critical timing signal is alternately in a first level state and a second level state;
  • control signal adjustment module configured to adjust the delay control signal based on the critical timing signal, wherein when the critical timing signal is in the first level state, the delay control signal is increased, and when the critical timing signal is in the second level state, the delay control signal is decreased;
  • a power drop sensing module is powered by the power supply voltage and is configured to generate a drop indication signal based on the original clock signal and the delay control signal, wherein the drop indication signal indicates whether the power supply voltage drops below the preset voltage.
  • Example 2 The apparatus according to Example 1, wherein the critical timing generation module comprises:
  • a first frequency divider configured to divide the original clock signal to generate a first frequency-divided signal
  • a first delay unit is configured to delay the first frequency-divided signal to generate a first delayed signal, wherein the delay amount provided by the first delay unit is controlled by the delay control signal;
  • the timing determination unit is configured to generate the critical timing signal based on the phase relationship between the first frequency-divided signal and the first delayed signal, wherein the first frequency-divided signal When the phase difference between the first frequency-divided signal and the first delayed signal is half a cycle, the critical timing signal is in the second level state, and when the phase difference between the first frequency-divided signal and the first delayed signal does not reach half a cycle, the critical timing signal is in the first level state.
  • Example 3 The apparatus of Example 2, wherein the timing determination unit comprises:
  • a first phase detector is configured to identify a phase difference between the first frequency-divided signal and the first delayed signal to generate a first phase detection signal representing the phase difference, wherein the first phase detection signal or an inverted signal of the first phase detection signal is used as the critical timing signal.
  • Example 4 The apparatus of Example 2, wherein the power drop sensing module comprises:
  • a second frequency divider is configured to divide the original clock signal to generate a second frequency-divided signal
  • a second delay unit configured to delay the second frequency-divided signal to generate a second delayed signal, wherein the delay amount provided by the second delay unit is controlled by the delay control signal;
  • the power drop determination module is configured to generate the power drop indication signal based on a phase relationship between the second frequency-divided signal and the second delayed signal.
  • Example 5 The apparatus of Example 4, wherein the power drop determination module comprises:
  • the second phase detector is configured to identify the phase difference between the second frequency-divided signal and the second delayed signal to generate a second phase detection signal representing the phase difference, wherein the second phase detection signal or an inverted signal of the second phase detection signal is used as the drop indication signal.
  • Example 6 The apparatus of Example 4, wherein the second frequency divider and the first frequency divider have the same division ratio.
  • Example 7 The apparatus of Example 4, wherein the second delay unit and the first delay unit have the same circuit structure.
  • Example 8 The apparatus of Example 1, wherein the control signal conditioning module It includes a digital state machine, which has a first adjustment state for increasing the delay control signal and a second adjustment state for decreasing the delay control signal, wherein when the critical timing signal is in the first level state, the digital state machine switches to the first adjustment state, and when the critical timing signal is in the second level state, the digital state machine switches to the second adjustment state.
  • the control signal conditioning module It includes a digital state machine, which has a first adjustment state for increasing the delay control signal and a second adjustment state for decreasing the delay control signal, wherein when the critical timing signal is in the first level state, the digital state machine switches to the first adjustment state, and when the critical timing signal is in the second level state, the digital state machine switches to the second adjustment state.
  • Example 9 The apparatus of Example 1, wherein the voltage regulator comprises:
  • a low-pass filter configured to perform low-pass filtering on the power supply voltage to generate a filtered voltage
  • a transistor and a capacitor are connected in series between the power supply voltage and ground, the control end of the transistor is connected to the output end of the amplifier, the intermediate node between the transistor and the capacitor is connected to the second input end of the amplifier, and the intermediate node provides the preset voltage.
  • Example 10 A method for monitoring a power supply voltage of an electronic circuit, comprising:
  • a critical timing signal is generated based on the original clock signal and the delay control signal, wherein the critical timing signal is alternately in a first level state and a second level state;
  • the delay control signal is increased if the critical timing signal is in the first level state, and the delay control signal is decreased if the critical timing signal is in the second level state;
  • a drop indication signal is generated based on the original clock signal and the delay control signal, wherein the drop indication signal indicates whether the power supply voltage drops below the preset voltage.
  • Example 11 The method of Example 10, wherein generating a critical timing signal based on the original clock signal and the delay control signal comprises:
  • the critical timing signal is generated based on the phase relationship between the first frequency-divided signal and the first delayed signal, wherein when the phase difference between the first frequency-divided signal and the first delayed signal is half a cycle, the critical timing signal is in the second level state, and when the phase difference between the first frequency-divided signal and the first delayed signal does not reach half a cycle, the critical timing signal is in the first level state.
  • Example 12 The method of Example 11, wherein generating the critical timing signal based on a phase relationship between the first frequency-divided signal and the first delayed signal comprises:
  • a phase difference between the first frequency-divided signal and the first delayed signal is identified to generate a first phase detection signal representing the phase difference, wherein the first phase detection signal or an inverted signal of the first phase detection signal is used as the critical timing signal.
  • Example 13 The method of Example 11, wherein generating a droop indication signal based on the original clock signal and the delay control signal comprises:
  • Example 14 The method of Example 13, wherein generating the drop indication signal based on a phase relationship between the second frequency-divided signal and the second delayed signal comprises:
  • a phase difference between the second frequency-divided signal and the second delayed signal is identified to generate a second phase discrimination signal indicating the phase difference, wherein the second phase discrimination signal or an inverted signal of the second phase discrimination signal is used as the drop indication signal.
  • Example 15 The method of Example 10, wherein the adjustment of the delay control signal is implemented by a digital state machine, the digital state machine including a control unit for increasing the delay control signal.
  • a first adjustment state of a delay control signal and a second adjustment state for reducing the delay control signal wherein when the critical timing signal is in the first level state, the digital state machine switches to the first adjustment state, and when the critical timing signal is in the second level state, the digital state machine switches to the second adjustment state.
  • Example 16 An electronic circuit comprising a device according to any one of Examples 1 to 9.

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Abstract

本公开的实施例提供了用于监测电子电路的电源电压的装置、方法和电子电路。该装置包括：稳压器，被配置为对电源电压进行处理以生成预设电压；临界时序生成模块，由预设电压供电，被配置为基于原始时钟信号和延迟控制信号生成临界时序信号，临界时序信号交替地处于第一电平状态和第二电平状态；控制信号调节模块，被配置为基于临界时序信号调节延迟控制信号，其中在临界时序信号处于第一电平状态的情况下，延迟控制信号被增大，在临界时序信号处于第二电平状态的情况下，延迟控制信号被减小；以及电源跌落感测模块，由电源电压供电，被配置为基于原始时钟信号和延迟控制信号生成跌落指示信号，跌落指示信号指示电源电压是否跌落至低于预设电压。

Description

用于监测电子电路的电源电压的装置、方法和电子电路
本申请要求2023年03月13日递交的、标题为“用于监测电子电路的电源电压的装置、方法和电子电路”、申请号为202310260003.8的中国发明专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本公开的示例实施例总体涉及电子电路领域，特别地涉及用于监测电子电路的电源电压的装置、方法和电子电路。
背景技术
在电子电路领域，时钟信号用于协调各种电子组件的动作，保证相关的电子组件能够同步运行。在集成电路中，如数字芯片中，数字电路在工作时会对供电网络抽取电流，造成电源的波动。当抽取的电流过大时可能会导致电源电压的瞬间跌落。如果电源电压跌落的幅度过大，则会使得数字电路的时序要求不能得以满足，出现时序错误，从而造成数字电路操作错误，导致数字电路出现锁死等状态。
发明内容
本公开的目的是提供一种用于监测电子电路的电源电压的装置、方法和电子电路，以至少部分地解决上述问题以及其他潜在问题。
在本公开的第一方面，提供了一种用于监测电子电路的电源电压的装置，包括：稳压器，被配置为对所述电源电压进行处理以生成预设电压；临界时序生成模块，由所述预设电压供电，并且被配 置为基于原始时钟信号和延迟控制信号生成临界时序信号，所述临界时序信号交替地处于第一电平状态和第二电平状态；控制信号调节模块，被配置为基于所述临界时序信号调节所述延迟控制信号，其中在所述临界时序信号处于所述第一电平状态的情况下，所述延迟控制信号被增大，并且在所述临界时序信号处于所述第二电平状态的情况下，所述延迟控制信号被减小；以及电源跌落感测模块，由所述电源电压供电，并且被配置为基于所述原始时钟信号和所述延迟控制信号生成跌落指示信号，所述跌落指示信号指示所述电源电压是否跌落至低于所述预设电压。
在本公开的第二方面，提供了一种用于监测电子电路的电源电压的方法，包括：对所述电源电压进行处理以生成预设电压；在所述预设电压下，基于原始时钟信号和延迟控制信号生成临界时序信号，所述临界时序信号交替地处于第一电平状态和第二电平状态；基于所述临界时序信号调节所述延迟控制信号，其中在所述临界时序信号处于所述第一电平状态的情况下，所述延迟控制信号被增大，并且在所述临界时序信号处于所述第二电平状态的情况下，所述延迟控制信号被减小；以及在所述电源电压下，基于所述原始时钟信号和所述延迟控制信号生成跌落指示信号，所述跌落指示信号指示所述电源电压是否跌落至低于所述预设电压。
在本公开的第三方面，提供了一种电子电路，包括根据本公开的第一方面的装置。
应当理解，本内容部分中所描述的内容并非旨在限定本公开的实施例的关键特征或重要特征，也不用于限制本公开的范围。本公开的其它特征将通过以下的描述而变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了根据本公开的一个实施例的用于监测电子电路的电源电压的装置的框图；
图2示出了根据本公开的一个实施例的用于监测电子电路的电源电压的装置的电路原理图；
图3示出了根据本公开的一个实施例的电源电压、预设电压、状态机锁定信号、临界时序信号和跌落指示信号的曲线；
图4示出了根据本公开的一个实施例的用于监测电子电路的电源电压的方法的流程图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中示出了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反，提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“一些实施例”应当理解为“至少一些实施例”。下文还可能包括其他明确的和隐含的定义。
如上所述，数字电路在工作时会对供电网络抽取电流，造成电源的波动；当抽取的电流过大时可能会导致电源电压的瞬间跌落；如果电源电压跌落的幅度过大，则会使得数字电路的时序要求不能得以满足，出现时序错误。本公开的实施例提供了一种用于监测电子电路的电源电压的方案，在该方案中，在稳定的预设电压下让一个数字逻辑电路的时序处于临界错误的状态，同时让另一个类似的数字逻辑电路工作在待监测的电源电压下，当待监测的电源电压低于预设电压时，该另一数字逻辑电路就会生成代表电源电压出现了 过大的跌落的指示信号。以此方式，可以准确地监测电源电压的跌落，以便电子电路采取相应的应对措施来避免因电源跌落而导致的时序错误。在下文中将结合图1至图4来详细描述本公开的原理。
图1示出了根据本公开的一个实施例的用于监测电子电路的电源电压的装置的框图，图2示出了根据本公开的一个实施例的用于监测电子电路的电源电压的装置的电路原理图。如图1和图2所示，在此描述的装置总体上包括稳压器10、临界时序生成模块20、控制信号调节模块30和电源跌落感测模块40。
稳压器10用于对电源电压vdd进行处理以生成预设电压vdroop。预设电压vdroop可以是根据电子电路的设计要求预先设定的电压，其用作待监测的电源跌落的极限值。也即，当电源电压vdd在预设电压vdroop以上时，意味着电子电路的时序要求能够基本上被满足；而当电源电压vdd跌落至低于预设电压vdroop时，则意味着数字电路的时序要求不能得以满足，可能会出现时序错误。电源电压vdd是否跌落至低于预设电压vdroop可以由临界时序生成模块20、控制信号调节模块30和电源跌落感测模块40来监测，这将在下文中进行详细描述。
作为示例，当电源电压vdd为1V时，预设电压vdroop可以被预先设置为0.8V。当然，根据电子电路的设计要求，预设电压vdroop也可以被设置为高于或低于0.8V。应当注意，此处以及本公开其他地方可能提及的数字、数值等，都是示例性的，无意以任何方式限制本公开的范围。任何其他适当的数字、数值都是可能的。
稳压器10可以采用任何适当的稳压技术来对电源电压vdd进行处理。例如，在一个实施例中，稳压器10可以包括低压差线性稳压器(LDO)，如图2所示。该LDO包括低通滤波器101、放大器102、晶体管103和电容器104。低通滤波器101用于对电源电压vdd进行低通滤波，以滤除电源电压vdd中的高频成分，从而生成滤波电压vref。滤波电压vref被提供给放大器102的第一输入端。晶体管103和电容器104串联连接在电源电压vdd与接地之间。晶 体管103可以是金属氧化物半导体场效应晶体管(MOSFET)或其他类型的开关器件，本公开的实施例对此不做限制。晶体管103的控制端连接至放大器102的输出端。晶体管103和电容器104之间的中间节点连接至放大器102的第二输入端。预设电压vdroop由晶体管103和电容器104之间的中间节点提供。利用这种布置，稳压器10能够提供稳定预设电压vdroop，该电压基本上不受电源电压vdd的波动的影响。
图3中示出了根据本公开的一个实施例的电源电压vdd的曲线301和预设电压vdroop的曲线302。如图3所示，电源电压vdd上下波动，而预设电压vdroop处于基本上稳定的电平。电源电压vdd的曲线301包括低于预设电压vdroop的多个跌落部分3011、3012、3013。多个跌落部分3011、3012、3013中的每个跌落波分将由临界时序生成模块20、控制信号调节模块30和电源跌落感测模块40来监测，这将在下文中进行详细描述。
应当理解，上文描述的仅仅是示例，无意以任何方式限制本公开的实施例。任何目前已知的或者将来开发的稳压技术均可与本公开的实施例结合使用，以用于生成预设电压vdroop。
如图1和图2所示，临界时序生成模块20连接至稳压器10的输出端，以便由预设电压vdroop供电。也即，临界时序生成模块20在预设电压vdroop下进行操作。临界时序生成模块20用于基于原始时钟信号clk和由控制信号调节模块30提供的延迟控制信号cal_code生成临界时序信号DIR。原始时钟信号clk可以具有任何适当的占空比，例如占空比可以为50％。当然，原始时钟信号clk的占空比高于或低于50％也是可行的。延迟控制信号cal_code由控制信号调节模块30提供，以用于控制临界时序生成模块20中的延迟单元的延时量，例如控制第一延迟单元202的延迟量，这将在下文中进行详细说明书。延迟控制信号cal_code越大，则延迟单元的延时量越大，相反，延迟控制信号cal_code越小，则延迟单元的延时量越小。
在预设电压vdroop下，通过延迟控制信号cal_code的控制，能够使得临界时序生成模块20所生成的临界时序信号DIR交替地处于第一电平状态和第二电平状态。第一电平状态和第二电平状态是相对电平状态。在一个实施例中，第一电平状态是高电平状态，而第二电平状态是低电平状态。在另一实施例中，第一电平状态是低电平状态，而第二电平状态是高电平状态。临界时序信号DIR交替地处于第一电平状态和第二电平状态意味着临界时序生成模块20在预设电压vdroop下的时序处于临界错误状态。换而言之，临界时序生成模块20在预设电压vdroop下的时序能够满足要求，但是没有更多调节裕量。如果临界时序生成模块20的操作电压低于预设电压vdroop，则临界时序生成模块20就会出现时序错误。
下面以第一电平状态是高电平状态并且第二电平状态是低电平状态作为示例来描述本公开的原理。
在一个实施例中，如图2所示，临界时序生成模块20包括第一分频器201、第一延迟单元202和时序确定单元203。
第一分频器201用于对原始时钟信号clk进行分频以生成第一分频信号clk_div1。第一分频器201可以具有任何适当的分频比，例如二分频、四分频等。第一分频器201所生成第一分频信号clk_div1将具有50％的占空比。
第一延迟单元202用于对第一分频信号clk_div1进行延迟以生成第一延迟信号clk_div_dly1。第一延迟单元202所提供的延时量由延迟控制信号cal_code来控制。理论上，当延迟控制信号cal_code为0时，第一延迟单元202所提供的延时量为0。延迟控制信号cal_code越大，则第一延迟单元202所提供的延时量越大。相反，延迟控制信号cal_code越小，则第一延迟单元202所提供的延时量越小。
时序确定单元203用于基于第一分频信号clk_div1和第一延迟信号clk_div_dly1之间的相位关系生成临界时序信号DIR。在一些实施例中，时序确定单元203可以包括第一鉴相器2031和第一反 相器2032。第一鉴相器2031用于鉴别第一分频信号clk_div1和第一延迟信号clk_div_dly1之间的相位差，以生成用于表示该相位差的第一鉴相信号P1。第一鉴相信号P1经第一反相器2032反相之后生成第一反相信号P1_B。在一个实施例中，第一反相信号P1_B用作临界时序信号DIR。在第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位相差半个周期的情况下，第一鉴相信号P1将处于高电平状态，而第一反相信号P1_B将处于低电平状态。因此，临界时序信号DIR处于低电平状态，即第二电平状态。在第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位未达到相差半个周期的情况下，第一鉴相信号P1将处于低电平状态，而第一反相信号P1_B将处于高电平状态。因此，临界时序信号DIR处于高电平状态，即第一电平状态。
在本公开的实施例中，也可以采用第一鉴相信号P1作为临界时序信号DIR。在这样的实施例中，第一电平状态将是低电平状态，而第二电平状态将是高电平状态。具体而言，在第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位相差半个周期的情况下，第一鉴相信号P1处于高电平状态。因此，临界时序信号DIR处于高电平状态，即第二电平状态。在第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位未达到相差半个周期的情况下，第一鉴相信号P1处于低电平状态。因此，临界时序信号DIR处于低电平状态，即第一电平状态。
图3中示出了根据本公开的一个实施例的临界时序信号DIR的曲线304。如图3所示，临界时序信号DIR交替地处于交替地处于第一电平状态和第二电平状态，其中第一电平状态是高电平状态和低电平状态中的一项，而第二电平状态是高电平状态和低电平状态中的另一项。
控制信号调节模块30用于基于临界时序信号DIR调节延迟控制信号cal_code，以动态地调节第一延迟单元202所提供的延时量。在临界时序信号DIR处于第一电平状态的情况下，延迟控制信号 cal_code被增大，并且在临界时序信号DIR处于第二电平状态的情况下，延迟控制信号cal_code被减小。如上所述，临界时序信号DIR处于第一电平状态意味着第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位未达到相差半个周期，而临界时序信号DIR处于第二电平状态意味着第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位相差半个周期。在第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位未达到相差半个周期的情况下，增大延迟控制信号cal_code将会使得第一延迟单元202所提供的延时量增大。当第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位相差半个周期时，减小延迟控制信号cal_code将会使得第一延迟单元202所提供的延时量减小。以此方式，能够使得临界时序信号DIR交替地处于交替地处于第一电平状态和第二电平状态。也即，通过根据临界时序信号DIR动态调节延迟控制信号cal_code，能够使得临界时序生成模块20在预设电压vdroop下的时序处于临界错误状态。
在一些实施例中，控制信号调节模块30包括数字状态机，数字状态机具有用于增大延迟控制信号cal_code的第一调节状态和用于减小延迟控制信号cal_code的第二调节状态。在临界时序信号DIR处于第一电平状态的情况下，数字状态机将会切换至第一调节状态，以增大第一延迟单元202所提供的延时量。在临界时序信号DIR处于第二电平状态的情况下，数字状态机将会切换至第二调节状态，以减小第一延迟单元202所提供的延时量。图3中还示出了状态机锁定信号的曲线303。如图3所示，在临界时序信号DIR交替变化时，状态机锁定信号将被启用，使数字状态机循环地在第一调节状态和第二调节状态之间切换。此外，如图3所示，临界时序信号DIR的脉冲宽度动态地变化，这是因为通过动态调节延迟控制信号cal_code，能够抵抗电子电路的工艺-电压-温度(PVT)偏差。
如图1和图2所示，电源跌落感测模块40由电源电压vdd供电。也即，电源跌落感测模块40在电源电压vdd下进行操作。电源跌 落感测模块40连接至控制信号调节模块30，以接收由控制信号调节模块30生成的延迟控制信号cal_code。电源跌落感测模块40用于基于原始时钟信号clk和延迟控制信号cal_code生成跌落指示信号ERR。跌落指示信号ERR指示电源电压vdd是否跌落至低于预设电压vdroop。如上所述，临界时序生成模块20在预设电压vdroop下的时序能够满足要求，但是没有更多调节裕量；如果临界时序生成模块20的操作电压低于预设电压vdroop，则临界时序生成模块20就会出现时序错误。通过将相同的延迟控制信号cal_code提供给电源跌落感测模块40，并且判断控制电源跌落感测模块40在电源电压vdd下的时序是否出现错误，能够确定电源电压vdd是否跌落至低于预设电压vdroop。跌落指示信号ERR可以用作报警信号，以便指示电子电路采取相应的应对措施来避免因电源跌落而导致的时序错误。
在一个实施例中，电源跌落感测模块40包括第二分频器401、第二延迟单元402和电源跌落确定模块403。
第二分频器401用于对原始时钟信号clk进行分频以生成第二分频信号clk_div2。第二分频器401可以具有任何适当的分频比，例如二分频、四分频等。第二分频器401所生成第二分频信号clk_div2将具有50％的占空比。在一些实施例中，第二分频器401和第一分频器201可以具有相同的分频比。
第二延迟单元402用于对第二分频信号clk_div2进行延迟以生成第二延迟信号clk_div_dly2。第二延迟单元402所提供的延时量也由延迟控制信号cal_code来控制。由于相同的延迟控制信号cal_code被提供给第一延迟单元202和第二延迟单元402，因此第一延迟单元202和第二延迟单元402具有类似的延迟特性。延迟控制信号cal_code越大，则第二延迟单元402所提供的延时量越大。相反，延迟控制信号cal_code越小，则第二延迟单元402所提供的延时量越小。在一些实施例中，第二延迟单元402和第一延迟单元202可以具有相同的电路结构。在一些实施例中，第二延迟单元402 和第一延迟单元202所提供的延迟量可以随着延迟控制信号cal_code基本同步地变化。
延迟单元的延迟量还与其操作电压有关，操作电压越高，则延迟单元所提供的延迟量越小，而操作电压越低，则延迟单元所提供的延迟量越大。因此，如果电源电压vdd在某个时刻高于预设电压vdroop，则第二延迟单元402所提供的延时量将低于第一延迟单元202所提供的延时量。相反，如果电源电压vdd在某个时刻低于预设电压vdroop，则第二延迟单元402所提供的延时量将高于第一延迟单元202所提供的延时量。
电源跌落确定模块403用于基于第二分频信号clk_div2和第二延迟信号clk_div_dly2之间的相位关系生成跌落指示信号ERR。在一些实施例中，电源跌落确定模块403可以包括第二鉴相器4031和第二反相器4032。第二鉴相器4031用于鉴别第二分频信号clk_div2和第二延迟信号clk_div_dly2之间的相位差，以生成用于表示相位差的第二鉴相信号P2。第二鉴相信号P2经第二反相器4032反相之后生成第二反相信号P2_B。
在第二分频信号clk_div2和第二延迟信号clk_div_dly2的相位未达到相差半个周期的情况下，第二鉴相信号P2将处于低电平状态，而第二反相信号P2_B将处于高电平状态。例如，如果电源电压vdd在某个时刻高于预设电压vdroop，则第二延迟单元402所提供的延时量将低于第一延迟单元202所提供的延时量，使得第二分频信号clk_div2和第二延迟信号clk_div_dly2的相位未达到相差半个周期，因而第二鉴相信号P2将处于低电平状态，而第二反相信号P2_B将处于高电平状态。在第二分频信号clk_div2和第二延迟信号clk_div_dly2的相位相差半个周期的情况下，第二鉴相信号P2将处于高电平状态，而第二反相信号P2_B将处于低电平状态。例如，如果电源电压vdd在某个时刻低于预设电压vdroop，则第二延迟单元402所提供的延时量将高于第一延迟单元202所提供的延时量，使得第二分频信号clk_div2和第二延迟信号clk_div_dly2的相 位已经经历过相差半个周期，因而第二鉴相信号P2将会出现高电平状态，而第二反相信号P2_B将会出现低电平状态。
在一个实施例中，第二鉴相信号P2用作跌落指示信号ERR。在这样的实施例中，当电源电压vdd高于预设电压vdroop时，跌落指示信号ERR将处于低电平状态，而当电源电压vdd跌落至低于预设电压vdroop时，跌落指示信号ERR将出现高电平状态。如图3所示，当电源电压vdd高于预设电压vdroop时，跌落指示信号ERR将处于低电平状态。当电源电压vdd出现低于预设电压vdroop的多个跌落部分3011、3012、3013时，跌落指示信号ERR将出现具有高电平状态的多个异常指示部分3051、3052、3053。以此方式，能够精确地监测电源电压vdd的跌落，以便电子电路采取相应的应对措施来避免因电源跌落而导致的时序错误。
在一个实施例中，第二反相信号P2_B用作跌落指示信号ERR。在这样的实施例中，当电源电压vdd高于预设电压vdroop时，跌落指示信号ERR将处于高电平状态，而当电源电压vdd跌落至低于预设电压vdroop时，跌落指示信号ERR将出现低电平状态。利用这样的实施例，同样能够精确地监测电源电压vdd的跌落。
本公开的实施例还提供了一种用于监测电子电路的电源电压的方法400，如图4所示。方法400可以由在上文中结合图1至图3所描述的用于监测电子电路的电源电压的装置执行。如图4所示，方法400包括：在框410，对电源电压vdd进行处理以生成预设电压vdroop；在框420，在预设电压vdroop下，基于原始时钟信号clk和延迟控制信号cal_code生成临界时序信号DIR，临界时序信号DIR交替地处于第一电平状态和第二电平状态；在框430，基于临界时序信号DIR调节延迟控制信号cal_code，其中在临界时序信号DIR处于第一电平状态的情况下，延迟控制信号cal_code被增大，并且在临界时序信号DIR处于第二电平状态的情况下，延迟控制信号cal_code被减小；以及在框440，在电源电压vdd下，基于原始时钟信号clk和延迟控制信号cal_code生成跌落指示信号ERR，跌 落指示信号ERR指示电源电压vdd是否跌落至低于预设电压vdroop。
在一些实施例中，基于原始时钟信号clk和延迟控制信号cal_code生成临界时序信号DIR包括：对原始时钟信号clk进行分频以生成第一分频信号clk_div1；对第一分频信号clk_div1进行延迟以生成第一延迟信号clk_div_dly1，其中对第一分频信号clk_div1的延时量由延迟控制信号cal_code来控制；以及基于第一分频信号clk_div1和第一延迟信号clk_div_dly1之间的相位关系生成临界时序信号DIR，其中在第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位相差半个周期的情况下，临界时序信号DIR处于第二电平状态，并且在第一分频信号clk_div1和第一延迟信号clk_div_dly1的相位未达到相差半个周期的情况下，临界时序信号DIR处于第一电平状态。
在一些实施例中，基于第一分频信号clk_div1和第一延迟信号clk_div_dly1之间的相位关系生成临界时序信号DIR包括：鉴别第一分频信号clk_div1和第一延迟信号clk_div_dly1之间的相位差，以生成用于表示相位差的第一鉴相信号P1，其中第一鉴相信号P1或第一鉴相信号P1的反相信号被用作临界时序信号DIR。
在一些实施例中，基于原始时钟信号clk和延迟控制信号cal_code生成跌落指示信号ERR包括：对原始时钟信号clk进行分频以生成第二分频信号clk_div2；对第二分频信号clk_div2进行延迟以生成第二延迟信号clk_div_dly2，其中对第二分频信号clk_div2的延时量由延迟控制信号cal_code来控制；以及基于第二分频信号clk_div2和第二延迟信号clk_div_dly2之间的相位关系生成跌落指示信号ERR。
在一些实施例中，基于第二分频信号clk_div2和第二延迟信号clk_div_dly2之间的相位关系生成跌落指示信号ERR包括：鉴别第二分频信号clk_div2和第二延迟信号clk_div_dly2之间的相位差，以生成用于表示相位差的第二鉴相信号P2，其中第二鉴相信号P2 或第二鉴相信号P2的反相信号被用作跌落指示信号ERR。
在一些实施例中，延迟控制信号cal_code的调节通过数字状态机来实现，数字状态机包括用于增大延迟控制信号cal_code的第一调节状态和用于减小延迟控制信号cal_code的第二调节状态，其中在临界时序信号DIR处于第一电平状态的情况下，数字状态机切换至第一调节状态，并且在临界时序信号DIR处于第二电平状态的情况下，数字状态机切换至第二调节状态。
本公开的实施例还体现在以下示例中。
示例1.一种用于监测电子电路的电源电压的装置，包括：
稳压器，被配置为对所述电源电压进行处理以生成预设电压；
临界时序生成模块，由所述预设电压供电，并且被配置为基于原始时钟信号和延迟控制信号生成临界时序信号，所述临界时序信号交替地处于第一电平状态和第二电平状态；
控制信号调节模块，被配置为基于所述临界时序信号调节所述延迟控制信号，其中在所述临界时序信号处于所述第一电平状态的情况下，所述延迟控制信号被增大，并且在所述临界时序信号处于所述第二电平状态的情况下，所述延迟控制信号被减小；以及
电源跌落感测模块，由所述电源电压供电，并且被配置为基于所述原始时钟信号和所述延迟控制信号生成跌落指示信号，所述跌落指示信号指示所述电源电压是否跌落至低于所述预设电压。
示例2.根据示例1所述的装置，其中所述临界时序生成模块包括：
第一分频器，被配置为对所述原始时钟信号进行分频以生成第一分频信号；
第一延迟单元，被配置为对所述第一分频信号进行延迟以生成第一延迟信号，其中所述第一延迟单元所提供的延时量由所述延迟控制信号来控制；以及
时序确定单元，被配置为基于所述第一分频信号和所述第一延迟信号之间的相位关系生成所述临界时序信号，其中在所述第一分 频信号和所述第一延迟信号的相位相差半个周期的情况下，所述临界时序信号处于所述第二电平状态，并且在所述第一分频信号和所述第一延迟信号的相位未达到相差半个周期的情况下，所述临界时序信号处于所述第一电平状态。
示例3.根据示例2所述的装置，其中所述时序确定单元包括：
第一鉴相器，被配置为鉴别所述第一分频信号和所述第一延迟信号之间的相位差，以生成用于表示所述相位差的第一鉴相信号，其中所述第一鉴相信号或所述第一鉴相信号的反相信号被用作所述临界时序信号。
示例4.根据示例2所述的装置，其中所述电源跌落感测模块包括：
第二分频器，被配置为对所述原始时钟信号进行分频以生成第二分频信号；
第二延迟单元，被配置为对所述第二分频信号进行延迟以生成第二延迟信号，其中所述第二延迟单元所提供的延时量由所述延迟控制信号来控制；以及
电源跌落确定模块，被配置为基于所述第二分频信号和所述第二延迟信号之间的相位关系生成所述跌落指示信号。
示例5.根据示例4所述的装置，其中所述电源跌落确定模块包括：
第二鉴相器，被配置为鉴别所述第二分频信号和所述第二延迟信号之间的相位差，以生成用于表示所述相位差的第二鉴相信号，其中所述第二鉴相信号或所述第二鉴相信号的反相信号被用作所述跌落指示信号。
示例6.根据示例4所述的装置，其中所述第二分频器和所述第一分频器具有相同的分频比。
示例7.根据示例4所述的装置，其中所述第二延迟单元和所述第一延迟单元具有相同的电路结构。
示例8.根据示例1所述的装置，其中所述控制信号调节模块 包括数字状态机，所述数字状态机具有用于增大所述延迟控制信号的第一调节状态和用于减小所述延迟控制信号的第二调节状态，其中在所述临界时序信号处于所述第一电平状态的情况下，所述数字状态机切换至所述第一调节状态，并且在所述临界时序信号处于所述第二电平状态的情况下，所述数字状态机切换至所述第二调节状态。
示例9.根据示例1所述的装置，其中所述稳压器包括：
低通滤波器，被配置为对所述电源电压进行低通滤波，以生成滤波电压；
放大器，其第一输入端接收所述滤波电压；以及
晶体管和电容器，串联连接在所述电源电压与接地之间，所述晶体管的控制端连接至所述放大器的输出端，所述晶体管和所述电容器之间的中间节点连接至所述放大器的第二输入端，所述中间节点提供所述预设电压。
示例10.一种用于监测电子电路的电源电压的方法，包括：
对所述电源电压进行处理以生成预设电压；
在所述预设电压下，基于原始时钟信号和延迟控制信号生成临界时序信号，所述临界时序信号交替地处于第一电平状态和第二电平状态；
基于所述临界时序信号调节所述延迟控制信号，其中在所述临界时序信号处于所述第一电平状态的情况下，所述延迟控制信号被增大，并且在所述临界时序信号处于所述第二电平状态的情况下，所述延迟控制信号被减小；以及
在所述电源电压下，基于所述原始时钟信号和所述延迟控制信号生成跌落指示信号，所述跌落指示信号指示所述电源电压是否跌落至低于所述预设电压。
示例11.根据示例10所述的方法，其中基于原始时钟信号和延迟控制信号生成临界时序信号包括：
对所述原始时钟信号进行分频以生成第一分频信号；
对所述第一分频信号进行延迟以生成第一延迟信号，其中对所述第一分频信号的延时量由所述延迟控制信号来控制；以及
基于所述第一分频信号和所述第一延迟信号之间的相位关系生成所述临界时序信号，其中在所述第一分频信号和所述第一延迟信号的相位相差半个周期的情况下，所述临界时序信号处于所述第二电平状态，并且在所述第一分频信号和所述第一延迟信号的相位未达到相差半个周期的情况下，所述临界时序信号处于所述第一电平状态。
示例12.根据示例11所述的方法，其中基于所述第一分频信号和所述第一延迟信号之间的相位关系生成所述临界时序信号包括：
鉴别所述第一分频信号和所述第一延迟信号之间的相位差，以生成用于表示所述相位差的第一鉴相信号，其中所述第一鉴相信号或所述第一鉴相信号的反相信号被用作所述临界时序信号。
示例13.根据示例11所述的方法，其中基于所述原始时钟信号和所述延迟控制信号生成跌落指示信号包括：
对所述原始时钟信号进行分频以生成第二分频信号；
对所述第二分频信号进行延迟以生成第二延迟信号，其中对所述第二分频信号的延时量由所述延迟控制信号来控制；以及
基于所述第二分频信号和所述第二延迟信号之间的相位关系生成所述跌落指示信号。
示例14.根据示例13所述的方法，其中基于所述第二分频信号和所述第二延迟信号之间的相位关系生成所述跌落指示信号包括：
鉴别所述第二分频信号和所述第二延迟信号之间的相位差，以生成用于表示所述相位差的第二鉴相信号，其中所述第二鉴相信号或所述第二鉴相信号的反相信号被用作所述跌落指示信号。
示例15.根据示例10所述的方法，其中所述延迟控制信号的调节通过数字状态机来实现，所述数字状态机包括用于增大所述延 迟控制信号的第一调节状态和用于减小所述延迟控制信号的第二调节状态，其中在所述临界时序信号处于所述第一电平状态的情况下，所述数字状态机切换至所述第一调节状态，并且在所述临界时序信号处于所述第二电平状态的情况下，所述数字状态机切换至所述第二调节状态。
示例16.一种电子电路，包括根据示例1至9中任一项所述的装置。
以上已经描述了本公开的各实现，上述说明是示例性的，并非穷尽性的，并且也不限于所公开的各实现。在不偏离所说明的各实现的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实现的原理、实际应用或对市场中的技术的改进，或者使本技术领域的其他普通技术人员能理解本文公开的各个实现方式。

Claims (16)

  1. 一种用于监测电子电路的电源电压的装置，包括：
    稳压器(10)，被配置为对所述电源电压进行处理以生成预设电压；
    临界时序生成模块(20)，由所述预设电压供电，并且被配置为基于原始时钟信号和延迟控制信号生成临界时序信号，所述临界时序信号交替地处于第一电平状态和第二电平状态；
    控制信号调节模块(30)，被配置为基于所述临界时序信号调节所述延迟控制信号，其中在所述临界时序信号处于所述第一电平状态的情况下，所述延迟控制信号被增大，并且在所述临界时序信号处于所述第二电平状态的情况下，所述延迟控制信号被减小；以及
    电源跌落感测模块(40)，由所述电源电压供电，并且被配置为基于所述原始时钟信号和所述延迟控制信号生成跌落指示信号，所述跌落指示信号指示所述电源电压是否跌落至低于所述预设电压。
  2. 根据权利要求1所述的装置，其中所述临界时序生成模块(20)包括：
    第一分频器(201)，被配置为对所述原始时钟信号进行分频以生成第一分频信号；
    第一延迟单元(202)，被配置为对所述第一分频信号进行延迟以生成第一延迟信号，其中所述第一延迟单元(202)所提供的延时量由所述延迟控制信号来控制；以及
    时序确定单元(203)，被配置为基于所述第一分频信号和所述第一延迟信号之间的相位关系生成所述临界时序信号，其中在所述第一分频信号和所述第一延迟信号的相位相差半个周期的情况下，所述临界时序信号处于所述第二电平状态，并且在所述第一分频信号和所述第一延迟信号的相位未达到相差半个周期的情况下， 所述临界时序信号处于所述第一电平状态。
  3. 根据权利要求2所述的装置，其中所述时序确定单元(203)包括：
    第一鉴相器(2031)，被配置为鉴别所述第一分频信号和所述第一延迟信号之间的相位差，以生成用于表示所述相位差的第一鉴相信号，其中所述第一鉴相信号或所述第一鉴相信号的反相信号被用作所述临界时序信号。
  4. 根据权利要求2所述的装置，其中所述电源跌落感测模块(40)包括：
    第二分频器(401)，被配置为对所述原始时钟信号进行分频以生成第二分频信号；
    第二延迟单元(402)，被配置为对所述第二分频信号进行延迟以生成第二延迟信号，其中所述第二延迟单元(402)所提供的延时量由所述延迟控制信号来控制；以及
    电源跌落确定模块(403)，被配置为基于所述第二分频信号和所述第二延迟信号之间的相位关系生成所述跌落指示信号。
  5. 根据权利要求4所述的装置，其中所述电源跌落确定模块(403)包括：
    第二鉴相器(4031)，被配置为鉴别所述第二分频信号和所述第二延迟信号之间的相位差，以生成用于表示所述相位差的第二鉴相信号，其中所述第二鉴相信号或所述第二鉴相信号的反相信号被用作所述跌落指示信号。
  6. 根据权利要求4所述的装置，其中所述第二分频器(401)和所述第一分频器(201)具有相同的分频比。
  7. 根据权利要求4所述的装置，其中所述第二延迟单元(402)和所述第一延迟单元(202)具有相同的电路结构。
  8. 根据权利要求1所述的装置，其中所述控制信号调节模块(30)包括数字状态机，所述数字状态机具有用于增大所述延迟控制信号的第一调节状态和用于减小所述延迟控制信号的第二调节 状态，其中在所述临界时序信号处于所述第一电平状态的情况下，所述数字状态机切换至所述第一调节状态，并且在所述临界时序信号处于所述第二电平状态的情况下，所述数字状态机切换至所述第二调节状态。
  9. 根据权利要求1所述的装置，其中所述稳压器(10)包括：
    低通滤波器(101)，被配置为对所述电源电压进行低通滤波，以生成滤波电压；
    放大器(102)，其第一输入端接收所述滤波电压；以及
    晶体管(103)和电容器(104)，串联连接在所述电源电压与接地之间，所述晶体管(103)的控制端连接至所述放大器(102)的输出端，所述晶体管(103)和所述电容器(104)之间的中间节点连接至所述放大器(102)的第二输入端，所述中间节点提供所述预设电压。
  10. 一种用于监测电子电路的电源电压的方法，包括：
    对所述电源电压进行处理以生成预设电压；
    在所述预设电压下，基于原始时钟信号和延迟控制信号生成临界时序信号，所述临界时序信号交替地处于第一电平状态和第二电平状态；
    基于所述临界时序信号调节所述延迟控制信号，其中在所述临界时序信号处于所述第一电平状态的情况下，所述延迟控制信号被增大，并且在所述临界时序信号处于所述第二电平状态的情况下，所述延迟控制信号被减小；以及
    在所述电源电压下，基于所述原始时钟信号和所述延迟控制信号生成跌落指示信号，所述跌落指示信号指示所述电源电压是否跌落至低于所述预设电压。
  11. 根据权利要求10所述的方法，其中基于原始时钟信号和延迟控制信号生成临界时序信号包括：
    对所述原始时钟信号进行分频以生成第一分频信号；
    对所述第一分频信号进行延迟以生成第一延迟信号，其中对所 述第一分频信号的延时量由所述延迟控制信号来控制；以及
    基于所述第一分频信号和所述第一延迟信号之间的相位关系生成所述临界时序信号，其中在所述第一分频信号和所述第一延迟信号的相位相差半个周期的情况下，所述临界时序信号处于所述第二电平状态，并且在所述第一分频信号和所述第一延迟信号的相位未达到相差半个周期的情况下，所述临界时序信号处于所述第一电平状态。
  12. 根据权利要求11所述的方法，其中基于所述第一分频信号和所述第一延迟信号之间的相位关系生成所述临界时序信号包括：
    鉴别所述第一分频信号和所述第一延迟信号之间的相位差，以生成用于表示所述相位差的第一鉴相信号，其中所述第一鉴相信号或所述第一鉴相信号的反相信号被用作所述临界时序信号。
  13. 根据权利要求11所述的方法，其中基于所述原始时钟信号和所述延迟控制信号生成跌落指示信号包括：
    对所述原始时钟信号进行分频以生成第二分频信号；
    对所述第二分频信号进行延迟以生成第二延迟信号，其中对所述第二分频信号的延时量由所述延迟控制信号来控制；以及
    基于所述第二分频信号和所述第二延迟信号之间的相位关系生成所述跌落指示信号。
  14. 根据权利要求13所述的方法，其中基于所述第二分频信号和所述第二延迟信号之间的相位关系生成所述跌落指示信号包括：
    鉴别所述第二分频信号和所述第二延迟信号之间的相位差，以生成用于表示所述相位差的第二鉴相信号，其中所述第二鉴相信号或所述第二鉴相信号的反相信号被用作所述跌落指示信号。
  15. 根据权利要求10所述的方法，其中所述延迟控制信号的调节通过数字状态机来实现，所述数字状态机包括用于增大所述延迟控制信号的第一调节状态和用于减小所述延迟控制信号的第二 调节状态，其中在所述临界时序信号处于所述第一电平状态的情况下，所述数字状态机切换至所述第一调节状态，并且在所述临界时序信号处于所述第二电平状态的情况下，所述数字状态机切换至所述第二调节状态。
  16. 一种电子电路，包括根据权利要求1至9中任一项所述的装置。
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