WO2024178683A1 - 显示基板和显示装置 - Google Patents

显示基板和显示装置 Download PDF

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Publication number
WO2024178683A1
WO2024178683A1 PCT/CN2023/079105 CN2023079105W WO2024178683A1 WO 2024178683 A1 WO2024178683 A1 WO 2024178683A1 CN 2023079105 W CN2023079105 W CN 2023079105W WO 2024178683 A1 WO2024178683 A1 WO 2024178683A1
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WO
WIPO (PCT)
Prior art keywords
signal line
control signal
initialization voltage
voltage signal
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/079105
Other languages
English (en)
French (fr)
Inventor
蒋志亮
张跳梅
赵攀
刘烺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/703,194 priority Critical patent/US12444365B2/en
Priority to PCT/CN2023/079105 priority patent/WO2024178683A1/zh
Priority to CN202380007975.4A priority patent/CN118974813A/zh
Publication of WO2024178683A1 publication Critical patent/WO2024178683A1/zh
Priority to US19/300,642 priority patent/US20250378788A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0465—Improved aperture ratio, e.g. by size reduction of the pixel circuit, e.g. for improving the pixel density or the maximum displayable luminance or brightness
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0233—Improving the luminance or brightness uniformity across the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes

Definitions

  • the present disclosure relates to the field of display technology, and particularly to a display substrate and a display device.
  • a display substrate comprising: a base substrate; a plurality of sub-pixels arranged on the base substrate, the plurality of sub-pixels being arranged along a first direction and a second direction, at least one of the sub-pixels comprising a light-emitting element; a plurality of pixel driving circuits arranged on the base substrate, the plurality of pixel driving circuits being arranged along a first direction and a second direction, the plurality of pixel driving circuits being used to drive the light-emitting elements of the plurality of sub-pixels respectively, at least one of the pixel driving circuits comprising at least two transistors; an initialization voltage signal line arranged on the base substrate, the initialization voltage signal line comprising a portion extending along the first direction, the initialization voltage signal line being used to provide initialization to the pixel driving circuit a control signal line disposed on the substrate, the control signal line including a portion extending in a first direction, the control signal line being used to provide a control signal to
  • the pixel driving circuit includes a first reset transistor, the first reset transistor includes a gate, a source and a drain, the initialization voltage signal line includes a first initialization voltage signal line, the first initialization voltage signal line is electrically connected to the source or drain of the first reset transistor, the orthographic projection of the first initialization voltage signal line on the substrate at least partially overlaps with the orthographic projection of the control signal line on the substrate, and the control signal line includes a reset control signal line.
  • the pixel driving circuit includes a second reset transistor, the second reset transistor includes a gate, a source and a drain, the initialization voltage signal line includes a second initialization voltage signal line, the second initialization voltage signal line is electrically connected to the source or drain of the second reset transistor, the orthographic projection of the second initialization voltage signal line on the substrate at least partially overlaps with the orthographic projection of the control signal line on the substrate, and the control signal line includes a scanning control signal line.
  • the pixel driving circuit includes a third reset transistor, the third reset transistor includes a gate, a source and a drain, the initialization voltage signal line includes a third initialization voltage signal line, the third initialization voltage signal line is electrically connected to the source or drain of the third reset transistor, the orthographic projection of the third initialization voltage signal line on the substrate at least partially overlaps with the orthographic projection of the control signal line on the substrate, and the control signal line includes a light-emitting control signal line.
  • the pixel driving circuit includes a first reset transistor, a second reset transistor and a third reset transistor, each of the first reset transistor, the second reset transistor and the third reset transistor includes a gate, a source and a drain, the initialization voltage signal line includes a first initialization voltage signal line, the first initialization voltage signal line is electrically connected to the source or drain of the first reset transistor, the initialization voltage signal line includes a second initialization voltage signal line, the first initialization voltage signal line is electrically connected to the source or drain of the second reset transistor, the initialization voltage signal line includes a third initialization voltage signal line, the first initialization voltage signal line is electrically connected to the source or drain of the third reset transistor, and the orthographic projection of at least one of the first initialization voltage signal line, the second initialization voltage signal line and the third initialization voltage signal line on the substrate substrate at least partially overlaps with the orthographic projection of the control signal line on the substrate substrate.
  • the pixel driving circuit further includes a data writing transistor and a light emission control transistor
  • the data writing transistor and the light emission control transistor include a gate, a source and a drain
  • the control signal line includes a first reset control signal line, a second reset control signal line, a scan control signal line and a light emission control signal line
  • the first reset control signal line is electrically connected to the gate of the first reset transistor
  • the second reset control signal line is electrically connected to the gate of the second reset transistor or the gate of the third reset transistor
  • the scan control signal line is electrically connected to the gate of the data writing transistor
  • the light emission control signal line is electrically connected to the gate of the light emission control transistor
  • the orthographic projection of the first initialization voltage signal line on the substrate substrate and the orthographic projection of the second reset control signal line on the substrate substrate at least partially overlap, the orthographic projection of the first initialization voltage signal line on the substrate substrate and the orthographic projection of the first reset control signal line on the substrate do not overlap, the orthographic projection of the first initialization voltage signal line
  • the orthographic projection of the second initialization voltage signal line on the substrate substrate at least partially overlaps with the orthographic projection of the scanning control signal line on the substrate substrate, the orthographic projection of the second initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the second reset control signal line on the substrate substrate, and the orthographic projection of the second initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the light emitting control signal line on the substrate substrate.
  • the orthographic projection of the third initialization voltage signal line on the substrate substrate at least partially overlaps with the orthographic projection of the light emitting control signal line on the substrate substrate, the orthographic projection of the third initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the first reset control signal line on the substrate substrate, the orthographic projection of the third initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the second reset control signal line on the substrate substrate, and the orthographic projection of the third initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the scanning control signal line on the substrate substrate.
  • the display substrate comprises: a first semiconductor layer disposed on the base substrate; a first conductive layer disposed on a side of the first semiconductor layer away from the base substrate; a second conductive layer disposed on a side of the first conductive layer away from the base substrate; a second semiconductor layer disposed on a side of the second conductive layer away from the base substrate; and a second conductive layer disposed on a side of the second semiconductor layer away from the base substrate.
  • a third conductive layer a third conductive layer; a fourth conductive layer arranged on a side of the third conductive layer away from the base substrate; a fifth conductive layer arranged on a side of the fourth conductive layer away from the base substrate, wherein the first initialization voltage signal line is located in the third conductive layer and the second reset control signal line is located in the first conductive layer.
  • the first reset transistor is an N-type transistor
  • the first reset control signal line includes a first reset control signal sub-line and a second reset control signal sub-line
  • the first reset control signal sub-line and the second reset control signal sub-line are located in different conductive layers
  • the orthographic projection of the first reset control signal sub-line on the substrate substrate at least partially overlaps with the orthographic projection of the second reset control signal sub-line on the substrate substrate.
  • the first reset transistor includes an active layer, and the active layer of the first reset transistor is located in the second semiconductor layer.
  • the pixel driving circuit also includes a compensation transistor
  • the compensation transistor includes an active layer, a gate, a source and a drain
  • the active layer of the compensation transistor is located in the second semiconductor layer
  • the display substrate also includes a compensation control signal line arranged on the base substrate, the compensation control signal line is electrically connected to the gate of the compensation transistor
  • the compensation control signal line includes a first compensation control signal sub-line and a second compensation control signal sub-line
  • the first compensation control signal sub-line is located in the second conductive layer
  • the second compensation control signal sub-line is located in the third conductive layer
  • the orthographic projection of the first compensation control signal sub-line on the base substrate at least partially overlaps with the orthographic projection of the second compensation control signal sub-line on the base substrate.
  • the scan control signal line is located in the first conductive layer, and the second initialization voltage signal line is located in the fourth conductive layer.
  • the light emitting control signal line is located in the first conductive layer
  • the third initialization voltage signal line is located in the third conductive layer.
  • the second reset control signal line is located in the first conductive layer.
  • the display substrate further comprises a first power signal line located on the base substrate, the first power signal line extends along the second direction, two columns of sub-pixels share one first power signal line, the display substrate comprises a first conductive transition portion located in the second conductive layer, a first power signal line transition portion and a second voltage signal line transition portion located in the fourth conductive layer, pixel driving circuits of two adjacent sub-pixels located in the same row have respective first conductive transition portions and second voltage signal line transition portions, pixel driving circuits of two adjacent sub-pixels located in the same row share the first power signal line transition portion, and the first The power signal line is electrically connected to the first power signal line adapter through a first via hole, and both ends of the first power signal line adapter are electrically connected to the first conductive adapters of the pixel driving circuits of two adjacent sub-pixels in the same row through second via holes, respectively; the first conductive adapter is electrically connected to one end of the second voltage signal line adapter through a third via
  • the display substrate also includes a first initialization voltage connection portion located in the fourth conductive layer, one end of the first initialization voltage connection portion is electrically connected to the first initialization voltage signal line through a fifth via, and the other end of the first initialization voltage connection portion is electrically connected to the source or drain of the first reset transistor of two adjacent sub-pixels in the same row through a sixth via.
  • the display substrate also includes a second initialization voltage connection portion located in the fourth conductive layer, two ends of the second initialization voltage connection portion are electrically connected to the third initialization voltage signal line through a seventh via, a middle end between the two ends is electrically connected to the source or drain of the third reset transistor of two adjacent sub-pixels in the same row through an eighth via, and the second initialization voltage connection portion is located between the first initialization voltage connection portion and the second voltage signal line transition portion in the first direction.
  • each of the first initialization voltage signal line, the second initialization voltage signal line, and the third initialization voltage signal line has an orthographic projection on the base substrate that does not overlap with an orthographic projection of the control signal line on the base substrate.
  • the first reset transistor is a P-type transistor
  • the first reset control signal line is located in the first conductive layer
  • the orthographic projection of the second initialization voltage signal line on the substrate at least partially overlaps with the orthographic projection of the first reset control signal line on the substrate.
  • the first reset transistor includes an active layer, and the active layer of the first reset transistor is located in the first semiconductor layer.
  • the display substrate further includes at least one hollow area
  • the at least one hollow area includes a first side, a second side, a third side and a fourth side
  • the first side and the second side are two sides of the at least one hollow area opposite to each other in the first direction
  • the third side and the fourth side are two sides of the at least one hollow area opposite to each other in the second direction
  • the display substrate includes a plurality of data lines arranged on the base substrate, the plurality of data lines extend respectively along the second direction
  • the plurality of data lines include a first data line and a second data line adjacent to the at least one hollow area
  • the first data line and the second data line In the first direction, they are respectively located on the first side and the second side of the at least one hollow area
  • the first reset control signal line and the scan control signal line are adjacent to the at least one hollow area.
  • they are respectively located on the third side and the fourth side of the at least one hollow area
  • the first reset control signal line and the scan control signal line respectively
  • the display substrate further includes at least one hollow area
  • the at least one hollow area includes a first side, a second side, a third side and a fourth side
  • the first side and the second side are two opposite sides of the at least one hollow area in the first direction
  • the third side and the fourth side are two opposite sides of the at least one hollow area in the second direction
  • the display substrate includes a plurality of data lines arranged on the base substrate, the plurality of data lines extend along the second direction respectively
  • the plurality of data lines include a first data line and a second data line adjacent to the at least one hollow area
  • the first data line and the second data line are respectively located on the first side and the second side of the at least one hollow area in the first direction
  • the first reset control signal line and the compensation control signal line are adjacent to the at least one hollow area, and are respectively located on the third side and the fourth side of the at least one hollow area in the second direction
  • the first reset control signal line and the compensation control signal line respectively cross the first data line and the second data line to
  • each of the first data line and the second data line includes a main body portion and a bent portion, the bent portion of the first data line is bent relative to the main body portion of the first data line in a direction away from the at least one hollow area, the bent portion of the second data line is bent relative to the main body portion of the second data line in a direction away from the at least one hollow area, and the bent portion of the first data line and the bent portion of the second data line are bent in opposite directions.
  • each of the first reset control signal line and the scan control signal line includes a main body portion and a bending portion, the bending portion of the first reset control signal line is bent relative to the main body portion of the first reset control signal line in a direction away from the at least one hollow area, the bending portion of the scan control signal line is bent relative to the main body portion of the scan control signal line in a direction away from the at least one hollow area, and the bending portion of the first reset control signal line and the bending portion of the scan control signal line are bent in opposite directions.
  • each of the first reset control signal line and the compensation control signal line includes a main body portion and a bent portion, and the bent portion of the first reset control signal line is relative to the The main part of the first reset control signal line is bent in a direction away from the at least one hollow area, and the bent part of the compensation control signal line is bent in a direction away from the at least one hollow area relative to the main part of the compensation control signal line, and the bent part of the first reset control signal line and the bent part of the compensation control signal line are bent in opposite directions.
  • a ratio of an area of the overlapping portion to an area of an orthographic projection of the control signal line on the substrate is in a range of 80% to 95%.
  • the display substrate includes a data signal transfer portion located in the fourth conductive layer, a portion of the data signal transfer portion is electrically connected to the first data line or the second data line through a fifth via, and in a first region, an orthographic projection of the data signal transfer portion on the base substrate at least partially overlaps with an orthographic projection of the first reset control signal sub-line on the base substrate, an orthographic projection of the data signal transfer portion on the base substrate at least partially overlaps with an orthographic projection of the second reset control signal sub-line on the base substrate, and an orthographic projection of the first reset control signal sub-line on the base substrate at least partially does not overlap with an orthographic projection of the second reset control signal sub-line on the base substrate.
  • a display substrate comprising: a base substrate; a plurality of sub-pixels arranged on the base substrate, the plurality of sub-pixels being arranged along a first direction and a second direction, at least one of the sub-pixels comprising a light-emitting element; a plurality of pixel driving circuits arranged on the base substrate, the plurality of pixel driving circuits being arranged along the first direction and the second direction, the plurality of pixel driving circuits being used to respectively drive the light-emitting elements of the plurality of sub-pixels, at least one of the pixel driving circuits comprising a first reset transistor, a second reset transistor and a third reset transistor; an initialization voltage signal line arranged on the base substrate, the initialization voltage signal line comprising a portion extending along the first direction, the initialization voltage signal line being used to provide an initialization voltage signal to the pixel driving circuit, the initialization voltage signal line comprising a first initialization voltage signal line, a second initialization
  • the second time period is set at intervals in time sequence; and the initialization voltage signal line and the control signal line are located in different conductive layers, and the orthographic projection of each of the first initialization voltage signal line, the second initialization voltage signal line and the third initialization voltage signal line on the substrate substrate at least partially overlaps with the orthographic projection of the control signal line on the substrate substrate, and within a sub-pixel, the ratio of the area of the overlapping part to the orthographic projection area of the control signal line on the substrate substrate is in the range of 60% to 100%.
  • a display device comprising the display substrate described above.
  • FIG1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure.
  • FIG. 2 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure
  • FIG. 3 is a timing diagram of signals for driving a pixel driving circuit according to some exemplary embodiments of the present disclosure
  • FIG. 4 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG. 5 to 14 are partial plan views of display substrates according to some exemplary embodiments of the present disclosure, wherein FIG. 5 is a partial plan view of a light shielding layer of the display substrate, FIG. 6 is a partial plan view of a first semiconductor layer of the display substrate, FIG. 7 is a partial plan view of a first conductive layer of the display substrate, FIG. 8 is a partial plan view of a second conductive layer of the display substrate, FIG. 9 is a partial plan view of a second semiconductor layer of the display substrate, FIG. 10 is a partial plan view of a third conductive layer of the display substrate, FIG. 11 is a partial plan view of a first insulating layer of the display substrate, schematically showing a plurality of vias in the first insulating layer, FIG.
  • FIG. 12 is a partial plan view of a fourth conductive layer of the display substrate
  • FIG. 13 is a partial plan view of a second insulating layer of the display substrate, schematically showing a plurality of vias in the second insulating layer
  • FIG. 14 is a partial plan view of a fifth conductive layer of the display substrate
  • FIG. 15 is a partial plan view of a display substrate according to an exemplary embodiment of the present disclosure, schematically showing an overlay of a first conductive layer and a third conductive layer;
  • 16 is a partial plan view of a display substrate according to an exemplary embodiment of the present disclosure, schematically illustrating an overlay of a first conductive layer, a third conductive layer, and a fourth conductive layer.
  • FIG. 17 is a partial plan view of a display substrate according to an exemplary embodiment of the present disclosure, schematically showing an overlay of a first conductive layer and a third conductive layer;
  • FIG. 18 is a partial plan view of a display substrate according to an exemplary embodiment of the present disclosure, schematically showing an overlay of a second semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer;
  • FIG. 19 is a partial enlarged view of a display substrate according to an exemplary embodiment of the present disclosure, schematically illustrating a switching method of a first power signal line;
  • FIG. 20 is a partial enlarged view of a display substrate according to an exemplary embodiment of the present disclosure, schematically illustrating a staggered design of a signal line of a stacking design
  • FIG. 21 is a timing diagram of signals for driving a pixel driving circuit according to other exemplary embodiments of the present disclosure.
  • FIG. 22 is a partial plan view of a display substrate according to some other exemplary embodiments of the present disclosure.
  • FIG. 23 to 32 are partial plan views of display substrates according to some exemplary embodiments of the present disclosure, wherein FIG. 23 is a partial plan view of a light shielding layer of the display substrate, FIG. 24 is a partial plan view of a first semiconductor layer of the display substrate, FIG. 25 is a partial plan view of a first conductive layer of the display substrate, FIG. 26 is a partial plan view of a second conductive layer of the display substrate, FIG. 27 is a partial plan view of a second semiconductor layer of the display substrate, FIG. 28 is a partial plan view of a third conductive layer of the display substrate, FIG. 29 is a partial plan view of a first insulating layer of the display substrate, schematically showing a plurality of via holes in the first insulating layer, FIG.
  • FIG. 30 is a partial plan view of a fourth conductive layer of the display substrate
  • FIG. 31 is a partial plan view of a second insulating layer of the display substrate, schematically showing a plurality of via holes in the second insulating layer
  • FIG. 32 is a partial plan view of a fifth conductive layer of the display substrate
  • FIGS. 33 and 35 are partial plan views of the display substrate shown in FIG. 23 , schematically showing the superposition of the first conductive layer and the third conductive layer;
  • FIGS. 34 and 36 are partial plan views of the display substrate shown in FIG. 23 , schematically showing the superposition of the first conductive layer, the third conductive layer and the fourth conductive layer;
  • FIG. 37 is a partial enlarged view of a display substrate according to some exemplary embodiments of the present disclosure.
  • 38 to 47 are schematic diagrams of partial planar structures of various film layers of the display substrate shown in FIG. 37 ;
  • FIG48 is a schematic diagram of a partial plan structure of a hollowed-out area of a display substrate according to some exemplary embodiments of the present disclosure.
  • FIG49 is a schematic diagram of a partial planar structure between adjacent hollow regions of a display substrate according to some exemplary embodiments of the present disclosure.
  • Figure 50 is a schematic cross-sectional view of the display substrate of some exemplary embodiments of the present disclosure, taken along line A-A’ in Figure 4 .
  • connection may refer to a physical connection, an electrical connection, a communication connection and/or a fluid connection.
  • connection may refer to a physical connection, an electrical connection, a communication connection and/or a fluid connection.
  • the X-axis, the Y-axis and the Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense.
  • the X-axis, the Y-axis and the Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other.
  • X, Y, and Z and "at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XYY, YZ, and ZZ.
  • the term “and/or” includes any and all combinations of one or more of the listed associated items.
  • first the terms “first”, “second”, etc. may be used herein to describe various parts, components, elements, regions, layers and/or parts, these parts, components, elements, regions, layers and/or parts should not be limited by these terms. Instead, these terms are used to distinguish one part, component, element, region, layer and/or part from another.
  • first part, first component, first element, first region, first layer and/or first part discussed below may be referred to as the second part, second component, second element, second region, second layer and/or the second part without departing from the teachings of the present disclosure.
  • spatial relational terms such as “upper”, “lower”, “left”, “right”, etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figure. It should be understood that the spatial relational terms are intended to cover other different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the figure is turned upside down, elements described as “below” or “beneath” other elements or features will be oriented “above” or “above” the other elements or features.
  • the expression "the same layer” refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single composition process.
  • a single composition process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and/or parts located in the "same layer” are composed of the same material and are formed through the same composition process. Generally, multiple elements, components, structures and/or parts located in the "same layer” have approximately the same thickness.
  • the expression “height” or “thickness” refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.
  • first direction and second direction are used to describe different directions along the pixel area, for example, the longitudinal direction and the transverse direction of the pixel area, or the row direction and the column direction of the sub-pixel arrangement. It should be understood that such expressions are only exemplary descriptions and are not limitations of the present disclosure.
  • the transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and drain of the thin film transistor used here are symmetrical, the source and drain can be interchanged.
  • the transistor may include a gate, a first electrode and a second electrode, wherein the first electrode may represent one of the source and the drain, and the second electrode may represent the other of the source and the drain.
  • the driving transistor may also be shown as an N-type thin film transistor.
  • PPI Pixel Per Inch
  • Some exemplary embodiments of the present disclosure provide a display substrate, the display substrate comprising: a base substrate; a plurality of sub-pixels arranged on the base substrate, the plurality of sub-pixels being arranged in an array along a first direction and a second direction;
  • the invention relates to a method for manufacturing a pixel driving circuit comprising: a plurality of pixel driving circuits provided on the substrate, the plurality of pixel driving circuits being arranged in an array along a first direction and a second direction, the plurality of pixel driving circuits being used to drive the light-emitting elements of the plurality of sub-pixels respectively, and at least one of the pixel driving circuits comprising at least one transistor; an initialization voltage signal line provided on the substrate, the initialization voltage signal line extending along a first direction, the initialization voltage signal line being used to provide an initialization voltage signal to the pixel driving circuit; a control signal line provided on the substrate, the control signal line extending along a first direction, the control signal line being used to
  • the signal lines spaced in timing are stacked to effectively optimize the layout design of the pixel driving circuit, which is conducive to realizing a high PPI pixel design and improving the display quality of the display device under the premise of meeting the process specifications.
  • the display substrate according to an embodiment of the present disclosure may include a base substrate 10 and a pixel unit PX disposed on the base substrate 10 .
  • the display substrate may include a display area AA and a non-display area NA.
  • the display area AA may be an area where a pixel unit PX displaying an image is disposed. Each pixel unit PX will be described later.
  • the non-display area NA is an area where a pixel unit PX is not disposed, that is, it may be an area where an image is not displayed.
  • the non-display area NA corresponds to a frame in a final display device, and the width of the frame may be determined based on the width of the non-display area NA.
  • the display area AA may have various shapes.
  • the display area AA may be provided in various shapes such as a polygon (e.g., a rectangle) of a closed shape including straight edges, a circle, an ellipse, etc. including curved edges, and a semicircle, a semiellipse, etc. including straight edges and curved edges.
  • the display area AA is provided as an area having a quadrilateral shape including straight edges, and it should be understood that this is merely an exemplary embodiment of the present disclosure, and not a limitation of the present disclosure.
  • the non-display area NA may be disposed at least one side of the display area AA. In an embodiment of the present disclosure, the non-display area NA may surround the periphery of the display area AA. In an embodiment of the present disclosure, the non-display area NA may include a transverse portion extending in the first direction X and a longitudinal portion extending in the second direction Y.
  • the pixel unit PX is disposed in the display area AA.
  • the pixel unit PX is the smallest unit for displaying an image and may be disposed in plurality.
  • the pixel unit PX may include a light emitting device that emits white light and/or color light.
  • the pixel unit PX may be provided in plurality to be arranged in a matrix form along rows extending in the first direction X and columns extending in the first direction Y.
  • the embodiments of the present disclosure do not specifically limit the arrangement form of the pixel unit PX, and the pixel unit PX may be arranged in various forms.
  • the pixel unit PX may be arranged such that a direction inclined relative to the first direction X and the first direction Y becomes a column direction, and such that a direction intersecting the column direction becomes a row direction.
  • the plurality of pixel units PX are arranged in an array along the first direction X and the second direction Y to form a plurality of rows of pixel units and a plurality of columns of pixel units.
  • a pixel unit PX may include a plurality of sub-pixels.
  • a pixel unit PX may include three sub-pixels, namely a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3.
  • the first sub-pixel SP1 may be a red sub-pixel
  • the second sub-pixel SP2 may be a green sub-pixel
  • the third sub-pixel SP3 may be a blue sub-pixel.
  • the number of sub-pixels included in a pixel unit is not particularly limited, and is not limited to the above-mentioned three.
  • a scan control signal line 110 and a data line 120 are schematically shown. That is, the display substrate may further include: a plurality of scan control signal lines 110 and a plurality of data lines 120 provided on the base substrate, the plurality of scan control signal lines 110 supply scan control signals to a plurality of rows of pixel units respectively, and the plurality of data lines 120 supply data signals to a plurality of columns of pixel units respectively.
  • the scan control signal lines 110 extend along a first direction X, and the plurality of scan control signal lines 110 are arranged at intervals along a second direction Y.
  • the data lines 120 extend along the second direction Y, and the plurality of data lines 120 are arranged at intervals along the first direction X.
  • the scan control signal line 110 may be a representative of a horizontal line
  • the data line 120 may be a representative of a vertical line.
  • the horizontal line may also include other types of lines or lines for supplying other signals
  • the vertical line may also include other types of lines or lines for supplying other signals.
  • Each sub-pixel may include a light-emitting element and a pixel driving circuit for driving the light-emitting element.
  • the light-emitting element of a sub-pixel may include a stacked anode, a light-emitting material layer, and a cathode.
  • the anodes of the light-emitting elements of each sub-pixel are arranged at intervals to form a matrix along rows extending in a first direction X and columns extending in a first direction Y.
  • each pixel driving circuit can also be a structure including other numbers of transistors, such as a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, and the embodiments of the present disclosure are not limited to this.
  • FIG2 is an equivalent circuit diagram of a pixel driving circuit of a display substrate according to some exemplary embodiments of the present disclosure.
  • the pixel driving circuit is used to drive an organic light emitting diode (i.e., OLED).
  • OLED organic light emitting diode
  • the pixel driving circuit may include a first reset transistor T1, a compensation transistor T2, a driving transistor T3, a data writing transistor T4, a first light emission control transistor T5, a second light emission control transistor T6, a second reset transistor T7, a third reset transistor T8, and a storage capacitor Cst.
  • the display substrate also includes a first scan control signal line 81 (corresponding to the first scan control signal PGate in Figure 2), a second scan control signal line 82 (corresponding to the second scan control signal NGate in Figure 2), a first reset control signal line 83 (corresponding to the first reset control signal PReset in Figure 2), a second reset control signal line 84 (corresponding to the second reset control signal NReset in Figure 2), a light-emitting control signal line 85 (corresponding to the light-emitting control signal EM in Figure 2), a first initialization voltage signal line 86 (corresponding to the first initialization voltage signal Vinit1 in Figure 2), a second initialization voltage signal line 87 (corresponding to the second initialization voltage signal Vinit2 in Figure 2), a third initialization voltage signal line 88 (corresponding to the third initialization voltage signal Vinit3 in Figure 3), a data line 91 (corresponding to the data signal Data in Figure 2), a first power signal line 92 (corresponding to the first power signal ELVDD in Figure 2) and a second power signal line (
  • the first electrode of the first reset transistor T1 is electrically connected to the first initialization voltage signal line 86
  • the second electrode of the first reset transistor T1 is electrically connected to the gate of the driving transistor T3, i.e., node N1
  • the gate of the first reset transistor T1 is electrically connected to the first reset control signal line 83.
  • the first initialization voltage signal Vinit1 transmitted by the first initialization voltage signal line 86 is selectively written to the node N1.
  • the first electrode of the compensation transistor T2 is electrically connected to the first electrode of the driving transistor T3, that is, the node N3;
  • the second electrode of the body transistor T2 is electrically connected to the gate of the driving transistor T3, ie, the node N1;
  • the gate of the compensation transistor T2 is electrically connected to the second scanning control signal line 82 to receive the compensation control signal.
  • the first electrode of the driving transistor T3 is electrically connected to the first electrode of the compensation transistor T2, that is, node N3; the second electrode of the driving transistor T3 is electrically connected to the second electrode of the first light-emitting control transistor T5, that is, node N2; the gate of the driving transistor T3 is electrically connected to the node N1.
  • the first electrode of the data writing transistor T4 is electrically connected to the second electrode of the driving transistor T3, that is, the node N2; the second electrode of the data writing transistor T4 is electrically connected to the data line 91 to receive the data signal, and the gate of the data writing transistor T4 is electrically connected to the first scanning control signal line 81 to receive the first scanning control signal. Under the control of the first scanning control signal, the data signal is selectively written into the node N2.
  • the first electrode of the first light emitting control transistor T5 is electrically connected to the first power signal line 92 to receive the first power signal ELVDD
  • the second electrode of the first light emitting control transistor T5 is electrically connected to the second electrode of the driving transistor T3 (i.e., node N2)
  • the gate of the first light emitting control transistor T5 is electrically connected to the light emitting control signal line 85 to receive the light emitting control signal EM.
  • the first electrode of the second light emitting control transistor T6 is electrically connected to the first electrode of the driving transistor T3 (i.e., node N3), the second electrode of the second light emitting control transistor T6 is electrically connected to the first electrode of the light emitting element 120 (i.e., node N4), and the gate of the second light emitting control transistor T6 is electrically connected to the light emitting control signal line 85 to receive the light emitting control signal EM.
  • the first electrode of the second reset transistor T7 is electrically connected to the second initialization voltage signal line 87 to receive the second initialization voltage signal Vinit2, the second electrode of the second reset transistor T7 is electrically connected to the first electrode of the light-emitting element 130 (i.e., the N4 node), and the gate of the second reset transistor T7 is electrically connected to the second reset control signal line 84 to receive the second reset control signal.
  • the first electrode of the third reset transistor T8 is electrically connected to the third initialization voltage signal line 88 to receive the third initialization voltage signal Vinit3, the second electrode of the third reset transistor T8 is electrically connected to the second electrode of the driving transistor T3 (i.e., node N2), and the gate of the third reset transistor T8 is electrically connected to the second reset control signal line 84 to receive the second reset control signal.
  • One end of the storage capacitor Cst (hereinafter referred to as the first capacitor electrode) Cst1 is electrically connected to the gate of the driving transistor T3 (i.e., node N1), and the other end of the storage capacitor Cst (hereinafter referred to as the second capacitor electrode) Cst2 is electrically connected to the first power signal line 92.
  • the cathode of the light emitting element 130 is electrically connected to the second power signal line to receive the second power signal ELVSS. Accordingly, the light emitting element 130 receives the driving current from the driving transistor T3 to emit light, thereby displaying an image.
  • the first power signal line 92 and the second power signal line may be signal lines for transmitting voltage signals ELVDD and ELVSS, respectively, and they may be connected to a voltage source to output constant voltage signals, such as positive voltage signals and negative voltage signals.
  • transistors can be divided into N-type transistors and P-type transistors.
  • the N-type switching transistor is controlled to be turned on by a high-level switching control signal and is controlled to be turned off by a low-level switching control signal.
  • the P-type switching transistor is controlled to be turned on by a low-level switching control signal and is controlled to be turned off by a high-level switching control signal.
  • the pixel driving circuit can adopt LTPO circuit, that is, the LTPO circuit is prepared by low temperature polysilicon (LTPS) technology and oxide (IGZO), and the low temperature polysilicon thin film transistor (Low Temperature Poly Silicon, referred to as LTPS) adopts polysilicon deposition to form the active layer.
  • LTPS has high electron mobility, fast reaction speed, and has the advantages of high brightness, high resolution and low power consumption.
  • Oxide thin film transistor oxide thin-film transistor, referred to as oxide TFT
  • oxide semiconductor oxide semiconductor as the active layer of TFT, such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, referred to as IGZO), oxide semiconductor has high electron mobility and good turn-off characteristics.
  • oxide semiconductor process is simple and has high compatibility with amorphous silicon process.
  • oxide thin film transistor can also be other metal oxide semiconductors, such as indium zinc tin oxide (IZTO) or indium gallium zinc tin oxide (IGZTO).
  • IZTO indium zinc tin oxide
  • IGZTO indium gallium zinc tin oxide
  • the use of oxide thin film transistors can effectively reduce the size of the transistors and prevent leakage current, thereby making the pixel circuit suitable for low-frequency driving while also increasing the resolution of the display substrate.
  • an exemplary 8T1C circuit includes 8 thin film transistors (T1-T8), of which T1 and T2 are N-type thin film transistors NMOS, using oxide TFT; the rest are P-type thin film transistors PMOS, using LTPS TFT. Accordingly, the reset control signal applied to the gate of transistor T1 is called NReset, the scan control signal applied to the gate of transistor T2 is called NGate, the scan control signal applied to the gate of transistor T4 is called PGate, and the reset control signal applied to the gates of transistors T7 and T8 is called PReset.
  • the node N1, the node N2, the node N3 and the node N4 do not represent actual existing components, but represent the junction points of related circuit connections in the circuit diagram.
  • the effective signal (level) refers to the signal (level) used to turn on the corresponding switch element
  • the invalid signal (level) refers to the signal (level) used to turn off the corresponding switch element.
  • the effective level and the invalid level only represent the signal.
  • the level has two state quantities, which does not mean that the valid level or invalid level has a specific value in the whole text.
  • FIG3 is a timing diagram of signals for driving a pixel driving circuit according to some exemplary embodiments of the present disclosure.
  • an embodiment of the present disclosure provides a driving method for a pixel driving circuit, which is applied to the pixel driving circuit described in any embodiment of the present disclosure, and the refresh drive cycle (i.e., one frame) of the driving method may include a first reset phase, a write phase t4, and a first bias phase t5.
  • EM represents the light emitting control signal transmitted on the light emitting control signal line 85
  • NGate represents the second scanning control signal transmitted on the second scanning control signal line 82
  • NReset represents the first reset control signal transmitted on the first reset control signal line 83
  • PGate represents the first scanning control signal line transmitted on the first scanning control signal line 81
  • PReset represents the second reset control signal transmitted on the second reset control signal line 84.
  • the first reset phase may include a first reset sub-phase t1, a second reset sub-phase t2, and a third reset sub-phase t3.
  • first reset sub-phase t1 the second reset sub-phase t2, and the third reset sub-phase t3, each node N1, N2, and N3 of the driving transistor T3 is selectively reset.
  • the writing phase t4 EM is at a high level, NGate is at a high level, NReset is at a low level, PGate is at a low level, and PReset is at a high level.
  • the compensation transistor T2 and the data writing transistor T4 are turned on.
  • the driving transistor T3 is turned on, and the data signal is applied to the gate of the driving transistor T3 through the data writing transistor T4 and the compensation transistor T2 to achieve the writing of the data signal and the voltage compensation of the gate of the driving transistor T3.
  • the voltage at the node N1 is Vdata+Vth
  • the voltage at the node N2 is Vdata
  • the voltage at the node N3 is Vdata, where Vth is the threshold voltage of the driving transistor T3.
  • the first bias stage t5 EM is at a high level, NGate is at a low level, NReset is at a low level, PGate is at a high level, and PReset is at a low level.
  • the second reset transistor T7 and the third reset transistor T8 are turned on.
  • the driving transistor T3 is turned on, and the third initialization voltage signal Vinit3 is applied to the first and second electrodes of the driving transistor T3 through the third reset transistor T8.
  • the voltage at the node N1 is Vdata+Vth
  • the voltage at the node N2 is Vinit3
  • the voltage at the node N3 is Vinit3, where Vth is the threshold voltage of the driving transistor T3.
  • the nodes N2 and N3 are reset to a high voltage through the third reset transistor T8, which is equivalent to adding a negative bias to the gate-source of the driving transistor T3, so that the recovery process of the threshold voltage of the driving transistor T3 will be changed again in the light-emitting stage.
  • the refresh drive cycle (i.e., one frame) of the driving method may also include a first light-emitting stage t6, in which the light-emitting element 130 emits light in response to the driving current of the driving transistor T3.
  • the light-emitting control signal EM is at a low level, and the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are at a low level.
  • T6 is turned on when the level is low, driving transistor T3 to be turned on; other transistors are all in the off state under the control of the corresponding switch control signal.
  • the driving transistor T3 works in a saturated state. According to the saturated current characteristics, the saturated current I flowing through the driving transistor T3 and used to drive the light-emitting element 130 to emit light is proportional to (Vdata-VDD)2. It can be seen that the working current of the light-emitting element 130 is no longer affected by the threshold voltage Vth of the driving transistor T3, which completely solves the threshold voltage Vth drift of the driving transistor T3 caused by the process and long-term operation, effectively improves the low-frequency flicker (Flicker) and other problems, thereby improving the unevenness of the panel display.
  • the second reset control signal PReset transmitted on the second reset control signal line 84 is in an effective state at stages t1 and t5, and at stages t1 and t5, the first reset control signal NReset transmitted on the first reset control signal line 83 is at a low level, that is, the first reset transistor T1 is in a closed state, at which time the first initialization voltage signal Vinit1 will not be transmitted to the node N1 through the first reset transistor T1.
  • the first reset control signal NReset transmitted on the first reset control signal line 83 is at a high level at stages t2 and t3, that is, the first reset transistor T1 is turned on at stages t2 and t3.
  • the second reset control signal PReset transmitted on the second reset control signal line 84 is separated from the first initialization voltage signal Vinit1 in timing.
  • the first scanning control signal PGate transmitted on the first scanning control signal line 81 is in an effective state at stage t4, and at stage t4, the second reset control signal PReset transmitted on the second reset control signal line 84 is at a high level, that is, the second reset transistor T7 and the third reset transistor T8 are both in a closed state.
  • the second initialization voltage signal Vinit2 will not be transmitted to the node N4 through the second reset transistor T7, and the third initialization voltage signal Vinit3 will not be transmitted to the node N2 through the third reset transistor T8.
  • the second reset control signal PReset transmitted on the second reset control signal line 84 is at a low level at stages t1 and t5, that is, the second reset transistor T7 and the third reset transistor T8 are turned on at stages t1 and t5.
  • the first scanning control signal PGate transmitted on the first scanning control signal line 81 is separated from the second initialization voltage signal Vinit2 in timing.
  • the light emitting control signal EM transmitted on the light emitting control signal line 85 is in an invalid state in stages t1 to t5, and the second reset control signal PReset transmitted on the second reset control signal line 84 is at a low level in stages t1 and t5, that is, the second reset transistor T7 and the third reset transistor T8 are turned on in stages t1 and t5.
  • the light emitting control signal EM transmitted on the light emitting control signal line 85 is separated from the third initialization voltage signal Vinit3 in terms of timing.
  • the signal lines transmitting these signals separated in time sequence can be stacked.
  • the second reset control signal PReset transmitted on the second reset control signal line 84 is parallel to the first reset control signal line 84, The initialization voltage signal Vinit1 is separated in timing, so the second reset control signal line 84 and the first initialization voltage signal line 86 can be stacked; since the first scan control signal PGate transmitted on the first scan control signal line 81 and the second initialization voltage signal Vinit2 are separated in timing, the first scan control signal line 81 and the second initialization voltage signal line 87 can be stacked; since the light-emitting control signal EM transmitted on the light-emitting control signal line 85 and the third initialization voltage signal Vinit3 are separated in timing, the light-emitting control signal line 85 and the third initialization voltage signal line 88 can be stacked.
  • Fig. 4 is a partial plan view of a display substrate according to some exemplary embodiments of the present disclosure, schematically showing a pixel driving circuit of two adjacent sub-pixels.
  • Figs. 5 to 14 are partial plan views of display substrates according to some exemplary embodiments of the present disclosure, wherein Fig. 5 is a partial plan view of a light shielding layer of the display substrate, Fig. 6 is a partial plan view of a first semiconductor layer of the display substrate, Fig. 7 is a partial plan view of a first conductive layer of the display substrate, Fig. 8 is a partial plan view of a second conductive layer of the display substrate, Fig. 9 is a partial plan view of a second semiconductor layer of the display substrate, Fig.
  • FIG. 10 is a partial plan view of a third conductive layer of the display substrate
  • Fig. 11 is a partial plan view of a first insulating layer of the display substrate, schematically showing a plurality of vias in the first insulating layer
  • Fig. 12 is a partial plan view of a fourth conductive layer of the display substrate
  • Fig. 13 is a partial plan view of a second insulating layer of the display substrate, schematically showing a plurality of vias in the second insulating layer
  • Fig. 14 is a partial plan view of a fifth conductive layer of the display substrate.
  • Figure 50 is a schematic cross-sectional view of the display substrate of some exemplary embodiments of the present disclosure, taken along line A-A’ in Figure 4 .
  • the display substrate may include a base substrate 10, a light-shielding layer LS arranged on the base substrate 10, a first semiconductor layer 21 arranged on a side of the light-shielding layer LS away from the base substrate, a first conductive layer 31 arranged on a side of the first semiconductor layer 21 away from the base substrate, a second conductive layer 32 arranged on a side of the first conductive layer 31 away from the base substrate, a second semiconductor layer 22 arranged on a side of the second conductive layer 32 away from the base substrate, a third conductive layer 33 arranged on a side of the second semiconductor layer 22 away from the base substrate, a fourth conductive layer 34 arranged on a side of the third conductive layer 33 away from the base substrate, and a fifth conductive layer 35 arranged on a side of the fourth conductive layer 34 away from the base substrate.
  • the first conductive layer 31, the second conductive layer 32 and the third conductive layer 33 may be conductive layers made of a gate material, such as Mo.
  • the fourth conductive layer 34 and the fifth conductive layer 35 may be It is a conductive layer composed of source and drain materials, such as Ti/Al/Ti.
  • the semiconductor material constituting the active layer may include, for example, amorphous silicon, polycrystalline silicon, oxide semiconductor, etc.
  • the oxide semiconductor material may include, for example, IGZO (indium gallium zinc oxide), ZnO (zinc oxide), etc.
  • the insulating layer may be provided between two adjacent conductive layers, and the insulating layer may be composed of insulating materials such as silicon nitride, silicon oxide or silicon oxynitride, and the insulating layer may have a single film layer structure or a stacked structure composed of multiple film layers.
  • the display substrate may include a first insulating layer ILD provided between the third conductive layer 33 and the fourth conductive layer 34, and a second insulating layer PLN provided between the fourth conductive layer 34 and the fifth conductive layer 35. It should be understood that the display substrate may also have more insulating layers, and the structure of the insulating layer may refer to the structure of the insulating layer in the existing display substrate, which will not be described in detail here.
  • FIG6 shows the first semiconductor layer 21.
  • the first semiconductor layer 21 can be used to make the active layer of the above-mentioned driving transistor T3, the data writing transistor T4, the second light-emitting control transistor T5, the first light-emitting control transistor T6, the second reset transistor T7 and the third reset transistor T8, so as to form the channel region of the above-mentioned transistors.
  • the first semiconductor layer 21 may include the active region pattern (channel region) and the doping region pattern (source and drain region) of the above-mentioned transistors of each sub-pixel, and the active region pattern and the doping region pattern of the above-mentioned transistors in the same pixel driving circuit are integrally arranged.
  • the first semiconductor layer 21 may include an integrally formed low temperature polysilicon layer, and the source region and the drain region may be conductively doped to achieve electrical connection of the structures.
  • the source region and the drain region may be regions doped with p-type impurities.
  • a first conductive layer 31 located on a side of the first semiconductor layer 21 away from the base substrate.
  • a first scan control signal line 81, a first capacitor electrode Cst1 of a storage capacitor Cst, a light emission control signal line 85, and a second reset control signal line 84 may be located in the first conductive layer 31.
  • the first conductive layer 31 may include a gate of a driving transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, a second reset transistor T7, and a third reset transistor T8.
  • the dotted rectangular boxes in FIG. 6 show the overlapping portions of the first semiconductor layer 21 and the first conductive layer 31, namely, the channel regions.
  • the active semiconductor layers on both sides of each channel region are conductively connected as the first and second electrodes of each transistor through processes such as ion doping.
  • the source and drain of the transistor may be symmetrical in structure, so there may be no difference in physical structure between the source and drain.
  • one of the electrodes is directly described.
  • the first pole is the first pole
  • the other pole is the second pole, so the first pole and the second pole of all or part of the transistors in the embodiment of the present disclosure can be interchanged as needed.
  • the gate of the data writing transistor T4 may be the portion where the first scanning control signal line 81 overlaps with the first semiconductor layer 21.
  • the gate of the first light emission control transistor T6 may be the first portion where the light emission control signal line 85 overlaps with the first semiconductor layer 21, and the gate of the second light emission control transistor T5 may be the second portion where the light emission control signal line 85 overlaps with the first semiconductor layer 21.
  • the gate of the third reset transistor T8 may be the first portion where the second reset control signal line 84 overlaps with the first semiconductor layer 21, and the gate of the second reset transistor T7 may be the second portion where the second reset control signal line 84 overlaps with the first semiconductor layer 21.
  • FIG 8 shows a second conductive layer 32 located on a side of the first conductive layer 31 away from the substrate.
  • a second scan control signal line 82 may be located in the second conductive layer 32 .
  • a second capacitor electrode Cst2 of the storage capacitor Cst may be located in the second conductive layer 32 .
  • FIG9 shows a second semiconductor layer 22 located on the side of the second conductive layer 32 away from the substrate.
  • the second semiconductor layer 22 includes the channel regions of the first reset transistor T1 and the compensation transistor T2.
  • the transistor made of oxide semiconductor can be used to replace the low-temperature polysilicon material in the transistor to form a low-temperature polysilicon oxide (LTPO) pixel driving circuit, so as to achieve low leakage and improve the stability of the gate voltage of the transistor.
  • LTPO low-temperature polysilicon oxide
  • the gate of the first reset transistor T1 can be the portion where the first reset control signal line 83 overlaps with the second semiconductor layer 22
  • the gate of the compensation transistor T2 can be the portion where the second scan control signal line 82 overlaps with the second semiconductor layer 22.
  • FIG 10 shows the third conductive layer 33 on the side of the second semiconductor layer 22 away from the substrate.
  • another second scan control signal line 82 another first reset control signal line 83 , a first initialization voltage signal line 86 and a third initialization voltage signal line 88 may be located in the third conductive layer 33 .
  • another first reset control signal line 83 overlaps with the channel region of the first reset transistor T1, and the first reset transistor T1 includes a top gate and a bottom gate located on both sides of the active layer; another second scan control signal line 82 overlaps with the channel region of the compensation transistor T2, and the compensation transistor T2 includes a top gate and a bottom gate located on both sides of the active layer.
  • the first reset transistor T1 and the compensation transistor T2 may have a dual-gate structure, namely, including a top gate and a bottom gate, respectively.
  • the first reset control signal line 83 may include a first reset control signal sub-line 831 and a second reset control signal line 832.
  • the first reset control signal line located in the second conductive layer 32 is described as the first reset control signal sub-line 831
  • the first reset control signal line located in the third conductive layer 33 is described as the second reset control signal sub-line 832.
  • the portion where the first reset control signal sub-line 831 overlaps with the second semiconductor layer 22 constitutes the bottom gate of the first reset transistor T1
  • the portion where the second reset control signal sub-line 832 overlaps with the second semiconductor layer 22 constitutes the top gate of the first reset transistor T1.
  • the second scan control signal line 82 may include a first scan control signal sub-line 821 and a second scan control signal sub-line 822.
  • the second scan control signal line in the second conductive layer 32 is described as the first scan control signal sub-line 821
  • the second scan control signal line in the third conductive layer 33 is described as the second scan control signal sub-line 822.
  • the portion where the first scan control signal sub-line 821 overlaps with the second semiconductor layer 22 constitutes the bottom gate of the compensation transistor T2
  • the portion where the second scan control signal sub-line 822 overlaps with the second semiconductor layer 22 constitutes the top gate of the compensation transistor T2.
  • the first reset transistor T1 and the compensation transistor T2 may be N-type transistors
  • the driving transistor T3, the data writing transistor T4, the second emission control transistor T5, the first emission control transistor T6, the second reset transistor T7 and the third reset transistor T8 may be P-type transistors.
  • the second initialization voltage signal line 87 may be located in the fourth conductive layer 34, and the display substrate may further include a plurality of connection parts located in the fourth conductive layer 34, for example, the plurality of connection parts may include a connection part 341, a connection part 342, a connection part 343, a second voltage signal line transition part 344, a connection part 345, a first power signal line transition part 346, a connection part 347, a connection part 348, and a first initialization voltage connection part 349.
  • FIG. 14 shows a fifth conductive layer 35 located on a side of the fourth conductive layer 34 away from the substrate.
  • the data line 91 and the first power signal line 92 may be located in the fifth conductive layer 35 .
  • connection portion 341 can be used to electrically connect the data line 91 located in the fifth conductive layer 35 and the first electrode of the data write transistor T4.
  • the data line 91 located in the fifth conductive layer 35 is electrically connected to a portion of the connection portion 341 through a via VH17 located in the second insulating layer PLN, and another portion of the connection portion 341 is electrically connected to the first electrode of the data write transistor T4 through a via VH1 located in the first insulating layer ILD.
  • connection portion 342 can be used to electrically connect the gate of the driving transistor T3 and the second electrode of the compensation transistor T2, that is, to form a node N1.
  • a portion (e.g., one end) of the connection portion 342 is electrically connected to the second electrode of the compensation transistor T2 through a via hole VH2 located in the first insulating layer ILD, and another portion (e.g., the other end) of the connection portion 342 is electrically connected to the second electrode of the compensation transistor T2.
  • the connecting portion 343 is electrically connected to the gate of the driving transistor T3 through the via hole VH4 located in the first insulating layer ILD.
  • the connecting portion 343 can be used to electrically connect the first electrode of the compensation transistor T2 and the first electrode of the first light-emitting control transistor T6, that is, to form a node N3.
  • a portion (for example, one end) of the connecting portion 343 is electrically connected to the first electrode of the compensation transistor T2 through the via hole VH5 located in the first insulating layer ILD, and another portion (for example, the other end) of the connecting portion 343 is electrically connected to the first electrode of the first light-emitting control transistor T6 through the via hole VH6 located in the first insulating layer ILD.
  • the connecting portion 345 can be used to electrically connect the second electrode of the third reset transistor T8 to the node N2.
  • a portion (for example, one end) of the connecting portion 345 is electrically connected to the second electrode of the third reset transistor T8 through the via hole VH13 located in the first insulating layer ILD, and another portion (for example, the other end) of the connecting portion 345 is electrically connected to the node N2 through the via hole VH3 located in the first insulating layer ILD.
  • connection portion 347 can be used to electrically connect the first electrode of the third reset transistor T8 and the third initialization voltage signal line 88.
  • a portion (e.g., one end) of the connection portion 347 is electrically connected to the third initialization voltage signal line 88 through a via hole VH11 located in the first insulating layer ILD
  • another portion (e.g., the other end) of the connection portion 347 is electrically connected to the first electrode of the first electrode of the third reset transistor T8 through a via hole VH16 located in the first insulating layer ILD.
  • FIG19 is a partial enlarged view of a display substrate according to an exemplary embodiment of the present disclosure, which schematically shows a switching method of the first power signal line.
  • the data line 91 and the first power signal line 92 both extend along the second direction Y.
  • each column of sub-pixels has its own data line 91, and two adjacent columns of sub-pixels share a first power signal line 92.
  • a shared first power signal line 92 is located between the pixel driving circuits of two adjacent columns of sub-pixels.
  • the main part of the first power signal line 92 extends along the second direction Y, and the width of the first power signal line 92 in the first direction X is relatively large.
  • the part of the first power signal line 92 where the width becomes larger is called a widening portion 921 (as shown in FIG14), and the widening portion 921 extends in the first direction X relative to the main part of the first power signal line 92.
  • Two adjacent columns of sub-pixels share a first power signal line transition portion 346 located in the fourth conductive layer 34, and the widened portion 921 of the first power signal line 92 is electrically connected to the middle portion of the first power signal line transition portion 346 through vias VH18 located in the second insulating layer PLN.
  • the second capacitor electrode Cst2 located in the second conductive layer 32 is also used as a conductive transition part.
  • One end of the first power signal line transition part 346 is electrically connected to the conductive transition part Cst2 of the pixel driving circuit of one sub-pixel through the via VH7 located in the first insulating layer ILD, and the other end of the first power signal line transition part 346 is electrically connected to the conductive transition part Cst2 of the pixel driving circuit of another sub-pixel through the via VH7 located in the first insulating layer ILD.
  • the pixel driving circuit of each sub-pixel further includes a respective second voltage signal line switching unit 344.
  • a portion of the conductive transition portion Cst2 is electrically connected to one end of the second voltage signal line transition portion 344 through the via VH14, and the other end of the second voltage signal line transition portion 344 is electrically connected to the second electrode of the second light-emitting control transistor T5 through the via VH15.
  • the first power signal on a first power signal line 92 shared by two adjacent columns of sub-pixels can be transmitted to the second light emitting control transistors T5 of the two adjacent columns of sub-pixels.
  • the first power signal line 92 is connected mainly through the conductive transition part Cst2 located in the second conductive layer in the first direction X, and is connected mainly through the main body located in the fifth conductive layer in the second direction Y.
  • the first power signal line 92 in the horizontal and vertical directions is connected between two sub-pixels through a via hole VH18 located in the second insulating layer PLN and two via holes VH7 located in the first insulating layer ILD. Two sub-pixels share a via hole VH18 located in the second insulating layer PLN.
  • the first power signal of each sub-pixel is first transferred to the first power signal line transfer part 346 through the main body extending longitudinally, and then transferred to the conductive transition part Cst2 in the second conductive layer extending transversely through the first power signal line transfer part 346, and then transferred to the second voltage signal line transfer part 344 through another via hole VH14 of the conductive transfer part Cst2 located in the first insulating layer ILD, and then transferred to the second light-emitting control transistor T5 through the second voltage signal line transfer part 344.
  • the conductive transfer portion Cst2 located in the second conductive layer 32 serves as a conductive transfer portion for laterally transmitting the first power signal and also serves as a first power signal transfer jumper within the sub-pixel.
  • connection portion 348 is electrically connected to the first electrode of the first light emission control transistor T6 through the via hole VH8 , so that the node N4 can be brought out to facilitate subsequent electrical connection between the first electrode of the first light emission control transistor T6 and the anode of the light emitting element 120 .
  • the display substrate also includes a first initialization voltage connection portion located in the fourth conductive layer, one end of the first initialization voltage connection portion is electrically connected to the first initialization voltage signal line through a fifth via, and the other end of the first initialization voltage connection portion is electrically connected to the source or drain of the first reset transistor of two adjacent sub-pixels in the same row through a sixth via.
  • a portion (e.g., one end) of the first initialization voltage connection portion 349 is electrically connected to the first initialization voltage signal line 86 through the via hole VH9, and another portion (e.g., the other end) of the first initialization voltage connection portion 349 is electrically connected to the first electrode of the first reset transistor T1 through the via hole VH10.
  • Another portion of the first initialization voltage connection portion 349 is electrically connected to the first electrodes of the first reset transistors of two adjacent sub-pixels in the same row through the sixth via hole, respectively.
  • a portion of the second initialization voltage signal line 87 is electrically connected to the first electrode of the second reset transistor T7 through the via hole VH12.
  • Fig. 15 is a partial plan view of a display substrate according to an exemplary embodiment of the present disclosure, schematically showing an overlay of a first conductive layer and a third conductive layer.
  • Fig. 16 is a partial plan view of a display substrate according to an exemplary embodiment of the present disclosure, schematically showing an overlay of a first conductive layer, a third conductive layer, and a fourth conductive layer.
  • the display substrate also includes a second initialization voltage connection portion located in the fourth conductive layer, two ends of the second initialization voltage connection portion are electrically connected to the third initialization voltage signal line through a seventh via, a middle end between the two ends is electrically connected to the source or drain of the third reset transistor of two adjacent sub-pixels in the same row through an eighth via, and the second initialization voltage connection portion is located between the first initialization voltage connection portion and the second voltage signal line transition portion in the first direction.
  • the orthographic projection of the light-emitting control signal line 85 on the substrate substrate 10 and the orthographic projection of the third initialization voltage signal line 88 on the substrate substrate 10 at least partially overlap, the orthographic projection of the third initialization voltage signal line on the substrate substrate and the orthographic projection of the first reset control signal line on the substrate substrate do not overlap, the orthographic projection of the third initialization voltage signal line on the substrate substrate and the orthographic projection of the second reset control signal line on the substrate substrate do not overlap, the orthographic projection of the third initialization voltage signal line on the substrate substrate and the orthographic projection of the scanning control signal line on the substrate substrate do not overlap, the orthographic projection of the light-emitting control signal line 85 on the substrate substrate 10 and the orthographic projection of the third initialization voltage signal line 88 on the substrate substrate 10 at least partially overlap, for example, within a sub-pixel, the ratio of the area of the overlapping portion to the orthographic projection area of the initialization voltage signal line on the substrate substrate or the orthographic projection area of the
  • the third initialization voltage signal line 88 extending along the first direction X is electrically connected to a portion (e.g., one end) of the connection portion 347 through the via hole VH11, and another portion (e.g., the other end) of the connection portion 347 is electrically connected to the first electrode of the first electrode of the third reset transistor T8 through the via hole VH16.
  • the second electrode of the third reset transistor T8 is electrically connected to the node N2 through the connection portion 345.
  • connection portion 347 can be used to electrically connect the first electrode of the third reset transistor T8 and the third initialization voltage signal line 88.
  • the connection portion 347 includes first ends respectively located in two adjacent sub-pixels and a middle end located between the two first ends.
  • the first ends of the connection portion 347 are electrically connected to the third initialization voltage signal line 88 through via holes VH11, the middle end of the connection portion 347 located between the two first ends is electrically connected to the first electrode of the third reset transistor T8 of the adjacent sub-pixel through via holes VH16, and the connection portion 347 between the two adjacent sub-pixels and in the first direction is electrically connected to the third reset transistor T8 of the adjacent sub-pixel through via holes VH16.
  • the second reset control signal PReset transmitted on the second reset control signal line 84 is at a low level in stages t1 and t5, that is, the third reset transistor T8 is turned on in stages t1 and t5.
  • the third initialization voltage signal transmitted on the third initialization voltage signal line 88 refreshes the node N2.
  • the light-emitting control signal EM transmitted on the light-emitting control signal line 85 is in an invalid state in stages t1 to t5. In other words, the light-emitting control signal EM transmitted on the light-emitting control signal line 85 is separated from the third initialization voltage signal Vinit3 in timing.
  • the positive projection of the light-emitting control signal line 85 on the substrate substrate 10 and the positive projection of the third initialization voltage signal line 88 on the substrate substrate 10 at least partially overlap, that is, a stacking design is adopted.
  • the light-emitting control signal EM transmitted on the light-emitting control signal line 85 and the third initialization voltage signal Vinit3 work in a misaligned timing and do not work at the same time, which can prevent crosstalk between signals.
  • the stacking design of the light control signal line 85 and the third initialization voltage signal line 88 can effectively optimize the pixel space layout, which is conducive to high-resolution pixel design.
  • Fig. 17 is a partial plan view of a display substrate according to an exemplary embodiment of the present disclosure, schematically showing a superposition of a first conductive layer and a third conductive layer.
  • Fig. 18 is a partial plan view of a display substrate according to an exemplary embodiment of the present disclosure, schematically showing a superposition of a second semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer.
  • the orthographic projection of the second reset control signal line 84 on the substrate 10 and the orthographic projection of the first initialization voltage signal line 86 on the substrate 10 at least partially overlap.
  • the orthographic projection of the first initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the first reset control signal line on the substrate substrate
  • the orthographic projection of the first initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the scanning control signal line on the substrate substrate
  • the orthographic projection of the first initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the light emitting control signal line on the substrate substrate.
  • the orthographic projection of the second reset control signal line 84 on the substrate substrate 10 and the orthographic projection of the first initialization voltage signal line 86 on the substrate substrate 10 at least partially overlap, for example, within a sub-pixel, the ratio of the area of the overlapping portion to the orthographic projection area of the first initialization voltage signal line on the substrate substrate is in the range of 60% to 100%, or the ratio of the area of the overlapping portion to the orthographic projection area of the second reset control signal line on the substrate substrate is in the range of 60% to 100%.
  • the ratio of the area of the overlapping portion to the orthographic projection area of the second reset control signal line on the substrate may be in the range of 80% to 95%, that is, the orthographic projection of the second reset control signal line 84 on the substrate 10 and the orthographic projection of the first initialization voltage signal line 86 on the substrate 10 mostly overlap, but not completely overlap.
  • the first initialization voltage signal line 86 The first reset voltage connection part 349 is electrically connected to a part (e.g., one end) of the first reset voltage connection part 349 through the via hole VH9, and the other part (e.g., the other end) of the first reset voltage connection part 349 is electrically connected to the first electrode of the first reset transistor T1 through the via hole VH10.
  • the second electrode of the first reset transistor T1 is electrically connected to the first electrode of the compensation transistor T2, and the gate of the driving transistor T3 is also electrically connected to the first electrode of the compensation transistor T2 through the connection part 342, thereby forming a node N1.
  • the positive projection of the second reset control signal line on the substrate substrate and the positive projection of the first initialization voltage signal line on the substrate substrate mostly overlap, for example, the ratio of the area of the overlapping part to the positive projection area of the second reset control signal line on the substrate substrate or the positive projection area of the first initialization voltage signal line on the substrate substrate is 60%, or it can be completely overlapped, for example, the ratio is 100%.
  • the positive projection of the second initialization voltage signal line on the substrate substrate can overlap with the positive projection of the scanning control signal line on the substrate substrate, and the positive projection of the second initialization voltage signal line on the substrate substrate can also overlap with the positive projection of the first reset control signal line on the substrate substrate.
  • the second reset control signal PReset transmitted on the second reset control signal line 84 is in an effective state at stages t1 and t5, and at stages t1 and t5, the first reset control signal NReset transmitted on the first reset control signal line 83 is at a low level, that is, the first reset transistor T1 is in a closed state, at this time, the first initialization voltage signal Vinit1 will not be transmitted to the node N1 through the first reset transistor T1.
  • the first reset control signal NReset transmitted on the first reset control signal line 83 is at a high level at stages t2 and t3, that is, the first reset transistor T1 is turned on at stages t2 and t3.
  • the second reset control signal PReset transmitted on the second reset control signal line 84 is separated from the first initialization voltage signal Vinit1 in timing.
  • the positive projection of the first scanning control signal line 81 on the substrate substrate 10 and the positive projection of the first initialization voltage signal line 86 on the substrate substrate 10 at least partially overlap, that is, a stacked design is adopted.
  • the orthographic projection of the first initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the first reset control signal line on the substrate substrate, the orthographic projection of the first initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the scanning control signal line on the substrate substrate, and the orthographic projection of the first initialization voltage signal line on the substrate substrate does not overlap with the orthographic projection of the light-emitting control signal line on the substrate substrate.
  • the working timing of the second reset control signal PReset transmitted on the second reset control signal line 84 and the first initialization voltage signal Vinit1 are misaligned and do not work at the same time, which can prevent crosstalk between signals.
  • the stacking design of the first scanning control signal line 81 and the first initialization voltage signal line 86 can effectively optimize the pixel space layout, which is conducive to high-resolution pixel design.
  • the orthographic projection of the first scanning control signal line 81 on the substrate substrate 10 and the orthographic projection of the first initialization voltage signal line 86 on the substrate substrate 10 are not overlapped.
  • the projections at least partially overlap, for example, the ratio of the area of the overlapping portion to the area of the orthographic projection of the first scanning control signal line 81 on the base substrate 10 is in the range of 80% to 95%, or the ratio of the area of the overlapping portion to the area of the orthographic projection of the first initialization voltage signal line 86 on the base substrate 10 is in the range of 80% to 95%.
  • FIG. 20 is a partial enlarged view of a display substrate according to an exemplary embodiment of the present disclosure, schematically illustrating a staggered design of a signal line of a stacking design.
  • each of the first initialization voltage signal line 86, the second initialization voltage signal line 87, and the third initialization voltage signal line 88 has an orthographic projection on the substrate substrate that does not overlap with the orthographic projection of the control signal line on the substrate substrate.
  • a portion of the first initialization voltage signal line 86 located in the third conductive layer 33 is designed to be misaligned with the control signal line (e.g., the second reset control signal line 84 or the third reset control signal line 84) in the first conductive layer 31 below, such as the area marked by the rectangular dotted line frame and the elliptical dotted line frame near the first initialization voltage signal line 86 in FIG. 20.
  • the control signal line e.g., the second reset control signal line 84 or the third reset control signal line 84
  • a portion of the third initialization voltage signal line 88 is designed to be misaligned with the control signal line (e.g., the light emitting control signal line 85) located in the first conductive layer 31 below, such as the area marked by the rectangular dotted line frame near the third initialization voltage signal line 88 in FIG. 20.
  • the second initialization voltage signal line 87 located in the fourth conductive layer 34 is designed to be misaligned with the control signal line (e.g., the scanning control signal line 81) located in the first conductive layer 31 below.
  • the arrows indicate the distance between adjacent signal lines and vias. It should be understood that the distance between adjacent signal lines and vias needs to meet the specified process specifications. Under the premise of meeting the specified process specifications, the initialization voltage signal line and the control signal line below are partially staggered to reduce the overlapping area between the two signal lines, thereby reducing the load on the signal line.
  • FIG. 21 is a timing diagram of signals for driving a pixel driving circuit according to other exemplary embodiments of the present disclosure.
  • the 8T1C circuit includes 8 thin film transistors (T1-T8), among which T2 is an N-type thin film transistor NMOS, which adopts an oxide transistor; T1, T3-T8 are P-type thin film transistors PMOS, which adopt low-temperature polysilicon transistors.
  • the first reset control signal line 83 transmits the first reset control signal PReseta
  • the second reset control signal line or the third reset control signal line 84 transmits the second reset control signal or the third reset control signal PResetb
  • the light emitting control signal line 85 transmits the light emitting control signal EM
  • the compensation control signal line 82 transmits the compensation control signal NGate
  • the scanning control signal line 81 transmits the second reset control signal or the third reset control signal PResetb.
  • the scanning control signal PGate is transmitted on the second reset control signal line or the third reset control signal PResetb transmitted on the third reset control signal line 84.
  • the second reset control signal or the third reset control signal PResetb transmitted on the second reset control signal line or the third reset control signal line 84 is in a valid state in stages t1, t3, and t6, and in stages t1, t3, and t6, the first reset control signal Preseta transmitted on the first reset control signal line 83 is in a closed state.
  • the first initialization voltage signal Vinit1 will not be transmitted to the node N1 through the first reset transistor T1.
  • the first reset control signal PReseteta transmitted on the first reset control signal line 83 is in a valid state, that is, the first reset transistor T1 is turned on in stages t2 and t4, that is, the second reset control signal PResetb transmitted on the second reset control signal line 84 is separated from the first initialization voltage signal Vinit1 in timing.
  • the second reset control signal line or the third control signal line 84 can be arranged to overlap with the first initialization voltage signal line 86, so that the signals on each signal line can be stacked with different film layers of the display substrate without causing interference, thereby improving the space utilization of each signal line and designing and laying out pixels with higher PPI while meeting existing process specifications, that is, realizing the design of high PPI pixels.
  • the first scanning control signal PGate transmitted on the first scanning control signal line 81 is in an effective state at stage t5, and at stage t5, the second reset control signal or the third reset control signal PResetb transmitted on the second reset control signal line or the third reset control signal line 84 is at a high level, that is, the second reset transistor T7 and the third reset transistor T8 are both in a closed state, at this time, the second initialization voltage signal Vinit2 will not be transmitted to the node N4 through the second reset transistor T7, and the third initialization voltage signal Vinit3 will not be transmitted to the node N2 through the third reset transistor T8.
  • the second reset control signal PResetb transmitted on the second reset control signal line 84 is at a low level at stages t1, t3, and t6, that is, the second reset transistor T7 and the third reset transistor T8 are turned on at stages t1, t3, and t6.
  • the first reset control signal Preseta transmitted on the first reset control signal line 83 is different from the second reset control signal or the third reset control signal PResetb in the stages t1 to t6.
  • the first reset control signal PReseta is in an effective state at t2 and t4, and is in an off state at other times.
  • the second reset control signal PResetb is in an effective state at t1, t3, and t6, that is, the second reset transistor T7 or the third reset transistor T8 is controlled to be turned on at t1, t3, and t6.
  • the first reset control signal PReseta transmitted on the first reset control signal line 83 is separated from the second initialization voltage signal Vinit2 in timing. Therefore, the first reset control signal line and the second initialization voltage signal line can be overlapped, so that the signals on each signal line can realize the stacking setting of different film layers of the display substrate without interference, improve the space utilization rate of each signal line, and realize the design and layout of pixels with higher PPI under the premise of meeting the existing process specifications, that is, realize the design of high PPI pixels.
  • the light emitting control signal EM transmitted on the light emitting control signal line 85 is in an invalid state in stages t1 to t6, and the second reset control signal or the third reset control signal PResetb transmitted on the second reset control signal line and the third reset control signal line 84 is at a low level in stages t1, t3, and t6, that is, the second reset transistor T7 and the third reset transistor T8 are turned on in stages t1, t3, and t6.
  • the light emitting control signal EM transmitted on the light emitting control signal line 85 is separated from the third initialization voltage signal Vinit3 in terms of timing.
  • the signal lines transmitting these signals separated in timing may be stacked.
  • the second reset control signal PResetb transmitted on the second reset control signal line or the third reset control signal line 84 is separated in timing from the first initialization voltage signal Vinit1
  • the second reset control signal line or the third reset control signal line 84 may be stacked with the first initialization voltage signal line 86.
  • the first scanning control signal PReseta transmitted on the first reset control signal line 83 is separated from the second initialization voltage signal Vinit2 in timing, the first reset control signal line 83 and the second initialization voltage signal line 87 can be stacked; since the light-emitting control signal EM transmitted on the light-emitting control signal line 85 is separated from the second initialization voltage signal or the third initialization voltage signal Vinit3 in timing, the light-emitting control signal line 85 and the third initialization voltage signal line 88 can be stacked.
  • the pixel driving circuit includes a first reset transistor, the first reset transistor includes a gate, a source and a drain, the initialization voltage signal line includes a first initialization voltage signal line, the first initialization voltage signal line is electrically connected to the source or drain of the first reset transistor, the orthographic projection of the first initialization voltage signal line on the substrate substrate overlaps at least partially with the orthographic projection of the control signal line on the substrate substrate, and the control signal line includes a reset control signal line.
  • the control signal line may include, for example, a second reset control signal line for controlling the gate of the second reset transistor.
  • the pixel driving circuit includes a second reset transistor, the second reset transistor includes a gate, a source and a drain, the initialization voltage signal line includes a second initialization voltage signal line, the second initialization voltage signal line is electrically connected to the source or drain of the second reset transistor, the positive projection of the second initialization voltage signal line on the substrate substrate overlaps at least partially with the positive projection of the control signal line on the substrate substrate, and the control signal line includes a scanning control signal line.
  • the control signal line may include, for example, a first scanning control signal line for controlling data writing into the transistor gate.
  • the pixel driving circuit includes a third reset transistor, the third reset transistor includes a gate, a source and a drain, the initialization voltage signal line includes a third initialization voltage signal line, the third initialization voltage signal line is electrically connected to the source or drain of the third reset transistor, the orthographic projection of the third initialization voltage signal line on the substrate substrate overlaps at least partially with the orthographic projection of the control signal line on the substrate substrate, and the control signal line includes a light-emitting control signal line.
  • the control signal line may include, for example, a light-emitting control signal line for controlling the gate of the first light-emitting control transistor and/or the second light-emitting control transistor.
  • FIG22 is a partial plan view of a display substrate according to some other exemplary embodiments of the present disclosure, which schematically shows a pixel driving circuit of two adjacent sub-pixels.
  • FIG23 to FIG32 are partial plan views of a display substrate according to the embodiment of FIG22 of the present disclosure, wherein FIG23 is a partial plan view of a light shielding layer of the display substrate, FIG24 is a partial plan view of a first semiconductor layer of the display substrate, FIG25 is a partial plan view of a first conductive layer of the display substrate, FIG26 is a partial plan view of a second conductive layer of the display substrate, FIG27 is a partial plan view of a second semiconductor layer of the display substrate, FIG28 is a partial plan view of a third conductive layer of the display substrate, FIG29 is a partial plan view of a first insulating layer of the display substrate, which schematically shows a plurality of vias located in the first insulating layer, FIG30 is a partial plan view of a fourth conductive layer of the display substrate, FIG
  • the display substrate may include a base substrate 10, a light-shielding layer LS arranged on the base substrate 10, a first semiconductor layer 21 arranged on a side of the light-shielding layer LS away from the base substrate, a first conductive layer 31 arranged on a side of the first semiconductor layer 21 away from the base substrate, a second conductive layer 32 arranged on a side of the first conductive layer 31 away from the base substrate, a second semiconductor layer 22 arranged on a side of the second conductive layer 32 away from the base substrate, a third conductive layer 33 arranged on a side of the second semiconductor layer 22 away from the base substrate, a fourth conductive layer 34 arranged on a side of the third conductive layer 33 away from the base substrate, and a fifth conductive layer 35 arranged on a side of the fourth conductive layer 34 away from the base substrate.
  • FIG24 shows a first semiconductor layer 21.
  • the first semiconductor layer 21 can be used to make The first semiconductor layer 21 is used as the active layer of the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the second light emission control transistor T5, the first light emission control transistor T6, the second reset transistor T7 and the third reset transistor T8 to form the channel region of the above transistors.
  • the first semiconductor layer 21 may include the active region pattern (channel region) and the doping region pattern (source and drain region) of the above transistors of each sub-pixel, and the active region pattern and the doping region pattern of the above transistors in the same pixel driving circuit are integrally arranged.
  • the first semiconductor layer 21 may include an integrally formed low temperature polysilicon layer, and the source region and the drain region may be conductively doped to achieve electrical connection of the structures.
  • the source region and the drain region may be regions doped with p-type impurities.
  • a first conductive layer 31 located on a side of the first semiconductor layer 21 away from the base substrate.
  • a first scan control signal line 81, a first capacitor electrode Cst1 of a storage capacitor Cst, a light emitting control signal line 85, a second reset control signal line 84, and a first reset control signal line 83 may be located in the first conductive layer 31.
  • the first conductive layer 31 may include a first reset transistor T1, a driving transistor T3, a data writing transistor T4, a second light emitting control transistor T5, a first light emitting control transistor T6, a second reset transistor T7, and a gate of a third reset transistor T8.
  • the dotted rectangular boxes in FIG. 25 show the overlapping portions of the first semiconductor layer 21 and the first conductive layer 31, i.e., the channel regions.
  • the active semiconductor layers on both sides of each channel region are conductively connected by ion doping and other processes as the first and second electrodes of each transistor.
  • the source and drain of the transistor may be symmetrical in structure, so there may be no difference in the physical structure of the source and drain.
  • one of the electrodes is directly described as the first electrode and the other electrode is the second electrode, so the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.
  • the gate of the first reset transistor T1 may be a portion where the first reset control signal line 83 overlaps with the first semiconductor layer 21.
  • the gate of the data write transistor T4 may be a portion where the first scan control signal line 81 overlaps with the first semiconductor layer 21.
  • the gate of the first light emission control transistor T6 may be a first portion where the light emission control signal line 85 overlaps with the first semiconductor layer 21, and the gate of the second light emission control transistor T5 may be a second portion where the light emission control signal line 85 overlaps with the first semiconductor layer 21.
  • the gate of the third reset transistor T8 may be a first portion where the second reset control signal line 84 overlaps with the first semiconductor layer 21, and the gate of the second reset transistor T7 may be a second portion where the second reset control signal line 84 overlaps with the first semiconductor layer 21.
  • FIG. 26 shows a second conductive layer 32 on a side of the first conductive layer 31 away from the substrate.
  • the second scan control signal line 82 , the second capacitance electrode Cst2 of the storage capacitor Cst, and the compensation control signal line 82 may be located in the second conductive layer 32 .
  • FIG27 shows a second semiconductor layer 22 on a side of the second conductive layer 32 away from the substrate.
  • the second semiconductor layer 22 includes a channel region of the compensation transistor T2.
  • the active layer in the compensation transistor T2 is made of an oxide semiconductor
  • the transistor made of an oxide semiconductor has the characteristics of good hysteresis characteristics and low leakage current
  • an oxide semiconductor transistor can be used to replace the low-temperature polysilicon material in the transistor to form a low-temperature polysilicon oxide (LTPO) pixel driving circuit, thereby achieving low leakage and improving the stability of the gate voltage of the transistor.
  • LTPO low-temperature polysilicon oxide
  • the gate of the compensation transistor T2 may be the portion where the second scan control signal line 82 overlaps with the second semiconductor layer 22. Specifically, the portion where the first scan control signal sub-line 821 and the second scan control signal sub-line 822 overlap with the second semiconductor layer 22.
  • FIG28 shows the third conductive layer 33 on the side of the second semiconductor layer 22 away from the substrate.
  • another second scan control signal line 82 may be located in the third conductive layer 33 .
  • another second scan control signal line 82 overlaps with a channel region of the compensation transistor T2 , and the compensation transistor T2 includes a top gate and a bottom gate located at both sides of the active layer.
  • the compensation transistor T2 may have a dual-gate structure, namely, including a top gate and a bottom gate.
  • the second scan control signal line 82 may include a first scan control signal sub-line 821 and a second scan control signal sub-line 822.
  • the second scan control signal line located in the second conductive layer 32 is described as the first scan control signal sub-line 821
  • the second scan control signal line located in the third conductive layer 33 is described as the second scan control signal sub-line 822.
  • the portion where the first scan control signal sub-line 821 overlaps with the second semiconductor layer 22 constitutes the bottom gate of the compensation transistor T2
  • the portion where the second scan control signal sub-line 822 overlaps with the second semiconductor layer 22 constitutes the top gate of the compensation transistor T2.
  • the compensation transistor T2 may be an N-type transistor
  • the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the second emission control transistor T5, the first emission control transistor T6, the second reset transistor T7 and the third reset transistor T8 may be P-type transistors.
  • FIG30 shows a fourth conductive layer 34 located on a side of the third conductive layer 33 away from the base substrate.
  • the display substrate may further include a plurality of connecting portions located in the fourth conductive layer 34, for example,
  • the connection part may include a connection part 341 , a connection part 342 , a connection part 343 ′, a second voltage signal line transfer part 344 , a connection part 345 , a first power signal line transfer part 346 , a connection part 347 , a connection part 348 , a first initialization voltage connection part 349 and a connection part 350 .
  • the 32 shows a fifth conductive layer 35 located on a side of the fourth conductive layer 34 away from the substrate.
  • the data line 91 and the first power signal line 92 may be located in the fifth conductive layer 35 .
  • connection part 341 , the connection part 342 , the second voltage signal line transfer part 344 , the connection part 345 , the first power signal line transfer part 346 , the connection part 347 , the connection part 348 , and the first initialization voltage connection part 349 are the same as those shown in FIG. 12 , and are not described again herein.
  • connection portion 343' and the connection portion 350 of this embodiment are somewhat different from the other connection portions shown above. Specifically, the connection portion 343' can be used to electrically connect the first electrode of the compensation transistor T2 and the first electrode of the first light emission control transistor T6, that is, to form a node N3.
  • connection portion 343' is electrically connected to the first electrode of the compensation transistor T2 through a via hole VH5 located in the first insulating layer ILD
  • another portion (e.g., one end) of the connection portion 343' is electrically connected to the first electrode of the first light emission control transistor T6 through a via hole VH6 located in the first insulating layer ILD
  • another portion (e.g., the other end) of the connection portion 343' is electrically connected to the second electrode of the first reset transistor through a via hole VH20 in the first insulating layer ILD.
  • connection portion 350 can electrically connect the second initialization voltage signal line 87 and the first electrode of the second reset transistor T7. Specifically, the connection portion 350 is connected to the second initialization voltage signal line 87 through the via VH19 and is electrically connected to the first electrode of the second reset transistor T7 through the via VH12.
  • Figures 33 and 35 are partial plan views of the display substrate shown in Figure 23, schematically showing the superposition of the first conductive layer and the third conductive layer.
  • Figures 34 and 36 are partial plan views of the display substrate shown in Figure 23, schematically showing the superposition of the first conductive layer, the third conductive layer and the fourth conductive layer.
  • Figure 33 schematically shows the stacked structure setting of the first initialization voltage signal line 86 and the second reset control signal line or the third reset control signal line 84
  • Figure 34 schematically shows the electrical connection method of the first initialization voltage signal line, which schematically shows the superposition diagram of the first conductive layer, the second semiconductor layer, the third conductive layer and the fourth conductive layer.
  • the orthographic projection of the first initialization voltage signal line 86 on the base substrate 10 at least partially overlaps with the orthographic projection of the second reset control signal line or the third reset control signal line 84 on the base substrate.
  • the first initialization voltage signal line 86 extending along the first direction X is electrically connected to a portion of the first initialization voltage connection portion 349 through the via hole VH9, and another portion (e.g., the other end) of the first initialization voltage connection portion 349 is electrically connected to the base substrate 10 through the via hole VH10.
  • the first electrode of the first reset transistor T1 is electrically connected to the second electrode of the first reset transistor T1 , and the second electrode of the first reset transistor is electrically connected to the connection portion 343 ′ through the via hole VH20 , so that the first initialization voltage signal Vinit1 refreshes the N1 node.
  • NGate is at a high level
  • T2 is turned on
  • PReseta is at a low level and is also turned on, that is, at t2 and t4
  • the first reset transistor T1 and the compensation control transistor T2 are turned on, so that the first initialization voltage signal Vinit1 can refresh the N1 node.
  • PResetb is at a high level, that is, it is in a closed state.
  • first initialization voltage signal line 86 By stacking the first initialization voltage signal line 86 with the second reset control signal line or the third reset control signal line 84, and because the signals on the first initialization voltage signal line 86 and the second reset control signal line or the third reset control signal line 84 are separated in timing and do not work at the same time, crosstalk between signals can be prevented.
  • the positive projection of the second initialization voltage signal line 87 on the base substrate 10 overlaps at least partially with the positive projection of the first reset control signal line 83 on the base substrate.
  • the second initialization voltage signal line 87 extending along the first direction X is electrically connected to a portion of the connection portion 350 through the via VH19, and the other portion (for example, the other end) of the connection portion 350 is electrically connected to the N4 node through the via VH20, so that the second initialization voltage signal Vinit2 refreshes the N4 node.
  • the second initialization voltage signal line 87 and the first reset control signal 83 By stacking the second initialization voltage signal line 87 and the first reset control signal 83, and because the second initialization voltage signal line 87 and the signals on the first reset control signal line are separated in timing (the signal PResetb and the signal PReseta are separated), they do not work at the same time, which can prevent crosstalk between the signals.
  • Fig. 37 is a partial enlarged view of a display substrate of some exemplary embodiments of the present disclosure, schematically showing a pixel driving circuit of 8 sub-pixels.
  • Fig. 38 to Fig. 47 are partial planar structural schematic views of various film layers of the display substrate shown in Fig. 37 .
  • FIG37 schematically shows a pixel driving circuit of 8 sub-pixels, including two rows of four sub-pixels arranged along a first direction X and four columns of sub-pixels arranged along a second direction Y, for a total of eight sub-pixels.
  • FIG38 to FIG47 are partial plan views of a display substrate according to the embodiment of FIG37 of the present disclosure, wherein FIG38 is a partial plan view of a light shielding layer LS of the display substrate, FIG39 is a partial plan view of a first semiconductor layer 21 of the display substrate, FIG40 is a partial plan view of a first conductive layer 31 of the display substrate, FIG41 is a partial plan view of a second conductive layer 32 of the display substrate, FIG42 is a partial plan view of a second semiconductor layer 22 of the display substrate, FIG43 is a partial plan view of a third conductive layer 33 of the display substrate, FIG44 is a partial plan view of a first insulating layer ILD of the display substrate, schematically showing a plurality of vias in the first insulating layer, FIG45 is a partial plan view of a fourth conductive layer 34 of the display substrate, and FIG46 is a partial plan view of a second insulating layer 35 of the display substrate.
  • FIG47 is a partial plan view of the PLN,
  • Fig. 48 is a schematic diagram of a partial planar structure of a hollow region of a display substrate according to some exemplary embodiments of the present disclosure.
  • Fig. 49 is a schematic diagram of a partial planar structure between adjacent hollow regions of a display substrate according to some exemplary embodiments of the present disclosure.
  • the display substrate further includes at least one hollow region M, and the at least one hollow region M includes a first side S1, a second side S2, a third side S3 and a fourth side S4, wherein the first side S1 and the second side S2 are two opposite sides of the at least one hollow region in the first direction X, and the third side S3 and the fourth side S4 are two opposite sides of the at least one hollow region in the second direction Y.
  • the display substrate includes a plurality of data lines arranged on the base substrate, and the plurality of data lines extend respectively along the second direction Y, and the plurality of data lines include a first data line W1 and a second data line W2 adjacent to the at least one hollow area, and the first data line W1 and the second data line W2 are respectively located on a first side S1 and a second side S2 of the at least one hollow area in the first direction X, the first reset control signal line 83 and the scan control signal line 81 are adjacent to the at least one hollow area, and are respectively located on a third side S3 and a fourth side S4 of the at least one hollow area in the second direction Y, and the first reset control signal line 83 and the scan control signal line 81 respectively cross the first data line W1 and the second data line W2 to surround and form the at least one hollow area M.
  • a first data line W1 extending along the second direction Y is disposed on the first side S1 of the hollow area M
  • a second data line W2 extending along the second direction Y is disposed on the second side S2 of the hollow area M.
  • the display substrate includes a plurality of data lines disposed on the base substrate, the plurality of data lines extend respectively along the second direction, the plurality of data lines include a first data line and a second data line adjacent to the at least one hollow region, the first data line and the second data line are respectively located at a first side and a second side of the at least one hollow region in the first direction, the scan control signal line 81 and the compensation control signal line 82 are adjacent to the at least one hollow region, and are respectively located at a third side and a fourth side of the at least one hollow region in the second direction, the scan control signal line 81 and the compensation control signal line 82 respectively cross the first data line W1 and the second data line W2 to surround and form the at least one hollow region M.
  • the hollow region M is located between the scan control signal line 81 and the compensation control signal line 82.
  • each of the first data line W1 and the second data line W2 includes a main body portion and a bent portion
  • the bent portion of the first data line W1 is bent relative to the main body portion of the first data line in a direction away from at least one hollow region M
  • the bent portion of the second data line is bent relative to the main body portion of the second data line in a direction away from at least one hollow region
  • the bent portion of the first data line and the bent portion of the second data line are bent in opposite directions.
  • the spacing between the bent portion W11 of the first data line W1 and the bent portion W21 of the second data line W2 is greater than the spacing between the main body portion W12 of the first data line W1 and the main body portion W22 of the second data line W2.
  • Each of the first reset control signal line 83 and the scanning control signal line 81 includes a main body portion and a bending portion.
  • the bending portion 8311 of the first reset control signal line is bent in a direction away from at least one hollow area M relative to the main body portion 8312 of the first reset control signal line.
  • the bending portion 8111 of the scanning control signal line 81 is bent in a direction away from at least one hollow area M relative to the main body portion 8112 of the scanning control signal line.
  • the bending portion 8311 of the first reset control signal line and the bending portion 8111 of the scanning control signal line are bent in opposite directions.
  • the bent portion W11 of the first data line W1 and the bent portion W21 of the second data line W2 and the bent portion 8311 of the first reset control signal line and the bent portion 8111 of the scan control signal line form a hollow area M.
  • each of the scan control signal line and the compensation control signal line includes a main body portion and a bent portion, the bent portion of the scan control signal line is bent relative to the main body portion of the scan control signal line in a direction away from the at least one hollow region, the bent portion of the compensation control signal line is bent relative to the main body portion of the compensation control signal line in a direction away from the at least one hollow region, and the bent portion of the scan control signal line and the bent portion of the compensation control signal line are bent in opposite directions.
  • the bent portion of the first data line and the bent portion of the second data line, the bent portion of the scan control signal line and the bent portion of the compensation control signal line form a hollow region M.
  • the display substrate includes a data signal located in the fourth conductive layer 34.
  • the transfer part i.e. the connection part mentioned above, a part of the data signal transfer part is electrically connected to the first data line or the second data line through the fifth via hole.
  • the orthographic projection of the data signal transfer part on the substrate substrate overlaps with the orthographic projection of the first reset control signal sub-line 831 on the substrate substrate at least partially, and the orthographic projection of the data signal transfer part on the substrate substrate overlaps with the orthographic projection of the second reset control signal sub-line 832 on the substrate substrate at least partially.
  • the orthographic projection of the data signal transfer part on the substrate substrate By overlapping the orthographic projection of the data signal transfer part on the substrate substrate with the orthographic projection of the first reset control signal sub-line or the second reset control signal sub-line on the substrate substrate at least partially, the area of the via hole is ensured, and the signal transmission is ensured.
  • the orthographic projection of the first reset control signal sub-line 831 on the substrate substrate does not overlap with the orthographic projection of the second reset control signal sub-line 832 on the substrate substrate at least partially, and the space utilization rate of the display substrate is improved without affecting the stability of the reset control signal.
  • the display device may include the display substrate described above.
  • the display device includes a display area AA and a non-display area NA, and the non-display area NA has a smaller width and a higher pixel density, thereby realizing a display device with a narrow frame and a high-density PPI.
  • the display device may include any device or product having a display function.
  • the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic garment, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.
  • PDA personal digital assistant
  • PMP portable multimedia player
  • a digital audio player a mobile medical device
  • a camera a wearable device (such as a head-mounted device, an electronic garment, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.
  • the display device according to the embodiment of the present disclosure has all the characteristics and advantages of the above-mentioned display substrate.
  • the terms “substantially,” “about,” “approximately,” “roughly,” and other similar terms are used as terms of approximation rather than as terms of degree, and they are intended to account for the inherent deviations in measured or calculated values that would be recognized by one of ordinary skill in the art. Taking into account factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), “about” or “approximately” as used herein include the stated value and mean that the particular value is within an acceptable range of deviation as determined by one of ordinary skill in the art. For example, “approximately” can mean within one or more standard deviations, or within ⁇ 30%, ⁇ 20%, ⁇ 10%, ⁇ 5% of the stated value.

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Abstract

提供一种显示基板和显示装置。显示基板包括：衬底基板；多个子像素；发光元件；多个像素驱动电路；像素驱动电路包括至少两个晶体管；设置于衬底基板上沿第一方向延伸的初始化电压信号线，用于提供初始化电压信号；设置于衬底基板上部分沿第一方向延伸的控制信号线，用于提供控制信号；在用于驱动一行子像素的像素驱动电路的一帧内，控制信号在至少一个第一时间段内控制像素驱动电路的至少两个晶体管导通，初始化电压信号在第二时间段内提供给像素驱动电路，第一时间段和第二时间段在时序上间隔设置；位于不同的导电层的初始化电压信号线在衬底基板上的正投影与控制信号线在衬底基板上的正投影至少部分重叠，重叠率为60％至100％的范围。

Description

显示基板和显示装置 技术领域
本公开涉及显示技术领域，并且具体地涉及一种显示基板和显示装置。
背景技术
随着显示技术的发展，消费者对于显示器件的画质追求越来越高，低密度的像素排布无法满足消费者的高显示画质要求，越来越多的开发者针对高密度像素显示技术进行了开发。然而，随着PPI(Pixels Per Inch)的不断增加，对显示器件的工艺要求越来越高，造成显示器件的制造成本大幅升高，不利于高密度像素显示技术的推广普及。
在本部分中公开的以上信息仅用于对本公开的技术构思的背景的理解，因此，以上信息可包含不构成现有技术的信息。
发明内容
在一个方面，提供一种显示基板，包括：衬底基板；设置在所述衬底基板上的多个子像素，所述多个子像素沿第一方向和第二方向布置，至少一个所述子像素包括发光元件；设置在所述衬底基板上的多个像素驱动电路，所述多个像素驱动电路沿第一方向和第二方向布置，所述多个像素驱动电路用于分别驱动所述多个子像素的发光元件，至少一个所述像素驱动电路包括至少两个晶体管；设置于所述衬底基板上的初始化电压信号线，所述初始化电压信号线包括沿第一方向延伸的部分，所述初始化电压信号线用于给所述像素驱动电路提供初始化电压信号；设置于所述衬底基板上的控制信号线，所述控制信号线包括沿第一方向延伸的部分，所述控制信号线用于给所述像素驱动电路提供控制信号，以控制所述像素驱动电路的至少两个晶体管导通；其中，在用于驱动一行子像素的像素驱动电路的一帧内，所述控制信号线上的控制信号在至少一个第一时间段内控制所述像素驱动电路的至少两个晶体管导通，所述初始化电压信号线上的初始化电压信号在第二时间段内提供给所述像素驱动电路，所述第一时间段和所述第二时间段在时序上间隔设置；以及所述初始化电压信号线和所述控制信号 线位于不同的导电层中，所述初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，在一个子像素内，重叠部分的面积与所述控制信号线在所述衬底基板上的正投影面积的比值在60％至100％的范围。
在本公开的一些示例性实施例中，所述像素驱动电路包括第一复位晶体管，所述第一复位晶体管包括栅极、源极和漏极，所述初始化电压信号线包括第一初始化电压信号线，所述第一初始化电压信号线与所述第一复位晶体管的源极或漏极电连接，所述第一初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，所述控制信号线包括复位控制信号线。
在本公开的一些示例性实施例中，所述像素驱动电路包括第二复位晶体管，所述第二复位晶体管包括栅极、源极和漏极，所述初始化电压信号线包括第二初始化电压信号线，所述第二初始化电压信号线与所述第二复位晶体管的源极或漏极电连接，所述第二初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，所述控制信号线包括扫描控制信号线。
在本公开的一些示例性实施例中，所述像素驱动电路包括第三复位晶体管，所述第三复位晶体管包括栅极、源极和漏极，所述初始化电压信号线包括第三初始化电压信号线，所述第三初始化电压信号线与所述第三复位晶体管的源极或漏极电连接，所述第三初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，所述控制信号线包括发光控制信号线。
在本公开的一些示例性实施例中，所述像素驱动电路包括第一复位晶体管、第二复位晶体管和第三复位晶体管，所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管中的每一个均包括栅极、源极和漏极，所述初始化电压信号线包括第一初始化电压信号线，所述第一初始化电压信号线与所述第一复位晶体管的源极或漏极电连接，所述初始化电压信号线包括第二初始化电压信号线，所述第一初始化电压信号线与所述第二复位晶体管的源极或漏极电连接，所述初始化电压信号线包括第三初始化电压信号线，所述第一初始化电压信号线与所述第三复位晶体管的源极或漏极电连接，所述第一初始化电压信号线、所述第二初始化电压信号线和所述第三初始化电压信号线中的至少一个在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠。
在本公开的一些示例性实施例中，所述像素驱动电路还包括数据写入晶体管和发光控制晶体管，所述数据写入晶体管和发光控制晶体管包括栅极、源极和漏极，所述控制信号线包括第一复位控制信号线、第二复位控制信号线、扫描控制信号线和发光控制信号线，所述第一复位控制信号线与所述第一复位晶体管的栅极电连接，所述第二复位控制信号线与所述第二复位晶体管的栅极或所述第三复位晶体管的栅极电连接，所述扫描控制信号线与所述数据写入晶体管的栅极电连接，所述发光控制信号线与所述发光控制晶体管的栅极电连接，所述第一初始化电压信号线在所述衬底基板上的正投影和所述第二复位控制信号线在所述衬底基板上的正投影至少部分重叠，所述第一初始化电压信号线在所述衬底基板上的正投影与所述第一复位控制信号线在所述衬底基板上的正投影不重叠，所述第一初始化电压信号线在所述衬底基板上的正投影与所述扫描控制信号线在所述衬底基板上的正投影不重叠，所述第一初始化电压信号线在所述衬底基板上的正投影与所述发光控制信号线在所述衬底基板上的正投影不重叠。
在本公开的一些示例性实施例中，所述第二初始化电压信号线在所述衬底基板上的正投影与所述扫描控制信号线在所述衬底基板上的正投影至少部分重叠，所述第二初始化电压信号线在所述衬底基板上的正投影与所述第二复位控制信号线在所述衬底基板上的正投影不重叠，所述第二初始化电压信号线在所述衬底基板上的正投影与所述发光控制信号线在所述衬底基板上的正投影不重叠。
在本公开的一些示例性实施例中，所述第三初始化电压信号线在所述衬底基板上的正投影与所述发光控制信号线在所述衬底基板上的正投影至少部分重叠，所述第三初始化电压信号线在所述衬底基板上的正投影与所述第一复位控制信号线在所述衬底基板上的正投影不重叠，所述第三初始化电压信号线在所述衬底基板上的正投影与所述第二复位控制信号线在所述衬底基板上的正投影不重叠，所述第三初始化电压信号线在所述衬底基板上的正投影与所述扫描控制信号线在所述衬底基板上的正投影不重叠。
在本公开的一些示例性实施例中，所述显示基板包括：设置在所述衬底基板上的第一半导体层；设置在所述第一半导体层远离所述衬底基板一侧的第一导电层；设置在所述第一导电层远离所述衬底基板一侧的第二导电层；设置在所述第二导电层远离所述衬底基板一侧的第二半导体层；设置在所述第二半导体层远离所述衬底基板一侧 的第三导电层；设置在所述第三导电层远离所述衬底基板一侧的第四导电层；设置在所述第四导电层远离所述衬底基板一侧的第五导电层，其中，所述第一初始化电压信号线位于所述第三导电层，所述第二复位控制信号线位于所述第一导电层。
在本公开的一些示例性实施例中，所述第一复位晶体管为N型晶体管，所述第一复位控制信号线包括第一复位控制信号子线和第二复位控制信号子线，所述第一复位控制信号子线和所述第二复位控制信号子线位于不同的导电层，且所述第一复位控制信号子线在所述衬底基板上的正投影与所述第二复位控制信号子线在所述衬底基板上的正投影至少部分重叠。
在本公开的一些示例性实施例中，所述第一复位晶体管包括有源层，所述第一复位晶体管的有源层位于所述第二半导体层。
在本公开的一些示例性实施例中，所述像素驱动电路还包括补偿晶体管，所述补偿晶体管包括有源层、栅极、源极和漏极，所述补偿晶体管的有源层位于所述第二半导体层，所述显示基板还包括设置于所述衬底基板上的补偿控制信号线，所述补偿控制信号线与所述补偿晶体管的栅极电连接，所述补偿控制信号线包括第一补偿控制信号子线和第二补偿控制信号子线，所述第一补偿控制信号子线位于所述第二导电层，所述第二补偿控制信号子线位于所述第三导电层，且所述第一补偿控制信号子线在所述衬底基板上的正投影与所述第二补偿控制信号子线在所述衬底基板上的正投影至少部分重叠。
在本公开的一些示例性实施例中，所述扫描控制信号线位于所述第一导电层，所述第二初始化电压信号线位于所述第四导电层。
在本公开的一些示例性实施例中，所述发光控制信号线位于所述第一导电层，所述第三初始化电压信号线位于所述第三导电层。
在本公开的一些示例性实施例中，所述第二复位控制信号线位于所述第一导电层。
在本公开的一些示例性实施例中，所述显示基板还包括位于所述衬底基板的第一电源信号线，所述第一电源信号线沿第二方向延伸，两列子像素共用一个所述第一电源信号线，所述显示基板包括位于所述第二导电层中的第一导电转接部、位于所述第四导电层中的第一电源信号线转接部和第二电压信号线转接部，位于同一行的两个相邻子像素的像素驱动电路具有各自的第一导电转接部和第二电压信号线转接部，位于同一行的两个相邻子像素的像素驱动电路共用所述第一电源信号线转接部，所述第一 电源信号线通过第一过孔与所述第一电源信号线转接部电连接，所述第一电源信号线转接部的两端分别通过第二过孔与位于同一行的两个相邻子像素的像素驱动电路的第一导电转接部电连接，所述第一导电转接部通过第三过孔与所述第二电压信号线转接部的一端电连接，所述第二电压信号线转接部的另一端通过第四过孔与第一发光控制晶体管的源极或漏极电连接。
在本公开的一些示例性实施例中，所述显示基板还包括位于第四导电层中的第一初始化电压连接部，所述第一初始化电压连接部的一端通过第五过孔与第一初始化电压信号线电连接，所述第一初始化电压连接部的另一端通过第六过孔分别与同一行的两个相邻子像素的第一复位晶体管的源极或漏极电连接。
在本公开的一些示例性实施例中，所述显示基板还包括位于第四导电层中的第二初始化电压连接部，所述第二初始化电压连接部的两端分别通过第七过孔与第三初始化电压信号线电连接，位于两端之间的中端通过第八过孔与同一行的两个相邻子像素的第三复位晶体管的源极或漏极电连接，所述第二初始化电压连接部的在所述第一方向上位于所述第一初始化电压连接部和所述第二电压信号线转接部之间。
在本公开的一些示例性实施例中，所述第一初始化电压信号线、所述第二初始化电压信号线和所述第三初始化电压信号线中的每一个的至少一部分在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影不重叠。
在本公开的一些示例性实施例中，其中，所述第一复位晶体管为P型晶体管，所述第一复位控制信号线位于所述第一导电层，所述第二初始化电压信号线在所述衬底基板上的正投影与所述第一复位控制信号线在所述衬底基板上的正投影至少部分重叠。
在本公开的一些示例性实施例中，所述第一复位晶体管包括有源层，所述第一复位晶体管的有源层位于所述第一半导体层。
在本公开的一些示例性实施例中，所述显示基板还包括至少一个镂空区域，所述至少一个镂空区域包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧为所述至少一个镂空区域在第一方向上相对的两侧，所述第三侧和所述第四侧为所述至少一个镂空区域在第二方向上相对的两侧，所述显示基板包括设置在所述衬底基板上的多个数据线，所述多个数据线分别沿第二方向延伸，所述多个数据线包括邻近所述至少一个镂空区域的第一数据线和第二数据线，所述第一数据线和所述第二数据线 在第一方向上分别位于所述至少一个镂空区域的第一侧和第二侧，所述第一复位控制信号线和所述扫描控制信号线邻近所述至少一个镂空区域，在第二方向上分别位于所述至少一个镂空区域的第三侧和第四侧，所述第一复位控制信号线和所述扫描控制信号线分别与所述第一数据线和所述第二数据线交叉，以包围形成所述至少一个镂空区域。
在本公开的一些示例性实施例中，所述显示基板还包括至少一个镂空区域，所述至少一个镂空区域包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧为所述至少一个镂空区域在第一方向上相对的两侧，所述第三侧和所述第四侧为所述至少一个镂空区域在第二方向上相对的两侧，所述显示基板包括设置在所述衬底基板上的多个数据线，所述多个数据线分别沿第二方向延伸，所述多个数据线包括邻近所述至少一个镂空区域的第一数据线和第二数据线，所述第一数据线和所述第二数据线在第一方向上分别位于所述至少一个镂空区域的第一侧和第二侧，所述第一复位控制信号线和所述补偿控制信号线邻近所述至少一个镂空区域，在第二方向上分别位于所述至少一个镂空区域的第三侧和第四侧，所述第一复位控制信号线和所述补偿控制信号线分别与所述第一数据线和所述第二数据线交叉，以包围形成所述至少一个镂空区域。
在本公开的一些示例性实施例中，所述第一数据线和所述第二数据线中的每一个包括主体部分和弯折部分，所述第一数据线的弯折部分相对于所述第一数据线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述第二数据线的弯折部分相对于所述第二数据线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述第一数据线的弯折部分和所述第二数据线的弯折部分朝相反的方向弯折。
在本公开的一些示例性实施例中，所述第一复位控制信号线和所述扫描控制信号线中的每一个包括主体部分和弯折部分，所述第一复位控制信号线的弯折部分相对于所述第一复位控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述扫描控制信号线的弯折部分相对于所述扫描控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述第一复位控制信号线的弯折部分和所述扫描控制信号线的弯折部分朝相反的方向弯折。
在本公开的一些示例性实施例中，所述第一复位控制信号线和所述补偿控制信号线中的每一个包括主体部分和弯折部分，所述第一复位控制信号线的弯折部分相对于 所述第一复位控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述补偿控制信号线的弯折部分相对于所述补偿控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述第一复位控制信号线的弯折部分和所述补偿控制信号线的弯折部分朝相反的方向弯折。
在本公开的一些示例性实施例中，在一个子像素内，重叠部分的面积与所述控制信号线在所述衬底基板上的正投影面积的比值在80％至95％的范围。
在本公开的一些示例性实施例中，所述显示基板包括位于所述第四导电层中的数据信号转接部，所述数据信号转接部的一部分通过第五过孔与所述第一数据线或所述第二数据线电连接，在第一区域中，所述数据信号转接部在所述衬底基板上的正投影与所述第一复位控制信号子线在所述衬底基板上的正投影至少部分重叠，所述数据信号转接部在所述衬底基板上的正投影与所述第二复位控制信号子线在所述衬底基板上的正投影至少部分重叠，所述第一复位控制信号子线在所述衬底基板上的正投影与所述第二复位控制信号子线在所述衬底基板上的正投影至少部分不重叠。
在本公开的另一方面，提供了一种显示基板，包括：衬底基板；设置在所述衬底基板上的多个子像素，所述多个子像素沿第一方向和第二方向布置，至少一个所述子像素包括发光元件；设置在所述衬底基板上的多个像素驱动电路，所述多个像素驱动电路沿第一方向和第二方向布置，所述多个像素驱动电路用于分别驱动所述多个子像素的发光元件，至少一个所述像素驱动电路包括第一复位晶体管、第二复位晶体管和第三复位晶体管；设置于所述衬底基板上的初始化电压信号线，所述初始化电压信号线包括沿第一方向延伸的部分，所述初始化电压信号线用于给所述像素驱动电路提供初始化电压信号，所述初始化电压信号线包括第一初始化电压信号线、第二初始化电压信号线和第三初始化电压信号线，所述第一初始化电压信号线、所述第二初始化电压信号线和所述第三初始化电压信号线分别与所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管的第一极电连接；设置于所述衬底基板上的控制信号线，所述控制信号线包括沿第一方向延伸的部分，所述控制信号线用于给所述像素驱动电路提供控制信号，以控制所述像素驱动电路的至少一个晶体管导通；其中，在用于驱动一行子像素的像素驱动电路的一帧内，所述控制信号线上的控制信号在至少一个第一时间段内控制所述像素驱动电路的至少两个晶体管导通，所述初始化电压信号线上的初始化电压信号在第二时间段内提供给所述像素驱动电路，所述第一时间段和所述 第二时间段在时序上间隔设置；以及所述初始化电压信号线和所述控制信号线位于不同的导电层中，所述第一初始化电压信号线、所述第二初始化电压信号线和所述第三初始化电压信号线中每一个在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，在一个子像素内，重叠部分的面积与所述控制信号线在所述衬底基板上的正投影面积的比值在60％至100％的范围。
在本公开的再一方面，提供了一种显示装置，包括上文所述的显示基板。
附图说明
通过参照附图详细描述本公开的示例性实施例，本公开的特征及优点将变得更加明显。
图1是根据本公开的实施例的显示基板的平面示意图；
图2是根据本公开的一些示例性实施例的显示基板的一个像素驱动电路的等效电路图；
图3是根据本公开的一些示例性实施例的用于驱动像素驱动电路的信号的时序图；
图4是根据本公开的一些示例性实施例的显示基板的局部平面图；
图5至图14分别是根据本公开的一些示例性实施例的显示基板的局部平面图，其中，图5为所述显示基板的遮光层的局部平面图，图6为所述显示基板的第一半导体层的局部平面图，图7是所述显示基板的第一导电层的局部平面图，图8为所述显示基板的第二导电层的局部平面图，图9为所述显示基板的第二半导体层的局部平面图，图10是所述显示基板的第三导电层的局部平面图，图11是所述显示基板的第一绝缘层的局部平面图，其示意性示出了位于该第一绝缘层中的多个过孔，图12是所述显示基板的第四导电层的局部平面图，图13是所述显示基板的第二绝缘层的局部平面图，其示意性示出了位于该第二绝缘层中的多个过孔，图14是所述显示基板的第五导电层的局部平面图；
图15是根据本公开的示例性实施例的显示基板的局部平面图，其示意性示出了第一导电层和第三导电层的叠加图；
图16是根据本公开的示例性实施例的显示基板的局部平面图，其示意性示出了第一导电层、第三导电层和第四导电层的叠加图。
图17是根据本公开的示例性实施例的显示基板的局部平面图，其示意性示出了第一导电层和第三导电层的叠加图；
图18是根据本公开的示例性实施例的显示基板的局部平面图，其示意性示出了第二半导体层、第一导电层、第二导电层、第三导电层和第四导电层的叠加图；
图19是根据本公开的示例性实施例的显示基板的局部放大图，其示意性示出了第一电源信号线的转接方式；；
图20是根据本公开的示例性实施例的显示基板的局部放大图，其示意性示出了叠层设计的信号线的错位设计；
图21是根据本公开的另一些示例性实施例的用于驱动像素驱动电路的信号的时序图；
图22是根据本公开的另一些示例性实施例的显示基板的局部平面图；
图23至图32分别是根据本公开的一些示例性实施例的显示基板的局部平面图，其中，图23为所述显示基板的遮光层的局部平面图，图24为所述显示基板的第一半导体层的局部平面图，图25是所述显示基板的第一导电层的局部平面图，图26为所述显示基板的第二导电层的局部平面图，图27为所述显示基板的第二半导体层的局部平面图，图28是所述显示基板的第三导电层的局部平面图，图29是所述显示基板的第一绝缘层的局部平面图，其示意性示出了位于该第一绝缘层中的多个过孔，图30是所述显示基板的第四导电层的局部平面图，图31是所述显示基板的第二绝缘层的局部平面图，其示意性示出了位于该第二绝缘层中的多个过孔，图32是所述显示基板的第五导电层的局部平面图；
图33和图35是图23所示的显示基板的局部平面图，其示意性示出了第一导电层和第三导电层的叠加图；图34和图36是图23所示的显示基板的局部平面图，其示意性示出了第一导电层、第三导电层和第四导电层的叠加图；
图37是本公开的一些示例性实施例的显示基板的局部放大图；
图38至图47是图37所示的显示基板的各个膜层的局部平面结构示意图；
图48是本公开示例性的一些示例性实施例的显示基板的镂空区域的局部平面结构示意图；
图49是本公开示例性的一些示例性实施例的显示基板的相邻的镂空区域之间的局部平面结构示意图；
图50是本公开示例性的一些实施例的显示基板的沿图4中的A-A’线截取的截面示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开的保护范围。
需要说明的是，在附图中，为了清楚和/或描述的目的，可以放大元件的尺寸和相对尺寸。如此，各个元件的尺寸和相对尺寸不必限于图中所示的尺寸和相对尺寸。在说明书和附图中，相同或相似的附图标号指示相同或相似的部件。
当元件被描述为“在”另一元件“上”、“连接到”另一元件或“结合到”另一元件时，所述元件可以直接在所述另一元件上、直接连接到所述另一元件或直接结合到所述另一元件，或者可以存在中间元件。然而，当元件被描述为“直接在”另一元件“上”、“直接连接到”另一元件或“直接结合到”另一元件时，不存在中间元件。用于描述元件之间的关系的其他术语和/或表述应当以类似的方式解释，例如，“在……之间”对“直接在……之间”、“相邻”对“直接相邻”或“在……上”对“直接在……上”等。此外，术语“连接”可指的是物理连接、电连接、通信连接和/或流体连接。此外，X轴、Y轴和Z轴不限于直角坐标系的三个轴，并且可以以更广泛的含义解释。例如，X轴、Y轴和Z轴可彼此垂直，或者可代表彼此不垂直的不同方向。出于本公开的目的，“X、Y和Z中的至少一个”和“从由X、Y和Z构成的组中选择的至少一个”可以被解释为仅X、仅Y、仅Z、或者诸如XYZ、XYY、YZ和ZZ的X、Y和Z中的两个或更多个的任何组合。如文中所使用的，术语“和/或”包括所列相关项中的一个或多个的任何组合和所有组合。
需要说明的是，虽然术语“第一”、“第二”等可以在此用于描述各种部件、构件、元件、区域、层和/或部分，但是这些部件、构件、元件、区域、层和/或部分不应受到这些术语限制。而是，这些术语用于将一个部件、构件、元件、区域、层和/或部分与另一个相区分。因而，例如，下面讨论的第一部件、第一构件、第一元件、第一区域、第一层和/或第一部分可以被称为第二部件、第二构件、第二元件、第二区域、第二层 和/或第二部分，而不背离本公开的教导。
为了便于描述，空间关系术语，例如，“上”、“下”、“左”、“右”等可以在此被使用，来描述一个元件或特征与另一元件或特征如图中所示的关系。应理解，空间关系术语意在涵盖除了图中描述的取向外，装置在使用或操作中的其它不同取向。例如，如果图中的装置被颠倒，则被描述为“在”其它元件或特征“之下”或“下面”的元件将取向为“在”其它元件或特征“之上”或“上面”。
需要说明的是，在本文中，表示“同一层”指的是采用同一成膜工艺形成用于形成特定图形的膜层，然后利用同一掩模板通过一次构图工艺对该膜层图案化所形成的层结构。根据特定图形的不同，一次构图工艺可能包括多次曝光、显影或刻蚀工艺，而形成的层结构中的特定图形可以是连续的也可以是不连续的。即，位于“同一层”的多个元件、部件、结构和/或部分由相同的材料构成，并且通过同一次构图工艺形成，通常，位于“同一层”的多个元件、部件、结构和/或部分具有大致相同的厚度。
本领域技术人员应该理解，在本文中，除非另有说明，表述“高度”或“厚度”指的是沿垂直于显示基板设置的各个膜层的表面的尺寸，即沿显示基板的出光方向的尺寸，或称为沿显示装置的法线方向的尺寸。
在本文中，使用方向性表述“第一方向”、“第二方向”来描述沿像素区的不同方向，例如，像素区的纵向方向和横向方向，或者子像素排列的行方向和列方向。应该理解，这样的表示仅为示例性的描述，而不是对本公开的限制。
本公开实施例中采用的晶体管均可以为薄膜晶体管或场效应管或其他特性相同的器件。由于这里采用的薄膜晶体管的源极、漏极是对称的，所以其源极、漏极可以互换。在本公开的实施例中，晶体管可以包括栅极、第一极和第二极，其中，第一极可以表示源极和漏极中的一个，第二极可以表示源极和漏极中的另一个。在以下示例中主要以用作驱动晶体管的P型薄膜晶体管的情况进行描述，其他晶体管根据电路设计与驱动晶体管具有相同或不同的类型。类似地，在其他实施例中，驱动晶体管也可以被示为N型薄膜晶体管。
在本文中，表述“PPI”(即Pixels Per Inch)表示像素密度，其所表示的是每英寸设置的像素数量。通常，PPI数值越高，代表显示装置能够以越高的密度显示图像。
本公开的一些示例性实施例提供一种显示基板，所述显示基板包括：衬底基板；设置在所述衬底基板上的多个子像素，所述多个子像素沿第一方向和第二方向阵列布 置，至少一个所述子像素包括发光元件；设置在所述衬底基板上的多个像素驱动电路，所述多个像素驱动电路沿第一方向和第二方向阵列布置，所述多个像素驱动电路用于分别驱动所述多个子像素的发光元件，至少一个所述像素驱动电路包括至少一个晶体管；设置于所述衬底基板上的初始化电压信号线，所述初始化电压信号线沿第一方向延伸，所述初始化电压信号线用于给所述像素驱动电路提供初始化电压信号；设置于所述衬底基板上的控制信号线，所述控制信号线沿第一方向延伸，所述控制信号线用于给所述像素驱动电路提供控制信号，以控制所述像素驱动电路的至少一个晶体管导通；其中，在用于驱动一行子像素的像素驱动电路的一帧内，所述控制信号线上的控制信号在至少一个第一时间段内控制所述像素驱动电路的至少一个晶体管导通，所述初始化电压信号线上的初始化电压信号在第二时间段内提供给所述像素驱动电路，所述第一时间段和所述第二时间段在时序上间隔设置；以及所述初始化电压信号线和所述控制信号线位于不同的导电层中，所述初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，在一个子像素内，重叠部分的面积与所述初始化电压信号线在所述衬底基板上的正投影面积或所述控制信号线在所述衬底基板上的正投影面积的比值在60％至100％的范围。在本公开的实施例中，将时序上间隔的信号线进行叠层设计，有效优化像素驱动电路的版图设计，在满足工艺规格的前提下，有利于实现高PPI的像素设计，且有利于提高显示装置的显示质量。
图1是根据本公开的实施例的显示基板的平面示意图。参照图1，根据本公开的实施例的显示基板可以包括衬底基板10和设置在衬底基板10上的像素单元PX。
所述显示基板可以包括显示区域AA和非显示区域NA。显示区域AA可以是设置有显示图像的像素单元PX的区域。稍后将描述每个像素单元PX。非显示区域NA是不设置像素单元PX的区域，即可以是不显示图像的区域。非显示区域NA与最终显示装置中的边框对应，并且边框的宽度可以根据非显示区域NA的宽度来确定。
显示区域AA可以具有各种形状。例如，显示区域AA可以以诸如包括直边的闭合形状的多边形(例如矩形)、包括曲边的圆形、椭圆形等以及包括直边和曲边的半圆形、半椭圆形等的各种形状设置。在本公开的实施例中，将显示区域AA设置为具有包括直边的四边形形状的一个区域，应该理解，这仅是本公开的示例性实施例，而不是对本公开的限制。
非显示区域NA可以设置在显示区域AA的至少一侧处。在本公开的实施例中，非显示区域NA可以围绕显示区域AA的外周。在本公开的实施例中，非显示区域NA可以包括在第一方向X上延伸的横向部分和在第二方向Y上延伸的纵向部分。
像素单元PX设置在显示区域AA中。像素单元PX是用于显示图像的最小单元，并且可以设置为多个。例如，像素单元PX可以包括发射白色光和/或彩色光的发光器件。
像素单元PX可以设置成多个，以沿着在第一方向X上延伸的行和在第一方向Y上延伸的列呈矩阵形式布置。然而，本公开的实施例不具体限制像素单元PX的布置形式，并且可以以各种形式布置像素单元PX。例如，像素单元PX可以布置为使得相对于第一方向X和第一方向Y倾斜的方向成为列方向，并且使得与列方向交叉的方向成为行方向。
也就是说，多个像素单元PX沿第一方向X和第二方向Y成阵列排列，以形成多行像素单元和多列像素单元。
一个像素单元PX可以包括多个子像素。例如，一个像素单元PX可以包括3个子像素，即第一子像素SP1、第二子像素SP2和第三子像素SP3。例如，第一子像素SP1可以为红色子像素，第二子像素SP2可以为绿色子像素，第三子像素SP3可以为蓝色子像素。
需要说明的是，在本公开的实施例中，一个像素单元包括的子像素的数量并不做特别的限制，并不局限于上述的3个。
例如，在图1所示的示例性实施例中，示意性示出了扫描控制信号线110和数据线120。即，所述显示基板还可以包括：设置于所述衬底基板的多个扫描控制信号线110和多个数据线120，所述多个扫描控制信号线110分别给多行像素单元供应扫描控制信号，所述多个数据线120分别给多列像素单元供应数据信号。所述扫描控制信号线110沿第一方向X延伸，所述多个扫描控制信号线110沿第二方向Y间隔排列。所述数据线120沿第二方向Y延伸，所述多个数据线120沿第一方向X间隔排列。
例如，所述扫描控制信号线110可以为横向走线的代表，所述数据线120可以为纵向走线的代表。应该理解，所述横向走线还可以包括其他类型或用于供应其他信号的走线，所述纵向走线还可以包括其他类型或用于供应其他信号的走线。
每一个子像素可以包括发光元件和用于驱动发光元件的像素驱动电路。例如，在 OLED显示基板或显示面板中，子像素的发光元件可以包括叠层设置的阳极、发光材料层和阴极。各个子像素的发光元件的阳极间隔设置，以沿着在第一方向X上延伸的行和在第一方向Y上延伸的列呈矩阵形式布置。
下面，以8T1C(即八个晶体管和一个电容)像素驱动电路为例，对所述像素驱动电路的结构进行详细描述，但是，本公开的实施例并不局限于8T1C像素驱动电路，在不冲突的情况下，其它已知的像素驱动电路结构都可以应用于本公开的实施例中。需要说明的是，在本公开的实施例中，各像素驱动电路除了可以为图2所示的8T1C结构之外，还可以为包括其他数量的晶体管的结构，如7T1C结构、7T2C结构、6T1C结构、6T2C结构或者9T2C结构，本公开实施例对此不作限定。
图2是根据本公开的一些示例性实施例的显示基板的一个像素驱动电路的等效电路图。所述像素驱动电路用于驱动有机发光二极管(即OLED)。参照图2，所述像素驱动电路可以包括第一复位晶体管T1、补偿晶体管T2、驱动晶体管T3、数据写入晶体管T4、第一发光控制晶体管T5、第二发光控制晶体管T6，第二复位晶体管T7、第三复位晶体管T8以及存储电容器Cst。所述显示基板还包括第一扫描控制信号线81(对应于图2中的第一扫描控制信号PGate)、第二扫描控制信号线82(对应于图2中的第二扫描控制信号NGate)、第一复位控制信号线83(对应于图2中的第一复位控制信号PReset)、第二复位控制信号线84(对应于图2中的第二复位控制信号NReset)、发光控制信号线85(对应于图2中的发光控制信号EM)、第一初始化电压信号线86(对应于图2中的第一初始化电压信号Vinit1)、第二初始化电压信号线87(对应于图2中的第二初始化电压信号Vinit2)、第三初始化电压信号线88(对应于图3中的第三初始化电压信号Vinit3)、数据线91(对应于图2中的数据信号Data)、第一电源信号线92(对应于图2中的第一电源信号ELVDD)和第二电源信号线(对应于图2中的第二电源信号ELVSS)。
继续参照图2，第一复位晶体管T1的第一极与第一初始化电压信号线86电连接，第一复位晶体管T1的第二极与驱动晶体管T3的栅极电连接，即节点N1，第一复位晶体管T1的栅极与第一复位控制信号线83电连接，在第一复位控制信号线83的控制下，选择性地将第一初始化电压信号线86传输的第一初始化电压信号Vinit1写入节点N1。
补偿晶体管T2的第一极与驱动晶体管T3的第一极电连接，即节点N3；补偿晶 体管T2的第二极与驱动晶体管T3的栅极电连接，即节点N1；补偿晶体管T2的栅极与第二扫描控制信号线82电连接以接收补偿控制信号。
驱动晶体管T3的第一极与补偿晶体管T2的第一极电连接，即节点N3；驱动晶体管T3的第二极与第一发光控制晶体管T5的第二极电连接，即节点N2；驱动晶体管T3的栅极电连接至节点N1。
数据写入晶体管T4的第一极与驱动晶体管T3的第二极电连接，即节点N2；数据写入晶体管T4的第二极与数据线91电连接以接收数据信号，数据写入晶体管T4的栅极与第一扫描控制信号线81电连接以接收第一扫描控制信号。在第一扫描控制信号的控制下，选择性地将数据信号写入节点N2。
第一发光控制晶体管T5的第一极与第一电源信号线92电连接以接收第一电源信号ELVDD，第一发光控制晶体管T5的第二极与驱动晶体管T3的第二极电连接(即节点N2)，第一发光控制晶体管T5的栅极与发光控制信号线85电连接以接收发光控制信号EM。
第二发光控制晶体管T6的第一极与驱动晶体管T3的第一极电连接(即节点N3)，第二发光控制晶体管T6的第二极与发光元件120的第一电极电连接(即节点N4)，第二发光控制晶体管T6的栅极与发光控制信号线85电连接以接收发光控制信号EM。
第二复位晶体管T7的第一极与第二初始化电压信号线87电连接以接收第二初始化电压信号Vinit2，第二复位晶体管T7的第二极与发光元件130的第一电极电连接(即N4节点)，第二复位晶体管T7的栅极与第二复位控制信号线84电连接以接收第二复位控制信号。
第三复位晶体管T8的第一极与第三初始化电压信号线88电连接以接收第三初始化电压信号Vinit3，第三复位晶体管T8的第二极与驱动晶体管T3的第二极电连接(即节点N2)，第三复位晶体管T8的栅极与第二复位控制信号线84电连接以接收第二复位控制信号。
存储电容器Cst的一端(下文称为第一电容电极)Cst1与驱动晶体管T3的栅极电连接(即节点N1)，存储电容器Cst的另一端(下文称为第二电容电极)Cst2电连接至第一电源信号线92。发光元件130的阴极电连接至第二电源信号线，以接收第二电源信号ELVSS。相应地，发光元件130从驱动晶体管T3接收驱动电流以发光，从而显示图像。
例如，上述第一电源信号线92和第二电源信号线可以分别为传输电压信号ELVDD和ELVSS的信号线，它们可以与电压源连接以输出恒定的电压信号，例如正电压信号和负电压信号。
需要说明的是，按照晶体管半导体特性的不同，晶体管可以分为N型晶体管和P型晶体管。其中，在晶体管作为开关晶体管使用时，N型开关晶体管受控于高电平开关控制信号而导通，受控于低电平开关控制信号而关闭。P型开关晶体管受控于低电平开关控制信号而导通，受控于高电平开关控制信号而关闭。
在本公开的实施例中，所述像素驱动电路可以采用LTPO电路，即用低温多晶硅(LTPS)技术和氧化物(IGZO)制备成LTPO电路，低温多晶硅薄膜晶体管(Low Temperature Poly Silicon，简称LTPS)，采用多晶硅沉积形成有源层。LTPS具有较高的电子迁移率，反应速度较快，且有高亮度、高分辨率与低耗电量等优点。氧化物薄膜晶体管(oxide thin-film transistor，简称oxide TFT)，例如以氧化物半导体作为TFT的有源层，如铟镓锌氧化物(Indium Gallium Zinc Oxide，简称IGZO)，氧化物半导体具有较高的电子迁移率、良好的关断特性，相比LTPS，氧化物半导体制程简单，与非晶硅制程相容性较高。当然，氧化物薄膜晶体管还可以为其他金属氧化物半导体，例如，铟锌锡氧化物(IZTO)或铟镓锌锡氧化物(IGZTO)等。采用氧化物薄膜晶体管可以有效减小晶体管的尺寸以及防止漏电流，从而在使得该像素电路的可以适用于低频驱动的同时，还可以增加显示基板的分辨率。
在本公开的一些示例性实施例中，示例性的8T1C电路中包含8个薄膜晶体管(T1-T8)，其中T1和T2是N型薄膜晶体管NMOS，采用oxide TFT；其余的为P型的薄膜晶体管PMOS，采用LTPS TFT。相应地，施加于晶体管T1的栅极上的复位控制信号称为NReset，施加于晶体管T2的栅极上的扫描控制信号称为NGate，施加于晶体管T4的栅极上的扫描控制信号称为PGate，施加于晶体管T7、T8的栅极上的复位控制信号称为PReset。
需要注意的是，在上述说明中，节点N1、节点N2、节点N3和节点N4并非表示实际存在的部件，而是表示电路图中相关电路连接的汇合点。
还需要说明的是，在本公开的实施例中，有效信号(电平)是指用于开启相应开关元件的信号(电平)，无效信号(电平)是指用于关闭相应开关元件的信号(电平)。同理，在本公开的其他实施例中，均作此解释。有效电平和无效电平仅代表该信号的 电平有2个状态量，不代表全文中有效电平或无效电平具有特定的数值。
图3是根据本公开的一些示例性实施例的用于驱动像素驱动电路的信号的时序图。结合参照图2和图3，本公开的实施例提供了一种像素驱动电路的驱动方法，应用于本公开任一实施例描述的像素驱动电路，所述驱动方法的刷新驱动周期(即一帧)可以包括第一复位阶段、写入阶段t4、第一偏置阶段t5。需要说明的是，在图3的实施例中，EM表示发光控制信号线85上传输的发光控制信号，NGate表示第二扫描控制信号线82上传输的第二扫描控制信号，NReset表示第一复位控制信号线83上传输的第一复位控制信号，PGate表示第一扫描控制信号线81上传输的第一扫描控制信号线，PReset表示第二复位控制信号线84上传输的第二复位控制信号。
例如，在本实施例中，所述第一复位阶段可以包括第一复位子阶段t1、第二复位子阶段t2、第三复位子阶段t3。在第一复位子阶段t1、第二复位子阶段t2、第三复位子阶段t3，选择性地对驱动晶体管T3的各个节点N1、N2、N3进行复位。
在写入阶段t4，EM为高电平，NGate为高电平，NReset为低电平，PGate为低电平，PReset为高电平。补偿晶体管T2和数据写入晶体管T4导通。在此阶段，驱动晶体管T3导通，通过数据写入晶体管T4和补偿晶体管T2将数据信号施加至所述驱动晶体管T3的栅极，实现数据信号的写入，并实现对所述驱动晶体管T3栅极的电压补偿。在此阶段，节点N1处的电压为Vdata+Vth，节点N2处的电压为Vdata，节点N3处的电压为Vdata，其中Vth为驱动晶体管T3的阈值电压。
在第一偏置阶段t5，EM为高电平，NGate为低电平，NReset为低电平，PGate为高电平，PReset为低电平。第二复位晶体管T7和第三复位晶体管T8导通。在此阶段，驱动晶体管T3导通，通过第三复位晶体管T8将第三初始化电压信号Vinit3施加至所述驱动晶体管T3的第一极和第二极。在此阶段，节点N1处的电压为Vdata+Vth，节点N2处的电压为Vinit3，节点N3处的电压为Vinit3，其中Vth为驱动晶体管T3的阈值电压。在此阶段，通过第三复位晶体管T8对于节点N2和节点N3复位为高电压，相当于又对驱动晶体管T3的栅源极加上一个负偏压，这样在发光阶段会重新改变驱动晶体管T3的阈值电压的恢复过程。
需要说明的是，所述驱动方法的刷新驱动周期(即一帧)还可以包括第一发光阶段t6，在所述第一发光阶段t6，发光元件130响应所述驱动晶体管T3的驱动电流而发光。发光控制信号EM为低电平，第一发光控制晶体管T5和第二发光控制晶体管 T6在低电平时导通，驱动晶体管T3导通；其他晶体管在相应的开关控制信号控制下均处于关闭状态。
驱动晶体管T3工作处于饱和状态，根据饱和状态电流特性可知，流过驱动晶体管T3且用于驱动发光元件130发光的饱和电流I与(Vdata-VDD)2成正比。可以看出发光元件130的工作电流已经不受驱动晶体管T3的阈值电压Vth的影响，彻底解决了由于工艺制程以及长时间的操作造成的驱动晶体管T3的阈值电压Vth漂移，有效改善低频闪烁(Flicker)等问题，从而改善了面板显示的不均匀性。
结合参照图2和图3，在时序图中，第二复位控制信号线84上传输的第二复位控制信号PReset在阶段t1、t5处于有效状态，而在阶段t1、t5，第一复位控制信号线83上传输的第一复位控制信号NReset均为低电平，即第一复位晶体管T1处于关闭状态，此时，第一初始化电压信号Vinit1不会通过第一复位晶体管T1传输给节点N1。实际上，第一复位控制信号线83上传输的第一复位控制信号NReset在阶段t2、t3为高电平，即第一复位晶体管T1在阶段t2、t3导通。也就是说，第二复位控制信号线84上传输的第二复位控制信号PReset与第一初始化电压信号Vinit1在时序上是间隔开的。
在时序图中，第一扫描控制信号线81上传输的第一扫描控制信号PGate在阶段t4处于有效状态，而在阶段t4，第二复位控制信号线84上传输的第二复位控制信号PReset均为高电平，即第二复位晶体管T7和第三复位晶体管T8均处于关闭状态，此时，第二初始化电压信号Vinit2不会通过第二复位晶体管T7传输给节点N4，第三初始化电压信号Vinit3不会通过第三复位晶体管T8传输给节点N2。实际上，第二复位控制信号线84上传输的第二复位控制信号PReset在阶段t1、t5为低电平，即第二复位晶体管T7和第三复位晶体管T8在阶段t1、t5导通。也就是说，第一扫描控制信号线81上传输的第一扫描控制信号PGate与第二初始化电压信号Vinit2在时序上是间隔开的。
在时序图中，发光控制信号线85上传输的发光控制信号EM在阶段t1～t5均处于无效状态，第二复位控制信号线84上传输的第二复位控制信号PReset在阶段t1、t5为低电平，即第二复位晶体管T7和第三复位晶体管T8在阶段t1、t5导通。也就是说，发光控制信号线85上传输的发光控制信号EM与第三初始化电压信号Vinit3在时序上是间隔开的。
在本公开的实施例中，可以将传输这些在时序上间隔开的信号的信号线进行叠层设计，例如，由于第二复位控制信号线84上传输的第二复位控制信号PReset与第一 初始化电压信号Vinit1在时序上是间隔开的，所以，可以将第二复位控制信号线84与第一初始化电压信号线86进行叠层设计；由于第一扫描控制信号线81上传输的第一扫描控制信号PGate与第二初始化电压信号Vinit2在时序上是间隔开的，所以，可以将第一扫描控制信号线81与第二初始化电压信号线87进行叠层设计；由于发光控制信号线85上传输的发光控制信号EM与第三初始化电压信号Vinit3在时序上是间隔开的，所以，可以将发光控制信号线85与第三初始化电压信号线88进行叠层设计。这样，由于叠层设计的各个信号线上传输的信号在时序上是错开的，所以，不会对信号产生不利的影响，同时，可以有效地利用显示基板的空间进行布局，有利于实现高PPI的显示面板。
图4是根据本公开的一些示例性实施例的显示基板的局部平面图，其示意性示出了2个相邻的子像素的像素驱动电路。图5至图14分别是根据本公开的一些示例性实施例的显示基板的局部平面图，其中，图5为所述显示基板的遮光层的局部平面图，图6为所述显示基板的第一半导体层的局部平面图，图7是所述显示基板的第一导电层的局部平面图，图8为所述显示基板的第二导电层的局部平面图，图9为所述显示基板的第二半导体层的局部平面图，图10是所述显示基板的第三导电层的局部平面图，图11是所述显示基板的第一绝缘层的局部平面图，其示意性示出了位于该第一绝缘层中的多个过孔，图12是所述显示基板的第四导电层的局部平面图，图13是所述显示基板的第二绝缘层的局部平面图，其示意性示出了位于该第二绝缘层中的多个过孔，图14是所述显示基板的第五导电层的局部平面图。图50是本公开示例性的一些实施例的显示基板的沿图4中的A-A’线截取的截面示意图。
结合参照图4至图14以及图50，所述显示基板可以包括衬底基板10，设置于衬底基板10上的遮光层LS，设置于遮光层LS远离衬底基板一侧的第一半导体层21，设置于第一半导体层21远离衬底基板一侧的第一导电层31，设置于第一导电层31远离衬底基板一侧的第二导电层32，设置于第二导电层32远离衬底基板一侧的第二半导体层22，设置于第二半导体层22远离衬底基板一侧的第三导电层33，设置于第三导电层33远离衬底基板一侧的第四导电层34，设置于第四导电层34远离衬底基板一侧的第五导电层35。
例如，所述第一导电层31、所述第二导电层32和所述第三导电层33可以是由栅极材料构成的导电层，例如Mo。例如，所述第四导电层34和所述第五导电层35可以 是由源漏极材料构成的导电层，例如Ti/Al/Ti。
构成有源层的半导体材料例如可以包括非晶硅、多晶硅、氧化物半导体等，氧化物半导体材料例如可以包括IGZO(铟镓锌氧化物)、ZnO(氧化锌)等。
在本公开的实施例中，两个相邻的导电层之间可以设置至少一个绝缘层，所述绝缘层可以由例如氮化硅、氧化硅或氮氧化硅等的绝缘材料构成，绝缘层具有单个膜层结构，也可以具有由多个膜层构成的叠层结构。例如，在图示的实施例中，所述显示基板可以包括设置在第三导电层33与第四导电层34之间的第一绝缘层ILD，以及设置在第四导电层34与第五导电层35之间的第二绝缘层PLN。应该理解，所述显示基板还可以更多的绝缘层，绝缘层的结构可以参照现有的显示基板中绝缘层的结构，在此不再赘述。
图6示出了第一半导体层21。例如，如图6所示，第一半导体层21可用于制作上述的驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第二复位晶体管T7以及第三复位晶体管T8的有源层，以用于形成上述晶体管的沟道区。第一半导体层21可以包括各子像素的上述晶体管的有源区图案(沟道区)和掺杂区图案(源漏区)，且同一像素驱动电路中的上述晶体管的有源区图案和掺杂区图案一体设置。
例如，第一半导体层21可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。例如，上述的源极区域和漏极区域可为掺杂有p型杂质的区域。
图7示出了位于第一半导体层21远离衬底基板一侧的第一导电层31。例如，如图7所示，第一扫描控制信号线81、存储电容器Cst的第一电容电极Cst1、发光控制信号线85和第二复位控制信号线84可以位于第一导电层31中。例如，第一导电层31可以包括驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第二复位晶体管T7以及第三复位晶体管T8的栅极。
需要说明的是，图6中的各虚线矩形框示出了第一半导体层21与第一导电层31交叠的各个部分，即沟道区。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为 第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
例如，结合参照图4、图6和图7，数据写入晶体管T4的栅极可以为第一扫描控制信号线81与第一半导体层21交叠的部分。第一发光控制晶体管T6的栅极可以为发光控制信号线85与第一半导体层21交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线85与第一半导体层21交叠的第二部分。第三复位晶体管T8的栅极为第二复位控制信号线84与第一半导体层21交叠的第一部分，第二复位晶体管T7的栅极为第二复位控制信号线84与第一半导体层21交叠的第二部分。
图8示出了位于第一导电层31远离衬底基板一侧的第二导电层32。例如，如图8所示，第二扫描控制信号线82、存储电容器Cst的第二电容电极Cst2以及第一复位控制信号线83可以位于第二导电层32中。
图9示出了位于第二导电层32远离衬底基板一侧的第二半导体层22。例如，如图9所示，第二半导体层22包括第一复位晶体管T1和补偿晶体管T2的沟道区。例如，第一复位晶体管T1和补偿晶体管T2中的有源层采用氧化物半导体的情况下，因用氧化物半导体的晶体管具备磁滞特性好、漏电流低的特点，故可以采用氧化物半导体的晶体管代替晶体管中的低温多晶硅材料，形成低温多晶硅氧化物的(LTPO)像素驱动电路，实现低漏电，利于提高晶体管的栅极电压的稳定性。
例如，如图4、图8和图9所示，第一复位晶体管T1的栅极可以为第一复位控制信号线83与第二半导体层22交叠的部分，补偿晶体管T2的栅极可以为第二扫描控制信号线82与第二半导体层22交叠的部分。
图10示出了第二半导体层22远离衬底基板一侧的第三导电层33。例如，如图10所示，另一第二扫描控制信号线82、另一第一复位控制信号线83、第一初始化电压信号线86和第三初始化电压信号线88可以位于第三导电层33中。
例如，如图4至图10所示，另一第一复位控制信号线83与第一复位晶体管T1的沟道区交叠，第一复位晶体管T1包括位于有源层两侧的顶栅和底栅；另一第二扫描控制信号线82与补偿晶体管T2的沟道区交叠，补偿晶体管T2包括位于有源层两侧的顶栅和底栅。
也就是说，在本公开的实施例中，第一复位晶体管T1和补偿晶体管T2可以具有双栅结构，即分别包括顶栅和底栅。
在本公开的实施例中，第一复位控制信号线83可以包括第一复位控制信号子线831和第二复位控制信号线832，将位于第二导电层32中的第一复位控制信号线描述为第一复位控制信号子线831，将位于第三导电层33中的第一复位控制信号线描述为第二复位控制信号子线832。第一复位控制信号子线831与第二半导体层22交叠的部分构成第一复位晶体管T1的底栅，第二复位控制信号子线832与第二半导体层22交叠的部分构成第一复位晶体管T1的顶栅。
第二扫描控制信号线82可以包括第一扫描控制信号子线821和第二扫描控制信号子线822，将位于第二导电层32中的第二扫描控制信号线描述为第一扫描控制信号子线821，将位于第三导电层33中的第二扫描控制信号线描述为第二扫描控制信号子线822。第一扫描控制信号子线821与第二半导体层22交叠的部分构成补偿晶体管T2的底栅，第二扫描控制信号子线822与第二半导体层22交叠的部分构成补偿晶体管T2的顶栅。
例如，第一复位晶体管T1和补偿晶体管T2可以为N型晶体管。驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第二复位晶体管T7以及第三复位晶体管T8可以为P型晶体管。
图12示出了位于第三导电层33远离衬底基板一侧的第四导电层34。例如，如图12所示，第二初始化电压信号线87可以位于第四导电层34中，所述显示基板还可以包括位于第四导电层34中的多个连接部，例如，所述多个连接部可以包括连接部341、连接部342、连接部343、第二电压信号线转接部344、连接部345、第一电源信号线转接部346、连接部347、连接部348和第一初始化电压连接部349。
图14示出了位于第四导电层34远离衬底基板一侧的第五导电层35。例如，如图14所示，数据线91和第一电源信号线92可以位于第五导电层35中。
结合参照图4至图14，连接部341可以用于电连接位于第五导电层35中的数据线91和数据写入晶体管T4的第一极，例如，位于第五导电层35中的数据线91通过位于第二绝缘层PLN中的过孔VH17与连接部341的一部分电连接，连接部341的另一部分通过位于第一绝缘层ILD中的过孔VH1与数据写入晶体管T4的第一极电连接。
连接部342可以用于电连接驱动晶体管T3的栅极与补偿晶体管T2的第二极，即形成节点N1。例如，连接部342的一部分(例如一端)通过位于第一绝缘层ILD中的过孔VH2与补偿晶体管T2的第二极电连接，连接部342的另一部分(例如另一端) 通过位于第一绝缘层ILD中的过孔VH4与驱动晶体管T3的栅极电连接。连接部343可以用于电连接补偿晶体管T2的第一极与第一发光控制晶体管T6的第一极，即形成节点N3。例如，连接部343的一部分(例如一端)通过位于第一绝缘层ILD中的过孔VH5与补偿晶体管T2的第一极电连接，连接部343的另一部分(例如另一端)通过位于第一绝缘层ILD中的过孔VH6与第一发光控制晶体管T6的第一极电连接。连接部345可以用于电连接第三复位晶体管T8的第二极与节点N2。例如，连接部345的一部分(例如一端)通过位于第一绝缘层ILD中的过孔VH13与第三复位晶体管T8的第二极电连接，连接部345的另一部分(例如另一端)通过位于第一绝缘层ILD中的过孔VH3与节点N2电连接。
连接部347可以用于电连接第三复位晶体管T8的第一极与第三初始化电压信号线88。例如，连接部347的一部分(例如一端)通过位于第一绝缘层ILD中的过孔VH11与第三初始化电压信号线88电连接，连接部347的另一部分(例如另一端)通过位于第一绝缘层ILD中的过孔VH16与第三复位晶体管T8的第一极的第一极电连接。
图19是根据本公开的示例性实施例的显示基板的局部放大图，其示意性示出了第一电源信号线的转接方式。参照图14和图19，数据线91和第一电源信号线92均沿第二方向Y延伸。例如，每一列子像素均具有各自的数据线91，相邻的两列子像素共用一个第一电源信号线92。如图14所示，共用的一个第一电源信号线92位于相邻的两列子像素的像素驱动电路之间。第一电源信号线92的主体部分沿第二方向Y延伸，第一电源信号线92在第一方向X上的宽度较大，为方便描述，第一电源信号线92的宽度变大的部分称为加宽部921(如图14所示)，加宽部921相对于第一电源信号线92的主体部分在第一方向X上延伸。
相邻的两列子像素共用一个位于第四导电层34中的第一电源信号线转接部346，第一电源信号线92的加宽部921分别通过位于第二绝缘层PLN中的过孔VH18与第一电源信号线转接部346的中间部分电连接。
位于第二导电层32中的第二电容电极Cst2还用作导电转接部，第一电源信号线转接部346的一端通过位于第一绝缘层ILD中的过孔VH7与一个子像素的像素驱动电路的导电转接部Cst2电连接，第一电源信号线转接部346的另一端通过位于第一绝缘层ILD中的过孔VH7与另一个子像素的像素驱动电路的导电转接部Cst2电连接。
每一个子像素的像素驱动电路还包括各自的第二电压信号线转接部344。在一个 子像素的像素驱动电路中，导电转接部Cst2的一部分通过过孔VH14与第二电压信号线转接部344的一端电连接，第二电压信号线转接部344的另一端通过过孔VH15与第二发光控制晶体管T5的第二极电连接。
通过这样的连接方式，可以将相邻的两列子像素共用的一个第一电源信号线92上的第一电源信号传输给相邻的两列子像素的第二发光控制晶体管T5。
在本公开的实施例中，第一电源信号线92在第一方向X上主要通过位于第二导电层中的导电转接部Cst2连通，在第二方向Y上主要通过位于第五导电层中的主体部分连通。横向和纵向的第一电源信号线92在两个子像素中间通过一个位于第二绝缘层PLN中的过孔VH18和两个位于第一绝缘层ILD中的过孔VH7连接。两个子像素共用一个位于第二绝缘层PLN中的过孔VH18。每个子像素的第一电源信号是通过纵向延伸的主体部分先转接到第一电源信号线转接部346，再通过第一电源信号线转接部346转接到横向延伸的第二导电层中的导电转接部Cst2，再通过导电转接部Cst2的另外一个位于第一绝缘层ILD中的过孔VH14再次转接到第二电压信号线转接部344，然后再通过第二电压信号线转接部344转接到第二发光控制晶体管T5。在本公开的实施例中，位于第二导电层32中的导电转接部Cst2既作为横向传递第一电源信号的导电转接部，同时起到子像素内第一电源信号转接跳线的作用。
连接部348的一部分通过过孔VH8与第一发光控制晶体管T6的第一极电连接，这样，可以将节点N4引出，以便于后续第一发光控制晶体管T6的第一极与发光元件120的阳极的电连接。
在本公开的一些实施例中，显示基板还包括位于第四导电层中的第一初始化电压连接部，第一初始化电压连接部的一端通过第五过孔与第一初始化电压信号线电连接，所述第一初始化电压连接部的另一端通过第六过孔分别与同一行的两个相邻子像素的第一复位晶体管的源极或漏极电连接。
示例性地，第一初始化电压连接部349的一部分(例如一端)通过过孔VH9与第一初始化电压信号线86电连接，第一初始化电压连接部349的另一部分(例如另一端)通过过孔VH10与第一复位晶体管T1的第一极电连接。第一初始化电压连接部349的另一部分通过第六过孔分别与同一行的两个相邻子像素的第一复位晶体管的第一极电连接，通过共用第一初始化电压连接部349，可以有效减少过孔面积占用，有利于提高像素密度。
第二初始化电压信号线87的一部分通过过孔VH12与第二复位晶体管T7的第一极电连接。
图15是根据本公开的示例性实施例的显示基板的局部平面图，其示意性示出了第一导电层和第三导电层的叠加图。图16是根据本公开的示例性实施例的显示基板的局部平面图，其示意性示出了第一导电层、第三导电层和第四导电层的叠加图。
在本公开的一些示例性实施例中，显示基板还包括位于第四导电层中的第二初始化电压连接部，第二初始化电压连接部的两端分别通过第七过孔与第三初始化电压信号线电连接，位于两端之间的中端通过第八过孔与同一行的两个相邻子像素的第三复位晶体管的源极或漏极电连接，第二初始化电压连接部在第一方向上位于第一初始化电压连接部和第二电压信号线转接部之间。
示例性地，结合参照图15和图16，发光控制信号线85在衬底基板10上的正投影和第三初始化电压信号线88在衬底基板10上的正投影至少部分重叠，第三初始化电压信号线在衬底基板上的正投影与第一复位控制信号线在衬底基板上的正投影不重叠，第三初始化电压信号线在衬底基板上的正投影与第二复位控制信号线在衬底基板上的正投影不重叠，第三初始化电压信号线在衬底基板上的正投影与扫描控制信号线在所述衬底基板上的正投影不重叠，发光控制信号线85在衬底基板10上的正投影和第三初始化电压信号线88在衬底基板10上的正投影至少部分重叠，例如，在一个子像素内，重叠部分的面积与初始化电压信号线在衬底基板上的正投影面积或控制信号线在所述衬底基板上的正投影面积的比值在80％至95％的范围，即发光控制信号线85在衬底基板10上的正投影和第三初始化电压信号线88在衬底基板10上的正投影大部分重叠，但是并不是完全重叠。沿第一方向X延伸的第三初始化电压信号线88通过过孔VH11与连接部347的一部分(例如一端)电连接，连接部347的另一部分(例如另一端)通过位于过孔VH16与第三复位晶体管T8的第一极的第一极电连接。第三复位晶体管T8的第二极又通过连接部345与节点N2电连接。
连接部347可以用于电连接第三复位晶体管T8的第一极与第三初始化电压信号线88。连接部347包括分别位于两个相邻子像素中的第一端，以及位于两个第一端之间的中端，连接部347的第一端分别通过过孔VH11与第三初始化电压信号线88电连接，连接部347的位于两个第一端之间的中端通过过孔VH16分别与相邻的子像素的第三复位晶体管T8的第一极电连接，以及在两个相邻子像素之间且在连接部347在第一方 向上位于第二电压信号线转接部344和第一初始化电压连接部349之间。第二复位控制信号线84上传输的第二复位控制信号PReset在阶段t1、t5为低电平，即第三复位晶体管T8在阶段t1、t5导通，在此阶段，第三初始化电压信号线88上传输的第三初始化电压信号对节点N2进行刷新。发光控制信号线85上传输的发光控制信号EM在阶段t1～t5均处于无效状态。也就是说，发光控制信号线85上传输的发光控制信号EM与第三初始化电压信号Vinit3在时序上是间隔开的。在本公开的实施例中，发光控制信号线85在衬底基板10上的正投影和第三初始化电压信号线88在衬底基板10上的正投影至少部分重叠，即采用叠层设计。在此叠层设计下，发光控制信号线85上传输的发光控制信号EM与第三初始化电压信号Vinit3工作时序错位，不同时工作，可以防止信号之间串扰。在发光控制信号线85上传输的发光控制信号EM与第三初始化电压信号Vinit3互不影响的状态下，对发光控制信号线85和第三初始化电压信号线88叠层设计，可以有效优化像素空间布局，有利于高分辨率的像素设计。
图17是根据本公开的示例性实施例的显示基板的局部平面图，其示意性示出了第一导电层和第三导电层的叠加图。图18是根据本公开的示例性实施例的显示基板的局部平面图，其示意性示出了第二半导体层、第一导电层、第二导电层、第三导电层和第四导电层的叠加图。
结合参照图17和图18，第二复位控制信号线84在衬底基板10上的正投影和第一初始化电压信号线86在衬底基板10上的正投影至少部分重叠。第一初始化电压信号线在衬底基板上的正投影与第一复位控制信号线在衬底基板上的正投影不重叠，第一初始化电压信号线在衬底基板上的正投影与扫描控制信号线在衬底基板上的正投影不重叠，第一初始化电压信号线在所述衬底基板上的正投影与发光控制信号线在所述衬底基板上的正投影不重叠。第二复位控制信号线84在衬底基板10上的正投影和第一初始化电压信号线86在衬底基板10上的正投影至少部分重叠，例如，在一个子像素内，重叠部分的面积与第一初始化电压信号线在衬底基板上的正投影面积的比值在60％至100％的范围，或者重叠部分的面积与第二复位控制信号线在衬底基板上的正投影面积的比值在60％至100％的范围。在一些可选的实施例中，重叠部分的面积与第二复位控制信号线在衬底基板上的正投影面积的比值可以是在80％至95％的范围内，即第二复位控制信号线84在衬底基板10上的正投影和第一初始化电压信号线86在衬底基板10上的正投影大部分重叠，但是并不是完全重叠。第一初始化电压信号线86 通过过孔VH9与第一初始化电压连接部349的一部分(例如一端)电连接，第一初始化电压连接部349的另一部分(例如另一端)通过过孔VH10与第一复位晶体管T1的第一极电连接。第一复位晶体管T1的第二极又与补偿晶体管T2的第一极电连接，驱动晶体管T3的栅极通过连接部342也与补偿晶体管T2的第一极电连接，从而形成节点N1。在可选的一些实施例中，第二复位控制信号线在衬底基板上的正投影和第一初始化电压信号线在衬底基板上的正投影大部分重叠，例如重叠部分的面积与第二复位控制信号线在衬底基板上的正投影面积的比值或第一初始化电压信号线在衬底基板上的正投影面积的比值为60％，也可以是完全重叠，例如比值为100％。在一些实施例中，第二初始化电压信号线在衬底基板上的正投影可以与扫描控制信号线在衬底基板上的正投影部分重叠，此外第二初始化电压信号线在衬底基板上的正投影也可以与第一复位控制信号线在衬底基板上的正投影部分重叠。
在时序图中，第二复位控制信号线84上传输的第二复位控制信号PReset在阶段t1、t5处于有效状态，而在阶段t1、t5，第一复位控制信号线83上传输的第一复位控制信号NReset均为低电平，即第一复位晶体管T1处于关闭状态，此时，第一初始化电压信号Vinit1不会通过第一复位晶体管T1传输给节点N1。实际上，第一复位控制信号线83上传输的第一复位控制信号NReset在阶段t2、t3为高电平，即第一复位晶体管T1在阶段t2、t3导通。也就是说，第二复位控制信号线84上传输的第二复位控制信号PReset与第一初始化电压信号Vinit1在时序上是间隔开的。在本公开的实施例中，第一扫描控制信号线81在衬底基板10上的正投影和第一初始化电压信号线86在衬底基板10上的正投影至少部分重叠，即采用叠层设计。第一初始化电压信号线在衬底基板上的正投影与第一复位控制信号线在衬底基板上的正投影不重叠，第一初始化电压信号线在衬底基板上的正投影与扫描控制信号线在衬底基板上的正投影不重叠，第一初始化电压信号线在衬底基板上的正投影与发光控制信号线在衬底基板上的正投影不重叠。在此叠层设计下，第二复位控制信号线84上传输的第二复位控制信号PReset与第一初始化电压信号Vinit1工作时序错位，不同时工作，可以防止信号之间串扰。在第二复位控制信号线84上传输的第二复位控制信号PReset与第一初始化电压信号Vinit1互不影响的状态下，对第一扫描控制信号线81和第一初始化电压信号线86叠层设计，可以有效优化像素空间布局，有利于高分辨率的像素设计。第一扫描控制信号线81在衬底基板10上的正投影和第一初始化电压信号线86在衬底基板10上的正 投影至少部分重叠，例如，重叠部分的面积与第一扫描控制信号线81在衬底基板10上的正投影面积的比值为80％至95％的范围，或者重叠部分的面积与第一初始化电压信号线86在衬底基板10上的正投影面积的比值为80％至95％的范围。
图20是根据本公开的示例性实施例的显示基板的局部放大图，其示意性示出了叠层设计的信号线的错位设计。
如图20所示，在本公开的实施例中，所述第一初始化电压信号线86、所述第二初始化电压信号线87和所述第三初始化电压信号线88中的每一个的至少一部分在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影不重叠。即，在叠层设计的前提下，位于第三导电层33中的第一初始化电压信号线86的一部分与下方第一导电层31中的控制信号线(例如第二复位控制信号线84或第三复位控制信号线84)是错位设计的，例如图20中的位于第一初始电压信号线86附近处的矩形虚线框和椭圆虚线框标注的区域部分。第三初始化电压信号线88的一部分与下方的位于第一导电层31中的控制信号线(例如发光控制信号线85)是错位设计的，例如图20中位于第三初始电压信号线88附近处的矩形虚线框标注的区域部分。位于第四导电层34中的第二初始化电压信号线87与下方的位于第一导电层31中的控制信号线(例如扫描控制信号线81)是错位设计的。
如图20所示，箭头表示相邻的信号线与过孔之间的距离，应该理解，相邻的信号线与过孔之间的距离需要满足规定的工艺规格。在满足该规定的工艺规格的前提下，将初始化电压信号线与下方的控制信号线进行部分错位设计，可以减小两个信号线之间的交叠面积，从而能够降低信号线上的负载。
图21是根据本公开的另一些示例性实施例的用于驱动像素驱动电路的信号的时序图。
在如图2和图21所示的示例性实施例中，8T1C电路中包含8个薄膜晶体管(T1-T8)，其中T2是N型薄膜晶体管NMOS，采用氧化物晶体管；T1、T3-T8为P型的薄膜晶体管PMOS，采用低温多晶硅晶体管。
结合参照图2和图21，在时序图中，第一复位控制信号线83上传输的是第一复位控制信号PReseta，第二复位控制信号线或第三复位控制信号线84上传输的是第二复位控制信号或第三复位控制信号PResetb，发光控制信号线85上传输的是发光控制信号EM，补偿控制信号线82上传输的是补偿控制信号NGate，扫描控制信号线81 上传输的是扫描控制信号PGate。如图21所示，第二复位控制信号线或第三复位控制信号线84上传输的第二复位控制信号或第三复位控制信号PResetb在阶段t1、t3、t6处于有效状态，而在阶段t1、t3、t6，第一复位控制信号线83上传输的第一复位控制信号Preseta处于关闭状态，此时，第一初始化电压信号Vinit1不会通过第一复位晶体管T1传输该节点N1。根据图21的时序图可知，在阶段t2、t4，第一复位控制信号线83上传输的第一复位控制信号PReseta处于有效状态，即第一复位晶体管T1在阶段t2、t4导通，也就是说，第二复位控制信号线84上传输的第二复位控制信号PResetb与第一初始化电压信号Vinit1在时序上是间隔开的。从而可以实现将第二复位控制信号线或第三控制信号线84与第一初始化电压信号线86进行重叠布置设置，使得各个信号线上的信号在不产生干扰的情况下，实现显示基板不同膜层的层叠设置，提高各个信号线的空间利用率，实现在满足现有工艺规格的前提下，设计布局更高PPI的像素，即实现高PPI像素的设计。
如图21所示，在时序图中，第一扫描控制信号线81上传输的第一扫描控制信号PGate在阶段t5处于有效状态，而在阶段t5，第二复位控制信号线或第三复位控制信号线84上传输的第二复位控制信号或第三复位控制信号PResetb均为高电平，即第二复位晶体管T7和第三复位晶体管T8均处于关闭状态，此时，第二初始化电压信号Vinit2不会通过第二复位晶体管T7传输给节点N4，第三初始化电压信号Vinit3不会通过第三复位晶体管T8传输给节点N2。实际上，第二复位控制信号线84上传输的第二复位控制信号PResetb在阶段t1、t3、t6为低电平，即第二复位晶体管T7和第三复位晶体管T8在阶段t1、t3、t6导通。根据时序图，第一复位控制信号线83上传输的第一复位控制信号Preseta与第二复位控制信号或第三复位控制信号PResetb在t1至t6阶段的导通状态均不同，例如，第一复位控制信号PReseta在t2、t4时刻处于有效状态，而在其他时刻处于关闭状态，第二复位控制信号PResetb在t1、t3、t6时刻处于有效状态，即在t1、t3、t6控制第二复位晶体管T7或第三复位晶体管T8导通，第一复位控制信号线83上传输的第一复位控制信号PReseta与第二初始化电压信号Vinit2在时序上是间隔开的。从而可以实现将第一复位控制信号线与第二初始化电压信号线进行重叠布置，使得各个信号线上的信号在不产生干扰的情况下，实现显示基板不同膜层的层叠设置，提高各个信号线的空间利用率，实现在满足现有工艺规格的前提下，设计布局更高PPI的像素，即实现高PPI像素的设计。
在时序图中，发光控制信号线85上传输的发光控制信号EM在阶段t1～t6均处于无效状态，第二复位控制信号线虎第三复位控制信号线84上传输的第二复位控制信号或第三复位控制信号PResetb在阶段t1、t3、t6为低电平，即第二复位晶体管T7和第三复位晶体管T8在阶段t1、t3、t6导通。也就是说，发光控制信号线85上传输的发光控制信号EM与第三初始化电压信号Vinit3在时序上是间隔开的。
在本公开的实施例中，可以将传输这些在时序上间隔开的信号的信号线进行叠层设计，例如，由于第二复位控制信号线或第三复位控制信号线84上传输的第二复位控制信号PResetb与第一初始化电压信号Vinit1在时序上是间隔开的，所以可以将第二复位控制信号线或第三复位控制信号线84与第一初始化电压信号线86进行叠层设计；
由于第一复位控制信号线83上传输的第一扫描控制信号PReseta与第二初始化电压信号Vinit2在时序上是间隔开的，所以，可以将第一复位控制信号线83与第二初始化电压信号线87进行叠层设计；由于发光控制信号线85上传输的发光控制信号EM与第二初始电压信号或第三初始化电压信号Vinit3在时序上是间隔开的，所以，可以将发光控制信号线85与第三初始化电压信号线88进行叠层设计。这样，由于叠层设计的各个信号线上传输的信号在时序上是错开的，所以，不会对信号产生不利的影响，同时，可以有效地利用显示基板的空间进行布局，有利于实现高PPI的显示面板。
在本公开的一些可选实施例中，像素驱动电路包括第一复位晶体管，第一复位晶体管包括栅极、源极和漏极，初始化电压信号线包括第一初始化电压信号线，第一初始化电压信号线与第一复位晶体管的源极或漏极电连接，第一初始化电压信号线在衬底基板上的正投影与控制信号线在衬底基板上的正投影至少部分重叠，控制信号线包括复位控制信号线。例如，像素驱动电路中仅有第一初始化电压信号线在衬底基板上的正投影与控制信号线在衬底基板上的正投影至少部分重叠，其他走线部不存在重叠的情况，该示例中的控制信号线例如可以包括用于控制第二复位晶体管栅极的第二复位控制信号线。
在本公开的一些可选实施例中，像素驱动电路包括第二复位晶体管，第二复位晶体管包括栅极、源极和漏极，初始化电压信号线包括第二初始化电压信号线，第二初始化电压信号线与第二复位晶体管的源极或漏极电连接，第二初始化电压信号线在衬底基板上的正投影与控制信号线在衬底基板上的正投影至少部分重叠，控制信号线包括扫描控制信号线。例如，像素驱动电路中仅有第二初始化电压信号线在衬底基板上 的正投影与控制信号线在衬底基板上的正投影至少部分重叠，其他走线部不存在重叠的情况，此处的控制信号线例如可以包括用于控制数据写入晶体管栅极的第一扫描控制信号线。
在本公开的一些可选实施例中，像素驱动电路包括第三复位晶体管，第三复位晶体管包括栅极、源极和漏极，初始化电压信号线包括第三初始化电压信号线，第三初始化电压信号线与第三复位晶体管的源极或漏极电连接，第三初始化电压信号线在衬底基板上的正投影与控制信号线在衬底基板上的正投影至少部分重叠，控制信号线包括发光控制信号线。例如，像素驱动电路中仅有第三初始化电压信号线在衬底基板上的正投影与控制信号线在衬底基板上的正投影至少部分重叠，其他走线部不存在重叠的情况，此处的控制信号线例如可以包括用于控制第一发光控制晶体管和/或第二发光控制晶体管晶体管栅极的发光控制信号线。
图22是根据本公开的另一些示例性实施例的显示基板的局部平面图，其示意性示出了2个相邻的子像素的像素驱动电路。图23至图32分别是根据本公开的图22的实施例的显示基板的局部平面图，其中，图23为所述显示基板的遮光层的局部平面图，图24为所述显示基板的第一半导体层的局部平面图，图25是所述显示基板的第一导电层的局部平面图，图26为所述显示基板的第二导电层的局部平面图，图27为所述显示基板的第二半导体层的局部平面图，图28是所述显示基板的第三导电层的局部平面图，图29是所述显示基板的第一绝缘层的局部平面图，其示意性示出了位于该第一绝缘层中的多个过孔，图30是所述显示基板的第四导电层的局部平面图，图31是所述显示基板的第二绝缘层的局部平面图，其示意性示出了位于该第二绝缘层中的多个过孔，图32是所述显示基板的第五导电层的局部平面图。
结合参照图21至图22以及图50，所述显示基板可以包括衬底基板10，设置于衬底基板10上的遮光层LS，设置于遮光层LS远离衬底基板一侧的第一半导体层21，设置于第一半导体层21远离衬底基板一侧的第一导电层31，设置于第一导电层31远离衬底基板一侧的第二导电层32，设置于第二导电层32远离衬底基板一侧的第二半导体层22，设置于第二半导体层22远离衬底基板一侧的第三导电层33，设置于第三导电层33远离衬底基板一侧的第四导电层34，设置于第四导电层34远离衬底基板一侧的第五导电层35。
图24示出了第一半导体层21。例如，如图24所示，第一半导体层21可用于制 作上述的第一复位晶体管T1、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第二复位晶体管T7以及第三复位晶体管T8的有源层，以用于形成上述晶体管的沟道区。第一半导体层21可以包括各子像素的上述晶体管的有源区图案(沟道区)和掺杂区图案(源漏区)，且同一像素驱动电路中的上述晶体管的有源区图案和掺杂区图案一体设置。
例如，第一半导体层21可以包括一体形成的低温多晶硅层，源极区域和漏极区域可以通过掺杂等进行导体化实现各结构的电连接。例如，上述的源极区域和漏极区域可为掺杂有p型杂质的区域。
图25示出了位于第一半导体层21远离衬底基板一侧的第一导电层31。例如，如图25所示，第一扫描控制信号线81、存储电容器Cst的第一电容电极Cst1、发光控制信号线85、第二复位控制信号线84、第一复位控制信号线83可以位于第一导电层31中。例如，第一导电层31可以包括第一复位晶体管T1、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第二复位晶体管T7以及第三复位晶体管T8的栅极。
需要说明的是，图25中的各虚线矩形框示出了第一半导体层21与第一导电层31交叠的各个部分，即沟道区。作为各个晶体管的沟道区，在每个沟道区两侧的有源半导体层通过离子掺杂等工艺导体化作为各个晶体管的第一极和第二极。晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在物理结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管，除作为控制极的栅极，直接描述了其中一极为第一极，另一极为第二极，所以本公开的实施例中全部或部分晶体管的第一极和第二极根据需要是可以互换的。
例如，结合参照图22、图24和图25，第一复位晶体管T1的栅极可以为第一复位控制信号线83与第一半导体层21交叠的部分。数据写入晶体管T4的栅极可以为第一扫描控制信号线81与第一半导体层21交叠的部分。第一发光控制晶体管T6的栅极可以为发光控制信号线85与第一半导体层21交叠的第一部分，第二发光控制晶体管T5的栅极可以为发光控制信号线85与第一半导体层21交叠的第二部分。第三复位晶体管T8的栅极为第二复位控制信号线84与第一半导体层21交叠的第一部分，第二复位晶体管T7的栅极为第二复位控制信号线84与第一半导体层21交叠的第二部分。
图26示出了第一导电层31远离衬底基板一侧的第二导电层32。例如，如图26 所示，第二扫描控制信号线82、存储电容器Cst的第二电容电极Cst2以及补偿控制信号线82可以位于第二导电层32中。
图27示出了第二导电层32远离衬底基板一侧的第二半导体层22。例如，如图27所示，第二半导体层22包括补偿晶体管T2的沟道区。例如，补偿晶体管T2中的有源层采用氧化物半导体的情况下，因用氧化物半导体的晶体管具备磁滞特性好、漏电流低的特点，故可以采用氧化物半导体的晶体管代替晶体管中的低温多晶硅材料，形成低温多晶硅氧化物的(LTPO)像素驱动电路，实现低漏电，利于提高晶体管的栅极电压的稳定性。
例如，如图22、图26和图27所示，补偿晶体管T2的栅极可以为第二扫描控制信号线82与第二半导体层22交叠的部分。具体地，为第一扫描控制信号子线821和第二扫描控制信号子线822与第二半导体层22交叠的部分。
图28示出了第二半导体层22远离衬底基板一侧的第三导电层33。例如，如图28所示，另一第二扫描控制信号线82、第一初始化电压信号线86、第二初始化电压信号线87和第三初始化电压信号线88可以位于第三导电层33中。
例如，如图22至图28所示，另一第二扫描控制信号线82与补偿晶体管T2的沟道区交叠，补偿晶体管T2包括位于有源层两侧的顶栅和底栅。
也就是说，在本公开的实施例中，补偿晶体管T2可以具有双栅结构，即分别包括顶栅和底栅。
在本公开的实施例中，第二扫描控制信号线82可以包括第一扫描控制信号子线821和第二扫描控制信号子线822，将位于第二导电层32中的第二扫描控制信号线描述为第一扫描控制信号子线821，将位于第三导电层33中的第二扫描控制信号线描述为第二扫描控制信号子线822。第一扫描控制信号子线821与第二半导体层22交叠的部分构成补偿晶体管T2的底栅，第二扫描控制信号子线822与第二半导体层22交叠的部分构成补偿晶体管T2的顶栅。
例如，补偿晶体管T2可以为N型晶体管。第一复位晶体管T1、驱动晶体管T3、数据写入晶体管T4、第二发光控制晶体管T5、第一发光控制晶体管T6、第二复位晶体管T7以及第三复位晶体管T8可以为P型晶体管。
图30示出了位于第三导电层33远离衬底基板一侧的第四导电层34。例如，如图30所示，显示基板还可以包括位于第四导电层34中的多个连接部，例如，所述多个 连接部可以包括连接部341、连接部342、连接部343’、第二电压信号线转接部344、连接部345、第一电源信号线转接部346、连接部347、连接部348、第一初始化电压连接部349以及连接部350。
图32示出了位于第四导电层34远离衬底基板一侧的第五导电层35。例如，如图32所示，数据线91和第一电源信号线92可以位于第五导电层35中。
结合参照图22至图32，连接部341、连接部342、第二电压信号线转接部344、连接部345、第一电源信号线转接部346、连接部347、连接部348、第一初始化电压连接部349与图12所示的连接部的布局相同，在此不再赘述。
本实施例的连接部343’与连接部350与上文所示的其他连接部存在一定区别，具体地，连接部343’可以用于电连接补偿晶体管T2的第一极与第一发光控制晶体管T6的第一极，即形成节点N3。例如，连接部343’的一部分(例如中端)通过位于第一绝缘层ILD中的过孔VH5与补偿晶体管T2的第一极电连接，连接部343’的另一部分(例如一端)通过位于第一绝缘层ILD中的过孔VH6与第一发光控制晶体管T6的第一极电连接，连接部343’的又一部分(例如，另一端)通过第一绝缘层ILD中的过孔VH20与第一复位晶体管的第二极电连接。
连接部350可以电连接第二初始化电压信号线87以及第二复位晶体管T7的第一极，具体地，连接部350通过过孔VH19与第二初始化电压信号线87点连接，并通过过孔VH12与第二复位晶体管T7的第一极电连接。
图33和图35是图23所示的显示基板的局部平面图，其示意性示出了第一导电层和第三导电层的叠加图。图34和图36是图23所示的显示基板的局部平面图，其示意性示出了第一导电层、第三导电层和第四导电层的叠加图。
图33示意性示出了第一初始化电压信号线86与第二复位控制信号线或第三复位控制信号线84的层叠结构设置，图34示意性示出了第一初始化电压信号线的电连接方式，其示意性示出了第一导电层、第二半导体层、第三导电层和第四导电层的叠加图。
参照图22和图34，第一初始化电压信号线86在衬底基板10上的正投影与第二复位控制信号线或第三复位控制信号线84在衬底基板上的正投影至少部分重叠。沿第一方向X延伸的第一初始化电压信号线86通过过孔VH9与第一初始化电压连接部349的一部分电连接，第一初始化电压连接部349的另一部分(例如另一端)通过过孔VH10 与第一复位晶体管T1的第一极电连接，第一复位晶体管的第二极通过过孔VH20与连接部343’电连接，从而使第一初始化电压信号Vinit1对N1节点进行刷新。
在本公开的实施例中，结合图21，例如，在t2和t4时刻，NGate处于高电平，T2导通，并且，PReseta处于低电平，也开启，即在t2和t4时刻，第一复位晶体管T1和补偿控制晶体管T2导通，使得第一初始化电压信号Vinit1可以对N1节点进行刷新。并且，在t2和t4时刻，PResetb处于高电平，即处于关闭状态。通过将第一初始化电压信号线86与第二复位控制信号线或第三复位控制信号线84层叠设置，同时由于第一初始化电压信号线86与第二复位控制信号线或第三复位控制信号线84上的信号在时序上间隔开，不同时工作，可以防止信号之间的串扰。
如图35和图36所示，第二初始化电压信号线87在衬底基板10上的正投影与第一复位控制信号线83在衬底基板上的正投影至少部分重叠。沿第一方向X延伸的第二初始化电压信号线87通过过孔VH19与连接部350的一部分电连接，连接部350的另一部分(例如另一端)通过过孔VH20与N4节点电连接，从而使第二初始化电压信号Vinit2对N4节点进行刷新。通过将第二初始化电压信号线87与第一复位控制信号83层叠设置，同时由于第二初始化电压信号线87与第一复位控制信号线上的信号在时序上间隔开(信号PResetb和信号PReseta间隔开)，不同时工作，可以防止信号之间的串扰。
图37是本公开的一些示例性实施例的显示基板的局部放大图，其示意性示出了8个子像素的像素驱动电路。图38至图47是图37所示的显示基板的各个膜层的局部平面结构示意图。
图37是示意性示出了8个子像素的像素驱动电路，包括沿第一方向X排列的两行四个子像素以及沿第二方向Y排列的四列子像素，一共八个子像素。图38至图47分别是根据本公开的图37的实施例的显示基板的局部平面图，其中，图38为所述显示基板的遮光层LS的局部平面图，图39为所述显示基板的第一半导体层21的局部平面图，图40是所述显示基板的第一导电层31的局部平面图，图41为所述显示基板的第二导电层32的局部平面图，图42为所述显示基板的第二半导体层22的局部平面图，图43是所述显示基板的第三导电层33的局部平面图，图44是所述显示基板的第一绝缘层ILD的局部平面图，其示意性示出了位于该第一绝缘层中的多个过孔，图45是所述显示基板的第四导电层34的局部平面图，图46是所述显示基板的第二绝缘层 PLN的局部平面图，其示意性示出了位于该第二绝缘层中的多个过孔，图47是所述显示基板的第五导电层35的局部平面图。
图48是本公开示例性的一些示例性实施例的显示基板的镂空区域的局部平面结构示意图。图49是本公开示例性的一些示例性实施例的显示基板的相邻的镂空区域之间的局部平面结构示意图。
如图37和图48、图49所示，显示基板还包括至少一个镂空区域M，所述至少一个镂空区域M包括第一侧S1、第二侧S2、第三侧S3和第四侧S4，所述第一侧S1和所述第二侧S2为所述至少一个镂空区域在第一方向X上相对的两侧，所述第三侧S3和所述第四侧S4为所述至少一个镂空区域在第二方向Y上相对的两侧，
所述显示基板包括设置在所述衬底基板上的多个数据线，所述多个数据线分别沿第二方向Y延伸，所述多个数据线包括邻近所述至少一个镂空区域的第一数据线W1和第二数据线W2，所述第一数据线W1和所述第二数据线W2在第一方向X上分别位于所述至少一个镂空区域的第一侧S1和第二侧S2，所述第一复位控制信号线83和所述扫描控制信号线81邻近所述至少一个镂空区域，在第二方向Y上分别位于所述至少一个镂空区域的第三侧S3和第四侧S4，所述第一复位控制信号线83和所述扫描控制信号线81分别与所述第一数据线W1和所述第二数据线W2交叉，以包围形成所述至少一个镂空区域M。
示例性地，如图49所示，在镂空区域M的第一侧S1设置有沿第二方向Y延伸的第一数据线W1，在镂空区域M的第二侧S2设置有沿第二方向Y延伸的第二数据线W2。
在本公开的另一些示例性实施例中，所述显示基板包括设置在所述衬底基板上的多个数据线，所述多个数据线分别沿第二方向延伸，所述多个数据线包括邻近所述至少一个镂空区域的第一数据线和第二数据线，所述第一数据线和所述第二数据线在第一方向上分别位于所述至少一个镂空区域的第一侧和第二侧，所述扫描控制信号线81和所述补偿控制信号线82邻近所述至少一个镂空区域，在第二方向上分别位于所述至少一个镂空区域的第三侧和第四侧，所述扫描控制信号线81和所述补偿控制信号线82分别与所述第一数据线W1和所述第二数据线W2交叉，以包围形成所述至少一个镂空区域M。在本实施例中，镂空区域M位于扫描控制信号线81和补偿控制信号线82之间。
如图49所示，第一数据线W1和第二数据线W2中的每一个包括主体部分和弯折部分，第一数据线W1的弯折部分相对于第一数据线的主体部分朝远离至少一个镂空区域M的方向弯折，第二数据线的弯折部分相对于第二数据线的主体部分朝远离至少一个镂空区域的方向弯折，第一数据线的弯折部分和第二数据线的弯折部分朝相反的方向弯折。例如，第一数据线W1的弯折部分W11与第二数据线W2的弯折部分W21之间的间距大于第一数据线W1的主体部分W12与第二数据线W2的主体部分W22之间的间距。
第一复位控制信号线83和扫描控制信号线81中的每一个包括主体部分和弯折部分，第一复位控制信号线的弯折部分8311相对于第一复位控制信号线的主体部分8312朝远离至少一个镂空区域M的方向弯折，扫描控制信号线81的弯折部分8111相对于扫描控制信号线的主体部分8112朝远离至少一个镂空区域M的方向弯折，第一复位控制信号线的弯折部分8311和扫描控制信号线的弯折部分8111朝相反的方向弯折。
如图49所示，第一数据线W1的弯折部分W11和第二数据线W2的弯折部分W21与第一复位控制信号线的弯折部分8311和扫描控制信号线的弯折部分8111围成镂空区域M。
如图49所示，在本实施例中，第二半导体层22与第一导体层31中的扫描控制信号线81存在交叠部分，如图49的虚线框所示的区域，在虚线框所示的区域内，通过将虚线框内扫描控制信号线81在衬底基板上的正投影设置为大于虚线框内第二半导体层22在衬底基板上的正投影，从而显示基板内的所有像素的第二半导体层22与第一导体层31中的扫描信号线81之间产生交叠电容大小一致，从而在不影响显示画质的情况下，有效提高镂空区域的面积。
在本公开的另一些示例性实施例中，扫描控制信号线和补偿控制信号线中的每一个包括主体部分和弯折部分，扫描控制信号线的弯折部分相对于扫描控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，补偿控制信号线的弯折部分相对于补偿控制信号线的主体部分朝远离至少一个镂空区域的方向弯折，扫描控制信号线的弯折部分和补偿控制信号线的弯折部分朝相反的方向弯折。在本实施例中，第一数据线的弯折部分和第二数据线的弯折部分与扫描控制信号线的弯折部分和补偿控制信号线的弯折部分围成镂空区域M。
在本公开的一些示例性实施例中，显示基板包括位于第四导电层34中的数据信号 转接部，即上文所述的连接部，数据信号转接部的一部分通过第五过孔与第一数据线或第二数据线电连接，在第一区域中，数据信号转接部在衬底基板上的正投影与第一复位控制信号子线831在衬底基板上的正投影至少部分重叠，数据信号转接部在衬底基板上的正投影与第二复位控制信号子线832在衬底基板上的正投影至少部分重叠，通过将数据信号转接部在衬底基板上的正投影与第一复位控制信号子线或第二复位控制信号子线在衬底基板上的正投影至少部分重叠，从而保证过孔的面积，保证信号的传输。第一复位控制信号子线831在衬底基板上的正投影与第二复位控制信号子线832在衬底基板上的正投影至少部分不重叠，在保证不影响复位控制信号的稳定性的情况下，提高显示基板的空间利用率。
本公开的至少一些实施例还提供一种显示装置。该显示装置可以包括如上所述的显示基板。所述显示装置包括显示区域AA和非显示区域NA，非显示区域NA具有较小的宽度以及较高的像素密度，从而实现了窄边框以及高密度PPI的显示装置。
所述显示装置可以包括任何具有显示功能的设备或产品。例如，所述显示装置可以是智能电话、移动电话、电子书阅读器、台式电脑(PC)、膝上型PC、上网本PC、个人数字助理(PDA)、便携式多媒体播放器(PMP)、数字音频播放器、移动医疗设备、相机、可穿戴设备(例如头戴式设备、电子服饰、电子手环、电子项链、电子配饰、电子纹身、或智能手表)、电视机等。
应该理解，根据本公开实施例的显示装置具有上述显示基板的所有特点和优点，具体可以参见上文的描述，在此不再赘述。
在本文中，术语“基本上”、“大约”、“近似”、“大致”和其它类似的术语用作近似的术语而不是用作程度的术语，并且它们意图解释将由本领域普通技术人员认识到的测量值或计算值的固有偏差。考虑到工艺波动、测量问题和与特定量的测量有关的误差(即，测量系统的局限性)等因素，如这里所使用的“大约”或“近似”包括所陈述的值，并表示对于本领域普通技术人员所确定的特定值在可接受的偏差范围内。例如，“大约”可以表示在一个或更多个标准偏差内，或者在所陈述的值的±30％、±20％、±10％、±5％内。
虽然本公开的总体技术构思的一些实施例已被显示和说明，本领域普通技术人员将理解，在不背离所述总体技术构思的原则和精神的情况下，可对这些实施例做出改变，本公开的范围以权利要求和它们的等同物限定。

Claims (25)

  1. 一种显示基板，其中，包括：
    衬底基板；
    设置在所述衬底基板上的多个子像素，所述多个子像素沿第一方向和第二方向布置，至少一个所述子像素包括发光元件；
    设置在所述衬底基板上的多个像素驱动电路，所述多个像素驱动电路沿第一方向和第二方向布置，所述多个像素驱动电路用于分别驱动所述多个子像素的发光元件，至少一个所述像素驱动电路包括至少两个晶体管；
    设置于所述衬底基板上的初始化电压信号线，所述初始化电压信号线包括沿第一方向延伸的部分，所述初始化电压信号线用于给所述像素驱动电路提供初始化电压信号；
    设置于所述衬底基板上的控制信号线，所述控制信号线包括沿第一方向延伸的部分，所述控制信号线用于给所述像素驱动电路提供控制信号，以控制所述像素驱动电路的至少两个晶体管导通；
    其中，在用于驱动一行子像素的像素驱动电路的一帧内，所述控制信号线上的控制信号在至少一个第一时间段内控制所述像素驱动电路的至少两个晶体管导通，所述初始化电压信号线上的初始化电压信号在第二时间段内提供给所述像素驱动电路，所述第一时间段和所述第二时间段在时序上间隔设置；以及
    所述初始化电压信号线和所述控制信号线位于不同的导电层中，所述初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，
    在一个子像素内，重叠部分的面积与所述控制信号线在所述衬底基板上的正投影面积的比值在60％至100％的范围。
  2. 根据权利要求1所述的显示基板，其中，所述像素驱动电路包括第一复位晶体管，所述第一复位晶体管包括栅极、源极和漏极，
    所述初始化电压信号线包括第一初始化电压信号线，所述第一初始化电压信号线与所述第一复位晶体管的源极或漏极电连接，
    所述第一初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，
    所述控制信号线包括复位控制信号线。
  3. 根据权利要求1所述的显示基板，其中，所述像素驱动电路包括第二复位晶体管，所述第二复位晶体管包括栅极、源极和漏极，
    所述初始化电压信号线包括第二初始化电压信号线，所述第二初始化电压信号线与所述第二复位晶体管的源极或漏极电连接，
    所述第二初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，所述控制信号线包括扫描控制信号线。
  4. 根据权利要求1所述的显示基板，其中，所述像素驱动电路包括第三复位晶体管，所述第三复位晶体管包括栅极、源极和漏极，
    所述初始化电压信号线包括第三初始化电压信号线，所述第三初始化电压信号线与所述第三复位晶体管的源极或漏极电连接，
    所述第三初始化电压信号线在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，所述控制信号线包括发光控制信号线。
  5. 根据权利要求1所述的显示基板，其中，所述像素驱动电路包括第一复位晶体管、第二复位晶体管和第三复位晶体管，所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管中的每一个均包括栅极、源极和漏极，
    所述初始化电压信号线包括第一初始化电压信号线，所述第一初始化电压信号线与所述第一复位晶体管的源极或漏极电连接，
    所述初始化电压信号线包括第二初始化电压信号线，所述第一初始化电压信号线与所述第二复位晶体管的源极或漏极电连接，
    所述初始化电压信号线包括第三初始化电压信号线，所述第一初始化电压信号线与所述第三复位晶体管的源极或漏极电连接，
    所述第一初始化电压信号线、所述第二初始化电压信号线和所述第三初始化电压信号线中的至少一个在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠。
  6. 根据权利要求5所述的显示基板，其中，所述像素驱动电路还包括数据写入晶体管和发光控制晶体管，所述数据写入晶体管和发光控制晶体管包括栅极、源极和漏极，所述控制信号线包括第一复位控制信号线、第二复位控制信号线、扫描控制信号线和发光控制信号线，所述第一复位控制信号线与所述第一复位晶体管的栅极电连接，所述第二复位控制信号线与所述第二复位晶体管的栅极或所述第三复位晶体管的栅极电连接，所述扫描控制信号线与所述数据写入晶体管的栅极电连接，所述发光控制信号线与所述发光控制晶体管的栅极电连接，
    所述第一初始化电压信号线在所述衬底基板上的正投影和所述第二复位控制信号线在所述衬底基板上的正投影至少部分重叠，
    所述第一初始化电压信号线在所述衬底基板上的正投影与所述第一复位控制信号线在所述衬底基板上的正投影不重叠，
    所述第一初始化电压信号线在所述衬底基板上的正投影与所述扫描控制信号线在所述衬底基板上的正投影不重叠，
    所述第一初始化电压信号线在所述衬底基板上的正投影与所述发光控制信号线在所述衬底基板上的正投影不重叠。
  7. 根据权利要求6所述的显示基板，其中，
    所述第二初始化电压信号线在所述衬底基板上的正投影与所述扫描控制信号线在所述衬底基板上的正投影至少部分重叠，
    所述第二初始化电压信号线在所述衬底基板上的正投影与所述第二复位控制信号线在所述衬底基板上的正投影不重叠，
    所述第二初始化电压信号线在所述衬底基板上的正投影与所述发光控制信号线在所述衬底基板上的正投影不重叠。
  8. 根据权利要求7所述的显示基板，其中，
    所述第三初始化电压信号线在所述衬底基板上的正投影与所述发光控制信号线在所述衬底基板上的正投影至少部分重叠，
    所述第三初始化电压信号线在所述衬底基板上的正投影与所述第一复位控制信号线在所述衬底基板上的正投影不重叠，
    所述第三初始化电压信号线在所述衬底基板上的正投影与所述第二复位控制信号线在所述衬底基板上的正投影不重叠，
    所述第三初始化电压信号线在所述衬底基板上的正投影与所述扫描控制信号线在所述衬底基板上的正投影不重叠。
  9. 根据权利要求8所述的显示基板，其中，所述显示基板包括：
    设置在所述衬底基板上的第一半导体层；
    设置在所述第一半导体层远离所述衬底基板一侧的第一导电层；
    设置在所述第一导电层远离所述衬底基板一侧的第二导电层；
    设置在所述第二导电层远离所述衬底基板一侧的第二半导体层；
    设置在所述第二半导体层远离所述衬底基板一侧的第三导电层；
    设置在所述第三导电层远离所述衬底基板一侧的第四导电层；
    设置在所述第四导电层远离所述衬底基板一侧的第五导电层，
    其中，所述第一初始化电压信号线位于所述第三导电层，所述第二复位控制信号线位于所述第一导电层。
  10. 根据权利要求9所述的显示基板，其中，所述扫描控制信号线位于所述第一导电层，所述第二初始化电压信号线位于所述第四导电层。
  11. 根据权利要求9所述的显示基板，其中，所述发光控制信号线位于所述第一导电层，所述第三初始化电压信号线位于所述第三导电层。
  12. 根据权利要求9所述的显示基板，其中，所述第二复位控制信号线位于所述第一导电层。
  13. 根据权利要求9所述的显示基板，其中，所述显示基板还包括位于所述衬底基板的第一电源信号线，所述第一电源信号线沿第二方向延伸，两列子像素共用一个所述第一电源信号线，
    所述显示基板包括位于所述第二导电层中的第一导电转接部、位于所述第四导电层中的第一电源信号线转接部和第二电压信号线转接部，位于同一行的两个相邻子像 素的像素驱动电路具有各自的第一导电转接部和第二电压信号线转接部，位于同一行的两个相邻子像素的像素驱动电路共用所述第一电源信号线转接部，
    所述第一电源信号线通过第一过孔与所述第一电源信号线转接部电连接，所述第一电源信号线转接部的两端分别通过第二过孔与位于同一行的两个相邻子像素的像素驱动电路的第一导电转接部电连接，所述第一导电转接部通过第三过孔与所述第二电压信号线转接部的一端电连接，所述第二电压信号线转接部的另一端通过第四过孔与第一发光控制晶体管的源极或漏极电连接。
  14. 根据权利要求13所述的显示基板，其中，所述显示基板还包括位于第四导电层中的第一初始化电压连接部，
    所述第一初始化电压连接部的一端通过第五过孔与第一初始化电压信号线电连接，所述第一初始化电压连接部的另一端通过第六过孔分别与同一行的两个相邻子像素的第一复位晶体管的源极或漏极电连接。
  15. 根据权利要求14所述的显示基板，其中，所述显示基板还包括位于第四导电层中的第二初始化电压连接部，
    所述第二初始化电压连接部的两端分别通过第七过孔与第三初始化电压信号线电连接，位于两端之间的中端通过第八过孔与同一行的两个相邻子像素的第三复位晶体管的源极或漏极电连接，
    所述第二初始化电压连接部在所述第一方向上位于所述第一初始化电压连接部和所述第二电压信号线转接部之间。
  16. 根据权利要求9至15中任一项所述的显示基板，其中，所述第一复位晶体管为P型晶体管，所述第一复位控制信号线位于所述第一导电层，
    所述第二初始化电压信号线在所述衬底基板上的正投影与所述第一复位控制信号线在所述衬底基板上的正投影至少部分重叠。
  17. 根据权利要求16中所述的显示基板，其中，所述第一复位晶体管包括有源层，所述第一复位晶体管的有源层位于所述第一半导体层。
  18. 根据权利要求9所述的显示基板，其中，所述显示基板还包括至少一个镂空区域，所述至少一个镂空区域包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧为所述至少一个镂空区域在第一方向上相对的两侧，所述第三侧和所述第四侧为所述至少一个镂空区域在第二方向上相对的两侧，
    所述显示基板包括设置在所述衬底基板上的多个数据线，所述多个数据线分别沿第二方向延伸，所述多个数据线包括邻近所述至少一个镂空区域的第一数据线和第二数据线，所述第一数据线和所述第二数据线在第一方向上分别位于所述至少一个镂空区域的第一侧和第二侧，
    所述第一复位控制信号线和所述扫描控制信号线邻近所述至少一个镂空区域，在第二方向上分别位于所述至少一个镂空区域的第三侧和第四侧，
    所述第一复位控制信号线和所述扫描控制信号线分别与所述第一数据线和所述第二数据线交叉，以包围形成所述至少一个镂空区域。
  19. 根据权利要求9所述的显示基板，其中，所述显示基板还包括至少一个镂空区域，所述至少一个镂空区域包括第一侧、第二侧、第三侧和第四侧，所述第一侧和所述第二侧为所述至少一个镂空区域在第一方向上相对的两侧，所述第三侧和所述第四侧为所述至少一个镂空区域在第二方向上相对的两侧，
    所述显示基板包括设置在所述衬底基板上的多个数据线，所述多个数据线分别沿第二方向延伸，所述多个数据线包括邻近所述至少一个镂空区域的第一数据线和第二数据线，所述第一数据线和所述第二数据线在第一方向上分别位于所述至少一个镂空区域的第一侧和第二侧，
    所述第一复位控制信号线和补偿控制信号线邻近所述至少一个镂空区域，在第二方向上分别位于所述至少一个镂空区域的第三侧和第四侧，
    所述第一复位控制信号线和所述补偿控制信号线分别与所述第一数据线和所述第二数据线交叉，以包围形成所述至少一个镂空区域。
  20. 根据权利要求18或19所述的显示基板，其中，所述第一数据线和所述第二数据线中的每一个包括主体部分和弯折部分，所述第一数据线的弯折部分相对于所述第一数据线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述第二数据线的 弯折部分相对于所述第二数据线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述第一数据线的弯折部分和所述第二数据线的弯折部分朝相反的方向弯折。
  21. 根据权利要求18所述的显示基板，其中，所述第一复位控制信号线和所述扫描控制信号线中的每一个包括主体部分和弯折部分，所述第一复位控制信号线的弯折部分相对于所述第一复位控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述扫描控制信号线的弯折部分相对于所述扫描控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述第一复位控制信号线的弯折部分和所述扫描控制信号线的弯折部分朝相反的方向弯折。
  22. 根据权利要求19所述的显示基板，其中，所述第一复位控制信号线和所述补偿控制信号线中的每一个包括主体部分和弯折部分，所述第一复位控制信号线的弯折部分相对于所述第一复位控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述补偿控制信号线的弯折部分相对于所述补偿控制信号线的主体部分朝远离所述至少一个镂空区域的方向弯折，所述第一复位控制信号线的弯折部分和所述补偿控制信号线的弯折部分朝相反的方向弯折。
  23. 根据权利要求1至8中任一项所述的显示基板，其中，在一个子像素内，重叠部分的面积与所述控制信号线在所述衬底基板上的正投影面积的比值在80％至95％的范围。
  24. 一种显示基板，其中，包括：
    衬底基板；
    设置在所述衬底基板上的多个子像素，所述多个子像素沿第一方向和第二方向布置，至少一个所述子像素包括发光元件；
    设置在所述衬底基板上的多个像素驱动电路，所述多个像素驱动电路沿第一方向和第二方向布置，所述多个像素驱动电路用于分别驱动所述多个子像素的发光元件，至少一个所述像素驱动电路包括第一复位晶体管、第二复位晶体管和第三复位晶体管；
    设置于所述衬底基板上的初始化电压信号线，所述初始化电压信号线包括沿第一方向延伸的部分，所述初始化电压信号线用于给所述像素驱动电路提供初始化电压信 号，所述初始化电压信号线包括第一初始化电压信号线、第二初始化电压信号线和第三初始化电压信号线，所述第一初始化电压信号线、所述第二初始化电压信号线和所述第三初始化电压信号线分别与所述第一复位晶体管、所述第二复位晶体管和所述第三复位晶体管的第一极电连接；
    设置于所述衬底基板上的控制信号线，所述控制信号线包括沿第一方向延伸的部分，所述控制信号线用于给所述像素驱动电路提供控制信号，以控制所述像素驱动电路的至少两个晶体管导通；
    其中，在用于驱动一行子像素的像素驱动电路的一帧内，所述控制信号线上的控制信号在至少一个第一时间段内控制所述像素驱动电路的至少两个晶体管导通，所述初始化电压信号线上的初始化电压信号在第二时间段内提供给所述像素驱动电路，所述第一时间段和所述第二时间段在时序上间隔设置；以及
    所述初始化电压信号线和所述控制信号线位于不同的导电层中，所述第一初始化电压信号线、所述第二初始化电压信号线和所述第三初始化电压信号线中每一个在所述衬底基板上的正投影与所述控制信号线在所述衬底基板上的正投影至少部分重叠，在一个子像素内，重叠部分的面积与所述控制信号线在所述衬底基板上的正投影面积的比值在60％至100％的范围。
  25. 一种显示装置，其中，包括如权利要求1至23中任一项所述的显示基板或如权利要求24所述的显示基板。
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