WO2024178673A1 - 像素驱动电路、显示面板及显示装置 - Google Patents

像素驱动电路、显示面板及显示装置 Download PDF

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Publication number
WO2024178673A1
WO2024178673A1 PCT/CN2023/079025 CN2023079025W WO2024178673A1 WO 2024178673 A1 WO2024178673 A1 WO 2024178673A1 CN 2023079025 W CN2023079025 W CN 2023079025W WO 2024178673 A1 WO2024178673 A1 WO 2024178673A1
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WIPO (PCT)
Prior art keywords
electrode
transistor
orthographic projection
gate
line
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
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PCT/CN2023/079025
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English (en)
French (fr)
Inventor
卢红婷
卢辉
张云鹏
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to US18/996,943 priority Critical patent/US20260031035A1/en
Priority to CN202380007989.6A priority patent/CN118901096A/zh
Priority to PCT/CN2023/079025 priority patent/WO2024178673A1/zh
Publication of WO2024178673A1 publication Critical patent/WO2024178673A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel and a display device.
  • a pixel driving circuit generally includes a driving transistor, which provides a driving current to a light-emitting unit according to a data signal at its gate.
  • the Data Range (voltage range of the data signal) is limited by the chip of the display panel, which causes the pixel driving circuit to be unable to output a larger driving current.
  • a pixel driving circuit comprising: a plurality of driving transistors, the second electrode of each driving transistor is connected to the first electrode of the same light-emitting unit, and each driving transistor is used to input a driving current to the light-emitting unit according to its gate voltage.
  • a gate of each of the driving transistors is connected to a first node, and a first electrode of each of the driving transistors is connected to a first power supply terminal.
  • the pixel driving circuit further includes: a data writing circuit, a compensation circuit, a light emitting control circuit, a first reset circuit, a second reset circuit, and a storage circuit.
  • the data writing circuit is connected to the data signal terminal, the first electrode of each of the driving transistors, and the first gate driving signal terminal, and is used to respond to the signal of the first gate driving signal terminal to transmit the signal of the data signal terminal to the first electrode of each of the driving transistors;
  • the compensation circuit is connected to the first node, the second electrode of each of the driving transistors, and the second gate driving signal terminal, and is used to respond to the signal of the second gate driving signal terminal to connect the first node and each of the driving transistors.
  • the light-emitting control circuit is connected to the first power supply terminal, the first electrode of each driving transistor, the enable signal terminal, the second electrode of each driving transistor, and the first electrode of the light-emitting unit, and is used to respond to the signal of the enable signal terminal to connect the first power supply terminal and the first electrode of each driving transistor, and is used to respond to the signal of the enable signal terminal to connect the second electrode of each driving transistor and the first electrode of the light-emitting unit;
  • the first reset circuit is connected to the first initial signal terminal, the first reset signal terminal, and the first node, and is used to respond to the signal of the first reset signal terminal to transmit the signal of the first initial signal terminal to the first node;
  • the second reset circuit is connected to the second initial signal terminal, the second reset signal terminal, and the first electrode of the light-emitting unit, and is used to respond to the signal of the second reset signal terminal to transmit the signal of the second initial signal terminal to the first electrode of the light-emitting unit;
  • the storage circuit is connected between the first
  • the data writing circuit includes: a fourth transistor, the first electrode of the fourth transistor is connected to the data signal terminal, the second electrode is connected to the first electrode of each of the driving transistors, and the gate is connected to the first gate driving signal terminal;
  • the compensation circuit includes: a second transistor, the first electrode of the second transistor is connected to the first node, the second electrode is connected to the second electrode of each of the driving transistors, and the gate is connected to the second gate driving signal terminal;
  • the light emitting control circuit includes: a fifth transistor and a sixth transistor, the first electrode of the fifth transistor is connected to the first power supply terminal, the second electrode is connected to the first electrode of each of the driving transistors, and the gate is connected to the enable signal terminal;
  • the first electrode of the sixth transistor is connected to the second electrode of each of the driving transistors, the second electrode is connected to the first electrode of the light emitting unit, and the gate is connected to the enable signal terminal;
  • the first reset circuit includes: a first transistor, the first electrode of the first transistor is connected to the first initial
  • the pixel driving circuit includes multiple sub-pixel driving circuits, each of the sub-pixel driving circuits includes at least one driving transistor, and each of the sub-pixel driving circuits is connected to the same light-emitting unit, and the sub-pixel driving circuit is used to provide a driving current to the light-emitting unit.
  • the sub-pixel driving circuit further includes: a data writing circuit, a compensation circuit, a light emitting control circuit, a first reset circuit, a second reset circuit, and a storage circuit.
  • the data writing circuit is connected to a data signal terminal, a first electrode of the driving transistor, and a first gate driving signal terminal, and is used to respond to a signal of the first gate driving signal terminal to transmit the signal of the data signal terminal to the first electrode of the driving transistor;
  • the compensation circuit is connected to the gate of the driving transistor, the second electrode of the driving transistor, and a second gate driving signal terminal, and is used to respond to a signal of the second gate driving signal terminal to connect the gate of the driving transistor and the second electrode of the driving transistor;
  • the light emitting control circuit is connected to a first power supply terminal, a first electrode of the driving transistor, an enable signal terminal, a second electrode of the driving transistor, and a first electrode of the light emitting unit, and is used to respond to a signal of the enable signal terminal to connect the first power supply
  • the data writing circuit includes: a fourth transistor, the first electrode of the fourth transistor is connected to the data signal terminal, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the first gate driving signal terminal;
  • the compensation circuit includes: a second transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the second gate driving signal terminal;
  • the light emitting control circuit includes: a fifth transistor and a sixth transistor, the first electrode of the fifth transistor is connected to the first power supply terminal, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the enable signal terminal;
  • the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode is connected to the first electrode of the light emitting unit, and the gate is connected to the enable signal terminal;
  • the first reset circuit includes: a first transistor, the first electrode of the first transistor is connected to the first initial signal terminal, the second electrode is connected to the first
  • the storage circuit includes: a capacitor, the first electrode of the capacitor is connected to the gate of the driving transistor, and the second electrode is connected to the first power supply terminal.
  • a display panel is provided, wherein the display panel includes the above-mentioned pixel driving circuit.
  • a display panel includes a light-emitting unit and a pixel driving circuit for driving the light-emitting unit, the pixel driving circuit includes a plurality of driving transistors, the second electrode of each driving transistor is connected to the first electrode of the same light-emitting unit, and each driving transistor is used to input a driving current to the light-emitting unit according to its gate voltage.
  • the display panel also includes: a substrate, an active layer, the active layer is located on one side of the substrate, the active layer includes a plurality of third active portions, and the third active portion is used to form a channel region of the driving transistor.
  • the active layer further includes an eighth active portion and a ninth active portion, and the third active portion in the same pixel driving circuit is connected in parallel between the eighth active portion and the ninth active portion.
  • the orthographic projection of the eighth active portion on the substrate and the orthographic projection of the ninth active portion on the substrate extend along the second direction; and the orthographic projections of multiple third active portions on the substrate in the same pixel driving circuit are spaced apart along the second direction.
  • the display panel also includes: a first conductive layer, the first conductive layer is located on the side of the active layer away from the base substrate, the first conductive layer includes a first conductive part, the orthographic projection of the first conductive part on the base substrate covers the orthographic projection of each third active part of the same pixel driving circuit on the base substrate; at least a portion of the structure of the first conductive part is used to form the gate of the driving transistor.
  • the pixel driving circuit further includes a fourth transistor and a fifth transistor, the first electrode of the fourth transistor is connected to the data line, the second electrode of the fourth transistor is connected to the first electrode of the driving transistor, the first electrode of the fifth transistor is connected to the first power line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor;
  • the active layer further includes: a fourth active portion and a fifth active portion, the fourth active portion is connected to one end of the eighth active portion, and the fourth active portion is used to form a channel region of the fourth transistor;
  • the The fifth active portion is connected to the other end of the eighth active portion, and the fifth active portion is used to form a channel region of the fifth transistor;
  • the display panel also includes: a first conductive layer, the first conductive layer is located on the side of the active layer away from the base substrate, the first conductive layer includes: a first gate line, an enable signal line, the orthographic projection of the first gate line on the base substrate extends along the first direction and covers the orthographic projection
  • the pixel driving circuit includes a plurality of sub-pixel driving circuits, and the orthographic projections of the plurality of sub-pixel driving circuits on the substrate are arrayed along a first direction and/or a second direction, and the first direction and the second direction intersect; each of the sub-pixel driving circuits includes the driving transistor, and each of the sub-pixel driving circuits is connected to the same light-emitting unit, and the sub-pixel driving circuit is used to provide a driving current to the light-emitting unit.
  • the display panel also includes: an active layer and a first conductive layer, the active layer is located on one side of the substrate, the active layer includes a plurality of third active portions, and the third active portions are used to form a channel region of the driving transistor; the first conductive layer is located on the side of the active layer away from the substrate, the first conductive layer includes a plurality of first conductive portions arranged at intervals, the first conductive portion and the third active portion are arranged correspondingly, the orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the corresponding third active portion on the substrate, and the first conductive portion is used to form the gate of the driving transistor.
  • the sub-pixel driving circuit further includes a sixth transistor and a seventh transistor, the first electrode of the sixth transistor is connected to the second electrode of the driving transistor, the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit;
  • the active layer further includes: a sixth active portion, a seventh active portion, and a tenth active portion, the sixth active portion is connected to the third active portion, and the sixth active portion is used to form a channel region of the sixth transistor;
  • the seventh active portion is connected to the sixth active portion away from the first electrode of the light-emitting unit
  • the seventh active portion is used to form a channel region of the seventh transistor at one end of the third active portion; the tenth active portion is connected between the sixth active portion and the seventh active portion.
  • the display panel further includes: a fourth conductive layer, the fourth conductive layer is located on a side of the first conductive layer away from the base substrate, the fourth conductive portion includes a first bridge portion, the first bridge portion is respectively connected to each of the tenth active portions in the same pixel driving circuit, and the first bridge portion is connected to the first electrode of the light emitting unit.
  • the sub-pixel driving circuit further includes a first transistor, a second transistor, and a seventh transistor, wherein the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the second transistor is connected to the gate of the driving transistor, the second electrode of the second transistor is connected to the second electrode of the driving transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit.
  • the active layer further includes: a first active portion and a second active portion, wherein the first active portion is used to form a channel region of the first transistor; and the second active portion is used to form a channel region of the second transistor.
  • the first conductive layer further includes: a first reset signal line and a first gate line, wherein the orthographic projection of the first reset signal line on the substrate extends along the first direction, the orthographic projection of the first reset signal line on the substrate covers the orthographic projection of the first active portion on the substrate, and a partial structure of the first reset signal line is used to form the gate of the first transistor; the orthographic projection of the first gate line on the substrate extends along the first direction, the orthographic projection of the first gate line on the substrate covers the orthographic projection of the second active portion on the substrate, and a partial structure of the first gate line is used to form the gate of the second transistor;
  • the display panel further includes a second conductive layer, which is located on a side of the first conductive layer away from the substrate, and the second conductive layer includes
  • the active layer further includes: an eleventh active portion, the eleventh active portion is connected between the first active portion and the second active portion.
  • the second conductive layer further includes: a first protruding portion, the first protruding portion is connected to the second initial signal line, An orthographic projection of the first protruding portion on the base substrate extends along the second direction, and an orthographic projection of the first protruding portion on the base substrate at least partially overlaps with an orthographic projection of the eleventh active portion on the base substrate.
  • the second transistor is a dual-channel structure, the dual channel of the second transistor includes a first channel and a second channel, the second active portion includes: a first sub-active portion and a second sub-active portion, the first sub-active portion is used to form the first channel of the second transistor; the second sub-active portion is used to form the second channel of the second transistor; the active layer also includes: a third sub-active portion, the third sub-active portion is connected between the first sub-active portion and the second sub-active portion.
  • the second conductive layer also includes: a second protruding portion, the second protruding portion is connected to the second initial signal line, the orthographic projection of the second protruding portion on the substrate extends along the second direction, and the orthographic projection of the second protruding portion on the substrate and the orthographic projection of the third sub-active portion on the substrate at least partially overlap.
  • the sub-pixel driving circuit in the pixel driving circuit is distributed at least in the second direction, and the sub-pixel driving circuit also includes a first transistor, a second transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor; a first electrode of the first transistor is connected to a first initial signal line, and a second electrode is connected to a gate of the driving transistor; a first electrode of the second transistor is connected to the gate of the driving transistor, and a second electrode is connected to a second electrode of the driving transistor; a first electrode of the fourth transistor is connected to a data line, and a second electrode is connected to a first electrode of the driving transistor; a first electrode of the fifth transistor is connected to a first power line, and a second electrode is connected to a first electrode of the driving transistor; a first electrode of the sixth transistor is connected to a second electrode of the driving transistor, and a second electrode is connected to a first electrode of the light-emitting unit; a first electrode of the seventh
  • the first conductive layer further includes: a first reset signal line, a second reset signal line, a first gate line, and an enable signal line, wherein the orthographic projection of the first reset signal line on the substrate extends along the first direction, and a portion of the structure of the first reset signal line is used to form the gate of the first transistor; the orthographic projection of the second reset signal line on the substrate extends along the first direction, and a portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, and the first reset signal line in the adjacent next row of sub-pixel driving circuits is multiplexed as the second reset signal line in the sub-pixel driving circuit of the current row; the orthographic projection of the first gate line on the substrate extends along the first direction, and a portion of the first gate line
  • the structure is used to form the gates of the second transistor and the fourth transistor respectively; the positive projection of the enable signal line on the substrate extends along the first direction, and the partial structure of the enable signal line is used to form the gates of the fifth transistor and the sixth transistor
  • the orthographic projections of the plurality of short enable signal lines corresponding to the path on the substrate substrate are arranged at intervals in the row direction;
  • the display panel also includes: a third conductive layer, the third conductive layer is located on the side of the first conductive layer away from the substrate substrate, the third conductive layer includes a first connecting line, a second connecting line, and a third connecting line; wherein the orthographic projections of the first connecting line, the second connecting line, and the third connecting line on the substrate substrate substrate extend along the second direction, the first connecting line is respectively connected to the first long reset signal line and the first short reset signal line through a via hole, the second connecting line is respectively connected to the first long gate line and the first short gate line through a via hole, and the third connecting line is respectively connected to the long enable signal line through a via hole. signal line and a short enable signal line.
  • the display panel further includes: a second conductive layer, the second conductive layer is located between the first conductive layer and the third conductive layer, the second conductive layer includes the first initial signal line and the second initial signal line, and the orthographic projections of the first initial signal line and the second initial signal line on the substrate extend along the first direction; wherein the plurality of first initial signal lines include a first long initial signal line and a first short initial signal line, the first long initial signal line and the sub-pixel driving circuits located in the same row are arranged correspondingly, the first long initial signal line is connected to the sub-pixel driving circuit corresponding thereto, the first short initial signal line and the sub-pixel driving circuits in the same row in the pixel driving circuit group are arranged correspondingly, the first short initial signal line is connected to the sub-pixel driving circuit corresponding thereto, and the plurality of first short initial signal lines corresponding to the sub-pixel driving circuits in the same row are arranged on the substrate.
  • the plurality of first initial signal lines include a first long initial signal line and
  • the multiple second initial signal lines include a second long initial signal line and a second short initial signal line, the second long initial signal line is arranged corresponding to the sub-pixel driving circuit located in the same row, the second long initial signal line is connected to the corresponding sub-pixel driving circuit, the second short initial signal line is arranged corresponding to the sub-pixel driving circuit in the same row in the pixel driving circuit group, the second short initial signal line is connected to the corresponding sub-pixel driving circuit, and the orthographic projections of the multiple second short initial signal lines corresponding to the sub-pixel driving circuit in the same row on the bottom substrate are arranged at intervals in the row direction;
  • the third conductive layer also includes a fourth connecting line and a fifth connecting line, the fourth connecting line is connected to the first long initial signal line and the first short initial signal line through a via hole, and the fifth connecting line is connected to the second long initial signal line and the second short initial signal line through a via hole.
  • the pixel driving circuit further includes a first transistor and a seventh transistor, the first electrode of the first transistor is connected to the first initial signal line, the second electrode of the first transistor is connected to the gate of the driving transistor, the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit;
  • the display panel further includes: a second conductive layer and a third conductive layer, the second conductive layer is located on the side of the active layer away from the base substrate, the second conductive layer includes the first initial signal line and the second initial signal line, the orthographic projection of the first initial signal line on the base substrate and the orthographic projection of the second initial signal line on the base substrate are along the first conductive layer.
  • the first conductive layer is located on a side of the second conductive layer away from the base substrate, the third conductive layer includes a first initial connection line and a second initial connection line, the orthographic projection of the first initial connection line on the base substrate and the orthographic projection of the second initial connection line on the base substrate extend along a second direction, and the first direction and the second direction intersect; wherein the first initial connection line is connected to the first initial signal line intersecting with its orthographic projection on the base substrate through a via hole, and the second initial connection line is connected to the second initial signal line intersecting with its orthographic projection on the base substrate through a via hole.
  • the display panel includes a plurality of pixel units, the pixel units include a plurality of pixel driving circuits distributed in the first direction, and the pixel driving circuits in the same pixel unit form a pixel driving circuit group; a column of the pixel driving circuit groups distributed in the second direction is correspondingly provided with a first initial connection line and a second initial connection line; the orthographic projection of the pixel driving circuit group on the substrate is located between the orthographic projections of the first initial connection line and the second initial connection line corresponding thereto on the substrate.
  • the display area of the display panel includes a normal display area
  • the display panel also includes: a plurality of pixel units, the plurality of pixel units include a first pixel unit, the first pixel unit is located in the normal display area, the first pixel unit includes a plurality of pixel driving circuits distributed in a first direction, and the pixel driving circuits in the same first pixel unit form a first pixel driving circuit group;
  • the display panel also includes: a fourth conductive layer, the fourth conductive layer is located on a side of the active layer away from the substrate, the fourth conductive layer includes a first power connection line, the first power connection line is used to provide a high-level power signal to the pixel driving circuit, and the orthographic projection of the first power connection line on the substrate is a ring; wherein the first power connection line and the first pixel driving circuit group are arranged correspondingly, and the orthographic projection of the first pixel driving circuit group on the substrate is located within the orthographic projection of the corresponding first power
  • the display panel further includes: a third conductive layer, the third conductive layer is located between the active layer and the fourth conductive layer, the third conductive layer includes a power bridge line, the orthographic projection of the power bridge line on the substrate extends along a second direction, and the first direction and the second direction intersect; wherein the orthographic projection of at least part of the structure of the power bridge line on the substrate is located between two adjacent layers in the first direction.
  • the first power connection line is between the orthographic projections on the base substrate, and the power bridge line is connected to two adjacent first power connection lines through via holes.
  • the pixel driving circuit includes a fifth transistor, a first electrode of the fifth transistor is connected to a first power line, and a second electrode of the fifth transistor is connected to the first electrode of the driving transistor;
  • the display panel also includes: a third conductive layer, the third conductive layer is located between the active layer and the fourth conductive layer, and the third conductive layer includes the first power line; wherein the orthographic projection of the first power line on the substrate extends along a second direction, the first direction and the second direction intersect, the orthographic projection of the first power line on the substrate intersects with the orthographic projection of the first power connection line on the substrate, and the first power line is connected to the first power connection line intersecting with its orthographic projection on the substrate through a via.
  • the pixel driving circuit includes a plurality of sub-pixel driving circuits, and the orthographic projections of the plurality of sub-pixel driving circuits on the substrate are arrayed along a first direction and/or a second direction, and the first direction and the second direction intersect; each of the sub-pixel driving circuits includes the driving transistor, and each of the sub-pixel driving circuits is connected to the same light-emitting unit, and the sub-pixel driving circuit is used to provide a driving current to the light-emitting unit; the sub-pixel driving circuit also includes a fifth transistor, a first electrode of the fifth transistor is connected to a first power line sub-portion, and a second electrode of the fifth transistor is connected to a first electrode of the driving transistor; the fourth conductive layer also includes the first power line sub-portion, and the orthographic projection of the first power line sub-portion on the substrate includes a portion extending along the second direction and a portion extending along the first direction, the first power line sub-portion and the pixel driving circuit are
  • the sub-pixel driving circuit further includes a second transistor, a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;
  • the display panel further includes: a third conductive layer, the third conductive layer is located between the active layer and the fourth conductive layer, the third conductive layer includes a second bridge portion, and the second bridge portion connects the gate electrode of the driving transistor and the second electrode of the second transistor;
  • the first power line sub-portion includes: a plurality of second conductive portions, The second conductive portion and the sub-pixel driving circuit are arranged correspondingly, the orthographic projection of the second conductive portion on the base substrate and the orthographic projection of the second bridge portion in the corresponding sub-pixel driving circuit on the base substrate at least partially overlap, and the second conductive portion is connected to the first electrode of the fifth transistor in the corresponding sub-pixel driving circuit.
  • the fourth conductive layer further includes: a first connecting portion, the orthographic projection of the first connecting portion on the base substrate extends along the second direction, and the first connecting portion is connected between the second conductive portion and the first power connection line adjacent to each other in the second direction.
  • the display panel also includes: a third conductive layer, the third conductive layer also includes: a plurality of third bridging portions, the orthographic projection of at least a portion of the structure of the third bridging portion on the base substrate is located between the orthographic projections of two adjacent first power connection lines in the second direction on the base substrate, and the third bridging portions are respectively connected to the two adjacent first power connection lines through vias.
  • the fourth conductive layer also includes: a second power connection line, the second power connection line and the first power connection line are arranged correspondingly, the orthographic projection of the second power connection line on the base substrate is a ring, and the orthographic projection of the first power connection line on the base substrate is located within the orthographic projection of the corresponding second power connection line on the base substrate;
  • the display panel also includes: a common electrode layer, the common electrode layer is located on the side of the fourth conductive layer away from the base substrate, the common electrode layer is used to form a second electrode of the light-emitting unit, and the second power connection line is connected to the common electrode layer through a via.
  • the display area of the display panel also includes a compression area, and the compression area is located on one side of the normal display area in the first direction;
  • the plurality of pixel units also include a second pixel unit, and the second pixel unit is located in the compression area.
  • the second pixel unit includes a plurality of pixel driving circuits distributed in the first direction, and the pixel driving circuits in the same second pixel unit form a second pixel driving circuit group;
  • the fourth conductive layer also includes: a third power connection line, and the third power connection line is used to provide a high-level power signal to the pixel driving circuit.
  • the third power connection line and the second pixel driving circuit group are correspondingly arranged, and the third power connection line includes a first side edge, and the orthographic projection of the first side edge on the substrate extends along the second direction and is located at the second image corresponding to it.
  • the orthographic projection of the pixel driving circuit group on the substrate is on one side of the first direction, and the first direction and the second direction intersect; wherein the distance between the orthographic projection of the first power connection line on the substrate and the orthographic projection of the first pixel driving circuit group on the substrate in the first direction is greater than the distance between the orthographic projection of the first side on the substrate and the orthographic projection of the second pixel driving circuit group on the substrate in the first direction.
  • the fourth conductive layer further includes: a second power connection line and a fourth power connection line, the second power connection line and the first power connection line are arranged correspondingly, the orthographic projection of the second power connection line on the substrate is a ring, and the orthographic projection of the first power connection line on the substrate is located within the orthographic projection of the corresponding second power connection line on the substrate; the fourth power connection line and the third power connection line are arranged correspondingly;
  • the display panel further includes: a common electrode layer, the common electrode layer is located on the side of the fourth conductive layer away from the substrate, the common electrode layer is used to form the second electrode of the light-emitting unit, the second power connection line and the fourth power connection line are both connected to the common electrode layer through vias;
  • the display panel further includes: an electrode layer, the electrode layer is located between the fourth conductive layer and the common electrode layer, the electrode layer includes a first electrode ring and a second electrode line; the first electrode ring is connected between the second power connection line and the common
  • a display device comprising the above-mentioned display panel.
  • FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;
  • FIG2 is a timing diagram of various control signals in a driving method of the pixel driving circuit shown in FIG1 ;
  • FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG4 is a structural diagram of the active layer in FIG3 ;
  • FIG5 is a structural diagram of the first conductive layer in FIG3 ;
  • FIG6 is a structural diagram of the second conductive layer in FIG3 ;
  • FIG7 is a structural diagram of the third conductive layer in FIG3 ;
  • FIG8 is a structural diagram of the fourth conductive layer in FIG3;
  • FIG9 is a structural layout diagram of the active layer and the first conductive layer in FIG3 ;
  • FIG10 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG3 ;
  • FIG11 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG3 ;
  • FIG12 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;
  • FIG13 is a structural diagram of the active layer in FIG12;
  • FIG14 is a structural layout diagram of the first conductive layer in FIG12;
  • FIG15 is a structural layout diagram of the second conductive layer in FIG12;
  • FIG16 is a structural layout diagram of the third conductive layer in FIG12;
  • FIG17 is a structural layout diagram of the fourth conductive layer in FIG12;
  • FIG18 is a structural plate of the electrode layer and the pixel defining layer in FIG12;
  • FIG19 is a structural layout diagram of the active layer and the first conductive layer in FIG12;
  • FIG20 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG12;
  • FIG21 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG12;
  • FIG. 22 is a diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, A structural layout of a fourth conductive layer;
  • FIG23 is a partial cross-sectional view of the display panel shown in FIG12 taken along dotted line BB;
  • FIG24 is a schematic structural diagram of another exemplary embodiment of a pixel driving circuit disclosed herein;
  • FIG. 25 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG26 is a structural layout diagram of the active layer in FIG25;
  • FIG27 is a structural layout diagram of the first conductive layer in FIG25;
  • FIG28 is a structural layout diagram of the second conductive layer in FIG25;
  • FIG29 is a structural layout diagram of the third conductive layer in FIG25;
  • FIG30 is a structural layout diagram of the fourth conductive layer in FIG25;
  • FIG31 is a structural layout diagram of the active layer and the first conductive layer in FIG25;
  • FIG32 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG25;
  • FIG33 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG25;
  • FIG34 is a structural diagram of another exemplary embodiment of a display panel disclosed herein;
  • FIG35 is a structural layout diagram of the active layer in FIG34;
  • FIG36 is a structural layout diagram of the first conductive layer in FIG34;
  • FIG37 is a structural layout diagram of the second conductive layer in FIG34;
  • FIG38 is a structural layout diagram of the third conductive layer in FIG34;
  • FIG39 is a structural layout diagram of the fourth conductive layer in FIG34;
  • FIG40 is a structural plate of the electrode layer and the pixel definition layer in FIG34;
  • FIG41 is a structural layout diagram of the active layer and the first conductive layer in FIG34;
  • FIG42 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG34;
  • FIG43 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG34;
  • FIG44 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG34;
  • FIG45 is a partial cross-sectional view of the display panel shown in FIG34 taken along the dotted line CC;
  • FIG46 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;
  • FIG47 is a structural layout diagram of the second pixel unit on the right side of FIG46 ;
  • FIG48 is a structural layout diagram of the active layer in FIG47;
  • FIG49 is a structural layout diagram of the first conductive layer in FIG47;
  • FIG50 is a structural layout diagram of the second conductive layer in FIG47;
  • FIG51 is a structural layout diagram of the third conductive layer in FIG47;
  • FIG52 is a structural layout diagram of the fourth conductive layer in FIG47;
  • FIG53 is a structural plate of the electrode layer and the pixel defining layer in FIG47;
  • FIG54 is a structural layout diagram of the active layer and the first conductive layer in FIG47;
  • FIG55 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG47;
  • FIG56 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG47;
  • FIG57 is a structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG47 .
  • a pixel driving circuit generally includes a driving transistor, which provides a driving current to a light-emitting unit according to a data signal at its gate.
  • the Data Range (voltage range of the data signal) is limited by the chip of the display panel, which causes the pixel driving circuit to be unable to output a larger driving current.
  • this exemplary embodiment provides a pixel driving circuit, which may include: multiple driving transistors, the second electrode of each driving transistor is connected to the first electrode of the same light-emitting unit, and each driving transistor is used to input a driving current to the light-emitting unit according to its gate voltage.
  • the pixel driving circuit provided in this exemplary embodiment provides a driving current to the same light-emitting unit through a plurality of driving transistors connected in parallel, so that a larger driving current can be provided to the light-emitting unit under the action of the same data signal.
  • the pixel driving circuit can be applied to a display panel and a display device with a large pixel unit layout area and a large driving current requirement.
  • the pixel driving circuit can be applied to a spliced screen.
  • FIG1 it is a schematic diagram of the structure of an exemplary embodiment of the pixel driving circuit of the present disclosure.
  • the pixel driving circuit includes a plurality of driving transistors T3, the second electrode of each of the driving transistors T3 is connected to the first electrode of the same light-emitting unit OLED, and each of the driving transistors T3 is used to input a driving current to the light-emitting unit OLED according to its gate voltage.
  • the gate of each of the driving transistors T3 is connected to the first node N1, and the first electrode of each of the driving transistors T3 is connected to the first power supply terminal VDD.
  • the second electrodes of the driving transistors T3 are all connected to the first electrode of the same light-emitting unit OLED.
  • the “connection” here can be understood as electrical connection, electrical coupling, etc., and the “connection” can be direct connection or indirect connection.
  • the pixel driving circuit further includes: a data writing circuit 1, a compensation circuit 2, a light emitting control circuit 3, a first reset circuit 4, a second reset circuit 5, and a storage circuit 6.
  • the data writing circuit 1 is connected to the data signal terminal Da, the first electrode of each of the driving transistors T3, and the first gate driving signal terminal G1, and is used to respond to the signal of the first gate driving signal terminal G1 to transmit the signal of the data signal terminal Da to the first electrode of each of the driving transistors T3;
  • the compensation circuit 2 is connected to the first node N1, the second electrode of each of the driving transistors T3, and the second gate driving signal terminal G2, and is used to respond to the signal of the second gate driving signal terminal G2 to connect the first node N1 and the second electrode of each of the driving transistors T3;
  • the light emitting control circuit 3 is connected to the first node N1, the second electrode of each of the driving transistors T3, and the second gate driving signal terminal G2.
  • a power supply terminal VDD a first electrode of each of the driving transistors T3, an enable signal terminal EM, a second electrode of each of the driving transistors T3, and a first electrode of the light-emitting unit OLED, for responding to a signal of the enable signal terminal EM to connect the first power supply terminal VDD and the first electrode of each of the driving transistors T3, and for responding to a signal of the enable signal terminal EM to connect the second electrode of each of the driving transistors T3 and the first electrode of the light-emitting unit OLED; a first reset circuit 4 connected to a first initial signal terminal Vinit1, a first reset signal terminal Re1, and the first node N1, for responding to a signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal Vinit1 to the first node N1; a second reset circuit 5 connected to The second initial signal terminal Vinit2, the second reset signal terminal Re2, and the first electrode of the light-emitting unit OLED are used to respond to the signal of the second reset signal terminal Re2 to
  • the first gate drive signal terminal G1 and the second gate drive signal terminal G2 may be the same signal control terminal or different signal control terminals; for example, the opening time of the second gate drive signal terminal G2 is longer than that of the first gate drive signal terminal G1, so that the data signal controlled by the first gate drive signal terminal G1 can be fully written into the gate of the driving transistor; for another example, the first gate drive signal terminal G1 and the second gate drive signal terminal G2 are the same control signal terminal to save control signal lines.
  • the embodiments below are described with the first gate drive signal terminal G1 and the second gate drive signal terminal G2 being the same control signal terminal, that is, the compensation circuit 2 is controlled by the first gate drive signal terminal G1.
  • the data writing circuit 1 may include: a fourth transistor T4, a first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode is connected to the first electrode of each of the driving transistors T3, and a gate is connected to the first gate driving signal terminal G1;
  • the compensation circuit 2 may include: a second transistor T2, a first electrode of the second transistor T2 is connected to the first node N1, a second electrode is connected to the second electrode of each of the driving transistors T3, and a gate is connected to the first gate driving signal terminal G1;
  • the light emitting control circuit 3 may include: a fifth transistor T5 and a sixth transistor T6, a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode is connected to the first electrode of each of the driving transistors T3, and a gate is connected to the enable signal terminal EM; a first electrode of the sixth transistor T6 is connected to the first node N1, a second electrode is connected to the second electrode of each of the driving transistor
  • the first reset circuit 4 may include: a first transistor T1, the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode is connected to the first node N1, and the gate is connected to the first reset signal terminal Re1;
  • the second reset circuit 5 may include: a seventh transistor T7, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the first electrode of the light emitting unit OLED, and the gate is connected to the second reset signal terminal Re2;
  • the storage circuit 6 may include: a capacitor C, the first electrode of the capacitor C is connected to the first node N1, and the second electrode is connected to the first power supply terminal VDD.
  • the second electrode of the light emitting unit OLED is connected to the second power supply terminal VSS.
  • the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be P-type transistors.
  • the first power supply terminal VDD may be a high-level power supply terminal
  • the second power supply terminal VSS may be a low-level power supply terminal.
  • FIG2 it is a timing diagram of each control signal in a driving method of the pixel driving circuit shown in FIG1.
  • G1 represents the timing of the signal of the first gate driving signal terminal G1
  • Re1 represents the timing of the signal of the first reset signal terminal Re1
  • Re2 represents the timing of the signal of the second reset signal terminal Re2
  • EM represents the timing of the signal of the enable signal terminal EM.
  • the driving method of the pixel driving circuit may include a first reset stage t1, a data writing stage t2, a second reset stage t3, and a light-emitting stage t4.
  • the first reset stage t1 the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the first node N1.
  • the data writing stage t2 the first gate driving signal terminal G1 outputs a low-level signal, the fourth transistor T4, the second transistor T2, and the data signal terminal Da output a data signal to write a voltage Vdata+Vth to the first node N1, wherein Vdata is the voltage of the data signal, and Vth is the threshold voltage of the driving transistor T3.
  • the second reset stage t3 the second reset signal terminal outputs a low-level signal
  • the seventh transistor is turned on
  • the second initial signal terminal Vinit2 inputs the second initial signal to the second electrode of the sixth transistor T6.
  • the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 are turned on, and the plurality of driving transistors T3 drive the light-emitting unit to emit light under the voltage Vdata+Vth of the first node N1.
  • the output current I of each driving transistor in the pixel driving circuit of the present disclosure is ( ⁇ WCox/2L)(Vdata+Vth-Vdd-Vth) 2.
  • ⁇ is the carrier mobility
  • Cox is the gate capacitance per unit area
  • W is the width of the driving transistor channel
  • L is the length of the driving transistor channel
  • Vgs is the gate-source voltage difference of the driving transistor
  • Vth is the threshold voltage of the driving transistor.
  • the pixel driving circuit can avoid the influence of the driving transistor threshold on its output current. It should be understood that in other exemplary embodiments, the pixel driving circuit can also have other driving methods, for example, the seventh transistor can be turned on in the data writing stage t2.
  • This exemplary embodiment provides a display panel, which may include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence, wherein an insulating layer may be provided between adjacent conductive layers.
  • FIG. 3 is a structural layout diagram of an exemplary embodiment of a display panel of the present disclosure
  • FIG. 4 is a structural layout diagram of an active layer in FIG. 3
  • FIG. 5 is a structural layout diagram of a first conductive layer in FIG.
  • FIG6 is a structural layout diagram of the second conductive layer in FIG3
  • FIG7 is a structural layout diagram of the third conductive layer in FIG3
  • FIG8 is a structural layout diagram of the fourth conductive layer in FIG3
  • FIG9 is a structural layout diagram of the active layer and the first conductive layer in FIG3
  • FIG10 is a structural layout diagram of the active layer, the first conductive layer, and the second conductive layer in FIG3
  • FIG11 is a structural layout diagram of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG3 .
  • the display panel may include a plurality of pixel driving circuits, and the structure of the pixel driving circuit in the display panel shown in FIG3 and the structure of the pixel driving circuit shown in FIG1 only differ in that the pixel driving circuit in the display panel shown in FIG3 includes six parallel driving transistors.
  • the active layer may include a first active portion 61, a second active portion 62, a plurality of third active portions 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, a seventh active portion 67, an eighth active portion 68, a ninth active portion 69, a tenth active portion 610, an eleventh active portion 611, a twelfth active portion 612, a thirteenth active portion 613, a fourteenth active portion 614, and a fifteenth active portion 615.
  • the first active portion 61 is used to form the channel region of the first transistor T1
  • the second active portion 62 is used to form the channel region of the second transistor T2
  • the second transistor T2 is a dual-channel structure
  • the second active portion 62 includes a first sub-active portion 621 and a second sub-active portion 622
  • the first sub-active portion 621 is used to form the first channel of the second transistor
  • the second sub-active portion 622 is used to form the second channel of the second transistor T2
  • the active layer also includes a third sub-active portion 623, and the third sub-active portion 623 is connected between the first sub-active portion 621 and the second sub-active portion 622
  • the third active portion 63 can be used to form the channel region of the driving transistor T3
  • the fourth active portion 64 can be used to form the channel region of the fourth transistor T4
  • the fifth active portion 65 can be used to form the channel region of the fifth transistor T5
  • the sixth active portion 66 can be used to form the channel region of the
  • the active layer may be formed of polysilicon material, and accordingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be P-type low temperature polysilicon thin film transistors.
  • the first conductive layer may include: a first conductive portion 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2.
  • the orthographic projection of the first gate line G1 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate may all extend along the first direction X, and the first direction X and the second direction Y may intersect, for example, the first direction X may be a row direction, and the second direction Y may be a column direction.
  • the first gate line G1 may be used to provide a first gate drive signal terminal; the enable signal line EM may be used to provide an enable signal terminal; the first reset signal line Re1 may be used to provide a first reset signal terminal; and the second reset signal line Re2 may be used to provide a second reset signal terminal.
  • the orthographic projection of the first gate line G1 on the substrate covers the orthographic projections of the second active portion 62 and the fourth active portion 64 on the substrate, and a partial structure of the first gate line G1 is used to form the gate of the second transistor T2 and the gate of the fourth transistor, respectively.
  • the orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the sixth active portion 66 on the substrate, and the partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively.
  • the orthographic projection of the first reset signal line Re1 on the substrate covers the orthographic projection of the first active portion 61 on the substrate, and the partial structure of the first reset signal line Re1 is used to form the gate of the first transistor T1.
  • the orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 67 on the substrate, and the partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7.
  • the orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projections of all the third active portions 63 on the substrate, and the first conductive portion 11 can be used to form the common gate of multiple driving transistors T3 and the first electrode of the capacitor C.
  • the display panel can use the first conductive layer as a mask to perform conductor processing on the active layer, that is, the area of the active layer covered by the first conductive layer can form a channel region of the transistor, and the area not covered by the first conductive layer forms a conductor structure.
  • the second conductive layer may include: a first initial signal line Vinit1, a second initial signal line Vinit2, a third conductive portion 23 and a fourth conductive portion 24.
  • the orthographic projection of the line Vinit1 on the substrate substrate and the orthographic projection of the second initial signal line Vinit2 on the substrate substrate extend along the first direction X, the first initial signal line Vinit1 is used to provide a first initial signal terminal, and the second initial signal line Vinit2 is used to provide a second initial signal terminal.
  • the orthographic projection of the third conductive portion 23 on the substrate substrate and the orthographic projection of the first conductive portion 11 on the substrate substrate at least partially overlap, and the third conductive portion 23 is used to form a second electrode of the capacitor C.
  • the orthographic projection of the fourth conductive portion 24 on the substrate substrate and the orthographic projection of the third sub-active portion 623 on the substrate substrate at least partially overlap.
  • the third conductive layer may include a first power line VDD, a data line Da, a first initial connection line 3Vinit1, a second bridge portion 32, a fourth bridge portion 34, a fifth bridge portion 35, a sixth bridge portion 36, a seventh bridge portion 37, and an eighth bridge portion 38.
  • the orthographic projection of the first power line VDD on the substrate, the orthographic projection of the data line Da on the substrate, and the orthographic projection of the first initial connection line 3Vinit1 on the substrate extend along the second direction Y
  • the first power line VDD is used to provide a first power supply terminal
  • the data line Da is used to provide a data signal terminal.
  • the data line Da can be connected to the thirteenth active portion 613 through a via (black square) to connect the first electrode of the fourth transistor T4.
  • the first power line VDD can be connected to the fifteenth active portion 615 through a via to connect the first electrode of the fifth transistor.
  • the first initial connection line 3Vinit1 is connected to the first initial signal line Vinit1 intersecting with its orthographic projection on the substrate through a via to form a first initial signal line of a grid structure, thereby reducing the voltage drop of the signal on the first initial signal line.
  • the orthographic projection of the second bridge portion 32 on the substrate substrate may extend along the second direction Y, and the second bridge portion 32 may be connected to the first conductive portion 11 through a plurality of vias distributed in the second direction Y, and the second bridge portion 32 may be connected to the eleventh active portion 611 through the vias to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • An opening 231 may be formed on the third conductive portion 23, and the orthographic projection of the via connected between the first conductive portion 11 and the second bridge portion 32 on the substrate substrate may be located within the orthographic projection of the opening 231 on the substrate substrate, so that the via connected between the first conductive portion 11 and the second bridge portion 32 is insulated from the third conductive portion 23.
  • the orthographic projection of the fourth bridge portion 34 on the substrate substrate may extend along the second direction, and the fourth bridge portion 34 may be connected to the ninth active portion 69 through a plurality of vias distributed in the second direction to reduce the voltage difference of the second electrodes of the plurality of driving transistors T3.
  • the fifth bridge portion 35 may be connected to the eighth active portion 68 through a plurality of vias distributed in the second direction to reduce the voltage difference of the first electrodes of the plurality of driving transistors T3.
  • the sixth bridge portion 36 may be connected to the tenth active portion 610 through a via. To connect the second electrode of the sixth transistor T6.
  • the seventh bridge portion 37 can be connected to the first initial signal line Vinit1 and the fourteenth active portion through vias to connect the first initial signal terminal and the first electrode of the first transistor.
  • the seventh bridge portion 37 can also be connected to the fourth conductive portion 24 through vias.
  • the fourth conductive portion 24 has a stable voltage under the action of the first initial signal line Vinit1.
  • the fourth conductive portion 24 can stabilize the third sub-active portion 623 to improve the problem of leakage to the source and drain of the second transistor T2 caused by the voltage fluctuation of the third sub-active portion 623.
  • the eighth bridge portion 38 can be connected to the twelfth active portion 612 and the second initial signal line Vinit2 through vias to connect the first electrode and the second initial signal terminal of the seventh transistor T7.
  • the fourth conductive layer may include a ninth bridge portion 49 , which may be connected to the sixth bridge portion 36 through a via hole, and may be used to connect the first electrode of the light-emitting unit to connect the second electrode of the sixth transistor and the first electrode of the light-emitting unit.
  • Figure 12 is a structural layout of another exemplary embodiment of the display panel disclosed in the present invention
  • Figure 13 is a structural layout of the active layer in Figure 12
  • Figure 14 is a structural layout of the first conductive layer in Figure 12
  • Figure 15 is a structural layout of the second conductive layer in Figure 12
  • Figure 16 is a structural layout of the third conductive layer in Figure 12
  • Figure 17 is a structural layout of the fourth conductive layer in Figure 12
  • Figure 18 is a structural plate of the electrode layer and the pixel defining layer in Figure 12
  • Figure 19 is a structural layout of the active layer and the first conductive layer in Figure 12
  • Figure 20 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 12
  • Figure 21 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in Figure 12
  • Figure 22 is a structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth
  • the display panel may include a plurality of pixel units, and the plurality of pixel units may be arrayed in a first direction X and a second direction Y.
  • FIG. 12 shows a layout structure of a pixel unit, and each pixel unit may include a plurality of pixel driving circuits distributed in the first direction X.
  • each pixel unit may include three pixel driving circuits distributed in the first direction X.
  • the pixel driving circuit in FIG. 12 may include all structural features of the pixel driving circuit shown in FIG. 3 .
  • the third conductive portion 23 in the pixel driving circuit corresponding to the green light emitting unit is different from the third conductive portion 23 in the pixel driving circuit corresponding to the red light emitting unit and the blue light emitting unit.
  • the overlapping area of the third conductive portion 23 and the first conductive portion 11 is larger, thereby increasing the pixel driving circuit corresponding to the green light emitting unit.
  • the capacitance of the capacitor C in the driving circuit can improve the image quality of the green light-emitting unit.
  • the capacitors in the pixel driving circuits corresponding to the red light-emitting unit, the blue light-emitting unit, and the green light-emitting unit can be differentiated from the image quality requirements of the other color light-emitting units.
  • the differentiated setting method can be shown in FIG. 20, by adding a transverse connecting block to the third conductive portion 23 to increase the capacitance between the third conductive portion 23 and the first conductive portion 11.
  • the first initial connection line 3Vinit1 is correspondingly arranged to a column of pixel driving circuit groups, and the first initial connection line 3Vinit1 is connected to the first initial signal line Vinit1 intersecting with its orthographic projection on the substrate through a via.
  • the third conductive layer may also include a second initial connection line 3Vinit2, and the second initial connection line 3Vinit2 is correspondingly arranged to a column of pixel driving circuit groups.
  • the second initial connection line 3Vinit2 is connected to the second initial signal line intersecting with its orthographic projection on the substrate through a via.
  • the orthographic projection of the pixel driving circuit group on the substrate substrate is located between the orthographic projections of the first initial connection line 3Vinit1 and the second initial connection line 3Vinit2 corresponding to it on the substrate substrate.
  • the fourth conductive layer may also include a first power connection line 4VDD, and the orthographic projection of the first power connection line 4VDD on the substrate substrate is a ring; wherein the first power connection line 4VDD and the pixel driving circuit group are arranged correspondingly, and the orthographic projection of the first pixel driving circuit group on the substrate substrate is located within the orthographic projection of the first power connection line 4VDD corresponding to it on the substrate substrate.
  • the first power connection line 4VDD can be connected to the three first power lines VDD corresponding to the pixel driving circuit group through a via.
  • the ring refers to an image formed by lines connected end to end, and the ring can be rectangular, circular, triangular, polygonal, etc.
  • the third conductive layer also includes a power bridge line 3VDD, and the orthographic projection of the power bridge line 3VDD on the substrate extends along the second direction Y.
  • the orthographic projection of at least part of the structure of the power bridge line 3VDD on the substrate is located between the orthographic projections of two adjacent first power connection lines 4VDD on the substrate in the first direction X, and the power bridge line 3VDD is respectively connected to the two adjacent first power connection lines 4VDD through vias.
  • the orthographic projection of at least part of the structure of the first power connection line 4VDD on the substrate is located between the orthographic projections of two adjacent power bridge lines 3VDD on the substrate in the first direction, and the power bridge line is respectively connected to the two adjacent first power connection lines 4VDD through vias.
  • the power bridge line 3VDD can connect the first power connection lines 4VDD distributed in the first direction X.
  • the power bridge line 3VDD and the first power connection line 4VDD can form a grid structure of the first power lines VDD to reduce the voltage drop of the power signal on the first power lines.
  • the fourth conductive layer may further include a plurality of fifth conductive parts 45 .
  • the fifth conductive parts 45 are connected to the first power connection line 4VDD.
  • the fifth conductive parts 45 may further reduce the voltage drop of the first power line.
  • the electrode layer may include a plurality of electrode portions: a first electrode portion G, a second electrode portion B, and a third electrode portion R. Each electrode portion may be connected to the ninth bridge portion 49 through a via hole to connect the second electrode of the sixth transistor.
  • a plurality of pixel openings PH are formed on the pixel defining layer. The pixel openings PH are arranged corresponding to the electrode portions. The orthographic projection of the pixel openings PH on the substrate coincides with the orthographic projection of the electrode portions on the substrate.
  • the first electrode portion G may be used to form the electrode portion of the green light emitting unit in the display panel
  • the second electrode portion B may be used to form the electrode portion of the blue light emitting unit in the display panel
  • the third electrode portion R may be used to form the electrode portion of the red light emitting unit.
  • the electrode portion can also be arranged corresponding to the fifth conductive portion 45, and the orthographic projection of the electrode portion on the substrate substrate and the orthographic projection of the corresponding fifth conductive portion 45 on the substrate substrate at least partially overlap, and the overlapping area of the orthographic projection of the electrode portion on the substrate substrate and the orthographic projection of the corresponding fifth conductive portion 45 on the substrate substrate is S1, and the area of the orthographic projection of the electrode portion on the substrate substrate is S2, and S1/S2 is greater than or equal to 80%, for example, S1/S2 can be 80%, 90%, 100%.
  • This arrangement can improve the flatness of the electrode portion.
  • a plurality of openings 451 can be formed on the fifth conductive portion 45, and the openings 451 can release water vapor in the flat layer between the fourth conductive layer and the third conductive layer.
  • the fourth conductive layer may further include a second power connection line 4VSS, the second power connection line 4VSS and the first power connection line 4VDD are correspondingly arranged, the orthographic projection of the second power connection line 4VSS on the substrate is a ring, and the orthographic projection of the first power connection line 4VDD on the substrate is located within the orthographic projection of the corresponding second power connection line 4VSS on the substrate.
  • the electrode layer may further include a first electrode ring 5VSS, the orthographic projection of the first electrode ring 5VSS on the substrate is a ring, the first electrode ring 5VSS and the second power connection line 4VSS are correspondingly arranged, and connected to the corresponding second power connection line 4VSS.
  • the display panel may further include a common electrode layer, the common electrode layer is located on the electrode layer away from the substrate On one side of the base substrate, the common electrode layer can be used to form the second electrode of the light-emitting unit, and the second power connection line 4VSS can be connected to the common electrode layer through the first electrode ring 5VSS.
  • the second power connection line 4VSS and the first electrode ring 5VSS can reduce the voltage drop of the power signal on the common electrode layer.
  • FIG. 23 it is a partial cross-sectional view of the display panel shown in FIG. 12 cut along the dotted line BB.
  • the display panel may also include a first insulating layer 92, a second insulating layer 93, a dielectric layer 94, a passivation layer 95, a first flat layer 96, a second flat layer 97, and a pixel defining layer 98.
  • the substrate 91, the active layer, the first insulating layer 92, the first conductive layer, the second insulating layer 93, the second conductive layer, the dielectric layer 94, the third conductive layer, the passivation layer 95, the first flat layer 96, the fourth conductive layer, the second flat layer 97, the electrode layer, and the pixel defining layer 98 are stacked in sequence.
  • the first insulating layer 92 and the second insulating layer 93 may include one or more layers of silicon oxide and silicon nitride layers; the dielectric layer 94 may include a silicon nitride layer; the materials of the first flat layer 96 and the second flat layer 97 may be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and other materials.
  • the passivation layer 95 may be a silicon oxide layer.
  • the substrate 91 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.
  • the material of the first conductive layer and the second conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate, etc.
  • the material of the third conductive layer and the fourth conductive layer may include a metal material, for example, one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate, etc., or a titanium/aluminum/titanium laminate.
  • the electrode layer may include an indium tin oxide layer and a silver layer. The square resistance of any conductive layer in the first conductive layer and the second conductive layer may be greater than the square resistance of any conductive layer in the third conductive layer and the fourth conductive layer.
  • FIG. 24 it is a schematic diagram of the structure of another exemplary embodiment of the pixel driving circuit disclosed in the present invention.
  • the pixel driving circuit may include a plurality of sub-pixel driving circuits pix, each of the sub-pixel driving circuits pix includes at least one driving transistor T3, and each of the sub-pixel driving circuits is connected to the same light-emitting unit OLED, and the sub-pixel driving circuit is used to provide a driving current to the light-emitting unit OLED.
  • the sub-pixel driving circuit further includes: a data writing circuit 1, a compensation circuit 2, a light emitting control circuit 3, a first reset circuit 4, a second reset circuit 5, and a storage circuit 6.
  • the data writing circuit 1 is connected to the data signal terminal Da, the first electrode of the driving transistor T3, and the first
  • the gate drive signal terminal G1 is used to respond to the signal of the first gate drive signal terminal G1 to transmit the signal of the data signal terminal Da to the first electrode of the driving transistor T3
  • the compensation circuit 2 is connected to the gate of the driving transistor T3, the second electrode of the driving transistor T3, and the first gate drive signal terminal G1, and is used to respond to the signal of the first gate drive signal terminal G1 to connect the gate of the driving transistor T3 and the second electrode of the driving transistor T3
  • the light emitting control circuit 3 is connected to the first power supply terminal VDD, the first electrode of the driving transistor T3, the enable signal terminal EM, the second electrode of the driving transistor T3, and the first electrode of the light emitting unit OLED, and is used to respond
  • the signal of the signal terminal EM is used to connect the second electrode of the driving transistor T3 and the first electrode of the light-emitting unit OLED;
  • the first reset circuit 4 is connected to the first initial signal terminal Vinit1, the first reset signal terminal Re1, and the gate of the driving transistor T3, and is used to respond to the signal of the first reset signal terminal Re1 to transmit the signal of the first initial signal terminal Vinit1 to the gate of the driving transistor T3;
  • the second reset circuit 5 is connected to the second initial signal terminal Vinit2, the second reset signal terminal Re2, and the first electrode of the light-emitting unit OLED, and is used to respond to the signal of the second reset signal terminal Re2 to transmit the signal of the second initial signal terminal Vinit2 to the first electrode of the light-emitting unit OLED;
  • the storage circuit 6 is connected between the gate of the driving transistor T3 and the first power supply terminal VDD.
  • the data writing circuit 1 includes: a fourth transistor T4, the first electrode of the fourth transistor T4 is connected to the data signal terminal Da, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1;
  • the compensation circuit 2 includes: a second transistor T2, the first electrode of the second transistor T2 is connected to the gate of the driving transistor T3, the second electrode is connected to the second electrode of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1;
  • the light emitting control circuit 3 includes: a fifth transistor T5 and a sixth transistor T6, the first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM;
  • the first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, the second electrode is connected to the first electrode of the light emitting unit OLED, and the gate is connected to the enable signal terminal EM;
  • the timing of each control signal in the pixel driving circuit shown in FIG24 can also be as shown in FIG2, wherein G1 represents the timing of the signal at the first gate driving signal terminal G1, Re1 represents the timing of the signal at the first reset signal terminal Re1, Re2 represents the timing of the signal at the second reset signal terminal Re2, and EM represents the timing of the signal at the enable signal terminal EM.
  • the driving method of the pixel driving circuit can also include a first reset stage t1, a data writing stage t2, a second reset stage t3, and a light emitting stage t4.
  • the first reset stage t1 the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 in each sub-pixel driving circuit is turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the gate of the driving transistor in each sub-pixel driving circuit.
  • the data writing stage t2 the first gate drive signal terminal G1 outputs a low-level signal, the fourth transistor T4 and the second transistor T2 in each sub-pixel drive circuit are turned on, and the data signal terminal Da outputs a data signal to write a voltage Vdata+Vth to the gate of the drive transistor in each sub-pixel drive circuit, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the drive transistor T3.
  • the second reset stage t3 the second reset signal terminal outputs a low-level signal
  • the seventh transistor in each sub-pixel drive circuit is turned on
  • the second initial signal terminal Vinit2 inputs a second initial signal to the second electrode of the sixth transistor T6 in each sub-pixel drive circuit.
  • the enable signal terminal EM outputs a low-level signal
  • the sixth transistor T6 and the fifth transistor T5 in each sub-pixel drive circuit are turned on, and multiple drive transistors T3 drive the light-emitting unit to emit light under the voltage Vdata+Vth at their gates.
  • the pixel drive circuit can also have other driving methods, for example, the seventh transistor can be turned on in the data writing stage t2.
  • a single sub-pixel driving circuit may also include a plurality of driving transistors connected in parallel.
  • This exemplary embodiment also provides another display panel, which may include a base substrate, an active layer, a first conductive layer, a second conductive layer, a third conductive layer, and a fourth conductive layer stacked in sequence, wherein an insulating layer may be provided between adjacent conductive layers.
  • Figure 25 is a structural layout diagram of an exemplary embodiment of the display panel of the present disclosure
  • Figure 26 is a structural layout diagram of the active layer in Figure 25
  • Figure 27 is a first conductive layer in Figure 25.
  • FIG28 is a structural layout of the second conductive layer in FIG25
  • FIG29 is a structural layout of the third conductive layer in FIG25
  • FIG30 is a structural layout of the fourth conductive layer in FIG25
  • FIG31 is a structural layout of the active layer and the first conductive layer in FIG25
  • FIG32 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in FIG25
  • FIG33 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG25 .
  • the display panel may include a plurality of pixel driving circuits, and the structure of the pixel driving circuit in the display panel shown in FIG25 and the structure of the pixel driving circuit shown in FIG24 only differ in that the pixel driving circuit in the display panel shown in FIG25 includes 9 sub-pixel driving circuits distributed in a 3 by 3 array.
  • the active layer may include a first active portion 61, a second active portion 62, a plurality of third active portions 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, a seventh active portion 67, a tenth active portion 610, an eleventh active portion 611, a twelfth active portion 612, a thirteenth active portion 613, a fourteenth active portion 614, and a fifteenth active portion 615.
  • the first active portion 61 is used to form the channel region of the first transistor T1
  • the second active portion 62 is used to form the channel region of the second transistor T2
  • the second transistor T2 is a dual-channel structure
  • the second active portion 62 includes a first sub-active portion 621 and a second sub-active portion 622
  • the first sub-active portion 621 is used to form the first channel of the second transistor
  • the second sub-active portion 622 is used to form the second channel of the second transistor T2
  • the active layer also includes a third sub-active portion 623, the third sub-active portion 623 is connected between the first sub-active portion 621 and the second sub-active portion 622
  • the third active portion 63 can be used to form the channel region of the driving transistor T3
  • the fourth active portion 64 can be used to form the channel region of the fourth transistor T4
  • the fifth active portion 65 can be used
  • the sixth active portion 66 can be used to form the channel region of the sixth transistor T5
  • the seventh active portion 67
  • the active layer may be formed of polysilicon material, and accordingly, the first transistor T1 , the second transistor T2 , the driving transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 may be P-type low-temperature polysilicon thin film transistors.
  • the first conductive layer may include: a plurality of first conductive portions 11, a first gate line G1, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2.
  • the orthographic projection of the first gate line G1 on the substrate, the orthographic projection of the enable signal line EM on the substrate, the orthographic projection of the first reset signal line Re1 on the substrate, and the orthographic projection of the second reset signal line Re2 on the substrate may all extend along the first direction X, and the first direction X and the second direction Y may intersect, for example, the first direction X may be a row direction, and the second direction Y may be a column direction.
  • the first gate line G1 may be used to provide a first gate drive signal terminal; the enable signal line EM may be used to provide an enable signal terminal; the first reset signal line Re1 may be used to provide a first reset signal terminal; and the second reset signal line Re2 may be used to provide a second reset signal terminal.
  • the orthographic projection of the first gate line G1 on the substrate covers the orthographic projections of the second active portion 62 and the fourth active portion 64 on the substrate, and a partial structure of the first gate line G1 is used to form the gate of the second transistor T2 and the gate of the fourth transistor, respectively.
  • the orthographic projection of the enable signal line EM on the substrate covers the orthographic projection of the fifth active portion 65 on the substrate and the orthographic projection of the sixth active portion 66 on the substrate, and the partial structure of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively.
  • the orthographic projection of the first reset signal line Re1 on the substrate covers the orthographic projection of the first active portion 61 on the substrate, and the partial structure of the first reset signal line Re1 is used to form the gate of the first transistor T1.
  • the orthographic projection of the second reset signal line Re2 on the substrate can cover the orthographic projection of the seventh active portion 67 on the substrate, and the partial structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7.
  • the first conductive portion 11 is arranged corresponding to the sub-pixel driving circuit, and the orthographic projection of the first conductive portion 11 on the substrate covers the orthographic projection of the third active portion 63 in the corresponding sub-pixel driving circuit on the substrate, and the first conductive portion 11 can be used to form the gates of multiple driving transistors T3 and the first electrode of the capacitor C.
  • the first reset signal line Re1 in the pixel driving circuit of the current row can be reused as the second reset signal line Re2 in the pixel driving circuit of the adjacent previous row. This setting can improve the integration of the pixel driving circuit to reduce the layout area of the pixel driving circuit.
  • the display panel can use the first conductive layer as a mask to perform conductor processing on the active layer, that is, the area covered by the first conductive layer in the active layer can form a channel region of the transistor, and the area not covered by the first conductive layer forms a conductor structure.
  • the second conductive layer may include: a first initial signal line Vinit1, a second initial signal line Vinit2 and a third conductive portion 23.
  • the first initial signal line The orthographic projection of Vinit1 on the substrate and the orthographic projection of the second initial signal line Vinit2 on the substrate extend along the first direction X, the first initial signal line Vinit1 is used to provide a first initial signal terminal, and the second initial signal line Vinit2 is used to provide a second initial signal terminal.
  • the orthographic projection of the second initial signal line Vinit2 in the adjacent previous row of sub-pixel driving circuits on the substrate is located between the orthographic projection of the first reset signal line Re1 in the sub-pixel driving circuit of this row on the substrate and the orthographic projection of the first gate line G1 in the sub-pixel driving circuit of this row on the substrate.
  • the orthographic projection of the third conductive portion 23 on the substrate at least partially overlaps with the orthographic projection of the first conductive portion 11 on the substrate, and the third conductive portion 23 is used to form the second electrode of the capacitor C.
  • the second conductive layer may further include: a first protrusion 21 and a second protrusion 22, wherein the first protrusion 21 is connected to the second initial signal line Vinit2, the orthographic projection of the first protrusion 21 on the substrate extends along the second direction Y, and the orthographic projection of the first protrusion 21 on the substrate and the orthographic projection of the eleventh active part 611 on the substrate overlap at least in part.
  • the first protrusion 21 can stabilize the voltage of the eleventh active part 611, thereby reducing the voltage fluctuation of the gate of the driving transistor.
  • the second protrusion 22 is connected to the second initial signal line Vinit2, the orthographic projection of the second protrusion 22 on the substrate extends along the second direction Y, and the orthographic projection of the second protrusion 22 on the substrate and the orthographic projection of the third sub-active part 623 on the substrate overlap at least in part.
  • the second protrusion 22 can stabilize the voltage of the third sub-active part 623, thereby improving the problem of leakage to the source and drain of the second transistor T2 due to the voltage fluctuation of the third sub-active part 623.
  • the third conductive layer may include a data line Da, a second bridge portion 32, a sixth bridge portion 36, a seventh bridge portion 37, an eighth bridge portion 38, and a tenth bridge portion 310.
  • the orthographic projection of the data line Da on the substrate extends along the second direction Y, and the data line Da is used to provide a data signal terminal.
  • the data line Da may be connected to the thirteenth active portion 613 through a via (black square) to connect the first electrode of the fourth transistor T4.
  • the second bridge portion 32 may be connected to the first conductive portion 11 and the eleventh active portion 611 through vias to connect the gate of the driving transistor T3 and the second electrode of the first transistor T1 and the first electrode of the second transistor T2.
  • An opening 231 may be formed on the third conductive portion 23, and the orthographic projection of the via connected between the first conductive portion 11 and the second bridge portion 32 on the substrate may be located within the orthographic projection of the opening 231 on the substrate, so that the via connected between the first conductive portion 11 and the second bridge portion 32 and the third conductive portion 23 are insulated.
  • the sixth bridge portion 36 may be connected to the tenth active portion 610 through a via hole to connect the second electrode of the sixth transistor T6.
  • the seventh bridge portion 37 may be connected to the first initial signal line Vinit1 and the fourteenth active portion through via holes to connect the first electrode and the first initial signal end of the first transistor.
  • the eighth bridge portion 38 may be connected to the twelfth active portion 612 and the second initial signal line Vinit2 through via holes to connect the first electrode and the second initial signal end of the seventh transistor T7.
  • the tenth bridge portion 310 may be connected to the third conductive portion 23 and the fifteenth active portion 615 through via holes to connect the second electrode of the capacitor and the first electrode of the fifth transistor.
  • the fourth conductive layer may include a first bridge portion 41 and a first power line sub-portion VDD.
  • the first bridge portion 41 may be connected to all the sixth bridge portions 36 in the same pixel driving circuit through a via hole.
  • the first bridge portion 41 may be used to connect the first electrode of the light-emitting unit to connect the second electrode of the sixth transistor and the first electrode of the light-emitting unit.
  • the first power line sub-portion VDD includes a portion whose orthographic projection on the substrate extends along the second direction Y and a portion extending along the first direction X.
  • the first power line sub-portion VDD may be used to provide a first power supply terminal.
  • the first power line sub-portion VDD may be connected to the tenth bridge portion 310 through a via hole to connect the first power supply terminal and the first electrode of the fifth transistor and the second electrode of the capacitor.
  • the first power line sub-portion VDD includes a second conductive portion 42.
  • the second conductive portion 42 may be arranged corresponding to the sub-pixel driving circuit.
  • the orthographic projection of the second conductive portion 42 on the substrate and the orthographic projection of the second bridge portion 32 in the corresponding sub-pixel driving circuit on the substrate at least partially overlap, and the second conductive portion 42 is connected to the tenth bridge portion 310 in the corresponding sub-pixel driving circuit through a via hole.
  • the second conductive portion 42 can shield the noise interference of other signals on the second bridge portion 32, so as to improve the stability of the gate voltage of the driving transistor.
  • the second conductive portions 42 distributed in the first direction X can be connected, and the connected second conductive portions 42 can reduce the voltage of the first power line sub-portion VDD, thereby reducing the voltage drop of the power signal on the first power line sub-portion VDD.
  • Figure 34 is a structural layout of another exemplary embodiment of the display panel disclosed in the present invention
  • Figure 35 is a structural layout of the active layer in Figure 34
  • Figure 36 is a structural layout of the first conductive layer in Figure 34
  • Figure 37 is a structural layout of the second conductive layer in Figure 34
  • Figure 38 is a structural layout of the third conductive layer in Figure 34
  • Figure 39 is a structural layout of the fourth conductive layer in Figure 34
  • Figure 40 is a structural plate of the electrode layer and the pixel defining layer in Figure 34
  • Figure 41 is a structural layout of the active layer and the first conductive layer in Figure 34
  • Figure 42 is a structural layout of the active layer, the first conductive layer, and the second conductive layer in Figure 34.
  • FIG43 is a structural layout of the active layer, the first conductive layer, the second conductive layer, and the third conductive layer in FIG34
  • FIG44 is a structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer in FIG34 .
  • the display panel may include a plurality of pixel units, and the plurality of pixel units may be arrayed in a first direction X and a second direction Y.
  • FIG. 34 shows a layout structure of a pixel unit, and each pixel unit may include a plurality of pixel driving circuits distributed in the first direction X.
  • each pixel unit may include three pixel driving circuits distributed in the first direction X.
  • the pixel driving circuit in FIG. 34 may include all structural features of the pixel driving circuit shown in FIG. 25 .
  • the multiple first reset signal lines include a first long reset signal line LRe1 and a first short reset signal line SRe1, the first long reset signal line LRe1 is arranged corresponding to the sub-pixel driving circuit located in the same row, the first long reset signal line LRe1 is connected to the corresponding sub-pixel driving circuit, the first short reset signal line SRe1 is arranged corresponding to the sub-pixel driving circuit in the same row of the pixel driving circuit group, the first short reset signal line SRe1 is connected to the corresponding sub-pixel driving circuit, and the multiple first short reset signal lines SRe1 corresponding to the sub-pixel driving circuit in the same row are spaced apart in the row direction with their orthographic projections on the substrate.
  • the multiple first gate lines include a first long gate line LG1 and a first short gate line SG1, the first long gate line LG1 is arranged corresponding to the sub-pixel driving circuit located in the same row, the first long gate line LG1 is connected to the corresponding sub-pixel driving circuit, the first short gate line SG1 is arranged corresponding to the sub-pixel driving circuit in the same row of the pixel driving circuit group, the first short gate line SG1 is connected to the corresponding sub-pixel driving circuit, and the orthographic projections of the multiple first short gate lines SG1 corresponding to the sub-pixel driving circuit in the same row on the substrate are arranged at intervals in the row direction.
  • the plurality of enable signal lines EM include a long enable signal line LEM and a short enable signal line SEM, the long enable signal line LEM is arranged corresponding to the sub-pixel drive circuit located in the same row, the long enable signal line LEM is connected to the sub-pixel drive circuit corresponding thereto, the short enable signal line SEM is arranged corresponding to the sub-pixel drive circuit in the same row in the pixel drive circuit group, the short enable signal line SEM is connected to the sub-pixel drive circuit corresponding thereto, and the orthographic projections of the plurality of short enable signal lines SEM corresponding to the sub-pixel drive circuit in the same row on the substrate are arranged at intervals in the row direction.
  • the third conductive layer also includes a first connecting line 311, a second connecting line 312, a third connecting line 313; wherein, the orthographic projections of the first connecting line 311, the second connecting line 312, and the third connecting line 313 on the substrate extend along the second direction Y, the first connecting line 311 is connected to the first long reset signal line LRe1 and the first short reset signal line SRe1 through vias, the second connecting line 312 is connected to the first long gate line LG1 and the first short gate line SG1 through vias, and the third connecting line 313 is connected to the long enable signal line LEM and the short enable signal line SEM through vias.
  • the multiple first initial signal lines include a first long initial signal line LVinit1 and a first short initial signal line SVinit1, the first long initial signal line LVinit1 is arranged corresponding to the sub-pixel driving circuit located in the same row, the first long initial signal line LVinit1 is connected to the corresponding sub-pixel driving circuit, the first short initial signal line SVinit1 is arranged corresponding to the sub-pixel driving circuit in the same row in the pixel driving circuit group, the first short initial signal line SVinit1 is connected to the corresponding sub-pixel driving circuit, and the multiple first short initial signal lines SVinit1 corresponding to the sub-pixel driving circuit in the same row are spaced apart in the row direction with their orthographic projections on the substrate.
  • the plurality of second initial signal lines include a second long initial signal line LVinit2 and a second short initial signal line SVinit2, the second long initial signal line LVinit2 is arranged correspondingly to the sub-pixel driving circuit located in the same row, the second long initial signal line LVinit2 is connected to the corresponding sub-pixel driving circuit, the second short initial signal line SVinit2 is arranged correspondingly to the sub-pixel driving circuit in the same row in the pixel driving circuit group, the second short initial signal line SVinit2 is connected to the corresponding sub-pixel driving circuit, and the orthographic projections of the plurality of second short initial signal lines SVinit2 corresponding to the sub-pixel driving circuit in the same row on the substrate are arranged at intervals in the row direction.
  • the third conductive layer also includes a fourth connecting line 314 and a fifth connecting line 315, the fourth connecting line 314 is connected to the first long initial signal line LVinit1 and the first short initial signal line SVinit1 through vias, respectively, and the fifth connecting line 315 is connected to the second long initial signal line LVinit2 and the second short initial signal line Svinit2 through vias, respectively.
  • the third conductive layer may also include a first initial connection line 3Vinit1 and a second initial connection line 3Vinit2.
  • the orthographic projections of the first initial connection line 3Vinit1 and the second initial connection line 3Vinit2 on the substrate extend along the second direction Y.
  • the first initial connection line 3Vinit1 is correspondingly arranged with a column of pixel driving circuit groups, and the first initial connection line 3Vinit1 is connected to the pixel driving circuit group through a via hole.
  • the first initial connection line intersecting with its orthographic projection on the substrate, the first initial connection line 3Vinit1 and the first initial connection line form a grid structure to reduce the voltage drop of the signal on the first initial signal line.
  • the second initial connection line 3Vinit2 is arranged corresponding to a column of pixel driving circuit groups, the second initial connection line 3Vinit2 is connected to the second initial connection line intersecting with its orthographic projection on the substrate through a via hole, and the second initial connection line 3Vinit2 and the second initial connection line form a grid structure to reduce the voltage drop of the signal on the second initial signal line.
  • the orthographic projection of the pixel driving circuit group on the substrate substrate is located between the orthographic projections of the first initial connection line 3Vinit1 and the second initial connection line 3Vinit2 corresponding to it on the substrate substrate.
  • the fourth conductive layer may further include a first power connection line 4VDD, the orthographic projection of the first power connection line 4VDD on the substrate substrate is a ring; wherein the first power connection line 4VDD and the pixel driving circuit group are arranged correspondingly, and the orthographic projection of the pixel driving circuit group on the substrate substrate is located within the orthographic projection of the first power connection line 4VDD corresponding to it on the substrate substrate.
  • the first power connection line 4VDD may be connected to the first power line sub-portion VDD corresponding to the pixel driving circuit group through a via.
  • the ring refers to an image formed by lines connected end to end, and the ring may be rectangular, circular, triangular, polygonal, etc.
  • the fourth conductive layer may further include a first connecting portion 43, the orthographic projection of the first connecting portion 43 on the substrate substrate extends along the second direction Y, and the first connecting portion 43 is connected between the second conductive portion 42 and the first power connection line 4VDD adjacent in the second direction.
  • the first connecting portion 43 may further reduce the voltage drop of the power signal on the first power line VDD.
  • the third conductive layer may further include: a plurality of third bridge portions 33, wherein at least a portion of the third bridge portion 33 has an orthographic projection on the substrate substrate between two adjacent first power connection lines 4VDD in the second direction Y, and the third bridge portion 33 may be connected to two adjacent first power connection lines through vias.
  • the third bridge portion 33 may be connected to the first power connection lines 4VDD distributed in the second direction Y.
  • the third conductive layer further comprises a power bridge wire 3VDD, the orthographic projection of the power bridge wire 3VDD on the substrate extends along the second direction Y.
  • the orthographic projection of at least a part of the structure of the power bridge wire 3VDD on the substrate is located between the orthographic projections of two adjacent first power connection lines 4VDD on the substrate in the first direction X, and the power bridge wire 3VDD is respectively connected to the two adjacent first power connection lines 4VDD through vias.
  • the power bridge line 3VDD can connect the first power connection lines 4VDD distributed in the first direction X.
  • the power bridge line 3VDD and the first power connection line 4VDD can form a grid structure of the first power lines VDD to reduce the voltage drop of the power signal on the first power lines.
  • the electrode layer may include a plurality of electrode portions: a first electrode portion G, a second electrode portion B, and a third electrode portion R. Each electrode portion may be connected to the first bridge portion 41 through a via hole to connect the second electrode of the sixth transistor.
  • a plurality of pixel openings PH are formed on the pixel defining layer. The pixel openings PH are arranged corresponding to the electrode portions. The orthographic projection of the pixel openings PH on the substrate coincides with the orthographic projection of the electrode portions on the substrate.
  • the first electrode portion G may be used to form the electrode portion of the green light-emitting unit in the display panel
  • the second electrode portion B may be used to form the electrode portion of the blue light-emitting unit in the display panel
  • the third electrode portion R may be used to form the electrode portion of the red light-emitting unit.
  • the fourth conductive layer may further include a second power connection line 4VSS, the second power connection line 4VSS and the first power connection line 4VDD are correspondingly arranged, the orthographic projection of the second power connection line 4VSS on the substrate is a ring, and the orthographic projection of the first power connection line 4VDD on the substrate is located within the orthographic projection of the corresponding second power connection line 4VSS on the substrate.
  • the electrode layer may further include a first electrode ring 5VSS, the orthographic projection of the first electrode ring 5VSS on the substrate is a ring, the first electrode ring 5VSS and the second power connection line 4VSS are correspondingly arranged, and connected to the corresponding second power connection line 4VSS.
  • the display panel may further include a common electrode layer, the common electrode layer is located on the side of the electrode layer away from the substrate, the common electrode layer can be used to form the second electrode of the light-emitting unit, and the second power connection line 4VSS can be connected to the common electrode layer through the first electrode ring 5VSS.
  • the second power connection line 4VSS and the first electrode ring 5VSS can reduce the voltage drop of the power signal on the common electrode layer.
  • the display panel may also include a first insulating layer 92, a second insulating layer 93, a dielectric layer 94, a passivation layer 95, a first flat layer 96, and a second flat layer 97.
  • the base substrate 91, the active layer, the first insulating layer 92, the first conductive layer, the second insulating layer 93, the second conductive layer, the dielectric layer 94, the third conductive layer, the passivation layer 95, the first flat layer 96, the fourth conductive layer, the second flat layer 97, and the electrode layer are stacked in sequence.
  • the first insulating layer 92 and the second insulating layer 93 may include one or more layers of silicon oxide and silicon nitride layers; the dielectric layer 94 may include a silicon nitride layer; the first flat layer 96,
  • the material of the second planar layer 97 may be an organic material, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG) and the like.
  • the passivation layer 95 may be a silicon oxide layer.
  • the substrate 91 may include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence, and the barrier layer may be an inorganic material.
  • the material of the first conductive layer and the second conductive layer may be one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate, etc.
  • the material of the third conductive layer and the fourth conductive layer may include a metal material, such as one of molybdenum, aluminum, copper, titanium, niobium or an alloy, or a molybdenum/titanium alloy or a laminate, etc., or a titanium/aluminum/titanium laminate.
  • the electrode layer may include an indium tin oxide layer and a silver layer. The square resistance of any one of the first conductive layer and the second conductive layer may be greater than the square resistance of any one of the third conductive layer and the fourth conductive layer.
  • the display area AA of the display panel may include a normal display area A1, a compression area A2, and an integrated area A3, wherein the compression area A2 is located on one side of the normal display area A1 in the first direction X, and the integrated area A3 is located on the side of the compression area A2 away from the normal display area A1.
  • the pixel unit located in the normal display area A1 is a first pixel unit
  • the pixel unit located in the compression area A2 is a second pixel unit.
  • the pixel driving circuit in the first pixel unit forms a first pixel driving circuit group, and the pixel driving circuit in the second pixel unit forms a second pixel driving circuit group.
  • the layout structure of the first pixel unit may be as shown in FIG. 12 or FIG. 34.
  • the compression area A2 in the display panel may be provided with one or more columns of pixel units.
  • the integrated area A3 may be used to integrate the gate driving circuit GOA.
  • Figure 47 is the structural layout of the second pixel unit on the right side of Figure 46
  • Figure 48 is the structural layout of the active layer in Figure 47
  • Figure 49 is the structural layout of the first conductive layer in Figure 47
  • Figure 50 is the structural layout of the second conductive layer in Figure 47
  • Figure 51 is the structural layout of the third conductive layer in Figure 47
  • Figure 52 is the structural layout of the fourth conductive layer in Figure 47
  • Figure 53 is the structural plate of the electrode layer and the pixel defining layer in Figure 47
  • Figure 54 is the structural layout of the active layer and the first conductive layer in Figure 47
  • Figure 55 is the structural layout of the active layer, the first conductive layer and the second conductive layer in Figure 47
  • Figure 56 is the structural layout of the active layer, the first conductive layer, the second conductive layer and the third conductive layer in Figure 47
  • Figure 57 is the structural layout of the active layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer in Figure 47.
  • the second pixel unit is mainly different from the first pixel unit in that:
  • the first initial connection line and the second initial connection line are not provided in the second pixel unit.
  • the side of the second pixel unit close to the integrated area A3 is not provided with a power bridge line 3VDD.
  • the first power connection line 4VDD is replaced by a third power connection line 43VDD.
  • the third power connection line 43VDD is opened at one side close to the integrated area A3.
  • the second power connection line 4VSS is replaced by a fourth power connection line 44VSS.
  • the fourth power connection line 44VSS is opened at both sides in the first direction X.
  • the third power connection line 43VDD includes a first side 4VDD1, the orthographic projection of the first side 4VDD1 on the substrate extends along the second direction Y and is located on the side of the second pixel driving circuit group corresponding to it in the first direction X, wherein the distance between the orthographic projection of the first power connection line 4VDD on the substrate and the orthographic projection of the first pixel driving circuit group on the substrate in the first pixel unit in the first direction X is greater than the distance between the orthographic projection of the first side 4VDD1 on the substrate and the orthographic projection of the second pixel driving circuit group on the substrate in the first direction X.
  • the first electrode ring 5VSS is replaced by a second electrode line 52VSS, and the second electrode line 52VSS is opened at one side close to the integrated area A3.
  • the second electrode line 52VSS includes a second side 5VSS2, and the orthographic projection of at least a part of the structure of the second side 5VSS2 on the substrate is located on a side where the orthographic projection of the first side 4VDD1 on the substrate is away from the orthographic projection of the second pixel driving circuit group on the substrate; wherein the distance between the orthographic projection of the first side 4VDD1 on the substrate and the orthographic projection of the second side 5VSS2 on the substrate in the first direction X is less than the distance between the orthographic projection of the first electrode ring 5VSS on the substrate and the orthographic projection of the first power connection line 4VDD on the substrate in the first direction X. As shown in FIG.
  • the orthographic projection of the first side 4VDD1 on the substrate and the orthographic projection of the second side 5VSS2 on the substrate intersect, and the distance between the orthographic projection of the first side 4VDD1 on the substrate and the orthographic projection of the second side 5VSS2 on the substrate in the first direction is 0.
  • the above-mentioned different settings can reduce the size of the pixel circuit layer (including the active layer, the first conductive layer, the second conductive layer, the third conductive layer, and the fourth conductive layer) in the second pixel unit in the first direction, thereby leaving space for the integrated area A3 for setting the gate drive circuit GOA.
  • the integrated area A3 is provided with a light-emitting unit.
  • the layout structure of the second pixel unit on the left side of the display panel shown in FIG46 can be the same as that of the pixel unit on the right side.
  • the layout structure of the elements is the same or similar.
  • the black squares drawn on the side of the third conductive layer away from the substrate substrate indicate that the third conductive layer is connected to the via holes of other layers facing the substrate substrate side; the black squares drawn on the side of the fourth conductive layer away from the substrate substrate indicate that the fourth conductive layer is connected to the via holes of other layers facing the substrate substrate side; the black squares drawn on the side of the electrode layer away from the substrate substrate indicate that the electrode layer is connected to the via holes of other layers facing the substrate substrate side.
  • the black squares indicate the positions of the via holes, and different via holes represented by black squares at different positions may pass through different insulating layers.
  • the proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited to this.
  • the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs.
  • the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the figure.
  • the drawings described in the present disclosure are only structural schematic diagrams.
  • the first, second and other qualifiers are only used to define different structural names, and they do not have a specific order and quantity.
  • the positive projection of a certain structure on the substrate substrate extends in a certain direction, which can be understood as the positive projection of the structure on the substrate substrate extending straight or bending along the direction.
  • a transistor refers to an element including at least three terminals: a gate, a drain and a source.
  • the transistor has a channel region between the drain (drain electrode terminal, a drain region or a drain electrode) and the source (source electrode terminal, a source region or a source electrode), and the current can flow through the drain, the channel region and the source.
  • the channel region refers to the area where the current mainly flows.
  • the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode.
  • the gate electrode may also be referred to as a control electrode.
  • This exemplary embodiment also provides a display device, which includes the above-mentioned display panel.
  • the display device can be a display device such as a mobile phone, a tablet computer, a television, etc.

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Abstract

一种像素驱动电路、显示面板及显示装置，像素驱动电路包括：多个驱动晶体管(T3)，每个所述驱动晶体管(T3)的第二极均连接同一发光单元(OLED)的第一电极，每个所述驱动晶体管(T3)用于根据其栅极电压向所述发光单元(OLED)输入驱动电流。

Description

像素驱动电路、显示面板及显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素驱动电路、显示面板及显示装置。
背景技术
相关技术中，像素驱动电路通常包括有驱动晶体管，驱动晶体管根据其栅极的数据信号向发光单元提供驱动电流，然而，Data Range(数据信号的电压范围)受限于显示面板的芯片，从而导致像素驱动电路无法输出较大的驱动电流。
需要说明的是，在上述背景技术部分公开的信息仅用于加强对本公开的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。
发明内容
根据本公开的一个方面，提供一种像素驱动电路，其中，所述像素驱动电路包括：多个驱动晶体管，每个所述驱动晶体管的第二极均连接同一发光单元的第一电极，每个所述驱动晶体管用于根据其栅极电压向所述发光单元输入驱动电流。
本公开一种示例性实施例中，每个所述驱动晶体管的栅极均连接第一节点，每个所述驱动晶体管的第一极均连接第一电源端。
本公开一种示例性实施例中，所述像素驱动电路还包括：数据写入电路、补偿电路、发光控制电路、第一复位电路、第二复位电路、存储电路。数据写入电路连接数据信号端、每个所述驱动晶体管的第一极、第一栅极驱动信号端，用于响应所述第一栅极驱动信号端的信号以将所述数据信号端的信号传输到每个所述驱动晶体管的第一极；补偿电路连接所述第一节点、每个所述驱动晶体管的第二极、第二栅极驱动信号端，用于响应所述第二栅极驱动信号端的信号以连通所述第一节点和每个所 述驱动晶体管的第二极；发光控制电路连接所述第一电源端、每个所述驱动晶体管的第一极、使能信号端、每个所述驱动晶体管的第二极、发光单元的第一电极，用于响应所述使能信号端的信号以连通所述第一电源端和每个所述驱动晶体管的第一极，以及用于响应所述使能信号端的信号以连通每个所述驱动晶体管的第二极和所述发光单元的第一电极；第一复位电路连接第一初始信号端、第一复位信号端、所述第一节点，用于响应所述第一复位信号端的信号以将所述第一初始信号端的信号传输到所述第一节点；第二复位电路连接第二初始信号端、第二复位信号端、发光单元的第一电极，用于响应所述第二复位信号端的信号以将所述第二初始信号端的信号传输到所述发光单元的第一电极；存储电路连接于所述第一节点和所述第一电源端之间。
本公开一种示例性实施例中，所述数据写入电路包括：第四晶体管，所述第四晶体管的第一极连接所述数据信号端，第二极连接每个所述驱动晶体管的第一极，栅极连接第一栅极驱动信号端；所述补偿电路包括:第二晶体管，所述第二晶体管的第一极连接所述第一节点，第二极连接每个所述驱动晶体管的第二极，栅极连接所述第二栅极驱动信号端；所述发光控制电路包括：第五晶体管、第六晶体管，第五晶体管的第一极连接所述第一电源端，第二极连接每个所述驱动晶体管的第一极，栅极连接所述使能信号端；第六晶体管的第一极连接每个所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极，栅极连接所述使能信号端；所述第一复位电路包括：第一晶体管，第一晶体管的第一极连接所述第一初始信号端，第二极连接所述第一节点，栅极连接所述第一复位信号端；所述第二复位电路包括：第七晶体管，第七晶体管的第一极连接第二初始信号端，第二极连接所述发光单元的第一电极，栅极连接所述第二复位信号端；所述存储电路包括：电容，电容的第一电极连接所述第一节点，第二电极连接所述第一电源端。
本公开一种示例性实施例中，所述像素驱动电路包括多个子像素驱动电路，每个所述子像素驱动电路均包括至少一个所述驱动晶体管，且每个所述子像素驱动电路连接同一所述发光单元，所述子像素驱动电路用于向所述发光单元提供驱动电流。
本公开一种示例性实施例中，所述子像素驱动电路还包括：数据写入电路、补偿电路、发光控制电路、第一复位电路、第二复位电路、存储电路。数据写入电路连接数据信号端、所述驱动晶体管的第一极、第一栅极驱动信号端，用于响应所述第一栅极驱动信号端的信号以将所述数据信号端的信号传输到所述驱动晶体管的第一极；补偿电路连接所述驱动晶体管的栅极、所述驱动晶体管的第二极、第二栅极驱动信号端，用于响应所述第二栅极驱动信号端的信号以连通所述所述驱动晶体管的栅极和所述驱动晶体管的第二极；发光控制电路连接第一电源端、所述驱动晶体管的第一极、使能信号端、所述驱动晶体管的第二极、发光单元的第一电极，用于响应所述使能信号端的信号以连通所述第一电源端和所述驱动晶体管的第一极，以及用于响应所述使能信号端的信号以连通所述驱动晶体管的第二极和所述发光单元的第一电极；第一复位电路连接第一初始信号端、第一复位信号端、所述驱动晶体管的栅极，用于响应所述第一复位信号端的信号以将所述第一初始信号端的信号传输到所述驱动晶体管的栅极；第二复位电路连接第二初始信号端、第二复位信号端、发光单元的第一电极，用于响应所述第二复位信号端的信号以将所述第二初始信号端的信号传输到所述发光单元的第一电极；存储电路连接于所述驱动晶体管的栅极和所述第一电源端之间。
本公开一种示例性实施例中，所述数据写入电路包括：第四晶体管，第四晶体管的第一极连接所述数据信号端，第二极连接所述驱动晶体管的第一极，栅极连接第一栅极驱动信号端；所述补偿电路包括:第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，栅极连接所述第二栅极驱动信号端；所述发光控制电路包括：第五晶体管、第六晶体管，第五晶体管的第一极连接所述第一电源端，第二极连接所述驱动晶体管的第一极，栅极连接所述使能信号端；第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极，栅极连接所述使能信号端；所述第一复位电路包括：第一晶体管，第一晶体管的第一极连接所述第一初始信号端，第二极连接所述驱动晶体管的栅极，栅极连接所述第一复位信号端；所述第二复位电路包括：第七晶体管，第七晶体管的第一极连接第 二初始信号端，第二极连接所述发光单元的第一电极，栅极连接所述第二复位信号端；所述存储电路包括：电容，电容的第一电极连接所述驱动晶体管的栅极，第二电极连接所述第一电源端。
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括上述的像素驱动电路。
根据本公开的一个方面，提供一种显示面板，其中，所述显示面板包括发光单元和用于驱动所述发光单元的像素驱动电路，所述像素驱动电路包括多个驱动晶体管，每个所述驱动晶体管的第二极均连接同一发光单元的第一电极，每个所述驱动晶体管用于根据其栅极电压向所述发光单元输入驱动电流。所述显示面板还包括:衬底基板、有源层，有源层位于所述衬底基板的一侧，所述有源层包括多个第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区。
本公开一种示例性实施例中，所述有源层还包括第八有源部、第九有源部，同一所述像素驱动电路中的所述第三有源部并联于所述第八有源部和所述第九有源部之间。
本公开一种示例性实施例中，所述第八有源部在所述衬底基板上的正投影和所述第九有源部在所述衬底基板上的正投影沿第二方向延伸；同一所述像素驱动电路中多个所述第三有源部在所述衬底基板上的正投影沿所述第二方向间隔分布。
本公开一种示例性实施例中，所述显示面板还包括：第一导电层，第一导电层位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖同一所述像素驱动电路每个所述第三有源部在所述衬底基板上的正投影；所述第一导电部的至少部分结构分别用于形成所述驱动晶体管的栅极。
本公开一种示例性实施例中，所述像素驱动电路还包括第四晶体管、第五晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述第五晶体管的第一极连接第一电源线，所述第五晶体管的第二极连接所述驱动晶体管第一极；所述有源层还包括：第四有源部、第五有源部，第四有源部连接于所述第八有源部的一端，所述第四有源部用于形成所述第四晶体管的沟道区；第 五有源部连接于所述第八有源部的另一端，所述第五有源部用于形成所述第五晶体管的沟道区；所述显示面板还包括:第一导电层，第一导电层位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括：第一栅线、使能信号线，所述第一栅线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第四有源部在所述衬底基板上的正投影，所述第一栅线的部分结构用于形成所述第四晶体管的栅极，所述第一方向和所述第二方向相交；所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第五有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第五晶体管的栅极；所述第三有源部在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影和所述使能信号线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述像素驱动电路包括多个子像素驱动电路，多个所述子像素驱动电路在所述衬底基板上的正投影沿第一方向和/或第二方向阵列分布，所述第一方向和所述第二方向相交；每个所述子像素驱动电路均包括所述驱动晶体管，且每个所述子像素驱动电路连接同一所述发光单元，所述子像素驱动电路用于向所述发光单元提供驱动电流。所述显示面板还包括：有源层、第一导电层，有源层位于所述衬底基板的一侧，所述有源层包括多个第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区；第一导电层位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括多个间隔设置的第一导电部，所述第一导电部和所述第三有源部对应设置，所述第一导电部在所述衬底基板上的正投影覆盖与其对应的所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极。
本公开一种示例性实施例中，所述子像素驱动电路还包括第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；所述有源层还包括：第六有源部、第七有源部、第十有源部，第六有源部连接于所述第三有源部，所述第六有源部用于形成所述第六晶体管的沟道区；第七有源部连接于所述第六有源部远离 所述第三有源部的一端，所述第七有源部用于形成所述第七晶体管的沟道区；第十有源部连接于所述第六有源部和所述第七有源部之间。所述显示面板还包括：第四导电层，第四导电层位于所述第一导电层背离所述衬底基板的一侧，所述第四导电部包括第一桥接部，所述第一桥接部分别连接同一所述像素驱动电路中的每一所述第十有源部，且所述第一桥接部连接所述发光单元的第一电极。
本公开一种示例性实施例中，所述子像素驱动电路还包括第一晶体管、第二晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极。所述有源层还包括：第一有源部、第二有源部，第一有源部用于形成所述第一晶体管的沟道区；第二有源部用于形成所述第二晶体管的沟道区。所述第一导电层还包括：第一复位信号线、第一栅线，第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；第一栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第一栅线的部分结构用于形成所述第二晶体管的栅极；所述显示面板还包括第二导电层，所述第二导电层位于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括：所述第二初始信号线，相邻上一行子像素驱动电路中所述第二初始信号线在所述衬底基板上的正投影位于本行子像素驱动电路中所述第一复位信号线在所述衬底基板上的正投影和本行子像素驱动电路中所述第一栅线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述有源层还包括：第十一有源部，第十一有源部连接于所述第一有源部和所述第二有源部之间。所述第二导电层还包括：第一凸起部，第一凸起部连接于所述第二初始信号线， 所述第一凸起部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第一凸起部在所述衬底基板上的正投影和所述第十一有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述第二晶体管为双沟道结构，所述第二晶体管的双沟道包括第一沟道和第二沟道，所述第二有源部包括：第一子有源部、第二子有源部，第一子有源部用于形成所述第二晶体管的第一沟道；第二子有源部用于形成所述第二晶体管的第二沟道；所述有源层还包括：第三子有源部，第三子有源部连接于所述第一子有源部和所述第二子有源部之间。所述第二导电层还包括：第二凸起部，第二凸起部连接于所述第二初始信号线，所述第二凸起部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第二凸起部在所述衬底基板上的正投影和所述第三子有源部在所述衬底基板上的正投影至少部分交叠。
本公开一种示例性实施例中，所述像素驱动电路中的所述子像素驱动电路至少在所述第二方向上分布，所述子像素驱动电路还包括第一晶体管、第二晶体管、第四晶体管、第五晶体管、第六晶体管、第七晶体管；所述第一晶体管的第一极连接第一初始信号线，第二极连接所述驱动晶体管的栅极；所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极；所述第四晶体管的第一极连接数据线，第二极连接所述驱动晶体管的第一极；所述第五晶体管的第一极连接第一电源线，第二极连接所述驱动晶体管的第一极；所述第六晶体管的第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极；所述第七晶体管的第一极连接第一初始信号线，第二极连接所述发光单元的第一电极。所述第一导电层还包括：第一复位信号线、第二复位信号线、第一栅线、使能信号线，第一复位信号线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；第二复位信号线在所述衬底基板上的正投影沿所述第一方向延伸，所述第二复位信号线的部分结构用于形成所述第七晶体管的栅极，且相邻下一行子像素驱动电路中所述第一复位信号线复用为本行子像素驱动电路中的所述第二复位信号线；第一栅线在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线的部分 结构用于分别形成所述第二晶体管和第四晶体管的栅极；使能信号线在所述衬底基板上的正投影沿所述第一方向延伸，所述使能信号线的部分结构用于分别形成所述第五晶体管和第六晶体管的栅极；所述显示面板包括多个像素单元，所述像素单元包括在所述第一方向上分布的多个像素驱动电路，同一像素单元中的像素驱动电路形成像素驱动电路组，所述第一方向为行方向；多条所述第一复位信号线中包括第一长复位信号线和第一短复位信号线，所述第一长复位信号线和位于同一行的所述子像素驱动电路对应设置，所述第一长复位信号线连接与其对应的所述子像素驱动电路，所述第一短复位信号线和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述第一短复位信号线连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述第一短复位信号线在所述衬底基板上的正投影在行方向上间隔设置；多条所述第一栅线中包括第一长栅线和第一短栅线，所述第一长栅线和位于同一行的所述子像素驱动电路对应设置，所述第一长栅线连接与其对应的所述子像素驱动电路，所述第一短栅线和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述第一短栅线连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述第一短栅线在所述衬底基板上的正投影在行方向上间隔设置；多条所述使能信号线中包括长使能信号线和短使能信号线，所述长使能信号线和位于同一行的所述子像素驱动电路对应设置，所述长使能信号线连接与其对应的所述子像素驱动电路，所述短使能信号线和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述短使能信号线连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述短使能信号线在所述衬底基板上的正投影在行方向上间隔设置；所述显示面板还包括：第三导电层，第三导电层位于所述第一导电层背离所述衬底基板的一侧，所述第三导电层包括第一连接线、第二连接线、第三连接线；其中，所述第一连接线、第二连接线、第三连接线在所述衬底基板上的正投影沿所述第二方向延伸，所述第一连接线分别通过过孔连接所述第一长复位信号线和第一短复位信号线，所述第二连接线分别通过过孔连接所述第一长栅线和第一短栅线，所述第三连接线分别通过过孔连接所述长使能 信号线和短使能信号线。
本公开一种示例性实施例中，所述显示面板还包括：第二导电层，第二导电层位于所述第一导电层和所述第三导电层之间，所述第二导电层包括所述第一初始信号线、第二初始信号线，所述第一初始信号线和所述第二初始信号线在所述衬底基板上的正投影沿所述第一方向延伸；其中，多条所述第一初始信号线中包括第一长初始信号线和第一短初始信号线，所述第一长初始信号线和位于同一行的所述子像素驱动电路对应设置，所述第一长初始信号线连接与其对应的所述子像素驱动电路，所述第一短初始信号线和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述第一短初始信号线连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述第一短初始信号线在所述衬底基板上的正投影在行方向上间隔设置；多条所述第二初始信号线中包括第二长初始信号线和第二短初始信号线，所述第二长初始信号线和位于同一行的所述子像素驱动电路对应设置，所述第二长初始信号线连接与其对应的所述子像素驱动电路，所述第二短初始信号线和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述第二短初始信号线连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述第二短初始信号线在所述衬底基板上的正投影在行方向上间隔设置；所述第三导电层还包括第四连接线、第五连接线，所述第四连接线分别通过过孔连接第一长初始信号线和第一短初始信号线，所述第五连接线分别通过过孔连接所述第二长初始信号线和第二短初始信号线。
本公开一种示例性实施例中，所述像素驱动电路还包括第一晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；所述显示面板还包括：第二导电层、第三导电层，第二导电层位于所述有源层背离所述衬底基板的一侧，所述第二导电层包括所述第一初始信号线和所述第二初始信号线，所述第一初始信号线在所述衬底基板上的正投影和所述第二初始信号线在所述衬底基板上的正投影沿第 一方向延伸；第三导电层位于所述第二导电层背离所述衬底基板的一侧，所述第三导电层包括第一初始连接线和第二初始连接线，所述第一初始连接线在所述衬底基板上的正投影和所述第二初始连接线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交；其中，所述第一初始连接线通过过孔连接与其在所述衬底基板上正投影相交的所述第一初始信号线，所述第二初始连接线通过过孔连接与其在所述衬底基板上正投影相交的所述第二初始信号线。
本公开一种示例性实施例中，所述显示面板包括多个像素单元，所述像素单元包括在所述第一方向上分布的多个像素驱动电路，同一像素单元中的像素驱动电路形成像素驱动电路组；在所述第二方向上分布的一列所述像素驱动电路组对应设置一条所述第一初始连接线和一条第二初始连接线；所述像素驱动电路组在所述衬底基板上的正投影位于与其对应的所述第一初始连接线和所述第二初始连接线在所述衬底基板上的正投影之间。
本公开一种示例性实施例中，所述显示面板的显示区包括正常显示区，所述显示面板还包括：多个像素单元，多个所述像素单元中包括第一像素单元，所述第一像素单元位于所述正常显示区，所述第一像素单元包括在第一方向上分布的多个像素驱动电路，同一所述第一像素单元中的像素驱动电路形成第一像素驱动电路组；所述显示面板还包括：第四导电层，第四导电层位于所述有源层背离所述衬底基板的一侧，所述第四导电层包括第一电源连接线，所述第一电源连接线用于向所述像素驱动电路提供高电平电源信号，所述第一电源连接线在所述衬底基板上的正投影为环形；其中，所述第一电源连接线和所述第一像素驱动电路组对应设置，所述第一像素驱动电路组在所述衬底基板上的正投影位于与其对应的所述第一电源连接线在所述衬底基板上的正投影内。
本公开一种示例性实施例中，所述显示面板还包括：第三导电层，第三导电层位于所述有源层和所述第四导电层之间，所述第三导电层包括电源桥接线，所述电源桥接线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交；其中，所述电源桥接线至少部分结构在所述衬底基板上的正投影位于在所述第一方向上相邻两所述 第一电源连接线在所述衬底基板上的正投影之间，且所述电源桥接线分别通过过孔连接与其相邻的两所述第一电源连接线。
本公开一种示例性实施例中，所述像素驱动电路包括第五晶体管，所述第五晶体管的第一极连接第一电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极；所述显示面板还包括：第三导电层，第三导电层位于所述有源层和所述第四导电层之间，所述第三导电层包括所述第一电源线；其中，所述第一电源线在所述衬底基板上的正投影沿第二方向延伸，所述第一方向和所述第二方向相交，所述第一电源线在所述衬底基板上的正投影和所述第一电源连接线在所述衬底基板上的正投影相交，且所述第一电源线通过过孔连接与其在所述衬底基板上正投影相交的所述第一电源连接线。
本公开一种示例性实施例中，所述像素驱动电路包括多个子像素驱动电路，多个所述子像素驱动电路在所述衬底基板上的正投影沿第一方向和/或第二方向阵列分布，所述第一方向和所述第二方向相交；每个所述子像素驱动电路均包括所述驱动晶体管，且每个所述子像素驱动电路连接同一所述发光单元，所述子像素驱动电路用于向所述发光单元提供驱动电流；所述子像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接第一电源线子部，所述第五晶体管的第二极连接所述驱动晶体管的第一极；所述第四导电层还包括所述第一电源线子部，所述第一电源线子部在所述衬底基板上的正投影包括沿所述第二方向延伸的部分和延所述第一方向延伸的部分，所述第一电源线子部和所述像素驱动电路对应设置，所述第一电源线子部连接与其对应的所述像素驱动电路中每个所述第五晶体管的第一极，且所述第一电源线子部连接所述第一电源连接线。
本公开一种示例性实施例中，所述子像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；所述显示面板还包括：第三导电层，第三导电层位于所述有源层和所述第四导电层之间，所述第三导电层包括第二桥接部，所述第二桥接部连接所述驱动晶体管的栅极和第二晶体管的第二极；所述第一电源线子部包括：多个第二导电部， 所述第二导电部和所述子像素驱动电路对应设置，所述第二导电部在所述衬底基板上的正投影和与其对应的所述子像素驱动电路中第二桥接部在所述衬底基板上的正投影至少部分交叠，且所述第二导电部连接与其对应的所述子像素驱动电路中所述第五晶体管的第一极。
本公开一种示例性实施例中，所述第四导电层还包括：第一连接部，所述第一连接部在所述衬底基板上的正投影沿所述第二方向延伸，所述第一连接部连接于在所述第二方向上相邻的所述第二导电部和所述第一电源连接线之间。
本公开一种示例性实施例中，所述显示面板还包括：第三导电层，所述第三导电层还包括：多个第三桥接部，所述第三桥接部至少部分结构在所述衬底基板上的正投影位于在所述第二方向上相邻的两所述第一电源连接线在所述衬底基板上的正投影之间，所述第三桥接部分别通过过孔连接与其相邻两所述第一电源连接线。
本公开一种示例性实施例中，所述第四导电层还包括：第二电源连接线，所述第二电源连接线和所述第一电源连接线对应设置，所述第二电源连接线在所述衬底基板上的正投影为环形，所述第一电源连接线在所述衬底基板上的正投影位于与其对应的所述第二电源连接线在所述衬底基板上的正投影以内；所述显示面板还包括：公共电极层，公共电极层位于所述第四导电层背离所述衬底基板的一侧，所述公共电极层用于形成所述发光单元的第二电极，所述第二电源连接线通过过孔连接所述公共电极层。
本公开一种示例性实施例中，所述显示面板的显示区还包括压缩区，所述压缩区位于所述正常显示区在所述第一方向上的一侧；多个所述像素单元中还包括第二像素单元，所述第二像素单元位于所述压缩区，所述第二像素单元包括在第一方向上分布的多个像素驱动电路，同一所述第二像素单元中的像素驱动电路形成第二像素驱动电路组；所述第四导电层还包括：第三电源连接线，所述第三电源连接线用于向所述像素驱动电路提供高电平电源信号，所述第三电源连接线和所述第二像素驱动电路组对应设置，所述第三电源连接线包括第一侧边，所述第一侧边在所述衬底基板上的正投影沿第二方向延伸且位于与其对应的所述第二像 素驱动电路组在所述衬底基板上的正投影在所述第一方向上的一侧，所述第一方向和所述第二方向相交；其中，所述第一电源连接线在所述衬底基板上的正投影和所述第一像素驱动电路组在所述衬底基板上的正投影在所述第一方向上的距离大于所述第一侧边在所述衬底基板上的正投影和所述第二像素驱动电路组在所述衬底基板上的正投影在所述第一方向上的距离。
本公开一种示例性实施例中，所述第四导电层还包括：第二电源连接线、第四电源连接线，所述第二电源连接线和所述第一电源连接线对应设置，所述第二电源连接线在所述衬底基板上的正投影为环形，所述第一电源连接线在所述衬底基板上的正投影位于与其对应的所述第二电源连接线在所述衬底基板上的正投影以内；所述第四电源连接线和所述第三电源连接线对应设置；所述显示面板还包括：公共电极层，公共电极层位于所述第四导电层背离所述衬底基板的一侧，所述公共电极层用于形成所述发光单元的第二电极，所述第二电源连接线和所述第四电源连接线均通过过孔连接所述公共电极层；所述显示面板还包括：电极层，电极层位于所述第四导电层和所述公共电极层之间，所述电极层包括第一电极环和第二电极线；所述第一电极环连接于所述第二电源连接线和所述公共电极层之间，所述第一电极环在所述衬底基板上的正投影为环形，所述第一电源连接线在所述衬底基板上的正投影位于所述第一电极环在所述衬底基板上的正投影内；所述第二电极线连接于所述第四电源连接线和所述公共电极层之间，所述第二电极线包括第二侧边，所述第二侧边至少部分结构在所述衬底基板上的正投影位于所述第一侧边在所述衬底基板上的正投影远离所述第二像素驱动电路组在所述衬底基板上的正投影的一侧；所述第一侧边在所述衬底基板上的正投影和所述第二侧边在所述衬底基板上的正投影在所述第一方向上的距离小于所述第一电源连接线在所述衬底基板上的正投影和所述第一电极环在所述衬底基板上的正投影在所述第一方向上的距离。
根据本公开的一个方面，提供一种显示装置，其中，包括上述的显示面板。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本公开。
附图说明
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本公开的实施例，并与说明书一起用于解释本公开的原理。显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开像素驱动电路一种示例性实施例的结构示意图；
图2为图1所示像素驱动电路一种驱动方法中各控制信号的时序图；
图3为本公开显示面板一种示例性实施例中的结构版图；
图4为图3中有源层的结构版图；
图5为图3中第一导电层的结构版图；
图6为图3中第二导电层的结构版图；
图7为图3中第三导电层的结构版图；
图8为图3中第四导电层的结构版图；
图9为图3中有源层、第一导电层的结构版图；
图10为图3中有源层、第一导电层、第二导电层的结构版图；
图11为图3中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图12为本公开显示面板另一种示例性实施例中的结构版图；
图13为图12中有源层的结构版图；
图14为图12中第一导电层的结构版图；
图15为图12中第二导电层的结构版图；
图16为图12中第三导电层的结构版图；
图17为图12中第四导电层的结构版图；
图18为图12中电极层和像素界定层的结构板；
图19为图12中有源层、第一导电层的结构版图；
图20为图12中有源层、第一导电层、第二导电层的结构版图；
图21为图12中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图22为图12中有源层、第一导电层、第二导电层、第三导电层、 第四导电层的结构版图；
图23为图12所示显示面板沿虚线BB剖开的部分剖视图；
图24为本公开像素驱动电路另一种示例性实施例的结构示意图；
图25为本公开显示面板一种示例性实施例中的结构版图；
图26为图25中有源层的结构版图；
图27为图25中第一导电层的结构版图；
图28为图25中第二导电层的结构版图；
图29为图25中第三导电层的结构版图；
图30为图25中第四导电层的结构版图；
图31为图25中有源层、第一导电层的结构版图；
图32为图25中有源层、第一导电层、第二导电层的结构版图；
图33为图25中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图34为本公开显示面板另一种示例性实施例中的结构版图；
图35为图34中有源层的结构版图；
图36为图34中第一导电层的结构版图；
图37为图34中第二导电层的结构版图；
图38为图34中第三导电层的结构版图；
图39为图34中第四导电层的结构版图；
图40为图34中电极层和像素界定层的结构板；
图41为图34中有源层、第一导电层的结构版图；
图42为图34中有源层、第一导电层、第二导电层的结构版图；
图43为图34中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图44为图34中有源层、第一导电层、第二导电层、第三导电层、第四导电层的结构版图；
图45为图34所示显示面板沿虚线CC剖开的部分剖视图；
图46为本公开显示面板一种示例性实施例的结构示意图；
图47为图46中右侧第二像素单元的结构版图；
图48为图47中有源层的结构版图；
图49为图47中第一导电层的结构版图；
图50为图47中第二导电层的结构版图；
图51为图47中第三导电层的结构版图；
图52为图47中第四导电层的结构版图；
图53为图47中电极层和像素界定层的结构板；
图54为图47中有源层、第一导电层的结构版图；
图55为图47中有源层、第一导电层、第二导电层的结构版图；
图56为图47中有源层、第一导电层、第二导电层、第三导电层的结构版图；
图57为图47中有源层、第一导电层、第二导电层、第三导电层、第四导电层的结构版图。
具体实施方式
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本公开将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。
用语“一个”、“一”、“所述”用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。
相关技术中，像素驱动电路通常包括有驱动晶体管，驱动晶体管根据其栅极的数据信号向发光单元提供驱动电流，然而，Data Range(数据信号的电压范围)受限于显示面板的芯片，从而导致像素驱动电路无法输出较大的驱动电流。
基于此，本示例性实施例提供一种像素驱动电路，所述像素驱动电路可以包括：多个驱动晶体管，每个所述驱动晶体管的第二极均连接同一发光单元的第一电极，每个所述驱动晶体管用于根据其栅极电压向所述发光单元输入驱动电流。
本示例性实施例提供的像素驱动电路通过并联的多个驱动晶体管向同一发光单元提供驱动电流，从而可以在相同的数据信号作用下向发光单元提供较大的驱动电流。该像素驱动电路可以应用于像素单元布图面积大，驱动电流需求大的显示面板和显示装置，例如，该像素驱动电路可以应用于拼接屏。
如图1所示，为本公开像素驱动电路一种示例性实施例的结构示意图。该像素驱动电路包括多个驱动晶体管T3，每个所述驱动晶体管T3的第二极均连接同一发光单元OLED的第一电极，每个所述驱动晶体管T3用于根据其栅极电压向所述发光单元OLED输入驱动电流。如图1所示，每个所述驱动晶体管T3的栅极均连接第一节点N1，每个所述驱动晶体管T3的第一极均连接第一电源端VDD。
本示例性实施例中，所述驱动晶体管T3的第二极均连接同一发光单元OLED的第一电极中的“连接”可以理解为电连接、电耦合等，且“连接”可以为直接连接也可以为间接连接。
如图1所示，所述像素驱动电路还包括：数据写入电路1、补偿电路2、发光控制电路3、第一复位电路4、第二复位电路5、存储电路6，数据写入电路1连接数据信号端Da、每个所述驱动晶体管T3的第一极、第一栅极驱动信号端G1，用于响应所述第一栅极驱动信号端G1的信号以将所述数据信号端Da的信号传输到每个所述驱动晶体管T3的第一极；补偿电路2连接所述第一节点N1、每个所述驱动晶体管T3的第二极、第二栅极驱动信号端G2，用于响应所述第二栅极驱动信号端G2的信号以连通所述第一节点N1和每个所述驱动晶体管T3的第二极；发光控制电路3连接所述第一电源端VDD、每个所述驱动晶体管T3的第一极、使能信号端EM、每个所述驱动晶体管T3的第二极、发光单元OLED的第一电极，用于响应所述使能信号端EM的信号以连通所述第一电源端VDD和每个所述驱动晶体管T3的第一极，以及用于响应所述使能信号端EM的信号以连通每个所述驱动晶体管T3的第二极和所述发光单元OLED的第一电极；第一复位电路4连接第一初始信号端Vinit1、第一复位信号端Re1、所述第一节点N1，用于响应所述第一复位信号端Re1的信号以将所述第一初始信号端Vinit1的信号传输到所述第一节点N1；第二复位电路5连接 第二初始信号端Vinit2、第二复位信号端Re2、发光单元OLED的第一电极，用于响应所述第二复位信号端Re2的信号以将所述第二初始信号端Vinit2的信号传输到所述发光单元OLED的第一电极；存储电路6连接于所述第一节点N1和所述第一电源端VDD之间。
具体实施例中，第一栅极驱动信号端G1和第二栅极驱动信号端G2，可以是同一个信号控制端，也可以是不同的信号控制端；例如，第二栅极驱动信号端G2的开启时间长于第一栅极驱动信号端G1，以使第一栅极驱动信号端G1控制下的数据信号可以充分写入驱动晶体管的栅极；又例如第一栅极驱动信号端G1和第二栅极驱动信号端G2为同一控制信号端，以节约控制信号线。下文中的实施例以第一栅极驱动信号端G1和第二栅极驱动信号端G2为同一控制信号端，也即是所述补偿电路2由第一栅极驱动信号端G1进行控制来描述。
如图1所示，所述数据写入电路1可以包括：第四晶体管T4，所述第四晶体管T4的第一极连接所述数据信号端Da，第二极连接每个所述驱动晶体管T3的第一极，栅极连接第一栅极驱动信号端G1；所述补偿电路2可以包括:第二晶体管T2，所述第二晶体管T2的第一极连接所述第一节点N1，第二极连接每个所述驱动晶体管T3的第二极，栅极连接所述第一栅极驱动信号端G1；所述发光控制电路3可以包括：第五晶体管T5、第六晶体管T6，所述第五晶体管T5的第一极连接所述第一电源端VDD，第二极连接每个所述驱动晶体管T3的第一极，栅极连接所述使能信号端EM；第六晶体管T6的第一极连接每个所述驱动晶体管T3的第二极，第二极连接所述发光单元OLED的第一电极，栅极连接所述使能信号端EM；所述第一复位电路4可以包括：第一晶体管T1，第一晶体管T1的第一极连接所述第一初始信号端Vinit1，第二极连接所述第一节点N1，栅极连接所述第一复位信号端Re1；所述第二复位电路5可以包括：第七晶体管T7，第七晶体管T7的第一极连接第二初始信号端Vinit2，第二极连接所述发光单元OLED的第一电极，栅极连接所述第二复位信号端Re2；所述存储电路6可以包括：电容C，电容C的第一电极连接所述第一节点N1，第二电极连接所述第一电源端VDD。发光单元OLED的第二电极连接第二电源端VSS。
其中，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型晶体管。第一电源端VDD可以为高电平电源端，第二电源端VSS可以为低电平电源端。
如图2所示，为图1所示像素驱动电路一种驱动方法中各控制信号的时序图。其中，G1表示第一栅极驱动信号端G1信号的时序，Re1表示第一复位信号端Re1信号的时序，Re2表示第二复位信号端Re2信号的时序，EM表示使能信号端EM信号的时序。该像素驱动电路的驱动方法可以包括第一复位阶段t1、数据写入阶段t2，第二复位阶段t3、发光阶段t4。在第一复位阶段t1：第一复位信号端Re1输出低电平信号，第一晶体管T1导通，第一初始信号端Vinit1向第一节点N1输入第一初始信号。在数据写入阶段t2：第一栅极驱动信号端G1输出低电平信号，第四晶体管T4、第二晶体管T2，同时数据信号端Da输出数据信号以向第一节点N1写入电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压。在第二复位阶段t3：第二复位信号端输出低电平信号，第七晶体管导通，第二初始信号端Vinit2向第六晶体管T6的第二极输入第二初始信号。在发光阶段t4：使能信号端EM输出低电平信号，第六晶体管T6、第五晶体管T5导通，多个驱动晶体管T3在第一节点N1的电压Vdata+Vth作用下驱动发光单元发光。本公开像素驱动电路中每个驱动晶体管的输出电流I＝(μWCox/2L)(Vdata+Vth-Vdd-Vth)2。其中，μ为载流子迁移率；Cox为单位面积栅极电容量，W为驱动晶体管沟道的宽度，L驱动晶体管沟道的长度，Vgs为驱动晶体管栅源电压差，Vth为驱动晶体管阈值电压。该像素驱动电路能够避免驱动晶体管阈值对其输出电流的影响。应该理解的是，在其他示例性实施例中，该像素驱动电路还可以有其他驱动方法，例如，第七晶体管可以在数据写入阶段t2导通。
本示例性实施例提供一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、有源层、第一导电层、第二导电层、第三导电层、第四导电层，其中，上述相邻导电层之间可以设置有绝缘层。
如图3-11所示，图3为本公开显示面板一种示例性实施例中的结构版图，图4为图3中有源层的结构版图，图5为图3中第一导电层的结 构版图，图6为图3中第二导电层的结构版图，图7为图3中第三导电层的结构版图，图8为图3中第四导电层的结构版图，图9为图3中有源层、第一导电层的结构版图，图10为图3中有源层、第一导电层、第二导电层的结构版图，图11为图3中有源层、第一导电层、第二导电层、第三导电层的结构版图。该显示面板可以包括多个像素驱动电路，图3所示显示面板中像素驱动电路的结构和图1所示像素驱动电路的结构仅区别在于图3所示显示面板中像素驱动电路包括六个并联的驱动晶体管。
如图3、4、9所示，有源层可以包括第一有源部61、第二有源部62、多个第三有源部63、第四有源部64、第五有源部65、第六有源部66、第七有源部67、第八有源部68、第九有源部69、第十有源部610、第十一有源部611、第十二有源部612、第十三有源部613、第十四有源部614、第十五有源部615。其中，第一有源部61用于形成第一晶体管T1的沟道区，第二有源部62用于形成第二晶体管T2的沟道区，第二晶体管T2为双沟道结构，第二有源部62包括第一子有源部621和第二子有源部622，第一子有源部621用于形成第二晶体管的第一沟道，第二子有源部622用于形成第二晶体管T2的第二沟道，有源层还包括第三子有源部623，第三子有源部623连接于第一子有源部621和第二子有源部622之间；第三有源部63可以用于形成驱动晶体管T3的沟道区；第四有源部64可以用于形成第四晶体管T4的沟道区；第五有源部65可以用于形成第五晶体管T5的沟道区；第六有源部66可以用于形成第六晶体管T6的沟道区；第七有源部67可以用于形成第七晶体管T7的沟道区；第八有源部68和第九有源部69在所述衬底基板上的正投影沿第二方向Y延伸，第八有源部68连接于第四有源部64和第五有源部65之间，第九有源部69连接于第六有源部66和第二有源部62之间，多个第三有源部63并联于第八有源部68和第九有源部69之间；第十有源部610连接于第六有源部66和第七有源部67之间；第十一有源部611连接于第一有源部61和第二有源部62之间；第十二有源部612连接于第七有源部67远离第六有源部66的一端；第十三有源部613连接于第四有源部64远离第三有源部63的一端；第十四有源部614连接于第一有源部61远离第二有源部62的一端；第十五有源部615连接于第五有源部65远离第四 有源部64的一端。其中，有源层可以由多晶硅材料形成，相应的，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图3、5、9所示，第一导电层可以包括：第一导电部11、第一栅线G1、使能信号线EM、第一复位信号线Re1、第二复位信号线Re2。第一栅线G1在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第一复位信号线Re1在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿第一方向X延伸，第一方向X和第二方向Y可以相交，例如，第一方向X可以为行方向，第二方向Y可以为列方向。第一栅线G1可以用于提供第一栅极驱动信号端；使能信号线EM可以用于提供使能信号端；第一复位信号线Re1可以用于提供第一复位信号端；第二复位信号线Re2可以用于提供第二复位信号端。其中，第一栅线G1在衬底基板上的正投影覆盖第二有源部62、第四有源部64在衬底基板上的正投影，第一栅线G1的部分结构用于分别形成第二晶体管T2的栅极和第四晶体管的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部65在衬底基板上的正投影、第六有源部66在衬底基板上的正投影，使能信号线EM的部分结构可以分别用于形成第五晶体管T5、第六晶体管T6的栅极。第一复位信号线Re1在衬底基板上的正投影覆盖第一有源部61在衬底基板上的正投影，第一复位信号线Re1的部分结构用于形成第一晶体管T1的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部67在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11在衬底基板上的正投影覆盖所有第三有源部63在衬底基板上的正投影，第一导电部11可以用于形成多个驱动晶体管T3的公共栅极和电容C的第一电极。此外，该显示面板可以利用第一导电层为掩膜对有源层进行导体化处理，即有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，未被第一导电层覆盖的区域形成导体结构。
如图3、6、10所示，第二导电层可以包括：第一初始信号线Vinit1、第二初始信号线Vinit2、第三导电部23、第四导电部24。第一初始信号 线Vinit1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影沿第一方向X延伸，第一初始信号线Vinit1用于提供第一初始信号端，第二初始信号线Vinit2用于提供第二初始信号端。第三导电部23在衬底基板上的正投影和第一导电部11在所述衬底基板上的正投影至少部分交叠，第三导电部23用于形成电容C的第二电极。第四导电部24在衬底基板上的正投影和第三子有源部623在衬底基板上的正投影至少部分交叠。
如图3、7、11所示，第三导电层可以包括第一电源线VDD、数据线Da、第一初始连接线3Vinit1、第二桥接部32、第四桥接部34、第五桥接部35、第六桥接部36、第七桥接部37、第八桥接部38。其中，第一电源线VDD在衬底基板上的正投影、数据线Da在衬底基板上的正投影、第一初始连接线3Vinit1在衬底基板上的正投影沿第二方向Y延伸，第一电源线VDD用于提供第一电源端，数据线Da用于提供数据信号端。数据线Da可以通过过孔(黑色方块)连接第十三有源部613，以连接第四晶体管T4的第一极。第一电源线VDD可以通过过孔连接第十五有源部615，以连接第五晶体管的第一极。第一初始连接线3Vinit1通过过孔连接与其在衬底基板上正投影相交的第一初始信号线Vinit1，以形成网格结构的第一初始信号线，从而降低第一初始信号线上信号的压降。第二桥接部32在衬底基板上的正投影可以沿第二方向Y延伸，第二桥接部32可以通过在第二方向Y上分布的多个过孔连接第一导电部11，且第二桥接部32可以通过过孔连接第十一有源部611，以连接驱动晶体管T3的栅极和第一晶体管T1的第二极、第二晶体管T2的第一极。第三导电部23上可以形成有开口231，连接于第一导电部11和第二桥接部32之间的过孔在衬底基板上的正投影可以位于开口231在衬底基板上的正投影内，以使连接于第一导电部11和第二桥接部32之间的过孔和第三导电部23绝缘设置。第四桥接部34在衬底基板上的正投影可以沿第二方向延伸，第四桥接部34可以通过在第二方向上分布的多个过孔连接第九有源部69，以减小多个驱动晶体管T3第二极的电压差。第五桥接部35可以通过在第二方向上分布的多个过孔连接第八有源部68，以减小多个驱动晶体管T3第一极的电压差。第六桥接部36可以通过过孔连接第十有源部610， 以连接第六晶体管T6的第二极。第七桥接部37可以分别通过过孔连接第一初始信号线Vinit1、第十四有源部，以连接第一初始信号端和第一晶体管的第一极，第七桥接部37还可以通过过孔连接第四导电部24，第四导电部24在第一初始信号线Vinit1作用下具有稳定电压，第四导电部24可以对第三子有源部623进行稳压，以改善由于第三子有源部623电压波动而导致的向第二晶体管T2源漏极漏电的问题。第八桥接部38可以分别通过过孔连接第十二有源部612和第二初始信号线Vinit2，以连接第七晶体管T7的第一极和第二初始信号端。
如图3、8所示，所述第四导电层可以包括第九桥接部49，第九桥接部49可以通过过孔连接第六桥接部36，第九桥接部49可以用于连接发光单元的第一电极，以连接第六晶体管的第二极和发光单元的第一电极。
如图12-22所示，图12为本公开显示面板另一种示例性实施例中的结构版图，图13为图12中有源层的结构版图，图14为图12中第一导电层的结构版图，图15为图12中第二导电层的结构版图，图16为图12中第三导电层的结构版图，图17为图12中第四导电层的结构版图，图18为图12中电极层和像素界定层的结构板，图19为图12中有源层、第一导电层的结构版图，图20为图12中有源层、第一导电层、第二导电层的结构版图，图21为图12中有源层、第一导电层、第二导电层、第三导电层的结构版图，图22为图12中有源层、第一导电层、第二导电层、第三导电层、第四导电层的结构版图。
如图12-22所示，该显示面板可以包括多个像素单元，多个像素单元可以在第一方向X和第二方向Y上阵列分布，图12示出了一个像素单元的版图结构，每个像素单元可以包括在第一方向X上分布的多个像素驱动电路，本示例性实施例中，每个像素单元可以包括在第一方向X上分布的三个像素驱动电路。图12中像素驱动电路可以包括图3所示像素驱动电路的全部结构特征。
如图12、15、20所示，绿色发光单元对应的像素驱动电路中的第三导电部23异于红色发光单元和蓝色发光单元对应的像素驱动电路中的第三导电部23，在绿色发光单元对应的像素驱动电路中，第三导电部23和第一导电部11的交叠面积较大，从而可以增大绿色发光单元对应的像素 驱动电路中电容C的容值，进而可以改善绿色发光单元的画质。应该理解的是，在其他示例性实施例中，也可以从其他颜色发光单元的画质要求角度对红色发光单元、蓝色发光单元、绿色发光单元对应像素驱动电路中的电容进行差异化设置，该差异化设置的方式可以如图20所示，通过在第三导电部23上增加横向连接块以增加第三导电部23和第一导电部11之间的电容。
如图12、16、21所示，同一像素单元中的三个像素驱动电路形成像素驱动电路组。第一初始连接线3Vinit1和一列像素驱动电路组对应设置，第一初始连接线3Vinit1通过过孔连接与其在衬底基板上正投影相交的第一初始信号线Vinit1。第三导电层还可以包括第二初始连接线3Vinit2，第二初始连接线3Vinit2和一列像素驱动电路组对应设置。第二初始连接线3Vinit2通过过孔连接与其在衬底基板上正投影相交的第二初始信号线。像素驱动电路组在所述衬底基板上的正投影位于与其对应的所述第一初始连接线3Vinit1和所述第二初始连接线3Vinit2在所述衬底基板上的正投影之间。
如图12、17、22所示，第四导电层还可以包括第一电源连接线4VDD，第一电源连接线4VDD在所述衬底基板上的正投影为环形；其中，第一电源连接线4VDD和像素驱动电路组对应设置，第一像素驱动电路组在所述衬底基板上的正投影位于与其对应的所述第一电源连接线4VDD在所述衬底基板上的正投影内。第一电源连接线4VDD可以通过过孔连接像素驱动电路组对应的三条第一电源线VDD。本示例性实施例中，环形指首尾相连的线形成的图像，环形可以矩形、圆形、三角形、多边形等。
如图12、16、21所示，第三导电层还包括电源桥接线3VDD，所述电源桥接线3VDD在所述衬底基板上的正投影沿第二方向Y延伸。其中，所述电源桥接线3VDD至少部分结构在所述衬底基板上的正投影位于在所述第一方向X上相邻两所述第一电源连接线4VDD在所述衬底基板上的正投影之间，且所述电源桥接线3VDD分别通过过孔连接与其相邻的两所述第一电源连接线4VDD。即所述第一电源连接线4VDD至少部分结构在所述衬底基板上的正投影位于在所述第一方向上相邻两个电源桥接线3VDD在所述衬底基板上的正投影之间，且所述电源桥接线分别通过过孔连接所述 第一电源连接线。电源桥接线3VDD可以使得在第一方向X上分布的第一电源连接线4VDD相连接。电源桥接线3VDD、第一电源连接线4VDD可以使得第一电源线VDD形成网格结构，以降低第一电源线上电源信号的压降。
如图8、12、17、22所示，第四导电层还可以包括多个第五导电部45，第五导电部45连接于第一电源连接线4VDD，第五导电部45可以进一步降低第一电源线的压降。
如图12、18所示，电极层可以包括多个电极部：第一电极部G、第二电极部B、第三电极部R，各个电极部可以通过过孔连接第九桥接部49，以连接第六晶体管的第二极。像素界定层上形成有多个像素开口PH，所述像素开口PH与所述电极部对应设置，所述像素开口PH在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合.第一电极部G可以用于形成显示面板中绿色发光单元的电极部，第二电极部B可以用于形成显示面板中蓝色发光单元的电极部，第三电极部R可以用于形成红色发光单元的电极部。电极部还可以和第五导电部45对应设置，电极部在衬底基板上的正投影和与其对应的第五导电部45在衬底基板上的正投影至少部分交叠，电极部在衬底基板上的正投影和与其对应的第五导电部45在衬底基板上的正投影的交叠面积为S1，电极部在衬底基板上的正投影的面积为S2，S1/S2大于等于80％，例如，S1/S2可以为80％、90％、100％。该设置可以提高电极部的平坦度。如图8所示，第五导电部45上可以形成有多个开口451，开口451能够释放第四导电层和第三导电层之间平坦层的水气。
如图12、17、22所示，第四导电层还可以包括第二电源连接线4VSS，所述第二电源连接线4VSS和所述第一电源连接线4VDD对应设置，所述第二电源连接线4VSS在所述衬底基板上的正投影为环形，所述第一电源连接线4VDD在所述衬底基板上的正投影位于与其对应的所述第二电源连接线4VSS在所述衬底基板上的正投影内。电极层还可以包括第一电极环5VSS，第一电极环5VSS在衬底基板上的正投影为环形，第一电极环5VSS和第二电源连接线4VSS对应设置，且连接与其对应的第二电源连接线4VSS。显示面板还可以包括公共电极层，公共电极层位于电极层背离衬 底基板的一侧，公共电极层可以用于形成发光单元的第二电极，第二电源连接线4VSS可以通过第一电极环5VSS连接公共电极层。第二电源连接线4VSS、第一电极环5VSS可以降低公共电极层上电源信号的压降。
如图23所示，为图12所示显示面板沿虚线BB剖开的部分剖视图。该显示面板还可以包括第一绝缘层92、第二绝缘层93、介电层94、钝化层95、第一平坦层96、第二平坦层97、像素界定层98。其中，衬底基板91、有源层、第一绝缘层92、第一导电层、第二绝缘层93、第二导电层、介电层94、第三导电层、钝化层95、第一平坦层96、第四导电层、第二平坦层97、电极层、像素界定层98依次层叠设置。第一绝缘层92、第二绝缘层93可以包括氧化硅、氮化硅层中的一层或多层；介电层94可以包括氮化硅层；第一平坦层96、第二平坦层97的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。钝化层95可以为氧化硅层。衬底基板91可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层、第二导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层、第四导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。电极层可以包括氧化铟锡层、银层。第一导电层、第二导电层中任一导电层的方块电阻可以大于第三导电层、第四导电层中任一导电层的方块电阻。
应该理解的是，在其他示例性实施例中，实现像素驱动电路中驱动晶体管并联还可以有其他方式。如图24所示，为本公开像素驱动电路另一种示例性实施例的结构示意图。像素驱动电路可以包括多个子像素驱动电路pix，每个所述子像素驱动电路pix均包括至少一个所述驱动晶体管T3，且每个所述子像素驱动电路连接同一所述发光单元OLED，所述子像素驱动电路用于向所述发光单元OLED提供驱动电流。
如图24所示，所述子像素驱动电路还包括：数据写入电路1、补偿电路2、发光控制电路3、第一复位电路4、第二复位电路5、存储电路6。数据写入电路1连接数据信号端Da、所述驱动晶体管T3的第一极、第一 栅极驱动信号端G1，用于响应所述第一栅极驱动信号端G1的信号以将所述数据信号端Da的信号传输到所述驱动晶体管T3的第一极；补偿电路2连接所述驱动晶体管T3的栅极、所述驱动晶体管T3的第二极、第一栅极驱动信号端G1，用于响应所述第一栅极驱动信号端G1的信号以连通所述所述驱动晶体管T3的栅极和所述驱动晶体管T3的第二极；发光控制电路3连接所述第一电源端VDD、所述驱动晶体管T3的第一极、使能信号端EM、所述驱动晶体管T3的第二极、发光单元OLED的第一电极，用于响应所述使能信号端EM的信号以连通所述第一电源端VDD和所述驱动晶体管T3的第一极，以及用于响应所述使能信号端EM的信号以连通所述驱动晶体管T3的第二极和所述发光单元OLED的第一电极；第一复位电路4连接第一初始信号端Vinit1、第一复位信号端Re1、所述驱动晶体管T3的栅极，用于响应所述第一复位信号端Re1的信号以将所述第一初始信号端Vinit1的信号传输到所述驱动晶体管T3的栅极；第二复位电路5连接第二初始信号端Vinit2、第二复位信号端Re2、发光单元OLED的第一电极，用于响应所述第二复位信号端Re2的信号以将所述第二初始信号端Vinit2的信号传输到所述发光单元OLED的第一电极；存储电路6连接于所述驱动晶体管T3的栅极和所述第一电源端VDD之间。
如图24所示，所述数据写入电路1包括：第四晶体管T4，第四晶体管T4的第一极连接所述数据信号端Da，第二极连接所述驱动晶体管T3的第一极，栅极连接第一栅极驱动信号端G1；所述补偿电路2包括:第二晶体管T2，所述第二晶体管T2的第一极连接所述驱动晶体管T3的栅极，第二极连接所述驱动晶体管T3的第二极，栅极连接所述第一栅极驱动信号端G1；所述发光控制电路3包括：第五晶体管T5、第六晶体管T6，第五晶体管T5的第一极连接所述第一电源端VDD，第二极连接所述驱动晶体管T3的第一极，栅极连接所述使能信号端EM；第六晶体管T6的第一极连接所述驱动晶体管T3的第二极，第二极连接所述发光单元OLED的第一电极，栅极连接所述使能信号端EM；所述第一复位电路4包括：第一晶体管T1，第一晶体管T1的第一极连接所述第一初始信号端Vinit1，第二极连接所述驱动晶体管T3的栅极，栅极连接所述第一复位信号端Re1；所述第二复位电路5包括：第七晶体管T7，第七晶体管T7的第一 极连接第二初始信号端Vinit2，第二极连接所述发光单元OLED的第一电极，栅极连接所述第二复位信号端Re2；所述存储电路6包括：电容C，电容C的第一电极连接所述驱动晶体管T3的栅极，第二电极连接所述第一电源端VDD。
本示例性实施例中，图24所示像素驱动电路中各控制信号的时序同样可以如图2所示，其中，G1表示第一栅极驱动信号端G1信号的时序，Re1表示第一复位信号端Re1信号的时序，Re2表示第二复位信号端Re2信号的时序，EM表示使能信号端EM信号的时序。该像素驱动电路的驱动方法同样可以包括第一复位阶段t1、数据写入阶段t2，第二复位阶段t3、发光阶段t4。在第一复位阶段t1：第一复位信号端Re1输出低电平信号，各个子像素驱动电路中第一晶体管T1导通，第一初始信号端Vinit1向各个子像素驱动电路中驱动晶体管的栅极输入第一初始信号。在数据写入阶段t2：第一栅极驱动信号端G1输出低电平信号，各个子像素驱动电路中第四晶体管T4、第二晶体管T2导通，同时数据信号端Da输出数据信号以向各个子像素驱动电路中驱动晶体管的栅极写入电压Vdata+Vth，其中Vdata为数据信号的电压，Vth为驱动晶体管T3的阈值电压。在第二复位阶段t3，第二复位信号端输出低电平信号，每个子像素驱动电路中的第七晶体管导通，第二初始信号端Vinit2向各个子像素驱动电路中第六晶体管T6的第二极输入第二初始信号。在发光阶段t4：使能信号端EM输出低电平信号，各个子像素驱动电路中第六晶体管T6、第五晶体管T5导通，多个驱动晶体管T3在其栅极的电压Vdata+Vth作用下驱动发光单元发光。应该理解的是，在其他示例性实施例中，该像素驱动电路还可以有其他驱动方法，例如，第七晶体管可以在数据写入阶段t2导通。
在其他示例性实施例中，单个子像素驱动电路中也可以包括多个并联的驱动晶体管。
本示例性实施例还提供另一种显示面板，该显示面板可以包括依次层叠设置的衬底基板、有源层、第一导电层、第二导电层、第三导电层、第四导电层，其中，上述相邻导电层之间可以设置有绝缘层。
如图25-33所示，图25为本公开显示面板一种示例性实施例中的结构版图，图26为图25中有源层的结构版图，图27为图25中第一导电 层的结构版图，图28为图25中第二导电层的结构版图，图29为图25中第三导电层的结构版图，图30为图25中第四导电层的结构版图，图31为图25中有源层、第一导电层的结构版图，图32为图25中有源层、第一导电层、第二导电层的结构版图，图33为图25中有源层、第一导电层、第二导电层、第三导电层的结构版图。该显示面板可以包括多个像素驱动电路，图25所示显示面板中像素驱动电路的结构和图24所示像素驱动电路的结构仅区别在于图25所示显示面板中像素驱动电路包括3乘3阵列分布的9个子像素驱动电路。
如图25、26、31所示，有源层可以包括第一有源部61、第二有源部62、多个第三有源部63、第四有源部64、第五有源部65、第六有源部66、第七有源部67、第十有源部610、第十一有源部611、第十二有源部612、第十三有源部613、第十四有源部614、第十五有源部615。其中，第一有源部61用于形成第一晶体管T1的沟道区，第二有源部62用于形成第二晶体管T2的沟道区，第二晶体管T2为双沟道结构，第二有源部62包括第一子有源部621和第二子有源部622，第一子有源部621用于形成第二晶体管的第一沟道，第二子有源部622用于形成第二晶体管T2的第二沟道，有源层还包括第三子有源部623，第三子有源部623连接于第一子有源部621和第二子有源部622之间；第三有源部63可以用于形成驱动晶体管T3的沟道区；第四有源部64可以用于形成第四晶体管T4的沟道区；第五有源部65可以用于形成第五晶体管T5的沟道区；第六有源部66可以用于形成第六晶体管T6的沟道区；第七有源部67可以用于形成第七晶体管T7的沟道区；第十有源部610连接于第六有源部66和第七有源部67之间；第十一有源部611连接于第一有源部61和第二有源部62之间；第十二有源部612连接于第七有源部67远离第六有源部66的一端；第十三有源部613连接于第四有源部64远离第三有源部63的一端；第十四有源部614连接于第一有源部61远离第二有源部62的一端；第十五有源部615连接于第五有源部65远离第四有源部64的一端。其中，有源层可以由多晶硅材料形成，相应的，第一晶体管T1、第二晶体管T2、驱动晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7可以为P型的低温多晶硅薄膜晶体管。
如图25、27、31所示，第一导电层可以包括：多个第一导电部11、第一栅线G1、使能信号线EM、第一复位信号线Re1、第二复位信号线Re2。第一栅线G1在衬底基板上的正投影、使能信号线EM在衬底基板上的正投影、第一复位信号线Re1在衬底基板上的正投影、第二复位信号线Re2在衬底基板上的正投影均可以沿第一方向X延伸，第一方向X和第二方向Y可以相交，例如，第一方向X可以为行方向，第二方向Y可以为列方向。第一栅线G1可以用于提供第一栅极驱动信号端；使能信号线EM可以用于提供使能信号端；第一复位信号线Re1可以用于提供第一复位信号端；第二复位信号线Re2可以用于提供第二复位信号端。其中，第一栅线G1在衬底基板上的正投影覆盖第二有源部62、第四有源部64在衬底基板上的正投影，第一栅线G1的部分结构用于分别形成第二晶体管T2的栅极和第四晶体管的栅极。使能信号线EM在衬底基板上的正投影覆盖第五有源部65在衬底基板上的正投影、第六有源部66在衬底基板上的正投影，使能信号线EM的部分结构可以分别用于形成第五晶体管T5、第六晶体管T6的栅极。第一复位信号线Re1在衬底基板上的正投影覆盖第一有源部61在衬底基板上的正投影，第一复位信号线Re1的部分结构用于形成第一晶体管T1的栅极。第二复位信号线Re2在衬底基板上的正投影可以覆盖第七有源部67在衬底基板上的正投影，第二复位信号线Re2的部分结构可以用于形成第七晶体管T7的栅极。第一导电部11和子像素驱动电路对应设置，第一导电部11在衬底基板上的正投影覆盖与其对应子像素驱动电路中第三有源部63在衬底基板上的正投影，第一导电部11可以用于形成多个驱动晶体管T3的栅极和电容C的第一电极。如图31所示，本行像素驱动电路中的第一复位信号线Re1可以复用为相邻上一行像素驱动电路中的第二复位信号线Re2，该设置可以提高像素驱动电路的集成度，以降低像素驱动电路的布图面积。此外，该显示面板可以利用第一导电层为掩膜对有源层进行导体化处理，即有源层中被第一导电层覆盖的区域可以形成晶体管的沟道区，未被第一导电层覆盖的区域形成导体结构。
如图25、28、32所示，第二导电层可以包括：第一初始信号线Vinit1、第二初始信号线Vinit2、第三导电部23。第一初始信号线 Vinit1在衬底基板上的正投影、第二初始信号线Vinit2在衬底基板上的正投影沿第一方向X延伸，第一初始信号线Vinit1用于提供第一初始信号端，第二初始信号线Vinit2用于提供第二初始信号端。相邻上一行子像素驱动电路中所述第二初始信号线Vinit2在所述衬底基板上的正投影位于本行子像素驱动电路中所述第一复位信号线Re1在所述衬底基板上的正投影和本行子像素驱动电路中所述第一栅线G1在所述衬底基板上的正投影之间。第三导电部23在衬底基板上的正投影和第一导电部11在所述衬底基板上的正投影至少部分交叠，第三导电部23用于形成电容C的第二电极。第二导电层还可以包括:第一凸起部21、第二凸起部22，第一凸起部21连接于所述第二初始信号线Vinit2，所述第一凸起部21在所述衬底基板上的正投影沿所述第二方向Y延伸，且所述第一凸起部21在所述衬底基板上的正投影和所述第十一有源部611在所述衬底基板上的正投影至少部分交叠。第一凸起部21可以对第十一有源部611起到稳压作用，从而降低驱动晶体管栅极的电压波动。第二凸起部22连接于所述第二初始信号线Vinit2，所述第二凸起部22在所述衬底基板上的正投影沿所述第二方向Y延伸，且所述第二凸起部22在所述衬底基板上的正投影和所述第三子有源部623在所述衬底基板上的正投影至少部分交叠。第二凸起部22可以对第三子有源部623起到稳压作用，从而可以改善由于第三子有源部623电压波动而产生向第二晶体管T2源漏极漏电的问题。
如图25、29、33所示，第三导电层可以包括数据线Da、第二桥接部32、第六桥接部36、第七桥接部37、第八桥接部38、第十桥接部310。其中，数据线Da在衬底基板上的正投影沿第二方向Y延伸，数据线Da用于提供数据信号端。数据线Da可以通过过孔(黑色方块)连接第十三有源部613，以连接第四晶体管T4的第一极。第二桥接部32可以分别过孔连接第一导电部11、第十一有源部611，以连接驱动晶体管T3的栅极和第一晶体管T1的第二极、第二晶体管T2的第一极。第三导电部23上可以形成有开口231，连接于第一导电部11和第二桥接部32之间的过孔在衬底基板上的正投影可以位于开口231在衬底基板上的正投影内，以使连接于第一导电部11和第二桥接部32之间的过孔和第三导电部23绝 缘设置。第六桥接部36可以通过过孔连接第十有源部610，以连接第六晶体管T6的第二极。第七桥接部37可以分别通过过孔连接第一初始信号线Vinit1和第十四有源部，以连接第一晶体管的第一极和第一初始信号端。第八桥接部38可以分别通过过孔连接第十二有源部612和第二初始信号线Vinit2，以连接第七晶体管T7的第一极和第二初始信号端。第十桥接部310可以分别通过过孔连接第三导电部23和第十五有源部615，以连接电容的第二电极和第五晶体管的第一极。
如图25、30所示，所述第四导电层可以包括第一桥接部41、第一电源线子部VDD，第一桥接部41可以通过过孔连接同一像素驱动电路中的所有第六桥接部36，第一桥接部41可以用于连接发光单元的第一电极，以连接第六晶体管的第二极和发光单元的第一电极。第一电源线子部VDD包括在衬底基板上的正投影沿第二方向Y延伸的部分和沿第一方向X延伸的部分，第一电源线子部VDD可以用于提供第一电源端，第一电源线子部VDD可以通过过孔连接第十桥接部310，以连接第一电源端和第五晶体管的第一极、电容的第二电极。第一电源线子部VDD包括第二导电部42。第二导电部42可以和所述子像素驱动电路对应设置，所述第二导电部42在所述衬底基板上的正投影和与其对应的所述子像素驱动电路中第二桥接部32在所述衬底基板上的正投影至少部分交叠，且所述第二导电部42通过过孔连接与其对应的所述子像素驱动电路中的第十桥接部310。第二导电部42可以屏蔽其他信号对第二桥接部32的噪音干扰，以提高驱动晶体管栅极电压的稳定性。其中，在同一所述像素驱动电路中，在所述第一方向X上分布的所述第二导电部42可以相连接，相连接的第二导电部42可以降低第一电源线子部VDD的电压，从而降低第一电源线子部VDD上电源信号的压降。
如图34-44所示，图34为本公开显示面板另一种示例性实施例中的结构版图，图35为图34中有源层的结构版图，图36为图34中第一导电层的结构版图，图37为图34中第二导电层的结构版图，图38为图34中第三导电层的结构版图，图39为图34中第四导电层的结构版图，图40为图34中电极层和像素界定层的结构板，图41为图34中有源层、第一导电层的结构版图，图42为图34中有源层、第一导电层、第二导电 层的结构版图，图43为图34中有源层、第一导电层、第二导电层、第三导电层的结构版图，图44为图34中有源层、第一导电层、第二导电层、第三导电层、第四导电层的结构版图。
如图34-44所示，该显示面板可以包括多个像素单元，多个像素单元可以在第一方向X和第二方向Y上阵列分布，图34示出了一个像素单元的版图结构，每个像素单元可以包括在第一方向X上分布的多个像素驱动电路，本示例性实施例中，每个像素单元可以包括在第一方向X上分布的三个像素驱动电路。图34中像素驱动电路可以包括图25所示像素驱动电路的全部结构特征。
如图27、31、34、36、38、41、42所示，多条所述第一复位信号线中包括第一长复位信号线LRe1和第一短复位信号线SRe1，所述第一长复位信号线LRe1和位于同一行的所述子像素驱动电路对应设置，所述第一长复位信号线LRe1连接与其对应的所述子像素驱动电路，所述第一短复位信号线SRe1和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述第一短复位信号线SRe1连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述第一短复位信号线SRe1在所述衬底基板上的正投影在行方向上间隔设置。多条所述第一栅线中包括第一长栅线LG1和第一短栅线SG1，所述第一长栅线LG1和位于同一行的所述子像素驱动电路对应设置，所述第一长栅线LG1连接与其对应的所述子像素驱动电路，所述第一短栅线SG1和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述第一短栅线SG1连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述第一短栅线SG1在所述衬底基板上的正投影在行方向上间隔设置。多条所述使能信号线EM中包括长使能信号线LEM和短使能信号线SEM，所述长使能信号线LEM和位于同一行的所述子像素驱动电路对应设置，所述长使能信号线LEM连接与其对应的所述子像素驱动电路，所述短使能信号线SEM和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述短使能信号线SEM连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述短使能信号线SEM在所述衬底基板上的正投影在行方向上间隔设置。第三导电层还包括第一连接线311、第二连接线 312、第三连接线313；其中，所述第一连接线311、第二连接线312、第三连接线313在所述衬底基板上的正投影沿所述第二方向Y延伸，所述第一连接线311分别通过过孔连接所述第一长复位信号线LRe1和第一短复位信号线SRe1，所述第二连接线312分别通过过孔连接所述第一长栅线LG1和第一短栅线SG1，所述第三连接线313分别通过过孔连接所述长使能信号线LEM和短使能信号线SEM。
如图28、33、34、37、39、42、43所示，多条所述第一初始信号线中包括第一长初始信号线LVinit1和第一短初始信号线SVinit1，所述第一长初始信号线LVinit1和位于同一行的所述子像素驱动电路对应设置，所述第一长初始信号线LVinit1连接与其对应的所述子像素驱动电路，所述第一短初始信号线SVinit1和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述第一短初始信号线SVinit1连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述第一短初始信号线SVinit1在所述衬底基板上的正投影在行方向上间隔设置。多条所述第二初始信号线中包括第二长初始信号线LVinit2和第二短初始信号线SVinit2，所述第二长初始信号线LVinit2和位于同一行的所述子像素驱动电路对应设置，所述第二长初始信号线LVinit2连接与其对应的所述子像素驱动电路，所述第二短初始信号线SVinit2和所述像素驱动电路组中同一行所述子像素驱动电路对应设置，所述第二短初始信号线SVinit2连接与其对应的所述子像素驱动电路，且同一行子像素驱动电路对应的多条所述第二短初始信号线SVinit2在所述衬底基板上的正投影在行方向上间隔设置。所述第三导电层还包括第四连接线314、第五连接线315，所述第四连接线314分别通过过孔连接第一长初始信号线LVinit1和第一短初始信号线SVinit1，所述第五连接线315分别通过过孔连接所述第二长初始信号线LVinit2和第二短初始信号线Svinit2。
如图34、38、43所示，同一像素单元中的三个像素驱动电路形成像素驱动电路组。第三导电层还可以包括第一初始连接线3Vinit1、第二初始连接线3Vinit2。第一初始连接线3Vinit1、第二初始连接线3Vinit2在衬底基板上的正投影沿第二方向Y延伸。第一初始连接线3Vinit1和一列像素驱动电路组对应设置，第一初始连接线3Vinit1通过过孔连接 与其在衬底基板上正投影相交的第一初始连接线，第一初始连接线3Vinit1和第一初始连接线形成网格结构，以降低第一初始信号线上的信号的压降。第二初始连接线3Vinit2和一列像素驱动电路组对应设置，第二初始连接线3Vinit2通过过孔连接与其在衬底基板上正投影相交的第二初始连接线，第二初始连接线3Vinit2和第二初始连接线形成网格结构，以降低第二初始信号线上的信号的压降。像素驱动电路组在所述衬底基板上的正投影位于与其对应的所述第一初始连接线3Vinit1和所述第二初始连接线3Vinit2在所述衬底基板上的正投影之间。
如图30、34、39、44所示，第四导电层还可以包括第一电源连接线4VDD，第一电源连接线4VDD在所述衬底基板上的正投影为环形；其中，第一电源连接线4VDD和像素驱动电路组对应设置，像素驱动电路组在所述衬底基板上的正投影位于与其对应的所述第一电源连接线4VDD在所述衬底基板上的正投影内。第一电源连接线4VDD可以通过过孔连接像素驱动电路组对应的第一电源线子部VDD。本示例性实施例中，环形指首尾相连的线形成的图像，环形可以矩形、圆形、三角形、多边形等。第四导电层还可以第一连接部43，第一连接部43在所述衬底基板上的正投影沿所述第二方向Y延伸，所述第一连接部43连接于在所述第二方向上相邻的所述第二导电部42和所述第一电源连接线4VDD之间。第一连接部43可以进一步降低第一电源线VDD上电源信号的压降。
如图34、38、43所示，所述第三导电层还可以包括：多个第三桥接部33，所述第三桥接部33至少部分结构在所述衬底基板上的正投影位于在所述第二方向Y上相邻的两所述第一电源连接线4VDD在所述衬底基板上的正投影之间，所述第三桥接部33可以分别通过过孔连接与其相邻两所述第一电源连接线。第三桥接部33可以连接在第二方向Y上分布的第一电源连接线4VDD。
如图34、38、43所示，第三导电层还包括电源桥接线3VDD，所述电源桥接线3VDD在所述衬底基板上的正投影沿第二方向Y延伸。其中，所述电源桥接线3VDD至少部分结构在所述衬底基板上的正投影位于在所述第一方向X上相邻两所述第一电源连接线4VDD在所述衬底基板上的正投影之间，且所述电源桥接线3VDD分别通过过孔连接与其相邻的两所述第 一电源连接线4VDD。电源桥接线3VDD可以连接使得在第一方向X上分布的第一电源连接线4VDD相连接。电源桥接线3VDD、第一电源连接线4VDD可以使得第一电源线VDD形成网格结构，以降低第一电源线上电源信号的压降。
如图34、40所示，电极层可以包括多个电极部：第一电极部G、第二电极部B、第三电极部R，各个电极部可以通过过孔连接第一桥接部41，以连接第六晶体管的第二极。像素界定层上形成有多个像素开口PH，所述像素开口PH与所述电极部对应设置，所述像素开口PH在所述衬底基板上的正投影和所述电极部在所述衬底基板上的正投影重合.第一电极部G可以用于形成显示面板中绿色发光单元的电极部，第二电极部B可以用于形成显示面板中蓝色发光单元的电极部，第三电极部R可以用于形成红色发光单元的电极部。
如图34、39、40、44所示，第四导电层还可以包括第二电源连接线4VSS，所述第二电源连接线4VSS和所述第一电源连接线4VDD对应设置，所述第二电源连接线4VSS在所述衬底基板上的正投影为环形，所述第一电源连接线4VDD在所述衬底基板上的正投影位于与其对应的所述第二电源连接线4VSS在所述衬底基板上的正投影内。电极层还可以包括第一电极环5VSS，第一电极环5VSS在衬底基板上的正投影为环形，第一电极环5VSS和第二电源连接线4VSS对应设置，且连接与其对应的第二电源连接线4VSS。显示面板还可以包括公共电极层，公共电极层位于电极层背离衬底基板的一侧，公共电极层可以用于形成发光单元的第二电极，第二电源连接线4VSS可以通过第一电极环5VSS连接公共电极层。第二电源连接线4VSS、第一电极环5VSS可以降低公共电极层上电源信号的压降。
如图45所示，为图34所示显示面板沿虚线CC剖开的部分剖视图。该显示面板还可以包括第一绝缘层92、第二绝缘层93、介电层94、钝化层95、第一平坦层96、第二平坦层97。其中，衬底基板91、有源层、第一绝缘层92、第一导电层、第二绝缘层93、第二导电层、介电层94、第三导电层、钝化层95、第一平坦层96、第四导电层、第二平坦层97、电极层依次层叠设置。第一绝缘层92、第二绝缘层93可以包括氧化硅、氮化硅层中的一层或多层；介电层94可以包括氮化硅层；第一平坦层96、 第二平坦层97的材料可以为有机材料，例如聚酰亚胺(PI)、聚对苯二甲酸乙二醇酯(PET)、聚萘二甲酸乙二醇酯(PEN)、硅-玻璃键合结构(SOG)等材料。钝化层95可以为氧化硅层。衬底基板91可以包括依次层叠设置的玻璃基板、阻挡层、聚酰亚胺层，阻挡层可以为无机材料。第一导电层、第二导电层的材料可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等。第三导电层、第四导电层的材料可以包括金属材料，例如可以是钼、铝、铜、钛、铌其中之一或者合金，或者钼/钛合金或者叠层等，或者可以是钛/铝/钛叠层。电极层可以包括氧化铟锡层、银层。第一导电层、第二导电层中任一导电层的方块电阻可以大于第三导电层、第四导电层中任一导电层的方块电阻。
如图46所示，为本公开显示面板一种示例性实施例的结构示意图。该显示面板的显示区AA可以包括正常显示区A1、压缩区A2、集成区A3，压缩区A2位于正常显示区A1在第一方向X上的一侧，集成区A3位于压缩区A2远离正常显示区A1的一侧。位于正常显示区A1中的像素单元为第一像素单元，位于压缩区A2中的像素单元为第二像素单元。第一像素单元中的像素驱动电路形成第一像素驱动电路组，第二像素单元中的像素驱动电路形成第二像素驱动电路组。第一像素单元的版图结构可以如图12或图34所示。该显示面板中的压缩区A2可以设置一列或多列像素单元。集成区A3可以用于集成栅极驱动电路GOA。
如图47-57所示，图47为图46中右侧第二像素单元的结构版图，图48为图47中有源层的结构版图，图49为图47中第一导电层的结构版图，图50为图47中第二导电层的结构版图，图51为图47中第三导电层的结构版图，图52为图47中第四导电层的结构版图，图53为图47中电极层和像素界定层的结构板，图54为图47中有源层、第一导电层的结构版图，图55为图47中有源层、第一导电层、第二导电层的结构版图，图56为图47中有源层、第一导电层、第二导电层、第三导电层的结构版图，图57为图47中有源层、第一导电层、第二导电层、第三导电层、第四导电层的结构版图。
第二像素单元和第一像素单元主要不同在于：
第二像素单元中没有设置第一初始连接线和第二初始连接线。
第二像素单元靠近集成区A3的一侧没有设置电源桥接线3VDD。
第二像素单元将第一电源连接线4VDD替换为第三电源连接线43VDD，第三电源连接线43VDD靠近集成区A3的一侧开口。
第二像素单元将第二电源连接线4VSS替换为第四电源连接线44VSS，第四电源连接线44VSS在第一方向X上的两侧开口。
第三电源连接线43VDD包括第一侧边4VDD1，第一侧边4VDD1在所述衬底基板上的正投影沿所述第二方向Y延伸且位于与其对应的所述第二像素驱动电路组在所述第一方向X上的一侧，其中，第一像素单元中第一电源连接线4VDD在所述衬底基板上的正投影和所述第一像素驱动电路组在所述衬底基板上的正投影在所述第一方向X上的距离大于所述第一侧边4VDD1在所述衬底基板上的正投影和所述第二像素驱动电路组在所述衬底基板上的正投影在所述第一方向X上的距离。
第二像素单元将第一电极环5VSS替换为第二电极线52VSS，第二电极线52VSS靠近集成区A3的一侧开口。
第二电极线52VSS包括第二侧边5VSS2，所述第二侧边5VSS2至少部分结构在所述衬底基板上的正投影位于所述第一侧边4VDD1在所述衬底基板上的正投影远离所述第二像素驱动电路组在所述衬底基板上的正投影的一侧；其中，所述第一侧边4VDD1在所述衬底基板上的正投影和所述第二侧边5VSS2在所述衬底基板上的正投影在所述第一方向X上的距离小于所述第一电极环5VSS在所述衬底基板上的正投影和所述第一电源连接线4VDD在所述衬底基板上的正投影在所述第一方向X上的距离。如图47所示，第一侧边4VDD1在所述衬底基板上的正投影和所述第二侧边5VSS2在所述衬底基板上的正投影相交，第一侧边4VDD1在所述衬底基板上的正投影和所述第二侧边5VSS2在所述衬底基板上的正投影在第一方向上的距离为0。
上述区别设置可以降低第二像素单元中像素电路层(包括有源层、第一导电层、第二导电层、第三导电层、第四导电层)在第一方向上的尺寸，从而可以空余出设置栅极驱动电路GOA的集成区A3。其中，集成区A3上设置有发光单元。
图46所示显示面板左侧第二像素单元的版图结构可以和右侧像素单 元的版图结构相同或近似。
需要说明的是，如图3、11、12、21、22、25、33、34、43、44、47、56、57所示，画于第三导电层背离衬底基板一侧的黑色方块表示第三导电层连接面向衬底基板一侧的其他层级的过孔；画于第四导电层背离衬底基板一侧的黑色方块表示第四导电层连接面向衬底基板一侧的其他层级的过孔；画于电极层背离衬底基板一侧的黑色方块表示电极层连接面向衬底基板一侧的其他层级的过孔。该黑色方块表示过孔的位置，不同位置黑色方块所表示的不同过孔可以贯穿于不同绝缘层。
需要说明的是，本公开中的附图比例可以作为实际工艺中的参考，但不限于此，例如：沟道的宽长比、各个膜层的厚度和间距、各个信号线的宽度和间距，可以根据实际需要进行调整。显示基板中像素的个数和每个像素中子像素的个数也不是限定为图中所示的数量，本公开中所描述的附图仅是结构示意图。此外，第一、第二等限定词仅用于限定不同的结构名称，其并没有特定顺序和数量的含义。在本示例性实施例中，某一结构在衬底基板上的正投影沿某一方向延伸，可以理解为该结构在衬底基板上的正投影沿该方向直线延伸或弯折延伸。晶体管是指至少包括栅极、漏极以及源极这三个端子的元件。晶体管在漏极(漏电极端子、漏区域或漏电极)与源极(源电极端子、源区域或源电极)之间具有沟道区，并且电流能够流过漏极、沟道区以及源极。在本示例性实施例中，沟道区是指电流主要流过的区域。在本示例性实施例中，第一极可以为漏极、第二极可以为源极，或者第一极可以为源极、第二极可以为漏极。在使用极性相反的晶体管的情况或电路工作中的电流方向变化的情况下，“源极”及“漏极”的功能有时互相调换。因此，在本示例性实施例中，“源极”和“漏极”可以互相调换。另外，栅极还可以称为控制极。
本示例性实施例还提供一种显示装置，其中，包括上述的显示面板。该显示装置可以为手机、平板电脑、电视等显示装置。
本领域技术人员在考虑说明书及实践这里公开的内容后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明 书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。
本公开中的附图只涉及本公开涉及到的结构，其他结构可参考通常设计。在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。本领域的普通技术人员应当理解，可以对本公开的技术方案进行修改或者等同替换，而不脱离本公开技术方案的精神和范围，均应涵盖在本公开的权利要求的范围当中。
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限定。

Claims (28)

  1. 一种像素驱动电路，其中，所述像素驱动电路包括：
    多个驱动晶体管，每个所述驱动晶体管的第二极均连接同一发光单元的第一电极，每个所述驱动晶体管用于根据其栅极电压向所述发光单元输入驱动电流。
  2. 根据权利要求1所述的像素驱动电路，其中，每个所述驱动晶体管的栅极均连接第一节点，每个所述驱动晶体管的第一极均连接第一电源端。
  3. 根据权利要求2所述的像素驱动电路，其中，所述像素驱动电路还包括：
    数据写入电路，连接数据信号端、每个所述驱动晶体管的第一极、第一栅极驱动信号端，用于响应所述第一栅极驱动信号端的信号以将所述数据信号端的信号传输到每个所述驱动晶体管的第一极；
    补偿电路，连接所述第一节点、每个所述驱动晶体管的第二极、第二栅极驱动信号端，用于响应所述第二栅极驱动信号端的信号以连通所述第一节点和每个所述驱动晶体管的第二极；
    发光控制电路，连接所述第一电源端、每个所述驱动晶体管的第一极、使能信号端、每个所述驱动晶体管的第二极、发光单元的第一电极，用于响应所述使能信号端的信号以连通所述第一电源端和每个所述驱动晶体管的第一极，以及用于响应所述使能信号端的信号以连通每个所述驱动晶体管的第二极和所述发光单元的第一电极；
    第一复位电路，连接第一初始信号端、第一复位信号端、所述第一节点，用于响应所述第一复位信号端的信号以将所述第一初始信号端的信号传输到所述第一节点；
    第二复位电路，连接第二初始信号端、第二复位信号端、发光单元的第一电极，用于响应所述第二复位信号端的信号以将所述第二初始信号端的信号传输到所述发光单元的第一电极；
    存储电路，连接于所述第一节点和所述第一电源端之间。
  4. 根据权利要求3所述的像素驱动电路，其中，所述数据写入电路包括：
    第四晶体管，所述第四晶体管的第一极连接所述数据信号端，第二极连接每个所述驱动晶体管的第一极，栅极连接第一栅极驱动信号端；
    所述补偿电路包括:
    第二晶体管，所述第二晶体管的第一极连接所述第一节点，第二极连接每个所述驱动晶体管的第二极，栅极连接所述第二栅极驱动信号端；
    所述发光控制电路包括：
    第五晶体管，第一极连接所述第一电源端，第二极连接每个所述驱动晶体管的第一极，栅极连接所述使能信号端；
    第六晶体管，第一极连接每个所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极，栅极连接所述使能信号端；
    所述第一复位电路包括：
    第一晶体管，第一极连接所述第一初始信号端，第二极连接所述第一节点，栅极连接所述第一复位信号端；
    所述第二复位电路包括：
    第七晶体管，第一极连接第二初始信号端，第二极连接所述发光单元的第一电极，栅极连接所述第二复位信号端；
    所述存储电路包括：
    电容，第一电极连接所述第一节点，第二电极连接所述第一电源端。
  5. 根据权利要求1所述的像素驱动电路，其中，所述像素驱动电路包括多个子像素驱动电路，每个所述子像素驱动电路均包括至少一个所述驱动晶体管，且每个所述子像素驱动电路连接同一所述发光单元，所述子像素驱动电路用于向所述发光单元提供驱动电流。
  6. 根据权利要求5所述的像素驱动电路，其中，所述子像素驱动电路还包括：
    数据写入电路，连接数据信号端、所述驱动晶体管的第一极、第一栅极驱动信号端，用于响应所述第一栅极驱动信号端的信号以将所述数据信号端的信号传输到所述驱动晶体管的第一极；
    补偿电路，连接所述驱动晶体管的栅极、所述驱动晶体管的第二极、第二栅极驱动信号端，用于响应所述第二栅极驱动信号端的信号以连通所述所述驱动晶体管的栅极和所述驱动晶体管的第二极；
    发光控制电路，连接第一电源端、所述驱动晶体管的第一极、使能信号端、所述驱动晶体管的第二极、发光单元的第一电极，用于响应所述使能信号端的信号以连通所述第一电源端和所述驱动晶体管的第一极，以及用于响应所述使能信号端的信号以连通所述驱动晶体管的第二极和所述发光单元的第一电极；
    第一复位电路，连接第一初始信号端、第一复位信号端、所述驱动晶体管的栅极，用于响应所述第一复位信号端的信号以将所述第一初始信号端的信号传输到所述驱动晶体管的栅极；
    第二复位电路，连接第二初始信号端、第二复位信号端、发光单元的第一电极，用于响应所述第二复位信号端的信号以将所述第二初始信号端的信号传输到所述发光单元的第一电极；
    存储电路，连接于所述驱动晶体管的栅极和所述第一电源端之间。
  7. 根据权利要求6所述的像素驱动电路，其中，所述数据写入电路包括：
    第四晶体管，第一极连接所述数据信号端，第二极连接所述驱动晶体管的第一极，栅极连接第一栅极驱动信号端；
    所述补偿电路包括:
    第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，第二极连接所述驱动晶体管的第二极，栅极连接所述第二栅极驱动信号端；
    所述发光控制电路包括：
    第五晶体管，第一极连接所述第一电源端，第二极连接所述驱动晶体管的第一极，栅极连接所述使能信号端；
    第六晶体管，第一极连接所述驱动晶体管的第二极，第二极连接所述发光单元的第一电极，栅极连接所述使能信号端；
    所述第一复位电路包括：
    第一晶体管，第一极连接所述第一初始信号端，第二极连接所述驱动晶体管的栅极，栅极连接所述第一复位信号端；
    所述第二复位电路包括：
    第七晶体管，第一极连接第二初始信号端，第二极连接所述发光单 元的第一电极，栅极连接所述第二复位信号端；
    所述存储电路包括：
    电容，第一电极连接所述驱动晶体管的栅极，第二电极连接所述第一电源端。
  8. 一种显示面板，其中，所述显示面板包括权利要求1-7任一项所述的像素驱动电路。
  9. 一种显示面板，其中，所述显示面板包括发光单元和用于驱动所述发光单元的像素驱动电路，所述像素驱动电路包括多个驱动晶体管，每个所述驱动晶体管的第二极均连接同一发光单元的第一电极，每个所述驱动晶体管用于根据其栅极电压向所述发光单元输入驱动电流；
    所述显示面板还包括:
    衬底基板；
    有源层，位于所述衬底基板的一侧，所述有源层包括多个第三有源部，所述第三有源部用于形成所述驱动晶体管的沟道区。
  10. 根据权利要求9所述的显示面板，其中，所述有源层还包括第八有源部、第九有源部，同一所述像素驱动电路中的所述第三有源部并联于所述第八有源部和所述第九有源部之间。
  11. 根据权利要求10所述的显示面板，其中，所述第八有源部在所述衬底基板上的正投影和所述第九有源部在所述衬底基板上的正投影沿第二方向延伸；
    同一所述像素驱动电路中多个所述第三有源部在所述衬底基板上的正投影沿所述第二方向间隔分布。
  12. 根据权利要求10所述的显示面板，其中，所述显示面板还包括：
    第一导电层，位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括第一导电部，所述第一导电部在所述衬底基板上的正投影覆盖同一所述像素驱动电路每个所述第三有源部在所述衬底基板上的正投影；
    所述第一导电部的至少部分结构分别用于形成所述驱动晶体管的栅极。
  13. 根据权利要求11所述的显示面板，其中，所述像素驱动电路还 包括第四晶体管、第五晶体管，所述第四晶体管的第一极连接数据线，所述第四晶体管的第二极连接所述驱动晶体管的第一极，所述第五晶体管的第一极连接第一电源线，所述第五晶体管的第二极连接所述驱动晶体管第一极；
    所述有源层还包括：
    第四有源部，连接于所述第八有源部的一端，所述第四有源部用于形成所述第四晶体管的沟道区；
    第五有源部，连接于所述第八有源部的另一端，所述第五有源部用于形成所述第五晶体管的沟道区；
    所述显示面板还包括:第一导电层，所述第一导电层位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括：
    第一栅线，所述第一栅线在所述衬底基板上的正投影沿第一方向延伸且覆盖所述第四有源部在所述衬底基板上的正投影，所述第一栅线的部分结构用于形成所述第四晶体管的栅极，所述第一方向和所述第二方向相交；
    使能信号线，所述使能信号线在所述衬底基板上的正投影沿所述第一方向延伸且覆盖所述第五有源部在所述衬底基板上的正投影，所述使能信号线的部分结构用于形成所述第五晶体管的栅极；
    所述第三有源部在所述衬底基板上的正投影位于所述第一栅线在所述衬底基板上的正投影和所述使能信号线在所述衬底基板上的正投影之间。
  14. 根据权利要求9所述的显示面板，其中，所述像素驱动电路包括多个子像素驱动电路，多个所述子像素驱动电路在所述衬底基板上的正投影沿第一方向和/或第二方向阵列分布，所述第一方向和所述第二方向相交；
    每个所述子像素驱动电路均包括所述驱动晶体管，且每个所述子像素驱动电路连接同一所述发光单元，所述子像素驱动电路用于向所述发光单元提供驱动电流；
    所述显示面板还包括：
    有源层，位于所述衬底基板的一侧，所述有源层包括多个第三有源 部，所述第三有源部用于形成所述驱动晶体管的沟道区；
    第一导电层，位于所述有源层背离所述衬底基板的一侧，所述第一导电层包括多个间隔设置的第一导电部，所述第一导电部和所述第三有源部对应设置，所述第一导电部在所述衬底基板上的正投影覆盖与其对应的所述第三有源部在所述衬底基板上的正投影，所述第一导电部用于形成所述驱动晶体管的栅极。
  15. 根据权利要求14所述的显示面板，其中，所述子像素驱动电路还包括第六晶体管、第七晶体管，所述第六晶体管的第一极连接所述驱动晶体管的第二极，所述第六晶体管的第二极连接所述发光单元的第一电极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；
    所述有源层还包括：
    第六有源部，连接于所述第三有源部，所述第六有源部用于形成所述第六晶体管的沟道区；
    第七有源部，连接于所述第六有源部远离所述第三有源部的一端，所述第七有源部用于形成所述第七晶体管的沟道区；
    第十有源部，连接于所述第六有源部和所述第七有源部之间；
    所述显示面板还包括：
    第四导电层，位于所述第一导电层背离所述衬底基板的一侧，所述第四导电部包括第一桥接部，所述第一桥接部分别连接同一所述像素驱动电路中的每一所述第十有源部，且所述第一桥接部连接所述发光单元的第一电极。
  16. 根据权利要求14所述的显示面板，其中，所述子像素驱动电路还包括第一晶体管、第二晶体管、第七晶体管，所述第一晶体管的第一极连接第一初始信号线，所述第一晶体管的第二极连接所述驱动晶体管的栅极，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极，所述第七晶体管的第一极连接第二初始信号线，所述第七晶体管的第二极连接所述发光单元的第一电极；
    所述有源层还包括：
    第一有源部，用于形成所述第一晶体管的沟道区；
    第二有源部，用于形成所述第二晶体管的沟道区；
    所述第一导电层还包括：
    第一复位信号线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第一复位信号线在所述衬底基板上的正投影覆盖所述第一有源部在所述衬底基板上的正投影，所述第一复位信号线的部分结构用于形成所述第一晶体管的栅极；
    第一栅线，在所述衬底基板上的正投影沿所述第一方向延伸，所述第一栅线在所述衬底基板上的正投影覆盖所述第二有源部在所述衬底基板上的正投影，所述第一栅线的部分结构用于形成所述第二晶体管的栅极；
    所述显示面板还包括第二导电层，所述第二导电层位于所述第一导电层背离所述衬底基板的一侧，所述第二导电层包括：
    所述第二初始信号线，相邻上一行子像素驱动电路中所述第二初始信号线在所述衬底基板上的正投影位于本行子像素驱动电路中所述第一复位信号线在所述衬底基板上的正投影和本行子像素驱动电路中所述第一栅线在所述衬底基板上的正投影之间。
  17. 根据权利要求16所述的显示面板，其中，所述有源层还包括：
    第十一有源部，连接于所述第一有源部和所述第二有源部之间；
    所述第二导电层还包括：
    第一凸起部，连接于所述第二初始信号线，所述第一凸起部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第一凸起部在所述衬底基板上的正投影和所述第十一有源部在所述衬底基板上的正投影至少部分交叠。
  18. 根据权利要求16所述的显示面板，其中，所述第二晶体管为双沟道结构，所述第二晶体管的双沟道包括第一沟道和第二沟道，所述第二有源部包括：
    第一子有源部，用于形成所述第二晶体管的第一沟道；
    第二子有源部，用于形成所述第二晶体管的第二沟道；
    所述有源层还包括：
    第三子有源部，连接于所述第一子有源部和所述第二子有源部之间；
    所述第二导电层还包括：
    第二凸起部，连接于所述第二初始信号线，所述第二凸起部在所述衬底基板上的正投影沿所述第二方向延伸，且所述第二凸起部在所述衬底基板上的正投影和所述第三子有源部在所述衬底基板上的正投影至少部分交叠。
  19. 根据权利要求9所述的显示面板，其中，所述显示面板的显示区包括正常显示区，所述显示面板还包括位于所述正常显示区的：
    第四导电层，位于所述有源层背离所述衬底基板的一侧，所述第四导电层包括第一电源连接线，所述第一电源连接线用于向所述像素驱动电路提供高电平电源信号，所述第一电源连接线在所述衬底基板上的正投影为环形。
  20. 根据权利要求19所述的显示面板，其中，所述显示面板还包括：
    第三导电层，位于所述有源层和所述第四导电层之间，所述第三导电层包括电源桥接线，所述电源桥接线在所述衬底基板上的正投影沿第二方向延伸；
    其中，所述第一电源连接线至少部分结构在所述衬底基板上的正投影位于在第一方向上相邻两个电源桥接线在所述衬底基板上的正投影之间，且所述电源桥接线分别通过过孔连接所述第一电源连接线，所述第一方向和所述第二方向相交。
  21. 根据权利要求19所述的显示面板，其中，所述像素驱动电路包括第五晶体管，所述第五晶体管的第一极连接第一电源线，所述第五晶体管的第二极连接所述驱动晶体管的第一极；
    所述显示面板还包括：
    第三导电层，位于所述有源层和所述第四导电层之间，所述第三导电层包括所述第一电源线；
    其中，所述第一电源线在所述衬底基板上的正投影沿第二方向延伸，所述第一电源线在所述衬底基板上的正投影和所述第一电源连接线在所述衬底基板上的正投影至少部分交叠，且所述第一电源线通过过孔连接所述第一电源连接线。
  22. 根据权利要求19所述的显示面板，其中，所述像素驱动电路包括多个子像素驱动电路，多个所述子像素驱动电路在所述衬底基板上的正投影沿第一方向和/或第二方向阵列分布，所述第一方向和所述第二方向相交；
    每个所述子像素驱动电路均包括所述驱动晶体管，且每个所述子像素驱动电路连接同一所述发光单元，所述子像素驱动电路用于向所述发光单元提供驱动电流；
    所述子像素驱动电路还包括第五晶体管，所述第五晶体管的第一极连接第一电源线子部，所述第五晶体管的第二极连接所述驱动晶体管的第一极；
    所述第四导电层还包括所述第一电源线子部，所述第一电源线子部在所述衬底基板上的正投影包括沿所述第二方向延伸的部分和延所述第一方向延伸的部分，所述第一电源线子部和所述像素驱动电路对应设置，所述第一电源线子部连接与其对应的所述像素驱动电路中每个所述第五晶体管的第一极，且所述第一电源线子部连接所述第一电源连接线。
  23. 根据权利要求22所述的显示面板，其中，所述子像素驱动电路还包括第二晶体管，所述第二晶体管的第一极连接所述驱动晶体管的栅极，所述第二晶体管的第二极连接所述驱动晶体管的第二极；
    所述显示面板还包括：
    第三导电层，位于所述有源层和所述第四导电层之间，所述第三导电层包括第二桥接部，所述第二桥接部连接所述驱动晶体管的栅极和第二晶体管的第二极；
    所述第一电源线子部包括：
    多个第二导电部，所述第二导电部和所述子像素驱动电路对应设置，所述第二导电部在所述衬底基板上的正投影和与其对应的所述子像素驱动电路中第二桥接部在所述衬底基板上的正投影至少部分交叠，且所述第二导电部连接与其对应的所述子像素驱动电路中所述第五晶体管的第一极。
  24. 根据权利要求23所述的显示面板，其中，所述第四导电层还包括：
    第一连接部，所述第一连接部在所述衬底基板上的正投影沿所述第二方向延伸，所述第一连接部连接于在所述第二方向上相邻的所述第二导电部和所述第一电源连接线之间。
  25. 根据权利要求19所述的显示面板，其中，所述第四导电层还包括：
    第二电源连接线，所述第一电源连接线在所述衬底基板上的正投影位于与其对应的所述第二电源连接线在所述衬底基板上的正投影以内；
    所述显示面板还包括：
    公共电极层，位于所述第四导电层背离所述衬底基板的一侧，所述公共电极层用于形成所述发光单元的第二电极，所述第二电源连接线通过过孔连接所述公共电极层。
  26. 根据权利要求19所述的显示面板，其中，所述显示面板的显示区还包括压缩区，所述压缩区位于所述正常显示区在第一方向上的一侧；
    所述显示面板还包括：
    多个像素单元，多个所述像素单元中包括第一像素单元和第二像素单元，所述第一像素单元位于所述正常显示区，所述第一像素单元包括在第一方向上分布的多个像素驱动电路，同一所述第一像素单元中的像素驱动电路形成第一像素驱动电路组，所述第二像素单元位于所述压缩区，所述第二像素单元包括在第一方向上分布的多个像素驱动电路，同一所述第二像素单元中的像素驱动电路形成第二像素驱动电路组；
    所述第四导电层还包括：
    第三电源连接线，所述第三电源连接线用于向所述像素驱动电路提供高电平电源信号，所述第三电源连接线和所述第二像素驱动电路组对应设置，所述第三电源连接线包括第一侧边，所述第一侧边在所述衬底基板上的正投影沿第二方向延伸且位于与其对应的所述第二像素驱动电路组在所述衬底基板上的正投影在所述第一方向上的一侧，所述第一方向和所述第二方向相交；
    其中，所述第一电源连接线在所述衬底基板上的正投影和所述第一像素驱动电路组在所述衬底基板上的正投影在所述第一方向上的距离大 于所述第一侧边在所述衬底基板上的正投影和所述第二像素驱动电路组在所述衬底基板上的正投影在所述第一方向上的距离。
  27. 根据权利要求26所述的显示面板，其中，所述第四导电层还包括：
    第二电源连接线，所述第一电源连接线在所述衬底基板上的正投影位于与其对应的所述第二电源连接线在所述衬底基板上的正投影以内；
    第四电源连接线，所述第四电源连接线和所述第三电源连接线对应设置；
    所述显示面板还包括：
    公共电极层，位于所述第四导电层背离所述衬底基板的一侧，所述公共电极层用于形成所述发光单元的第二电极，所述第二电源连接线和所述第四电源连接线均与所述公共电极层电连接；
    电极层，位于所述第四导电层和所述公共电极层之间，所述电极层包括第一电极环和第二电极线；
    所述第一电极环连接于所述第二电源连接线和所述公共电极层之间，所述第一电极环在所述衬底基板上的正投影为环形，所述第一电源连接线在所述衬底基板上的正投影位于所述第一电极环在所述衬底基板上的正投影内；
    所述第二电极线连接于所述第四电源连接线和所述公共电极层之间，所述第二电极线包括第二侧边，所述第二侧边至少部分结构在所述衬底基板上的正投影位于所述第一侧边在所述衬底基板上的正投影远离所述第二像素驱动电路组在所述衬底基板上的正投影的一侧；
    所述第一侧边在所述衬底基板上的正投影和所述第二侧边在所述衬底基板上的正投影在所述第一方向上的距离小于所述第一电源连接线在所述衬底基板上的正投影和所述第一电极环在所述衬底基板上的正投影在所述第一方向上的距离。
  28. 一种显示装置，其中，所述显示装置包括权利要求9-27任一项所述的显示面板。
PCT/CN2023/079025 2023-03-01 2023-03-01 像素驱动电路、显示面板及显示装置 Ceased WO2024178673A1 (zh)

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