WO2024178648A1 - 显示面板及显示装置 - Google Patents

显示面板及显示装置 Download PDF

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Publication number
WO2024178648A1
WO2024178648A1 PCT/CN2023/078868 CN2023078868W WO2024178648A1 WO 2024178648 A1 WO2024178648 A1 WO 2024178648A1 CN 2023078868 W CN2023078868 W CN 2023078868W WO 2024178648 A1 WO2024178648 A1 WO 2024178648A1
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WO
WIPO (PCT)
Prior art keywords
pattern
base substrate
layer
circuit
insulating layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2023/078868
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English (en)
French (fr)
Other versions
WO2024178648A9 (zh
Inventor
何庆
王世龙
王梦奇
陈文波
燕青青
王格
蒋志亮
方芳
袁晓敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202380007962.7A priority Critical patent/CN118872416A/zh
Priority to PCT/CN2023/078868 priority patent/WO2024178648A1/zh
Priority to US18/567,143 priority patent/US12672439B2/en
Publication of WO2024178648A1 publication Critical patent/WO2024178648A1/zh
Publication of WO2024178648A9 publication Critical patent/WO2024178648A9/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/82—Interconnections, e.g. terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass

Definitions

  • the present application relates to the field of display technology, and in particular to a display panel and a display device.
  • the display panel generally has a display area and a peripheral area surrounding the display area.
  • the display panel generally includes a plurality of pixel units located in the display area, a driving circuit located in the peripheral area for providing a driving signal to the pixel units, and a power supply line located in the peripheral area for providing a negative power supply signal to the cathode layer of the display panel.
  • the negative power supply signal is generally referred to as a VSS signal
  • the power supply line is generally referred to as a VSS line.
  • the present application provides a display panel and a display device, and the technical solution is as follows:
  • a display panel comprising:
  • a base substrate having a display area and a peripheral area surrounding the display area;
  • a plurality of pixel units are located in the display area, wherein the pixel units include a light-emitting unit, and the light-emitting unit includes a first electrode layer, a light-emitting layer and a second electrode layer stacked in sequence;
  • a blocking structure located in the peripheral area and surrounding the plurality of pixel units
  • a transfer structure located in the peripheral region, the transfer structure and the first electrode layer are located in the same layer with a gap therebetween, and the transfer structure is electrically connected to the second electrode layer;
  • a first insulating layer is located between the first electrode layer and the base substrate, and a portion of the first insulating layer located in the peripheral area has a via hole;
  • a circuit structure is located in the peripheral area, the circuit structure includes a first circuit structure located in the area surrounded by the blocking structure, the first circuit structure includes a first circuit sub-pattern and a second circuit sub-pattern, the first circuit sub-pattern is located in the first metal layer, the second circuit sub-pattern is located in the second metal layer, the first metal layer and the second metal layer are located on both sides of the first insulating layer, the via hole of the first insulating layer includes a first via hole, and the first circuit sub-pattern and the second circuit sub-pattern are connected. electrically connected through the first via hole;
  • a second insulating layer is located on a side of the second metal layer away from the substrate;
  • a third insulating layer located on a side of the second insulating layer away from the base substrate includes a main pattern located in the display area and the peripheral area, the main pattern includes a third side surface located in the peripheral area; the orthographic projection of the third side surface on the base substrate is located within the orthographic projection of the blocking structure on the base substrate, and the portion of the main pattern located in the peripheral area is a continuous pattern on the side of the third side surface close to the display area.
  • the blocking structure includes a first blocking dam and a second blocking dam; the first blocking dam is closer to the plurality of pixel units than the second blocking dam, and a thickness of the first blocking dam is less than a thickness of the second blocking dam;
  • the transfer structure comprises a first side surface and a second side surface opposite to each other, wherein the first side surface is closer to the plurality of pixel units than the second side surface;
  • the orthographic projection of the second side surface on the base substrate is located within the orthographic projection of the first blocking dam on the base substrate, and the orthographic projection of the switching structure on the base substrate does not overlap with the orthographic projection of the second blocking dam on the base substrate.
  • the circuit structure further includes a second circuit structure located between the first barrier dam and the second barrier dam;
  • the second circuit structure includes a third circuit sub-pattern and a fourth circuit sub-pattern, the third circuit sub-pattern is located in the first metal layer, the fourth circuit sub-pattern is located in the second metal layer, the via hole of the first insulating layer includes a second via hole, and the third circuit sub-pattern and the fourth circuit sub-pattern are electrically connected through the second via hole.
  • the blocking structure includes a first blocking dam and a second blocking dam; the first blocking dam is closer to the plurality of pixel units than the second blocking dam, and a thickness of the first blocking dam is less than a thickness of the second blocking dam;
  • the transfer structure comprises a first side surface and a second side surface opposite to each other, wherein the first side surface is closer to the plurality of pixel units than the second side surface;
  • the orthographic projection of the second side surface on the base substrate is located within the orthographic projection of the second blocking dam on the base substrate, and the orthographic projection of the switching structure on the base substrate overlaps with the orthographic projection of the first blocking dam on the base substrate.
  • the circuit structure further includes a A second circuit structure
  • the second circuit structure includes a third circuit sub-pattern and a fourth circuit sub-pattern, the via hole of the first insulating layer includes a second via hole, and the third circuit sub-pattern and the fourth circuit sub-pattern are electrically connected through the second via hole;
  • the display panel further includes: a protection layer located on the base substrate, the protection layer includes a plurality of protection patterns, and the orthographic projection of the protection pattern on the base substrate covers the orthographic projection of the second via hole on the base substrate.
  • the plurality of protection patterns are located in the third insulating layer.
  • the protective layer is a third metal layer located on a side of the second insulating layer away from the base substrate;
  • the plurality of metal patterns included in the third metal layer are the plurality of protection patterns, and the orthographic projections of the metal patterns on the base substrate cover the orthographic projections of the second via holes on the base substrate.
  • the protective layer is an active layer located between the substrate and the first metal layer;
  • the plurality of active patterns included in the active layer are the plurality of protection patterns, and the orthographic projections of the active patterns on the base substrate cover the orthographic projections of the second via holes on the base substrate.
  • the protective layer is a light shielding layer located between the base substrate and the first metal layer;
  • the plurality of light-shielding patterns included in the light-shielding layer are the plurality of protection patterns, and the orthographic projections of the light-shielding patterns on the base substrate cover the orthographic projections of the second via holes on the base substrate.
  • a difference between an area of an orthographic projection of the protection pattern on the base substrate and an area of an orthographic projection of the second via hole on the base substrate ranges from 1 square micrometer to 50 square micrometers.
  • the plurality of second via holes include a plurality of target second via holes, and the orthographic projections of the plurality of target second via holes on the base substrate are covered by the orthographic projections of the same protection pattern on the base substrate;
  • a gap between any target second via hole and another target second via hole among the plurality of target second via holes is less than 4 micrometers.
  • the circuit structure further includes a second circuit structure located between the first barrier dam and the second barrier dam;
  • the second circuit structure includes a third circuit sub-pattern and a fourth circuit sub-pattern, the via hole of the first insulating layer includes a second via hole, and the third circuit sub-pattern and the fourth circuit sub-pattern are connected through the The second via is electrically connected;
  • the transfer structure includes a plurality of openings, and the orthographic projections of the openings on the base substrate cover the orthographic projections of the second via holes on the base substrate.
  • a difference between an area of an orthographic projection of the opening on the base substrate and an area of an orthographic projection of the second via hole on the base substrate ranges from 1 square micrometer to 50 square micrometers.
  • the plurality of second via holes include a plurality of target second via holes, and the orthographic projections of the plurality of target second via holes on the base substrate are covered by the orthographic projection of the same opening on the base substrate;
  • a gap between any target second via hole and another target second via hole among the plurality of target second via holes is less than 4 micrometers.
  • the third insulating layer further includes: a first insulating pattern; the display panel further includes a fourth insulating layer located on a side of the third insulating layer away from the base substrate, the fourth insulating layer including a second insulating pattern and a third insulating pattern;
  • the first barrier dam includes at least the second insulating pattern
  • the second barrier dam includes at least a first insulating pattern and a second insulating pattern stacked in a direction away from the base substrate.
  • an edge of the transfer structure on the base substrate away from the display area is closer to the display area than an edge of the blocking structure on the base substrate away from the display area;
  • An orthographic projection of the main body pattern on the base substrate does not overlap with an orthographic projection of the second blocking dam on the base substrate.
  • the display panel further includes: at least one first power line;
  • the at least one first power line is located in the peripheral area, and the at least one first power line includes a first part and a second part, the first part is located on a side of the blocking structure away from the multiple pixel units, and is used to receive a first power signal, and the second part surrounds the multiple pixel units and is electrically connected to the first part and the switching structure, respectively.
  • a display panel comprising:
  • a base substrate having a display area and a peripheral area surrounding the display area;
  • a plurality of pixel units are located in the display area, wherein the pixel units include a light-emitting unit, and the light-emitting unit includes a first electrode layer, a light-emitting layer and a second electrode layer stacked in sequence;
  • a blocking structure located in the peripheral area and surrounding the plurality of pixel units
  • a transfer structure located in the peripheral region, the transfer structure and the first electrode layer are located in the same layer with a gap therebetween, and the transfer structure is electrically connected to the second electrode layer;
  • a first insulating layer is located between the first electrode layer and the base substrate, and a portion of the first insulating layer located in the peripheral area has a via hole;
  • circuit structure located in the peripheral area, the circuit structure comprising a first circuit structure located between the first barrier dam and the display area, the first circuit structure comprising a first circuit sub-pattern and a second circuit sub-pattern, the first sub-circuit pattern being located in a first metal layer, the second circuit sub-pattern being located in a second metal layer, the first metal layer and the second metal layer being located on both sides of the first insulating layer, the via hole of the first insulating layer comprising a first via hole, the first circuit sub-pattern and the second circuit sub-pattern being electrically connected through the first via hole;
  • a second insulating layer is located on a side of the second metal layer away from the substrate;
  • a third insulating layer located on a side of the second insulating layer away from the base substrate, the third insulating layer comprising a main body pattern located in the display area and the peripheral area, the main body pattern comprising a third side surface located in the peripheral area; an orthographic projection of the third side surface on the base substrate being located between the blocking structure and the display area;
  • the protection layer comprises a plurality of protection patterns
  • the orthographic projections of the protection patterns on the base substrate cover the orthographic projections of the first via holes on the base substrate.
  • a display panel comprising:
  • a base substrate having a display area and a peripheral area surrounding the display area;
  • a plurality of pixel units are located in the display area, wherein the pixel units include a light-emitting unit, and the light-emitting unit includes a first electrode layer, a light-emitting layer and a second electrode layer stacked in sequence;
  • a blocking structure located in the peripheral area and surrounding the plurality of pixel units
  • a transfer structure located in the peripheral region, the transfer structure and the first electrode layer are located in the same layer with a gap therebetween, and the transfer structure is electrically connected to the second electrode layer;
  • a first insulating layer is located between the first electrode layer and the base substrate, and a portion of the first insulating layer located in the peripheral area has a via hole;
  • a circuit structure is located in the peripheral area, the circuit structure includes a first circuit structure located between the first barrier dam and the display area, the first circuit structure includes a first circuit sub-pattern and a second circuit sub-pattern, the first sub-circuit pattern is located in the first metal layer, and the second circuit sub-pattern Located in the second metal layer, the first metal layer and the second metal layer are located on both sides of the first insulating layer, the via hole of the first insulating layer includes a first via hole, and the first circuit sub-pattern and the second circuit sub-pattern are electrically connected through the first via hole;
  • a second insulating layer is located on a side of the second metal layer away from the substrate;
  • a third insulating layer located on a side of the second insulating layer away from the base substrate, the third insulating layer comprising a main body pattern located in the display area and the peripheral area, the main body pattern comprising a third side surface located in the peripheral area; an orthographic projection of the third side surface on the base substrate being located between the first blocking dam and the display area;
  • the transfer structure includes a plurality of openings, and the orthographic projections of the openings on the base substrate cover the orthographic projections of the first via holes on the base substrate.
  • a display device comprising: a power supply component and the display panel as described in the above aspect;
  • the power supply component is used to supply power to the display panel.
  • FIG1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • FIG2 is a partial cross-sectional view of a peripheral area of a display panel provided by an embodiment of the present application.
  • FIG3 is a schematic structural diagram of a substrate provided in an embodiment of the present application.
  • FIG4 is a schematic diagram of the structure of a light-emitting unit provided in an embodiment of the present application.
  • FIG5 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG6 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG7 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG8 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG9 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG10 is a partial cross-sectional view of a display panel provided in an embodiment of the present application.
  • FIG11 is a schematic diagram of the structure of another display panel provided in an embodiment of the present application.
  • FIG12 is an equivalent circuit diagram of a pixel circuit provided in an embodiment of the present application.
  • FIG13 is an equivalent circuit diagram of a shift register unit provided in an embodiment of the present application.
  • FIG14 is a schematic diagram of the layout of the shift register unit shown in FIG13 on a display panel
  • FIG15 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG16 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG17 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG18 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG19 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG20 is a partial schematic diagram of a peripheral area of a display panel provided in an embodiment of the present application.
  • FIG21 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG22 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG23 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG24 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG25 is a partial cross-sectional view of a peripheral area of another display panel provided by an embodiment of the present application.
  • FIG26 is a partial schematic diagram of a peripheral area of a transfer structure provided in an embodiment of the present application.
  • FIG27 is a partial schematic diagram of another display panel in a peripheral area provided by an embodiment of the present application.
  • FIG. 28 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • At least one circuit structure in the driving circuit includes a first metal pattern in a first metal layer in a display panel and a second metal pattern in a second metal layer.
  • An insulating layer is provided between the first metal layer and the second metal layer, and the first metal pattern and the second metal pattern are overlapped through vias in the insulating layer.
  • Another insulating layer is provided between the switching structure located in the anode layer and the second metal pattern of the circuit structure to insulate the switching structure from the signal line.
  • the other insulating layer at the overlapping position of the first metal pattern and the second metal pattern is easily over-etched, it may cause the transfer structure and the circuit structure to be short-circuited, and the yield of the display panel is low.
  • the display panel includes a base substrate, a circuit structure and a transfer structure located in the peripheral area of the base substrate, and a first insulating layer and a second insulating layer located on the base substrate.
  • the circuit structure includes a first circuit pattern (the first circuit pattern is located in the first metal layer) and a second circuit pattern (the second circuit pattern is located in the second metal layer) located on both sides of the first insulating layer, respectively, and electrically connected through vias in the first insulating layer.
  • the second insulating layer is located between the second metal layer and the transfer structure, and is used to insulate the circuit structure from the transfer structure.
  • the display panel further includes a third metal layer located in the display area of the base substrate.
  • the third metal layer is located between the second insulating layer and the transfer structure.
  • the process of preparing the third metal layer includes: forming a third metal film on the side of the second insulating layer away from the base substrate, coating a photoresist on the side of the third metal film away from the base substrate, exposing the photoresist using a mask, developing the exposed photoresist, etching the third metal film not protected by the photoresist using an etching solution, removing the remaining photoresist, and then obtaining the third metal layer.
  • the portion of the third metal film located in the peripheral area needs to be etched by the etching solution. Since the peripheral area is designed with a circuit structure (the first metal pattern and the second metal pattern of the circuit structure are electrically connected through the vias of the first insulating layer), when etching the third metal film, it is easy for the etching solution to gather at the position of the via, causing the portion of the second insulating layer located at the via to be over-etched (the thickness of the second insulating layer is usually thin and is easily penetrated by the etching solution).
  • the second insulating layer will lose the effect of insulating the circuit structure and the transfer structure, thereby causing the transfer structure to be in direct contact with the second circuit pattern in the circuit structure and short-circuited, resulting in a low yield of the display panel.
  • FIG1 is a schematic diagram of the structure of a display panel provided in an embodiment of the present application.
  • FIG2 is a partial cross-sectional view of a display panel in a peripheral area provided in an embodiment of the present application.
  • the display panel 10 may include: a base substrate 101, a plurality of pixel units 102, a blocking structure 103, a transfer structure 104, a first insulating layer 105, a circuit structure 106, a second insulating layer 107, and a third insulating layer 108 located on a side of the second insulating layer 107 away from the base substrate 101.
  • FIG2 may be a cross-sectional view of FIG1 along the AA direction.
  • FIG3 is a schematic diagram of the structure of a substrate provided by an embodiment of the present application.
  • the substrate 101 may have a display area 101a and a peripheral area 101b surrounding the display area 101a. 1 to 3 , the plurality of pixel units 102 are located in the display region 101 a , and the blocking structure 103 , the transfer structure 104 and the circuit structure 106 are all located in the peripheral region 101 b .
  • the pixel unit 102 includes a light emitting unit 1021.
  • the light emitting unit 1021 includes a first electrode layer a1, a light emitting layer a2 and a second electrode layer a3 stacked in sequence.
  • the first electrode layer a1 is an anode layer
  • the second electrode layer a3 is a cathode layer.
  • the blocking structure 103 can surround a plurality of pixel units 102.
  • the transfer structure 104 is located in the same layer as the first electrode layer a1 and has a gap therebetween, and the transfer structure 104 is electrically connected to the second electrode layer a3. That is, the transfer structure 104 and the first electrode layer a1 are made of the same material and are prepared by the same patterning process.
  • the signals transmitted by the transfer structure 104 and the second electrode layer a3 are the same signals.
  • the circuit structure 106 is located in the peripheral region 101b, and the circuit structure 106 includes a first circuit structure 106a, and the first circuit structure 106a includes a first circuit sub-pattern b11 and a second circuit sub-pattern b22.
  • the first circuit sub-pattern b11 is located in the first metal layer
  • the second circuit sub-pattern b22 is located in the second metal layer
  • the first insulating layer 105 included in the display panel 10 is located between the first metal layer and the second metal layer.
  • the portion of the first insulating layer 105 located in the peripheral region 101b has a via hole (the via hole includes a first via hole c1), and the first circuit sub-pattern b11 and the second circuit sub-pattern b22 are electrically connected through the first via hole c1.
  • the second insulating layer 107 is located on the side of the second metal layer away from the base substrate 101, and is used to insulate the second circuit sub-pattern b22 in the second metal layer from the transfer structure 104 located in the same layer as the first electrode layer a1.
  • the third insulating layer 108 includes a main body pattern 1081 located in the display area 101a and the peripheral area 101b, and the main body pattern 1081 includes a third side surface 1081a located in the peripheral area 101b.
  • the orthographic projection of the third side surface 1081a on the base substrate 101 is located within the orthographic projection of the blocking structure 103 on the base substrate 101.
  • the portion of the main body pattern 1081 located in the peripheral area 101b is a continuous pattern on the side of the third side surface 1081a close to the display area 101a.
  • the orthographic projection of the main pattern 1081 on the base substrate 101 can cover the orthographic projection of the first via c1 on the base substrate 101, thereby enabling the main pattern 1081 to protect the position of the first via c1.
  • the second insulating layer 107 at the first via c1 is over-etched, it will not cause the second circuit sub-pattern b22 of the transfer structure 104 and the first circuit structure 106a to be short-circuited, thereby ensuring the yield of the display panel 10.
  • an embodiment of the present application provides a display panel, which includes a substrate.
  • the first insulating layer is located between a first circuit sub-pattern and a second circuit sub-pattern of the first circuit structure, and has a first via hole, and the first circuit sub-pattern and the second circuit sub-pattern are electrically connected through the first via hole.
  • the orthographic projection of the third insulating layer on the base substrate covers the orthographic projection of the first via hole on the base substrate, even if the second insulating layer at the first via hole is over-etched, it will not cause the switching structure and the second circuit sub-pattern of the first circuit structure to be short-circuited, thereby ensuring the yield of the display panel.
  • the portion of the main pattern 1081 of the third insulating layer 108 located in the peripheral area 101b is a continuous pattern on the third side 1081a close to the display area 101a, which can be used to indicate that the portion of the main pattern 1081 located in the left and right side areas of the peripheral area 101b (such as the second area 101b2 and the fourth area 101b4 described below) is a continuous pattern on the third side 1081a close to the display area 101a.
  • the blocking structure 103 may be a ring-shaped structure surrounding a plurality of pixel units 102, and is used to block the overflow of the organic layer in the area surrounded by the blocking structure 103 in the display panel 10.
  • the blocking structure 103 includes a first blocking dam 1031 and a second blocking dam 1032.
  • the first blocking dam 1031 is closer to the plurality of pixel units 102 than the second blocking dam 1032, and the thickness of the first blocking dam 1031 is less than the thickness of the second blocking dam 1032.
  • the blocking structure 103 may also include one blocking dam, or more than two blocking dams, which is not limited in the embodiment of the present application.
  • the orthographic projections of the first barrier dam 1031 and the second barrier dam 1032 on the substrate 101 may be annular.
  • the first barrier dam 1031 being closer to the plurality of pixel units 102 relative to the second barrier dam 1032 may be used to indicate that the area enclosed by the first barrier dam 1031 is within the area enclosed by the second barrier dam 1032.
  • the edge of the transfer structure 104 on the base substrate 101 away from the display area 101a is closer to the display area 101a than the edge of the blocking structure 103 on the base substrate 101 away from the display area 101a.
  • the edge of the blocking structure 103 on the base substrate 101 away from the display area 101a may refer to the edge of the second blocking dam 1032 on the base substrate 101 away from the display area 101a.
  • the first circuit structure 106a included in the circuit structure 106 may be located at the first blocking dam 1031 and the display area 101a.
  • the circuit structure 106 further includes a second circuit structure 106b located between the first blocking dam 1031 and the second blocking dam 1032.
  • the second circuit structure 106b includes a third circuit sub-pattern b33 and a fourth circuit sub-pattern b44
  • the via hole of the first insulating layer 105 includes a second via hole c2
  • the third circuit sub-pattern b33 and the fourth circuit sub-pattern b44 are electrically connected through the second via hole c2.
  • the first circuit structure 106a may be a related structure in a gate driver on array (GOA) circuit in the display panel 10.
  • the second circuit structure 106b may be a related structure in a signal input circuit in the display panel that provides a related signal to the GOA circuit.
  • GOA gate driver on array
  • the transfer structure 104 may include a first side surface 104a and a second side surface 104b opposite to each other, and the first side surface 104a is closer to the plurality of pixel units 102 than the second side surface 104b.
  • the orthographic projection of the second side surface 104b on the substrate 101 is located within the orthographic projection of the first barrier dam 1031 on the substrate 101, and the orthographic projection of the transfer structure 104 on the substrate 101 does not overlap with the orthographic projection of the second barrier dam 1032 on the substrate 101. That is, the transfer structure 104 may be located in the area between the first barrier dam 1031 and the display area 101a, but not in the area between the first barrier dam 1031 and the second barrier dam 1032.
  • the orthographic projection of the second side surface 104b (boundary) of the transfer structure 104 on the base substrate 101 is located within the orthographic projection of the first blocking dam 1031 on the base substrate 101, there is a risk of short circuit between the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106a, but there is no risk of short circuit between the transfer structure 104 and the fourth circuit sub-pattern b44 of the second circuit structure 106b.
  • the third insulating layer 108 can be provided between the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106a in addition to the second insulating layer 107.
  • the third insulating layer 108 can play a role in insulating the transfer structure 104 from the second circuit sub-pattern b22.
  • the second insulating layer 107 at the first via c1 is over-etched (such as the second circuit sub-pattern b22 of the first circuit structure 106a is exposed due to the over-etching of the second insulating layer 107), since the third insulating layer 108 can cover the over-etched area of the second insulating layer 107, the short circuit between the transfer structure 104 and the second circuit sub-pattern b22 can be avoided, thereby ensuring the yield of the display panel 10.
  • the transfer structure 104 may include a first side surface 104a and a second side surface 104b opposite to each other, wherein the first side surface 104a is closer to the plurality of pixel units 102 than the second side surface 104b.
  • the orthographic projection of the second side surface 104b on the substrate 101 is located at the position of the second blocking dam 1032.
  • the orthographic projection of the transfer structure 104 on the base substrate 101 overlaps with the orthographic projection of the first barrier dam 1031 on the base substrate 101. That is, the transfer structure 104 can be located in the area between the first barrier dam 1031 and the display area 101a, and also in the area between the first barrier dam 1031 and the second barrier dam 1032.
  • the orthographic projection of the third side surface 1081a of the main pattern 1081 included in the third insulating layer 108 on the base substrate 101 is located within the orthographic projection of the first blocking dam 1031 on the base substrate 101. Therefore, the main pattern 1081 of the third insulating layer can protect the second circuit sub-pattern b22 of the first circuit structure 106a, but cannot protect the fourth circuit sub-pattern b44 of the second circuit structure 106b.
  • the display panel 10 may further include: a protective layer M located on the base substrate 101, the protective layer M including a plurality of protective patterns.
  • the orthographic projection of the protective pattern on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the protective layer M may be located between the first metal layer and the base substrate 101, or the protective layer M may be located on the side of the second insulating layer 107 away from the base substrate 101.
  • the protective layer M it is possible to either prevent the second insulating layer 107 at the second via hole c2 from being overetched, or even if the second insulating layer 107 at the second via hole c2 is overetched, it will not cause the fourth circuit pattern b44 of the transfer structure 104 and the second circuit structure 106b to be short-circuited, thereby ensuring the yield of the display panel 10.
  • the protective layer M may have the following optional implementation modes:
  • the multiple protection patterns included in the protection layer M are located on the third insulating layer 108. That is, the multiple protection patterns of the protection layer M can be made of the same material and by the same patterning process as the main pattern 1081 of the third insulating layer 108.
  • the fourth insulating pattern 1083 included in the third insulating layer 108 is the protection pattern.
  • a fourth insulating pattern 1083 is designed above the second insulating layer 107 at the second via hole c2, and the fourth insulating pattern 1083 can insulate the transfer structure 104 from the fourth circuit sub-pattern b44. Therefore, even if the second insulating layer 107 at the second via hole c2 is overetched (for example, the fourth circuit sub-pattern b44 of the second circuit structure 106b is exposed due to the overetching of the second insulating layer 107), The fourth insulating pattern 1083 of the third insulating layer 108 can cover the over-etched area of the second insulating layer 107, thereby avoiding the short circuit between the transfer structure 104 and the fourth circuit sub-pattern b44, thereby ensuring the yield of the display panel 10.
  • the protection layer M is a third metal layer 109 located on a side of the second insulating layer 107 away from the base substrate 101.
  • the third metal layer 109 includes a plurality of metal patterns 1091 which are protection patterns.
  • the orthographic projection of the metal pattern 1091 on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the third metal layer 109 may be a second source and drain electrode layer of the display panel.
  • the third metal layer 109 is not located in the peripheral region 101b. Therefore, when the third metal film used to form the third metal layer 109 is etched with an etching solution, the portion of the third metal film located in the peripheral region 101b needs to be etched away. However, in the process of etching the third metal film, the etching solution is easily accumulated at the position of the via hole (the first via hole c1 or the second via hole c2), resulting in the portion of the second insulating layer 107 located at the via hole being overetched.
  • the metal pattern 1091 of the third metal layer 109 located in the second via c2 is retained, so that when etching the third metal film, it is not necessary to etch the third metal film located in the second via c2, and the etching liquid will not be accumulated in the second via c2, thereby avoiding over-etching of the second insulating layer 107 located at the second via c2.
  • the short-circuiting of the fourth circuit sub-pattern b44 of the transition structure 104 and the second circuit structure 106b can be avoided. As a result, there is no risk of short-circuiting between the first via c1 and the second via c2, ensuring the yield of the display panel.
  • a signal line can be designed to be connected to the metal pattern 1091 to provide a fixed voltage to the metal pattern 1091.
  • the metal pattern 1091 can also be directly made a floating pattern without providing a fixed voltage to the metal pattern 1091.
  • the protective layer M is an active layer 110 located between the base substrate 101 and the first metal layer.
  • the active layer 110 includes a plurality of active patterns 1101 which are protective patterns.
  • the orthographic projection of the active pattern 1101 on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the main pattern 1081 of the third insulating layer 108 covers the first via c1 to protect the second circuit sub-pattern b22 of the first circuit structure 106a, thereby preventing the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106a from being short-circuited.
  • 110 is located on the side of the first metal layer close to the base substrate 101.
  • the distance between the third circuit sub-pattern b33 and the fourth circuit sub-pattern b44 located on the side of the active pattern 1101 away from the base substrate 101 can be relatively close, and thus the thickness of the first insulating layer 105 located at the third circuit sub-pattern b33 and the fourth circuit sub-pattern b44 can be relatively thin.
  • the depth of the second via c2 designed in the first insulating layer 105 can be reduced.
  • the depth of the second via c2 in the first insulating layer 105 is relatively small, the aggregation degree of the etching solution can be reduced, and the probability of the second insulating layer 107 located at the second via c2 being over-etched can be reduced, thereby avoiding the short circuit between the transfer structure 104 and the fourth circuit sub-structure. That is, there is no risk of short circuit between the first via c1 and the second via c2, thereby ensuring the yield of the display panel.
  • the first insulating layer 105 may include a first sub-insulating layer 1051 and a second sub-insulating layer 1052.
  • the first sub-insulating layer 1051 is located between the active layer and the first metal layer
  • the second insulating layer 1052 is located between the first metal layer and the second metal layer.
  • the protective layer M is a light shielding layer 111 located between the base substrate 101 and the first metal layer.
  • the light shielding layer 111 includes a plurality of light shielding patterns 1111, which are protective patterns.
  • the orthographic projection of the light shielding pattern 1111 on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the main pattern 1081 of the third insulating layer 108 cover the first via c1
  • the second circuit sub-pattern b22 of the first circuit structure 106a is protected, and the second circuit sub-pattern b22 of the first circuit structure 106a is prevented from short-circuiting.
  • the light shielding layer 111 is located on the side of the first metal layer close to the base substrate 101, by designing the light shielding pattern 1111 at the second via c2, the distance between the third circuit sub-pattern b33 and the fourth circuit sub-pattern b44 located on the side of the light shielding pattern 1111 away from the base substrate 101 can be relatively close, and then the thickness of the first insulating layer 105 located at the third circuit sub-pattern b33 and the fourth circuit sub-pattern b44 can be relatively thin. In this way, the depth of the second via c2 designed in the first insulating layer 105 can be reduced.
  • the depth of the second via hole c2 in the first insulating layer 105 is small, the aggregation of the etching solution can be reduced, and the probability of the second insulating layer 107 located at the second via hole c2 being overetched is reduced, thereby avoiding the short circuit between the transfer structure 104 and the fourth circuit substructure. In other words, there is no risk of short circuit between the first via hole c1 and the second via hole c2, thereby ensuring the yield of the display panel.
  • the first insulating layer 105 may include a first sub-insulating layer 1051, a second sub-insulating layer 1052 and a third sub-insulating layer 1053.
  • the first sub-insulating layer 1051 is located between the base substrate 101 and the light shielding layer 111
  • the second sub-insulating layer 1052 is located between the light shielding layer 111 and the first metal layer
  • the third sub-insulating layer 1053 is located between the first metal layer and the second metal layer.
  • the difference between the orthographic projection area of the protection pattern on the base substrate 101 and the orthographic projection area of the second via c2 on the base substrate 101 ranges from 1 ⁇ m 2 (square micrometer) to 50 ⁇ m 2.
  • a plurality of second vias c2 may correspond to one protective pattern (i.e., the orthographic projection of each protective pattern on the base substrate 101 covers the orthographic projections of a plurality of second vias c2 on the base substrate 101, and the number of protective patterns is less than the number of second vias c2).
  • the shape of the protective pattern may be adjusted to a strip or other shape based on the design of the second vias c2, and the embodiment of the present application does not limit the shape of the protective pattern.
  • the plurality of second via holes c2 include a plurality of target second via holes, and the orthographic projections of the plurality of target second via holes on the base substrate 101 are covered by the orthographic projection of the same protection pattern on the base substrate 101. If the gap between any target second via hole and another target second via hole in the plurality of target second via holes is less than 4 ⁇ m (micrometers), it can be considered that the gap between the two target second via holes is small and can be covered by one protection pattern.
  • the transfer structure 104 may include a plurality of openings d1.
  • the orthographic projection of the openings d1 on the base substrate 101 covers the orthographic projection of the second vias c2 on the base substrate 101.
  • the transfer structure 104 is designed with an opening d1 at the second via hole c2, even if the second insulating layer 107 at the second via hole c2 is over-etched (for example, the fourth circuit sub-pattern b44 of the second circuit structure 106b is exposed due to over-etching of the second insulating layer 107), the transfer structure 104 will not be short-circuited with the fourth circuit sub-pattern b44, thereby ensuring the yield of the display panel 10.
  • the difference between the orthographic projection area of the opening d1 on the base substrate 101 and the orthographic projection area of the second via c2 on the base substrate 101 ranges from 1 ⁇ m 2 to 50 ⁇ m 2.
  • the hole density of the second via holes c2 in the display panel 10 is related to the specific design of the signal input circuit that provides relevant signals to the GOA circuit in the display panel 10. If the hole density of the second via holes c2 is small, even if each second via hole c2 corresponds to one opening (i.e., each opening is projected on the substrate 101), The shadow covers the orthographic projection of a second via c2 on the base substrate 101, and the number of openings is the same as the number of second vias c2), and the setting density of the openings will not be too large. In this case, the difficulty of preparing the mask plate used for preparing the adapter structure 104 will not be too great.
  • each second via c2 corresponds to an opening
  • the setting density of the openings will be too large, and the difficulty of preparing the mask plate used for preparing the adapter structure 104 will be relatively high.
  • multiple second vias c2 can be made to correspond to one opening d1 (that is, the orthographic projection of each opening d1 on the base substrate 101 covers the orthographic projections of multiple second vias c2 on the base substrate 101, and the number of openings is less than the number of second vias c2).
  • the shape of the opening d1 can be adjusted to a long strip or other shape based on the design of the second via c2, and the embodiment of the present application does not limit the shape of the opening d1.
  • the plurality of second via holes c2 include a plurality of target second via holes, and the orthographic projections of the plurality of target second via holes on the base substrate 101 are covered by the orthographic projection of the same opening on the base substrate 101. If the gap between any target second via hole and another target second via hole in the plurality of target second via holes is less than 4 ⁇ m (micrometers), it can be considered that the gap between the two target second via holes is small and can be covered by one opening d1.
  • the third insulating layer 108 in the display panel 10 further includes: a first insulating pattern 1082.
  • the display panel 10 further includes a fourth insulating layer 112 located on a side of the third insulating layer 108 away from the base substrate 101.
  • the fourth insulating layer 112 includes a second insulating pattern 1121 and a third insulating pattern 1122.
  • the first barrier dam 1031 at least includes a second insulating pattern 1121
  • the second barrier dam 1032 at least includes a first insulating pattern 1082 and a third insulating pattern 1122 stacked in a direction away from the base substrate 101. That is, the second barrier dam 1032 is provided with an additional pattern located in the third insulating layer 108 relative to the first barrier dam 1031, so that the thickness of the second barrier dam 1032 is greater than that of the first barrier dam 1031, thereby preventing the organic layer from overflowing.
  • the display panel 10 further includes a fifth insulating layer 113 and a sixth insulating layer 114 located on a side of the fourth insulating layer 112 away from the base substrate 101.
  • the fifth insulating layer 113 includes a fifth insulating pattern 1131 and a sixth insulating pattern 1132
  • the sixth insulating layer 114 includes a seventh insulating pattern 1141 and an eighth insulating pattern 1142.
  • the first blocking dam 1031 further includes a fifth insulating pattern 1131 and a seventh insulating pattern 1141
  • the second blocking dam 1032 further includes a sixth insulating pattern 1132 and an eighth insulating pattern 1142.
  • each insulating layer includes multiple patterns including the same material and having the same
  • the second insulating pattern 1121 and the third insulating pattern 1122 in the fourth insulating layer 112 may include the same material and be manufactured by the same patterning process.
  • the fifth insulating pattern 1131 and the sixth insulating pattern 1132 in the fifth insulating layer 113 may include the same material and be manufactured by the same patterning process.
  • the seventh insulating pattern 1141 and the eighth insulating pattern 1142 in the sixth insulating layer 114 may include the same material and be manufactured by the same patterning process.
  • the third insulating layer 108 can be a first planarization layer (PLN)
  • the fourth insulating layer 112 can be a second planarization layer
  • the fifth insulating layer 113 can be a pixel definition layer (pixel definition layer, PDL)
  • the sixth insulating layer 114 can be a support layer (photo spacer, PS).
  • the materials used to make the first planar layer 108 , the second planar layer 112 , the pixel defining layer 113 , and the supporting layer 114 may include organic materials such as resin, etc. This embodiment of the present application does not limit this.
  • the display panel 10 further includes: at least one first power line 115.
  • the at least one first power line 115 is located in the peripheral area 101b.
  • the at least one first power line 115 includes a first portion 1151 and a second portion 1152.
  • the first portion 1151 is located on a side of the blocking structure 103 away from the plurality of pixel units 102, and is used to receive a first power signal
  • the second portion 1152 surrounds the plurality of pixel units 102, and is electrically connected to the first portion 1151 and the switching structure 104, respectively.
  • the first power signal is transmitted to the second electrode layer a3 through the first power line 115 and the switching structure 104.
  • the first power signal provided by the second portion 1152 of the first power line 115 to the second electrode layer a3 of the plurality of pixel units 102 may be a negative power signal, so the first power line 115 may also be called a VSS power line or a VSS line.
  • the second electrode layer a3 may be a cathode layer.
  • the material of the first power line 115 may include a metal material for transmitting the first power signal.
  • the peripheral region 101b may include: a first region 101b1 and a second region 101b2 arranged oppositely and in parallel, and a third region 101b3 and a fourth region 101b4 arranged oppositely and in parallel.
  • the extension direction of the first region 101b1 is perpendicular to the extension direction of the third region 101b3.
  • the first area 101b1 may be an area below the display area 101a
  • the second area 101b2 may be an area above the display area 101a
  • the third area 101b3 may be an area on the left side of the display area 101a
  • the fourth area 101b4 may be an area on the right side of the display area 101a.
  • the first portion 1151 of the first power line 115 may be located in the first region 101b1
  • the second portion 1152 may be located in the second region 101b2 , the third region 101b3 , and the fourth region 101b4 . That is, the second portion 1152 of the first power line 115 can surround three sides of the display area 101a. Of course, the second portion 1152 can also surround two sides or four sides of the display area 101a, which is not limited in the embodiment of the present application.
  • the portion of the blocking structure 103 through which the power cord passes can be referred to as a port, such as the portion through which the first power cord 115 passes can be referred to as a first port 10a.
  • the first power cord 115 can include two first portions 1151, whereby the two first portions 1151 can pass through the blocking structure 103 respectively, and the blocking structure 103 can have two first ports 10a through which the two first portions 1151 pass.
  • the two first portions 1151 may be arranged symmetrically with respect to the axis of the base substrate 101.
  • the two first portions 1151 may be located on both sides of the base substrate 101.
  • the axis of the base substrate 101 may be parallel to the column direction of the plurality of pixel units 102.
  • the two first parts 1151 located on both sides of the substrate 101 may mean: for a first part 1151 located on the same side of the axis as the third region 101b3, the distance between the first part 1151 and the third region 101b3 is smaller than the distance between the first part 1151 and the axis; for another first part 1151 located on the same side of the axis as the fourth region 101b4, the distance between the first part 1151 and the fourth region 101b4 is smaller than the distance between the first part 1151 and the axis.
  • the first power cord 115 may further include a second portion 1152.
  • One end of the second portion 1152 may be connected to a first portion 1151, and the other end of the second portion 1152 may be connected to another first portion 1151.
  • the two first portions 1151 and the one second portion 1152 may be an integral structure, and the second portion 1152 of the first power cord 115 may be a non-enclosed structure.
  • the display panel 10 may further include: at least one second power line 116 located in the peripheral region 101b.
  • One end of the at least one second power line 116 may be located on a side of the blocking structure 103 away from the plurality of pixel units 102, for receiving a second power signal, and the other end may be located on a side of the blocking structure 103 close to the plurality of pixel units 102, and electrically connected to the plurality of pixel units 102, so that the second power line 116 may provide the second power signal to the plurality of pixel units 102.
  • each second power line 116 may be located in the first region 101b1 of the peripheral region 101b.
  • the other end of the at least one second power line 116 may be electrically connected to the thin film transistors in the plurality of pixel units 102.
  • the second power line 116 may be connected to the source or drain of the thin film transistor in the pixel unit 102.
  • the second power line 116 is a second power signal provided to the thin film transistor in the pixel unit 102. It can be a positive power signal, so the second power line 116 can also be called a VDD power line or a VDD routing line.
  • each second power line 116 is located outside the area surrounded by the blocking structure 103, and the other end is located within the area surrounded by the blocking structure 103. That is, each second power line 116 can pass through the blocking structure 103 and enter the area surrounded by the blocking structure 103.
  • the portion of the blocking structure 103 through which the second power line 116 passes can be referred to as a second line inlet 10b.
  • the display panel 10 may include: two second power lines 116, wherein the two second power lines 116 may be symmetrically arranged with respect to the axis of the base substrate 101.
  • transmitting the second power signal through two second power lines 116 can improve the reliability of the second power signal received by each pixel unit 102 compared with transmitting the second power signal through only one second power line 116.
  • FIG10 is a schematic diagram of the structure of another display panel provided by an embodiment of the present application.
  • each pixel unit 102 included in the display panel 10 may include: a thin film transistor (TFT) 1022 and a light emitting unit 1021 stacked in sequence in a direction away from the base substrate 101.
  • TFT thin film transistor
  • FIG10 shows one pixel unit 102.
  • the thin film transistor 1022 may include: a first buffer layer (buffer) e1, a third active pattern e2, a first gate insulating layer (gate insulator, GI) e3, a first gate pattern e4, a second gate insulating layer e5, a second buffer layer e6, an interlayer dielectric (inter layer dielectric, ILD) e7, and a source and drain electrode e8, which are sequentially stacked in a direction away from the base substrate 101.
  • the source and drain electrode may include a source electrode (source, S) and a drain electrode (drain, D) arranged at intervals, and the source electrode and the drain electrode may be connected to the third active pattern e2.
  • the light emitting unit 1021 may include: an anode in an anode layer a1 , a light emitting pattern in a light emitting layer a2 , and a cathode layer a3 , which are sequentially stacked in a direction away from the base substrate 101 .
  • the first circuit structure 106a in the embodiment of the present application is a related structure in the GOA circuit.
  • the GOA circuit f included in the display panel may include: a first buffer layer f1, a fourth active pattern f2, a first gate insulating layer f3, a second gate pattern f4, a second gate insulating layer f5, a third gate pattern f6, a second buffer layer f7, an interlayer dielectric layer f8, and a first source and drain layer f9 stacked in sequence in a direction away from the base substrate 101.
  • the first source and drain layer includes a second connection pattern, which can be connected to the first gate pattern f4 to achieve the function of transmitting signals.
  • the display panel 10 further includes a passivation layer (second insulating layer 107 ), a first planar layer (third insulating layer 108 ), a second source and drain layer (third metal layer 109 ) and a second planar layer (fourth insulating layer 112 ).
  • the thin film transistor 1022 in the multiple pixel units 102 included in the display panel 10 and the first buffer layer, the first gate insulating layer, the second gate insulating layer, the second buffer layer, the interlayer dielectric layer, the passivation layer, the first planarization layer and the second planarization layer of the GOA circuit f are all common film layers.
  • the pixel defining layer 113 included in the display panel 10 may be located on the side of the anode layer away from the base substrate 101, and the support layer 114 may be located on the side of the pixel defining layer 113 away from the base substrate 101.
  • the pixel defining layer 113 may have a plurality of openings, each of which may be used to expose an anode in the anode layer so that the light-emitting pattern subsequently formed in the opening can contact the anode, thereby realizing light emission of the pixel unit 102.
  • the GOA circuit f may include a plurality of shift register units. Each shift register unit is used to drive one or more rows of pixel units 102. The embodiment of the present application is described by taking each shift register unit as an example to drive a row of pixel units 102, but the embodiment of the present application is not limited thereto.
  • Each shift register unit f0 can be connected to a row of pixel units 102 through at least one connecting wire 117, such as being connected to a light emitting control subcircuit of a row of pixel units 102, thereby providing a light emitting control signal for a row of pixel units 102.
  • the GOA circuit can be called an EM GOA circuit (light emitting control gate scanning drive circuit).
  • the display panel 10 further includes a plurality of data lines 118 and a data driving circuit DD, wherein the plurality of data lines 118 vertically pass through the display area 101a, and the data driving circuit DD may be arranged on the side along the extension direction of the data lines DL to drive the pixel circuit 1022 in the pixel unit 102 to provide data signals to the pixel units 102 arranged in the array so that the display panel 10 performs display.
  • each pixel unit 102 may include a pixel circuit having a circuit structure 106 such as 7T1C, 7T2C, 8T2C or 4T1C in the art, and the pixel circuit is used to drive the light-emitting unit 1021 to emit light under the control of the data signal transmitted by the data line 118.
  • the light-emitting unit 1021 may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED), which is not limited in the embodiments of the present application.
  • Fig. 12 is an equivalent circuit diagram of a pixel circuit of a pixel unit provided in an embodiment of the present application.
  • the pixel circuit 1022 included in each pixel unit 102 includes a driving subcircuit 10223, a data writing subcircuit 10224, a threshold compensation subcircuit 10222, a reset subcircuit, a light emitting control subcircuit and a storage capacitor Cst.
  • the first reset sub-circuit 10221 includes a first reset transistor BT1
  • the threshold compensation sub-circuit 10222 includes a threshold compensation transistor BT2
  • the driving sub-circuit 10223 includes a driving transistor BT3
  • the data writing sub-circuit 10224 includes a data writing transistor BT4
  • the first light-emitting control sub-circuit 10225 includes a first light-emitting control transistor BT5
  • the second light-emitting control sub-circuit 10226 includes a second light-emitting control transistor BT6,
  • the second reset subcircuit 10227 includes a second reset transistor BT7.
  • the first reset transistor BT1 and the threshold compensation transistor BT2 are N-type transistors
  • the data writing transistor BT4 and the second reset transistor BT7 are P-type transistors.
  • the connection relationship and working principle of the pixel unit 102 in the embodiment of the present application are only examples, and the pixel unit 102 can also adopt other structures as needed, and the embodiment of the present application does not limit this.
  • the driving subcircuit 10223 includes a control terminal, a first terminal, and a second terminal, and is configured to control the driving current flowing through the light emitting unit 1021.
  • the control terminal of the driving subcircuit 10223 is connected to the first node S1, the first terminal is connected to the second node S2, and the second terminal is connected to the third node S3.
  • the data writing sub-circuit 10224 is connected to the first end of the driving sub-circuit 10223, the data line 118 (Vdata) and the first gate scanning signal line GP, and is configured to write the data signal provided by the data line 118 (Vdata) into the first end of the driving sub-circuit 10224 in response to the data writing control signal provided by the first gate scanning signal line GP.
  • the threshold compensation sub-circuit 10222 is connected to the control end and the second end of the driving sub-circuit 10223, the second power line 116 (VDD routing) and the second gate scan signal line GN, and is configured to compensate the driving sub-circuit in response to the threshold compensation control signal provided by the second gate scan signal line GN and the written data signal.
  • the reset subcircuit includes a first reset subcircuit 10221, which is connected to the control end of the driving subcircuit 10223, the initial signal line Vinit1 and the reset signal line RST, and is configured to apply the initial voltage provided by the initial signal line to the second end of the driving subcircuit 10223 in response to the reset control signal provided by the reset signal line RST.
  • the reset subcircuit further includes a second reset subcircuit 10227, which is connected to the initial signal line Vinit2, the first gate scan signal line GP and the anode of the light emitting unit 1021, and is configured to apply the initial voltage provided by the initial signal line Vinit2 to the first end of the light emitting unit 1021 in response to the control signal provided by the first gate scan signal line GP.
  • the cathode of the light emitting unit 1021 is connected to the first power line 115 (VSS wiring).
  • the light-emitting control subcircuit includes a first light-emitting control subcircuit 10225, which is connected to the VDD line, the first end of the driving subcircuit 10223 and the light-emitting control signal line E, and is configured to apply the first voltage provided by the VDD line to the first end of the driving subcircuit in response to the light-emitting control signal provided by the light-emitting control signal line E.
  • the light emitting control subcircuit further includes a second light emitting control subcircuit 10226.
  • 10226 is connected to the second end of the driving sub-circuit 10223, the anode of the light-emitting unit 1021 and the light-emitting control signal line E, and is configured to respond to the light-emitting control signal provided by the light-emitting control signal line E so that the driving current is applied to the anode of the light-emitting unit 1021.
  • the display panel 10 further includes a first voltage signal line Evgh (not shown in FIG. 1 ) and a second voltage signal line Evgl (not shown in FIG. 1 ) located in the peripheral area 101 b, the first voltage signal line Evgh is configured to provide a first voltage, and the second voltage signal line Evgl is configured to provide a second voltage, the second voltage being less than the first voltage.
  • the EM GOA circuit is connected to the first voltage signal line Evgh to output the first voltage as the first part of the light emitting control signal.
  • the first voltage signal line Evgh is connected to a plurality of shift register units in the EM GOA circuit.
  • the first part of the light emitting control signal is, for example, a high level part of the light emitting control signal.
  • the high level part of the light emitting control signal can turn off the first light emitting control transistor BT5 and the second light emitting control transistor BT6 in the non-light emitting stage.
  • the EM GOA circuit is also connected to the second voltage signal line Evgl to output the second voltage as the second part of the light emitting control signal.
  • the second voltage signal line Evgl is connected to a plurality of shift register units in the EM GOA circuit.
  • the second part of the light emitting control signal is, for example, a low level part of the light emitting control signal.
  • the low level of the light emitting control signal can turn on the first light emitting control transistor BT5 and the second light emitting control transistor BT6 in the light emitting stage.
  • Fig. 13 is an equivalent circuit diagram of a shift register unit provided in an embodiment of the present application.
  • Fig. 14 is a schematic diagram of the layout of the shift register unit shown in Fig. 13 on a display panel. The shift register unit is briefly introduced below in conjunction with Figs. 13 and 14.
  • the shift register unit includes 12 transistors (a first transistor ET1, a second transistor ET2, a third transistor ET3, a fourth transistor ET4, a fifth transistor ET5, a sixth transistor ET6, a seventh transistor ET7, an eighth transistor ET8, a ninth transistor ET9 (also called an output transistor), a tenth transistor ET10 (which can be called an output control transistor or an output transistor, and the embodiments of the present disclosure are not limited to this), an eleventh transistor ET11 and a twelfth transistor ET12, and three capacitors (a first capacitor EC1, a second capacitor EC2, and a third capacitor EC3).
  • the shift register unit may also be a 10T3C circuit that does not include the first transistor ET11 and the twelfth transistor ET12.
  • the second electrode of the first transistor ET1 in the first stage of the shift register unit is connected to the input terminal EI, and the input terminal EI is configured to be connected to the trigger signal line ESTV to receive the trigger signal as an input signal, while the second electrode of the first transistor ET1 in the other stages of the shift register unit is connected to the input terminal EI.
  • the diode is electrically connected to the output end of the previous shift register unit to receive the output signal output by the output end EOUT of the previous shift register unit as an input signal, thereby realizing shift output, so as to provide, for example, a row-by-row shifted light emitting control signal to the pixel units 102 arranged in an array in the display area 101a.
  • the ninth transistor ET9 is taken as an output transistor as an example for description below.
  • the shift register unit f0 also includes a first clock signal terminal ECK and a second clock signal terminal ECB, ECK also represents a first clock signal line, and ECB also represents a second clock signal line.
  • ECK also represents a first clock signal line
  • ECB also represents a second clock signal line.
  • the first clock signal and the second clock signal can be pulse signals with a duty cycle greater than 50%, and the two are, for example, half a cycle apart.
  • Evgh represents the first voltage signal line and the first voltage provided by the first voltage signal line
  • Evgl represents the second voltage signal line and the second voltage provided by the second voltage signal line
  • the second voltage is less than the first voltage.
  • the first voltage is a DC high level
  • the second voltage is a DC low level.
  • the gate of the first transistor ET1 is connected to the first clock signal terminal ECK (the first clock signal terminal is connected to the first clock signal line ECK) to receive the first clock signal
  • the second electrode of the first transistor ET1 is connected to the input terminal EI
  • the first electrode of the first transistor ET1 is connected to the first node ED1.
  • the shift register unit is a first-stage shift register unit
  • the input terminal EI is connected to the trigger signal line ESTV to receive the trigger signal
  • the shift register unit is a shift register unit of other stages except the first-stage shift register unit
  • the input terminal EI is connected to the output terminal EOUT of the previous stage shift register unit.
  • a gate of the second transistor ET2 is connected to the first node ED1, a first electrode of the second transistor ET2 is connected to the second node ED2, and a second electrode of the second transistor ET2 is connected to the first clock signal terminal ECK to receive the first clock signal.
  • a gate of the third transistor ET3 is connected to the first clock signal terminal ECK to receive the first clock signal, a first electrode of the third transistor ET3 is connected to the second node ED2, and a second electrode of the third transistor ET3 is connected to the second voltage signal line Evgl to receive the second voltage.
  • the gate of the fourth transistor ET4 is connected to the second clock signal terminal ECB (for example, the second clock signal terminal ECB is connected to the second clock signal line ECB) to receive the second clock signal, the first electrode of the fourth transistor ET4 is connected to the first node ED1, and the second electrode of the fourth transistor ET4 is connected to the second electrode of the fifth transistor ET5.
  • a gate electrode of the fifth transistor ET5 is connected to the second node ED2 , and a first electrode of the fifth transistor ET5 is connected to the first voltage signal line Evgh to receive the first voltage.
  • a gate of the sixth transistor ET6 is connected to the second electrode of the eleventh transistor ET11 , a first electrode of the sixth transistor ET6 is connected to the second clock signal terminal ECB to receive the second clock signal, and a second electrode of the sixth transistor ET6 is connected to the third node ED3 .
  • a first electrode of the first capacitor EC1 is connected to a second electrode of the eleventh transistor ET11 , and a second electrode of the first capacitor EC2 is connected to a third node ED3 .
  • a gate of the seventh transistor ET7 is connected to the second clock signal terminal ECB to receive the second clock signal, a first electrode of the seventh transistor ET7 is connected to the third node ED3, and a second electrode of the seventh transistor ET7 is connected to the fourth node ED4.
  • a gate of the eighth transistor ET8 is connected to the first node ED1 , a first electrode of the eighth transistor ET8 is connected to the fourth node ED4 , and a second electrode of the eighth transistor ET8 is connected to the first voltage signal line Evgh to receive the first voltage.
  • a gate of the output transistor ET9 is connected to the fourth node ED4 , a first electrode of the output transistor ET9 is connected to the first voltage signal line Evgh to receive the first voltage, and a second electrode of the output transistor ET9 is connected to the output terminal EOUT.
  • a first electrode of the third capacitor EC3 is connected to the fourth node ED4 , and a second electrode of the third capacitor EC3 is connected to the first voltage signal line Evgh to receive the third voltage.
  • the gate of the tenth transistor ET10 is connected to the second electrode of the twelfth transistor ET12, the first electrode of the tenth transistor ET10 is connected to the second voltage signal line Evgl to receive the second voltage, and the second electrode of the tenth transistor ET10 is connected to the output terminal EOUT.
  • a first electrode of the second capacitor EC2 is connected to a second electrode of the twelfth transistor ET12 , and a second electrode of the second capacitor EC2 is connected to the second clock signal terminal ECB to receive the second clock signal.
  • a gate electrode of the eleventh transistor ET11 is connected to the third voltage signal line Evgl to receive the third voltage, and a first electrode of the eleventh transistor ET11 is connected to the second node ED2.
  • a gate electrode of the twelfth transistor ET12 is connected to the third voltage signal line Evgl to receive the third voltage, and a first electrode of the twelfth transistor ET12 is connected to the first node ED1.
  • the signal lines ECB, ECK, Evgl, and Evgh may be arranged along a first direction (eg, an X-axis direction) and all extend along a second direction (eg, a Y-axis direction).
  • the transistors in the shift register unit shown in FIG14 are all described by taking P-type transistors as an example, that is, each transistor is turned on when the gate is connected to a low level (on level), and is turned off when the gate is connected to a high level (off level).
  • the first electrode of the transistor can be the source electrode
  • the second electrode of the transistor can be Drain.
  • the shift register unit includes but is not limited to the configuration of FIG13.
  • the shift register unit may not include ET11 and ET12, and a transistor with a similar function to ET11 or ET12 may be set at the ED3 or ED4 node position.
  • Each transistor may also use an N-type transistor or a mixture of a P-type transistor and an N-type transistor. It is only necessary to simultaneously connect the port polarity of the selected type of transistor according to the port polarity of the corresponding transistor in the embodiment of the present application.
  • the layout shown in FIG14 is only an example. The layout of the shift register unit in the display panel can be determined according to actual needs, and the embodiment of the present application does not limit this.
  • the display panel 10 may further include a power driving circuit 119.
  • the power driving circuit 119 may be located in the peripheral region 101b and located on a side of the first portion 1151 of the first power line 115 away from the blocking structure 103.
  • the power driving circuit 119 may be located in the first region 101b1 of the peripheral region 101b.
  • the power driving circuit 119 can be connected to the first portion 1151 of the first power line 115, and is used to provide the first power signal to the first power line 115, so that the first power line 115 provides the first power signal from the power driving circuit 119 to the cathode layer a3 of the plurality of pixel units 102.
  • the power driving circuit 119 can also be connected to the second power line 116, and is used to provide the second power signal to the second power line 116, so that the second power line 116 provides the second power signal from the power driving circuit 119 to the plurality of pixel units 102.
  • FIG. 1 shows a first power line 115 including two first parts 1151 and two second power lines 116.
  • the power driving circuit 119 can be connected to both the two first parts 1151 and the two second power lines 116.
  • the display panel 10 may further include: an encapsulation film layer 120.
  • the encapsulation film layer 120 may be located on a side of the plurality of pixel units 102 away from the base substrate 101, and the encapsulation film layer 120 covers the area surrounded by the blocking structure 103.
  • the boundary of the area covered by the encapsulation film layer 120 may be located on a side of the blocking structure 103 away from the plurality of pixel units 102.
  • the encapsulation film layer 120 may include: a first film layer 1201 , a second film layer 1202 , and a third film layer 1203 stacked in a direction away from the base substrate 101 .
  • the first film layer 1201 and the third film layer 1203 may be made of an inorganic material, and the second film layer 1202 may be made of an organic material.
  • the first film layer 1201 and the third film layer 1203 may be made of one or more of SiNx (silicon nitride), SiOx (silicon oxide), and SiOxNy (silicon oxynitride).
  • the second film layer 1202 may be made of a resin material.
  • the resin may be a thermoplastic resin or a thermoplastic resin, the thermoplastic resin may include an acrylic (PMMA) resin, and the thermosetting resin may include an epoxy resin.
  • the second film layer 1202 may be located in the area enclosed by the blocking structure 103, and the first film layer 1201 and the third film layer 1203 may cover the area enclosed by the blocking structure 103 and cover the blocking structure 103. That is, the orthographic projection of the blocking structure 103 on the base substrate 101 is located in the area covered by the encapsulation film layer 120, thereby ensuring that the encapsulation film layer 120 effectively encapsulates each structure located in the area enclosed by the blocking structure 103.
  • the second film layer 1202 can be manufactured by ink jet printing (IJP).
  • IJP ink jet printing
  • the first film layer 1201 and the third film layer 1203 can be manufactured by chemical vapor deposition (CVD).
  • an embodiment of the present application provides a display panel, which includes a base substrate, a plurality of pixel units, a blocking structure, a transfer structure, a first insulating layer, a circuit structure, a second insulating layer and a protective layer.
  • the first insulating layer is located between the first circuit pattern and the second circuit pattern of the circuit structure, and has a via, and the first circuit pattern and the second circuit pattern are electrically connected through the via.
  • the orthographic projection of the transfer structure on the base substrate does not overlap with the orthographic projection of the via on the base substrate.
  • the orthographic projection of the protective layer on the base substrate covers the orthographic projection of the via on the base substrate.
  • FIG15 is a partial cross-sectional view of a peripheral region of another display panel provided in an embodiment of the present application.
  • the display panel 10 includes: a base substrate 101, a plurality of pixel units (not shown in FIG15 , but refer to FIG1 ), a blocking structure 103, a transfer structure 104, a first insulating layer 105, a circuit structure 106, a second insulating layer 107, a third insulating layer 108, and a protective layer M.
  • the plurality of pixel units 102 are located in the display region 101 a , and the blocking structure 103 , the transfer structure 104 and the circuit structure 106 are all located in the peripheral region 101 b .
  • the pixel unit 102 includes a light emitting unit 1021.
  • the light emitting unit 1021 includes a first electrode layer a1, a light emitting layer a2 and a second electrode layer a3 stacked in sequence.
  • the first electrode layer a1 is an anode layer
  • the second electrode layer a3 is a cathode layer.
  • the blocking structure 103 may surround a plurality of pixel units 102 .
  • the orthographic projection of the structure 104 on the base substrate 101 is closer to the display area 101a than the orthographic projection of the blocking structure 103 on the base substrate 101 is closer to the display area 101a.
  • the transfer structure 104 and the first electrode layer a1 are located in the same layer with a gap, and the transfer structure 104 is electrically connected to the second electrode layer a3. That is, the transfer structure 104 and the first electrode layer a1 are made of the same material and are prepared by the same patterning process.
  • the signals transmitted by the transfer structure 104 and the second electrode layer a3 are the same signal.
  • the circuit structure 106 is located in the peripheral region 101b, and the circuit structure 106 includes a first circuit structure 106a, and the first circuit structure 106a includes a first circuit sub-pattern b11 and a second circuit sub-pattern b22.
  • the first circuit sub-pattern b11 is located in the first metal layer
  • the second circuit sub-pattern b22 is located in the second metal layer
  • the first insulating layer 105 included in the display panel 10 is located between the first metal layer and the second metal layer.
  • the portion of the first insulating layer 105 located in the peripheral region 101b has a via hole (the via hole includes a first via hole c1), and the first circuit sub-pattern b11 and the second circuit sub-pattern b22 are electrically connected through the first via hole c1.
  • the second insulating layer 107 is located on the side of the second metal layer away from the base substrate 101, and is used to insulate the second circuit sub-pattern b22 in the second metal layer from the transfer structure 104 located in the same layer as the first electrode layer a1.
  • the third insulating layer 108 includes a main pattern 1081 located in the display area 101a and the peripheral area 101b, and the main pattern 1081 includes a third side surface 1081a located in the peripheral area 101b.
  • the orthographic projection of the third side surface 1081a on the base substrate 101 is located between the blocking structure 103 and the display area 101a. That is, the orthographic projection of the main pattern 1081 on the base substrate 101 does not overlap with the orthographic projection of the first circuit structure 106a on the base substrate 101.
  • the orthographic projection of the protection pattern included in the protection layer M on the base substrate 101 can cover the orthographic projection of the first via c1 on the base substrate 101 .
  • the protective layer M may be located between the first metal layer and the base substrate 101, or the protective layer M may be located on the side of the second insulating layer 107 away from the base substrate 101.
  • the second insulating layer 107 at the first via hole c1 is prevented from being over-etched, or the second insulating layer 107 at the first via hole c1 is over-etched, and the short circuit between the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106 is not caused, thereby ensuring the yield of the display panel 10.
  • the embodiment of the present application provides a display panel, which includes a substrate, a plurality of pixel units, a blocking structure, a transfer structure, a first insulating layer, a circuit structure, a second insulating layer, a third insulating layer and a protective layer.
  • the first insulating layer is located in the first circuit sub-diagram of the first circuit structure.
  • the first circuit sub-pattern and the second circuit sub-pattern are provided between the first circuit sub-pattern and the second circuit sub-pattern, and a first via hole is provided, and the first circuit sub-pattern and the second circuit sub-pattern are electrically connected through the first via hole.
  • the second insulating layer at the via hole can be prevented from being over-etched by designing the protective pattern of the protective layer to cover the first via hole, or even if the second insulating layer at the via hole is over-etched, it will not cause the short circuit between the transfer structure and the second circuit sub-pattern of the first circuit structure, thereby ensuring the yield of the display panel.
  • the transfer structure 104 may include a first side surface 104a and a second side surface 104b opposite to each other, and the first side surface 104a is closer to the plurality of pixel units 102 than the second side surface 104b.
  • the orthographic projection of the second side surface 104b on the substrate 101 is located within the orthographic projection of the first blocking dam 1031 on the substrate 101, and the orthographic projection of the transfer structure 104 on the substrate 101 does not overlap with the orthographic projection of the second blocking dam 1032 on the substrate 101. That is, the transfer structure 104 may be located in the area between the first blocking dam 1031 and the display area 101a, but not in the area between the first blocking dam 1031 and the second blocking dam 1032.
  • the orthographic projection of the second side surface 104b (boundary) of the transfer structure 104 on the base substrate 101 is located within the orthographic projection of the first blocking dam 1031 on the base substrate 101, there is a risk of short circuit between the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106a, but there is no risk of short circuit between the transfer structure 104 and the fourth circuit sub-pattern b44 of the second circuit structure 106b.
  • the orthographic projection of the protection pattern of the protection layer M in the embodiment of the present application on the base substrate 101 covers the orthographic projection of the second circuit sub-pattern b22 on the base substrate 101, the short circuit between the transfer structure 104 and the second circuit sub-pattern b22 can be avoided.
  • the protective layer M may be located between the first metal layer and the base substrate 101, or the protective layer M may be located on the side of the second insulating layer 107 away from the base substrate 101.
  • the protective layer M it is possible to either prevent the second insulating layer 107 at the first via hole c1 from being overetched, or even if the second insulating layer 107 at the first via hole c1 is overetched, it will not cause a short circuit between the transfer structure 104 and the second circuit pattern b22 of the first circuit structure 106a, thereby ensuring the yield of the display panel 10.
  • the protective layer M may have the following optional implementation modes:
  • the multiple protection patterns included in the protection layer M are located on the third insulating layer 108. That is, the multiple protection patterns of the protection layer M can be made of the same material and by the same patterning process as the main pattern 1081 of the third insulating layer 108.
  • the ninth insulating pattern 1084 included in the third insulating layer 108 is the protection pattern.
  • a ninth insulating pattern is designed above the second insulating layer 107 located at the first via hole c1, and the ninth insulating pattern can play a role in insulating the transfer structure 104 from the second circuit sub-pattern b22. Therefore, even if the second insulating layer 107 at the first via hole c1 is over-etched (for example, the second circuit sub-pattern b22 of the first circuit structure 106a is exposed due to the over-etching of the second insulating layer 107), since the ninth insulating pattern 1084 of the third insulating layer 108 can cover the over-etched area of the second insulating layer 107, the short circuit between the transfer structure 104 and the second circuit sub-pattern b22 can be avoided, thereby ensuring the yield of the display panel 10.
  • the protection layer M is a third metal layer 109 located on the side of the second insulating layer 107 away from the base substrate 101.
  • the third metal layer 109 includes a plurality of metal patterns 1091 which are protection patterns.
  • the orthographic projection of the metal pattern 1091 on the base substrate 101 covers the orthographic projection of the first via c1 on the base substrate 101.
  • the third metal layer 109 may be a second source and drain electrode layer of the display panel.
  • the third metal layer 109 is not located in the peripheral region 101b. Therefore, when the third metal film used to form the third metal layer 109 is etched with an etching solution, the portion of the third metal film located in the peripheral region 101b needs to be etched away. However, in the process of etching the third metal film, the etching solution is easily accumulated at the position of the via hole (the first via hole c1 or the second via hole c2), resulting in the portion of the second insulating layer 107 located at the via hole being overetched.
  • the metal pattern 1091 of the third metal layer 109 located in the first via c1 is retained, so that when etching the third metal film, it is not necessary to etch the third metal film located in the first via c1, and thus the etching solution will not be accumulated in the first via c1, thereby avoiding over-etching of the second insulating layer 107 located at the first via c1. Further, the short circuit between the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106a can be avoided.
  • a signal line can be designed to be connected to the metal pattern 1091 to provide a fixed voltage to the metal pattern 1091.
  • the metal pattern 1091 can also be directly made a floating pattern without providing a fixed voltage to the metal pattern 1091.
  • the protective layer M is an active layer 110 located between the base substrate 101 and the first metal layer.
  • the active layer 110 includes a plurality of active patterns 1101 which are protective patterns.
  • the orthographic projection on the base substrate 101 covers the orthographic projection of the first via hole c1 on the base substrate 101 .
  • the active layer 110 is located on the side of the first metal layer close to the base substrate 101, by designing the active pattern 1101 at the first via hole c1, the distance between the first circuit sub-pattern b11 and the second circuit sub-pattern b22 located on the side of the active pattern 1101 away from the base substrate 101 can be made closer, and thus the thickness of the first insulating layer 105 located at the first circuit sub-pattern b11 and the second circuit sub-pattern b22 can be made thinner. Thus, the depth of the first via hole c1 designed in the first insulating layer 105 can be reduced.
  • the depth of the first via hole c1 in the first insulating layer 105 is small, the aggregation degree of the etching solution can be reduced, and the probability of the second insulating layer 107 located at the first via hole c1 being over-etched can be reduced, thereby avoiding the short circuit between the transfer structure 104 and the second circuit sub-structure 22. Furthermore, since the orthographic projection of the adapter structure 104 on the base substrate 101 does not overlap with the orthographic projection of the second circuit structure 106b on the base substrate 101, there is no risk of short circuit between the adapter structure 104 and the fourth circuit sub-pattern b44 of the second circuit structure 106b. Therefore, there is no risk of short circuit between the first via c1 and the second via c2, thereby ensuring the yield of the display panel.
  • the first insulating layer 105 may include a first sub-insulating layer 1051 and a second sub-insulating layer 1052.
  • the first sub-insulating layer 1051 is located between the active layer and the first metal layer
  • the second insulating layer 1052 is located between the first metal layer and the second metal layer.
  • the protective layer M is a light shielding layer 111 located between the base substrate 101 and the first metal layer.
  • the light shielding layer 111 includes a plurality of light shielding patterns 1111, which are protective patterns.
  • the orthographic projection of the light shielding pattern 1111 on the base substrate 101 covers the orthographic projection of the first via c1 on the base substrate 101.
  • the light shielding layer 111 is located on the side of the first metal layer close to the base substrate 101, by designing a light shielding pattern at the first via hole c1, the distance between the first circuit sub-pattern b11 and the second circuit sub-pattern b22 located on the side of the light shielding pattern 1111 away from the base substrate 101 can be relatively close, and thus the thickness of the first insulating layer 105 located at the first circuit sub-pattern b11 and the second circuit sub-pattern b22 can be relatively thin. Thus, the depth of the first via hole c1 designed in the first insulating layer 105 can be reduced.
  • the depth of the first via hole c1 in the first insulating layer 105 is relatively small, the aggregation degree of the etching solution can be reduced, and the probability of the second insulating layer 107 located at the first via hole c1 being over-etched can be reduced, thereby avoiding the short circuit between the transfer structure 104 and the second circuit sub-structure 22. Furthermore, since the orthographic projection of the adapter structure 104 on the base substrate 101 does not overlap with the orthographic projection of the second circuit structure 106b on the base substrate 101, there is no risk of short circuit between the adapter structure 104 and the fourth circuit sub-pattern b44 of the second circuit structure 106b. Therefore, there is no risk of short circuit between the first via c1 and the second via c2, thereby ensuring the yield of the display panel.
  • the first insulating layer 105 may include a first sub-insulating layer 1051.
  • the second sub-insulating layer 1052 and the third sub-insulating layer 1053 are located between the first sub-insulating layer 1051 and the base substrate 101 and the light shielding layer 111, the second sub-insulating layer 1052 is located between the light shielding layer 111 and the first metal layer, and the third sub-insulating layer 1053 is located between the first metal layer and the second metal layer.
  • the transfer structure 104 may include a first side surface 104a and a second side surface 104b opposite to each other, and the first side surface 104a is closer to the plurality of pixel units 102 than the second side surface 104b.
  • the orthographic projection of the second side surface 104b on the substrate 101 is located within the orthographic projection of the second blocking dam 1032 on the substrate 101, and the orthographic projection of the transfer structure 104 on the substrate 101 overlaps with the orthographic projection of the first blocking dam 1031 on the substrate 101. That is, the transfer structure 104 may be located in the area between the first blocking dam 1031 and the display area 101a, and also in the area between the first blocking dam 1031 and the second blocking dam 1032.
  • the protective layer M includes a plurality of first protective patterns and a plurality of second protective patterns.
  • the orthographic projection of the first protective pattern on the base substrate 101 covers the orthographic projection of the first via c1 on the base substrate 101, and the orthographic projection of the second protective pattern on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the protective layer M may be located between the first metal layer and the base substrate 101, or the protective layer M may be located on the side of the second insulating layer 107 away from the base substrate 101.
  • the protective layer M it is possible to either prevent the second insulating layer 107 at the first via hole c1 and the second via hole c2 from being overetched, or even if the second insulating layer 107 at the first via hole c1 and the second via hole c2 is overetched, it will not cause a short circuit between the transfer structure 104 and the circuit structure, thereby ensuring the yield of the display panel 10.
  • the protective layer M may have the following optional implementation modes:
  • the plurality of protection patterns included in the protection layer M are located on the third insulating layer 108. That is, the plurality of protection patterns of the protection layer M can be made of the same material and by the same patterning process as the main pattern 1081 of the third insulating layer 108.
  • the ninth insulating pattern 1084 included in the third insulating layer 108 is the first protection pattern
  • the tenth insulating pattern 1085 is the second protection pattern.
  • a ninth insulating pattern is designed above the second insulating layer 107 located at the first via hole c1
  • a tenth insulating pattern is designed above the second insulating layer 107 located at the second via hole c2.
  • the ninth insulating pattern can insulate the transfer structure 104 from the second circuit sub-pattern b22
  • the tenth insulating pattern can insulate the transfer structure 104 from the fourth circuit sub-pattern b44.
  • the ninth insulating pattern 1083 and the tenth insulating pattern 1084 of the third insulating layer 108 can cover the overetched area of the second insulating layer 107, the short circuit between the transfer structure 104, the second circuit sub-pattern b22 and the fourth circuit sub-pattern b44 can be avoided, thereby ensuring the yield of the display panel 10.
  • the protection layer M is a third metal layer 109 located on the side of the second insulating layer 107 away from the base substrate 101.
  • the third metal layer 109 includes a plurality of first metal patterns 1091 and a plurality of second metal patterns 1092, wherein the first metal pattern 1091 is a first protection pattern, and the second metal pattern 1092 is a second protection pattern.
  • the orthographic projection of the first metal pattern 1091 on the base substrate 101 covers the orthographic projection of the first via c1 on the base substrate 101
  • the orthographic projection of the second metal pattern 1092 on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the third metal layer 109 may be a second source and drain electrode layer of the display panel.
  • the third metal layer 109 is not located in the peripheral region 101b. Therefore, when the third metal film used to form the third metal layer 109 is etched with an etching solution, the portion of the third metal film located in the peripheral region 101b needs to be etched away. However, in the process of etching the third metal film, the etching solution is easily accumulated at the position of the via hole (the first via hole c1 or the second via hole c2), resulting in the portion of the second insulating layer 107 located at the via hole being overetched.
  • the first metal pattern 1091 of the third metal layer 109 located in the first via c1 and the second metal pattern 1092 located in the second via c2 are retained, so that when etching the third metal film, it is not necessary to etch away the third metal film located in the first via c1 and the second via c2, thereby preventing the etching solution from gathering in the first via c1 and the second via c2, thereby avoiding over-etching of the second insulating layer 107 located in the first via c1 and the second via c2.
  • the short circuit between the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106a and the fourth circuit sub-pattern b44 of the second circuit structure 106b can be avoided. As a result, there is no risk of short circuit between the first via c1 and the second via c2, thereby ensuring the yield of the display panel.
  • the protective layer M is located between the first metal layer of the base substrate 101.
  • Active layer 110 The multiple first active patterns 1101 included in the active layer 110 are first protection patterns, and the multiple second active patterns 1102 are second protection patterns.
  • the orthographic projection of the first active pattern 1101 on the base substrate 101 covers the orthographic projection of the first via hole c1 on the base substrate 101, and the orthographic projection of the second active pattern 1102 on the base substrate 101 covers the orthographic projection of the second via hole c2 on the base substrate 101.
  • the active layer 110 is located on the side of the first metal layer close to the base substrate 101, by designing the first active pattern 1101 at the first via hole c1 and designing the second active pattern 1102 at the second via hole c2, the first circuit sub-pattern b11 and the second circuit sub-pattern b22 located on the side of the first active pattern 1101 away from the base substrate 101 can be closer, and the third circuit sub-pattern b33 and the fourth circuit sub-pattern b44 located on the side of the second active pattern 1102 away from the base substrate 101 can be closer, so that the thickness of the first insulating layer 105 located in the area of the first circuit sub-pattern b11 and the second circuit sub-pattern b22, and the area of the third circuit sub-pattern b33 and the fourth circuit sub-pattern b44 can be thinner.
  • the depth of the first via hole c1 and the second via hole c2 designed in the first insulating layer 105 can be reduced. Since the depths of the first via hole c1 and the second via hole c2 in the first insulating layer 105 are relatively small, the aggregation of the etching solution can be reduced, and the probability of the second insulating layer 107 being overetched at the first via hole c1 and the second via hole c2 is reduced, thereby avoiding the short circuit between the transfer structure 104 and the second circuit substructure b11 and the fourth circuit substructure b44. That is, there is no risk of short circuit between the first via hole c1 and the second via hole c2, thereby ensuring the yield of the display panel.
  • the first insulating layer 105 may include a first sub-insulating layer 1051 and a second sub-insulating layer 1052.
  • the first sub-insulating layer 1051 is located between the active layer and the first metal layer
  • the second insulating layer 1052 is located between the first metal layer and the second metal layer.
  • the protective layer M is a light shielding layer 111 located between the base substrate 101 and the first metal layer.
  • the light shielding layer 111 includes a plurality of first light shielding patterns 1111, which are first protection patterns, and a plurality of second light shielding patterns 1112, which are second protection patterns.
  • the orthographic projection of the first light shielding pattern 1111 on the base substrate 101 covers the orthographic projection of the first via c1 on the base substrate 101
  • the orthographic projection of the second light shielding pattern 1112 on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the light shielding layer 111 is located on the side of the first metal layer close to the base substrate 101, by designing the first light shielding pattern 1111 at the first via hole c1 and designing the second light shielding pattern 1112 at the second via hole c2, the distance between the first circuit sub-pattern b11 and the second circuit sub-pattern b22 located on the side of the first light shielding pattern 1111 away from the base substrate 101 can be made closer, and the distance between the third circuit sub-pattern b33 and the fourth circuit sub-pattern b22 located on the side of the second light shielding pattern 1112 away from the base substrate 101 can be made closer.
  • the distance between the patterns b44 is relatively close, so that the thickness of the first insulating layer 105 in the area of the first circuit sub-pattern b11 and the second circuit sub-pattern b22, as well as in the area of the third circuit sub-pattern b33 and the fourth circuit sub-pattern b44 can be relatively thin.
  • the depth of the first via c1 and the second via c2 designed in the first insulating layer 105 can be reduced.
  • the depth of the first via c1 and the second via c2 in the first insulating layer 105 is relatively small, the aggregation degree of the etching liquid can be reduced, and the probability of the second insulating layer 107 located at the first via c1 and the second via c2 being over-etched can be reduced, thereby avoiding short circuit between the transfer structure 104 and the second circuit sub-structure and the fourth circuit sub-structure. That is, there is no risk of short circuit between the first via c1 and the second via c2, thereby ensuring the yield of the display panel.
  • the first insulating layer 105 may include a first sub-insulating layer 1051, a second sub-insulating layer 1052 and a third sub-insulating layer 1053.
  • the first sub-insulating layer 1051 is located between the base substrate 101 and the light shielding layer 111
  • the second sub-insulating layer 1052 is located between the light shielding layer 111 and the first metal layer
  • the third sub-insulating layer 1053 is located between the first metal layer and the second metal layer.
  • the difference between the area of the orthographic projection of the first protection pattern on the base substrate 101 and the area of the orthographic projection of the first via c1 on the base substrate 101 ranges from 1 ⁇ m 2 to 50 ⁇ m 2.
  • the first protection pattern slightly larger than the first via c1
  • the short circuit between the transfer structure 104 and the second circuit sub-pattern b22 can be avoided.
  • the difference between the area of the orthographic projection of the second protection pattern on the base substrate 101 and the area of the orthographic projection of the second via c2 on the base substrate 101 ranges from 1 ⁇ m 2 to 50 ⁇ m 2.
  • the second protection pattern slightly larger than the second via c2 the short circuit between the transfer structure 104 and the fourth circuit sub-pattern b44 can be avoided.
  • a plurality of first vias c1 can correspond to a first protective pattern
  • a plurality of second vias c2 can correspond to a second protective pattern (that is, the orthographic projection of each first protective pattern on the base substrate 101 covers the orthographic projections of a plurality of first vias c1 on the base substrate 101, and the number of first protective patterns is less than the number of first vias c1; the orthographic projection of each second protective pattern on the base substrate 101 covers the orthographic projections of a plurality of second vias c2 on the base substrate 101, and the number of second protective patterns is less than the number of second vias c2).
  • the shape of the first protective pattern can be adjusted based on the design of the first via c1
  • the shape of the second protective pattern can be adjusted based on the design of the second via c2
  • the first protective pattern and the second protective pattern are designed to be long strips or other shapes, and the embodiment of the present application does not limit the shape of the protective pattern.
  • the plurality of first via holes c1 include a plurality of target first via holes, and the plurality of target first via holes are The orthographic projection on the base substrate 101 is covered by the orthographic projection of the same first protection pattern on the base substrate 101. If the gap between any target first via and another target first via among the plurality of target first vias is less than 4 ⁇ m, it can be considered that the gap between the two target first vias is small and can be covered by a first protection pattern.
  • the plurality of second vias c2 include a plurality of target second vias, and the orthographic projections of the plurality of target second vias on the base substrate 101 are covered by the orthographic projection of the same second protection pattern on the base substrate 101. If the gap between any target second via and another target second via among the plurality of target second vias is less than 4 ⁇ m, it can be considered that the gap between the two target second vias is small and can be covered by a second protection pattern.
  • an embodiment of the present application provides a display panel, which includes a base substrate, a plurality of pixel units, a blocking structure, a transfer structure, a first insulating layer, a circuit structure, a second insulating layer, a third insulating layer and a protective layer.
  • the first insulating layer is located between the first circuit sub-pattern and the second circuit sub-pattern of the first circuit structure, and has a first via hole, and the first circuit sub-pattern and the second circuit sub-pattern are electrically connected through the first via hole.
  • the protective pattern of the protective layer is designed to cover the first via hole, so that the second insulating layer at the via hole can be prevented from being over-etched, or, even if the second insulating layer at the via hole is over-etched, it will not cause the transfer structure and the second circuit sub-pattern of the first circuit structure to be short-circuited, thereby ensuring the yield of the display panel.
  • FIG24 is a partial cross-sectional view of a peripheral region of another display panel provided in an embodiment of the present application.
  • the display panel 10 includes: a base substrate 101, a plurality of pixel units (not shown in FIG24 , refer to FIG1 ), a blocking structure 103, a transfer structure 104, a first insulating layer 105, a circuit structure 106, a second insulating layer 107, and a third insulating layer 108.
  • the plurality of pixel units 102 are located in the display region 101 a , and the blocking structure 103 , the transfer structure 104 and the circuit structure 106 are all located in the peripheral region 101 b .
  • the pixel unit 102 includes a light emitting unit 1021.
  • the light emitting unit 1021 includes a first electrode layer a1, a light emitting layer a2 and a second electrode layer a3 stacked in sequence.
  • the first electrode layer a1 is an anode layer
  • the second electrode layer a3 is a cathode layer.
  • the blocking structure 103 may surround a plurality of pixel units 102.
  • the orthographic projection of the structure 104 on the base substrate 101 is closer to the display area 101a than the orthographic projection of the blocking structure 103 on the base substrate 101 is closer to the display area 101a.
  • the transfer structure 104 and the first electrode layer a1 are located in the same layer with a gap, and the transfer structure 104 is electrically connected to the second electrode layer a3. That is, the transfer structure 104 and the first electrode layer a1 are made of the same material and are prepared by the same patterning process.
  • the signals transmitted by the transfer structure 104 and the second electrode layer a3 are the same signal.
  • the circuit structure 106 is located in the peripheral region 101b, and the circuit structure 106 includes a first circuit structure 106a, and the first circuit structure 106a includes a first circuit sub-pattern b11 and a second circuit sub-pattern b22.
  • the first circuit sub-pattern b11 is located in the first metal layer
  • the second circuit sub-pattern b22 is located in the second metal layer
  • the first insulating layer 105 included in the display panel 10 is located between the first metal layer and the second metal layer.
  • the portion of the first insulating layer 105 located in the peripheral region 101b has a via hole (the via hole includes a first via hole c1), and the first circuit sub-pattern b11 and the second circuit sub-pattern b22 are electrically connected through the first via hole c1.
  • the second insulating layer 107 is located on the side of the second metal layer away from the base substrate 101, and is used to insulate the second circuit sub-pattern b22 in the second metal layer from the transfer structure 104 located in the same layer as the first electrode layer a1.
  • the third insulating layer 108 includes a main pattern 1081 located in the display area 101a and the peripheral area 101b, and the main pattern 1081 includes a third side surface 1081a located in the peripheral area 101b.
  • the orthographic projection of the third side surface 1081a on the base substrate 101 is located between the blocking structure 103 and the display area 101a. That is, the orthographic projection of the main pattern 1081 on the base substrate 101 does not overlap with the orthographic projection of the first circuit structure 106a on the base substrate 101.
  • the adapter structure 104 may include a plurality of openings d1, and the orthographic projection of the openings d1 on the base substrate 101 covers the orthographic projection of the first via hole c1 on the base substrate 101, that is, the orthographic projection of the adapter structure 104 on the base substrate 101 does not overlap with the orthographic projection of the first via hole c1 on the base substrate 101.
  • the adapter structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106 will not be short-circuited, thereby ensuring the yield of the display panel 10.
  • an embodiment of the present application provides a display panel, which includes a base substrate, a plurality of pixel units, a blocking structure, a transfer structure, a first insulating layer, a circuit structure, a second insulating layer, a third insulating layer and a protective layer.
  • the first insulating layer is located between the first circuit sub-pattern and the second circuit sub-pattern of the first circuit structure, and has a first via hole, and the first circuit sub-pattern and the second circuit sub-pattern are electrically connected through the first via hole.
  • the orthographic projection of the opening included in the transfer structure on the base substrate covers the orthographic projection of the first via hole on the base substrate, even if the second insulating layer 107 at the first via hole is blocked by the via hole, the first via hole is not blocked. Even if the switching structure is short-circuited, the second circuit sub-pattern of the first circuit structure will not be short-circuited, thereby ensuring the yield of the display panel.
  • the transfer structure 104 may include a first side surface 104a and a second side surface 104b opposite to each other, and the first side surface 104a is closer to the plurality of pixel units 102 than the second side surface 104b.
  • the orthographic projection of the second side surface 104b on the substrate 101 is located within the orthographic projection of the first blocking dam 1031 on the substrate 101, and the orthographic projection of the transfer structure 104 on the substrate 101 does not overlap with the orthographic projection of the second blocking dam 1032 on the substrate 101. That is, the transfer structure 104 may be located in the area between the first blocking dam 1031 and the display area 101a, but not in the area between the first blocking dam 1031 and the second blocking dam 1032.
  • the orthographic projection of the second side surface 104b (boundary) of the transfer structure 104 on the base substrate 101 is located within the orthographic projection of the first blocking dam 1031 on the base substrate 101, there is a risk of short circuit between the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106a, but there is no risk of short circuit between the transfer structure 104 and the fourth circuit sub-pattern b44 of the second circuit structure 106b.
  • the orthographic projection of the opening d1 of the adapter structure 104 in the embodiment of the present application on the base substrate 101 covers the first via hole c1
  • the orthographic projection of the adapter structure 104 on the base substrate 101 and the orthographic projection of the second circuit substructure b22 on the base substrate do not overlap. Therefore, even if the second insulating layer 107 at the first via hole c1 is over-etched, it will not cause the adapter structure 104 and the second circuit pattern b22 of the first circuit structure 106a to be short-circuited, thereby ensuring the yield of the display panel 10.
  • the transfer structure 104 may include a first side surface 104a and a second side surface 104b opposite to each other, and the first side surface 104a is closer to the plurality of pixel units 102 than the second side surface 104b.
  • the orthographic projection of the second side surface 104b on the substrate 101 is located within the orthographic projection of the second blocking dam 1032 on the substrate 101, and the orthographic projection of the transfer structure 104 on the substrate 101 overlaps with the orthographic projection of the first blocking dam 1031 on the substrate 101. That is, the transfer structure 104 may be located in the area between the first blocking dam 1031 and the display area 101a, and also in the area between the first blocking dam 1031 and the second blocking dam 1032.
  • the orthographic projection of the second side surface 104b (boundary) of the transfer structure 104 on the base substrate 101 is located within the orthographic projection of the second blocking dam 1032 on the base substrate 101, there is a risk of short circuit between the transfer structure 104 and the second circuit sub-pattern b22 of the first circuit structure 106a and the fourth circuit sub-pattern b44 of the second circuit structure 106b.
  • the pattern b44 is short-circuited, so that the opening of the transfer structure 104 includes a first opening d1 and a second opening d2.
  • the orthographic projection of the first opening d1 on the base substrate 101 covers the orthographic projection of the first via c1 on the base substrate 101
  • the orthographic projection of the second opening d2 on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the transition structure 104 includes a plurality of first openings d1 and a plurality of second openings d2.
  • the dotted line is used as the dividing line
  • the smaller opening on the left is the second opening d2
  • the smaller opening on the right is the first opening d1.
  • the larger opening in the transition structure 104 can be an exhaust hole.
  • the positions of the two unmarked brackets in Figure 27 are the areas where the third insulating layer 108 is dug out. It can be seen that the multiple first openings d1 and the multiple third openings d2 designed in the transition structure 104 can be located in the area where the third insulating layer 108 is dug out.
  • the orthographic projection of the first opening d1 on the base substrate 101 covers the orthographic projection of the first via c1 on the base substrate 101.
  • the orthographic projection of the second opening d2 on the base substrate 101 covers the orthographic projection of the second via c2 on the base substrate 101.
  • the adapter structure 104 Since the adapter structure 104 has the first opening d1 at the first via c1 and the second opening d2 at the second via c2, even if the second insulating layer 107 at the first via c1 and the second via c2 is over-etched (for example, the second circuit sub-pattern b22 of the first circuit structure 106a and the fourth circuit sub-pattern b44 of the second circuit structure 106b are exposed due to the over-etching of the second insulating layer 107), the adapter structure 104 will not be short-circuited with the second circuit sub-pattern b22 and the fourth circuit sub-pattern b44, thereby ensuring the yield of the display panel 10.
  • the difference between the area of the orthographic projection of the first opening d1 on the base substrate 101 and the area of the orthographic projection of the first via hole c1 on the base substrate 101 ranges from 1 ⁇ m 2 to 50 ⁇ m 2.
  • the difference between the area of the orthographic projection of the second opening d2 on the base substrate 101 and the area of the orthographic projection of the second via hole c2 on the base substrate 101 ranges from 1 ⁇ m 2 to 50 ⁇ m 2 .
  • first opening d1 slightly larger than the first via hole c1
  • second opening d2 slightly larger than the second via hole c2
  • the hole density of the first vias c1 and the hole density of the second vias c2 in the display panel 10 are related to the specific design of the GOA circuit in the display panel. If the hole density of the first vias c1 or the second vias c2 is small, even if each first via c1 corresponds to a first opening d1 and each second via c2 corresponds to a second opening d2, the setting density of the first openings d1 or the second openings d2 will not be too high. In this case, the difficulty of preparing the mask plate used to prepare the transfer structure 104 will not be too great.
  • first vias c1 can correspond to one first opening d1
  • second vias c2 can correspond to one second opening d2.
  • shape of the first opening d1 can be adjusted based on the design of the first via c1
  • shape of the second opening d2 can be adjusted based on the design of the second via c2. For example, it can be adjusted to a long strip or other shape, and the embodiment of the present application does not limit the shape of the opening.
  • the plurality of first vias c1 include a plurality of target first vias, and the orthographic projections of the plurality of target first vias on the substrate 101 are covered by the orthographic projection of the same first opening d1 on the substrate 101. If the gap between any target first via and another target first via in the plurality of target first vias is less than 4 ⁇ m, it can be considered that the gap between the two target first vias is small and can be covered by one first opening d1.
  • the plurality of second vias c2 include a plurality of target second vias, and the orthographic projections of the plurality of target second vias on the substrate 101 are covered by the orthographic projection of the same second opening d2 on the substrate 101. If the gap between any target second via and another target second via in the plurality of target second vias is less than 4 ⁇ m, it can be considered that the gap between the two target first vias is small and can be covered by one second opening d3.
  • an embodiment of the present application provides a display panel, which includes a base substrate, a plurality of pixel units, a blocking structure, a transfer structure, a first insulating layer, a circuit structure, a second insulating layer, a third insulating layer and a protective layer.
  • the first insulating layer is located between the first circuit sub-pattern and the second circuit sub-pattern of the first circuit structure, and has a first via hole, and the first circuit sub-pattern and the second circuit sub-pattern are electrically connected through the first via hole.
  • the orthographic projection of the opening included in the transfer structure on the base substrate covers the orthographic projection of the first via hole on the base substrate, even if the second insulating layer 107 at the first via hole is over-etched, it will not cause the transfer structure and the second circuit sub-pattern of the first circuit structure to be short-circuited, thereby ensuring the yield of the display panel.
  • FIG28 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.
  • the display device includes a power supply component 20 and a display panel 10 provided in the above embodiment.
  • the power supply component 20 can be used to supply power to the display panel 10.
  • the display device may be an OLED display device, a liquid crystal display device, electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame or a navigator, or any other product or component with a display function.
  • the display device can have substantially the same technical effects as the display panel described in the previous embodiment, the technical effects of the display device will not be repeatedly described here for the purpose of brevity.
  • first and second, etc. may be used to describe various elements, components, regions, layers and/or parts in this article, these elements, components, regions, layers and/or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another region, layer or part. Therefore, the first element, component, region, layer or part discussed above may be referred to as the second element, component, region, layer or part without departing from the teaching of the present disclosure.

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Abstract

本申请公开了一种显示面板及显示装置，涉及显示技术领域。该显示面板包括衬底基板，多个像素单元，阻挡结构，转接结构，第一绝缘层，电路结构，第二绝缘层以及第三绝缘层。其中，第一绝缘层位于第一电路结构的第一电路子图案和第二电路子图案之间，且具有第一过孔，第一电路子图案和第二电路子图案通过第一过孔电连接。由于第三绝缘层在衬底基板上的正投影覆盖第一过孔在衬底基板上的正投影，因此即使第一过孔处的第二绝缘层被过刻，也不会导致转接结构和第一电路结构的第二电路子图案短接，保证了显示面板的良率。

Description

显示面板及显示装置 技术领域
本申请涉及显示技术领域，特别涉及一种显示面板及显示装置。
背景技术
显示面板通常具有显示区域和包围该显示区域的周边区域。并且，显示面板通常包括位于显示区域的多个像素单元，位于周边区域用于为像素单元提供驱动信号的驱动电路，以及位于周边区域用于为显示面板的阴极层提供负极电源信号的电源走线。其中，负极电源信号一般称为VSS信号，该电源走线一般称为VSS走线。
发明内容
本申请提供了一种显示面板及显示装置，所述技术方案如下：
一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有显示区域以及围绕所述显示区域的周边区域；
多个像素单元，位于所述显示区域，所述像素单元包括发光单元，所述发光单元包括依次层叠的第一电极层，发光层以及第二电极层；
阻挡结构，位于所述周边区域且围绕所述多个像素单元；
转接结构，位于所述周边区域，所述转接结构与所述第一电极层位于同层且具有间隙，且所述转接结构与所述第二电极层电连接；
第一绝缘层，位于所述第一电极层和所述衬底基板之间，且所述第一绝缘层位于所述周边区域的部分具有过孔；
电路结构，位于所述周边区域，所述电路结构包括位于所述阻挡结构围成的区域内的第一电路结构，所述第一电路结构包括第一电路子图案和第二电路子图案，所述第一电路子图案位于第一金属层，所述第二电路子图案位于第二金属层，所述第一金属层和所述第二金属层位于所述第一绝缘层两侧，所述第一绝缘层的过孔包括第一过孔，所述第一电路子图案和所述第二电路子图案通 过所述第一过孔电连接；
第二绝缘层，位于所述第二金属层远离所述衬底基板的一侧；
以及位于所述第二绝缘层远离所述衬底基板的一侧的第三绝缘层，第三绝缘层包括位于所述显示区域和所述周边区域的主体图案，所述主体图案包括位于所述周边区域的第三侧面；所述第三侧面在所述衬底基板上的正投影位于所述阻挡结构在所述衬底基板上的正投影内，且所述主体图案位于所述周边区域的部分在所述第三侧面靠近所述显示区域的一侧为连续性图案。
可选的，所述阻挡结构包括第一阻挡坝和第二阻挡坝；所述第一阻挡坝相对于所述第二阻挡坝靠近所述多个像素单元，且所述第一阻挡坝的厚度小于所述第二阻挡坝的厚度；
所述转接结构包括相对的第一侧面和第二侧面，所述第一侧面相对于所述第二侧面更靠近所述多个像素单元；
其中，所述第二侧面在所述衬底基板上的正投影位于所述第一阻挡坝在所述衬底基板上的正投影内，所述转接结构在所述衬底基板上的正投影与所述第二阻挡坝在所述衬底基板上的正投影不重叠。
可选的，所述电路结构还包括位于所述第一阻挡坝和所述第二阻挡坝之间的第二电路结构；
所述第二电路结构包括第三电路子图案和第四电路子图案，所述第三电路子图案位于所述第一金属层，所述第四电路子图案位于所述第二金属层，所述第一绝缘层的过孔包括第二过孔，所述第三电路子图案和所述第四电路子图案通过所述第二过孔电连接。
可选的，所述阻挡结构包括第一阻挡坝和第二阻挡坝；所述第一阻挡坝相对于所述第二阻挡坝靠近所述多个像素单元，且所述第一阻挡坝的厚度小于所述第二阻挡坝的厚度；
所述转接结构包括相对的第一侧面和第二侧面，所述第一侧面相对于所述第二侧面更靠近所述多个像素单元；
其中，所述第二侧面在所述衬底基板上的正投影位于所述第二阻挡坝在所述衬底基板上的正投影内，所述转接结构在所述衬底基板上的正投影与所述第一阻挡坝在所述衬底基板上的在正投影重叠。
可选的，所述电路结构还包括位于所述第一阻挡坝和所述第二阻挡坝之间 的第二电路结构；
所述第二电路结构包括第三电路子图案和第四电路子图案，所述第一绝缘层的过孔包括第二过孔，所述第三电路子图案和所述第四电路子图案通过所述第二过孔电连接；
所述显示面板还包括：位于所述衬底基板上的保护层，所述保护层包括多个保护图案，所述保护图案在所述衬底基板上的正投影覆盖所述第二过孔在所述衬底基板上的正投影。
可选的，所述多个保护图案位于所述第三绝缘层。
可选的，所述保护层为位于所述第二绝缘层远离所述衬底基板的一侧的第三金属层；
所述第三金属层包括的多个金属图案为所述多个保护图案，所述金属图案在所述衬底基板上的在正投影覆盖所述第二过孔在所述衬底基板上的正投影。
可选的，所述保护层为位于所述衬底基板和所述第一金属层之间的有源层；
所述有源层包括的多个有源图案为所述多个保护图案，所述有源图案在所述衬底基板上的在正投影覆盖所述第二过孔在所述衬底基板上的正投影。
可选的，所述保护层为位于所述衬底基板和所述第一金属层之间的遮光层；
所述遮光层包括的多个遮光图案为所述多个保护图案，所述遮光图案在所述衬底基板上的正投影覆盖所述第二过孔在所述衬底基板上的正投影。
可选的，所述保护图案在所述衬底基板上的正投影的面积，减去所述第二过孔在所述衬底基板上的正投影的面积的差值的范围为1平方微米至50平方微米。
可选的，所述多个第二过孔包括多个目标第二过孔，所述多个目标第二过孔在所述衬底基板上的正投影被同一所述保护图案在所述衬底基板上的正投影覆盖；
其中，所述多个目标第二过孔中任一目标第二过孔与另一目标第二过孔之间的间隙小于4微米。
可选的，所述电路结构还包括位于所述第一阻挡坝和所述第二阻挡坝之间的第二电路结构；
所述第二电路结构包括第三电路子图案和第四电路子图案，所述第一绝缘层的过孔包括第二过孔，所述第三电路子图案和所述第四电路子图案通过所述 第二过孔电连接；
所述转接结构包括多个开口，所述开口在所述衬底基板上的正投影覆盖所述第二过孔在所述衬底基板上的正投影。
可选的，所述开口在所述衬底基板上的正投影的面积，减去所述第二过孔在所述衬底基板上的正投影的面积的差值的范围为1平方微米至50平方微米。
可选的，所述多个第二过孔包括多个目标第二过孔，所述多个目标第二过孔在所述衬底基板上的正投影被同一所述开口在所述衬底基板上的正投影覆盖；
其中，所述多个目标第二过孔中任一目标第二过孔与另一目标第二过孔之间的间隙小于4微米。
可选的，所述第三绝缘层还包括：第一绝缘图案；所述显示面板还包括位于所述第三绝缘层远离所述衬底基板的一侧的第四绝缘层，所述第四绝缘层包括第二绝缘图案和第三绝缘图案；
所述第一阻挡坝至少包括所述第二绝缘图案，所述第二阻挡坝至少包括沿远离所述衬底基板的方向层叠设置的第一绝缘图案和第二绝缘图案。
可选的，所述转接结构在所述衬底基板上的正投影远离所述显示区域的边缘相对于所述阻挡结构在所述衬底基板上的正投影远离所述显示区域的边缘更靠近所述显示区域；
所述主体图案在所述衬底基板上的正投影与所述第二阻挡坝在所述衬底基板上的正投影不重叠。
可选的，所述显示面板还包括：至少一条第一电源线；
所述至少一条第一电源线位于所述周边区域，所述至少一条第一电源线包括第一部分和第二部分，所述第一部分位于所述阻挡结构远离所述多个像素单元的一侧，用于接收第一电源信号，所述第二部分环绕所述多个像素单元，且分别与所述第一部分和所述转接结构电连接。
另一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有显示区域以及围绕所述显示区域的周边区域；
多个像素单元，位于所述显示区域，所述像素单元包括发光单元，所述发光单元包括依次层叠的第一电极层，发光层以及第二电极层；
阻挡结构，位于所述周边区域且围绕所述多个像素单元；
转接结构，位于所述周边区域，所述转接结构与所述第一电极层位于同层且具有间隙，且所述转接结构与所述第二电极层电连接；
第一绝缘层，位于所述第一电极层和所述衬底基板之间，且所述第一绝缘层位于所述周边区域的部分具有过孔；
电路结构，位于所述周边区域，所述电路结构包括位于所述第一阻挡坝和所述显示区域之间的第一电路结构，所述第一电路结构包括第一电路子图案和第二电路子图案，所述第一子电路图案位于第一金属层，所述第二电路子图案位于第二金属层，所述第一金属层和所述第二金属层位于所述第一绝缘层两侧，所述第一绝缘层的过孔包括第一过孔，所述第一电路子图案和所述第二电路子图案通过所述第一过孔电连接；
第二绝缘层，位于所述第二金属层远离所述衬底基板的一侧；
位于所述第二绝缘层远离所述衬底基板的一侧的第三绝缘层，第三绝缘层包括位于所述显示区域和所述周边区域的主体图案，所述主体图案包括位于所述周边区域的第三侧面；所述第三侧面在所述衬底基板上的正投影位于所述阻挡结构和所述显示区域之间；
以及位于所述衬底基板上的保护层，所述保护层包括多个保护图案，所述保护图案在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影。
又一方面，提供了一种显示面板，所述显示面板包括：
衬底基板，所述衬底基板具有显示区域以及围绕所述显示区域的周边区域；
多个像素单元，位于所述显示区域，所述像素单元包括发光单元，所述发光单元包括依次层叠的第一电极层，发光层以及第二电极层；
阻挡结构，位于所述周边区域且围绕所述多个像素单元；
转接结构，位于所述周边区域，所述转接结构与所述第一电极层位于同层且具有间隙，且所述转接结构与所述第二电极层电连接；
第一绝缘层，位于所述第一电极层和所述衬底基板之间，且所述第一绝缘层位于所述周边区域的部分具有过孔；
电路结构，位于所述周边区域，所述电路结构包括位于所述第一阻挡坝和所述显示区域之间的第一电路结构，所述第一电路结构包括第一电路子图案和第二电路子图案，所述第一子电路图案位于第一金属层，所述第二电路子图案 位于第二金属层，所述第一金属层和所述第二金属层位于所述第一绝缘层两侧，所述第一绝缘层的过孔包括第一过孔，所述第一电路子图案和所述第二电路子图案通过所述第一过孔电连接；
第二绝缘层，位于所述第二金属层远离所述衬底基板的一侧；
位于所述第二绝缘层远离所述衬底基板的一侧的第三绝缘层，第三绝缘层包括位于所述显示区域和所述周边区域的主体图案，所述主体图案包括位于所述周边区域的第三侧面；所述第三侧面在所述衬底基板上的正投影位于所述第一阻挡坝和所述显示区域之间；
其中，所述转接结构包括多个开口，所述开口在所述衬底基板上的正投影覆盖所述第一过孔在所述衬底基板上的正投影。
再一方面，提供了一种显示装置，所述显示装置包括：供电组件以及如上述方面所述的显示面板；
其中，所述供电组件用于为所述显示面板供电。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1是本申请实施例提供的一种显示面板的结构示意图；
图2是本申请实施例提供的一种显示面板在周边区域的局部截面图；
图3是本申请实施例提供的一种衬底基板的结构示意图；
图4是本申请实施例提供的一种发光单元的结构示意图；
图5是本申请实施例提供的另一种显示面板在周边区域的局部截面图；
图6是本申请实施例提供的又一种显示面板在周边区域的局部截面图；
图7是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图8是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图9是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图10是本申请实施例提供的显示面板的局部截面图；
图11是本申请实施例提供的另一种显示面板的结构示意图；
图12是本申请实施例提供的一种像素电路的等效电路图；
图13是本申请实施例提供的一种移位寄存器单元的等效电路图；
图14是图13所示的移位寄存器单元在显示面板上的布局示意图；
图15是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图16是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图17是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图18是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图19是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图20是本申请实施例提供的一种显示面板在周边区域的局部示意图；
图21是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图22是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图23是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图24是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图25是本申请实施例提供的再一种显示面板在周边区域的局部截面图；
图26是本申请实施例提供的一种转接结构在周边区域的局部示意图；
图27是本申请实施例提供的另一种显示面板在周边区域的局部示意图；
图28是本申请实施例提供的一种显示装置的结构示意图。
具体实施方式
为了使本公开的目的、技术方案和优点更加清楚，下面将结合附图对本公开作进一步地详细描述。
相关技术中，驱动电路中的至少一个电路结构包括显示面板中第一金属层中的第一金属图案和第二金属层中的第二金属图案。其中，第一金属层和第二金属层之间具有一绝缘层，第一金属图案和第二金属图案通过该绝缘层中的过孔搭接。为了降低显示面板的电压降(loading)，通常可以使得VSS走线与阴极层之间通过显示面板中位于阳极层的转接结构搭接。其中，位于阳极层的转接结构和电路结构的第二金属图案之间具有另一绝缘层，以将转接结构和信号线绝缘。
但是，由于第一金属图案和第二金属图案的搭接位置的另一绝缘层容易被过刻，因此可能导致转接结构与电路结构短接，显示面板的良率较低。
相关技术，显示面板包括衬底基板，位于衬底基板的周边区域的电路结构和转接结构，以及位于衬底基板上的第一绝缘层和第二绝缘层。其中，电路结构包括的第一电路图案(第一电路图案位于第一金属层)和第二电路图案(第二电路图案位于第二金属层)分别位于第一绝缘层的两侧，且通过第一绝缘层中的过孔电连接。第二绝缘层位于第二金属层和转接结构之间，用于将电路结构和转接结构绝缘。
通常情况下，显示面板还包括位于衬底基板的显示区域的第三金属层。该第三金属层位于第二绝缘层和转接结构之间。制备该第三金属层的过程包括：在第二绝缘层远离衬底基板的一侧形成第三金属薄膜，在第三金属薄膜远离衬底基板的一侧涂覆光刻胶，采用掩膜板对光刻胶进行曝光，对曝光后的光刻胶进行显影，采用刻蚀液对未被光刻胶保护的第三金属薄膜进行刻蚀，去除剩余光刻胶，进而得到第三金属层。
由于最终制备得到的第三金属层不位于周边区域，因此第三金属薄膜位于周边区域的部分需要经过刻蚀液的刻蚀。而由于周边区域设计有电路结构(电路结构的第一金属图案和第二金属图案通过第一绝缘层的过孔电连接)，因此刻蚀第三金属薄膜时，容易导致刻蚀液聚集在过孔的位置，导致第二绝缘层位于过孔处的部分被过刻(第二绝缘层的厚度通常较薄，容易被刻蚀液刻透)。进一步的，若第二绝缘层位于过孔处的部分被过刻，则会导致第二绝缘层失去绝缘电路结构和转接结构的效果，进而导致转接结构与电路结构中的第二电路图案直接接触而短接，显示面板的良率较低。
图1是本申请实施例提供的一种显示面板的结构示意图。图2是本申请实施例提供的一种显示面板在周边区域的局部截面图。参考图1，该显示面板10可以包括：衬底基板101，多个像素单元102，阻挡结构103，转接结构104，第一绝缘层105，电路结构106，第二绝缘层107以及位于第二绝缘层107远离衬底基板101的一侧的第三绝缘层108。其中，图2可以为图1沿AA方向的截面图。
图3是本申请实施例提供的一种衬底基板的结构示意图。参考图3，衬底基板101可以具有显示区域101a以及围绕该显示区域101a的周边区域101b。结 合图1至图3，该多个像素单元102位于显示区域101a，阻挡结构103，转接结构104和电路结构106均位于周边区域101b。
在本申请实施例中，参考图4，像素单元102包括发光单元1021。该发光单元1021包括依次层叠的第一电极层a1，发光层a2以及第二电极层a3。例如第一电极层a1为阳极层，第二电极层a3为阴极层。
结合图1至图3，阻挡结构103可以围绕多个像素单元102。该转接结构104与第一电极层a1位于同层且具有间隙，且转接结构104与第二电极层a3电连接。也即是，转接结构104与第一电极层a1采用相同材料并由同一次构图工艺制备得到。转接结构104和第二电极层a3所传输的信号为相同信号。
参考图2，电路结构106位于周边区域101b，且电路结构106包括第一电路结构106a，该第一电路结构106a包括第一电路子图案b11和第二电路子图案b22。其中，第一电路子图案b11位于第一金属层，第二电路子图案b22位于第二金属层，显示面板10包括的第一绝缘层105位于第一金属层和第二金属层之间。该第一绝缘层105位于周边区域101b的部分具有过孔(过孔包括第一过孔c1)，第一电路子图案b11和第二电路子图案b22通过第一过孔c1电连接。第二绝缘层107位于第二金属层远离衬底基板101的一侧，用于将第二金属层中的第二电路子图案b22和与第一电极层a1位于同层的转接结构104绝缘。
在本申请实施例中，第三绝缘层108包括位于显示区域101a和周边区域101b的主体图案1081，该主体图案1081包括位于周边区域101b的第三侧面1081a。第三侧面1081a在衬底基板101上的正投影位于阻挡结构103在衬底基板101上的正投影内。并且，主体图案1081位于周边区域101b的部分在第三侧面1081a靠近显示区域101a的一侧为连续性图案。
由于第三绝缘层108的主体图案1081位于周边区域101b的部分在第三侧面1081a靠近显示区域101a的一侧为连续性图案，且主体图案1081的第三侧面1081a位于阻挡结构103在衬底基板101上的正投影内，因此主体图案1081在衬底基板101上的正投影可以覆盖第一过孔c1在衬底基板101上的正投影，进而可以使得主体图案1081对第一过孔c1的位置起到保护作用。进一步的，即使第一过孔c1处的第二绝缘层107被过刻，也不会导致转接结构104和第一电路结构106a的第二电路子图案b22短接，保证了显示面板10的良率。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括衬底基板， 多个像素单元，阻挡结构，转接结构，第一绝缘层，电路结构，第二绝缘层以及第三绝缘层。其中，第一绝缘层位于第一电路结构的第一电路子图案和第二电路子图案之间，且具有第一过孔，第一电路子图案和第二电路子图案通过第一过孔电连接。由于第三绝缘层在衬底基板上的正投影覆盖第一过孔在衬底基板上的正投影，因此即使第一过孔处的第二绝缘层被过刻，也不会导致转接结构和第一电路结构的第二电路子图案短接，保证了显示面板的良率。
可选的，第三绝缘层108的主体图案1081位于周边区域101b的部分在第三侧面1081a靠近显示区域101a的一侧为连续性图案可以用于表示：主体图案1081位于周边区域101b的左右两侧区域(如下文所描述的第二区域101b2和第四区域101b4)的部分在第三侧面1081a靠近显示区域101a的一侧为连续性图案。
在本申请实施例中，参考图1，阻挡结构103可以为环绕多个像素单元102的环状结构，用于阻挡显示面板10中位于该阻挡结构103围成的区域内的有机层溢流。该阻挡结构103包括第一阻挡坝1031和第二阻挡坝1032。第一阻挡坝1031相对于第二阻挡坝1032靠近多个像素单元102，且第一阻挡坝1031的厚度小于第二阻挡坝1032的厚度。
通过设置两个阻挡坝，且远离多个像素单元102的第二阻挡坝1032的厚度大于靠近多个像素单元102的第一阻挡坝1031的厚度，可以进一步防止位于该阻挡结构103围成的区域内的有机层溢流。当然，该阻挡结构103还可以包括一个阻挡坝，或两个以上的阻挡坝，本申请实施例对此不做限定。
参考图1，第一阻挡坝1031和第二阻挡坝1032在衬底基板101上的正投影均可以为环形。其中，该第一阻挡坝1031相对于该第二阻挡坝1032靠近该多个像素单元102可以用于表示：该第一阻挡坝1031围成的区域位于第二阻挡坝1032围成的区域内。
在本申请实施例中，转接结构104在衬底基板101上的正投影远离显示区域101a的边缘相对于阻挡结构103在衬底基板101上的正投影远离显示区域101a的边缘更靠近显示区域101a。其中，阻挡结构103在衬底基板101上的正投影远离显示区域101a的边缘可以是指第二阻挡坝1032在衬底基板101上的正投影远离显示区域101a的边缘。
参考图2，电路结构106包括的第一电路结构106a可以位于第一阻挡坝1031 和显示区域101a之间。并且，电路结构106还包括位于第一阻挡坝1031和第二阻挡坝1032之间的第二电路结构106b。第二电路结构106b包括第三电路子图案b33和第四电路子图案b44，第一绝缘层105的过孔包括第二过孔c2，第三电路子图案b33和第四电路子图案b44通过第二过孔c2电连接。
在本申请实施例中，第一电路结构106a可以为显示面板10中的阵列基板行驱动(gate driver on array，GOA)电路中的相关结构。第二电路结构106b可以为显示面板中为GOA电路提供相关信号的信号输入电路中的相关结构。
作为一种可选的实现方式，参考图1至图3，转接结构104可以包括相对的第一侧面104a和第二侧面104b，第一侧面104a相对于第二侧面104b更靠近多个像素单元102。第二侧面104b在衬底基板101上的正投影位于第一阻挡坝1031在衬底基板101上的正投影内，且转接结构104在衬底基板101上的正投影与第二阻挡坝1032在衬底基板101上的正投影不重叠。也即是，转接结构104可以位于第一阻挡坝1031和显示区域101a之间的区域，而不位于第一阻挡坝1031和第二阻挡坝1032之间的区域。
在该实现方式中，由于转接结构104的第二侧面104b(边界)在衬底基板101上的正投影位于第一阻挡坝1031在衬底基板101上的正投影内，因此转接结构104与第一电路结构106a的第二电路子图案b22会存在短接风险，而与第二电路结构106b的第四电路子图案b44不会存在短接风险。
由此，由于本申请实施例中的第三绝缘层108的主体图案1081在衬底基板101上的正投影覆盖第二电路子图案b22在衬底基板101上的正投影(即将第三绝缘层108延长至第一阻挡坝1031)，因此可以使得转接结构104和第一电路结构106a的第二电路子图案b22之间除了第二绝缘层107之外，还具有第三绝缘层108。该第三绝缘层108可以起到将转接结构104和第二电路子图案b22绝缘的作用。由此，即使该第一过孔c1处的第二绝缘层107过刻(如由于第二绝缘层107过刻而导致暴露出第一电路结构106a的第二电路子图案b22)，由于该第三绝缘层108可覆盖第二绝缘层107过刻的区域，因此可以避免转接结构104和第二电路子图案b22短接，保证显示面板10的良率。
作为另一种可选的实现方式，参考图5，转接结构104可以包括相对的第一侧面104a和第二侧面104b，第一侧面104a相对于第二侧面104b更靠近多个像素单元102。第二侧面104b在衬底基板101上的正投影位于第二阻挡坝1032在 衬底基板101上的正投影内，且转接结构104在衬底基板101上的正投影与第一阻挡坝1031在衬底基板101上的正投影重叠。也即是，转接结构104可以位于第一阻挡坝1031和显示区域101a之间的区域，也位于第一阻挡坝1031和第二阻挡坝1032之间的区域。
并且，参考图5，第三绝缘层108包括的主体图案1081的第三侧面1081a在衬底基板101上的正投影位于第一阻挡坝1031在衬底基板101上的正投影内，因此第三绝缘层的主体图案1081可以对第一电路结构106a的第二电路子图案b22起到保护作用，而无法对第二电路结构106b的第四电路子图案b44起到保护作用。
由此，在该实现方式中，由于转接结构104的第二侧面104b(边界)在衬底基板101上的正投影位于第二阻挡坝1032在衬底基板101上的正投影内，因此转接结构104与第二电路结构106b的第四电路子图案b44会存在短接风险。由此，为了避免转接结构104与第二电路结构106b的第四电路子图案b44短接，显示面板10还可以包括：位于衬底基板101上的保护层M，保护层M包括多个保护图案。保护图案在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
其中，保护层M可以位于第一金属层和衬底基板101之间，或者保护层M可以位于第二绝缘层107远离衬底基板101的一侧。由此，通过设计保护层M，要么可以避免第二过孔c2处的第二绝缘层107被过刻，要么即使第二过孔c2处的第二绝缘层107被过刻，也不会导致转接结构104和第二电路结构106b的第四电路图案b44短接，保证了显示面板10的良率。
在本申请实施例中，保护层M可以具有以下几种可选的实现方式：
方案一，参考图5，保护层M包括的多个保护图案位于第三绝缘层108。也即是，保护层M的多个保护图案可以与第三绝缘层108的主体图案1081采用相同材料并由同一次构图工艺制备得到。例如，图5中，第三绝缘层108包括的第四绝缘图案1083即为保护图案。
也即是，在位于第二过孔c2处的第二绝缘层107的上方设计有第四绝缘图案1083，该第四绝缘图案1083可以起到将转接结构104和第四电路子图案b44绝缘的作用。由此，即使第二过孔c2处的第二绝缘层107过刻(如由于第二绝缘层107过刻而导致暴露出第二电路结构106b的第四电路子图案b44)，由于 该第三绝缘层108的第四绝缘图案1083可覆盖第二绝缘层107过刻的区域，因此可以避免转接结构104和第四电路子图案b44短接，保证显示面板10的良率。
方案二，参考图6，保护层M为位于第二绝缘层107远离衬底基板101的一侧的第三金属层109。第三金属层109包括的多个金属图案1091为保护图案。金属图案1091在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
其中，第三金属层109可以为显示面板的第二源漏极层。通常情况下，第三金属层109不位于周边区域101b，因此采用刻蚀液刻蚀用于形成第三金属层109的第三金属薄膜时，需将第三金属薄膜位于周边区域101b的部分刻蚀掉。但是，刻蚀第三金属薄膜的过程中，容易导致刻蚀液聚集在过孔(第一过孔c1或第二过孔c2)的位置，导致第二绝缘层107位于过孔处的部分被过刻。
本申请实施例的方案中，通过使得第三绝缘层108的主体图案1081覆盖第一过孔c1，实现对第一电路结构106a的第二电路子图案b22的保护，避免转接结构104和第一电路结构106a的第二电路子图案b22短接。并且，保留第三金属层109位于第二过孔c2的金属图案1091，由此可以在刻蚀第三金属薄膜时，无需将位于第二过孔c2内的第三金属薄膜刻蚀掉，进而不会导致刻蚀液聚集在第二过孔c2内，避免位于第二过孔c2处的第二绝缘层107过刻。进一步的可以避免转接结构104和第二电路结构106b的第四电路子图案b44短接。由此，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板的良率。
在本申请实施例中，由于第三金属层109中的金属图案1091具有导电能力，因此可以通过设计信号线与金属图案1091连接，以为金属图案1091提供一固定电压。当然，由于设计信号线会导致显示面板中的走线较多，版图设计较困难，因此也可以直接使得金属图案1091为浮动(floating)图案，无需为金属图案1091提供固定电压。
方案三，参考图7，保护层M为位于衬底基板101和第一金属层之间的有源层110。有源层110包括的多个有源图案1101即为保护图案。有源图案1101在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
本申请实施例的方案中，通过使得第三绝缘层108的主体图案1081覆盖第一过孔c1，实现对第一电路结构106a的第二电路子图案b22的保护，避免转接结构104和第一电路结构106a的第二电路子图案b22短接。并且，由于有源层 110位于第一金属层靠近衬底基板101的一侧，因此通过在第二过孔c2处设计有源图案，可以使得位于有源图案1101远离衬底基板101的一侧的第三电路子图案b33和第四电路子图案b44的距离均较近，进而可以使得第一绝缘层105位于第三电路子图案b33和第四电路子图案b44的厚度较薄。由此，可以减小第一绝缘层105中设计的第二过孔c2的深度。由于第一绝缘层105中的第二过孔c2的深度较小，因此可以减小刻蚀液的聚集程度，降低位于第二过孔c2处的第二绝缘层107被过刻的概率，进而避免转接结构104和第四电路子结构短接。也即是，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板的良率。
需要说明的是，在该方案三中，第一绝缘层105可以包括第一子绝缘层1051和第二子绝缘层1052。第一子绝缘层1051位于有源层和第一金属层之间，第二绝缘层1052位于第一金属层和第二金属层之间。
方案四，参考图8，保护层M为位于衬底基板101和第一金属层之间的遮光层111。遮光层111包括的多个遮光图案1111即为保护图案。遮光图案1111在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
本申请实施例的方案中，通过使得第三绝缘层108的主体图案1081覆盖第一过孔c1，实现对第一电路结构106a的第二电路子图案b22的保护，避免转接结构104和第一电路结构106a的第二电路子图案b22短接。并且，由于遮光层111位于第一金属层靠近衬底基板101的一侧，因此通过在第二过孔c2处设计遮光图案1111，可以使得位于遮光图案1111远离衬底基板101的一侧的第三电路子图案b33和第四电路子图案b44的距离均较近，进而可以使得第一绝缘层105位于第三电路子图案b33和第四电路子图案b44的厚度较薄。由此，可以减小第一绝缘层105中设计的第二过孔c2的深度。由于第一绝缘层105中的第二过孔c2的深度较小，因此可以减小刻蚀液的聚集程度，降低位于第二过孔c2处的第二绝缘层107被过刻的概率，进而避免转接结构104和第四电路子结构短接。也即是，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板的良率。
需要说明的是，在该方案四中，第一绝缘层105可以包括第一子绝缘层1051，第二子绝缘层1052以及第三子绝缘层1053。第一子绝缘层1051位于衬底基板101和遮光层111之间，第二子绝缘层1052位于遮光层111和第一金属层之间，第三子绝缘层1053位于第一金属层和第二金属层之间。
在上述几种方案中，保护图案在衬底基板101上的正投影的面积，减去第二过孔c2在衬底基板101上的正投影的面积的差值的范围为1μm2(平方微米)至50μm2。通过使得保护图案稍大于第二过孔c2，可以避免转接结构104和第四电路子图案b44短接。
另外，为了降低制备保护层M所采用的掩膜板的制备难度，需降低保护图案的设置密度。例如，可以使得多个第二过孔c2对应一个保护图案(即每个保护图案在衬底基板101上的正投影覆盖多个第二过孔c2在衬底基板101上的正投影，保护图案的数量少于第二过孔c2的数量)。可选的，保护图案的形状可以基于第二过孔c2的设计调整为长条形或其他形状，本申请实施例对保护图案的形状不做限定。
可选的，多个第二过孔c2中包括多个目标第二过孔，多个目标第二过孔在衬底基板101上的正投影被同一保护图案在衬底基板101上的正投影覆盖。如果多个目标第二过孔中任一目标第二过孔与另一目标第二过孔之间的间隙小于4μm(微米)，则可认为这两个目标第二过孔之间的间隙较小，可以通过一个保护图案覆盖。
除了上述设计保护层M的方式之外，为了避免转接结构104与第二电路结构106b的第四电路子图案b44短接，参考图9，可以使得转接结构104包括多个开口d1。开口d1在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
由于转接结构104在第二过孔c2处设计开口d1，因此即使该第二过孔c2处的第二绝缘层107过刻(如由于第二绝缘层107过刻而导致暴露出第二电路结构106b的第四电路子图案b44)，也不会导致转接结构104与第四电路子图案b44短接，保证显示面板10的良率。
可选的，开口d1在衬底基板101上的正投影的面积，减去第二过孔c2在衬底基板101上的正投影的面积的差值的范围为1μm2至50μm2。通过使得开口d1稍大于第二过孔c2，可以进一步确保转接结构104和第四电路子图案b44不会短接。
另外，显示面板10中第二过孔c2的孔密度和显示面板10中为GOA电路提供相关信号的信号输入电路的具体设计相关。如果第二过孔c2的孔密度较小，则即使每个第二过孔c2对应有一个开口(即每个开口在衬底基板101上的正投 影覆盖一个第二过孔c2在衬底基板101上的正投影，开口的数量和第二过孔c2的数量相同)，也不会使得开口的设置密度太大。此种情况下，制备该转接结构104所采用的掩膜板的制备难度不会太大。但是，如果第二过孔c2的孔密度较大，则若每个第二过孔c2对应一个开口，则会导致开口的设置密度太大，制备该转接结构104所采用的掩膜板的制备难度较高。此种情况下，为了降低开口的设置密度，可以使得多个第二过孔c2对应一个开口d1(即每个开口d1在衬底基板101上的正投影覆盖多个第二过孔c2在衬底基板101上的正投影，开口的数量少于第二过孔c2的数量)。可选的，开口d1的形状可以基于第二过孔c2的设计调整为长条形或其他形状，本申请实施例对开口d1的形状不做限定。
可选的，多个第二过孔c2中包括多个目标第二过孔，多个目标第二过孔在衬底基板101上的正投影被同一开口在衬底基板101上的正投影覆盖。如果多个目标第二过孔中任一目标第二过孔与另一目标第二过孔之间的间隙小于4μm(微米)，则可认为这两个目标第二过孔之间的间隙较小，可以通过一个开口d1覆盖。
在本申请实施例中，参考图2，以及图5至图9，显示面板10中的第三绝缘层108还包括：第一绝缘图案1082。并且，显示面板10还包括位于第三绝缘层108远离衬底基板101的一侧的第四绝缘层112。第四绝缘层112包括第二绝缘图案1121和第三绝缘图案1122。
其中，第一阻挡坝1031至少包括第二绝缘图案1121，第二阻挡坝1032至少包括沿远离衬底基板101的方向层叠设置的第一绝缘图案1082和第三绝缘图案1122。也即是，第二阻挡坝1032的相对于第一阻挡坝1031多设置了一层位于第三绝缘层108的图案，从而使得第二阻挡坝1032的厚度大于第一阻挡坝1031的厚度，防止有机层溢流。
另外，显示面板10还包括位于第四绝缘层112远离衬底基板101的一侧的第五绝缘层113和第六绝缘层114。第五绝缘层113包括第五绝缘图案1131和第六绝缘图案1132，第六绝缘层114包括第七绝缘图案1141和第八绝缘图案1142。第一阻挡坝1031还包括第五绝缘图案1131和第七绝缘图案1141，第二阻挡坝1032还包括第六绝缘图案1132和第八绝缘图案1142。
在本申请实施例中，每个绝缘层包括的多个图案包括相同材料，并由同一 次构图工艺制得。例如，第四绝缘层112中的第二绝缘图案1121和第三绝缘图案1122可以包括相同材料，并由同一次构图工艺制得。第五绝缘层113中的第五绝缘图案1131和第六绝缘图案1132可以包括相同材料，并由同一次构图工艺制得。第六绝缘层114中的第七绝缘图案1141和第八绝缘图案1142可以包括相同材料，并由同一次构图工艺制得。
其中，该第三绝缘层108可以为第一平坦层(planarization，PLN)，第四绝缘层112可以为第二平坦层，第五绝缘层113可以为像素界定层(pixel definition layer，PDL)，第六绝缘层114可以为支撑层(photo spacer，PS)。
可选的，制成该第一平坦层108，第二平坦层112，像素界定层113，以及支撑层114的材料可以包括：树脂等有机材料。本申请实施例对此不做限定。
在本申请实施例中，参考图1，显示面板10还包括：至少一条第一电源线115。该至少一条第一电源线115位于周边区域101b。该至少一条第一电源线115包括第一部分1151和第二部分1152。其中，第一部分1151位于阻挡结构103远离多个像素单元102的一侧，用于接收第一电源信号，第二部分1152环绕多个像素单元102，且分别与第一部分1151和转接结构104电连接。由此使得，第一电源信号通过第一电源线115以及转接结构104向第二电极层a3传输第一电源信号。
其中，该第一电源线115的第二部分1152为多个像素单元102的第二电极层a3提供的第一电源信号可以为负极电源信号，因此该第一电源线115也可以称为VSS电源线或者VSS走线。其中，该第二电极层a3可以为阴极层。该第一电源线115的材料可以包括金属材料，用于传输第一电源信号。
在本申请实施例中，参考图3，该周边区域101b可以包括：相对且平行排布的第一区域101b1和第二区域101b2，以及相对且平行排布的第三区域101b3和第四区域101b4。该第一区域101b1的延伸方向垂直于第三区域101b3的延伸方向。
可选的，该第一区域101b1可以为显示区域101a下侧的区域，该第二区域101b2可以为显示区域101a上侧的区域，该第三区域101b3可以为显示区域101a左侧的区域，该第四区域101b4可以为显示区域101a右侧的区域。
其中，参考图1，第一电源线115的第一部分1151可以位于第一区域101b1，第二部分1152可以位于第二区域101b2，第三区域101b3和第四区域101b4。 也即是，该第一电源线115的第二部分1152可以围绕显示区域101a的三条边。当然，该第二部分1152也可以围绕显示区域101a的两条边或者四条边，本申请实施例对此不做限定。
在本申请实施例中，阻挡结构103中供电源线穿过的部分可以称为进线口(port口)，如供第一电源线115穿过的部分可以称为第一进线口10a。参考图1，第一电源线115可以包括两个第一部分1151，由此，两个第一部分1151可以分别穿过阻挡结构103，阻挡结构103中可以具有供该两个第一部分1151穿过的两个第一进线口10a。
并且，两个第一部分1151可以以衬底基板101的轴线为轴对称设置。例如，两个第一部分1151可以位于衬底基板101的两侧。其中，衬底基板101的轴线可以平行于多个像素单元102的列方向。
可选的，两个第一部分1151位于衬底基板101的两侧可以是指：对于与第三区域101b3位于轴线同一侧的一个第一部分1151，该第一部分1151和第三区域101b3之间的距离，小于该第一部分1151与轴线之间的距离；对于与第四区域101b4位于轴线同一侧的另一个第一部分1151，该第一部分1151和第四区域101b4之间的距离，小于该第一部分1151与轴线之间的距离。
参考图1还可以看出，该第一电源线115还可以包括一个第二部分1152。该第二部分1152的一端可以与一个第一部分1151连接，第二部分1152的另一端可以与另一个第一部分1151连接。可选的，两个第一部分1151和一个第二部分1152可以为一体结构，且该第一电源线115的第二部分1152可以为非封闭结构。
参考图1，该显示面板10还可以包括：位于周边区域101b的至少一条第二电源线116。该至少一条第二电源线116的一端可以位于阻挡结构103远离多个像素单元102的一侧，用于接收第二电源信号，另一端可以位于阻挡结构103靠近多个像素单元102的一侧，且与多个像素单元102电连接，从而可以使得第二电源线116为多个像素单元102提供第二电源信号。可选的，每条第二电源线116可以位于周边区域101b的第一区域101b1。
可选的，该至少一条第二电源线116的另一端可以与多个像素单元102中的薄膜晶体管电连。例如，可以与像素单元102中薄膜晶体管的源极或者漏极连接。该第二电源线116为像素单元102中的薄膜晶体管提供的第二电源信号 可以为正极电源信号，因此该第二电源线116也可以称为VDD电源线或者VDD走线。
参考图1，每条第二电源线116的一端位于阻挡结构103围成的区域之外，另一端位于阻挡结构103围成的区域之内。即每条第二电源线116可以穿过阻挡结构103进入该阻挡结构103围成的区域内。其中，阻挡结构103中供第二电源线116穿过的部分可以称为第二进线口10b。
可选的，参考图1，该显示面板10可以包括：两条第二电源线116，其中该两条第二电源线116可以以衬底基板101的轴线为轴对称设置。由此，通过两个第二电源线116传输第二电源信号相对于仅通过一个第二电源线116传输第二电源信号，可以提高各个像素单元102接收到的第二电源信号的可靠性。
图10是本申请实施例提供的再一种显示面板的结构示意图。参考图15可以看出，显示面板10包括的每个像素单元102可以包括：沿远离衬底基板101的方向依次层叠的薄膜晶体管(thin film transistor，TFT)1022和发光单元1021。其中，图10中示出了一个像素单元102。
参考图10，该薄膜晶体管1022可以包括：沿远离衬底基板101的方向依次层叠的第一缓冲层(buffer)e1，第三有源图案e2，第一栅极绝缘层(gate insulator，GI)e3，第一栅极图案e4，第二栅极绝缘层e5，第二缓冲层e6，层间介电层(inter layer dielectric，ILD)e7，以及源漏极e8。其中，该源漏极可以包括间隔设置的源极(source，S)和漏极(drain，D)，且该源极和漏极可以均与第三有源图案e2连接。
参考图10，该发光单元1021可以包括：沿远离衬底基板101的方向依次层叠的阳极层a1中的阳极，发光层a2中的发光图案以及阴极层a3。
另外，本申请实施例中的第一电路结构106a为GOA电路中的相关结构。参考图10还可以看出，显示面板包括的GOA电路f可以包括：沿远离衬底基板101的方向依次层叠的第一缓冲层f1，第四有源图案f2，第一栅极绝缘层f3，第二栅极图案f4，第二栅极绝缘层f5，第三栅极图案f6，第二缓冲层f7，层间介电层f8，以及第一源漏层f9。该第一源漏层包括第二连接图案，该第二连接图案可以与第一栅极图案f4连接，实现传输信号的作用。
另外，显示面板10还包括钝化层(第二绝缘层107)，第一平坦层(第三绝缘层108)，第二源漏层(第三金属层109)以及第二平坦层(第四绝缘层112)。
在本申请实施例中，显示面板10包括的多个像素单元102中的薄膜晶体管1022以及GOA电路f的第一缓冲层，第一栅极绝缘层，第二栅极绝缘层，第二缓冲层，层间介电层，钝化层，第一平坦层以及第二平坦层均为共用膜层。
参考图10，显示面板10包括的像素界定层113可以位于阳极层远离衬底基板101的一侧，支撑层114可以位于像素界定层113远离衬底基板101的一侧。其中，该像素界定层113可以具有多个开孔，每个开孔可以用于露出阳极层中的一个阳极，以便于后续形成在开孔内的发光图案能够与该阳极接触，从而实现像素单元102发光。
在本申请实施例中，GOA电路f可以包括多个移位寄存器单元。每个移位寄存器单元用于驱动一行或多行像素单元102。本申请实施例以每个移位寄存器单元用于驱动一行像素单元102为例进行说明，但是本申请实施例不以此为限。
其中，每个移位寄存器单元f0可以通过至少一条连接走线117与一行像素单元102连接，如与一行像素单元102的发光控制子电路连接，进而为一行像素单元102提供发光控制信号。其中，该GOA电路可以称为EM GOA电路(发光控制栅极扫描驱动电路)。
如图11所示，显示面板10还包括多条数据线118和数据驱动电路DD，该多条数据线118纵向穿过显示区域101a，数据驱动电路DD可以设置在沿数据线DL的延伸方向上的侧边，以驱动像素单元102中的像素电路1022，以为阵列排布的像素单元102提供数据信号，使显示面板10进行显示。例如，各个像素单元102可以包括本领域内的具有7T1C、7T2C、8T2C或4T1C等电路结构106的像素电路，像素电路用于在数据线118传输的数据信号的控制下驱动发光单元1021发光。其中，发光单元1021可以为有机发光二极管(OLED)或量子点发光二极管(QLED)，本申请的实施例对此不做限定。
图12为本申请实施例提供的一种像素单元的像素电路的等效电路图。如图12所示，每个像素单元102包括的像素电路1022包括驱动子电路10223、数据写入子电路10224、阈值补偿子电路10222、复位子电路、发光控制子电路和存储电容Cst。
第一复位子电路10221包括第一复位晶体管BT1，阈值补偿子电路10222包括阈值补偿晶体管BT2，驱动子电路10223包括驱动晶体管BT3，数据写入子电路10224包括数据写入晶体管BT4，第一发光控制子电路10225包括第一发光控制晶体管BT5，第二发光控制子电路10226包括第二发光控制晶体管 BT6，第二复位子电路10227包括第二复位晶体管BT7。例如，第一复位晶体管BT1和阈值补偿晶体管BT2为N型晶体管，数据写入晶体管BT4和第二复位晶体管BT7为P型晶体管。本申请实施例的像素单元102的连接关系和工作原理仅为示例，像素单元102还可以根据需要采用其他结构，本申请实施例对此对此不做限定。
如图12，驱动子电路10223包括控制端、第一端和第二端，且配置为控制流经发光单元1021的驱动电流。例如，驱动子电路10223的控制端和第一节点S1连接，第一端和第二节点S2连接，第二端和第三节点S3连接。
如图12所示，数据写入子电路10224与驱动子电路10223的第一端、数据线118(Vdata)和第一栅极扫描信号线GP连接，且配置为响应于第一栅极扫描信号线GP提供的数据写入控制信号将数据线118(Vdata)提供的数据信号写入驱动子电路10224的第一端。
阈值补偿子电路10222与驱动子电路10223的控制端和第二端、第二电源线116(VDD走线)以及第二栅极扫描信号线GN连接，且配置为响应于第二栅极扫描信号线GN提供的阈值补偿控制信号以及写入的数据信号对驱动子电路进行补偿。
复位子电路包括第一复位子电路10221，第一复位子电路10221与驱动子电路10223的控制端、初始信号线Vinit1和复位信号线RST连接，且配置为响应于复位信号线RST提供的复位控制信号将初始信号线提供的初始电压施加至驱动子电路10223的第二端。
复位子电路还包括第二复位子电路10227，第二复位子电路10227与初始信号线Vinit2、第一栅极扫描信号线GP和发光单元1021的阳极连接，且配置为响应于第一栅极扫描信号线GP提供的控制信号将初始信号线Vinit2提供的初始电压施加至发光单元1021的第一端。发光单元1021的阴极与第一电源线115(VSS走线)连接。
发光控制子电路包括第一发光控制子电路10225，第一发光控制子电路10225与VDD走线、驱动子电路10223的第一端以及发光控制信号线E连接，且配置为响应于发光控制信号线E提供的发光控制信号将VDD走线提供的第一电压施加至驱动子电路的第一端。
发光控制子电路还包括第二发光控制子电路10226，第二发光控制子电路 10226和驱动子电路10223的第二端、发光单元1021的阳极以及发光控制信号线E连接，且配置为响应于发光控制信号线E提供的发光控制信号，使得驱动电流被施加至发光单元1021的阳极。
在本申请实施例中，显示面板10还包括位于周边区域101b的第一电压信号线Evgh(图1未示出)和第二电压信号线Evgl(图1未示出)，第一电压信号线Evgh配置为提供第一电压，第二电压信号线Evgl配置为提供第二电压，第二电压小于第一电压。EM GOA电路与第一电压信号线Evgh连接以输出第一电压作为发光控制信号的第一部。例如，第一电压信号线Evgh与EM GOA电路中的多个移位寄存器单元连接。发光控制信号的第一部例如为发光控制信号的高电平部。例如，该发光控制信号的高电平部可以使得第一发光控制晶体管BT5和第二发光控制晶体管BT6在非发光阶段截止。EM GOA电路还与第二电压信号线Evgl连接以输出第二电压作为发光控制信号的第二部。例如，第二电压信号线Evgl与EM GOA电路中的多个移位寄存器单元均连接。发光控制信号的第二部例如为发光控制信号的低电平部分。例如，该发光控制信号的低电平可以使得第一发光控制晶体管BT5和第二发光控制晶体管BT6在发光阶段导通。
图13是本申请实施例提供的一种移位寄存器单元的等效电路图。图14是图13所示的移位寄存器单元在显示面板上的布局示意图。下面结合图13和图14对该移位寄存器单元进行简要地介绍。
如图13和图14所示，该移位寄存器单元包括12个晶体管(第一晶体管ET1、第二晶体管ET2、第三晶体管ET3、第四晶体管ET4、第五晶体管ET5、第六晶体管ET6、第七晶体管ET7、第八晶体管ET8、第九晶体管ET9(也叫输出晶体管)、第十晶体管ET10(可以叫做输出控制晶体管，也可以叫输出晶体管，本公开的实施例对此不做限制)、第十一晶体管ET11和第十二晶体管ET12以及3个电容(第一电容EC1、第二电容EC2和第三电容EC3)。在一些实施例中，该移位寄存器单元也可以为不包括第一晶体管ET11和第十二晶体管ET12的10T3C的电路。
当多个移位寄存器单元级联时，第一级移位寄存器单元中的第一晶体管ET1的第二极和输入端EI连接，输入端EI被配置为与触发信号线ESTV连接以接收触发信号作为输入信号，而其它各级移位寄存器单元中的第一晶体管ET1的第 二极和上一级移位寄存器单元的输出端电连接，以接收上一级移位寄存器单元的输出端EOUT输出的输出信号作为输入信号，由此实现移位输出，以向显示区域101a中阵列排布的像素单元102提供例如逐行移位的发光控制信号。例如，下面以第九晶体管ET9为输出晶体管为例进行介绍。
如图13和图14所示，该移位寄存器单元f0还包括第一时钟信号端ECK和第二时钟信号端ECB，ECK还表示第一时钟信号线，ECB还表示第二时钟信号线。例如，第一时钟信号以及第二时钟信号可以采用占空比大于50％的脉冲信号，并且二者例如相差半个周期。
Evgh表示第一电压信号线以及第一电压信号线提供的第一电压，Evgl表示第二电压信号线以及第二电压信号线提供的第二电压，且第二电压小于第一电压。例如，第一电压为直流高电平，第二电压为直流低电平。
如图13和图14所示，第一晶体管ET1的栅极和第一时钟信号端ECK连接(第一时钟信号端和第一时钟信号线ECK连接)以接收第一时钟信号，第一晶体管ET1的第二极和输入端EI连接，第一晶体管ET1的第一极和第一节点ED1连接。例如，当该移位寄存器单元为第一级移位寄存器单元时，输入端EI与触发信号线ESTV连接以接收触发信号，当该移位寄存器单元为除第一级移位寄存器单元以外的其他各级移位寄存器单元时，输入端EI与其上一级移位寄存器单元的输出端EOUT连接。
第二晶体管ET2的栅极和第一节点ED1连接，第二晶体管ET2的第一极和第二节点ED2连接，第二晶体管ET2的第二极和第一时钟信号端ECK连接以接收第一时钟信号。
第三晶体管ET3的栅极和第一时钟信号端ECK连接以接收第一时钟信号，第三晶体管ET3的第一极和第二节点ED2连接，第三晶体管ET3的第二极和第二电压信号线Evgl连接以接收第二电压。
第四晶体管ET4的栅极和第二时钟信号端ECB(例如，第二时钟信号端ECB与第二时钟信号线ECB连接)连接以接收第二时钟信号，第四晶体管ET4的第一极和第一节点ED1连接，第四晶体管ET4的第二极和第五晶体管ET5的第二极连接。
第五晶体管ET5的栅极和第二节点ED2连接，第五晶体管ET5的第一极与第一电压信号线Evgh连接以接收第一电压。
第六晶体管ET6的栅极和第十一晶体管ET11的第二极连接，第六晶体管ET6的第一极和第二时钟信号端ECB连接以接收第二时钟信号，第六晶体管ET6的第二极和第三节点ED3连接。
第一电容EC1的第一极和第十一晶体管ET11的第二极连接，第一电容EC2的第二极和第三节点ED3连接。
第七晶体管ET7的栅极和第二时钟信号端ECB连接以接收第二时钟信号，第七晶体管ET7的第一极和第三节点ED3连接，第七晶体管ET7的第二极和第四节点ED4连接。
第八晶体管ET8的栅极和第一节点ED1连接，第八晶体管ET8的第一极和第四节点ED4连接，第八晶体管ET8的第二极和第一电压信号线Evgh连接以接收第一电压。
输出晶体管ET9的栅极和第四节点ED4连接，输出晶体管ET9的第一极和第一电压信号线Evgh连接以接收第一电压，输出晶体管ET9的第二极和输出端EOUT连接。
第三电容EC3的第一极和第四节点ED4连接，第三电容EC3的第二极和第一电压信号线Evgh连接以接收第三电压。
第十晶体管ET10的栅极和第十二晶体管ET12的第二极连接，第十晶体管ET10的第一极和第二电压信号线Evgl连接以接收第二电压，第十晶体管ET10的第二极和输出端EOUT连接。
第二电容EC2的第一极和第十二晶体管ET12的第二极连接，第二电容EC2的第二极和第二时钟信号端ECB连接以接收第二时钟信号。
第十一晶体管ET11的栅极和第三电压信号线Evgl连接以接收第三电压，第十一晶体管ET11的第一极和第二节点ED2连接。
第十二晶体管ET12的栅极和第三电压信号线Evgl连接以接收第三电压，第十二晶体管ET12的第一极和第一节点ED1连接。
如图14所示，信号线ECB、ECK、Evgl、Evgh可以沿第一方向(例如X轴方向)排列，并均沿第二方向(例如Y轴方向)延伸。
图14中所示的移位寄存器单元中的晶体管均是以P型晶体管为例进行说明的，即各个晶体管在栅极接入低电平(导通电平)时导通，而在接入高电平(截止电平)时截止。此时，晶体管的第一极可以是源极，晶体管的第二极可以是 漏极。
该移位寄存器单元包括但不限于图13的配置方式，例如，移位寄存器单元中可以不包括ET11和ET12，也可以在ED3或ED4节点位置设置同ET11或ET12类似功能的晶体管，各个晶体管也可以采用N型晶体管或混合采用P型晶体管和N型晶体管，只需同时将选定类型的晶体管的端口极性按照本申请实施例中的相应晶体管的端口极性进行连接即可。图14所示的布局仅为示例，移位寄存器单元在显示面板中的布局可以根据实际需求而定，本申请实施例对此不做限定。
参考图1，该显示面板10还可以包括：电源驱动电路119。该电源驱动电路119可以位于周边区域101b，且位于第一电源线115的第一部分1151远离阻挡结构103的一侧。例如，该电源驱动电路119可以位于周边区域101b的第一区域101b1。
该电源驱动电路119可以与第一电源线115的第一部分1151连接，用于为该第一电源线115提供第一电源信号，从而使得该第一电源线115向多个像素单元102的阴极层a3提供来自电源驱动电路119的第一电源信号。并且，该电源驱动电路119还可以与第二电源线116连接，用于为该第二电源线116提供第二电源信号，从而使得该第二电源线116向多个像素单元102提供来自电源驱动电路119的第二电源信号。
示例的，图1中示出了一条第一电源线115，且该第一电源线115包括两个第一部分1151，且示出了两条第二电源线116。该电源驱动电路119可以与该两个第一部分1151以及两条第二电源线116均连接。
在本申请实施例中，参考图10，该显示面板10还可以包括：封装膜层120。该封装膜层120可以位于多个像素单元102远离衬底基板101的一侧，该封装膜层120覆盖阻挡结构103围成的区域。参考图10，该封装膜层120覆盖的区域的边界可以位于阻挡结构103远离多个像素单元102的一侧。
在本申请实施例中，封装膜层120可以包括：沿远离衬底基板101的方向层叠设置的第一膜层1201，第二膜层1202以及第三膜层1203。
可选的，该第一膜层1201和该第三膜层1203可以由无机材料制成，该第二膜层1202可以由有机材料制成。例如，该第一膜层1201和该第三膜层1203可以由SiNx(氮化硅)、SiOx(氧化硅)和SiOxNy(氮氧化硅)等一种或多种 无机氧化物制成。第二膜层1202可以由树脂材料制成。该树脂可以为热塑性树脂或热塑性树脂，热塑性树脂可以包括亚克力(PMMA)树脂，热固性树脂可以包括环氧树脂。
需要说明的是，该第二膜层1202可以位于阻挡结构103围成的区域内，第一膜层1201和第三膜层1203可以覆盖阻挡结构103围成的区域，且覆盖该阻挡结构103。即阻挡结构103在衬底基板101上的正投影，位于该封装膜层120覆盖的区域内，由此确保该封装膜层120对位于阻挡结构103围成的区域内的各个结构的有效封装。
在本申请实施例中，第二膜层1202可以采用喷墨打印(ink jet printing，IJP)的方法制作。第一膜层1201和第三膜层1203可以采用化学气相沉积(chemical vapor deposition，CVD)的方法制作。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括衬底基板，多个像素单元，阻挡结构，转接结构，第一绝缘层，电路结构，第二绝缘层以及保护层。其中，第一绝缘层位于电路结构的第一电路图案和第二电路图案之间，且具有过孔，第一电路图案和第二电路图案通过过孔电连接。转接结构在衬底基板上的正投影与过孔在衬底基板上的正投影不重叠。和/或，保护层在衬底基板上的正投影覆盖过孔在衬底基板上的正投影。由此，可以避免过孔处的第二绝缘层被过刻，或者，即使过孔处的第二绝缘层被过刻，也不会导致转接结构和电路结构的第二电路图案短接，保证了显示面板的良率。
图15是本申请实施例提供的再一种显示面板在周边区域的局部截面图。参考图15，该显示面板10包括：衬底基板101，多个像素单元(图15中未示出，可参考图1)，阻挡结构103，转接结构104，第一绝缘层105，电路结构106，第二绝缘层107，第三绝缘层108以及保护层M。
结合图1，图3以及图15，该多个像素单元102位于显示区域101a，阻挡结构103，转接结构104和电路结构106均位于周边区域101b。
参考图4，像素单元102包括发光单元1021。该发光单元1021包括依次层叠的第一电极层a1，发光层a2以及第二电极层a3。例如第一电极层a1为阳极层，第二电极层a3为阴极层。
结合图1，图3以及图15，阻挡结构103可以围绕多个像素单元102。转接 结构104在衬底基板101上的正投影远离显示区域101a的边缘相对于阻挡结构103在衬底基板101上的正投影远离显示区域101a的边缘更靠近显示区域101a，该转接结构104与第一电极层a1位于同层且具有间隙，且转接结构104与第二电极层a3电连接。也即是，转接结构104与第一电极层a1采用相同材料并由同一次构图工艺制备得到。转接结构104和第二电极层a3所传输的信号为相同信号。
参考图15，电路结构106位于周边区域101b，且电路结构106包括第一电路结构106a，该第一电路结构106a包括第一电路子图案b11和第二电路子图案b22。其中，第一电路子图案b11位于第一金属层，第二电路子图案b22位于第二金属层，显示面板10包括的第一绝缘层105位于第一金属层和第二金属层之间。该第一绝缘层105位于周边区域101b的部分具有过孔(过孔包括第一过孔c1)，第一电路子图案b11和第二电路子图案b22通过第一过孔c1电连接。第二绝缘层107位于第二金属层远离衬底基板101的一侧，用于将第二金属层中的第二电路子图案b22和与第一电极层a1位于同层的转接结构104绝缘。
在本申请实施例中，第三绝缘层108包括位于显示区域101a和周边区域101b的主体图案1081，该主体图案1081包括位于周边区域101b的第三侧面1081a。第三侧面1081a在衬底基板101上的正投影位于阻挡结构103和显示区域101a之间。也即是，主体图案1081在衬底基板101上的正投影与第一电路结构106a在衬底基板101上的正投影不重叠。
由此，为了避免转接结构104和第一电路结构106a的第二电路子图案b22短接，可以使得保护层M包括的保护图案在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影。
其中，保护层M可以位于第一金属层和衬底基板101之间，或者保护层M可以位于第二绝缘层107远离衬底基板101的一侧。由此，要么可以避免第一过孔c1处的第二绝缘层107被过刻，要么第一过孔c1处的第二绝缘层107被过刻，也不会导致转接结构104和第一电路结构106的第二电路子图案b22短接，保证了显示面板10的良率。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括衬底基板，多个像素单元，阻挡结构，转接结构，第一绝缘层，电路结构，第二绝缘层，第三绝缘层以及保护层。其中，第一绝缘层位于第一电路结构的第一电路子图 案和第二电路子图案之间，且具有第一过孔，第一电路子图案和第二电路子图案通过第一过孔电连接。由于第三绝缘层在衬底基板上的正投影与第一过孔在衬底基板上的正投影不重叠，因此通过设计使得保护层的保护图案覆盖第一过孔，可以避免过孔处的第二绝缘层被过刻，或者，即使过孔处的第二绝缘层被过刻，也不会导致转接结构和第一电路结构的第二电路子图案短接，保证了显示面板的良率。
作为一种可选的实现方式，参考图15，转接结构104可以包括相对的第一侧面104a和第二侧面104b，第一侧面104a相对于第二侧面104b更靠近多个像素单元102。第二侧面104b在衬底基板101上的正投影位于第一阻挡坝1031在衬底基板101上的正投影内，且转接结构104在衬底基板101上的正投影与第二阻挡坝1032在衬底基板101上的正投影不重叠。也即是，转接结构104可以位于第一阻挡坝1031和显示区域101a之间的区域，而不位于第一阻挡坝1031和第二阻挡坝1032之间的区域。
在该实现方式中，由于转接结构104的第二侧面104b(边界)在衬底基板101上的正投影位于第一阻挡坝1031在衬底基板101上的正投影内，因此转接结构104与第一电路结构106a的第二电路子图案b22会存在短接风险，而与第二电路结构106b的第四电路子图案b44不会存在短接风险。
并且，由于本申请实施例中的保护层M的保护图案在衬底基板101上的正投影覆盖第二电路子图案b22在衬底基板101上的正投影，因此可以避免转接结构104和第二电路子图案b22短接。
其中，保护层M可以位于第一金属层和衬底基板101之间，或者保护层M可以位于第二绝缘层107远离衬底基板101的一侧。由此，通过设计保护层M，要么可以避免第一过孔c1处的第二绝缘层107被过刻，要么即使第一过孔c1处的第二绝缘层107被过刻，也不会导致转接结构104和第一电路结构106a的第二电路图案b22短接，保证了显示面板10的良率。
在本申请实施例中，保护层M可以具有以下几种可选的实现方式：
方案一，参考图15，保护层M包括的多个保护图案位于第三绝缘层108。也即是，保护层M的多个保护图案可以与第三绝缘层108的主体图案1081采用相同材料并由同一次构图工艺制备得到。例如，图15中，第三绝缘层108包括的第九绝缘图案1084即为保护图案。
也即是，在位于第一过孔c1处的第二绝缘层107的上方设计有第九绝缘图案，该第九绝缘图案可以起到将转接结构104和第二电路子图案b22绝缘的作用。由此，即使第一过孔c1处的第二绝缘层107过刻(如由于第二绝缘层107过刻而导致暴露出第一电路结构106a的第二电路子图案b22)，由于该第三绝缘层108的第九绝缘图案1084可覆盖第二绝缘层107过刻的区域，因此可以避免转接结构104和第二电路子图案b22短接，保证显示面板10的良率。
方案二，参考图16，保护层M为位于第二绝缘层107远离衬底基板101的一侧的第三金属层109。第三金属层109包括的多个金属图案1091为保护图案。金属图案1091在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影。
其中，第三金属层109可以为显示面板的第二源漏极层。通常情况下，第三金属层109不位于周边区域101b，因此采用刻蚀液刻蚀用于形成第三金属层109的第三金属薄膜时，需将第三金属薄膜位于周边区域101b的部分刻蚀掉。但是，刻蚀第三金属薄膜的过程中，容易导致刻蚀液聚集在过孔(第一过孔c1或第二过孔c2)的位置，导致第二绝缘层107位于过孔处的部分被过刻。
本申请实施例的方案中，保留第三金属层109位于第一过孔c1的金属图案1091，由此可以在刻蚀第三金属薄膜时，无需将位于第一过孔c1内的第三金属薄膜刻蚀掉，进而不会导致刻蚀液聚集在第一过孔c1内，避免位于第一过孔c1处的第二绝缘层107过刻。进一步的可以避免转接结构104和第一电路结构106a的第二电路子图案b22短接。并且，由于转接结构104在衬底基板101上的正投影与第二电路结构106b在衬底基板101上的正投影不重叠，因此转接结构104和第二电路结构106b的第四电路子图案b44没有短接风险。由此，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板10的良率。
在本申请实施例中，由于第三金属层109中的金属图案1091具有导电能力，因此可以通过设计信号线与金属图案1091连接，以为金属图案1091提供一固定电压。当然，由于设计信号线会导致显示面板中的走线较多，版图设计较困难，因此也可以直接使得金属图案1091为浮动(floating)图案，无需为金属图案1091提供固定电压。
方案三，参考图17，保护层M为位于衬底基板101和第一金属层之间的有源层110。有源层110包括的多个有源图案1101即为保护图案。有源图案1101 在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影。
本申请实施例的方案中，由于有源层110位于第一金属层靠近衬底基板101的一侧，因此通过在第一过孔c1处设计有源图案1101，可以使得位于有源图案1101远离衬底基板101的一侧的第一电路子图案b11和第二电路子图案b22的距离均较近，进而可以使得第一绝缘层105位于第一电路子图案b11和第二电路子图案b22的厚度较薄。由此，可以减小第一绝缘层105中设计的第一过孔c1的深度。由于第一绝缘层105中的第一过孔c1的深度较小，因此可以减小刻蚀液的聚集程度，降低位于第一过孔c1处的第二绝缘层107被过刻的概率，进而避免转接结构104和第二电路子结构22短接。并且，由于转接结构104在衬底基板101上的正投影与第二电路结构106b在衬底基板101上的正投影不重叠，因此转接结构104和第二电路结构106b的第四电路子图案b44没有短接风险。由此，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板的良率。
需要说明的是，在该方案二中，第一绝缘层105可以包括第一子绝缘层1051和第二子绝缘层1052。第一子绝缘层1051位于有源层和第一金属层之间，第二绝缘层1052位于第一金属层和第二金属层之间。
方案四，参考图18，保护层M为位于衬底基板101和第一金属层之间的遮光层111。遮光层111包括的多个遮光图案1111即为保护图案。遮光图案1111在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影。
本申请实施例的方案中，由于遮光层111位于第一金属层靠近衬底基板101的一侧，因此通过在第一过孔c1处设计遮光图案，可以使得位于遮光图案1111远离衬底基板101的一侧的第一电路子图案b11和第二电路子图案b22的距离均较近，进而可以使得第一绝缘层105位于第一电路子图案b11和第二电路子图案b22的厚度较薄。由此，可以减小第一绝缘层105中设计的第一过孔c1的深度。由于第一绝缘层105中的第一过孔c1的深度较小，因此可以减小刻蚀液的聚集程度，降低位于第一过孔c1处的第二绝缘层107被过刻的概率，进而避免转接结构104和第二电路子结构22短接。并且，由于转接结构104在衬底基板101上的正投影与第二电路结构106b在衬底基板101上的正投影不重叠，因此转接结构104和第二电路结构106b的第四电路子图案b44没有短接风险。由此，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板的良率。
需要说明的是，在该方案三中，第一绝缘层105可以包括第一子绝缘层1051， 第二子绝缘层1052以及第三子绝缘层1053。第一子绝缘层1051位于衬底基板101和遮光层111之间，第二子绝缘层1052位于遮光层111和第一金属层之间，第三子绝缘层1053位于第一金属层和第二金属层之间。
作为另一种可选的实现方式，参考图19，转接结构104可以包括相对的第一侧面104a和第二侧面104b，第一侧面104a相对于第二侧面104b更靠近多个像素单元102。第二侧面104b在衬底基板101上的正投影位于第二阻挡坝1032在衬底基板101上的正投影内，且转接结构104在衬底基板101上的正投影与第一阻挡坝1031在衬底基板101上的正投影重叠。也即是，转接结构104可以位于第一阻挡坝1031和显示区域101a之间的区域，也位于第一阻挡坝1031和第二阻挡坝1032之间的区域。
在该实现方式中，由于转接结构104的第二侧面104b(边界)在衬底基板101上的正投影位于第二阻挡坝1032在衬底基板101上的正投影内，因此转接结构104与第一电路结构106a的第二电路子图案b22以及第二电路结构106b的第四电路子图案b44均会存在短接风险。由此，为了避免转接结构104与第一电路结构106a的第二电路子图案b22以及第二电路结构106b的第四电路子图案b44短接，保护层M包括多个第一保护图案和多个第二保护图案。第一保护图案在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影，第二保护图案在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
其中，保护层M可以位于第一金属层和衬底基板101之间，或者保护层M可以位于第二绝缘层107远离衬底基板101的一侧。由此，通过设计保护层M，要么可以避免第一过孔c1处和第二过孔c2处的第二绝缘层107被过刻，要么即使第一过孔c1处和第二过孔c2处的第二绝缘层107被过刻，也不会导致转接结构104和电路结构短接，保证了显示面板10的良率。
在本申请实施例中，保护层M可以具有以下几种可选的实现方式：
方案一，参考图19和图20，保护层M包括的多个保护图案位于第三绝缘层108。也即是，保护层M的多个保护图案可以与第三绝缘层108的主体图案1081采用相同材料并由同一次构图工艺制备得到。例如，图19中，第三绝缘层108包括的第九绝缘图案1084即为第一保护图案，第十绝缘图案1085即为第二保护图案。
也即是，在位于第一过孔c1处的第二绝缘层107的上方设计有第九绝缘图案，在位于第二过孔c2处的第二绝缘层107的上方设计有第十绝缘图案。该第九绝缘图案可以起到将转接结构104和第二电路子图案b22绝缘的作用，该第十绝缘图案可以起到将转接结构104和第四电路子图案b44绝缘的作用。由此，即使第一过孔c1处和第二过孔c2处的第二绝缘层107过刻(如由于第二绝缘层107过刻而导致暴露出第一电路结构106a的第二电路子图案b22以及暴露出第二电路结构106b的第四电路子图案b44)，由于该第三绝缘层108的第九绝缘图案1083和第十绝缘图案1084可覆盖第二绝缘层107过刻的区域，因此可以避免转接结构104和第二电路子图案b22以及第四电路子图案b44短接，保证显示面板10的良率。
方案二，参考图21，保护层M为位于第二绝缘层107远离衬底基板101的一侧的第三金属层109。第三金属层109包括多个第一金属图案1091和多个第二金属图案1092，第一金属图案1091为第一保护图案，第二金属图案1092为第二保护图案。第一金属图案1091在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影，第二金属图案1092在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
其中，第三金属层109可以为显示面板的第二源漏极层。通常情况下，第三金属层109不位于周边区域101b，因此采用刻蚀液刻蚀用于形成第三金属层109的第三金属薄膜时，需将第三金属薄膜位于周边区域101b的部分刻蚀掉。但是，刻蚀第三金属薄膜的过程中，容易导致刻蚀液聚集在过孔(第一过孔c1或第二过孔c2)的位置，导致第二绝缘层107位于过孔处的部分被过刻。
本申请实施例的方案中，保留第三金属层109位于第一过孔c1的第一金属图案1091以及位于第二过孔c2的第二金属图案1092，由此可以在刻蚀第三金属薄膜时，无需将位于第一过孔c1内和第二过孔c2内的第三金属薄膜刻蚀掉，进而不会导致刻蚀液聚集在第一过孔c1和第二过孔c2内，避免位于第一过孔c1和第二过孔c2处的第二绝缘层107过刻。进一步的可以避免转接结构104和第一电路结构106a的第二电路子图案b22以及第二电路结构106b的第四电路子图案b44短接。由此，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板的良率。
方案三，参考图22，保护层M为位于衬底基板101的第一金属层之间的有 源层110。有源层110包括的多个第一有源图案1101即为第一保护图案，多个第二有源图案1102即为第二保护图案。第一有源图案1101在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影，第二有源图案1102在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
本申请实施例的方案中，由于有源层110位于第一金属层靠近衬底基板101的一侧，因此通过在第一过孔c1处设计第一有源图案1101，在第二过孔c2处设计第二有源图案1102，可以使得位于第一有源图案1101远离衬底基板101的一侧的第一电路子图案b11和第二电路子图案b22的距离较近，且使得位于第二有源图案1102远离衬底基板101的一侧的第三电路子图案b33和第四电路子图案b44的距离较近，进而可以使得第一绝缘层105位于第一电路子图案b11和第二电路子图案b22的区域，以及位于第三电路子图案b33和第四电路子图案b44的区域的厚度较薄。由此，可以减小第一绝缘层105中设计的第一过孔c1和第二过孔c2的深度。由于第一绝缘层105中的第一过孔c1和第二过孔c2的深度较小，因此可以减小刻蚀液的聚集程度，降低位于第一过孔c1和第二过孔c2处的第二绝缘层107被过刻的概率，进而避免转接结构104和第二电路子结构b11以及第四电路子结构b44短接。也即是，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板的良率。
需要说明的是，在该方案三中，第一绝缘层105可以包括第一子绝缘层1051和第二子绝缘层1052。第一子绝缘层1051位于有源层和第一金属层之间，第二绝缘层1052位于第一金属层和第二金属层之间。
方案四，参考图23，保护层M为位于衬底基板101和第一金属层之间的遮光层111。遮光层111包括的多个第一遮光图案1111即为第一保护图案，多个第二遮光图案1112即为第二保护图案。第一遮光图案1111在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影，第二遮光图案1112在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
本申请实施例的方案中，由于遮光层111位于第一金属层靠近衬底基板101的一侧，因此通过在第一过孔c1处设计第一遮光图案1111，在第二过孔c2处设计第二遮光图案1112，可以使得位于第一遮光图案1111远离衬底基板101的一侧的第一电路子图案b11和第二电路子图案b22的距离较近，且使得位于第二遮光图案1112远离衬底基板101的一侧的第三电路子图案b33和第四电路子 图案b44的距离较近，进而可以使得第一绝缘层105位于第一电路子图案b11和第二电路子图案b22的区域，以及位于第三电路子图案b33和第四电路子图案b44的区域的厚度较薄。由此，可以减小第一绝缘层105中设计的第一过孔c1和第二过孔c2的深度。由于第一绝缘层105中的第一过孔c1和第二过孔c2的深度较小，因此可以减小刻蚀液的聚集程度，降低位于第一过孔c1和第二过孔c2处的第二绝缘层107被过刻的概率，进而避免转接结构104和第二电路子结构以及第四电路子结构短接。也即是，第一过孔c1和第二过孔c2均没有短接风险，保证显示面板的良率。
需要说明的是，在该方案四中，第一绝缘层105可以包括第一子绝缘层1051，第二子绝缘层1052以及第三子绝缘层1053。第一子绝缘层1051位于衬底基板101和遮光层111之间，第二子绝缘层1052位于遮光层111和第一金属层之间，第三子绝缘层1053位于第一金属层和第二金属层之间。
在本申请实施例中，第一保护图案在衬底基板101上的正投影的面积，减去第一过孔c1在衬底基板101上的正投影的面积的差值的范围为1μm2至50μm2。通过使得第一保护图案稍大于第一过孔c1，可以避免转接结构104和第二电路子图案b22短接。第二保护图案在衬底基板101上的正投影的面积，减去第二过孔c2在衬底基板101上的正投影的面积的差值的范围为1μm2至50μm2。通过使得第二保护图案稍大于第二过孔c2，可以避免转接结构104和第四电路子图案b44短接。
另外，为了降低制备保护层M所采用的掩膜板的制备难度，需降低保护图案的设置密度。例如，可以使得多个第一过孔c1对应一个第一保护图案，多个第二过孔c2对应一个第二保护图案(即每个第一保护图案在衬底基板101上的正投影覆盖多个第一过孔c1在衬底基板101上的正投影，第一保护图案的数量少于第一过孔c1的数量；每个第二保护图案在衬底基板101上的正投影覆盖多个第二过孔c2在衬底基板101上的正投影，第二保护图案的数量少于第二过孔c2的数量)。可选的，第一保护图案的形状可以基于第一过孔c1的设计调整，第二保护图案的形状可以基于第二过孔c2的设计调整，例如第一保护图案和第二保护图案设计为长条形或其他形状，本申请实施例对保护图案的形状不做限定。
可选的，多个第一过孔c1中包括多个目标第一过孔，多个目标第一过孔在 衬底基板101上的正投影被同一第一保护图案在衬底基板101上的正投影覆盖。如果过多个目标第一过孔中任一目标第一过孔与另一目标第一过孔之间的间隙小于4μm，则可认为这两个目标第一过孔之间的间隙较小，可以通过一个第一保护图案覆盖。多个第二过孔c2中包括多个目标第二过孔，多个目标第二过孔在衬底基板101上的正投影被同一第二保护图案在衬底基板101上的正投影覆盖。如果多个目标第二过孔中任一目标第二过孔与另一目标第二过孔之间的间隙小于4μm，则可认为这两个目标第二过孔之间的间隙较小，可以通过一个第二保护图案覆盖。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括衬底基板，多个像素单元，阻挡结构，转接结构，第一绝缘层，电路结构，第二绝缘层，第三绝缘层以及保护层。其中，第一绝缘层位于第一电路结构的第一电路子图案和第二电路子图案之间，且具有第一过孔，第一电路子图案和第二电路子图案通过第一过孔电连接。由于第三绝缘层在衬底基板上的正投影与第一过孔在衬底基板上的正投影不重叠，因此通过设计使得保护层的保护图案覆盖第一过孔，可以避免过孔处的第二绝缘层被过刻，或者，即使过孔处的第二绝缘层被过刻，也不会导致转接结构和第一电路结构的第二电路子图案短接，保证了显示面板的良率。
本申请实施例提供的显示面板中的其他相关描述可以与前面的实施例描述的显示面板的内容相同，因此，出于简洁的目的，此处不再赘述。
图24是本申请实施例提供的再一种显示面板在周边区域的局部截面图。参考图24，该显示面板10包括：衬底基板101，多个像素单元(图24中未示出，可参考图1)，阻挡结构103，转接结构104，第一绝缘层105，电路结构106，第二绝缘层107，以及第三绝缘层108。
结合图1，图3以及图24，该多个像素单元102位于显示区域101a，阻挡结构103，转接结构104和电路结构106均位于周边区域101b。
参考图4，像素单元102包括发光单元1021。该发光单元1021包括依次层叠的第一电极层a1，发光层a2以及第二电极层a3。例如第一电极层a1为阳极层，第二电极层a3为阴极层。
结合图1，图3和图24，阻挡结构103可以围绕多个像素单元102。转接结 构104在衬底基板101上的正投影远离显示区域101a的边缘相对于阻挡结构103在衬底基板101上的正投影远离显示区域101a的边缘更靠近显示区域101a，该转接结构104与第一电极层a1位于同层且具有间隙，且转接结构104与第二电极层a3电连接。也即是，转接结构104与第一电极层a1采用相同材料并由同一次构图工艺制备得到。转接结构104和第二电极层a3所传输的信号为相同信号。
参考图24，电路结构106位于周边区域101b，且电路结构106包括第一电路结构106a，该第一电路结构106a包括第一电路子图案b11和第二电路子图案b22。其中，第一电路子图案b11位于第一金属层，第二电路子图案b22位于第二金属层，显示面板10包括的第一绝缘层105位于第一金属层和第二金属层之间。该第一绝缘层105位于周边区域101b的部分具有过孔(过孔包括第一过孔c1)，第一电路子图案b11和第二电路子图案b22通过第一过孔c1电连接。第二绝缘层107位于第二金属层远离衬底基板101的一侧，用于将第二金属层中的第二电路子图案b22和与第一电极层a1位于同层的转接结构104绝缘。
在本申请实施例中，第三绝缘层108包括位于显示区域101a和周边区域101b的主体图案1081，该主体图案1081包括位于周边区域101b的第三侧面1081a。第三侧面1081a在衬底基板101上的正投影位于阻挡结构103和显示区域101a之间。也即是，主体图案1081在衬底基板101上的正投影与第一电路结构106a在衬底基板101上的正投影不重叠。
由此，为了避免转接结构104和第一电路结构106a的第二电路子图案b22短接，可以使得转接结构104包括多个开口d1，开口d1在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影，即转接结构104在衬底基板101上的正投影与第一过孔c1在衬底基板101上的正投影不重叠。由此即使第一过孔处的第二绝缘层107被过刻，也不会导致转接结构104和第一电路结构106的第二电路子图案b22短接，保证了显示面板10的良率。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括衬底基板，多个像素单元，阻挡结构，转接结构，第一绝缘层，电路结构，第二绝缘层，第三绝缘层以及保护层。其中，第一绝缘层位于第一电路结构的第一电路子图案和第二电路子图案之间，且具有第一过孔，第一电路子图案和第二电路子图案通过第一过孔电连接。由于转接结构包括的开口在衬底基板上的正投影覆盖第一过孔在衬底基板上的正投影，因此即使第一过孔处的第二绝缘层107被过 刻，也不会导致转接结构和第一电路结构的第二电路子图案短接，保证了显示面板的良率。
作为一种可选的实现方式，参考图24，转接结构104可以包括相对的第一侧面104a和第二侧面104b，第一侧面104a相对于第二侧面104b更靠近多个像素单元102。第二侧面104b在衬底基板101上的正投影位于第一阻挡坝1031在衬底基板101上的正投影内，且转接结构104在衬底基板101上的正投影与第二阻挡坝1032在衬底基板101上的正投影不重叠。也即是，转接结构104可以位于第一阻挡坝1031和显示区域101a之间的区域，而不位于第一阻挡坝1031和第二阻挡坝1032之间的区域。
在该实现方式中，由于转接结构104的第二侧面104b(边界)在衬底基板101上的正投影位于第一阻挡坝1031在衬底基板101上的正投影内，因此转接结构104与第一电路结构106a的第二电路子图案b22会存在短接风险，而与第二电路结构106b的第四电路子图案b44不会存在短接风险。
并且，由于本申请实施例中的转接结构104的开口d1在衬底基板101上的正投影覆盖第一过孔c1，因此转接结构104在衬底基板101上的正投影和第二电路子结构b22在衬底基板上的正投影不重叠。由此，即使第一过孔c1处的第二绝缘层107被过刻，也不会导致转接结构104和第一电路结构106a的第二电路图案b22短接，保证了显示面板10的良率。
作为另一种可选的实现方式，参考图25至图27，转接结构104可以包括相对的第一侧面104a和第二侧面104b，第一侧面104a相对于第二侧面104b更靠近多个像素单元102。第二侧面104b在衬底基板101上的正投影位于第二阻挡坝1032在衬底基板101上的正投影内，且转接结构104在衬底基板101上的正投影与第一阻挡坝1031在衬底基板101上的正投影重叠。也即是，转接结构104可以位于第一阻挡坝1031和显示区域101a之间的区域，也位于第一阻挡坝1031和第二阻挡坝1032之间的区域。
在该实现方式中，由于转接结构104的第二侧面104b(边界)在衬底基板101上的正投影位于第二阻挡坝1032在衬底基板101上的正投影内，因此转接结构104与第一电路结构106a的第二电路子图案b22以及第二电路结构106b的第四电路子图案b44均会存在短接风险。由此，为了避免转接结构104与第一电路结构106a的第二电路子图案b22以及第二电路结构106b的第四电路子 图案b44短接，可以使得转接结构104的开口包括第一开口d1和第二开口d2。第一开口d1在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影，第二开口d2在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。
参考图26至图27，转接结构104包括多个第一开口d1和多个第二开口d2。图26中以虚线为分界线，左侧的较小尺寸的开口为第二开口d2，右侧的较小尺寸的开口为第一开口d1。并且，转接结构104中的较大开口可以为排气孔。图27中未标注的两个大括号的位置为第三绝缘层108挖除的区域。可见，转接结构104中设计的多个第一开口d1和多个第三开口d2可以位于第三绝缘层108挖除的区域。
其中，第一开口d1在衬底基板101上的正投影覆盖第一过孔c1在衬底基板101上的正投影。第二开口d2在衬底基板101上的正投影覆盖第二过孔c2在衬底基板101上的正投影。由于转接结构104在第一过孔c1处具有第一开口d1，在第二过孔c2处具有第二开口d2，因此即使该第一过孔c1和第二过孔c2处的第二绝缘层107过刻(如由于第二绝缘层107过刻而导致暴露出第一电路结构106a的第二电路子图案b22和第二电路结构106b的第四电路子图案b44)，也不会导致转接结构104与第二电路子图案b22以及第四电路子图案b44短接，保证显示面板10的良率。
可选的，第一开口d1在衬底基板101上的正投影的面积，减去第一过孔c1在衬底基板101上的正投影的面积的差值的范围为1μm2至50μm2。第二开口d2在衬底基板101上的正投影的面积，减去第二过孔c2在衬底基板101上的正投影的面积的差值的范围为1μm2至50μm2。
通过使得第一开口d1稍大于第一过孔c1，可以进一步确保转接结构104和第二电路子图案b22不会短接。并且，通过使得第二开口d2稍大于第二过孔c2，可以进一步确保转接结构104和第四电路子图案b44不会短接。
另外，显示面板10中第一过孔c1的孔密度以及第二过孔c2的孔密度和显示面板中GOA电路的具体设计相关。如果第一过孔c1或第二过孔c2的孔密度较小，则即使每个第一过孔c1对应有一个第一开口d1，每个第二过孔c2对应有一个第二开口d2，也不会使得第一开口d1或第二开口d2的设置密度太大。此种情况下，制备该转接结构104所采用的掩膜板的制备难度不会太大。但是， 如果第一过孔c1或第二过孔c2的孔密度较大，则若每个第一过孔c1或第二过孔c2对应一个开口，则会导致开口的设置密度太大，制备该转接结构104所采用的掩膜板的制备难度较高。此种情况下，为了降低开口的设置密度，可以使得多个第一过孔c1对应一个第一开口d1，多个第二过孔c2对应一个第二开口d2。可选的，第一开口d1的形状可以基于第一过孔c1的设计调整，第二开口d2的形状可以基于第二过孔c2的设计调整。例如调整为长条形或其他形状，本申请实施例对开口的形状不做限定。
可选的，多个第一过孔c1包括多个目标第一过孔，多个目标第一过孔在衬底基板101上的正投影被同一第一开口d1在衬底基板101上的正投影覆盖。如果多个目标第一过孔中任一目标第一过孔与另一目标第一过孔之间的间隙小于4μm，则可认为这两个目标第一过孔之间的间隙较小，可以通过一个第一开口d1覆盖。相应的，多个第二过孔c2包括多个目标第二过孔，多个目标第二过孔在衬底基板101上的正投影被同一第二开口d2在衬底基板101上的正投影覆盖。如果多个目标第二过孔中任一目标第二过孔与另一目标第二过孔之间的间隙小于4μm，则可以认为这两个目标第一过孔之间的间隙较小，可以通过一个第二开口d3覆盖。
综上所述，本申请实施例提供了一种显示面板，该显示面板包括衬底基板，多个像素单元，阻挡结构，转接结构，第一绝缘层，电路结构，第二绝缘层，第三绝缘层以及保护层。其中，第一绝缘层位于第一电路结构的第一电路子图案和第二电路子图案之间，且具有第一过孔，第一电路子图案和第二电路子图案通过第一过孔电连接。由于转接结构包括的开口在衬底基板上的正投影覆盖第一过孔在衬底基板上的正投影，因此即使第一过孔处的第二绝缘层107被过刻，也不会导致转接结构和第一电路结构的第二电路子图案短接，保证了显示面板的良率。
本申请实施例提供的显示面板中的其他相关描述可以与前面的实施例描述的显示面板的内容相同，因此，出于简洁的目的，此处不再赘述。
图28是本申请实施例提供的一种显示装置的结构示意图。参考图28，该显示装置包括供电组件20以及如上述实施例所提供的显示面板10。其中，供电组件20可以用于为显示面板10供电。
可选的，该显示装置可以为OLED显示装置、液晶显示装置、电子纸、手机、平板电脑、电视机、显示器、笔记本电脑、数码相框或导航仪等任何具有显示功能的产品或部件。
由于显示装置可以与前面实施例描述的显示面板具有基本相同的技术效果，因此，出于简洁的目的，此处不再重复描述显示装置的技术效果。
将理解的是，尽管术语第一和第二等在本文中可以用来描述各种元件、部件、区、层和/或部分，但是这些元件、部件、区、层和/或部分不应当由这些术语限制。这些术语仅用来将一个元件、部件、区、层或部分与另一个区、层或部分相区分。因此，上面讨论的第一元件、部件、区、层或部分可以被称为第二元件、部件、区、层或部分而不偏离本公开的教导。
诸如“在…之下”、“在…之上”、“左”、“右”等等之类的空间相对术语在本文中可以为了便于描述而用来描述如图中所图示的一个元件或特征与另一个(些)元件或特征的关系。将理解的是，这些空间相对术语意图涵盖除了图中描绘的取向之外在使用或操作中的器件的不同取向。例如，如果翻转图中的器件，那么被描述为“在其他元件或特征之下”的元件将取向为“在其他元件或特征之上”。因此，示例性术语“在…之下”可以涵盖在…之上和在…之下的取向两者。器件可以取向为其他方式(旋转90度或以其他取向)并且相应地解释本文中使用的空间相对描述符。另外，还将理解的是，当层被称为“在两个层之间”时，其可以是在该两个层之间的唯一的层，或者也可以存在一个或多个中间层。
本文中使用的术语仅出于描述特定实施例的目的并且不意图限制本公开。如本文中使用的，单数形式“一个”、“一”和“该”意图也包括复数形式，除非上下文清楚地另有指示。将进一步理解的是，术语“包括”和/或“包含”当在本说明书中使用时指定所述特征、整体、步骤、操作、元件和/或部件的存在，但不排除一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组的存在或添加一个或多个其他特征、整体、步骤、操作、元件、部件和/或其群组。如本文中使用的，术语“和/或”包括相关联的列出项目中的一个或多个的任意和全部组合。在本说明书中，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的 情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结合和组合。
除非另有定义，本文中使用的所有术语(包括技术术语和科学术语)具有与本公开所属领域的普通技术人员所通常理解的相同含义。将进一步理解的是，诸如那些在通常使用的字典中定义的之类的术语应当被解释为具有与其在相关领域和/或本说明书上下文中的含义相一致的含义，并且将不在理想化或过于正式的意义上进行解释，除非本文中明确地如此定义。
以上所述仅为本申请的可选实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (20)

  1. 一种显示面板，其特征在于，所述显示面板(10)包括：
    衬底基板(101)，所述衬底基板(101)具有显示区域(101a)以及围绕所述显示区域(101a)的周边区域(101b)；
    多个像素单元(102)，位于所述显示区域(101a)，所述像素单元(102)包括发光单元(1021)，所述发光单元(1021)包括依次层叠的第一电极层(a1)，发光层(a2)以及第二电极层(a3)；
    阻挡结构(103)，位于所述周边区域(101b)且围绕所述多个像素单元(102)；
    转接结构(104)，位于所述周边区域(101b)，所述转接结构(104)与所述第一电极层(a1)位于同层且具有间隙，且所述转接结构(104)与所述第二电极层(a3)电连接；
    第一绝缘层(105)，位于所述第一电极层(a1)和所述衬底基板(101)之间，且所述第一绝缘层(105)位于所述周边区域(101b)的部分具有过孔；
    电路结构(106)，位于所述周边区域(101b)，所述电路结构(106)包括位于所述阻挡结构(103)围成的区域内的第一电路结构(106a)，所述第一电路结构(106a)包括第一电路子图案(b11)和第二电路子图案(b22)，所述第一电路子图案(b11)位于第一金属层，所述第二电路子图案(b22)位于第二金属层，所述第一金属层和所述第二金属层位于所述第一绝缘层(105)两侧，所述第一绝缘层(105)的过孔包括第一过孔(c1)，所述第一电路子图案(b11)和所述第二电路子图案(b22)通过所述第一过孔(c1)电连接；
    第二绝缘层(107)，位于所述第二金属层远离所述衬底基板(101)的一侧；
    以及位于所述第二绝缘层(107)远离所述衬底基板(101)的一侧的第三绝缘层(108)，第三绝缘层(108)包括位于所述显示区域(101a)和所述周边区域(101b)的主体图案(1081)，所述主体图案(1081)包括位于所述周边区域(101b)的第三侧面(1081a)；所述第三侧面(1081a)在所述衬底基板(101)上的正投影位于所述阻挡结构(103)在所述衬底基板(101)上的正投影内，且所述主体图案(1081)位于所述周边区域(101b)的部分在所述第三侧面(1081a)靠近所述显示区域(101a)的一侧为连续性图案。
  2. 根据权利要求1所述的显示面板，其特征在于，所述阻挡结构(103)包括第一阻挡坝(1031)和第二阻挡坝(1032)；所述第一阻挡坝(1031)相对于所述第二阻挡坝(1032)靠近所述多个像素单元(102)，且所述第一阻挡坝(1031)的厚度小于所述第二阻挡坝(1032)的厚度；
    所述转接结构(104)包括相对的第一侧面(104a)和第二侧面(104b)，所述第一侧面(104a)相对于所述第二侧面(104b)更靠近所述多个像素单元(102)；
    其中，所述第二侧面(104b)在所述衬底基板(101)上的正投影位于所述第一阻挡坝(1031)在所述衬底基板(101)上的正投影内，所述转接结构(104)在所述衬底基板(101)上的正投影与所述第二阻挡坝(1032)在所述衬底基板(101)上的正投影不重叠。
  3. 根据权利要求2所述的显示面板，其特征在于，所述电路结构(106)还包括位于所述第一阻挡坝(1031)和所述第二阻挡坝(1032)之间的第二电路结构(106b)；
    所述第二电路结构(106b)包括第三电路子图案(b33)和第四电路子图案(b44)，所述第三电路子图案(b33)位于所述第一金属层，所述第四电路子图案(b44)位于所述第二金属层，所述第一绝缘层(105)的过孔包括第二过孔(c2)，所述第三电路子图案(b33)和所述第四电路子图案(b44)通过所述第二过孔(c2)电连接。
  4. 根据权利要求1所述的显示面板，其特征在于，所述阻挡结构(103)包括第一阻挡坝(1031)和第二阻挡坝(1032)；所述第一阻挡坝(1031)相对于所述第二阻挡坝(1032)靠近所述多个像素单元(102)，且所述第一阻挡坝(1031)的厚度小于所述第二阻挡坝(1032)的厚度；
    所述转接结构(104)包括相对的第一侧面(104a)和第二侧面(104b)，所述第一侧面(104a)相对于所述第二侧面(104b)更靠近所述多个像素单元(102)；
    其中，所述第二侧面(104b)在所述衬底基板(101)上的正投影位于所述 第二阻挡坝(1032)在所述衬底基板(101)上的正投影内，所述转接结构(104)在所述衬底基板(101)上的正投影与所述第一阻挡坝(1031)在所述衬底基板(101)上的在正投影重叠。
  5. 根据权利要求4所述的显示面板，其特征在于，所述电路结构(106)还包括位于所述第一阻挡坝(1031)和所述第二阻挡坝(1032)之间的第二电路结构(106b)；
    所述第二电路结构(106b)包括第三电路子图案(b33)和第四电路子图案(b44)，所述第一绝缘层(105)的过孔包括第二过孔(c2)，所述第三电路子图案(b33)和所述第四电路子图案(b44)通过所述第二过孔(c2)电连接；
    所述显示面板(10)还包括：位于所述衬底基板上的保护层(M)，所述保护层(M)包括多个保护图案，所述保护图案在所述衬底基板(101)上的正投影覆盖所述第二过孔(c2)在所述衬底基板(101)上的正投影。
  6. 根据权利要求5所述的显示面板，其特征在于，所述多个保护图案位于所述第三绝缘层(108)。
  7. 根据权利要求5所述的显示面板，其特征在于，所述保护层(M)为位于所述第二绝缘层(107)远离所述衬底基板(101)的一侧的第三金属层(109)；
    所述第三金属层(109)包括的多个金属图案(1091)为所述多个保护图案，所述金属图案(1091)在所述衬底基板(101)上的在正投影覆盖所述第二过孔(c2)在所述衬底基板(101)上的正投影。
  8. 根据权利要求5所述的显示面板，其特征在于，所述保护层(M)为位于所述衬底基板(101)和所述第一金属层之间的有源层(110)；
    所述有源层(110)包括的多个有源图案(1101)为所述多个保护图案，所述有源图案(1101)在所述衬底基板(101)上的在正投影覆盖所述第二过孔(c2)在所述衬底基板(101)上的正投影。
  9. 根据权利要求5所述的显示面板，其特征在于，所述保护层(M)为位于 所述衬底基板(101)和所述第一金属层之间的遮光层(111)；
    所述遮光层(111)包括的多个遮光图案(1111)为所述多个保护图案，所述遮光图案(1111)在所述衬底基板(101)上的正投影覆盖所述第二过孔(c2)在所述衬底基板(101)上的正投影。
  10. 根据权利要求5至9任一所述的显示面板，其特征在于，所述保护图案在所述衬底基板(101)上的正投影的面积，减去所述第二过孔(c2)在所述衬底基板(101)上的正投影的面积的差值的范围为1平方微米至50平方微米。
  11. 根据权利要求5至10任一所述的显示面板，其特征在于，所述多个第二过孔(c2)包括多个目标第二过孔，所述多个目标第二过孔在所述衬底基板(101)上的正投影被同一所述保护图案在所述衬底基板(101)上的正投影覆盖；
    其中，所述多个目标第二过孔中任一目标第二过孔与另一目标第二过孔之间的间隙小于4微米。
  12. 根据权利要求4所述的显示面板，其特征在于，所述电路结构(106)还包括位于所述第一阻挡坝(1031)和所述第二阻挡坝(1032)之间的第二电路结构(106b)；
    所述第二电路结构(106b)包括第三电路子图案(b33)和第四电路子图案(b44)，所述第一绝缘层(105)的过孔包括第二过孔(c2)，所述第三电路子图案(b33)和所述第四电路子图案(b44)通过所述第二过孔(c2)电连接；
    所述转接结构(104)包括多个开口，所述开口在所述衬底基板(101)上的正投影覆盖所述第二过孔(c2)在所述衬底基板(101)上的正投影。
  13. 根据权利要求12所述的显示面板，其特征在于，所述开口在所述衬底基板(101)上的正投影的面积，减去所述第二过孔(c2)在所述衬底基板(101)上的正投影的面积的差值的范围为1平方微米至50平方微米。
  14. 根据权利要求12或13所述的显示面板，其特征在于，所述多个第二过孔(c2)包括多个目标第二过孔，所述多个目标第二过孔在所述衬底基板(101) 上的正投影被同一所述开口在所述衬底基板(101)上的正投影覆盖；
    其中，所述多个目标第二过孔中任一目标第二过孔与另一目标第二过孔之间的间隙小于4微米。
  15. 根据权利要求2至14任一所述的显示面板，其特征在于，所述第三绝缘层(108)还包括：第一绝缘图案(1082)；所述显示面板(10)还包括位于所述第三绝缘层(108)远离所述衬底基板(101)的一侧的第四绝缘层(112)，所述第四绝缘层(112)包括第二绝缘图案(1121)和第三绝缘图案(1122)；
    所述第一阻挡坝(1031)至少包括所述第二绝缘图案(1121)，所述第二阻挡坝(1032)至少包括沿远离所述衬底基板(101)的方向层叠设置的第一绝缘图案(1082)和第二绝缘图案(1122)。
  16. 根据权利要求1至15任一所述的显示面板，其特征在于，所述转接结构(104)在所述衬底基板(101)上的正投影远离所述显示区域(101a)的边缘相对于所述阻挡结构(103)在所述衬底基板(101)上的正投影远离所述显示区域(101a)的边缘更靠近所述显示区域(101a)；
    所述主体图案(1081)在所述衬底基板(101)上的正投影与所述第二阻挡坝(1032)在所述衬底基板(101)上的正投影不重叠。
  17. 根据权利要求1至16任一所述的显示面板，其特征在于，所述显示面板(10)还包括：至少一条第一电源线(115)；
    所述至少一条第一电源线(115)位于所述周边区域(101b)，所述至少一条第一电源线(115)包括第一部分(1151)和第二部分(1152)，所述第一部分(1151)位于所述阻挡结构(103)远离所述多个像素单元(102)的一侧，用于接收第一电源信号，所述第二部分(1152)环绕所述多个像素单元(102)，且分别与所述第一部分(1151)和所述转接结构(105)电连接。
  18. 一种显示面板，其特征在于，所述显示面板(10)包括：
    衬底基板(101)，所述衬底基板(101)具有显示区域(101a)以及围绕所述显示区域(101a)的周边区域(101b)；
    多个像素单元(102)，位于所述显示区域(101a)，所述像素单元(102)包括发光单元(1021)，所述发光单元(1021)包括依次层叠的第一电极层(a1)，发光层(a2)以及第二电极层(a3)；
    阻挡结构(103)，位于所述周边区域(101b)且围绕所述多个像素单元(102)；
    转接结构(104)，位于所述周边区域(101b)，所述转接结构(104)与所述第一电极层(a1)位于同层且具有间隙，且所述转接结构(104)与所述第二电极层(a3)电连接；
    第一绝缘层(105)，位于所述第一电极层(a1)和所述衬底基板(101)之间，且所述第一绝缘层(105)位于所述周边区域(101b)的部分具有过孔；
    电路结构(106)，位于所述周边区域(101b)，所述电路结构(106)包括位于所述第一阻挡坝(1031)和所述显示区域(101a)之间的第一电路结构(106a)，所述第一电路结构(106a)包括第一电路子图案(b11)和第二电路子图案(b22)，所述第一子电路图案(b11)位于第一金属层，所述第二电路子图案(b22)位于第二金属层，所述第一金属层和所述第二金属层位于所述第一绝缘层(105)两侧，所述第一绝缘层(105)的过孔包括第一过孔(c1)，所述第一电路子图案(b11)和所述第二电路子图案(b22)通过所述第一过孔(c1)电连接；
    第二绝缘层(107)，位于所述第二金属层远离所述衬底基板(101)的一侧；
    位于所述第二绝缘层(107)远离所述衬底基板(101)的一侧的第三绝缘层(108)，第三绝缘层(108)包括位于所述显示区域(101a)和所述周边区域(101b)的主体图案(1081)，所述主体图案(1081)包括位于所述周边区域(101b)的第三侧面(1081a)；所述第三侧面(1081a)在所述衬底基板(101)上的正投影位于所述阻挡结构(103)和所述显示区域(101a)之间；
    以及位于所述衬底基板(101)上的保护层(M)，所述保护层(M)包括多个保护图案，所述保护图案在所述衬底基板(101)上的正投影覆盖所述第一过孔在所述衬底基板(101)上的正投影。
  19. 一种显示面板，其特征在于，所述显示面板(10)包括：
    衬底基板(101)，所述衬底基板(101)具有显示区域(101a)以及围绕 所述显示区域(101a)的周边区域(101b)；
    多个像素单元(102)，位于所述显示区域(101a)，所述像素单元(102)包括发光单元(1021)，所述发光单元(1021)包括依次层叠的第一电极层(a1)，发光层(a2)以及第二电极层(a3)；
    阻挡结构(103)，位于所述周边区域(101b)且围绕所述多个像素单元(102)；
    转接结构(104)，位于所述周边区域(101b)，所述转接结构(104)与所述第一电极层(a1)位于同层且具有间隙，且所述转接结构(104)与所述第二电极层(a3)电连接；
    第一绝缘层(105)，位于所述第一电极层(a1)和所述衬底基板(101)之间，且所述第一绝缘层(105)位于所述周边区域(101b)的部分具有过孔；
    电路结构(106)，位于所述周边区域(101b)，所述电路结构(106)包括位于所述第一阻挡坝(1031)和所述显示区域(101a)之间的第一电路结构(106a)，所述第一电路结构(106a)包括第一电路子图案(b11)和第二电路子图案(b22)，所述第一子电路图案(b11)位于第一金属层，所述第二电路子图案(b22)位于第二金属层，所述第一金属层和所述第二金属层位于所述第一绝缘层(105)两侧，所述第一绝缘层(105)的过孔包括第一过孔(c1)，所述第一电路子图案(b11)和所述第二电路子图案(b22)通过所述第一过孔(c1)电连接；
    第二绝缘层(107)，位于所述第二金属层远离所述衬底基板(101)的一侧；
    位于所述第二绝缘层(107)远离所述衬底基板(101)的一侧的第三绝缘层(108)，第三绝缘层(108)包括位于所述显示区域(101a)和所述周边区域(101b)的主体图案(1081)，所述主体图案(1081)包括位于所述周边区域(101b)的第三侧面(1081a)；所述第三侧面(1081a)在所述衬底基板(101)上的正投影位于所述第一阻挡坝(1031)和所述显示区域(101a)之间；
    其中，所述转接结构(104)包括多个开口，所述开口在所述衬底基板(101)上的正投影覆盖所述第一过孔在所述衬底基板(101)上的正投影。
  20. 一种显示装置，其特征在于，所述显示装置包括：供电组件(20)以及如权利要求1至19任一所述的显示面板(10)；
    其中，所述供电组件(20)用于为所述显示面板(10)供电。
PCT/CN2023/078868 2023-02-28 2023-02-28 显示面板及显示装置 Ceased WO2024178648A1 (zh)

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