WO2024176064A1 - 半導体装置、及び記憶装置 - Google Patents

半導体装置、及び記憶装置 Download PDF

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Publication number
WO2024176064A1
WO2024176064A1 PCT/IB2024/051467 IB2024051467W WO2024176064A1 WO 2024176064 A1 WO2024176064 A1 WO 2024176064A1 IB 2024051467 W IB2024051467 W IB 2024051467W WO 2024176064 A1 WO2024176064 A1 WO 2024176064A1
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Prior art keywords
wiring
transistor
conductor
semiconductor
memory
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PCT/IB2024/051467
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
村川努
國武寛司
宮入秀和
倉田求
岡本佑樹
宮田翔希
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020257029422A priority Critical patent/KR20250156120A/ko
Priority to JP2025501907A priority patent/JPWO2024176064A1/ja
Priority to CN202480009965.9A priority patent/CN120642592A/zh
Publication of WO2024176064A1 publication Critical patent/WO2024176064A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Definitions

  • One aspect of the present invention relates to a transistor, a semiconductor device, a memory device, and an electronic device. Alternatively, one aspect of the present invention relates to a method for manufacturing a memory device or a semiconductor device. Alternatively, one aspect of the present invention relates to a semiconductor wafer and a module.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices, are one embodiment of semiconductor devices.
  • display devices such as liquid crystal display devices and light-emitting display devices
  • projection devices such as liquid crystal display devices and light-emitting display devices
  • lighting devices such as electro-optical devices
  • power storage devices such as memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to have semiconductor devices.
  • one aspect of the present invention is not limited to the above technical fields.
  • One aspect of the invention disclosed in this specification relates to an object, a method, or a manufacturing method.
  • Another aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials. Transistors using oxide semiconductors are known to have extremely small current flowing in the non-conducting state (off state).
  • Patent Document 1 discloses a memory device that can retain stored contents for a long period of time by utilizing the characteristic of low leakage current of transistors that use oxide semiconductors.
  • Patent Document 2 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 3 discloses a vertical transistor in which the side surface of the oxide semiconductor is covered by a gate electrode via a gate insulator.
  • JP 2011-151383 A International Publication No. 2021/053473 JP 2013-211537 A
  • the memory cell disclosed in Patent Document 1 has a write transistor and a read transistor, and the read transistor changes the potential of the bit line (read line) by passing a current corresponding to the data potential held in the gate.
  • This memory cell does not require a large-volume capacitive element within the cell, as in DRAM, and it is possible to form a highly integrated storage device (memory).
  • a highly integrated storage device memory
  • planarization process When arranging the transistors of a memory cell three-dimensionally, a planarization process is used to reduce unevenness caused by the components of the transistor.
  • the number of steps required for the planarization process increases in proportion to the number of layers, so it is preferable to reduce the number of steps as much as possible.
  • one object of one embodiment of the present invention is to provide a semiconductor device with a reduced number of steps. Another object is to provide a semiconductor device with high reliability in data reading. Another object is to provide a semiconductor device with small parasitic capacitance. Another object is to provide a semiconductor device that enables high integration. Another object is to provide a semiconductor device with good electrical characteristics. Another object is to provide a semiconductor device with good reliability. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a new semiconductor device. Another object is to provide a new semiconductor device, etc.
  • One aspect of the present invention is a semiconductor device having an arithmetic processing unit and a sense amplifier in a first layer, a memory device in a second layer, the second layer being provided on the first layer, the sense amplifier having a function of reading data from the memory device, the memory device having a plurality of memory cells, the memory cell having a first transistor and a second transistor, the first transistor and the second transistor being electrically connected via a conductor, the first transistor having a channel formation region in a first semiconductor provided along a side surface of a first opening in a first insulator, the second transistor having a channel formation region in a second semiconductor provided along a side surface of a second opening in a second insulator, the second insulator being provided on the first insulator, and the second opening being provided diagonally above the first opening.
  • the conductor can have a region that functions as the gate electrode of the first transistor and a region that functions as the source or drain electrode of the second transistor.
  • the second opening is located in a position that does not overlap with the first opening when viewed from above.
  • Another aspect of the present invention is a semiconductor device having an arithmetic processing unit and a sense amplifier in a first layer, a memory device in a second layer, the second layer being provided on the first layer, the sense amplifier having a function of reading data from the memory device, the memory device having a plurality of memory cells, the memory cell having a first transistor and a second transistor, the first transistor having a first conductor, a first semiconductor, a first insulator, a second conductor, and a third conductor, the first semiconductor having a region formed on a side of a first opening penetrating each of the second insulator and the second conductor provided on the first conductor, the first insulator being a region formed on a side of the first semiconductor
  • the semiconductor device has a region in contact with the first semiconductor and covering the first opening, the third conductor has a region in contact with the first insulator and covering the first opening, the second transistor has a third conductor, a second semiconductor, a third insulator, a fourth conduct
  • the first conductor has a region that functions as one of the source electrode or drain electrode of the first transistor
  • the second conductor has a region that functions as the other of the source electrode or drain electrode of the first transistor
  • the third conductor has a region that functions as the gate electrode of the first transistor and one of the source electrode or drain electrode of the second transistor
  • the fourth conductor has a region that functions as the other of the source electrode or drain electrode of the second transistor
  • the fifth conductor has a region that functions as the gate electrode of the second transistor.
  • the second opening is located in a position that does not overlap with the first opening when viewed from above.
  • the third conductor may be arranged so that it entirely overlaps the second conductor when viewed from above.
  • the third conductor may be elliptical or oval in top view
  • the first conductor, the second conductor, the fourth conductor and the fifth conductor may be strip-shaped in top view
  • the third conductor may be arranged such that the direction of its major axis in top view is not the same as, and is not perpendicular to, any of the longitudinal directions of the first conductor, the second conductor, the fourth conductor and the fifth conductor in top view.
  • Each of the first semiconductor and the second semiconductor is an oxide semiconductor, and it is preferable that the oxide semiconductor contains one or more selected from In, Ga, and Zn.
  • a semiconductor device with a reduced number of steps can be provided.
  • a semiconductor device with high reliability in data reading can be provided.
  • a semiconductor device with small parasitic capacitance can be provided.
  • a semiconductor device that enables high integration can be provided.
  • a semiconductor device with good electrical characteristics can be provided.
  • a semiconductor device with good reliability can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a new semiconductor device can be provided.
  • a new semiconductor device, etc. can be provided.
  • FIG. 1 is a diagram illustrating a memory cell.
  • 2A and 2B are circuit diagrams illustrating a memory cell.
  • FIG. 3 is a timing chart illustrating the operation of the memory cell.
  • Fig. 4A is a cross-sectional view illustrating a memory cell
  • Fig. 4B and Fig. 4C are cross-sectional views illustrating a defect in the memory cell.
  • Fig. 5A is a diagram for explaining a memory cell array
  • Fig. 5B is a layout diagram of the memory cell array.
  • 6A and 6B are side views for explaining the positional relationship of the wiring
  • Fig. 6C to Fig. 6F are top views for explaining the positional relationship of the wiring.
  • FIG. 7A is a cross-sectional view illustrating a memory cell
  • FIG 7B is a diagram illustrating a memory cell array
  • Fig. 8A is a diagram for explaining a memory cell array
  • Fig. 8B is a layout diagram of the memory cell array
  • 9A and 9B are side views for explaining the positional relationship of the wiring
  • Fig. 9C to Fig. 9F are top views for explaining the positional relationship of the wiring.
  • FIG. 10 is a diagram for explaining a three-dimensional arrangement of a memory cell array.
  • 11A and 11B are diagrams illustrating a transistor.
  • 12A and 12B are diagrams illustrating an example of the configuration of a storage device.
  • 13A to 13G are diagrams for explaining examples of the circuit configuration of a memory cell.
  • FIG. 14 is a block diagram illustrating the CPU.
  • 15A and 15B are diagrams illustrating a semiconductor device.
  • 16A and 16B are diagrams illustrating a semiconductor device.
  • 17A and 17B are diagrams showing various storage devices by hierarchical level.
  • FIG. 18 is a block diagram illustrating an example of the configuration of a computer.
  • 19A and 19B are schematic diagrams illustrating an example of the configuration of a computer.
  • 20A to 20D are schematic diagrams for explaining examples of the configuration of a computer.
  • FIG. 21 is a circuit diagram illustrating a configuration example of a semiconductor device.
  • FIG. 22 is a timing chart illustrating an example of the operation of the semiconductor device.
  • 23A to 23D are schematic diagrams illustrating an example of the operation of the semiconductor device.
  • FIG. 24 is a timing chart illustrating an example of the operation of the semiconductor device.
  • 25A to 25G are schematic diagrams illustrating an example of the operation of the semiconductor device.
  • 26A and 26B are diagrams illustrating an example of an electronic component.
  • 27A and 27B are diagrams for explaining an example of an electronic device, and
  • Fig. 27C to Fig. 27E are diagrams for explaining an example of a mainframe computer.
  • FIG. 28 is a diagram illustrating an example of space equipment.
  • FIG. 29 is a diagram illustrating an example of a storage system that can be applied to a data center.
  • an oxynitride is a material whose composition contains more oxygen than nitrogen.
  • examples of oxynitrides include silicon oxynitride, aluminum oxynitride, and hafnium oxynitride.
  • a nitride oxide is a material whose composition contains more nitrogen than oxygen. Examples of nitride oxides include silicon nitride oxide, aluminum nitride oxide, and hafnium nitride oxide.
  • the term “insulator” can be replaced with “insulating film” or “insulating layer.”
  • the term “conductor” can be replaced with “conductive film” or “conductive layer.”
  • the term “semiconductor” can be replaced with “semiconductor film” or “semiconductor layer.”
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes the case of -5 degrees or more and 5 degrees or less.
  • Approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • orthogonal refers to a state in which two straight lines cross or connect at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes the case of 85 degrees or more and 95 degrees or less. "Approximately perpendicular” or “approximately perpendicular” refers to a state in which two straight lines cross or connect at an angle of 60 degrees or more and 120 degrees or less.
  • arrows indicating the X direction, Y direction, and Z direction may be attached.
  • the "X direction” is the direction along the X axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated.
  • the X direction, Y direction, and Z direction are directions that intersect with each other. More specifically, the X direction, Y direction, and Z direction are directions that are perpendicular to each other.
  • one of the X direction, Y direction, and Z direction may be called the "first direction” or "first direction”.
  • the other one may be called the “second direction” or “second direction”.
  • the remaining one may be called the "third direction” or "third direction”.
  • Embodiment 1 In this embodiment, a semiconductor device such as a memory device according to one embodiment of the present invention will be described.
  • a memory cell included in the memory device according to one embodiment of the present invention includes two transistors.
  • vertical transistors are used that have a channel formation region along the side of an opening in an insulator.
  • Vertical transistors have the advantage that it is easy to increase the on-current because they have a short channel length and a long channel width.
  • Vertical transistors also have the advantage that they can reduce the area they occupy when viewed from above. Therefore, by using vertical transistors in memory cells, it is possible to form a memory device that is capable of high-speed operation and has a high degree of integration.
  • the two transistors can be of the same structure, and stacking them one on top of the other maximizes cell density.
  • unevenness caused by the components of the transistors becomes an unstable factor in the manufacturing process.
  • highly difficult via filling processes, as well as planarization processes such as forming and polishing thick insulating layers, are performed. These processes are used frequently depending on the number of layers stacked, and are one factor in increasing the overall number of steps. Therefore, in one aspect of the present invention, some of the unevenness caused by the components of the lower transistor is tolerated, and the upper transistor is positioned where the unevenness does not cause defects, thereby reducing the number of steps.
  • the capacitance of the parasitic capacitance can be reduced by appropriately arranging each wiring, thereby improving the reliability of data reading.
  • the capacitance of the parasitic capacitance generated between the wirings can be reduced, allowing the memory device to operate faster and consume less power.
  • Figure 1 is a perspective view showing a part of a memory device of one embodiment of the present invention, and illustrates a memory cell 150 (transistor 100, transistor 200) and each wiring.
  • the wiring may have a region of a component of a transistor, such as an electrode.
  • the wiring and the electrode may also be called a conductor.
  • Transistor 100 and transistor 200 are vertical transistors, with transistor 200 provided diagonally above transistor 100.
  • Memory cell 150 is electrically connected to wiring 110, wiring 140, wiring 240, and wiring 210. Note that insulators such as interlayer films are not shown in FIG. 1 for clarity.
  • Transistor 100 has wiring 110, wiring 140, and conductor 120 as its components.
  • Transistor 200 has conductor 120, wiring 240, and wiring 210 as its components.
  • the wiring 110 has a region that functions as one of the source electrode and the drain electrode of the transistor 100.
  • the wiring 140 has a region that functions as the other of the source electrode and the drain electrode of the transistor 100.
  • the conductor 120 has a region that functions as the gate electrode of the transistor 100 and a region that functions as one of the source electrode or drain electrode of the transistor 200. In other words, the conductor 120 has a region that shares the gate electrode of the transistor 100 and one of the source electrode or drain electrode of the transistor 200.
  • the wiring 240 has a region that functions as the other of the source electrode or drain electrode of the transistor 200.
  • the wiring 210 has a region that functions as the gate electrode of the transistor 200. Note that a conductor that functions as the gate electrode may be provided, and the wiring 210 may be provided so as to be electrically connected to the conductor. Details of the structure and connection of each transistor will be described later.
  • Figure 2A is a diagram illustrating an example of a circuit diagram of a memory cell 150.
  • the transistor 100 has a function of reading data.
  • the transistor 200 has a function of writing data.
  • One of the source and drain of transistor 200 is connected to the gate of transistor 100. In FIG. 1, this connection is borne by conductor 120. Conductor 120 can also be said to be a component of node SN that holds the data potential in memory cell 150 shown in FIG. 2A.
  • the wiring 210 connected to the gate of the transistor 200 is a wiring that supplies a write word signal to the memory cell 150 and is also called a write word line (WWL).
  • the write word signal is a signal that controls the timing of writing data to the memory cell 150.
  • the wiring 240 connected to the other of the source and the drain of the transistor 200 is a wiring that applies a potential corresponding to a data signal (data) to the memory cell 150 and is also referred to as a write bit line (WBL).
  • the data signal is a signal expressed as a binary value of a high level (also referred to as "1" or VH ) or a low level (also referred to as "0" or VL ) that is written to the memory cell 150.
  • the wiring 110 connected to one of the source and drain of the transistor 100 is a wiring that supplies a read word signal to the memory cell 150, and is also called a read word line (RWL).
  • the read word signal is a signal that controls the timing of reading data from the memory cell 150.
  • the wiring 140 connected to the other of the source or drain of the transistor 100 is a wiring for reading out a potential corresponding to a data signal (data) stored in the memory cell 150, and is also called a read bit line (RBL).
  • a current flows through the transistor 100 according to the data ("1" or "0") written to the memory cell 150, changing the potential of the precharged wiring 140.
  • the data can be read by inputting the potential to a sense amplifier or the like.
  • parasitic capacitance Cp1 occurs between node SN and wiring 210.
  • Parasitic capacitance Cp2 occurs between node SN and wiring 240.
  • Parasitic capacitance Cp3 occurs between node SN and wiring 110.
  • Parasitic capacitance Cp4 occurs between node SN and wiring 140.
  • the components of each parasitic capacitance include the components of transistor 100 or transistor 200.
  • node SN Since node SN is floating, when the potential of each wiring fluctuates, one or more of the parasitic capacitances Cp1 to Cp4 are affected, and the potential of node SN also fluctuates due to capacitive coupling.
  • the range of fluctuation in the potential of node SN varies depending on the amount of fluctuation in the potential of each wiring and the electrostatic capacitance of each parasitic capacitance, but if the fluctuation in the potential of node SN is too large, transistor 100 may not operate normally and data may not be read accurately.
  • FIG. 3 is a timing chart for explaining an example of the operation of memory cell 150 shown in FIG. 2A.
  • FIG. 3 shows potentials applied to the wiring 210 (WWL), the wiring 240 (WBL), and the wiring 110 (RWL), a potential read out to the wiring 140 (RBL), and a potential of the node SN. Note that in FIG. 3, the standby state of the wiring 240 (WBL) is set to a low level (V L ).
  • Period T1 is a standby period.
  • Period T2 is a write period.
  • Period T3 is a standby period.
  • Periods T4 and T5 are read periods.
  • Period T6 is a standby period. Note that FIG. 3 illustrates data “1” or “0” written to memory cell 150 (node SN) via wiring 240 (WBL). Data written to memory cell 150 is data “1" when at high level and data "0" when at low level.
  • Figure 3 shows data "1” or “0” read from memory cell 150 via wiring 140 (RBL).
  • Wiring 140 (RBL) is precharged to a high-level potential (e.g., a high power supply potential such as VDD) during the read period, and data is read to an external read circuit connected to wiring 140 (RBL) according to changes in the precharged potential.
  • a high-level potential e.g., a high power supply potential such as VDD
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level ( VL )
  • the wiring 110 (RWL) is at a high level
  • the wiring 140 (RBL) is at a high level.
  • the transistor 200 is in a non-conducting state.
  • the source and drain terminals of the transistor 100 have the same potential, so that no current flows.
  • the potential of the gate (node SN) of the transistor 100 is the potential VH or VL written in the previous write period.
  • the wiring 210 (WWL) is at a high level
  • the wiring 240 (WBL) is at a signal ( VH or VL ) corresponding to the data
  • the wiring 110 (RWL) is at a high level
  • the wiring 140 (RBL) is at a high level.
  • the transistor 200 is turned on, and the potential of the gate (node SN) of the transistor 100 becomes a potential corresponding to the data. Since the source and drain terminals of the transistor 100 are at the same potential, no current flows regardless of the gate potential.
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level (V L )
  • the wiring 110 (RWL) is at a high level
  • the wiring 140 (RBL) is at a high level.
  • both the transistors 100 and 200 are in a non-conducting state.
  • the potential written to the gate (node SN) of the transistor 100 is held. Since the source and drain terminals of the transistor 100 have the same potential, no current flows regardless of the gate potential.
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level (V L )
  • the wiring 110 (RWL) is at a high level.
  • the wiring 140 (RBL) is precharged to a high level (also referred to as a precharge potential V PRE ).
  • V PRE is, for example, VDD, which is equal to the high level of the wiring 140 (RBL). Since the source and drain terminals of the transistor 100 are at the same potential, no current flows regardless of the potential of the gate (node SN). In other words, the potential of the wiring 140 does not change.
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level (V L )
  • the wiring 110 (RWL) is at a low level.
  • the transistor 200 is in a non-conducting state.
  • the wiring 140 (RBL) is in an electrically floating state. That is, the potential of the wiring 210 (WWL) is changed depending on the current flowing through the transistor 100 in the memory cell 150.
  • period T5 a potential difference occurs between the source and drain terminals of transistor 100, causing a current to flow according to the potential of the gate (node SN) of transistor 100.
  • the current flowing through transistor 100 is large, causing the potential of wiring 140 (RBL) to drop to a low level.
  • This change in the potential of wiring 140 (RBL) can be used to activate a sense amplifier connected to wiring 140 (RBL), allowing the data of the selected memory cell 150 to be read out to the outside.
  • the wiring 210 (WWL) is at a low level
  • the wiring 240 (WBL) is at a low level (V L )
  • the wiring 110 (RWL) is at a high level
  • the wiring 140 (RBL) is at a high level.
  • the transistor 200 is in a non-conducting state. Since the source and drain terminals of the transistor 100 have the same potential, no current flows regardless of the gate potential.
  • Fig. 4A is a diagram illustrating a cross section taken along line A1-A2 shown in Fig. 1 .
  • Memory cell 150 has an insulator 160 on a substrate (not shown), a transistor 100 provided on insulator 160, and a transistor 200 provided diagonally above transistor 100. Note that an insulator 180, insulator 280, insulator 285, or the like that functions as an interlayer film can be provided between the transistors and between each wiring.
  • the transistor 100 has an oxide semiconductor 170, an insulator 130, and a conductor 120.
  • the oxide semiconductor 170 functions as a semiconductor layer
  • the insulator 130 functions as a gate insulator
  • the conductor 120 functions as a gate electrode.
  • the wiring 110 has a region that functions as one of the source electrode and the drain electrode of the transistor 100.
  • the wiring 140 has a region that functions as the other of the source electrode and the drain electrode of the transistor 100.
  • An insulator 180 and an interconnect 140 are provided on the insulator 160 and the interconnect 110.
  • An opening 190 is provided through the insulator 180 and the interconnect 140, reaching the interconnect 110.
  • the opening 190 has a columnar shape with a roughly circular upper surface. This configuration allows for miniaturization or high integration of memory cells. Note that the side surface of the opening 190 is preferably perpendicular to the upper surface of the interconnect 110.
  • the oxide semiconductor 170 is disposed in the opening 190.
  • the oxide semiconductor 170 has a region in contact with the top surface of the wiring 110, a region in contact with the side surface of the wiring 140, and a region in contact with the side surface of the insulator 180.
  • the insulator 130 is arranged so that at least a portion of it covers the opening 190.
  • the conductor 120 is arranged so that at least a portion of it is located in the opening 190. It is preferable that the conductor 120 is provided so as to fill the opening 190.
  • the conductor 120 preferably has a small area that overlaps with each wiring in order to reduce parasitic capacitance. That is, the area of the conductor 120 in top view is preferably as small as possible.
  • the conductor 120 since the conductor 120 also functions as a wiring that electrically connects the transistor 100 and the transistor 200, it is preferable that the conductor 120 has a rectangular shape in top view. It is more preferable that the conductor 120 has an elliptical or oval shape in top view (see FIG. 1), which can have a smaller area than a rectangle.
  • the transistor 200 has an oxide semiconductor 270, an insulator 230, and a wiring 210.
  • the oxide semiconductor 270 functions as a semiconductor layer
  • the insulator 230 functions as a gate insulator
  • the wiring 210 functions as a gate electrode.
  • the conductor 120 has a region that functions as one of the source electrode and the drain electrode of the transistor 200.
  • the wiring 240 has a region that functions as the other of the source electrode and the drain electrode of the transistor 200.
  • An insulator 280 and a wiring 240 are provided on the insulator 130 and the conductor 120.
  • An opening 290 is provided through the insulator 280 and the wiring 240, reaching the conductor 120.
  • the opening 290 has a columnar shape with a roughly circular upper surface. This configuration allows for miniaturization or high integration of memory cells. Note that the side surface of the opening 290 is preferably perpendicular to the upper surface of the conductor 120.
  • the oxide semiconductor 270 is disposed in the opening 290. Note that the oxide semiconductor 270 has a region in contact with the top surface of the conductor 120 in the opening 290, a region in contact with the side surface of the wiring 240, and a region in contact with the side surface of the insulator 280.
  • the insulator 230 is arranged so that at least a portion of it covers the opening 290.
  • the wiring 210 is arranged so that at least a portion of it is located in the opening 290.
  • a conductor may be provided so as to fill the opening 290, and the wiring 210 may be formed on the conductor.
  • the diameter of the opening 190 and the diameter of the opening 290 are approximately the same, and that the transistors 100 and 200 have approximately the same configuration.
  • the memory cells 150 can be arranged at a high density, and the memory capacity of the memory device can be increased. In other words, the memory device can be highly integrated.
  • one of the source electrode or drain electrode of transistor 200 and the gate electrode of transistor 100 are shared, that is, transistor 200 and transistor 100 are directly connected without an intervening wiring. Therefore, the electrical resistance between the two can be minimized, and data can be written quickly.
  • transistor 200 is provided diagonally above transistor 100.
  • opening 290 is provided diagonally above opening 190.
  • the cell area can be minimized by arranging the two transistors one above the other.
  • labor is required to eliminate unevenness caused by the components of the transistor.
  • FIGS 4B and 4C are diagrams showing a process of providing an opening 290 directly above an opening 190.
  • a depression may be formed on the top of the conductor 120 due to the shape of the opening 190, and etching residue 280r of the insulator 280 may be generated in the depression when the opening 290 is formed. This etching residue 280r induces contact defects between the oxide semiconductor 270 provided in a later process and the conductor 120.
  • the etching may proceed too deep, leading to poor contact and disconnection. Therefore, in a configuration in which the opening 290 is provided directly above the opening 190, it is preferable to eliminate unevenness by using a difficult filling process or planarization process that does not create a depression on the top of the conductor 120.
  • the conductor 120 in order to eliminate the effects of depressions occurring in the conductor 120, as shown in FIG. 4A, the conductor 120 is extended in one direction, and an opening 290 is formed in the area where the conductor 120 is flat.
  • an opening 290 is formed in the area where the conductor 120 is flat.
  • parasitic capacitance can be reduced by reducing the overlap area between the conductor 120 and wiring located in close proximity.
  • the wiring closest to the conductor 120 is the wiring 140, followed by the wiring 240.
  • the conductor 120 is preferably elliptical or oval in top view.
  • the wirings 140 and 240 are strip-shaped in top view. Therefore, as shown in the layout diagrams shown in Figures 1, 4A, and Figure 5B used in the description below, the conductor 120 may be arranged so that the direction of the long axis intersects perpendicularly with the longitudinal direction of the wirings 140 and 240. With this configuration, the overlapping area between the conductor 120 and each of the wirings 140 and 240 can be reduced, and the parasitic capacitances Cp2 and Cp4 (see Figure 2B) can be reduced.
  • wiring 110 and wiring 210 are next closest wirings to the conductor 120 after wiring 140 and wiring 240. These wirings are also strip-shaped when viewed from above, and by arranging the long axis of the conductor 120 so as to intersect perpendicularly with the longitudinal direction of wiring 110 and wiring 210, the parasitic capacitances Cp1 and Cp3 (see FIG. 2B) formed between the conductor 120 and the wiring 110 can be reduced.
  • FIG. 5A is a perspective view illustrating a memory cell array in which a plurality of the above-mentioned memory cells 150 are arranged two-dimensionally
  • FIG. 5B is a layout diagram of the memory cell array as viewed from above.
  • the widths of the wiring 110, wiring 210, wiring 140, and wiring 240, and the width of the conductor 120 in the minor axis direction are set to the minimum processing dimension (F)
  • the area of each memory cell 150 can be set to 6F2 .
  • the wiring provided at the bottom of the transistor 100 is the wiring 110
  • the wiring located close to the conductor 120 is the wiring 140
  • the wiring provided at the bottom of the transistor 100 may be the wiring 140
  • the wiring located close to the conductor 120 may be the wiring 110.
  • each wiring in the height direction may be the same as or perpendicular to the direction of the long axis of the conductor 120.
  • wirings 110 and 140, and wirings 210 and 240 are arranged to be perpendicular to each other.
  • the direction of the long axis of the conductor 120 and the direction of the longitudinal direction of the wiring 110 and the wiring 210 can be arranged so as to be the same, and the longitudinal directions of the wiring 140 and the wiring 240 can be arranged orthogonal to each other.
  • the direction of the long axis of the conductor 120 and the direction of the longitudinal direction of the wiring 140 and the wiring 210 can be arranged so as to be the same, and the longitudinal directions of the wiring 110 and the wiring 240 can be arranged orthogonal to each other.
  • FIG. 6C the direction of the long axis of the conductor 120 and the direction of the longitudinal direction of the wiring 110 and the wiring 210 can be arranged so as to be the same, and the longitudinal directions of the wiring 140 and the wiring 240 can be arranged orthogonal to each other.
  • the direction of the long axis of the conductor 120 and the direction of the longitudinal direction of the wiring 110 and the wiring 240 can be arranged so as to be the same, and the longitudinal directions of the wiring 140 and the wiring 210 can be arranged orthogonal to each other.
  • the long axis of the conductor 120 can be oriented in the same direction as the longitudinal direction of the wiring 140 and wiring 240, and the longitudinal directions of the wiring 110 and wiring 210 can be arranged perpendicular to each other.
  • FIG. 4A shows an example in which the opening 290 is formed on a region where the conductor 120 is flat, avoiding not only the unevenness caused by the opening 190, but also the unevenness caused by the wiring 140 and the oxide semiconductor 170.
  • the opening 190 and the opening 290 can be brought closer together, and the cell density can be increased.
  • the wiring 140 and the oxide semiconductor 170 may be arranged so that the direction of the long axis of the conductor 120 and the direction of the longitudinal direction of the wiring 140 are the same.
  • the oxide semiconductor 170 is arranged so as to overlap with the wiring 140.
  • the parasitic capacitance Cp4 (see FIG. 2) formed between the conductor 120 and the wiring 140 is permissible (does not impede the reliability of reading).
  • Figure 7A is a cross-sectional view of the conductor 120 when it is arranged so that the long axis direction of the conductor 120 and the longitudinal direction of the wiring 140 are the same.
  • the conductor 120 By arranging the conductor 120 so that the long axis direction of the conductor 120 and the longitudinal direction of the wiring 140 are the same, that is, by configuring the conductor 120 to entirely overlap the wiring 140, the unevenness caused by the wiring 140 as shown in Figure 4A is not formed.
  • the opening 190 and the opening 290 can be brought closer to each other to the extent that the depression in the conductor 120 caused by the opening 190 does not affect it.
  • the depression in the conductor 120 and the opening 290 overlap, the depth of the opening 290 in the transistor 200 will not be uniform, resulting in the formation of a portion in which the channel length changes. This may result in deterioration of the electrical characteristics and reliability of the transistor 200. Therefore, it is preferable that the depression in the conductor 120 and the opening 290 are separated from each other. In addition, since the depression in the conductor 120 is caused by the opening 190, it can also be said that it is preferable that the opening 190 and the opening 290 are separated from each other so as not to overlap each other when viewed from above.
  • FIG. 7B is a perspective view illustrating a memory cell array in which a plurality of memory cells 150 shown in FIG. 7A are arranged two-dimensionally.
  • FIG. 7A corresponds to a cross section taken along line B1-B2 in FIG. 7B.
  • the distance between the opening 190 and the opening 290 can be made closer in top view than in the configurations shown in FIGS. 5A and 5B, so that the cell area can be made smaller than 6F2 .
  • the area of the conductor 120 can be made smaller than in the configurations shown in FIGS. 5A and 5B, so that the electrostatic capacitance of the parasitic capacitance generated between the conductor 120 and each wiring can be made smaller.
  • the direction of the long axis of the conductor 120 may be configured not to be the same as, and not to be perpendicular to, the longitudinal direction of any of the wiring 110, wiring 210, wiring 140, and wiring 240.
  • FIG. 8A is a perspective view illustrating a memory cell array when the direction of the conductor 120 is inclined with respect to the longitudinal direction of the wiring 110
  • FIG. 8B is a layout diagram seen from above.
  • the widths of the wiring 110, wiring 210, wiring 140, and wiring 240, and the width of the conductor 120 in the minor axis direction are set as the minimum processing dimension (F)
  • the area of each memory cell 150 can be set to 6F2 .
  • the long axis of the conductor 120 and the longitudinal direction of the wiring 110 and wiring 210 are aligned in the same direction, so the parasitic capacitances Cp1 and Cp3 (see Figure 2B) are relatively large.
  • the wiring 110 and wiring 210 are arranged to overlap, the electrostatic capacitance of the parasitic capacitance generated between these wirings is also large.
  • the direction of the long axis of the conductor 120 is different from the direction of the longitudinal direction of each of the wirings, so the overlapping area between the conductor 120 and the wirings 110 and 210 is small, and the capacitance of the parasitic capacitances Cp1 and Cp3 can be made smaller than in the configuration shown in Figures 5A and 5B.
  • the overlapping area between the wirings 110 and 210 is also small, so the capacitance of the parasitic capacitance generated between these wirings can be made smaller, improving the operating speed and reducing power consumption.
  • FIG. 8A and 8B show an example of a configuration in which the orientation of the conductor 120 is tilted at an angle of 45° with respect to the longitudinal direction of the wiring 110, but this angle is not limited.
  • the overlapping area between the conductor 120 and each wiring and the overlapping area between each wiring will differ depending on this angle, and the capacitance of each parasitic capacitance and the capacitance between the wirings shown in FIG. 2B will change. Therefore, the angle can be determined appropriately taking into account the influence of each parasitic capacitance and the parasitic capacitance between the wirings shown in FIG. 2B.
  • the wiring provided in the lower part is the wiring 110 and the wiring located close to the conductor 120 is the wiring 140, but this is not limited thereto.
  • the wiring provided in the lower part may be the wiring 140 and the wiring located close to the conductor 120 may be the wiring 110.
  • each wire is not limited as long as the positional relationship of each wire in the height direction is maintained as shown in FIG. 9A or FIG. 9B.
  • the longitudinal direction of each wire can be determined by taking into consideration the influence of each parasitic capacitance and the parasitic capacitance between wires shown in FIG. 2.
  • the wiring 110 and wiring 210 arranged in parallel can be arranged so that they intersect with the wiring 140 and wiring 240 arranged in parallel.
  • the wiring 140 and wiring 210 arranged in parallel can be arranged so that they intersect with the wiring 110 and wiring 240 arranged in parallel.
  • the wiring 110 and wiring 240 arranged in parallel can be arranged so that they intersect with the wiring 140 and wiring 210 arranged in parallel.
  • the wiring 140 and wiring 240 arranged in parallel can be arranged so that they intersect with the wiring 110 and wiring 210 arranged in parallel.
  • a memory cell array in which memory cells 150 are arranged two-dimensionally can be arranged three-dimensionally to increase the storage capacity.
  • the memory cell array can be stacked in n layers (n is an integer of 2 or more) as necessary, and can have, for example, 100 layers or more. Since the wiring is arranged to overlap in the height direction, it is easy to electrically connect them through vias, and signal potential can be supplied collectively.
  • a read circuit can be shared by electrically connecting multiple readout lines (such as wiring 140) through vias.
  • transistors 100, 200 Next, details of the transistors 100 and 200 will be described. As described above, the transistors 100 and 200 differ from each other in terms of the wiring connection configuration, but the parts related to the operation can be regarded as basically having the same structure, and therefore the transistor 200 will be described here.
  • the transistor 200 can have a configuration including a conductor 120, a wiring 240 on an insulator 280, an oxide semiconductor 270 provided in contact with the upper surface of the conductor 120 exposed in the opening 290, the side surface of the insulator 280 in the opening 290, the side surface of the wiring 240 in the opening 290, and at least a portion of the upper surface of the wiring 240, an insulator 230 provided in contact with the upper surface of the oxide semiconductor 270, and a wiring 210 provided in contact with the upper surface of the insulator 230.
  • the bottom of the opening 290 is also the top surface of the conductor 120
  • the side of the opening 290 is also the side of the insulator 280 and the side of the wiring 240.
  • the opening 290 has a columnar shape with a roughly circular upper surface. This configuration allows for miniaturization or high integration of the memory device. It is preferable that the side of the opening 290 is perpendicular to the upper surface of the wiring 110.
  • the top surface shape of the opening 290 in which the transistor 200 is formed is the same as the top surface shape of the opening 190 in which the transistor 100 is formed.
  • the portions of the oxide semiconductor 270, the insulator 230, and the wiring 210 that are to be placed in the opening 290 are provided to reflect the shape of the opening 290.
  • the oxide semiconductor 270 is provided to cover the bottom and side surfaces of the opening 290
  • the insulator 230 is provided to cover the oxide semiconductor 270
  • the wiring 210 is provided to fill the recess in the insulator 230 that reflects the shape of the opening 290.
  • the present embodiment has been described with respect to an example in which the opening 290 is roughly circular when viewed from above, the present invention is not limited to this.
  • the opening 290 may be elliptical, polygonal such as a rectangle, or polygonal such as a rectangle with rounded corners when viewed from above.
  • the maximum width of the opening 290 may be calculated appropriately according to the shape of the opening 290 when viewed from above.
  • the maximum width of the wiring 210 may be calculated appropriately according to the shape of the wiring 210 when viewed from above.
  • the maximum width of opening 290 may be the length of the diagonal of the rectangle.
  • the maximum width of opening 290 may be the diameter of the smallest circle that contains the shape of opening 290 in top view (also called the minimum containing circle). The above description of the shape of opening 290 can also be applied to opening 190.
  • FIG. 11A shows an enlarged view of the oxide semiconductor 270 and its vicinity in FIG. 4A.
  • FIG. 11B shows a cross-sectional view in the XY plane including the wiring 240.
  • the oxide semiconductor 270 has a region 270i and regions 270na and 270nb arranged to sandwich the region 270i.
  • Region 270na is a region of oxide semiconductor 270 that is in contact with conductor 120. At least a portion of region 270na functions as one of the source region and drain region of transistor 200.
  • Region 270nb is a region of oxide semiconductor 270 that is in contact with wiring 240. At least a portion of region 270nb functions as the other of the source region and drain region of transistor 200.
  • wiring 240 is in contact with the entire outer periphery of oxide semiconductor 270.
  • the other of the source region and drain region of transistor 200 can be formed on the entire outer periphery of a portion of oxide semiconductor 270 that is formed in the same layer as wiring 240.
  • Region 270i is a region in the oxide semiconductor 270 that is sandwiched between regions 270na and 270nb. At least a part of region 270i functions as a channel formation region of the transistor 200. That is, the channel formation region of the transistor 200 is formed in a part of the oxide semiconductor 270 that is located in a region between the conductor 120 and the wiring 240. It can also be said that the channel formation region of the transistor 200 is located in a region of the oxide semiconductor 270 that is in contact with the insulator 280 or in a region in the vicinity of the insulator 280.
  • the channel length of the transistor 200 is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200 is determined by the thickness of the insulator 280 on the conductor 120.
  • the channel length L of the transistor 200 is indicated by a dashed double-headed arrow. In a cross-sectional view, the channel length L is the distance between the end of the region where the oxide semiconductor 270 and the conductor 120 contact each other and the end of the region where the oxide semiconductor 270 and the wiring 240 contact each other. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in a cross-sectional view.
  • the channel length is set by the exposure limit of photolithography, but in the present invention, the channel length can be set by the film thickness of the insulator 280. Therefore, the channel length of the transistor 200 can be made into a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 200, and improves the frequency characteristics. Therefore, a memory device with high operating speed can be provided.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290. This allows the area occupied by the transistor 200 to be reduced compared to conventional transistors in which the channel formation region, the source region, and the drain region are provided separately on the XY plane. This allows the memory device to be highly integrated, thereby increasing the memory capacity per unit area.
  • a transistor having a channel formation region along the side of the insulator 280 in the opening 290 is also called a vertical transistor.
  • the channel width of the transistor 200 is determined by the outer periphery length of the oxide semiconductor 270. That is, it can be said that the channel width of the transistor 200 is determined by the maximum width of the opening 290 (maximum diameter when the opening 290 is circular in the top view).
  • the maximum width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line.
  • the channel width W of the transistor 200 is indicated by a double-dot chain line of a one-dot chain line.
  • the maximum width D of the opening 290 is set by the exposure limit of photolithography.
  • the maximum width D of the opening 290 is set by the film thickness of each of the oxide semiconductor 270, the insulator 230, and the wiring 210 provided in the opening 290.
  • the maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in top view, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x ⁇ ".
  • the channel length L of the transistor 200 is preferably at least smaller than the channel width W of the transistor 200.
  • the channel length L of the transistor 200 of one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 200.
  • the oxide semiconductor 270, the insulator 230, and the wiring 210 are arranged concentrically. This makes the distance between the wiring 210 and the oxide semiconductor 270 roughly uniform, so that a gate electric field can be applied roughly uniformly to the oxide semiconductor 270.
  • the channel formation region of a transistor using an oxide semiconductor for the semiconductor layer has fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, and metal elements than the source and drain regions.
  • impurities such as hydrogen, nitrogen, and metal elements
  • VOH defects in which hydrogen enters the oxygen vacancies and generate electrons that serve as carriers
  • VOH is also reduced in the channel formation region.
  • the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, it can be said that the channel formation region of the transistor is i-type (intrinsic) or substantially i-type.
  • the source and drain regions of a transistor that uses an oxide semiconductor for its semiconductor layer have more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, and thus have an increased carrier concentration and low resistance.
  • the source and drain regions of the transistor are n-type regions that have a higher carrier concentration and lower resistance than the channel formation region.
  • the opening 290 is provided so that the side of the opening 290 is perpendicular to the top surface of the conductor 120, but the present invention is not limited to this.
  • the side of the opening 290 may be tapered.
  • the band gap of the metal oxide used as the oxide semiconductor 270 is preferably 2 eV or more, more preferably 2.5 eV or more.
  • the frequency of the refresh operation can be about once per 10 sec, which is 10 times or more or 100 times or more. Note that in the memory device of one embodiment of the present invention, the frequency of the refresh operation can be set to once per 1 sec to 100 sec, preferably once per 5 sec to 50 sec.
  • oxide semiconductor 270 can be a single layer or a stack of metal oxides described in the [Metal Oxides] section below.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic ratio. It is also preferable to use gallium as the element M.
  • the above atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of the sputtering target used to form the metal oxide film.
  • energy dispersive X-ray spectrometry EDX
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the oxide semiconductor 270 preferably has crystallinity.
  • oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, single crystal oxide semiconductor, and the like. It is preferable to use CAAC-OS or nc-OS as the oxide semiconductor 270, and it is particularly preferable to use CAAC-OS.
  • the CAAC-OS preferably has multiple layered crystal regions with the c-axis oriented in the normal direction to the surface on which it is formed.
  • the oxide semiconductor 270 preferably has layered crystals that are approximately parallel to the side surface of the opening 290, particularly to the side surface of the insulator 280. With this structure, the layered crystals of the oxide semiconductor 270 are formed approximately parallel to the channel length direction of the transistor 200, thereby increasing the on-state current of the transistor.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies).
  • a temperature e.g. 400° C. or higher and 600° C. or lower
  • the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.
  • the oxide semiconductor 270 by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 270, it is possible to suppress the extraction of oxygen from the oxide semiconductor 270 by the source electrode or the drain electrode. As a result, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 270, and the transistor 200 is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the crystallinity of the oxide semiconductor 270 can be analyzed, for example, by an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, the analysis may be performed by combining a plurality of these methods.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor 270 is shown as a single layer in FIG. 4A and other figures, the present invention is not limited to this.
  • the oxide semiconductor 270 may have a laminated structure of multiple oxide layers with different chemical compositions.
  • the oxide semiconductor 270 may have a structure in which multiple types selected from the above metal oxides are appropriately laminated.
  • the insulators described in the [Insulator] section below can be used in a single layer or a multilayer.
  • silicon oxide or silicon oxynitride can be used as the insulator 230. Silicon oxide and silicon oxynitride are preferred because they are stable against heat.
  • the insulator 230 may be a material with a high relative dielectric constant, so-called high-k material, as described in the [Insulator] section below.
  • high-k material such as hafnium oxide or aluminum oxide may be used.
  • the film thickness of the insulator 230 is preferably 0.5 nm or more and 15 nm or less, more preferably 0.5 nm or more and 12 nm or less, and even more preferably 0.5 nm or more and 10 nm or less. It is sufficient that the insulator 230 has a region with the above film thickness in at least a portion.
  • the concentration of impurities such as water and hydrogen in the insulator 230 is reduced. This can prevent impurities such as water and hydrogen from entering the channel formation region of the oxide semiconductor 270.
  • a portion of the insulator 230 is located outside the opening 290, i.e., above the wiring 240 and the insulator 280. At this time, it is preferable that the insulator 230 covers the side end of the oxide semiconductor 270. This can prevent the wiring 210 and the oxide semiconductor 270 from shorting out. It is also preferable that the insulator 230 covers the side end of the wiring 240. This can prevent the wiring 210 and the wiring 240 from shorting out.
  • the insulator 230 is shown as a single layer, but the present invention is not limited to this.
  • the insulator 230 may have a laminated structure.
  • the wiring 210 can be made of a single layer or a multilayer of the conductors described in the section below titled "Conductor.”
  • the wiring 210 can be made of a conductive material with high conductivity, such as tungsten.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the wiring 210.
  • conductive materials include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials that contain oxygen (e.g., ruthenium oxide). This can suppress a decrease in the conductivity of the wiring 210.
  • FIG. 4A shows the wiring 210 as a single layer, the present invention is not limited to this.
  • the wiring 210 may have a multilayer structure.
  • the wiring 240 can be made of a conductor, as described below in the section on conductors, in a single layer or multilayer.
  • the wiring 240 can be made of a highly conductive material, such as tungsten.
  • the wiring 240 is preferably made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen.
  • a conductive material that is difficult to oxidize For example, titanium nitride or tantalum nitride can be used. With this structure, excessive oxidation of the wiring 240 by the oxide semiconductor 270 can be suppressed.
  • a structure in which tungsten is laminated on titanium nitride may be used.
  • the conductivity of the wiring 240 can be improved.
  • the first conductor may be formed using a conductive material with high conductivity
  • the second conductor may be formed using a conductive material containing oxygen.
  • a conductive material containing oxygen as the second conductor of the wiring 240 that contacts the insulator 230, it is possible to suppress the diffusion of oxygen in the insulator 230 to the first conductor of the wiring 240.
  • the oxide semiconductor 270 comes into contact with the conductor 120, a metal compound or oxygen vacancy is formed, and the resistance of the region 270na of the oxide semiconductor 270 is reduced.
  • the contact resistance between the oxide semiconductor 270 and the conductor 120 is reduced.
  • the resistance of the region 270nb of the oxide semiconductor 270 is reduced. Therefore, the contact resistance between the oxide semiconductor 270 and the wiring 240 can be reduced.
  • the insulator 280 functions as an interlayer film, it is preferable that it has a low dielectric constant. By using a material with a low dielectric constant as the interlayer film, the electrostatic capacitance of the parasitic capacitance occurring between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant as described in the [Insulator] section below, can be used in a single layer or a multilayer configuration. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 270.
  • An insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is preferably used as the insulator 280.
  • excess oxygen an insulator containing oxygen that is released by heating
  • oxygen can be supplied from the insulator 280 to the channel formation region of the oxide semiconductor 270, thereby reducing oxygen vacancies and VOH .
  • the electrical characteristics of the transistor 200 can be stabilized and reliability can be improved.
  • an insulator having a function of capturing or fixing hydrogen as described in the section [Insulator] below, may be used. With such a structure, hydrogen in the oxide semiconductor 270 can be captured or fixed, and the hydrogen concentration in the oxide semiconductor 270 can be reduced.
  • the insulator 280 magnesium oxide, aluminum oxide, or the like can be used.
  • the insulator 280 may be an insulator having barrier properties against hydrogen, as described in the [Insulator] section below. With such a structure, hydrogen that may penetrate into the oxide semiconductor 270 can be reduced.
  • the insulator 280 may be aluminum oxide, magnesium oxide, hafnium oxide, silicon nitride, silicon nitride oxide, or the like. It is particularly preferable to use silicon nitride as the insulator 280.
  • the insulator 280 is shown as a single layer, but the present invention is not limited to this.
  • the insulator 280 may have a laminated structure.
  • the substrate on which the transistor 100 and the transistor 200 are formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate.
  • the insulating substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), and a resin substrate.
  • the semiconductor substrate include a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, and gallium oxide.
  • Examples of the semiconductor substrate include a semiconductor substrate having an insulating region inside the semiconductor substrate, such as an SOI (Silicon On Insulator) substrate.
  • Examples of the conductive substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate.
  • Examples of the conductive substrate include a substrate having a metal nitride and a substrate having a metal oxide.
  • Examples of the conductive substrate include a substrate having a conductor or semiconductor provided on an insulating substrate, a substrate having a conductor or insulator provided on a semiconductor substrate, and a substrate having a semiconductor or insulator provided on a conductive substrate.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding the transistor with an insulator that has a function of suppressing the permeation of impurities and oxygen.
  • an insulator that has a function of suppressing the permeation of impurities and oxygen for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • Insulators in contact with a semiconductor such as a gate insulator, or insulators provided near a semiconductor layer are preferably insulators having a region containing excess oxygen.
  • insulators having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer, oxygen vacancies in the semiconductor layer can be reduced.
  • Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.
  • Insulators that have a barrier property against oxygen include oxides containing either or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.
  • oxides containing either or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • Insulators that have barrier properties against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, silicon nitride, and silicon nitride oxide.
  • An insulator that has a barrier property against oxygen and an insulator that has a barrier property against hydrogen can be said to have a barrier property against either or both of oxygen and hydrogen.
  • Insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium. It is more preferable that these oxides have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. It is preferable that these metal oxides have an amorphous structure, but crystalline regions may be formed in some parts.
  • a barrier insulating film refers to an insulating film having a barrier property.
  • the barrier property refers to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • the function of capturing or fixing a corresponding substance can be rephrased as a barrier property.
  • hydrogen refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities refer to impurities in a channel formation region or a semiconductor layer unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , etc.), a copper atom, etc.
  • oxygen refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • the barrier property against oxygen refers to a property that at least one of an oxygen atom, an oxygen molecule, etc. is difficult to diffuse.
  • the conductor it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements.
  • a nitride of the alloy or an oxide of the alloy may be used as the alloy containing the above-mentioned metal elements as a component.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing the diffusion of oxygen, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide to which silicon has been added, indium zinc oxide, and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • conductive materials primarily composed of tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.
  • a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed as a conductor that functions as a gate electrode may also be used.
  • a conductive material containing the above-mentioned metal element and nitrogen may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride, may be used.
  • Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • Metal oxides may have lattice defects.
  • Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids.
  • Factors that cause lattice defects include a deviation in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.
  • the metal oxide used in the semiconductor layer of a transistor When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects.
  • V O H oxygen vacancies
  • the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies and impurities are reduced as much as possible in the channel formation region in the metal oxide. In other words, it is preferable that the carrier concentration of the channel formation region in the metal oxide is reduced and the channel formation region in the metal oxide is made i-type (intrinsic) or substantially i-type.
  • the types of lattice defects likely to exist in metal oxides and the amount of lattice defects present vary depending on the structure of the metal oxide or the method of forming the metal oxide film.
  • Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures.
  • A-like structures have a structure between the nc structures and the amorphous structures. The classification of crystal structures will be described later.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, metal oxides having an a-like structure have a higher hydrogen concentration in the metal oxide than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a metal oxide with high crystallinity for the semiconductor layer of the transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using such a metal oxide for the transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.
  • a metal oxide for the channel formation region of a transistor, which increases the on-state current of the transistor.
  • the crystal has a crystal structure in which multiple layers (for example, a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also called a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked.
  • metal oxides having the crystal include single crystal oxide semiconductors and CAAC-OS (c-axis aligned crystalline oxide semiconductors).
  • the c-axis of the crystal in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the multiple layers to be arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the multiple layers extend in the channel length direction.
  • the above three-layered crystal structure has the following structure.
  • the first layer has an atomic coordination structure of an oxygen octahedron with the metal of the first layer at the center.
  • the second layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the second layer at the center.
  • the third layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the third layer at the center.
  • Examples of the crystal structure of the above crystal include a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first layer to the third layer is preferably composed of one metal element or multiple metal elements having the same valence, and oxygen.
  • the valence of the one or multiple metal elements constituting the first layer is preferably the same as the valence of the one or multiple metal elements constituting the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of the one or multiple metal elements constituting the first layer is different from the valence of the one or multiple metal elements constituting the third layer.
  • the above structure improves the crystallinity of the metal oxide and increases the mobility of the metal oxide. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor increases, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably has two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semimetal element having a high bond energy with oxygen, for example, a metal element or semimetal element having a higher bond energy with oxygen than indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • the metal oxide of one embodiment of the present invention preferably has one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element” described in this specification, etc. may include metalloid elements.
  • indium zinc oxide In-Zn oxide
  • indium tin oxide In-Sn oxide
  • indium titanium oxide In-Ti oxide
  • indium gallium oxide In-Ga oxide
  • indium gallium aluminum oxide In-Ga-Al oxide
  • indium gallium tin oxide In-Ga-Sn oxide
  • gallium zinc oxide Ga-Zn oxide, also referred to as GZO
  • aluminum zinc oxide Al-Zn oxide, also referred to as AZO
  • IAZO indium Indium aluminum zinc oxide
  • indium tin zinc oxide In-Sn-Zn oxide
  • indium titanium zinc oxide In-Ti-Zn oxide
  • indium gallium tin zinc oxide In-Ga-Sn-Zn oxide, also written as IGZTO
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may have one or more metal elements with a large periodic number instead of indium.
  • the metal oxide may have one or more metal elements with a large periodic number in addition to indium.
  • Examples of metal elements with a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • In-Ga-Zn oxide may be used as an example of a metal oxide.
  • the metal oxide film formation method of the present invention it is preferable to deposit atoms one layer at a time.
  • the ALD method is used, so that it is easy to form a metal oxide having the above-mentioned layered crystal structure.
  • ALD plasma Enhanced ALD
  • the ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios; films can be formed with fewer defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures.
  • the PEALD method may be preferable because it can form films at lower temperatures by using plasma.
  • some precursors used in the ALD method contain elements such as carbon or chlorine.
  • films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the quantification of these elements can be performed using XPS or SIMS.
  • the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of the conditions of a high substrate temperature during film formation and the implementation of an impurity removal process, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles released from a target are deposited. Therefore, it is a film formation method that is not easily affected by the shape of the workpiece and has good step coverage.
  • the ALD method has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio.
  • the ALD method since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method or a CVD method, which have a fast film formation speed.
  • a method of forming a first metal oxide film using a sputtering method and forming a second metal oxide film on the first metal oxide using an ALD method can be mentioned.
  • the second metal oxide may grow as a crystal with the crystal part as a nucleus.
  • the ALD method can control the composition of the resulting film by the amount of raw material gas introduced.
  • the ALD method can form a film of any composition by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), and the like.
  • the ALD method can form a film whose composition changes continuously by changing the raw material gas while forming the film.
  • the time required for film formation can be shortened compared to forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of memory devices can be increased in some cases.
  • a transistor with high field-effect mobility can be realized.
  • a highly reliable transistor can be realized.
  • a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.
  • an oxide semiconductor having a low carrier concentration is preferably used for the channel formation region of the transistor.
  • the carrier concentration of the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less, and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more. Note that in order to reduce the carrier concentration of the oxide semiconductor, it is only necessary to reduce the impurity concentration in the oxide semiconductor and reduce the density of defect states.
  • a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film has a low density of defect states, and therefore may also have a low density of trap states.
  • the charge trapped in the trap states of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • an impurity in an oxide semiconductor refers to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (channel length is reduced).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the OS transistor can also be regarded as having an n + / n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ /n + accumulation-type non-junction transistor structure in which the channel formation region is an n ⁇ type region and the source and drain regions are n + type regions.
  • the OS transistor can have good electrical characteristics even when the memory device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more.
  • the OS transistor can be preferably used as a transistor having a shorter channel length than that of a Si transistor.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 18 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor 270 can be rephrased as a semiconductor layer including a channel formation region of a transistor.
  • a semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides.
  • a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer.
  • a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used for the semiconductor material.
  • layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of elemental semiconductors that can be used in the semiconductor material include silicon and germanium.
  • Examples of silicon that can be used in the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • An example of polycrystalline silicon is low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • the boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • the boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic crystal structure.
  • Layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements that belong to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Other examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).
  • Figure 12A shows a schematic perspective view of a storage device according to one embodiment of the present invention.
  • Figure 12B shows a block diagram of a storage device according to one embodiment of the present invention.
  • the memory device 750 shown in Figures 12A and 12B has a drive circuit layer 701 and n memory layers 700 (n is an integer equal to or greater than 1). Each memory layer 700 has a memory cell array 10.
  • the memory cell array 10 has a plurality of memory cells 11.
  • memory cell 150 As an example of the circuit configuration of memory cell 11, the configuration described in the above embodiment (memory cell 150) can be applied.
  • the n-layered memory layer 700 is provided on the drive circuit layer 701.
  • the area occupied by the memory device 750 can be reduced.
  • the memory capacity per unit area can be increased.
  • the first memory layer 700 is indicated as memory layer 700_1, the second memory layer 700 is indicated as memory layer 700_2, and the third memory layer 700 is indicated as memory layer 700_3.
  • the kth memory layer 700 (k is an integer between 1 and n) is indicated as memory layer 700_k, and the nth memory layer 700 is indicated as memory layer 700_n. Note that in this embodiment and the like, when describing matters related to the n memory layers 700 as a whole, or when indicating matters common to each layer of the n memory layers 700, the term "memory layer 700" may be used.
  • the drive circuit layer 701 has a PSW22 (power switch), a PSW23, and a peripheral circuit 31.
  • the peripheral circuit 31 has a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • Signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data, and signal RDA is read data.
  • Signals PON1 and PON2 are signals for power gating control. Signals PON1 and PON2 may be generated by control circuit 32.
  • the control circuit 32 is a logic circuit that has the function of controlling the overall operation of the memory device 750. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 750. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 750.
  • the control circuit 32 generates a control signal for the peripheral circuit 41 so that this operation mode is executed.
  • the voltage generation circuit 33 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.
  • the peripheral circuit 41 is a circuit for writing and reading data to the memory cells 11.
  • the peripheral circuit 41 has a row decoder 42, a column decoder 44 (Column Decoder), a row driver 43, a column driver 45 (Column Driver), an input circuit 47 (Input Cir.), an output circuit 48 (Output Cir.), and a sense amplifier 46 (Sense Amplifier).
  • the row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR.
  • the row decoder 42 is a circuit for specifying the row to be accessed
  • the column decoder 44 is a circuit for specifying the column to be accessed.
  • the row driver 43 has the function of selecting the wiring WWL (write word line) or wiring RWL (read word line) specified by the row decoder 42.
  • the column driver 45 has the function of writing data to the memory cell 11, the function of reading data from the memory cell 11, and the function of retaining the read data.
  • the column driver 45 has the function of selecting the wiring WBL (write bit line) and wiring RBL (read bit line) specified by the column decoder 44.
  • the input circuit 47 has a function of holding a signal WDA.
  • the data held by the input circuit 47 is output to the column driver 45.
  • the output data of the input circuit 47 is the data (Din) to be written to the memory cell 11.
  • the data (Dout) read from the memory cell 11 by the column driver 45 is output to the output circuit 48.
  • the output circuit 48 has a function of holding Dout.
  • the output circuit 48 has a function of outputting Dout to the outside of the memory device 750.
  • the data output from the output circuit 48 is the signal RDA.
  • PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31.
  • PSW23 has a function of controlling the supply of VHM to the row driver 43.
  • the high power supply voltage of the memory device 750 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW22 is controlled by signal PON1, and the on/off of PSW23 is controlled by signal PON2.
  • the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power domain.
  • Each of the n memory layers 700 has a memory cell array 10. Furthermore, the memory cell array 10 has a plurality of memory cells 11. Figures 12A and 12B show an example in which the memory cell array 10 has a plurality of memory cells 11 arranged in a matrix of p rows and q columns (p and q are integers equal to or greater than 2).
  • rows and columns extend in directions perpendicular to each other.
  • the X direction is referred to as the "rows” and the Y direction is referred to as the “columns”, but the X direction may also be referred to as the “columns” and the Y direction as the "rows”.
  • the memory cell 11 located in the first row and first column is indicated as memory cell 11[1,1]
  • the memory cell 11 located in the pth row and qth column is indicated as memory cell 11[p,q].
  • the memory cell 11 located in the ith row and jth column (i is an integer between 1 and p, and j is an integer between 1 and q) is indicated as memory cell 11[i,j].
  • the wiring WBL and wiring RBL are arranged in a direction perpendicular to the substrate surface.
  • the signal propagation distance between the wiring WBL and the sense amplifier connected to the wiring RBL can be shortened, and the resistance and parasitic capacitance of the wiring WBL and wiring RBL can be significantly reduced, thereby reducing power consumption and signal delay.
  • [DOSRAM] 13A shows an example of a circuit configuration of a memory cell of a DRAM.
  • a DRAM using an OS transistor is referred to as a dynamic oxide semiconductor random access memory (DOSRAM).
  • a memory cell 651 includes a transistor M1 and a capacitor CA.
  • the transistor M1 may have a front gate (sometimes simply called a gate) and a back gate.
  • the back gate may be connected to a wiring that supplies a constant potential or a signal, or the front gate and the back gate may be connected.
  • the first terminal of transistor M1 is connected to the first terminal of capacitance element CA, the second terminal of transistor M1 is connected to wiring BIL, and the gate of transistor M1 is connected to wiring WOL.
  • the second terminal of capacitance element CA is connected to wiring CAL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CA. When writing and reading data, it is preferable to apply a low-level potential (sometimes called a reference potential) to the wiring CAL.
  • Data is written and read by applying a high-level potential to the wiring WOL, turning on the transistor M1, and connecting the wiring BIL to the first terminal of the capacitance element CA.
  • the memory cell that can be used for memory cell 11 is not limited to memory cell 651, and the circuit configuration can be changed.
  • the configuration of memory cell 652 shown in FIG. 13B may be used.
  • Memory cell 652 is an example of a case where memory cell 652 does not have a capacitance element CA and a wiring CAL.
  • the first terminal of transistor M1 is in an electrically floating state.
  • the potential written through transistor M1 is held in the capacitance (also called parasitic capacitance) between the first terminal and the gate, as shown by the dashed line.
  • an OS transistor has a characteristic that its off-state current is extremely small.
  • the leakage current of transistor M1 can be made extremely low. That is, since written data can be held by transistor M1 for a long time, the frequency of refreshing the memory cell can be reduced. Alternatively, the refresh operation of the memory cell can be made unnecessary.
  • the leakage current is extremely low, multi-value data or analog data can be held in memory cell 651 and memory cell 652.
  • [NOSRAM] 13C shows an example of a circuit configuration of a gain cell type memory cell having two transistors and one capacitor.
  • the memory cell 653 includes a transistor M2, a transistor M3, and a capacitor CB.
  • a storage device having a gain cell type memory cell using an OS transistor as the transistor M2 is referred to as a nonvolatile oxide semiconductor RAM (NOSRAM).
  • the first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M2 is connected to wiring WBL, and the gate of transistor M2 is connected to wiring WOL.
  • the second terminal of capacitance element CB is connected to wiring CAL.
  • the first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitance element CB.
  • the wiring WBL functions as a write bit line
  • the wiring RBL functions as a read bit line
  • the wiring WOL functions as a word line.
  • the wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitance element CB.
  • a low-level potential sometimes called a reference potential
  • Data is written by applying a high-level potential to the wiring WOL, turning on transistor M2, and connecting wiring WBL to the first terminal of capacitance element CB. Specifically, when transistor M2 is on, a potential corresponding to the information to be recorded is applied to wiring WBL, and this potential is written to the first terminal of capacitance element CB and the gate of transistor M3. Then, a low-level potential is applied to wiring WOL, turning off transistor M2, thereby maintaining the potential of the first terminal of capacitance element CB and the potential of the gate of transistor M3.
  • Data is read by applying a predetermined potential to the wiring SL.
  • the current flowing between the source and drain of transistor M3 and the potential of the first terminal of transistor M3 are determined by the potential of the gate of transistor M3 and the potential of the second terminal of transistor M3. Therefore, by reading the potential of the wiring RBL connected to the first terminal of transistor M3, the potential held in the first terminal of capacitance element CB (or the gate of transistor M3) can be read. In other words, the information written in this memory cell can be read from the potential held in the first terminal of capacitance element CB (or the gate of transistor M3).
  • the wiring WBL and the wiring RBL may be combined into a single wiring BIL.
  • An example of the circuit configuration of such a memory cell is shown in FIG. 13D.
  • Memory cell 654 is configured such that the wiring WBL and the wiring RBL of memory cell 653 are combined into a single wiring BIL, and the second terminal of transistor M2 and the first terminal of transistor M3 are connected to the wiring BIL.
  • memory cell 654 is configured to operate the write bit line and the read bit line as a single wiring BIL.
  • Memory cell 656 shown in FIG. 13E is an example of memory cell 654 in which capacitance CB and wiring CAL are omitted. With this configuration, the integration density of the memory cell can be increased.
  • OS transistor for at least transistor M2.
  • OS transistors for transistors M2 and M3.
  • the OS transistor Since the OS transistor has a characteristic that the off-state current is extremely small, the written data can be held for a long time by the transistor M2. This reduces the frequency of refreshing the memory cell. Alternatively, the refresh operation of the memory cell can be eliminated. In addition, since the leakage current is extremely low, multi-value data or analog data can be held in the memory cell 653, the memory cell 654, and the memory cell 656.
  • Memory cell 653, memory cell 654, and memory cell 656, in which an OS transistor is used as transistor M2, are one embodiment of NOSRAM.
  • Si transistors may be used as transistor M3.
  • Si transistors can increase the field effect mobility and can also be used as p-channel transistors, allowing for greater freedom in circuit design.
  • the memory cell can be configured as a unipolar circuit.
  • FIG. 13F shows a three-transistor, one-capacitor gain cell type memory cell 657.
  • Memory cell 657 has transistors M4 to M6 and a capacitative element CC.
  • the first terminal of transistor M4 is connected to the first terminal of the capacitance element CC, the second terminal of transistor M4 is connected to the wiring BIL, and the gate of transistor M4 is connected to the wiring WOL.
  • the second terminal of the capacitance element CC is electrically connected to the first terminal of transistor M5 and the wiring GNDL.
  • the second terminal of transistor M5 is connected to the first terminal of transistor M6, and the gate of transistor M5 is connected to the first terminal of the capacitance element CC.
  • the second terminal of transistor M6 is connected to the wiring BIL, and the gate of transistor M6 is connected to the wiring RWL.
  • the wiring BIL functions as a bit line
  • the wiring WOL functions as a write word line
  • the wiring RWL functions as a read word line.
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL, turning on the transistor M4, and connecting the wiring BIL to the first terminal of the capacitance element CC.
  • a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the first terminal of the capacitance element CC and the gate of the transistor M5.
  • a low-level potential is applied to the wiring WOL, turning off the transistor M4, thereby holding the potential of the first terminal of the capacitance element CC and the potential of the gate of the transistor M5.
  • Data is read by precharging the wiring BIL with a predetermined potential, then electrically floating the wiring BIL, and applying a high-level potential to the wiring RWL. Since the wiring RWL is at a high-level potential, the transistor M6 is in a conductive state, and the wiring BIL and the second terminal of the transistor M5 are electrically connected. At this time, the potential of the wiring BIL is applied to the second terminal of the transistor M5, and the potential of the second terminal of the transistor M5 and the potential of the wiring BIL change depending on the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5) can be read.
  • the information written in this memory cell can be read from the potential held in the first terminal of the capacitance element CC (or the gate of the transistor M5).
  • Si transistors may be used as transistors M5 and M6. As mentioned above, Si transistors may have higher field-effect mobility than OS transistors depending on the crystal state of the silicon used in the semiconductor layer.
  • the memory cell can be configured as a unipolar circuit.
  • OS-SRAM 13G shows an example of a static random access memory (SRAM) using an OS transistor.
  • SRAM static random access memory
  • OS-SRAM oxide semiconductor SRAM
  • a memory cell 658 shown in FIG. 13G is a memory cell of an SRAM capable of backing up data.
  • Memory cell 658 includes transistors M7 to M10, transistors MS1 to MS4, and capacitance elements CD1 and CD2. Note that transistors MS1 and MS2 are p-channel transistors, and transistors MS3 and MS4 are n-channel transistors.
  • the first terminal of transistor M7 is connected to the wiring BIL, and the second terminal of transistor M7 is connected to the first terminal of transistor MS1, the first terminal of transistor MS3, the gate of transistor MS2, the gate of transistor MS4, and the first terminal of transistor M10.
  • the gate of transistor M7 is connected to the wiring WOL.
  • the first terminal of transistor M8 is connected to the wiring BILB, and the second terminal of transistor M8 is connected to the first terminal of transistor MS2, the first terminal of transistor MS4, the gate of transistor MS1, the gate of transistor MS3, and the first terminal of transistor M9.
  • the gate of transistor M8 is connected to the wiring WOL.
  • the second terminal of the transistor MS1 is electrically connected to the wiring VDL.
  • the second terminal of the transistor MS2 is electrically connected to the wiring VDL.
  • the second terminal of the transistor MS3 is electrically connected to the wiring GNDL.
  • the second terminal of the transistor MS4 is electrically connected to the wiring GNDL.
  • the second terminal of transistor M9 is connected to the first terminal of capacitance element CD1, and the gate of transistor M9 is connected to wiring BRL.
  • the second terminal of transistor M10 is connected to the first terminal of capacitance element CD2, and the gate of transistor M10 is connected to wiring BRL.
  • the second terminal of the capacitance element CD1 is connected to the wiring GNDL, and the second terminal of the capacitance element CD2 is connected to the wiring GNDL.
  • the wiring BIL and the wiring BILB function as bit lines
  • the wiring WOL functions as a word line
  • the wiring BRL is a wiring that controls the conductive state and non-conductive state of the transistors M9 and M10.
  • the wiring VDL is a wiring that provides a high-level potential
  • the wiring GNDL is a wiring that provides a low-level potential.
  • Data is written by applying a high-level potential to the wiring WOL and a high-level potential to the wiring BRL. Specifically, when the transistor M10 is in a conductive state, a potential corresponding to the information to be recorded is applied to the wiring BIL, and the potential is written to the second terminal side of the transistor M10.
  • the memory cell 658 forms an inverter loop with the transistors MS1 and MS2, an inverted signal of the data signal corresponding to the potential is input to the second terminal of the transistor M8. Since the transistor M8 is in a conductive state, the potential applied to the wiring BIL, i.e., the inverted signal of the signal input to the wiring BIL, is output to the wiring BILB. Also, since the transistors M9 and M10 are in a conductive state, the potential of the second terminal of the transistor M7 and the potential of the second terminal of the transistor M8 are held in the first terminal of the capacitance element CD2 and the first terminal of the capacitance element CD1, respectively.
  • a low-level potential is applied to the wiring WOL and a low-level potential is applied to the wiring BRL to make the transistors M7 to M10 non-conductive, thereby holding the potential of the first terminal of the capacitance element CD1 and the first terminal of the capacitance element CD2.
  • a high-level potential is applied to the wiring WOL and a high-level potential is applied to the wiring BRL, so that the potential of the first terminal of the capacitance element CD1 is refreshed by the inverter loop of the memory cell 658 and output to the wiring BILB.
  • the potential of the first terminal of the capacitance element CD2 is refreshed by the inverter loop of the memory cell 658 and output to the wiring BIL.
  • the potentials of the wiring BIL and wiring BILB change from the precharged potentials to the potential of the first terminal of the capacitance element CD2 and the potential of the first terminal of the capacitance element CD1, respectively, so that the potential held in the memory cell can be read from the potential of the wiring BIL or wiring BILB.
  • OS transistors as the transistors M7 to M10. This allows the written data to be held for a long time by the transistors M7 to M10, so that the frequency of refreshing the memory cells can be reduced. Alternatively, the refresh operation of the memory cells can be eliminated.
  • Si transistors may be used as transistors MS1 to MS4.
  • Figure 14 shows a block diagram of the arithmetic processing device 660.
  • the arithmetic processing device 660 shown in Figure 14 can be applied to, for example, a CPU (Central Processing Unit).
  • the arithmetic processing device 660 can also be applied to arithmetic processing devices such as a GPU (Graphics Processing Unit), a TPU (Tensor Processing Unit), and an NPU (Neural Processing Unit) that have multiple processor cores (several tens to several hundreds) capable of parallel processing more than a CPU.
  • a GPU Graphics Processing Unit
  • TPU Torsor Processing Unit
  • NPU Neurological Processing Unit
  • the arithmetic processing device 660 shown in FIG. 14 has an ALU 691 (ALU: Arithmetic logic unit, arithmetic circuit), an ALU controller 692, an instruction decoder 693, an interrupt controller 694, a timing controller 695, a register 696, a register controller 697, a bus interface 698, a cache 699, and a cache interface 689 on a substrate 690.
  • the substrate 690 is a semiconductor substrate, an SOI substrate, a glass substrate, or the like. It may have a rewritable ROM and a ROM interface.
  • the cache 699 and the cache interface 689 may be provided on separate chips.
  • the cache 699 is connected to a main memory provided on a separate chip via a cache interface 689.
  • the cache interface 689 has a function of supplying a portion of the data held in the main memory to the cache 699.
  • the cache interface 689 also has a function of outputting a portion of the data held in the cache 699 to the ALU 691 or register 696, etc. via the bus interface 698.
  • the memory cell array 10 can be provided by stacking it on the arithmetic processing device 660.
  • the memory cell array 10 can be used as a cache.
  • the cache interface 689 may have a function of supplying data held in the memory cell array 10 to the cache 699.
  • it is preferable that part of the cache interface 689 has a drive circuit for the memory cell array (a circuit included in the drive circuit layer 701).
  • the arithmetic processing device 660 shown in FIG. 14 is merely one example of a simplified configuration, and the actual arithmetic processing device 660 has a wide variety of configurations depending on the application.
  • the more cores there are, the more preferable it is, but for example, two, preferably four, more preferably eight, even more preferably twelve, and even more preferably sixteen or more.
  • the number of bits that the arithmetic processing device 660 can handle in its internal arithmetic circuit, data bus, etc. can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, etc.
  • Instructions input to the arithmetic processing unit 660 via the bus interface 698 are input to the instruction decoder 693, decoded, and then input to the ALU controller 692, interrupt controller 694, register controller 697, and timing controller 695.
  • the ALU controller 692, interrupt controller 694, register controller 697, and timing controller 695 perform various controls based on the decoded instructions. Specifically, the ALU controller 692 generates signals for controlling the operation of the ALU 691. In addition, the interrupt controller 694 determines and processes interrupt requests from external input/output devices, peripheral circuits, etc. based on their priority and mask state while the arithmetic processing unit 660 is executing a program.
  • the register controller 697 generates the address of the register 696, and reads and writes to the register 696 depending on the state of the arithmetic processing unit 660.
  • the timing controller 695 also generates signals that control the timing of the operations of the ALU 691, the ALU controller 692, the instruction decoder 693, the interrupt controller 694, and the register controller 697.
  • the timing controller 695 includes an internal clock generating unit that generates an internal clock signal based on a reference clock signal, and supplies the internal clock signal to the various circuits described above.
  • the register controller 697 selects the holding operation in the register 696 according to instructions from the ALU 691. That is, it selects whether the memory cells in the register 696 will hold data using flip-flops or using capacitive elements. If holding data using flip-flops is selected, a power supply voltage is supplied to the memory cells in the register 696. If holding data in capacitive elements is selected, the data is rewritten to the capacitive elements, and the supply of power supply voltage to the memory cells in the register 696 can be stopped.
  • FIGS 15A and 15B show perspective views of a semiconductor device 670A.
  • the semiconductor device 670A has a memory layer 700 in which a memory cell array is provided on the arithmetic processing device 660.
  • the memory layer 700 is provided with a memory cell array 10L1, a memory cell array 10L2, and a memory cell array 10L3.
  • the arithmetic processing device 660 and each memory cell array have mutually overlapping regions.
  • Figure 15B shows the arithmetic processing device 660 and the memory layer 700 separated.
  • connection distance between the two can be shortened. This allows the communication speed between the two to be increased. In addition, the short connection distance allows for reduced power consumption.
  • a method for stacking the memory layer 700 having a memory cell array and the arithmetic processing unit 660 a method of stacking the memory layer 700 having a memory cell array directly on the arithmetic processing unit 660 (also called monolithic stacking) may be used, or a method of forming the arithmetic processing unit 660 and the memory layer 700 on different substrates, bonding the two substrates, and electrically connecting them using through-vias or conductive film bonding technology (such as Cu-Cu bonding) may be used.
  • the former method does not require consideration of misalignment during bonding, so it is possible to not only reduce the chip size but also reduce manufacturing costs.
  • the arithmetic processing device 660 does not have a cache 699, and the memory cell arrays 10L1, 10L2, and 10L3 provided in the memory layer 700 can each be used as a cache.
  • the memory cell array 10L1 can be used as an L1 cache (also called a level 1 cache)
  • the memory cell array 10L2 can be used as an L2 cache (also called a level 2 cache)
  • the memory cell array 10L3 can be used as an L3 cache (also called a level 3 cache).
  • the memory cell array 10L3 has the largest capacity and is accessed the least frequently.
  • the memory cell array 10L1 has the smallest capacity and is accessed the most frequently.
  • each memory cell array provided in the memory layer 700 can be used as a lower-level cache or a main memory.
  • the main memory has a larger capacity than the cache and is accessed less frequently.
  • the arithmetic processing device 660 is provided with a driving circuit 610L1, a driving circuit 610L2, and a driving circuit 610L3.
  • the driving circuit 610L1 is connected to the memory cell array 10L1 via a connection electrode 640L1.
  • the driving circuit 610L2 is connected to the memory cell array 10L2 via a connection electrode 640L2
  • the driving circuit 610L3 is connected to the memory cell array 10L3 via a connection electrode 640L3.
  • the drive circuit 610L1 may function as part of the cache interface 689, or the drive circuit 610L1 may be configured to be connected to the cache interface 689.
  • the drive circuit 610L2 and the drive circuit 610L3 may also function as part of the cache interface 689, or may be configured to be connected to it.
  • Whether the memory cell array 10 functions as a cache or as a main memory is determined by the control circuit 32 of each drive circuit 610.
  • the control circuit 32 can cause some of the multiple memory cells 11 in the storage device 750 to function as RAM based on a signal supplied from the arithmetic processing device 660.
  • the memory device 750 can cause some of the multiple memory cells 11 to function as a cache, and the other part to function as a main memory. In other words, the memory device 750 can function both as a cache and as a main memory.
  • the memory device 750 according to one aspect of the present invention can function, for example, as a universal memory.
  • a memory layer 700 having one memory cell array 10 may be provided on top of the arithmetic processing device 660.
  • Figure 16A shows a perspective view of the semiconductor device 670B.
  • one memory cell array 10 can be divided into multiple areas, each of which can be used for different functions.
  • Figure 16A shows an example in which area L1 is used as an L1 cache, area L2 is used as an L2 cache, and area L3 is used as an L3 cache.
  • the capacity of each of areas L1 to L3 can be changed according to the situation. For example, if it is desired to increase the capacity of the L1 cache, this can be achieved by increasing the area of area L1. With such a configuration, it is possible to improve the efficiency of calculation processing and increase the processing speed.
  • Figure 16B shows a perspective view of semiconductor device 670C.
  • the semiconductor device 670C has a memory layer 700L1 having a memory cell array 10L1 stacked on top of a memory layer 700L2 having a memory cell array 10L2, and a memory layer 700L3 having a memory cell array 10L3 stacked on top of that.
  • the memory cell array 10L1 which is physically closest to the arithmetic processing device 660, can be used as a higher-level cache, and the memory cell array 10L3, which is the furthest away, can be used as a lower-level cache or main memory. With this configuration, the capacity of each memory cell array can be increased, thereby further improving processing power.
  • Figure 17A shows various storage devices used in semiconductor devices by hierarchy. The higher the storage device, the faster the operating speed is required, and the lower the storage device, the larger the storage capacity and the higher the recording density are required.
  • a processor such as a CPU, an L1 cache, an L2 cache, an L3 cache, a main memory, storage, etc. Note that, although an example having up to an L3 cache is shown here, it is also possible to have even lower-level caches.
  • Registers also have the function of storing setting information for the processor.
  • a cache has the function of duplicating and storing a portion of the data stored in the main memory. By duplicating frequently used data and storing it in the cache, the speed of accessing the data can be increased.
  • the storage capacity required for a cache is less than that of the main memory, but it is required to operate at a faster speed than the main memory.
  • data that is rewritten in the cache is duplicated and supplied to the main memory.
  • the main memory has the function of holding programs, data, etc. read from storage.
  • Storage has the function of holding data that requires long-term storage, as well as various programs used by the processor. Therefore, storage requires a larger memory capacity and higher recording density than operating speed.
  • a high-capacity, non-volatile storage device such as 3D NAND can be used.
  • a storage device (OS memory) using an oxide semiconductor according to one embodiment of the present invention has a high operating speed and can retain data for a long period of time. Therefore, as shown in FIG. 17A, the storage device according to one embodiment of the present invention can be suitably used in both the hierarchy where the cache is located and the hierarchy where the main memory is located. In addition, the storage device according to one embodiment of the present invention can also be applied to the hierarchy where the storage is located.
  • FIG 17B also shows an example in which SRAM is used for part of the cache and OS memory according to one aspect of the present invention is used for the other part.
  • the lowest level cache can be called an LLC (Last Level cache).
  • LLC Low Level cache
  • the OS memory of one embodiment of the present invention has a fast operating speed and is capable of retaining data for a long period of time, making it suitable for use as an LLC. Note that the OS memory of one embodiment of the present invention can also be applied to an FLC (Final Level cache).
  • a configuration can be used in which SRAM is used for the higher-level cache (L1 cache, L2 cache, etc.) and the OS memory of one aspect of the present invention is used for the LLC. Also, as shown in FIG. 17B, not only the OS memory but also DRAM can be used for the main memory.
  • a semiconductor device such as a computer (also referred to as a computer) according to one embodiment of the present invention will be described with reference to the drawings.
  • the computer includes a storage device according to one embodiment of the present invention. At least a part of the computer according to one embodiment of the present invention can be used in, for example, a microcomputer, a personal computer, a workstation, a mainframe, a supercomputer, or the like.
  • FIG. 18 is a block diagram illustrating an example of the configuration of a computer 900 of one embodiment of the present invention.
  • the electronic computer 900 has a processing unit 910 (also called a processing device), a storage unit 920 (sometimes called a memory), and a control unit 930.
  • the processing unit 910, the storage unit 920, and the control unit 930 are electrically connected to each other via a bus line 971.
  • the electronic calculator 900 may have, for example, an input/output unit (sometimes called an interface).
  • the input/output unit has a function of exchanging data with, for example, functional devices (e.g., an input device, an output device, a storage device, etc.) provided outside the electronic calculator 900.
  • functional devices e.g., an input device, an output device, a storage device, etc.
  • the processing unit 910 has a function of executing a series of processes (tasks), for example, by sequentially executing processes according to a program. It also has a function of executing multiple tasks, for example. At least a part of the processing unit 910 can be used as, for example, a CPU (Central Processing Unit), an MPU (Micro Processing Unit), and a GPU (Graphics Processing Unit).
  • a CPU Central Processing Unit
  • MPU Micro Processing Unit
  • GPU Graphics Processing Unit
  • the processing unit 910 has an arithmetic unit 911 (sometimes called a core), a control unit 912, and a register unit 913.
  • the register unit 913 has one or more register units 914.
  • the register unit 914 has a scan flip-flop 915 and a backup memory 916. At least a portion of the register unit 914 can be used as, for example, a general-purpose register and a dedicated register (e.g., a program counter (PC), an instruction register (IR), and a status register (SR)).
  • PC program counter
  • IR instruction register
  • SR status register
  • the calculation unit 911 may have, for example, an arithmetic logic unit (ALU) and a floating point unit (FPU).
  • ALU arithmetic logic unit
  • FPU floating point unit
  • the control unit 912 has a function of controlling the operation of the processing unit 910. For example, it has a function of controlling processing performed while switching between multiple tasks. It can also have, for example, an instruction decoder (ID: Instruction Decoder) and the like.
  • ID Instruction Decoder
  • register unit 914 Specific configuration examples of the register unit 914 will be described later.
  • the memory unit 920 has a function of storing, for example, programs and data. At least a portion of the memory unit 920 can be used as, for example, a main memory, a cache memory, etc.
  • the memory unit 920 has a memory array unit 921 and a control unit 922.
  • the memory array section 921 has one or more memory blocks 923.
  • the memory block 923 has one or more memory units 924 and a sense amplifier 926.
  • the memory unit 924 has one or more memory cells 925 and a sub-sense amplifier 927. Note that the memory unit 924 may not have the sub-sense amplifier 927 depending on the configuration of the memory cells 925.
  • a group of multiple memory cells 925 enclosed by a dotted line in FIG. 18 may be referred to as a memory cell array.
  • the memory cells 150 described in embodiment 1 may be used as the memory cells 925.
  • the control unit 922 has a function of controlling the operation of the memory unit 920. For example, it has a function of controlling the writing and reading of data to and from the memory array unit 921.
  • the control unit 930 has a function of controlling the operation of the electronic computer 900. It can also have, for example, a power management unit (PMU).
  • the PMU has a function of controlling, for example, the operation of power gating. For example, it has a function of controlling the supply of power to each component of the electronic computer 900 by putting a power switch (not shown) into a conductive state or a non-conductive state.
  • Figures 19A and 19B are schematic diagrams each illustrating an example of the layer structure of an electronic calculator 900.
  • the electronic calculator 900 has a layer 985 and a layer 982.
  • the layer 982 has a layer 983 and multiple layers 984 (layers 984[1] to 984[K] (K is an integer of 2 or more)). Note that the layer 982 may have a single layer 984.
  • Layer 983 is stacked on layer 985.
  • Layers 984[1] to 984[K] are stacked on layer 983.
  • the X, Y, and Z directions are defined to make it easier to understand the positional relationship between the components.
  • the X, Y, and Z directions are perpendicular or approximately perpendicular to each other. Approximately perpendicular means that the angle between the two elements is between 85 degrees and 95 degrees.
  • the Z direction is the direction in which layer 983 and layers 984[1] to 984[K] are stacked on top of layer 985. Therefore, the X and Y directions are the directions along the respective surfaces of layer 985, layer 983, and layers 984[1] to 984[K].
  • Layer 985 can be provided on an insulating or semiconducting substrate including a variety of materials.
  • the layer 985 can be provided on a substrate containing silicon. That is, the layer 985 can be provided with a Si transistor (a transistor containing silicon in a channel formation region).
  • a CMOS circuit for example, a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit
  • a CMOS circuit can be configured by electrically connecting the gate of an n-channel Si transistor and the gate of a p-channel Si transistor in the layer 985.
  • Each of the layers 983 and 984[1] to 984[K] can include various materials, such as a conductor, a semiconductor, and an insulator. Also, each of the layers 983 and 984[1] to 984[K] can include various elements, such as a capacitor and a transistor.
  • the semiconductor layer including the channel formation region of the transistor provided in layer 983 and the semiconductor layer including the channel formation region of the transistor provided in layers 984[1] to 984[K] may have the same material or different materials.
  • the transistor provided in layer 983 and the transistor provided in layers 984[1] to 984[K] may have the same structure or different structures.
  • OS transistors transistors including an oxide semiconductor in a channel formation region
  • layers 984[1] to 984[K] can be provided in layer 983 and layers 984[1] to 984[K].
  • OS transistors have a characteristic of having an extremely low off-state current.
  • the off-state current hardly increases even in a high-temperature environment, and the on-state current is not easily decreased. Therefore, for example, when a wiring electrically connected to one of the source and drain of an OS transistor is in a floating state (also called floating), the charge accumulated in the wiring can be held for a long period of time. Therefore, in one embodiment of the present invention, for example, by forming a memory cell using an OS transistor, data written to the memory cell can be stored for a long period of time.
  • the OS transistor can have a structure in which, for example, a planar transistor is provided in layer 983, and vertical transistors (transistors in which at least a part of a semiconductor layer including a channel formation region is provided inside an opening formed in an insulating layer) are provided in layers 984[1] to 984[K].
  • Vertical transistors have a structure that makes it easier to reduce the area (footprint) they occupy compared to planar transistors.
  • the channel length can be made small and the channel width can be made large, it is easy to reduce the on-resistance (increase the on-current). Therefore, in one embodiment of the present invention, for example, by configuring a memory cell using vertical transistors, the cell area (cell size) of the memory cell can be reduced.
  • Planar transistors have a structure that makes it easier to increase the channel length compared to vertical transistors, and therefore, for example, it is easy to reduce short channel effects such as drain induced barrier lowering (DIBL). In other words, it is easy to realize a transistor with high saturation (small change in drain current with respect to drain voltage in the saturation region of the transistor). Therefore, one aspect of the present invention is, for example, to improve the characteristics of a sense amplifier by configuring the sense amplifier using planar transistors.
  • DIBL drain induced barrier lowering
  • a vertical transistor may be provided in the layer 983.
  • a planar transistor may be provided in the layers 984[1] to 984[K].
  • the electronic calculator 900 may have a configuration in which wiring layers are appropriately provided between each of the layers 985, 983, and 984[1] to 984[K].
  • the wiring layers may include wiring for electrically connecting various elements to each other.
  • the electronic computer 900 may have a configuration in which multiple layers 983 (layers 983[1] to 983[H] (H is an integer of 2 or more)) are provided, and layers 983[1] to 983[H] are stacked.
  • the electronic computer 900 may have a configuration in which multiple layers 982 (layers 982[1] to 982[L] (L is an integer of 2 or more)) are provided, and layers 982[1] to 982[L] are stacked.
  • Figures 20A to 20D are schematic diagrams illustrating an example of the arrangement of each component of the electronic calculator 900.
  • each component shown in Figure 18 can be appropriately arranged, for example, in each layer shown in Figure 19A.
  • Figures 20A to 20D illustrate an arithmetic unit 911, a control unit 912, a scan flip-flop 915, and a backup memory 916 of the processing unit 910 as some of the components of the electronic calculator 900.
  • Also illustrated are a memory cell 925, a sense amplifier 926, and a sub-sense amplifier 927 of the storage unit 920.
  • the electronic calculator 900 shown in FIG. 20A has a layer 985, a layer 983, and layers 984[1] to 984[K].
  • the arithmetic unit 911, the control unit 912, the scan flip-flop 915, and the sense amplifier 926 are arranged in the layer 985.
  • the control unit 930 and the control unit 922 of the memory unit 920 are also arranged in the layer 985.
  • the sense amplifier 926 can be arranged, for example, between the arithmetic unit 911 and the control unit 912.
  • the backup memory 916 is arranged in the layer 983 so as to overlap the scan flip-flop 915.
  • the sub-sense amplifier 927 is arranged in the layer 983 so as to overlap the sense amplifier 926.
  • the sub-sense amplifier 927 can be arranged, for example, so as to overlap the arithmetic unit 911 and the control unit 912.
  • the memory cells 925 are arranged in layers 984[1] to 984[K] so as to overlap the sub-sense amplifier 927.
  • the memory cells 925 can also be arranged so as to overlap, for example, the arithmetic unit 911 and the control unit 912. They can also be arranged so as to overlap, for example, the backup memory 916.
  • the electronic calculator 900 shown in FIG. 20A can be said to have a configuration in which the memory array unit 921 of the storage unit 920 is arranged inside the processing unit 910.
  • the control unit 922 may also be arranged inside the processing unit 910.
  • the dead space of layer 983 and layers 984[1] to 984[K] can be reduced, and area efficiency can be improved. Therefore, the surface density (recording density) of the memory array section 921 can be improved. Therefore, the storage capacity of the storage section 920 of the electronic computer 900 can be improved, and the electronic computer 900 can be made smaller.
  • the bus line 971 between the processing section 910 and the storage section 920 can be shortened. Therefore, the access time (the time required to write and read data) and the access energy (the energy consumed by writing and reading data) can be reduced. Therefore, the operating speed of the electronic computer 900 can be improved, and power consumption can be reduced.
  • the electronic calculator 900 shown in FIG. 20B is a modified example of the electronic calculator 900 shown in FIG. 20A, and differs in that it does not have a sub-sense amplifier 927. As described above, the electronic calculator 900 may not have the sub-sense amplifier 927 depending on the configuration of the memory cell 925.
  • the electronic calculator 900 shown in FIG. 20C is a modified example of the electronic calculator 900 shown in FIG. 20B, and differs in that it includes a functional circuit 928.
  • the functional circuit 928 is disposed on a layer 983 so as to overlap the sense amplifier 926. Note that the functional circuit 928 can also be disposed so as to overlap, for example, the arithmetic unit 911 and the control unit 912.
  • the functional circuit 928 can have the function of selecting one of the multiple memory cell arrays. This allows the sense amplifier 926 to write and read data to and from the memory cells 925 of the selected memory cell array. Therefore, for example, by sharing the sense amplifier 926 and the control unit 922 for multiple memory cell arrays, the layout area in the layer 985 can be reduced. This allows the electronic calculator 900 to be made smaller.
  • the electronic computer 900 shown in FIG. 20D is a modified example of the electronic computer 900 shown in FIG. 20A, and differs in that it has layers 983[1] and 983[2] instead of layer 983.
  • the backup memory 916 is arranged in layer 983[1] so as to overlap the scan flip-flop 915.
  • the sub-sense amplifier 927 is arranged in layer 983[2] so as to overlap the sense amplifier 926. Note that the sub-sense amplifier 927 can also be arranged, for example, so as to overlap the arithmetic unit 911, the control unit 912, and the backup memory 916.
  • the parasitic capacitance between the sub-sense amplifier 927 and the arithmetic unit 911 and between the sub-sense amplifier 927 and the arithmetic unit 911 and the control unit 912 can be reduced. This can reduce the effect of the operation of one unit on the operation of the other unit as noise, for example. This can improve the reliability of the electronic calculator 900.
  • the potential corresponding to the binary data is the potential VDD, which is a high power supply potential
  • the potential corresponding to the binary data "0" is the potential VSS, which is a low power supply potential
  • the potential VDD is a potential higher than the potential VSS at least the threshold voltage of the transistor.
  • the potential VSS may be, for example, a ground potential.
  • the potential of the signal is the potential H or the potential L.
  • the potential H is a potential that is applied to the gate of an n-channel transistor to make the transistor conductive, and is a potential that is applied to the gate of a p-channel transistor to make the transistor non-conductive.
  • the potential L is a potential that is applied to the gate of an n-channel transistor to make the transistor non-conductive, and is a potential that is applied to the gate of a p-channel transistor to make the transistor conductive.
  • the potential H can be, for example, the same potential as the potential VDD or a potential higher than the potential VDD.
  • the potential L can be, for example, the same potential as the potential VSS or a potential lower than the potential VSS.
  • the potential H and the potential L do not need to be the same for each of the multiple signals.
  • the potential H and the potential L for each of the multiple signals may be different depending on the threshold voltage of the transistor to which the signal is applied.
  • the potential H and the potential L of a signal applied to the gate of a Si transistor provided in layer 985 may be different from the potential H and the potential L of a signal applied to the gate of an OS transistor provided in layer 983 and layers 984[1] to 984[K].
  • a semiconductor device 810 according to one embodiment of the present invention will be described. At least a part of the semiconductor device 810 can be used for, for example, the above-described electronic computer 900 illustrated in FIG. 18 and the like. For example, the semiconductor device can be used for the register unit 914 included in the processing unit 910.
  • FIG. 21 is a circuit diagram illustrating an example of the configuration of a semiconductor device 810. As shown in FIG.
  • the semiconductor device 810 shown in FIG. 21 has a scan flip-flop circuit 850 and a backup circuit 830.
  • the scan flip-flop circuit 850 corresponds to the scan flip-flop 915
  • the backup circuit 830 corresponds to the backup memory 916. That is, for example, the scan flip-flop circuit 850 is arranged in the layer 985, and the backup circuit 830 is arranged in the layer 983. Therefore, for example, a Si transistor can be used for the scan flip-flop circuit 850, and an OS transistor can be used for the backup circuit 830.
  • the scan flip-flop circuit 850 includes a selector circuit 851 and a flip-flop circuit 852.
  • the backup circuit 830 includes holding circuits 831[1] to 831[G] (G is an integer of 2 or more) and a transistor M801.
  • Each of the holding circuits 831[1] to 831[G] includes a transistor M802, a transistor M803, and a capacitor C801.
  • the semiconductor device 810 can store and hold data input from the wiring D or data input from the wiring SD in the flip-flop circuit 852 in the scan flip-flop circuit 850 in synchronization with a clock signal applied to the wiring PCK, and output the data to the wiring Q.
  • the data held in the flip-flop circuit 852 is written to one of the holding circuits 831[1] to 831[G] in the backup circuit 830 via the wiring Q by a signal applied to the wiring BK[1] to wiring BK[G], and then held.
  • Such an operation may be called, for example, save, evacuation, store, or backup.
  • the data held in one of the holding circuits 831[1] to 831[G] is written back to the flip-flop circuit 852 via the wiring SD by a signal applied to the wiring RV[1] to wiring RV[G], and then held.
  • Such an operation may be called, for example, load, return, restore, or recovery.
  • the flip-flop circuit 852 has a function of storing and holding data given to the input terminal Df in synchronization with a clock signal given to the wiring PCK, and outputting the data from the output terminal Qf.
  • a flip-flop circuit provided in a standard circuit library can be used.
  • a positive edge trigger type D flip-flop can be used.
  • the selector circuit 851 has a function of transmitting data provided to the wiring D or the wiring SD to the flip-flop circuit 852 by a signal provided to the wiring SE. Data input from outside the semiconductor device 810 is provided to the wiring D. Data held in any one of the holding circuits 831[1] to 831[G] in the backup circuit 830 or data input from the wiring SD_IN is provided to the wiring SD_IN. Data for a scan test is provided to the wiring SD_IN.
  • the backup circuit 830 can hold the state of the scan flip-flop circuit 850 in one of the holding circuits 831[1] to 831[G]. In addition, when performing processing while switching between multiple tasks, the backup circuit 830 can hold the state of the scan flip-flop circuit 850 for each task in one-to-one correspondence with each of the holding circuits 831[1] to 831[G].
  • one of the holding circuits 831[1] to 831[G] is selected by a signal provided to the wirings BK[1] to BK[G].
  • one of the holding circuits 831[1] to 831[G] is selected by a signal provided to the wirings RV[1] to RV[G]. Signals are provided to the wirings BK[1] to BK[G] and the wirings RV[1] to RV[G] so as to correspond one-to-one to the holding circuits 831[1] to 831[G].
  • each of the holding circuits 831[1] to 831[G] may be described as the holding circuit 831.
  • each of the wirings BK[1] to BK[G] may be described as the wiring BK
  • each of the wirings RV[1] to RV[G] may be described as the wiring RV.
  • the holding circuit 831 is electrically connected to each of the wiring Q and the wiring SD.
  • the terminal (wiring) electrically connected to the wiring Q is the input terminal
  • the terminal (wiring) electrically connected to the wiring SD is the output terminal. That is, in the semiconductor device 810, the output terminal Qf of the flip-flop circuit 852 is electrically connected to the input terminal of the holding circuit 831, and the input terminal Df of the flip-flop circuit 852 is electrically connected to the output terminal of the holding circuit 831 via the selector circuit 851.
  • one of the source and drain of the transistor M802 is electrically connected to one terminal of the capacitance C801.
  • One of the source and drain of the transistor M803 is electrically connected to one terminal of the capacitance C801.
  • the other terminal of the capacitance C801 is electrically connected to the wiring CM.
  • the other of the source and drain of the transistor M802 is electrically connected to the input terminal of the holding circuit 831 (i.e., the wiring Q).
  • the other of the source and drain of the transistor M803 is electrically connected to the output terminal of the holding circuit 831 (i.e., the wiring SD).
  • the gate of the transistor M802 is electrically connected to the wiring BK.
  • the gate of the transistor M803 is electrically connected to the wiring RV.
  • each of the holding circuits 831[1] to 831[G] the wirings through which one of the source or drain of the transistor M802, one of the source or drain of the transistor M803, and one terminal of the capacitor C801 are electrically connected to each other may be described as wirings SN[1] to SN[G].
  • each of the wirings SN[1] to SN[G] may be described as wirings SN.
  • one of the source and drain of the transistor M801 is electrically connected to the wiring SD.
  • the other of the source and drain of the transistor M801 is electrically connected to the wiring SD_IN.
  • the gate of transistor M801 is electrically connected to wiring GBK.
  • a signal that controls whether or not to perform a scan test is applied to wiring GBK.
  • OS transistors can be used as the transistors M801, M802, and M803.
  • OS transistors have a characteristic of having an extremely low off-state current. In addition, they have a characteristic that the off-state current hardly increases even in a high-temperature environment and the on-state current is not easily reduced.
  • the holding circuit 831 can hold the data written to the wiring SN for a long period of time by turning off the transistors M802 and M803.
  • the data can be held even when power is not supplied to the scan flip-flop circuit 850 due to the power gating operation.
  • the holding circuit 831 can be used as a non-volatile memory.
  • the potential of the data may change due to the parasitic capacitance of the wiring SD. Therefore, it is preferable to make the capacitance of the capacitor C801 larger than the parasitic capacitance of the wiring SD so that the amount of change in the potential of the data is smaller than, for example, the logical threshold value of the flip-flop circuit 852.
  • a configuration in which a transistor M801 is provided for each of the multiple holding circuits 831 may be used.
  • a Si transistor may be used for the transistor M801.
  • multiple layers 983 may be stacked and a backup circuit 830 may be provided in each layer 983.
  • the backup circuit 830 can be provided in the semiconductor device 810 without changing the circuit configuration and layout of the scan flip-flop circuit 850.
  • the backup circuit 830 is a highly versatile circuit.
  • the backup circuit 830 is stacked on top of the scan flip-flop circuit 850, so the distance of the wiring electrically connecting them can be shortened. This makes it possible to reduce the energy (access energy) required to save and load data. This makes it possible to reduce the power consumption of the semiconductor device 810.
  • FIG. 22 is a timing chart illustrating an example of the operation of the semiconductor device 810 shown in FIG.
  • the flip-flop circuit 852 stores data given to the input terminal Df and outputs the data from the output terminal Qf in synchronization with the timing (rising edge) at which the clock signal given to the wiring PCK switches from potential L to potential H. It is also assumed that a potential L is given to the wiring GBK. It is also assumed that a constant potential (for example, potential VSS) is given to the wiring CM.
  • the timing chart shown in FIG. 22 illustrates the state (potential H or potential L) of the signal provided to each of the wiring PCK, wiring BK[1], wiring RV[1], and wiring SE during each period of operation (periods T811 to T814). Note that wirings BK[2] to BK[4] and wirings RV[2] to RV[4] are not illustrated.
  • the diagram also illustrates the state of data provided to each of the wirings D, Q, SD, and SN[1] (any one of data D1 to D3). Note that wirings SN[2] to SN[4] are not illustrated.
  • the diagram also illustrates the state in which power is supplied to the scan flip-flop circuit 850 (Power on) or not supplied (Power off).
  • 23A to 23D are schematic diagrams showing how data is stored in the scan flip-flop circuit 850 and the holding circuits 831[1] to 831[4] of the backup circuit 830 during each period of the timing chart shown in FIG. 22.
  • the input and output of data (data flow) is shown by dashed arrows.
  • a potential L is applied to each of the wirings BK[1] to BK[4], the wirings RV[1] to RV[4], and the wiring SE.
  • the state of the data applied to each of the wirings SN[1] and SN[2] is undefined (data D1 to D3 are not shown).
  • a clock signal is applied to the wiring PCK.
  • Power is supplied to the scan flip-flop circuit 850.
  • Data D1 is stored in the scan flip-flop circuit 850. In the following description, unless otherwise specified, the previous state is maintained.
  • period T812 the power supply to the scan flip-flop circuit 850 is cut off. Then, the data D1 stored in the scan flip-flop circuit 850 disappears. At this time, the data D1 held in the wiring SN[1] of the holding circuit 831[1] is held.
  • the wiring SD is selected.
  • the data D1 applied to the wiring SD is stored in the scan flip-flop circuit 850 in synchronization with the rising edge and output to the wiring Q. After that, a potential L is applied to the wiring RV[1] and the wiring SE.
  • period T814 the clock signal provided to the wiring PCK is resumed. Also, assume that data D2 is provided to the wiring D. Then, in synchronization with the rising edge of the clock signal, the data D2 provided to the wiring D is stored in the scan flip-flop circuit 850 and output to the wiring Q.
  • the semiconductor device 810 can be operated as shown in the timing chart in FIG. 22.
  • a power gating operation is performed in the electronic computer 900, for example, when the scan flip-flop circuit 850 is powered on, it can be quickly restored to the state it was in immediately before it was powered off, shortening the time it takes to resume processing.
  • FIG. 24 is a timing chart illustrating an example of the operation of the semiconductor device 810 shown in FIG.
  • the flip-flop circuit 852 stores data given to the input terminal Df and outputs the data from the output terminal Qf in synchronization with the timing (rising edge) at which the clock signal given to the wiring PCK switches from potential L to potential H. It is also assumed that a potential L is given to the wiring GBK. It is also assumed that a constant potential (for example, potential VSS) is given to the wiring CM.
  • the timing chart shown in FIG. 24 illustrates the state (potential H or potential L) of the signal applied to each of the wiring PCK, wiring BK[1], wiring BK[2], wiring RV[1], wiring RV[2], and wiring SE during each period of operation (periods T821 to T827). Note that wirings BK[3], wiring BK[4], wiring RV[3], and wiring RV[4] are not shown. Also illustrated is the state of data (any one of data D1 to data D7) applied to each of the wirings D, wiring Q, wiring SD, wiring SN[1], and wiring SN[2]. Note that wirings SN[3] and wiring SN[4] are not shown.
  • 25A to 25G are schematic diagrams showing how data is stored in the scan flip-flop circuit 850 and the holding circuits 831[1] to 831[4] of the backup circuit 830 during each period of the timing chart shown in FIG. 24.
  • the input and output of data is shown by dashed arrows.
  • a potential L is applied to each of the wirings BK[1] to BK[4], the wirings RV[1] to RV[4], and the wiring SE.
  • the state of the data applied to each of the wirings SN[1] and SN[2] is undefined (none of the data D1 to D7 is shown). Note that in the following description, unless otherwise specified, the previous state is maintained.
  • a potential H is applied to the wiring RV[1], so that the data D2 stored in the wiring SN[1] of the holding circuit 831[1] is applied to the wiring SD.
  • data D5 is applied to the wiring D, but the wiring SD is selected by applying a potential H to the wiring SE.
  • the data D2 provided to the wiring SD is stored in the scan flip-flop circuit 850 and output to the wiring Q. Then, a potential L is provided to the wiring RV[1].
  • a potential H is applied to the wiring RV[2], so that the data D3 stored in the wiring SN[2] of the holding circuit 831[2] is applied to the wiring SD. Note that data D6 is applied to the wiring D, but the wiring SD is selected by applying a potential H to the wiring SE.
  • the data D3 provided to the wiring SD is stored in the scan flip-flop circuit 850 and output to the wiring Q. After that, a potential L is provided to the wiring RV[2], and a potential L is provided to the wiring SE.
  • the semiconductor device 810 can be operated as shown in the timing chart in FIG. 24.
  • the electronic computer 900 when it performs processing while switching between multiple tasks, for example, it can be configured to save data of an interrupted task and load data of a task to be resumed.
  • the power consumption of the electronic computer 900 can be reduced.
  • the OS transistor is a semiconductor element having three terminals, a gate, a source, and a drain, in the above description.
  • the OS transistor may be a semiconductor element having four terminals.
  • the on-resistance can be reduced (on-current can be increased) by applying the same potential as the gate to the back gate.
  • applying the same potential as the source to the back gate makes it difficult for an electric field generated outside the transistor to act on the channel formation region, so that the electrical characteristics can be stabilized and the reliability can be improved.
  • the threshold voltage can be changed by applying an arbitrary potential to the back gate.
  • the current flowing between the source and the drain can be independently controlled depending on the potentials applied to the gate and the back gate.
  • a rise time and a fall time may occur due to, for example, a load (parasitic capacitance and parasitic resistance) such as wiring.
  • the time is, for example, more than 0 seconds and less than 1000 nanoseconds, less than 100 nanoseconds, less than 10 nanoseconds, or less than 1 nanosecond.
  • the time difference is, for example, more than 0 seconds and less than 1000 nanoseconds, less than 100 nanoseconds, less than 10 nanoseconds, or less than 1 nanosecond.
  • the potential H or potential L applied to each of the multiple wirings does not have to be the same potential for each wiring.
  • the potential may be different for each wiring.
  • the potential H or potential L applied to each wiring may include, for example, a decrease in potential due to the threshold voltage of the transistor.
  • each period is shown to have the same length in the timing chart, the length of each period may be different. In other words, the length of each period can be set appropriately when actually operating the semiconductor device.
  • Embodiment 5 electronic components, electronic devices, large scale computers, space equipment, and data centers (also referred to as data centers (DCs)) that can use the memory devices described in the above embodiments will be described.
  • the electronic components, electronic devices, large scale computers, space equipment, and data centers that use the memory devices of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.
  • FIG. 26A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 709 is mounted.
  • the electronic component 709 shown in FIG. 26A has a memory device 710 in a mold 711. In FIG. 26A, some parts are omitted in order to show the inside of the electronic component 709.
  • the electronic component 709 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the memory device 710 via wires 714.
  • the electronic component 709 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the memory device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking multiple memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding.
  • TSV Through Silicon Via
  • a bonding technology such as Cu-Cu direct bonding.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked.
  • OS transistors By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve either or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.
  • the memory device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple memory devices 710 provided on interposer 731.
  • the memory device 710 is used as a high bandwidth memory (HBM).
  • the semiconductor device 735 can be an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV may be used as the through electrode.
  • the interposer on which the HBM is mounted is required to have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.
  • silicon interposers Furthermore, in SiP and MCM using silicon interposers, deterioration of reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 26B shows an example in which the electrodes 733 are formed of solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be realized.
  • the electrodes 733 may also be formed of conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be realized.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • FIG. 27A a perspective view of an electronic device 6500 is shown in FIG. 27A.
  • the electronic device 6500 shown in FIG. 27A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the storage device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • the electronic device 6600 shown in FIG. 27B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, a control device 6616, and the like.
  • the control device 6616 includes, for example, one or more of a CPU, a GPU, and a storage device.
  • the storage device of one embodiment of the present invention can be applied to the display unit 6615, the control device 6616, and the like. Note that the use of the storage device of one embodiment of the present invention for the above-described control device 6509 and the control device 6616 is preferable because power consumption can be reduced.
  • Fig. 27C shows a perspective view of the large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 27C has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • the computer 5620 can have, for example, the configuration shown in the perspective view in FIG. 27D.
  • the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 27E is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 27E illustrates semiconductor devices other than the semiconductor devices 5626, 5627, and 5628, but for those semiconductor devices, please refer to the description of the semiconductor devices 5626, 5627, and 5628 described below.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected to the terminals by, for example, reflow soldering to wiring provided on the board 5622.
  • Examples of the semiconductor device 5628 include a memory device.
  • the electronic component 709 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the memory device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing information.
  • the memory device of one embodiment of the present invention can include an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in outer space.
  • Figure 28 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown as an example of outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the above-mentioned battery management system or battery control circuit is preferable because it has low power consumption and high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the control device 6807 is preferably a storage device according to one embodiment of the present invention.
  • an OS transistor Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, the OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is given as an example of space equipment, but the present invention is not limited to this.
  • a storage device according to one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, or a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the storage device can be suitably used in a storage system applied to, for example, a data center.
  • the data center is required to perform long-term management of data, such as ensuring the immutability of the data.
  • long-term management of data such as ensuring the immutability of the data.
  • it is necessary to increase the size of the building, such as by installing storage and servers for storing a huge amount of data, by securing a stable power source for storing the data, or by securing cooling equipment required for storing the data.
  • a storage device By using a storage device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the storage device that stores the data. This makes it possible to miniaturize the storage system, the power source for storing data, and the cooling equipment. This makes it possible to save space in the data center.
  • the memory device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the memory device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.
  • Figure 29 shows a storage system applicable to a data center.
  • the storage system 7000 shown in Figure 29 has multiple servers 7001sb as hosts 7001 (illustrated as Host Computer). It also has multiple storage devices 7003md as storage 7003 (illustrated as Storage).
  • the host 7001 and storage 7003 are shown connected via a storage area network 7004 (illustrated as SAN: Storage Area Network) and a storage control circuit 7002 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 7001 corresponds to a computer that accesses data stored in the storage 7003.
  • the hosts 7001 may be connected to each other via a network.
  • Storage 7003 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • storage systems usually provide cache memory within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003, and then output to the host 7001 or the storage 7003.
  • OS transistors as transistors for storing data in the above-mentioned cache memory and configuring them to hold a potential corresponding to the data, it is possible to reduce the frequency of refreshing and reduce power consumption.
  • configuring the memory cell array in a stacked manner it is possible to reduce the size.
  • the application of the memory device of one embodiment of the present invention to one or more selected from electronic components, electronic devices, mainframes, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the performance or integration of memory devices, the use of the memory device of one embodiment of the present invention can reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the memory device of one embodiment of the present invention is also effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases

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Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2011151383A (ja) * 2009-12-25 2011-08-04 Semiconductor Energy Lab Co Ltd 半導体装置
JP2013211537A (ja) * 2012-02-29 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2020123612A (ja) * 2019-01-29 2020-08-13 株式会社半導体エネルギー研究所 半導体装置の製造方法、半導体装置の製造装置

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Publication number Priority date Publication date Assignee Title
JP2011151383A (ja) * 2009-12-25 2011-08-04 Semiconductor Energy Lab Co Ltd 半導体装置
JP2013211537A (ja) * 2012-02-29 2013-10-10 Semiconductor Energy Lab Co Ltd 半導体装置
JP2016149552A (ja) * 2015-02-11 2016-08-18 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法
JP2020123612A (ja) * 2019-01-29 2020-08-13 株式会社半導体エネルギー研究所 半導体装置の製造方法、半導体装置の製造装置

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