WO2024171007A1 - 半導体装置、および表示装置 - Google Patents

半導体装置、および表示装置 Download PDF

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Publication number
WO2024171007A1
WO2024171007A1 PCT/IB2024/051188 IB2024051188W WO2024171007A1 WO 2024171007 A1 WO2024171007 A1 WO 2024171007A1 IB 2024051188 W IB2024051188 W IB 2024051188W WO 2024171007 A1 WO2024171007 A1 WO 2024171007A1
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WIPO (PCT)
Prior art keywords
transistor
wiring
potential
semiconductor device
electrically connected
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Ceased
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PCT/IB2024/051188
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English (en)
French (fr)
Japanese (ja)
Inventor
木村肇
小林英智
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2025500417A priority Critical patent/JPWO2024171007A1/ja
Publication of WO2024171007A1 publication Critical patent/WO2024171007A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals

Definitions

  • One aspect of the present invention relates to a semiconductor device and a display device.
  • one aspect of the present invention is not limited to the above technical fields.
  • the technical field of one aspect of the invention disclosed in this specification relates to an object, a method, a driving method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, manufacture, or a composition of matter.
  • examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic devices, control devices, memory devices, input devices, output devices, input/output devices, signal processing devices, arithmetic processing devices, electronic computers, electronic devices, driving methods thereof, or manufacturing methods thereof.
  • Examples of display devices that can be used include liquid crystal display devices and light-emitting devices equipped with light-emitting elements such as organic electroluminescence (EL) elements (also called OLEDs (organic light-emitting diodes)) or light-emitting diodes (LEDs: light-emitting diodes).
  • EL organic electroluminescence
  • LEDs light-emitting diodes
  • a source follower circuit is an analog circuit for outputting an output voltage according to an input voltage.
  • a bias current flows in a transistor to which a bias voltage is applied, thereby obtaining an output voltage according to the input voltage (see, for example, Patent Document 1 and Patent Document 2).
  • bias current flows through a transistor to which a bias voltage is applied, resulting in high power consumption.
  • One embodiment of the present invention has an object to provide a high-definition semiconductor device or display device. Alternatively, one embodiment of the present invention has an object to provide a miniaturized semiconductor device or display device. Alternatively, one embodiment of the present invention has an object to provide a semiconductor device or display device with improved display quality. Alternatively, one embodiment of the present invention has an object to provide a semiconductor device or display device with increased operating speed. Alternatively, one embodiment of the present invention has an object to provide a semiconductor device or display device with reduced power consumption. Alternatively, one embodiment of the present invention has an object to provide a highly reliable semiconductor device or display device. Alternatively, one embodiment of the present invention has an object to provide a novel semiconductor device or display device.
  • one embodiment of the present invention has an object to provide a method for driving a semiconductor device or a method for driving a display device that can improve display quality.
  • one embodiment of the present invention has an object to provide a method for driving a semiconductor device or a display device that can increase the operating speed.
  • one embodiment of the present invention has an object to provide a method for driving a semiconductor device or a display device that can reduce power consumption.
  • one object of one embodiment of the present invention is to provide a method for driving a semiconductor device or a display device that can improve reliability.
  • one object of one embodiment of the present invention is to provide a novel method for driving a semiconductor device or a display device.
  • One aspect of the present invention is a semiconductor device having a first transistor, a first switch, a second switch, and a signal line, where the first transistor has a function of providing an output voltage to the signal line via the first switch according to an input voltage provided to the gate, the second switch has a function of performing an initialization operation to initialize the potential of the signal line, and the first switch has a function of performing a signal output operation to provide an output voltage to the signal line.
  • One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a first switch, a second switch, a first power supply line, a second power supply line, and a signal line
  • the first transistor has a function of providing an output voltage to the signal line via the first switch according to an input voltage provided to the gate
  • one of the source and drain of the first transistor is electrically connected to the first power supply line
  • one of the source and drain of the second transistor is electrically connected to the other of the source and drain of the first transistor
  • the gate and the other of the source and drain of the second transistor are electrically connected to the second power supply line
  • the second switch has a function of performing an initialization operation to initialize the potential of the signal line
  • the first switch has a function of performing a signal output operation to provide an output voltage to the signal line following the initialization operation.
  • One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a first switch, a second switch, a first power supply line, a second power supply line, and a signal line
  • the first transistor has a function of providing an output voltage to the signal line via the first switch according to an input voltage provided to the gate
  • one of the source and drain of the first transistor is electrically connected to the first power supply line
  • one of the source and drain of the second transistor is electrically connected to the other of the source and drain of the first transistor
  • the other of the source and drain of the second transistor is electrically connected to the second power supply line
  • the gate of the second transistor is electrically connected to a first capacitor that holds the threshold voltage of the second transistor
  • the second switch has a function of performing an initialization operation to initialize the potential of the signal line
  • the first switch has a function of performing a signal output operation to provide an output voltage to the signal line following the initialization operation.
  • a semiconductor device in which the gate of the first transistor is electrically connected to one electrode of a second capacitor that holds the threshold voltage of the first transistor, and the wiring that provides the input voltage is electrically connected to the other electrode of the second capacitor.
  • the first transistor and the second transistor each preferably have a semiconductor layer, and the semiconductor layer preferably has an oxide semiconductor.
  • a semiconductor device in which at least a portion of the semiconductor layer is provided inside an opening formed in the insulating layer is preferred.
  • One aspect of the present invention is a display device having the semiconductor device of the above aspect of the present invention and a pixel, the pixel having a third transistor, and one of the source and drain of the third transistor being electrically connected to a signal line.
  • the third transistor preferably has a semiconductor layer, and the semiconductor layer preferably includes an oxide semiconductor.
  • a display device in which at least a portion of the semiconductor layer is provided inside an opening formed in the insulating layer is preferred.
  • One embodiment of the present invention can provide a high-definition semiconductor device or display device. Alternatively, one embodiment of the present invention can provide a miniaturized semiconductor device or display device. Alternatively, one embodiment of the present invention can provide a semiconductor device or display device with improved display quality. Alternatively, one embodiment of the present invention can provide a semiconductor device or display device with increased operating speed. Alternatively, one embodiment of the present invention can provide a semiconductor device or display device with reduced power consumption. Alternatively, one embodiment of the present invention can provide a highly reliable semiconductor device or display device. Alternatively, one embodiment of the present invention can provide a novel semiconductor device or display device. Alternatively, one embodiment of the present invention can provide a method for driving a semiconductor device or a display device with improved display quality.
  • one embodiment of the present invention can provide a method for driving a semiconductor device or a display device with increased operating speed.
  • one embodiment of the present invention can provide a method for driving a semiconductor device or a display device with reduced power consumption.
  • one embodiment of the present invention can provide a method for driving a semiconductor device or a display device with improved reliability.
  • 1A to 1C are circuit diagrams illustrating a semiconductor device.
  • 2A and 2B are circuit diagrams illustrating a semiconductor device.
  • 3A to 3C are circuit diagrams illustrating a semiconductor device.
  • 4A to 4C are circuit diagrams illustrating a semiconductor device.
  • 5A to 5C are circuit diagrams illustrating a semiconductor device.
  • 6A and 6B are circuit diagrams illustrating a semiconductor device.
  • FIG. 7 is a circuit diagram illustrating a semiconductor device.
  • 8A to 8C are circuit diagrams illustrating a semiconductor device.
  • 9A to 9C are circuit diagrams and layout diagrams illustrating a semiconductor device.
  • 10A and 10B are circuit diagrams illustrating a semiconductor device.
  • 11A and 11B are circuit diagrams illustrating a semiconductor device.
  • FIG. 12A and 12B are a layout diagram and a cross-sectional view illustrating a semiconductor device.
  • FIG. 13 is a circuit diagram illustrating a semiconductor device.
  • 14A and 14B are circuit diagrams illustrating a semiconductor device.
  • 15A and 15B are circuit diagrams illustrating a semiconductor device.
  • 16A and 16B are circuit diagrams illustrating a semiconductor device.
  • 17A and 17B are circuit diagrams illustrating a semiconductor device.
  • FIG. 18 is a layout diagram illustrating a semiconductor device.
  • 19A and 19B are circuit diagrams illustrating a semiconductor device.
  • 20A and 20B are circuit diagrams illustrating a semiconductor device.
  • 21A and 21B are circuit diagrams illustrating a semiconductor device.
  • 22A and 22B are a layout diagram and a cross-sectional view illustrating a semiconductor device.
  • FIG. 23 is a circuit diagram illustrating a semiconductor device.
  • 24A and 24B are circuit diagrams illustrating a semiconductor device.
  • 25A and 25B are circuit diagrams illustrating a semiconductor device.
  • 26A and 26B are circuit diagrams illustrating a semiconductor device.
  • 27A and 27B are circuit diagrams illustrating a semiconductor device.
  • 28A and 28B are circuit diagrams illustrating a semiconductor device.
  • 29A and 29B are circuit diagrams illustrating a semiconductor device.
  • 30A and 30B are circuit diagrams illustrating a semiconductor device.
  • 31A to 31E are block diagrams showing configuration examples of the display device.
  • FIG. 32 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 33 is a timing chart showing an example of the operation of the semiconductor device.
  • FIG. 32 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 33 is a timing chart showing an example of the operation of the semiconductor device.
  • FIG. 32 is a circuit diagram
  • FIG. 34 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 35 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 36 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 37 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 38 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 39 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 40 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 41 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 42 is a circuit diagram illustrating a semiconductor device.
  • FIG. 43 is a circuit diagram illustrating a semiconductor device.
  • 44A to 44C and 44E are circuit diagrams showing a configuration example of a semiconductor device, and Fig. 44D is a timing chart showing an operation example of the semiconductor device.
  • 45A to 45C and 45E are circuit diagrams showing a configuration example of a semiconductor device, and Fig. 45D is a timing chart showing an operation example of the semiconductor device.
  • 46A to 46C are circuit diagrams showing configuration examples of a semiconductor device.
  • FIG. 47 is a circuit diagram showing a configuration example of a semiconductor device.
  • 48A to 48C and 48E are circuit diagrams showing a configuration example of a semiconductor device, and Fig. 48D is a timing chart showing an operation example of the semiconductor device.
  • FIG. 49 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 50A to 50F are circuit diagrams showing configuration examples of a semiconductor device.
  • FIG. 51 is a timing chart showing an example of the operation of the semiconductor device.
  • 52A to 52C are circuit diagrams showing configuration examples of a semiconductor device.
  • Fig. 53A is a top view showing a configuration example of a semiconductor device, and Fig. 53B and Fig. 53C are cross-sectional views showing the configuration example of a semiconductor device.
  • 54A is a top view showing a configuration example of a semiconductor device, and FIG 54B is a cross-sectional view showing the configuration example of a semiconductor device.
  • Fig. 55A is a top view showing a configuration example of a semiconductor device, and Fig. 55B and Fig.
  • FIG. 55C are cross-sectional views showing the configuration example of a semiconductor device.
  • FIG. 56 is a cross-sectional view showing a configuration example of a semiconductor device.
  • 57A and 57B are cross-sectional views showing a configuration example of a semiconductor device.
  • 58A and 58B are cross-sectional views showing a configuration example of a semiconductor device.
  • 59A and 59B are cross-sectional views showing a configuration example of a semiconductor device.
  • 60A and 60B are circuit diagrams showing a configuration example of a semiconductor device
  • Fig. 60C is a top view showing the configuration example of a semiconductor device.
  • FIG. 61 is a cross-sectional view showing a configuration example of a semiconductor device.
  • FIG. 62A and 62B are circuit diagrams showing a configuration example of a semiconductor device, and Fig. 62C is a top view showing a configuration example of a semiconductor device.
  • FIG. 63 is a cross-sectional view showing a configuration example of a semiconductor device.
  • Fig. 64A is a perspective view showing a configuration example of a display device, and Fig. 64B to Fig. 64F are top views showing an example of a pixel arrangement.
  • 65A and 65B are cross-sectional views showing a configuration example of a display device.
  • 66A and 66B are cross-sectional views showing a configuration example of a display device.
  • 67A to 67D are diagrams showing an example of an electronic device.
  • 68A to 68F are diagrams showing an example of an electronic device.
  • 69A to 69G are diagrams showing an example of an electronic device.
  • a semiconductor device is a device that utilizes semiconductor characteristics, such as a circuit including a semiconductor element (e.g., a transistor or a diode) or a device having such a circuit. It also refers to any device that can function by utilizing semiconductor characteristics.
  • a semiconductor element e.g., a transistor or a diode
  • an integrated circuit including a semiconductor element, a chip equipped with an integrated circuit, an electronic component in which a chip is housed in a package, or an electronic device equipped with an electronic component are examples of semiconductor devices.
  • display devices for example, display devices, light-emitting devices, power storage devices, optical devices, imaging devices, lighting devices, arithmetic devices, control devices, memory devices, input devices, output devices, input/output devices, signal processing devices, electronic computers, or electronic devices may themselves be semiconductor devices and may have semiconductor devices.
  • the size, layer thickness, or area may be exaggerated for clarity.
  • the drawings are not limited to, for example, their size or aspect ratio.
  • the drawings are schematic representations of ideal examples, and are not limited to, for example, the shapes or values shown in the drawings.
  • layers or resist masks may be unintentionally thinned by processes such as etching, but this may not be reflected in the drawings to facilitate understanding.
  • variations in voltage or current may occur due to noise or timing deviations, but this may not be reflected in the drawings to facilitate understanding.
  • the components of the present invention may be classified by function and shown as independent elements.
  • the elements shown in this specification and drawings, etc. are not limited to the explanations therein, and may be rephrased appropriately depending on the situation.
  • an identifying symbol such as "A”, “b”, “_1”, “[n]”, or “[m, n]” may be added to the reference numeral.
  • the identifying symbol may not be added.
  • the "conductive state” or “on state” of a transistor refers to, for example, a state in which the source and drain of the transistor can be regarded as being electrically short-circuited, or a state in which a current can flow between the source and drain.
  • a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage may be referred to as the "conductive state” or "on state”.
  • non-conductive state refers to a state in which the source and drain of the transistor can be regarded as being electrically cut off.
  • a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage may be referred to as the "non-conductive state", “cut-off state”, or "off state”.
  • the voltage between the gate and source may be referred to as the "gate voltage”
  • the voltage between the drain and source may be referred to as the “drain voltage”
  • the voltage between the backgate and source may be referred to as the “backgate voltage”.
  • the current flowing from the drain to the source may be referred to as the "drain current”.
  • the "off current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification, the off current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may be referred to as leakage current.
  • FIG. 1A is a block diagram illustrating a configuration example of a display device including a semiconductor device.
  • a display device 40 shown in FIG. 1A includes a display portion 42 and a driver circuit portion 44.
  • the display portion 42 includes a plurality of pixels 41 electrically connected to wirings DL (wirings DL_1 to DL_n (n is an integer of 2 or more)).
  • the driver circuit portion 44 includes a semiconductor device 60. Note that the wirings DL may be referred to as signal lines.
  • a data potential is applied from the drive circuit unit 44 to the pixels 41 via the wiring DL, whereby light emission according to the data potential is controlled and an image is displayed on the display unit 42.
  • the drive circuit unit 44, the display device 40, and the pixels 41 will be described later.
  • the semiconductor device 60 is an analog circuit for outputting an output voltage according to an input voltage Vin (Vin_1 to Vin_n) to the wirings DL_1 to DL_n of each row (or each column). As shown in FIG. 1B, the semiconductor device 60 can be represented as a circuit block that outputs an input voltage applied to an input terminal IN from an output terminal OUT.
  • FIG. 1C is a circuit diagram illustrating an example configuration of semiconductor device 60.
  • Semiconductor device 60 has a transistor M01, a switch S01, and a switch S02.
  • the gate of the transistor M01 is electrically connected to a wiring that provides an input voltage Vin to the input terminal IN.
  • One of the source and drain of the transistor M01 is electrically connected to a wiring VLD.
  • the other of the source and drain of the transistor M01 is electrically connected to a first terminal of the switch S01.
  • the second terminal of the switch S01 is electrically connected to a first terminal of the switch S02 and a wiring DL.
  • the second terminal of the switch S02 is electrically connected to a wiring VLS.
  • the wiring VLD is a wiring that supplies a potential VDD (potential H) to an element such as a transistor.
  • the wiring VLD is also called a first power supply line.
  • the wiring VLS is a wiring that supplies a potential VSS (potential L) to an element such as a transistor.
  • the wiring VLS is also called a second power supply line. The following description assumes that the potential VDD is a potential that is sufficiently higher than the potential VSS and is higher than the threshold voltage of the transistor in the semiconductor device 60.
  • Transistor M01 has a function of providing an output voltage Vout corresponding to an input voltage Vin applied to its gate to wiring DL via switch S01.
  • Transistor M01 functions as a source follower circuit in which the gate of transistor M01 is the input and the source of transistor M01 is the output. Note that in this specification, a transistor having a function similar to that of transistor M01 may be referred to as a "drive transistor.”
  • the semiconductor device 60 having the transistor M01 can reduce the output impedance, thereby shortening the time it takes for the potential of the wiring DL to change in response to changes in the potential of the input voltage Vin, even when the load (parasitic capacitance) of the wiring DL is large. In other words, the semiconductor device 60 has an impedance conversion function.
  • Switches S01 and S02 can be transistors, similar to transistor M01. By using transistors as switches S01 and S02, switches S01 and S02 can be manufactured through the same process as transistor M01. Note that switches other than switches S01 and S02 may also be transistors.
  • the transistors (e.g., transistor M01) constituting the semiconductor device 60 are enhancement type (normally off type) n-channel transistors unless otherwise specified. Therefore, their threshold voltages are greater than 0 V.
  • the semiconductor device 60 can be configured using various transistors.
  • some or all of the transistors constituting the semiconductor device 60 may be p-channel transistors.
  • transistors constituting the semiconductor device 60 transistors containing various semiconductors can be used.
  • a transistor containing a single crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor in a channel formation region can be used.
  • the semiconductor is not limited to a single semiconductor whose main component is composed of a single element (such as silicon or germanium), but can be, for example, a compound semiconductor (such as silicon germanium or gallium arsenide), an oxide semiconductor, or the like.
  • transistors that make up the semiconductor device 60 can be used as the transistors that make up the semiconductor device 60.
  • MOS type field effect transistors can be used.
  • transistors constituting the semiconductor device 60 transistors of various structures can be used.
  • transistors of various structures such as planar type, staggered type, FIN type, TRI-GATE type, top gate type, bottom gate type, or dual gate type (structure in which gates are arranged on both sides (e.g., above and below) of a channel formation region) can be used.
  • transistors constituting the semiconductor device 60 it is preferable to use vertical transistors (transistors in which at least a part of a semiconductor layer including a channel formation region is provided along the side of an insulating layer in an opening formed in the insulating layer).
  • the source electrode and drain electrode are located at different heights, so current flows in the height direction (vertical direction) in the channel formation region of the semiconductor layer.
  • the channel length direction has a height direction (vertical direction) component. Therefore, the above-mentioned vertical transistor can also be called a VFET (Vertical Field Effect Transistor), vertical channel transistor, vertical channel transistor, or vertical transistor.
  • VFET Vertical Field Effect Transistor
  • Vertical transistors have a structure in which the source region, the channel formation region, and the drain region can at least partially overlap when viewed from above, so that the area they occupy (also called the footprint) can be made small.
  • the structure allows the channel length to be small and the channel width to be large, the on-resistance can be made small (the on-current can be made large).
  • the source electrode and the drain electrode can be located at the same height, and current can flow in the circumferential (horizontal) direction in the channel formation region of the semiconductor layer.
  • the channel width direction can have a height (vertical) component.
  • a transistor with such a configuration can be called a VLFET (Vertical Lateral Field Effect Transistor). Since the VLFET has a structure that can reduce the occupied area while increasing the channel length, it can reduce short channel effects such as drain induced barrier lowering (DIBL).
  • DIBL drain induced barrier lowering
  • vertical transistors are preferably used as some or all of the transistors constituting the semiconductor device 60.
  • vertical transistors are preferably used as transistors that function as switches (e.g., switches S01 and S02).
  • a transistor with high saturation should be used as the drive transistor (e.g., transistor M01).
  • the drive transistor e.g., transistor M01
  • a transistor with a long channel length should be used.
  • the above-mentioned VLFET may be used.
  • an OS transistor (a transistor that includes an oxide semiconductor in a channel formation region) may be used as a transistor that constitutes the semiconductor device 60.
  • the OS transistor has a characteristic of having an extremely low off-state current because the band gap of the oxide semiconductor in which the channel is formed is 2 eV or more.
  • the off-state current value of the OS transistor per 1 ⁇ m of channel width at room temperature can be 1 aA (1 ⁇ 10 ⁇ 18 A) or less, 1 zA (1 ⁇ 10 ⁇ 21 A) or less, or 1 yA (1 ⁇ 10 ⁇ 24 A) or less.
  • the off-state current value of a Si transistor (a transistor containing silicon in a channel formation region) per 1 ⁇ m of channel width at room temperature is 1 fA (1 ⁇ 10 ⁇ 15 A) or more and 1 pA (1 ⁇ 10 ⁇ 12 A) or less. Therefore, it can be said that the off-state current of an OS transistor is about 10 orders of magnitude lower than that of a Si transistor.
  • the charge accumulated in a capacitor and a wiring having a parasitic capacitor can be held for a long period of time.
  • the potential of the wiring DL can be held for a long period of time. Therefore, the power consumption of the semiconductor device can be reduced.
  • the off-current of an OS transistor hardly increases even in a high-temperature environment. Specifically, the off-current hardly increases even in an environment of room temperature or higher and 200° C. or lower. Furthermore, the on-current of an OS transistor is unlikely to decrease even in a high-temperature environment.
  • the on-current of a Si transistor decreases in a high-temperature environment. That is, the on-current of an OS transistor is higher than that of a Si transistor in a high-temperature environment.
  • an OS transistor can perform a good switching operation even in an environment of 125° C. or higher and 150° C. or lower because the ratio of the on-current to the off-current is large. Therefore, a semiconductor device using an OS transistor can operate stably and with high reliability even in a high-temperature environment. That is, by using an OS transistor as a transistor constituting the semiconductor device 60, the reliability of the semiconductor device can be improved.
  • OS transistors have a high withstand voltage between the source and drain (also referred to as drain withstand voltage). Therefore, a semiconductor device using an OS transistor can operate stably even when driven at a high voltage, and can achieve high reliability. That is, for example, by using an OS transistor as transistor M01 among the transistors constituting the semiconductor device 60, the operation of the semiconductor device 60 can be stabilized even when the potential difference (voltage) between the potential VDD and the potential VSS is large. Therefore, the reliability of the semiconductor device can be improved.
  • one embodiment of the present invention is not limited to a configuration in which an OS transistor is used as the semiconductor device 60, and may be a configuration in which multiple types of transistors containing different semiconductor materials are used.
  • the semiconductor device 60 may be configured with a transistor (LTPS transistor) containing low temperature polysilicon (LTPS) in the channel formation region, and an OS transistor.
  • the LTPS transistor has high field-effect mobility and good frequency characteristics.
  • a configuration in which an LTPS transistor and an OS transistor are combined may be referred to as LTPO.
  • OS transistors can be used for the transistors functioning as switches S01 and S02
  • an LTPS transistor can be used for the driving transistor (transistor M01).
  • the transistors may be provided in different layers for each type of transistor.
  • the semiconductor device 60 is configured with Si transistors and OS transistors
  • a layer containing the Si transistors and a layer containing the OS transistors may be stacked. With such a configuration, the area occupied by the semiconductor device 60 can be reduced.
  • vertical OS transistors may be used as the transistors functioning as switches S01 and S02, and a dual-gate OS transistor may be used as the driver transistor (transistor M01).
  • a driver transistor transistor M01
  • the semiconductor device 60 performs an initialization operation T01, an initialization ending operation T02, and a signal output operation T03 during a period TSEL during which the semiconductor device 60 outputs an output voltage corresponding to the input voltage Vin.
  • the semiconductor device 60 may omit the initialization ending operation T02 as shown in Fig. 2B.
  • the time required for the initialization operation T01 and the signal output operation T03 can be set long, and therefore a stable output voltage can be obtained.
  • FIG. 3A is a circuit diagram for explaining the initialization operation T01.
  • the initialization operation T01 the potential of the wiring DL is initialized.
  • the initialization operation T01 is performed with the switch S01 in a non-conducting state (OFF) and the switch S02 in a conducting state (ON).
  • the switch S02 has a function of performing the initialization operation to initialize the potential of the wiring DL by being in a conducting state.
  • the switch S01 is in a non-conducting state, so the output voltage Vout (the voltage on the first terminal side of the switch S01) corresponding to the input voltage Vin does not change.
  • the switch S02 is turned on, so that the potential of the wiring DL can be set to the potential VSS.
  • the initialization operation T01 will be described as an operation for discharging the charge of the wiring DL. Note that the initialization operation is sometimes called a discharging operation.
  • the potential of the wiring DL changes depending on the current I that flows through the switch S02.
  • a transistor can be used for the switch S02, similar to the transistor M01. The same applies to the switch S01.
  • switch S02 is a transistor
  • a bias voltage may be applied to the gate of the transistor so that a bias current flows.
  • the transistor may be operated by switching between allowing or not allowing a bias current to flow, depending on whether or not a bias voltage is applied.
  • FIG. 3B is a circuit diagram for explaining the initialization end operation T02.
  • both switches S01 and S02 are in a non-conducting state (OFF).
  • the potential VSS of the wiring DL set in the initialization operation T01 is maintained.
  • FIG. 3C is a circuit diagram for explaining the signal output operation T03.
  • a current flows through the transistor M01 by turning the switch S01 on (ON).
  • the wiring DL becomes the output voltage Vout.
  • the switch S01 When the switch S01 is turned on, it has the function of performing a signal output operation that provides the output voltage Vout to the wiring DL.
  • Vout When the output voltage Vout becomes Vin-Vth, a voltage equal to or lower than Vth, which corresponds to the threshold voltage of transistor M01, is applied between the gate and source of transistor M01, causing a subthreshold current to flow between the source and drain.
  • the period TSEL during which the output voltage according to the input voltage Vin is output may end before the output voltage Vout increases to Vin-Vth (see FIG. 4B). In this case, the output voltage Vout becomes Vin-Vth- ⁇ ( ⁇ >0), which is smaller than Vin-Vth.
  • the output voltage Vout can rise to Vin-Vth. Since a voltage equal to or lower than Vth, which corresponds to the threshold voltage of the transistor M01, is applied between the gate and source of the transistor M01, a subthreshold current flows between the source and drain. Since a subthreshold current flows through the transistor M01, the output voltage Vout may continue to rise until the end of the period TSEL (see FIG. 4C). In this case, the output voltage Vout becomes Vin-Vth+ ⁇ ( ⁇ >0), which is larger than Vin-Vth.
  • One aspect of the present invention reduces power consumption by blocking or reducing the bias current flowing through a source follower circuit. Specifically, the number of transistors to which a bias voltage is applied is reduced, and the steady flow of bias current is suppressed, thereby reducing power consumption. If the bias current does not flow steadily, it may take some time (also called the settling time) until the output voltage according to the input voltage stabilizes. In particular, the settling time may be long when changing the voltage of the signal line in a decreasing direction.
  • the conductive state of the switch is changed over to perform an initialization operation and then a signal output operation.
  • charging to a desired voltage by the signal output operation can be performed in a state where the voltage of the signal line is lowered before the signal output operation is performed. Therefore, when inputting an input voltage, even if the voltage of the signal line is changed in a lowering direction, it can be changed to a desired voltage.
  • a vertical transistor in order to reduce the settling time, it is preferable to use a vertical transistor as the driving transistor.
  • the footprint of the driving transistor can be reduced, and the channel length and channel width can be increased.
  • a vertical driving transistor can reduce the on-resistance (increase the on-current), but consumes more power. Therefore, by combining it with the above-described configuration in which a signal output operation is performed after the initialization operation, it is possible to improve the operating speed of a display device having a semiconductor device while suppressing increases in the area occupied by the semiconductor device and power consumption.
  • one aspect of the present invention is not limited to the configuration example of the semiconductor device 60 described above.
  • Figs. 5A to 5C modified examples of the semiconductor device 60 described above are described.
  • the switch S01 may be located in the path between the wiring VLD and the wiring DL.
  • a switch having the function of the switch S01 may be provided between the drain side of the transistor M01 and the wiring VLD.
  • the switch S01 in the semiconductor device 60 shown in FIG. 1C may be omitted in cases where the period required for the initialization operation is short.
  • the semiconductor device 60A shown in FIG. 5A is a modified example of the semiconductor device 60 shown in FIG. 1C in which the switch S01 in the semiconductor device 60 shown in FIG. 1C is omitted and a new switch S03 is added.
  • the semiconductor device 60B shown in FIG. 5B is a modified example of the semiconductor device 60 shown in FIG. 1C in which a switch S03 is added to the semiconductor device 60 shown in FIG. 1C.
  • the semiconductor device 60C shown in FIG. 5C is a modified example of the semiconductor device 60 shown in FIG. 1C in which the switch S01 in the semiconductor device 60 shown in FIG. 1C is omitted.
  • the arrangement of switch S01 and the number of switches having the function of switch S01 can be changed as appropriate.
  • the arrangement of switch S01 it is possible to increase the degree of freedom in design.
  • by increasing the number of switches it is possible to further reduce the current flowing through transistor M01 during the initialization operation.
  • the display section 42 and the drive circuit section 44 may be arranged so as to overlap each other.
  • the display section 42 having the pixels 41 may be provided on a layer above the layer on which the drive circuit section 44 having the semiconductor device 60 is provided.
  • the transistors in the display unit 42 and the transistors in the drive circuit unit 44 can be arranged in different layers. Therefore, transistors with different structures can be applied to the transistors in the display unit 42 or the transistors in the drive circuit unit 44.
  • connection distance (wiring length) between the pixels 41 of the display section 42 and the semiconductor device 60 of the drive circuit section 44 can be made extremely short.
  • the wiring resistance and parasitic capacitance of the wiring DL are reduced, so the time required for charging and discharging is shortened, and high-speed driving can be achieved. Also, power consumption can be reduced. Also, miniaturization and weight reduction can be achieved.
  • FIG. 6B shows a configuration example of a semiconductor device 60_p in which a p-channel transistor is used for the transistor M01.
  • the potential of each wiring may be set so that the high and low potentials are inverted.
  • the wiring DL that is discharged via the switch S02 in FIG. 1C may be configured to be charged by the wiring VLD in FIG. 6B.
  • FIG. 7 is a circuit diagram illustrating an example of the configuration of semiconductor device 60D.
  • Semiconductor device 60D has transistor M02 in addition to transistor M01, switch S01, and switch S02. Note that the explanations of transistor M01, switch S01, and switch S02 in semiconductor device 60D overlap with the explanation of semiconductor device 60 described above, and therefore may be omitted.
  • the gate of the transistor M02 is electrically connected to the wiring VLS.
  • One of the source and drain of the transistor M02 is electrically connected to the other of the source and drain of the transistor M01 and the first terminal of the switch S01.
  • the other of the source and drain of the transistor M02 is electrically connected to the wiring VLS.
  • transistor M02 Because the gate and source voltages of transistor M02 are equipotential, that is, 0 V is applied as the gate-source voltage Vgs, a subthreshold current flows between the source and drain. Transistor M02 functions as a current source that passes subthreshold current. The subthreshold current that flows through transistor M02 is much smaller than the current that flows through transistor M01 when charging line DL.
  • a transistor that functions like transistor M02 may be called a "load transistor.” Note that transistor M02 that functions as a load transistor may be replaced with, for example, a resistive element.
  • the description of the drive transistor can be referred to as an example of the configuration of the load transistor (transistor M02).
  • a transistor with high saturation and a large channel length may be used as the load transistor.
  • the semiconductor device 60D performs an initialization operation T01, an initialization ending operation T02, and a signal output operation T03 during a period TSEL during which an output voltage corresponding to an input voltage Vin is output, similar to the semiconductor device 60 described above. Note that the semiconductor device 60D may omit the initialization ending operation T02 as illustrated in FIG. 2B.
  • FIG. 8A is a circuit diagram for explaining the initialization operation T01 in a schematic manner.
  • the explanation of the initialization operation T01 in FIG. 8A is the same as that in FIG. 3A.
  • FIG. 8B is a circuit diagram for illustrating the initialization end operation T02.
  • the explanation of the initialization end operation T02 in FIG. 8B is the same as that in FIG. 3B.
  • FIG. 8C is a circuit diagram for illustrating signal output operation T03.
  • the explanation of signal output operation T03 in FIG. 8C is the same as that in FIG. 3C.
  • Vout When the output voltage Vout becomes Vin-Vth, a voltage equal to or lower than Vth, which corresponds to the threshold voltage of transistor M01, is applied between the gate and source of transistor M01, causing a subthreshold current to flow between the source and drain.
  • Semiconductor device 60D has a configuration including transistor M02. Therefore, during signal output operation T03, a subthreshold current also flows through transistor M02.
  • the subthreshold current flowing through transistor M02 is preferably designed to be the same in magnitude as the subthreshold current flowing through transistor M01. For example, as shown in the layout diagram of FIG. 9B, it is preferable that the areas of the overlapping regions between the semiconductor layer SEM and the wiring GE functioning as the gate electrode in transistors M01 and M02 are approximately the same. With this configuration, the subthreshold current flowing through transistor M02 can be made close to the same in magnitude as the subthreshold current flowing through transistor M01.
  • signals SEL SW01 and SEL SW02 are shown as signals for controlling the conductive states of switches S01 and S02.
  • the signals SEL SW01 and SEL SW02 are signals provided to the gates of transistors functioning as switches.
  • one aspect of the present invention is not limited to the configuration example of the semiconductor device 60D described above.
  • Figs. 10A and 12B a modified example of the semiconductor device 60D described above is described.
  • the switch S01 may be located in the path between the wiring VLD and the wiring DL.
  • a switch having the function of the switch S01 may be provided between the drain side of the transistor M01 and the wiring VLD.
  • the switch S01 in the semiconductor device 60D shown in FIG. 7 can be omitted in cases where the period required for the initialization operation is short.
  • the semiconductor device 60F shown in FIG. 10A is a modified example of the semiconductor device 60D shown in FIG. 7, in which the switch S01 in the semiconductor device 60D shown in FIG. 7 is omitted and a new switch S03 is provided.
  • the semiconductor device 60G shown in FIG. 10B is a modified example of the semiconductor device 60D shown in FIG. 7, in which the switch S03 is added to the semiconductor device 60D shown in FIG. 7.
  • the arrangement of switch S01 and the number of switches having the function of switch S01 can be changed as appropriate. Being able to change the arrangement of switch S01 as appropriate increases the degree of freedom in design. Also, by increasing the number of switches, the current flowing through transistor M01 during the initialization operation can be made smaller.
  • the wiring VLS electrically connected to the other of the source and drain of the transistor M02 and the wiring VLS electrically connected to the second terminal of the switch S02 may be different wirings.
  • FIG. 11A shows a configuration example of a semiconductor device 60D_b in which the wiring electrically connected to the other of the source and drain of the transistor M02 is wiring VLS_SF and the wiring electrically connected to the second terminal of the switch S02 is wiring VLS_DL.
  • the potentials of the wirings VLS_SF and VLS_D may be the same potential VSS or different potentials.
  • FIG. 11B shows a configuration example of a semiconductor device 60D_p in which p-channel transistors are used for the transistors M01 and M02.
  • the potential of each wiring may be set so that the high and low potentials are inverted.
  • the wiring DL that is discharged via the switch S02 in FIG. 7 may be configured to be charged by the wiring VLD in FIG. 11B.
  • FIG. 12A shows a modified version of the layout diagram shown in FIG. 9B.
  • VFETs are used for the transistors M01 and M02 and the transistors that function as switches S01 and S02.
  • a VFET can have at least a portion of the source region, the channel formation region, and the drain region overlap.
  • FIG. 12B shows a cross-sectional view between the dashed lines X1-X2 in FIG. 12A.
  • a VFET has a configuration in which the electrodes SDE1 and SDE2 that contact the source region or drain region, the semiconductor layer SEM having the channel formation region, and the wiring GE that becomes the gate electrode overlap.
  • This allows the occupied area (also called the footprint) to be small.
  • the on-resistance can be small (the on-current can be large).
  • a VLFET can be applied to FIG. 12A as a modified version of the above-mentioned vertical transistor.
  • FIG. 13 is a circuit diagram illustrating an example configuration of semiconductor device 60H.
  • semiconductor device 60H has switches S04, S05, and a capacitor C01. Note that the explanations of transistors M01, M02, switches S01, and S02 in semiconductor device 60H may be omitted because they overlap with the explanations of semiconductor devices 60 and 60D described above.
  • the first terminal of the switch S04 is electrically connected to the other of the source and drain of the transistor M01 and the first terminal of the switch S01.
  • the second terminal of the switch S04 is electrically connected to one of the source and drain of the transistor M02 and the first terminal of the switch S05.
  • the second terminal of the switch S05 is electrically connected to the gate of the transistor M02 and the first electrode of the capacitor C01.
  • the wiring VLS is electrically connected to the other of the source and drain of the transistor M02 and the second electrode of the capacitor C01.
  • Switches S04 and S05 have the function of controlling the charging or discharging of capacitor C01 by controlling the conductive state.
  • Capacitor C01 has the function of holding the gate-source voltage of transistor M02. The charge stored in capacitor C01 can be discharged through the source and drain of transistor M02 to hold the threshold voltage of transistor M02.
  • the threshold voltage of transistor M02 is applied as a bias voltage to transistor M02, and transistor M02 has the function of passing a bias current corresponding to the threshold voltage.
  • Transistor M02 has the function of a current source that passes a bias current corresponding to the threshold voltage. The bias current flowing through transistor M02 according to the threshold voltage is much smaller than the current flowing through transistor M01 when charging line DL.
  • the threshold voltage of transistor M02 is described as being Vth, the same as the threshold voltage of transistor M01, but it may be a different value.
  • the semiconductor device 60H performs a first initialization operation T01_1, a second initialization operation T01_2, an initialization ending operation T02, and a signal output operation T03 during a period TSEL during which the semiconductor device 60H outputs an output voltage corresponding to the input voltage Vin.
  • the semiconductor device 60H may omit the initialization ending operation T02 as shown in Fig. 14B.
  • the times required for the first initialization operation T01_1, the second initialization operation T01_2, and the signal output operation T03 can be set long, and therefore a stable output voltage can be obtained.
  • FIG. 15A is a circuit diagram for illustrating a schematic of the first initialization operation T01_1.
  • the potential of the wiring DL is initialized and the capacitor C01 is charged.
  • the first initialization operation T01_1 is performed with the switch S01 in a non-conductive state (OFF) and the switches S02, S04, and S05 in a conductive state (ON).
  • the switches S04 and S05 have the function of charging the capacitor C01 by being in a conductive state.
  • the switches S04 and S05 are in a conductive state, so a current I1 flows according to the input voltage Vin.
  • a voltage for passing the current I1 is held in the capacitor C01 as the gate-source voltage of the transistor M02.
  • the input voltage Vin is set to a voltage at which the current I1 flows through the transistors M01 and M02 during the first initialization operation T01_1.
  • the switch S02 is in a conductive state, so the potential of the line DL changes to the potential VSS due to the current I2 flowing through the switch S02.
  • FIG. 15B is a circuit diagram for illustrating the second initialization operation T01_2.
  • the capacitor C01 is discharged.
  • the second initialization operation T01_2 is performed with the switches S01 and S04 in a non-conductive state (OFF) and the switches S02 and S05 in a conductive state (ON).
  • the switches S04 and S05 have the function of discharging the capacitor C01 by putting the switch S04 in a non-conductive state and the switch S05 in a conductive state.
  • FIG. 16A is a circuit diagram for explaining the initialization end operation T02.
  • the switches S01, S02, S04, and S05 are all in a non-conducting state (OFF).
  • the potential VSS of the wiring DL set in the initialization operation T01_2 and the threshold voltage of the transistor M02 are held in the capacitor C01.
  • FIG. 16B is a circuit diagram for explaining the signal output operation T03.
  • a current flows through the transistor M01 by turning the switch S01 on (ON).
  • the wiring DL becomes the output voltage Vout.
  • the switch S01 When the switch S01 is turned on, it has the function of performing a signal output operation that provides the output voltage Vout to the wiring DL.
  • a current flows through transistor M02 by turning switch S04 conductive (ON).
  • the current flowing through transistor M02 is a current at the threshold voltage of transistor M02.
  • a subthreshold current flows between the gate and source of transistor M02.
  • Switches S04 and S05 have the function of passing a subthreshold current through transistor M02 by turning switch S04 conductive and switch S05 non-conductive.
  • the subthreshold current flowing through transistor M02 is a current that corresponds to the threshold voltage held between the gate and source of transistor M02. Therefore, even if the transistor characteristics fluctuate in response to fluctuations in the threshold voltage, a small, constant current can flow.
  • Vout When the output voltage Vout becomes Vin-Vth, a voltage equal to or lower than Vth, which corresponds to the threshold voltage of transistor M01, is applied between the gate and source of transistor M01, causing a subthreshold current to flow between the source and drain.
  • Semiconductor device 60H has a configuration including transistor M02. Therefore, during signal output operation T03, a subthreshold current also flows through transistor M02.
  • the subthreshold current flowing through transistor M02 is preferably designed to be the same in magnitude as the subthreshold current flowing through transistor M01. For example, as shown in the layout diagram of FIG. 18, it is preferable that the areas of the overlapping regions between the semiconductor layer SEM and the wiring GE functioning as the gate electrode in transistors M01 and M02 are approximately the same. With this configuration, the subthreshold current flowing through transistor M02 can be made close to the same in magnitude as the subthreshold current flowing through transistor M01.
  • signals SEL SW04 and SEL SW05 are shown as signals for controlling the conductive states of switches S04 and S05.
  • the signals SEL SW04 and SEL SW05 are signals given to the gates of transistors functioning as switches.
  • One aspect of the present invention reduces power consumption by blocking or reducing the bias current flowing through a source follower circuit.
  • a transistor to which a bias voltage is applied is designed to have a gate and source connected so that a subthreshold current flows, and power consumption can be reduced by preventing the bias current from flowing steadily. If the bias current does not flow steadily, it may take some time (also called the settling time) for the output voltage according to the input voltage to stabilize. In particular, the settling time may be long when changing the voltage of the signal line in a downward direction.
  • the conductive state of the switch is changed over to perform an initialization operation and then a signal output operation.
  • charging to a desired voltage by the signal output operation can be performed in a state where the voltage of the signal line is lowered before the signal output operation is performed. Therefore, when inputting an input voltage, even if the voltage of the signal line is changed in a lowering direction, it can be changed to a desired voltage.
  • a vertical transistor in order to reduce the settling time, it is preferable to use a vertical transistor as the driving transistor.
  • the footprint of the driving transistor can be reduced, and the channel length and channel width can be increased.
  • a vertical driving transistor can reduce the on-resistance (increase the on-current), but consumes more power. Therefore, by combining it with the above-described configuration in which a signal output operation is performed after the initialization operation, it is possible to improve the operating speed of a display device having a semiconductor device while suppressing increases in the area occupied by the semiconductor device and power consumption.
  • one embodiment of the present invention is not limited to the configuration example of the semiconductor device 60H described above. Modifications of the semiconductor device 60H described above are described in Figures 19A to 22B.
  • the switch S01 may be located in the path between the wiring VLD and the wiring DL.
  • a switch having the function of the switch S01 may be provided between the drain side of the transistor M01 and the wiring VLD.
  • the switch S01 in the semiconductor device 60H shown in FIG. 13 may be omitted in cases where the period required for the initialization operation is short.
  • Semiconductor device 60I shown in FIG. 19A is a modified example of semiconductor device 60H shown in FIG. 13, in which switch S01 in semiconductor device 60H shown in FIG. 13 is omitted and a new switch S03 is provided.
  • Semiconductor device 60J shown in FIG. 19B is a modified example of semiconductor device 60H shown in FIG. 13, in which switch S03 is added to semiconductor device 60H shown in FIG. 13.
  • the switch S04 may be located in the path between the wiring VLD and the transistor M02.
  • a switch having the function of the switch S04 may be provided between the source side of the transistor M01 and the switch S01.
  • the semiconductor device 60K shown in FIG. 20A is a modified example of the semiconductor device 60H shown in FIG. 13, in which the switch S04 in the semiconductor device 60H shown in FIG. 13 is omitted and a new switch S06 is provided.
  • the semiconductor device 60L shown in FIG. 20B is a modified example of the semiconductor device 60H shown in FIG. 13, in which a switch S06 is added to the semiconductor device 60H shown in FIG. 13.
  • the arrangement of switch S01 or switch S04 and the number of switches having the functions of switch S01 or switch S04 can be changed as appropriate.
  • the arrangement of switch S01 or switch S04 it is possible to increase the degree of freedom in design. Also, by increasing the number of switches, it is possible to further reduce the current flowing through transistor M01 or switch S04 during the initialization operation.
  • the wiring VLS electrically connected to the other of the source and drain of the transistor M02 and the wiring VLS electrically connected to the second terminal of the switch S02 may be different wirings.
  • FIG. 21A shows a configuration example of a semiconductor device 60H_b in which the wiring electrically connected to the other of the source and drain of the transistor M02 is wiring VLS_SF and the wiring electrically connected to the second terminal of the switch S02 is wiring VLS_DL.
  • the potentials of the wirings VLS_SF and VLS_D may be the same potential VSS or different potentials.
  • FIG. 21B shows a configuration example of a semiconductor device 60H_p in which p-channel transistors are used for the transistors M01 and M02.
  • the potential of each wiring may be set so that the high and low potentials are inverted.
  • the wiring DL that is discharged via the switch S02 in FIG. 13 may be configured to be charged by the wiring VLD in FIG. 21B.
  • FIG. 22A shows a modified version of the layout diagram shown in FIG. 18.
  • VFETs are used as the transistors M01 and M02 and the transistors that function as the switches S01, S02, S04, and S05.
  • a VFET can have at least a portion of the source region, the channel formation region, and the drain region overlap.
  • FIG. 22B shows a cross-sectional view between the dashed lines X1-X2 in FIG. 22A.
  • a VFET has a configuration in which the electrodes SDE1 and SDE2 in contact with the region that will become the source region or the drain region, the semiconductor layer SEM having the channel formation region, and the wiring GE that will become the gate electrode overlap. This allows the occupied area (also called the footprint) to be reduced.
  • a VLFET can also be applied to FIG. 22A as a modified version of the above-mentioned vertical transistor.
  • FIG. 23 is a circuit diagram illustrating an example of the configuration of semiconductor device 60M.
  • semiconductor device 60M also has switches S07 to S09 and capacitor C02. Note that the explanations of transistor M01, transistor M02, switch S01, switch S02, switch S04, switch S05, and capacitor C01 in semiconductor device 60M may be omitted because they overlap with the explanations of semiconductor devices 60, 60D, and 60H described above.
  • the first terminal of the switch S07 is electrically connected to a terminal that provides a potential Vx.
  • the second terminal of the switch S07 is electrically connected to a first electrode of the capacitor C02 and the gate of the transistor M01.
  • the first terminal of the switch S08 is electrically connected to a terminal that provides an input voltage Vin.
  • the second terminal of the switch S08 is electrically connected to a second electrode of the capacitor C02 and a first terminal of the switch S09.
  • the second terminal of the switch S09 is electrically connected to a first terminal of the switch S04, the other of the source and drain of the transistor M01, and the first terminal of the switch S01.
  • the potential Vx is a voltage for making the transistor M01 conductive during the first initialization operation.
  • the potential Vx may be the potential VDD.
  • the switch S07 has a function of controlling whether or not the potential Vx is applied to the gate of the transistor M01 by controlling the conductive state.
  • the switch S08 has a function of controlling whether or not the input voltage Vin is applied to the second electrode of the capacitor C02 by controlling the conductive state.
  • the switch S09 has a function of controlling the conductive state to control the retention of the threshold voltage of the transistor M01 in the capacitor C02 by charging and discharging the capacitor C02.
  • Capacitor C02 has the function of holding a voltage for turning on transistor M01 during the first initialization operation.
  • Capacitor C02 which has been charged with a voltage for turning on transistor M01 during the first initialization operation, holds the threshold voltage of transistor M02 by the current flowing through the source and drain of transistor M01 during the second initialization operation.
  • the threshold voltage of transistor M01 held in capacitor C02 is held during the second initialization operation, the initialization end operation, and the signal output operation.
  • Vth threshold voltage
  • the semiconductor device 60M performs a first initialization operation T01_1, a second initialization operation T01_2, an initialization ending operation T02, and a signal output operation T03 during a period TSEL during which an output voltage corresponding to an input voltage Vin is output. Note that the semiconductor device 60M may omit the initialization ending operation T02 as illustrated in FIG. 14B.
  • FIG. 24A is a circuit diagram for explaining the first initialization operation T01_1.
  • the potential of the wiring DL is initialized and the capacitor C01 is charged.
  • the first initialization operation T01_1 is performed with the switches S01, S08, and S09 in a non-conductive state (OFF) and the switches S02, S04, S05, and S07 in a conductive state (ON).
  • the switch S07 By making the switch S07 conductive, the potential Vx is held in the capacitor C02 and a current I1 flows through the transistor M01.
  • the potential Vx is set to a voltage at which the current I1 flows through the transistors M01 and M02 during the first initialization operation T01_1.
  • the switches S04 and S05 are in a conductive state, so a current I1 corresponding to the potential Vx flows.
  • a voltage for passing the current I1 is held in the capacitor C01 as the gate-source voltage of the transistor M02.
  • the switch S02 is in a conductive state, so the potential of the line DL changes to the potential VSS due to the current I2 flowing through the switch S02.
  • FIG. 24B is a circuit diagram for illustrating the second initialization operation T01_2.
  • the second initialization operation T01_2 is performed with switches S01, S04, and S08 in a non-conductive state (OFF), and switches S02, S05, S07, and S09 in a conductive state (ON).
  • Switches S04 and S05 have the function of discharging capacitor C01 by setting switch S04 in a non-conductive state and switch S05 in a conductive state.
  • Switches S07, S08, and S09 have the function of discharging capacitor C02 by setting switch S08 in a non-conductive state and switches S07 and S09 in a conductive state.
  • capacitor C2 When capacitor C2 is discharged, a current I4 flows, and the current I4 becomes small when the gate-source voltage of transistor M01 becomes the threshold voltage of transistor M01. In other words, when capacitor C02 is discharged, the threshold voltage of transistor M01 is held in capacitor C02.
  • FIG. 25A is a circuit diagram for illustrating the initialization end operation T02.
  • switches S01, S02, S04, S05, S07, S08, and S09 are all in a non-conducting state (OFF).
  • the potential VSS of the wiring DL set in the initialization operation T01_2 is held, and the threshold voltage of the transistor M02 is held in the capacitor C01.
  • the threshold voltage of the transistor M01 is held in the capacitor C02.
  • FIG. 25B is a circuit diagram for explaining the signal output operation T03.
  • a current flows through the transistor M01 by turning the switch S01 on (ON).
  • the wiring DL becomes the output voltage Vout.
  • the switch S01 When the switch S01 is turned on, it has the function of performing a signal output operation that provides the output voltage Vout to the wiring DL.
  • switch S07 is turned off (OFF) to put the first electrode side of capacitor C02, i.e., the gate of transistor M01, into an electrically floating state (floating), and switch S08 is turned on (ON). Therefore, with a voltage corresponding to the threshold voltage (Vth) of transistor M01 held across capacitor C02, the potential of the second electrode side of capacitor C02 becomes the input voltage Vin. Therefore, due to the capacitive coupling of capacitor C02, the potential of the first electrode side of capacitor C02, i.e., the gate of transistor M01, becomes Vin+Vth.
  • Vth threshold voltage
  • the potential of the gate of transistor M01 is set to Vin+Vth, and the switch S01 is turned on (ON), so that the current flowing through transistor M01 is reduced by the gate-source voltage of transistor M01 being equal to or lower than Vth.
  • the output voltage Vout can be a voltage with the threshold voltage Vth corrected.
  • a current flows through transistor M02 by turning switch S04 conductive (ON).
  • the current flowing through transistor M02 is a current at the threshold voltage of transistor M02.
  • a subthreshold current flows between the gate and source of transistor M02.
  • Switches S04 and S05 have the function of passing a subthreshold current through transistor M02 by turning switch S04 conductive and switch S05 non-conductive.
  • the subthreshold current flowing through transistor M02 is a current that corresponds to the threshold voltage held between the gate and source of transistor M02. Therefore, even if the transistor characteristics fluctuate in response to fluctuations in the threshold voltage, a small, constant current can flow.
  • Vout When the output voltage Vout becomes Vin, a voltage equal to or lower than Vth, which corresponds to the threshold voltage of transistor M01, is applied between the gate and source of transistor M01, causing a subthreshold current to flow between the source and drain.
  • Semiconductor device 60M has a configuration including transistor M02. Therefore, during signal output operation T03, a subthreshold current also flows through transistor M02.
  • the subthreshold current flowing through the transistor M02 is the same as the subthreshold current flowing through the transistor M01.
  • the area of the region where the semiconductor layer SEM and the wiring GE functioning as the gate electrode overlap in the transistor M01 and the transistor M02 is preferable to make the area of the region where the semiconductor layer SEM and the wiring GE functioning as the gate electrode overlap in the transistor M01 and the transistor M02 approximately the same.
  • the subthreshold current (I st ) flowing through the transistor M02 shown in FIG. 26A can be made to approach the same magnitude as the subthreshold current (I st ) flowing through the transistor M01.
  • one aspect of the present invention is not limited to the configuration example of the semiconductor device 60M described above. Modifications of the semiconductor device 60M described above are described in Figures 27A to 30B.
  • the switch S01 may be located in the path between the wiring VLD and the wiring DL.
  • a switch having the function of the switch S01 may be provided between the drain side of the transistor M01 and the wiring VLD.
  • the switch S01 in the semiconductor device 60M shown in FIG. 23 may be omitted in cases where the period required for the initialization operation is short.
  • the potential Vx may be the potential VDD.
  • the semiconductor device 60N shown in FIG. 27A is a modified example of the semiconductor device 60M shown in FIG. 23, in which the switch S01 in the semiconductor device 60M shown in FIG. 23 is omitted and a new switch S03 is provided.
  • the semiconductor device 60O shown in FIG. 27B is a modified example of the semiconductor device 60M shown in FIG. 23, in which the terminal for applying the potential Vx in the semiconductor device 60M shown in FIG. 23 is connected to the wiring VLD.
  • the switch S04 may be located in the path between the wiring VLD and the transistor M02.
  • a switch having the function of the switch S04 may be provided between the drain side of the transistor M01 and the switch S01.
  • the semiconductor device 60P shown in FIG. 28A is a modified example of the semiconductor device 60M shown in FIG. 23, in which the switch S04 in the semiconductor device 60M shown in FIG. 23 is omitted and a new switch S06 is provided.
  • the semiconductor device 60Q shown in FIG. 28B is a modified example of the semiconductor device 60M shown in FIG. 23, in which the switches S03 and S06 are added to the semiconductor device 60M shown in FIG. 23.
  • the switches S04, S05, and the transistor M02 can be omitted, as in FIG. 1C described above. Also, in the configuration example of the semiconductor device 60M shown in FIG. 23, the switches S04, S05, and the transistor M02 can be replaced with the configuration of the transistor M02 described in FIG. 7 described above.
  • the semiconductor device 60R shown in FIG. 29A is a modified example of the semiconductor device 60M shown in FIG. 23 in which the switches S04, S05, and transistor M02 in the semiconductor device 60M shown in FIG. 23 are omitted.
  • the semiconductor device 60S shown in FIG. 29B is a modified example of the semiconductor device 60M shown in FIG. 23 in which the switches S04, S05, and transistor M02 in the semiconductor device 60M shown in FIG. 23 are replaced with the configuration of the transistor M02 described in FIG. 7 above.
  • the wiring VLS electrically connected to the other of the source and drain of the transistor M02 and the wiring VLS electrically connected to the second terminal of the switch S02 may be different wirings.
  • FIG. 30A shows a configuration example of a semiconductor device 60M_b in which the wiring electrically connected to the other of the source and drain of the transistor M02 is wiring VLS_SF and the wiring electrically connected to the second terminal of the switch S02 is wiring VLS_DL.
  • the potentials of the wirings VLS_SF and VLS_D may be the same potential VSS or different potentials.
  • FIG. 30B shows a configuration example of a semiconductor device 60M_p in which p-channel transistors are used for the transistors M01 and M02.
  • the potential of each wiring may be set so that the high and low potentials are inverted.
  • the wiring DL that is discharged via the switch S02 in FIG. 23 may be configured to be charged by the wiring VLD in FIG. 30B.
  • the arrangement of the switches and the number of switches can be changed as appropriate.
  • the arrangement of the switches it is possible to increase the degree of freedom in design.
  • the number of switches it is possible to further reduce the current flowing through transistor M01 during the initialization operation.
  • 31A to 31E are block diagrams illustrating configuration examples of a display device according to one embodiment of the present invention.
  • the display device 40 has a display unit 42, a drive circuit unit 43, and a drive circuit unit 44.
  • the display unit 42 has a plurality of pixels 41 arranged in a matrix of, for example, m rows and n columns (m and n are each an integer of 2 or more).
  • the pixel 41 arranged in the first row and first column is indicated as pixel 41[1,1]
  • the pixel 41 arranged in the first row and n column is indicated as pixel 41[1,n]
  • the pixel 41 arranged in the mth row and first column is indicated as pixel 41[m,1]
  • the pixel 41 arranged in the mth row and nth column is indicated as pixel 41[m,n].
  • the pixel 41 arranged in the uth row and vth column (u is an integer of 1 to m, v is an integer of 1 to n) may be indicated as pixel 41[u,v].
  • the display device 40 also has m wirings 45 that are arranged in parallel or approximately parallel and whose potential is controlled by a circuit included in the drive circuit section 43.
  • the potential of one wiring 45 is provided to n pixels 41 arranged in the row direction. Note that a configuration in which multiple wirings are included per wiring 45 may be used in accordance with the configuration of the pixel 41.
  • the display device 40A shown in FIG. 31B shows an example configuration in which one wiring 45 includes two wirings.
  • the display device 40 also has n wirings 46 that are arranged in parallel or approximately parallel and whose potential is controlled by a circuit included in the drive circuit unit 44.
  • the potential of one wiring 46 is applied to m pixels 41 arranged in the column direction. Note that a configuration in which multiple wirings are included per wiring 46 may be used in accordance with the configuration of the pixels 41.
  • the pixel 41 has a function of causing a light-emitting element to emit light with an emission intensity according to a data potential written via the wiring 46 to a pixel circuit selected by the potential of the wiring 45, for example.
  • a specific configuration example of the pixel 41 will be described later.
  • the circuit included in the drive circuit unit 43 functions, for example, as a scanning line drive circuit (sometimes called a gate line drive circuit, gate driver, scan driver, or row driver).
  • a scanning line drive circuit sometimes called a gate line drive circuit, gate driver, scan driver, or row driver.
  • the circuit included in the drive circuit unit 44 functions, for example, as a signal line drive circuit (which may also be called a source line drive circuit, source driver, data driver, or column driver). It may also have a function of converting, for example, the data of an image (image data) displayed on the display device 40 into a data potential (digital-analog conversion).
  • a signal line drive circuit which may also be called a source line drive circuit, source driver, data driver, or column driver. It may also have a function of converting, for example, the data of an image (image data) displayed on the display device 40 into a data potential (digital-analog conversion).
  • a configuration can be used in which a current to be passed through the light-emitting element is output to a monitor line.
  • the current output to the monitor line can be converted to an analog voltage (current-voltage conversion) or a digital signal (analog-digital conversion) in the drive circuit unit 44, for example, and output to the outside of the display device 40.
  • analog voltage or digital signal for example, correction of image data (also called external correction) can be performed outside the display device.
  • drive circuit unit 43 and drive circuit unit 44 may be collectively referred to as the "peripheral drive circuit.”
  • the peripheral drive circuit can be configured using various element circuits.
  • the element circuits include a shift register circuit, a flip-flop circuit, a latch circuit, a buffer circuit, an inverter circuit, and a level shifter circuit.
  • the element circuits include a multiplexer circuit, a demultiplexer circuit, a source follower circuit, a source-grounded amplifier circuit, a sample-and-hold circuit, and a switch circuit (e.g., a transmission gate, an analog switch, etc.).
  • Examples of the element circuits include a current-voltage conversion circuit, an analog-digital conversion circuit, a digital-analog conversion circuit, an operational amplifier circuit, a comparator circuit, a pass-transistor logic circuit, an encoder circuit, a decoder circuit, and a gate circuit (e.g., an AND circuit, an OR circuit, and a NOT circuit, etc.).
  • Examples of the element circuits include a combination of these circuits. Note that these element circuits can be configured using, for example, transistors, capacitors, etc.
  • the semiconductor device 60 described above can also be used as at least a part of the peripheral drive circuit.
  • various transistors can be used as transistors constituting the peripheral driver circuit, similar to the semiconductor device 60 described above.
  • vertical transistors can be used as some or all of the transistors constituting the peripheral driver circuit.
  • Si transistors may be used as some or all of the transistors constituting the peripheral driver circuit.
  • OS transistors and Si transistors may be used.
  • Si transistors have a faster operating speed than OS transistors.
  • a CMOS circuit for example, a circuit that operates complementarily, a CMOS logic gate, or a CMOS logic circuit
  • the peripheral driver circuit can be configured using Si transistors as appropriate depending on the specifications of the display device.
  • various configurations can be used as modified examples of the display device 40.
  • a configuration can be used in which a driver circuit unit 43L and a driver circuit unit 43R are disposed to face each other with a display unit 42 interposed therebetween.
  • the display device 40B shown in FIG. 31C shows an example configuration having m wirings 45L whose potentials are controlled by a circuit included in the drive circuit unit 43L, and m wirings 45R whose potentials are controlled by a circuit included in the drive circuit unit 43R.
  • the potentials of one wiring 45L and one wiring 45R are respectively provided to n pixels 41 arranged in the row direction.
  • the display device 40C shown in FIG. 31D shows an example configuration having m wirings 45 whose potential is controlled by both a circuit included in a drive circuit unit 43L and a circuit included in a drive circuit unit 43R.
  • the potential of one wiring 45 is provided to n pixels 41 arranged in the row direction.
  • the effective wiring load parasititic capacitance and parasitic resistance
  • the display device 40D shown in FIG. 31E shows an example configuration having m/2 wirings 45L whose potentials are controlled by a circuit included in a drive circuit unit 43L, and m/2 wirings 45R whose potentials are controlled by a circuit included in a drive circuit unit 43R.
  • the potential of one wiring 45L is provided to n pixels 41 arranged in the row direction in odd-numbered rows.
  • the potential of one wiring 45R is provided to n pixels 41 arranged in the row direction in even-numbered rows.
  • two drive circuit units 44 may be arranged facing each other with the display unit 42 in between.
  • one embodiment of the present invention may be a display device 40 having various configurations as described above, and may also be configured to have a sensor unit that overlaps with the display unit 42 when viewed from above.
  • the sensor unit may have the function of, for example, a touch sensor, a near-touch sensor, or a fingerprint sensor. These sensors may be, for example, capacitive or optical.
  • the drive circuit unit 43 (or the drive circuit unit 43L and the drive circuit unit 43R) can include, for example, a circuit having a function of driving the sensor unit.
  • the drive circuit unit 44 can include, for example, a circuit having a function of outputting a signal detected by the sensor unit to the outside of the display device.
  • FIG. 32 is a circuit diagram illustrating a configuration example of a semiconductor device that can be used for the pixel 41. As shown in FIG. 32
  • the semiconductor device 20A has a pixel circuit 31A and a light-emitting element 32.
  • the pixel circuit 31A has a transistor M1, a transistor M2, a transistor M3, a transistor M4, a transistor M5, a transistor M6, a capacitor C1, and a capacitor C2.
  • the gate of transistor M1 is electrically connected to wiring GLa.
  • One of the source and drain of transistor M1 is electrically connected to the gate of transistor M2.
  • the other of the source and drain of transistor M1 is electrically connected to wiring DL.
  • Transistor M1 has a function (function as a switch) of bringing the gate of transistor M2 and wiring DL into a conductive or non-conductive state.
  • transistor M2 The gate of transistor M2 is electrically connected to one terminal of capacitor C1.
  • One of the source and drain of transistor M2 is electrically connected to the other terminal of capacitor C1.
  • the other of the source and drain of transistor M2 is electrically connected to wiring 21.
  • Transistor M2 also has a backgate. The backgate of transistor M2 is electrically connected to one terminal of capacitor C2. The other terminal of capacitor C2 is electrically connected to one of the source and drain of transistor M2.
  • the gate of transistor M3 is electrically connected to wiring GLb.
  • One of the source and drain of transistor M3 is electrically connected to one terminal of capacitor C1.
  • the other of the source and drain of transistor M3 is electrically connected to the other terminal of capacitor C1.
  • Transistor M3 has a function (function as a switch) of establishing a conductive state or a non-conductive state between the gate of transistor M2 and one of the source and drain of transistor M2.
  • Transistor M4 has a function (function as a switch) of establishing a conductive state or a non-conductive state between one terminal of capacitor C2 and wiring 24.
  • the gate of transistor M5 is electrically connected to wiring GLc.
  • One of the source and drain of transistor M5 is electrically connected to one of the source and drain of transistor M2.
  • the other of the source and drain of transistor M5 is electrically connected to one terminal (e.g., the anode terminal) of light-emitting element 32.
  • Transistor M5 has a function (function as a switch) of establishing a conductive state or a non-conductive state between one of the source and drain of transistor M2 and one terminal of light-emitting element 32.
  • Transistor M6 has a function (function as a switch) of establishing a conductive state or a non-conductive state between one of the source and drain of transistor M2 and wiring 23.
  • the other terminal (e.g., the cathode terminal) of the light-emitting element 32 is electrically connected to the wiring 22.
  • the light-emitting element 32 emits light with a light emission intensity according to the amount of current flowing through the light-emitting element 32.
  • various elements such as, for example, an EL (Electro Luminescence) element (an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), a light-emitting diode (LED: Light Emitting Diode), a micro LED (for example, an LED having an area of a light-emitting region of 10000 ⁇ m 2 or less), an OLED (Organic Light Emitting Diode), a QLED (Quantum-dot Light Emitting Diode), or an electron emission element can be used.
  • an EL Electro Luminescence
  • LED Light Emitting Diode
  • micro LED for example, an LED having an area of a light-emitting region of 10000 ⁇ m 2 or less
  • OLED Organic Light Emitting Diode
  • QLED Quadantum-dot Light
  • Transistor M2 can change its drain current depending on the potential applied to its gate.
  • transistor M2 has the function of controlling the amount of current flowing through light-emitting element 32.
  • transistor M2 has the function of controlling the light-emitting intensity of light-emitting element 32.
  • a transistor having a function similar to that of transistor M2 may be referred to as a "drive transistor.”
  • transistor M2 can change its threshold voltage depending on the potential applied to its back gate.
  • pixel circuit 31A can correct the threshold voltage of transistor M2 by the potential applied to the back gate (node ND2) of transistor M2. That is, in a display device using pixel circuit 31A, it is possible to correct the variation in the threshold voltage of transistor M2 for each pixel circuit 31A.
  • a pixel circuit that can correct the threshold voltage of the drive transistor (transistor M2), such as pixel circuit 31A is also referred to as a pixel circuit equipped with an "internal correction circuit.” By incorporating an internal correction circuit, it is possible to improve the display quality of the display device.
  • node ND1 The region where one of the source and drain of transistor M2, the other of the source and drain of transistor M3, one of the source and drain of transistor M5, one of the source and drain of transistor M6, the other terminal of capacitor C1, and the other terminal of capacitor C2 are electrically connected to each other is sometimes referred to as node ND1.
  • node ND2 The region where the backgate of transistor M2, one of the source and drain of transistor M4, and one terminal of capacitor C2 are electrically connected to each other is sometimes referred to as node ND2.
  • node ND3 The region where the gate of transistor M2, one of the source and drain of transistor M1, one of the source and drain of transistor M3, and one terminal of capacitor C1 are electrically connected to each other is sometimes referred to as node ND3.
  • Capacitor C1 has the function of maintaining the potential difference (voltage) between one of the source and drain of transistor M2 and the gate of transistor M2, for example, when node ND3 is in a floating state.
  • Capacitor C2 has the function of holding the potential difference (voltage) between one of the source and drain of transistor M2 and the backgate of transistor M2, for example, when node ND2 is in a floating state.
  • the lines GLa, GLb, and GLc may be referred to as gate lines, scan lines, or selection lines, for example.
  • the lines DL may be referred to as source lines, data lines, or signal lines, for example.
  • the transistors (transistors M1 to M6) constituting pixel circuit 31A are enhancement type (normally off type) n-channel transistors unless otherwise specified. Therefore, their threshold voltage is greater than 0V.
  • the pixel circuit 31A can be configured using various transistors, similar to the semiconductor device 60 described above.
  • some or all of the transistors that make up pixel circuit 31A may be p-channel transistors.
  • vertical transistors may be used as the transistors that make up pixel circuit 31A.
  • the pixel arrangement can be changed from a pentile arrangement to a stripe arrangement without lowering the resolution of the display device.
  • vertical transistors are preferably used as some or all of the transistors constituting the pixel circuit 31A.
  • vertical transistors are preferably used as the transistors that function as switches (transistor M1 and transistors M3 to M6).
  • transistor M2 it is advisable to use a transistor with high saturation as the drive transistor (transistor M2).
  • a transistor with a long channel length may be used.
  • the above-mentioned VLFET may be used.
  • an OS transistor with extremely low off-state current may be used as a transistor included in the pixel circuit 31A.
  • the charge stored in capacitor C1 and capacitor C2 can be held for a long period of time.
  • the drive method of stopping the operation of the peripheral drive circuit while displaying a still image is also called "idling stop drive.” By performing idling stop drive, it is possible to reduce the power consumption of the display device.
  • the potential applied to the back gate of the drive transistor can be maintained for a long period of time. Therefore, even if the operation to correct the threshold voltage of the drive transistor is performed not every frame but, for example, once every few frames or once every few seconds, the display quality of the display device can be improved.
  • one embodiment of the present invention is not limited to a configuration in which OS transistors are used as pixel circuit 31A, and may be a configuration in which multiple types of transistors containing different semiconductor materials are used.
  • pixel circuit 31A may be configured with LTPO (i.e., both LTPS transistors and OS transistors).
  • OS transistors can be used for the transistors that function as switches (transistor M1 and transistors M3 to M6), and an LTPS transistor can be used for the driving transistor (transistor M2).
  • the transistors may be provided in different layers for each type of transistor.
  • a layer containing Si transistors and a layer containing OS transistors may be provided in an overlapping manner. With such a configuration, the area occupied by pixel circuit 31A can be reduced.
  • One embodiment of the present invention is a semiconductor device 20A in which vertical OS transistors are used as the transistors that function as switches (transistor M1 and transistors M3 to M6) among the transistors that constitute pixel circuit 31A, and a dual-gate OS transistor is used as the driving transistor (transistor M2).
  • vertical OS transistors are used as the transistors that function as switches (transistor M1 and transistors M3 to M6) among the transistors that constitute pixel circuit 31A
  • a dual-gate OS transistor is used as the driving transistor (transistor M2).
  • FIG. 33 is a timing chart illustrating an example of the operation of semiconductor device 20A.
  • a data potential Vdata is applied to the wiring DL.
  • a potential Va is applied to the wiring 21
  • a potential Vc is applied to the wiring 22
  • a potential V0 is applied to the wiring 23
  • a potential V1 is applied to the wiring 24.
  • a potential H e.g., high level, H, or High
  • a potential L e.g., low level, L, or Low
  • the potential H is higher than the potential L.
  • the potential H is at least higher than the threshold voltage of the transistor with respect to the potential L.
  • the potential H is a potential that is input to the gate of a transistor constituting the semiconductor device 20A to turn the transistor on (conductive state).
  • the potential L is a potential that is input to the gate of a transistor constituting the semiconductor device 20A to turn the transistor off (non-conductive state).
  • the potential Va is an anode potential
  • the potential Vc is a cathode potential
  • the potential V0 may be, for example, a potential that can be applied to the gate of the transistor M2 to turn off the transistor M2.
  • the potential V1 may be, for example, a potential that can be applied to the backgate of the transistor M2 to lower (also referred to as negatively shift) the threshold voltage until the transistor M2 is normally on.
  • the potential V0 is, for example, 0 V or a potential L.
  • the potential V1 is, for example, a potential higher than the potential V0 and lower than the potential H.
  • the light emission intensity of the light emitting element 32 is controlled by the magnitude of the current Ie flowing through the light emitting element 32.
  • the pixel circuit 31A has a function of controlling the magnitude of the current Ie according to the data potential Vdata provided from the wiring DL.
  • the timing chart in FIG. 33 shows the potential (potential H or potential L) applied to each of the wirings GLa, GLb, and GLc during each operation period (periods T11 to T16). It also shows changes in the potentials of the nodes ND1, ND2, and ND3.
  • each period may be shown to have the same length, but the length of each period may be different.
  • each period (period T11 to period T16) is shown to have the same length for ease of explanation, but the length of each period may be different.
  • the length of each period can be set appropriately according to the specifications of the display device using the semiconductor device 20A.
  • the current Ie flowing through the light-emitting element 32 is determined mainly by the data potential Vdata and the threshold voltage of the transistor M2. Therefore, in a display device having multiple pixel circuits 31A, even if the same data potential Vdata is applied to each pixel circuit 31A, if the threshold voltage of the transistor M2 in each pixel circuit 31A is different, a different current Ie will flow through each pixel circuit 31A. Therefore, the variation in the threshold voltage of the transistor M2 is one of the factors that causes a decrease in the display quality of the display device.
  • a potential L is applied to the wirings GLa and GLb, and a potential H is applied to the wiring GLc. Therefore, the transistors M1, M3, M4, and M6 are in an off state, and the transistor M5 is in an on state.
  • the potential of each wiring is assumed to be maintained at the potential of the previous period.
  • period T11 a reset (initialization) operation is performed. Specifically, a potential H is applied to wiring GLb. Then, transistors M3 and M4 are turned on.
  • the potential of node ND1 becomes potential Ve0. Furthermore, via transistor M3, the potential of node ND3 also becomes potential Ve0.
  • potential Ve0 is a potential that is higher than potential Vc by the amount of the voltage drop in light-emitting element 32.
  • potential V1 is applied to node ND2 via transistor M4. It is assumed that transistor M2 is normally on when "potential V1-potential Ve0" is applied as the backgate voltage of transistor M2.
  • the backgate voltage of the transistor M2 is "potential V1-potential Ve0", so the transistor M2 is normally on. Therefore, charge is supplied to the node ND1 from the wiring 21 via the transistor M2. As a result, the potential of the node ND1 rises over time. Also, because the transistor M3 is on, the potential of the node ND3 similarly rises. Here, as the potential of the node ND1 gradually rises, the backgate voltage of the transistor M2 gradually decreases. In other words, the threshold voltage of the transistor M2 gradually rises (also called a plus shift).
  • the transistor M2 turns off and the rise in the potential of the node ND1 stops.
  • the backgate voltage at which the threshold voltage of the transistor M2 becomes 0V is set to the correction voltage Vb.
  • the potential of the node ND1 becomes "potential V1-correction voltage Vb".
  • nodes ND2 and ND3 are in a floating state, and the charges of the respective nodes are retained. In other words, the state in which the correction voltage Vb obtained during period T12 is applied as the backgate voltage of transistor M2 is maintained.
  • a potential H is applied to the wiring GLa. This causes the transistors M1 and M6 to turn on.
  • the data potential Vdata is applied to node ND3, and the potential V0 is applied to node ND1.
  • data potential Vdata - potential V0 is applied as the gate voltage of transistor M2.
  • node ND2 is in a floating state, and nodes ND1 and ND2 are capacitively coupled via capacitor C2. Therefore, when the potential of node ND1 changes to potential V0, the potential of node ND2 also changes to "potential V0 + correction voltage Vb." In other words, correction voltage Vb is applied as the backgate voltage of transistor M2, and data potential Vdata can be written while maintaining the state in which the threshold voltage of transistor M2 is corrected to 0V.
  • a potential L is applied to the wiring GLa. This turns off the transistors M1 and M6.
  • node ND3 is in a floating state, and the charge at node ND3 is retained.
  • charge is supplied to node ND1 from wiring 21 via transistor M2, so that the potential at node ND1 gradually increases.
  • node ND3 is floating, and nodes ND1 and ND3 are capacitively coupled via capacitor C1. Therefore, the potential of node ND3 also rises following the rise in the potential of node ND1. In other words, a state in which "data potential Vdata-potential V0" is applied as the gate voltage of transistor M2 is maintained.
  • node ND2 is floating, and nodes ND1 and ND2 are capacitively coupled via capacitor C2. Therefore, the potential of node ND2 also rises following the rise in the potential of node ND1. In other words, a state in which correction voltage Vb is applied as the backgate voltage of transistor M2 is maintained.
  • a current flows from wiring 21 to wiring 22 via transistor M2, transistor M5, and light-emitting element 32. That is, current Ie flows through light-emitting element 32, and light-emitting element 32 emits light with a light intensity according to current Ie.
  • the operation of the period T16 may be performed at the same timing as the operation of the period T15.
  • the timing at which the potential L is applied to the wiring GLa and the timing at which the potential H is applied to the wiring GLc may be the same.
  • the threshold voltage of the transistor M2 can be corrected to 0 V by performing the above-described threshold voltage correction operation (periods T11 to T13).
  • the state in which the threshold voltage of the transistor M2 is corrected to 0 V i.e., the state in which the correction voltage Vb is applied as the backgate voltage of the transistor M2 can be maintained for a long period of time.
  • the current Ie flowing through the light-emitting element 32 is proportional to the square of "gate voltage of transistor M2-threshold voltage of transistor M2". Therefore, by correcting the threshold voltage of transistor M2 to 0V, the current Ie is proportional to the square of "data potential Vdata-potential V0". In other words, the current Ie is independent of the threshold voltage of transistor M2. Therefore, the state in which the current Ie flows independent of the threshold voltage of transistor M2 can be maintained for a long period of time.
  • the frequency of performing the above-described threshold voltage correction operation (periods T11 to T13) can be made lower than the frequency of performing the data writing operation and the light-emitting operation (periods T14 to T16).
  • the threshold voltage of the transistor M2 can be maintained in a state where it is corrected to 0 V. Therefore, in a display device using the semiconductor device, it is possible to improve the display quality and reduce power consumption.
  • FIG. 34 is a circuit diagram illustrating a semiconductor device 20B, which is a modified example of the semiconductor device 20A.
  • the semiconductor device 20B has a pixel circuit 31B instead of the pixel circuit 31A.
  • the pixel circuit 31B differs from the pixel circuit 31A in that the transistor M1 and the transistors M3 to M6 each have a backgate.
  • the backgate of the transistor is electrically connected to the gate of the transistor. In this way, in a transistor having a backgate, the on-resistance can be reduced by applying the same potential to the backgate as to the gate.
  • the potential that can be applied to the back gate is not limited to the same potential as that of the gate.
  • the threshold voltage can be changed by applying an arbitrary potential to the back gate.
  • the potential applied to the back gate is not limited to a fixed potential.
  • the potential applied to the back gate may be the same or different for each transistor.
  • FIG. 35 is a circuit diagram illustrating a semiconductor device 20C, which is a modified example of the semiconductor device 20A.
  • the semiconductor device 20C has a pixel circuit 31C instead of the pixel circuit 31A.
  • the pixel circuit 31C differs from the pixel circuit 31A in that it does not have a transistor M6.
  • the transistor M5 is turned on so that the potential of the node ND1 becomes a potential that is higher by an amount corresponding to the voltage drop in the light-emitting element 32.
  • the semiconductor device 20C further does not need to have the wiring 23. This makes it possible to reduce the area occupied by the pixel circuit 31C.
  • FIG. 36 is a circuit diagram illustrating a semiconductor device 20D, which is a modified example of the semiconductor device 20A.
  • the semiconductor device 20D has a pixel circuit 31D instead of the pixel circuit 31A.
  • the pixel circuit 31D differs from the pixel circuit 31A in that it does not have a transistor M5. Therefore, one of the source and drain of the transistor M2 is electrically connected to one terminal of the light-emitting element 32.
  • a potential Va may be applied to the wiring 22 to prevent current from flowing through the light-emitting element 32.
  • the semiconductor device 20D does not further have to have the wiring GLc. Therefore, the area occupied by the pixel circuit 31D can be reduced.
  • FIG. 37 is a circuit diagram illustrating a semiconductor device 20E, which is a modified example of the semiconductor device 20D.
  • the semiconductor device 20E has a pixel circuit 31E instead of the pixel circuit 31D.
  • the pixel circuit 31E differs from the pixel circuit 31D in that it does not have the transistor M3, the transistor M4, or the capacitor C2.
  • the transistor M2 does not have to have a back gate.
  • the pixel circuit 31E does not have an internal correction circuit.
  • the semiconductor device 20E further does not have to have the wiring GLb and the wiring 24. This makes it possible to reduce the area occupied by the pixel circuit 31E.
  • FIG. 38 is a circuit diagram illustrating a semiconductor device 20F, which is a modified example of semiconductor device 20A.
  • Semiconductor device 20F has pixel circuit 31F instead of pixel circuit 31A.
  • Pixel circuit 31F differs from pixel circuit 31A in that it has transistors M7, M8, and capacitor C3 instead of transistors M3, M4, M6, capacitors C1, and C2.
  • transistor M2 does not need to have a backgate.
  • Pixel circuit 31F has an internal correction circuit different from that of pixel circuit 31A.
  • One of the source and drain of transistor M1 is electrically connected to one terminal of capacitor C3.
  • the gate of transistor M2 is electrically connected to one of the source and drain of transistor M7.
  • One of the source and drain of transistor M2 is electrically connected to the other terminal of capacitor C3.
  • the gate of transistor M7 is electrically connected to wiring GLa.
  • the other of the source and drain of transistor M7 is electrically connected to wiring 25.
  • Transistor M7 has a function of bringing the gate of transistor M2 and wiring 25 into a conductive or non-conductive state (functions as a switch).
  • the gate of transistor M8 is electrically connected to wiring GLb.
  • One of the source and drain of transistor M8 is electrically connected to the gate of transistor M2.
  • the other of the source and drain of transistor M8 is electrically connected to one terminal of capacitor C3.
  • Transistor M8 has a function (function as a switch) of establishing a conductive state or a non-conductive state between the gate of transistor M2 and one terminal of capacitor C3.
  • node ND3 The region where the gate of transistor M2, one of the source and drain of transistor M7, and one of the source and drain of transistor M8 are electrically connected to each other is sometimes referred to as node ND3.
  • node ND4 The region where one of the source and drain of transistor M1, the other of the source and drain of transistor M8, and one terminal of capacitor C3 are electrically connected to each other is sometimes referred to as node ND4.
  • Capacitor C3 has the function of maintaining the potential difference (voltage) between one of the source and drain of transistor M2 and one of the source and drain of transistor M1, for example, when node ND4 is in a floating state.
  • a potential L is applied to the wiring GLa and wiring GLb, and a potential H is applied to the wiring GLc. Then, a potential H is applied to the wiring GLa. Then, a potential L is applied to the wiring GLc. Then, a potential L is applied to the wiring GLa. Then, a potential H is applied to the wiring GLb and wiring GLc.
  • FIG. 39 is a circuit diagram illustrating a semiconductor device 20G, which is a modified example of the semiconductor device 20A.
  • the semiconductor device 20G has a pixel circuit 31G instead of the pixel circuit 31A.
  • the pixel circuit 31G further has a transistor M9 and a capacitor C4.
  • the gate of transistor M5 is electrically connected to one terminal of capacitor C4.
  • the other of the source and drain of transistor M5 is electrically connected to the other terminal of capacitor C4.
  • the gate of transistor M9 is electrically connected to wiring 26.
  • One of the source and drain of transistor M9 is electrically connected to the gate of transistor M5.
  • the other of the source and drain of transistor M9 is electrically connected to wiring GLc.
  • node ND5 The region where the gate of transistor M5, one of the source and drain of transistor M9, and one terminal of capacitor C4 are electrically connected to each other is sometimes referred to as node ND5.
  • Capacitor C4 has the function of holding the potential difference (voltage) between the other of the source and drain of transistor M5 and the gate of transistor M5, for example, when node ND5 is in a floating state.
  • the transistor M5 when the potential of one terminal of the light-emitting element 32 (i.e., the other of the source and drain of the transistor M5) rises during light-emitting operation, the potential of the node ND5 (i.e., the gate of the transistor M5) also rises accordingly due to capacitive coupling via the capacitor C4. Therefore, the transistor M5 can be reliably turned on during light-emitting operation. This allows a stable current to be supplied to the light-emitting element 32.
  • the capacitor C4 is sometimes called a bootstrap capacitance.
  • FIG. 40 is a circuit diagram illustrating semiconductor device 20H, which is a modified example of semiconductor device 20F.
  • Semiconductor device 20H has pixel circuit 31H instead of pixel circuit 31F.
  • pixel circuit 31H further has transistor M9 and capacitor C4.
  • pixel circuit 31H is configured by combining the internal correction circuit of pixel circuit 31F and the bootstrap capacitance of pixel circuit 31G.
  • FIG. 41 is a circuit diagram illustrating the semiconductor device 20I.
  • the semiconductor device 20I has a pixel circuit 31I and a liquid crystal element 33.
  • the pixel circuit 31I has a transistor M1 and a capacitor C5.
  • the pixel circuit 31I has a transistor M1 and a capacitor C5.
  • Transistor M1 has a function (function as a switch) of establishing a conductive state or a non-conductive state between one terminal of capacitor C5 and wiring DL.
  • the other terminal of the liquid crystal element 33 is electrically connected to the wiring 22.
  • the light transmittance of the liquid crystal element 33 changes according to the potential difference (voltage) between a pair of terminals (between one terminal and the other terminal).
  • capacitor C5 One terminal of capacitor C5 is electrically connected to one of the source and drain of transistor M1. The other terminal of capacitor C5 is electrically connected to wiring 27.
  • node ND6 The region where one of the source and drain of transistor M1, one terminal of capacitor C5, and one terminal of liquid crystal element 33 are electrically connected to each other is sometimes referred to as node ND6.
  • Capacitor C5 has the function of maintaining the potential difference between a pair of terminals of liquid crystal element 33, for example, when node ND6 is in a floating state.
  • the semiconductor device 20 can be applied to a pixel circuit such as an image sensor.
  • FIG. 42 is a circuit diagram illustrating the semiconductor device 20J.
  • the semiconductor device 20J has a pixel circuit 31J and a light receiving element 34.
  • the pixel circuit 31J has transistors M1 to M3.
  • the gate of transistor M1 is electrically connected to one terminal of the light receiving element 34.
  • One of the source and drain of transistor M1 is electrically connected to wiring DL.
  • the other of the source and drain of transistor M1 is electrically connected to one of the source and drain of transistor M2.
  • the other of the source and drain of transistor M2 is electrically connected to wiring 28.
  • the gate of transistor M2 is electrically connected to wiring GLa.
  • One of the source and drain of transistor M3 is electrically connected to one terminal of the light receiving element 34.
  • the other of the source and drain of transistor M3 is electrically connected to wiring 28.
  • the gate of transistor M3 is electrically connected to wiring GLb.
  • the other terminal of the light receiving element 34 is electrically connected to wiring 22.
  • Transistor M3 is a reset transistor. In response to control of line GLb, it performs a reset operation to make the potential of one terminal of light receiving element 34 (potential of node ND7) equal to the potential of line 28.
  • Transistor M1 is a drive transistor for passing a current corresponding to the potential of node ND7.
  • Transistor M2 is a read control transistor. In response to control of line GLa, it controls whether or not a current corresponding to the potential of node ND7 is passed to line DL.
  • the transistor M1 can function as a source follower circuit. Therefore, by providing the switches S01 and S02 of the semiconductor device 60 of one embodiment of the present invention in the wiring DL, an output voltage according to the potential of the node ND7 can be output through the wiring DL.
  • FIG. 43 is a circuit diagram illustrating the semiconductor device 20K.
  • the semiconductor device 20K has a memory cell 31K.
  • the memory cell 31K has transistors M1 to M3.
  • the gate of transistor M1 is electrically connected to one terminal of wiring GLb.
  • One of the source and drain of transistor M1 is electrically connected to wiring DL.
  • the other of the source and drain of transistor M1 is electrically connected to the gate of transistor M2.
  • One of the source and drain of transistor M2 is electrically connected to wiring DL.
  • the other of the source and drain of transistor M2 is electrically connected to one of the source and drain of transistor M.
  • the other of the source and drain of transistor M3 is electrically connected to wiring 28.
  • Transistor M1 is a charge retention transistor. In response to control of line GLb, it retains a charge in the gate of transistor M2 that corresponds to the potential of line DL. The potential of the gate of transistor M2 (the potential of node ND8) is retained by making transistor M1 non-conductive. Transistor M2 is a drive transistor for passing a current that corresponds to the potential of node ND8. Transistor M3 is a read control transistor. In response to control of line GLa, it controls whether or not a current that corresponds to the potential of node ND8 is passed to line DL.
  • the transistor M1 can function as a source follower circuit. Therefore, by providing the switches S01 and S02 of the semiconductor device 60 of one embodiment of the present invention in the wiring DL, the potential of one terminal of the light-receiving element 34 can be output through the wiring DL.
  • [Shift Register] 44A to 44E and 45A to 45E are circuit diagrams illustrating examples of the configuration of a semiconductor device that can be used in a peripheral driving circuit.
  • the semiconductor device can be used, for example, as a part of a gate driver. Also, for example, the semiconductor device can be used as a part of a shift register.
  • the semiconductor device 70A shown in FIG. 44A has m register units 71 and m buffer units 72.
  • the semiconductor device 70A is electrically connected to m wirings GLa and m wirings GLb.
  • the m register units 71 are electrically connected to each other via m wirings SR.
  • FIG. 44A a part of the semiconductor device 70A is excerpted, and the register units 71_u to 71_u+2, the buffer units 72_u to 72_u+2, the wirings SR_u-1 to SR_u+4, the wirings GLa_u to GLa_u+2, and the wirings GLb_u to GLb_u+2 are illustrated.
  • m is an integer of 2 or more, and corresponds to the number m of rows of the pixels 41 arranged in a matrix in the display device 40 described above.
  • u is an integer of 1 to m.
  • Figure 44B is a circuit diagram explaining an example configuration of the register unit 71 and the buffer unit 72.
  • Figure 44C is a circuit block corresponding to the register unit 71 and the buffer unit 72.
  • the register unit 71 can be applied to each of the register units 71_1 to 71_m.
  • the buffer unit 72 can be applied to each of the buffer units 72_1 to 72_m. That is, for example, in the register unit 71_u, the wiring IN21 is electrically connected to the wiring SR_u-1, the wiring IN22 is electrically connected to the wiring SR_u+2, and the wiring OUT21 is electrically connected to the wiring SR_u.
  • the wiring OUT31 is electrically connected to the wiring GLa_u
  • the wiring OUT32 is electrically connected to the wiring GLb_u. 44A and 44C, wirings IN21, IN31, IN32, VLD, and VLS are not shown.
  • register units 71_1 to 71_u-1 and register units 71_u+1 to 71_m are not shown.
  • the wiring OUT21 in the register portion 71_u-1 is electrically connected to the wiring IN21 in the register portion 71_u through the wiring SR_u-1
  • the wiring OUT21 in the register portion 71_u is electrically connected to the wiring IN21 in the register portion 71_u+1 through the wiring SR_u.
  • each of the register portions 71_1 to 71_m is sequentially selected, and a desired potential can be applied to each of the wirings GLa_u and GLb_u in the buffer portion 72_u electrically connected to the selected register portion 71_u.
  • the potential of the wiring VLS is applied to each of the wirings GLa_u and GLb_u in the buffer portion 72_u electrically connected to the unselected register portion 71_u.
  • the register unit 71 shown in FIG. 44B includes transistors M21, M22, M23, M24, M25, and M26.
  • Transistor M21 has a function of bringing the wiring VLD and wiring NL21 into a conductive state or a non-conductive state depending on the potential of wiring IN21.
  • Transistor M22 has a function of bringing the wiring VLD and wiring NL22 into a conductive state or a non-conductive state depending on the potential of wiring IN22.
  • Transistor M23 has a function of bringing the wiring VLS and wiring NL21 into a conductive state or a non-conductive state depending on the potential of wiring NL22.
  • Transistor M24 has a function of bringing the wiring VLS and wiring NL22 into a conductive state or a non-conductive state depending on the potential of wiring IN21.
  • the transistor M25 has a function of bringing the wiring IN23 and the wiring OUT21 into a conductive state or a non-conductive state depending on the potential of the wiring NL21.
  • the transistor M26 has a function of bringing the wiring VLS and the wiring OUT21 into a conductive state or a non-conductive state depending on the potential of the wiring NL22.
  • the buffer unit 72 shown in FIG. 44B includes transistors M31, M32, M33, and M34.
  • Transistor M31 has a function of bringing wiring IN31 and wiring OUT31 into a conductive state or a non-conductive state depending on the potential of wiring NL21.
  • Transistor M32 has a function of bringing wiring IN32 and wiring OUT32 into a conductive state or a non-conductive state depending on the potential of wiring NL21.
  • Transistor M33 has a function of bringing wiring VLS and wiring OUT31 into a conductive state or a non-conductive state depending on the potential of wiring NL22.
  • Transistor M34 has a function of bringing wiring VLS and wiring OUT32 into a conductive state or a non-conductive state depending on the potential of wiring NL22.
  • FIG. 44D is a timing chart illustrating an example of the operation of the register unit 71 and the buffer unit 72 shown in FIG. 44B.
  • a potential H is applied to the wiring VLD and a potential L is applied to the wiring VLS. It is also assumed that either a potential H or a potential L is applied to each of the wirings IN21, IN22, IN23, IN31, and IN32.
  • the timing chart shown in FIG. 44D shows the potential (potential H or potential L) applied to each of wirings IN21, IN22, IN23, IN31, and IN32 during each operation period (periods T71 to T73). It also shows the change in the potential of each of wirings NL21, NL22, OUT21, OUT31, and OUT32.
  • potential H is applied to wiring IN21, so that the potential of wiring NL22 becomes potential L and the potential of wiring NL21 becomes potential H. Then, transistors M25, M31, and M32 are each turned on, and transistors M26, M33, and M34 are each turned off. Thus, the potentials (potential H or potential L) of wiring IN23, wiring IN31, and wiring IN32 are applied to wiring OUT21, wiring OUT31, and wiring OUT32, respectively, via transistors M25, M31, and M32, respectively. Note that even if potential L is applied to wiring IN21 after that, the potentials of wiring NL22 and wiring NL21 are maintained.
  • potential H is applied to wiring IN22, so that the potential of wiring NL22 becomes potential H and the potential of wiring NL21 becomes potential L. Then, transistors M25, M31, and M32 are each turned off, and transistors M26, M33, and M34 are each turned on. Therefore, regardless of the potentials (potential H or potential L) of wiring IN23, wiring IN31, and wiring IN32, potential L is applied to wiring OUT21, wiring OUT31, and wiring OUT32. Note that even if potential L is applied to wiring IN22 after that, the potentials of wiring NL22 and wiring NL21 are maintained.
  • FIG. 44E is a circuit diagram illustrating a modified example of the register unit 71 and the buffer unit 72.
  • the register unit 71a and the buffer unit 72a shown in FIG. 44E differ from the register unit 71 and the buffer unit 72 in that they have a bootstrap circuit. That is, the register unit 71a has a transistor M27 and a capacitor C21 in addition to the register unit 71, and the buffer unit 72a has a transistor M35, a transistor M36, a capacitor C31, and a capacitor C32 in addition to the buffer unit 72. Note that the capacitors C21, C31, and C32 are sometimes referred to as bootstrap capacitances.
  • the gate of transistor M27 is electrically connected to the wiring VLD.
  • the gate of transistor M25 is electrically connected to the wiring NL21 via the source and drain of transistor M27.
  • the gate of transistor M25 is electrically connected to the wiring OUT21 via capacitor C21.
  • the gate of transistor M35 is electrically connected to the wiring VLD.
  • the gate of transistor M31 is electrically connected to the wiring NL21 via the source and drain of transistor M35.
  • the gate of transistor M31 is electrically connected to the wiring OUT31 via capacitor C31.
  • the gate of transistor M36 is electrically connected to the wiring VLD.
  • the gate of transistor M32 is electrically connected to the wiring NL21 via the source and drain of transistor M36.
  • the gate of transistor M32 is electrically connected to the wiring OUT32 via capacitor C32.
  • the transistor M25 when the transistor M25 transmits the potential H from the wiring IN23 to the wiring OUT21, a drop in potential occurs due to the threshold voltage. Therefore, by adopting a bootstrap circuit as in the register unit 71a, the transistor M25 can maintain the on state due to capacitive coupling by the bootstrap capacitance. Therefore, the potential H can be transmitted to the wiring OUT21 without a drop in potential due to the threshold voltage.
  • the buffer unit 72 when the transistor M31 transmits the potential H from the wiring IN31 to the wiring OUT31, a potential drop occurs due to the threshold voltage, and when the transistor M32 transmits the potential H from the wiring IN32 to the wiring OUT32, a potential drop occurs due to the threshold voltage. Therefore, by employing a bootstrap circuit as in the buffer unit 72a, the on state can be maintained in each of the transistors M31 and M32 by capacitive coupling due to the bootstrap capacitance. Therefore, the potential H can be transmitted to each of the wiring OUT31 and the wiring OUT32 without a potential drop due to the threshold voltage.
  • the semiconductor device 70B shown in FIG. 45A has m register units 71 and m inverter units 73.
  • the semiconductor device 70B is electrically connected to m wirings GLc.
  • the m register units 71 are electrically connected to each other via m wirings SR.
  • FIG. 45A illustrates a portion of the semiconductor device 70B, and shows register units 71_u to 71_u+2, inverter units 73_u to 73_u+2, wirings SR_u-1 to SR_u+4, and wirings GLc_u to GLc_u+2.
  • FIG. 45B is a circuit diagram for explaining a configuration example of the inverter unit 73.
  • FIG. 45C is a circuit block corresponding to the inverter unit 73.
  • the inverter unit 73 can be applied to each of the inverter units 73_1 to 73_m. That is, for example, in the inverter unit 73_u, the wiring IN41 is electrically connected to the wiring SR_u, the wiring IN42 is electrically connected to the wiring SR_u+2, and the wiring OUT41 is electrically connected to the wiring GLc_u. Note that the wiring VLD and the wiring VLS are omitted from the illustration in FIG. 45A and FIG. 45C. Note that the same is true for the inverter units 73_1 to 73_u-1 and the inverter units 73_u+1 to 73_m.
  • each of the register units 71_1 to 71_m is selected in sequence, and a desired potential can be applied to the wiring GLc_u in the inverter unit 73_u electrically connected to the selected register unit 71_u.
  • the potential of the wiring VLD is applied to the wiring GLc_u in the inverter unit 73_u electrically connected to the unselected register unit 71_u.
  • the inverter unit 73 shown in FIG. 45B includes transistors M41, M42, M43, and M44.
  • Transistor M41 has a function of bringing the wiring VLD and wiring NL41 into a conductive state or a non-conductive state depending on the potential of wiring IN42.
  • Transistor M42 has a function of bringing the wiring VLS and wiring NL41 into a conductive state or a non-conductive state depending on the potential of wiring IN41.
  • Transistor M43 has a function of bringing the wiring VLD and wiring OUT41 into a conductive state or a non-conductive state depending on the potential of wiring NL41.
  • Transistor M44 has a function of bringing the wiring VLS and wiring OUT41 into a conductive state or a non-conductive state depending on the potential of wiring IN41.
  • FIG. 45D is a timing chart illustrating an example of the operation of the inverter unit 73 shown in FIG. 45B.
  • the timing chart shown in FIG. 45D shows the potential (potential H or potential L) applied to each of the wirings IN41 and IN42 during each operation period (periods T74 to T76). It also shows the change in the potential of each of the wirings NL41 and OUT41.
  • a potential L is applied to wiring IN41 and wiring IN42.
  • the potential of wiring NL41 is also assumed to be a potential H.
  • transistor M43 is on (conductive), and transistor M44 is off (non-conductive).
  • a potential H is applied to wiring OUT41. Note that in the following description of the operation, unless otherwise specified, the potential of each wiring is assumed to be maintained at the potential of the previous period.
  • a potential H is applied to wiring IN41, causing the potential of wiring NL41 to become a potential L.
  • This causes transistor M43 to be turned off and transistor M44 to be turned on.
  • potential L is applied to wiring OUT41.
  • potential L is applied to wiring IN41, causing transistor M44 to be turned off.
  • the potentials of wiring NL41 and wiring OUT41 are maintained.
  • FIG. 45E is a circuit diagram illustrating a modified example of inverter unit 73.
  • Inverter unit 73a shown in FIG. 45E differs from inverter unit 73 in that it has a bootstrap circuit. That is, inverter unit 73a has, in addition to inverter unit 73, transistor M45 and capacitor C41. Note that capacitor C41 is sometimes referred to as a bootstrap capacitance.
  • the gate of transistor M45 is electrically connected to the wiring VLD.
  • the gate of transistor M43 is electrically connected to the wiring NL41 via the source and drain of transistor M45.
  • the gate of transistor M43 is electrically connected to the wiring OUT41 via capacitor C41.
  • the transistor M43 when the transistor M43 transmits the potential H from the wiring VLD to the wiring OUT41, a drop in potential occurs due to the threshold voltage. Therefore, by adopting a bootstrap circuit as in the inverter unit 73a, the transistor M43 can maintain the on state due to capacitive coupling by the bootstrap capacitance. Therefore, the potential H can be transmitted to the wiring OUT41 without a drop in potential due to the threshold voltage.
  • the semiconductor device 70A and the semiconductor device 70B can be used in the display device 40.
  • the semiconductor device 70A and the semiconductor device 70B can be used as part of a gate driver in the display device 40.
  • the wirings GLa_1 to GLa_m correspond to the wiring GLa in the case where the semiconductor device 20A is used for the pixel 41 in each of the pixels 41 arranged in the mth row.
  • the wirings GLb_1 to GLb_m correspond to the wiring GLb
  • the wirings GLc_1 to GLc_m correspond to the wiring GLc.
  • one aspect of the present invention is not limited to the configurations of the semiconductor device 70A and the semiconductor device 70B described above, and the configurations may be changed as appropriate within the scope in which the display device described above can be realized.
  • [Demultiplexer] 46A to 46C are circuit diagrams illustrating an example of the configuration of a semiconductor device that can be used in a peripheral driving circuit.
  • the semiconductor device can be used, for example, as a part of a source driver. Also, for example, the semiconductor device can be used, for example, as a part of a demultiplexer.
  • the semiconductor device 80 shown in FIG. 46A has n/2 selector units 81.
  • the semiconductor device 80 is electrically connected to a wiring SMP1, a wiring SMP2, n/2 wirings SL, and n wirings DL.
  • FIG. 46 a part of the semiconductor device 80 is excerpted, and selector units 81_1 and 81_2, selector units 81_n/2, wirings SMP1, SMP2, wirings SL_1 and SL_2, wirings SL_n/2, wirings DL_1 to DL_4, and wirings DL_n-1 and DL_n are illustrated.
  • n is an integer of 2 or more, and corresponds to the number of columns n of the pixels 41 arranged in a matrix in the display device 40 described above.
  • 46B and 46C are a circuit diagram and a block diagram, respectively, explaining a configuration example of the selector unit 81.
  • the selector unit 81 can be applied to each of the selector units 81_1 to 81_n/2. That is, for example, in the selector unit 81_1, the wiring IN51 is electrically connected to the wiring SL_1, the wiring SW51 is electrically connected to the wiring SMP1, the wiring SW52 is electrically connected to the wiring SMP2, the wiring OUT51 is electrically connected to the wiring DL_1, and the wiring OUT52 is electrically connected to the wiring DL_2.
  • the wiring IN51 is electrically connected to the wiring SL_n/2
  • the wiring SW51 is electrically connected to the wiring SMP1
  • the wiring SW52 is electrically connected to the wiring SMP2
  • the wiring OUT51 is electrically connected to the wiring DL_n-1
  • the wiring OUT52 is electrically connected to the wiring DL_n.
  • selector unit 81_2 through selector unit 81_n/2-1.
  • the selector unit 81 shown in FIG. 46B includes a transistor M51 and a transistor M52.
  • the transistor M51 has a function of bringing the wiring IN51 and the wiring OUT51 into a conductive state or a non-conductive state depending on the potential of the wiring SW51.
  • the transistor M52 has a function of bringing the wiring IN51 and the wiring OUT52 into a conductive state or a non-conductive state depending on the potential of the wiring SW52.
  • the selector unit 81 has a function of transmitting the potential of the wiring IN51 to either the wiring OUT51 or the wiring OUT52 depending on the potential of the wiring SW51 and the potential of the wiring SW52.
  • the selector unit 81 can be said to have one input (wiring IN51) and two outputs (wiring OUT51 and wiring OUT52).
  • the semiconductor device 80 can be used in the display device 40.
  • the semiconductor device 80 can be used as part of a source driver in the display device 40.
  • the wirings DL_1 to DL_n correspond to the wirings DL in the case where the semiconductor device 20A is used in each of the pixels 41 arranged in n columns.
  • the semiconductor device 80 in the display device 40 it is possible to use a source driver with a number of outputs smaller than the number of columns n of the pixels 41.
  • a source driver with a number of outputs n/2 can be used. This makes it possible to, for example, reduce the size and cost of the display device. It can also be said that it is possible to drive a display device having a number of columns of pixels greater than the number of outputs of the source driver. This makes it possible to, for example, increase the resolution of the display device.
  • the selector unit 81 of the semiconductor device 80 has been shown here as having two outputs, the present invention is not limited to this and may have three or more outputs.
  • a source driver with n/3 outputs can be used.
  • [Source Driver] 47 to 50F are circuit diagrams for explaining a configuration example of a semiconductor device that can be used in a peripheral driver circuit.
  • Fig. 51 is a timing chart for explaining an operation example of the semiconductor device.
  • the semiconductor device can be used, for example, as a part of a source driver.
  • the semiconductor device 90 shown in FIG. 47 has a shift register section 90A, a latch section 90B, a latch section 90C, and a source follower section 90D.
  • the shift register unit 90A is electrically connected to a plurality of wirings CLK, a plurality of wirings PWC, and a wiring SP.
  • the shift register unit 90A is also electrically connected to the latch unit 90B via n/h wirings SMP (sometimes referred to as wirings SMP[1:n/h]).
  • the latch unit 90B is electrically connected to h wirings DAT (sometimes referred to as wirings DAT[1:h]).
  • the latch unit 90B is also electrically connected to the latch unit 90C via n wirings LAT1 (sometimes referred to as wirings LAT1[1:n]).
  • the latch unit 90C is electrically connected to wirings SW1 and SW2.
  • the latch unit 90C is also electrically connected to the source follower unit 90D via n wirings LAT2 (sometimes referred to as wirings LAT2[1:n]).
  • the source follower unit 90D is electrically connected to the wiring SW3, the wiring SW4, the wiring SW5, and the wiring SW6.
  • the source follower unit is also electrically connected to n wirings DL (sometimes referred to as wirings DL[1:n]).
  • n is an integer of 2 or more, and corresponds to, for example, the number of columns n of pixels 41 arranged in a matrix in the display device 40 described above.
  • h is an integer of 1 or more, and corresponds to, for example, the number of data lanes input to the drive circuit unit 44 from outside the display device 40 in the display device 40 described above.
  • the shift register unit 90A has the function of sequentially outputting signals to the wiring SMP[1:n/h] in response to signals input via each of the multiple wirings CLK, the multiple wirings PWC, and the wiring SP.
  • the multiple wirings CLK are each provided with a clock signal whose potential changes periodically with different phases.
  • the multiple wirings PWC are each provided with a clock signal whose potential changes periodically with different phases.
  • the wiring SP is provided with a start pulse signal that serves as a trigger to start the operation of sequentially outputting signals.
  • the latch unit 90B has a function of storing and holding the potential input via the wiring DAT[1:h], triggered by a signal output sequentially to the wiring SMP[1:n/h], and outputting the potential to the wiring LAT1[1:n].
  • the latch unit 90B has the function of a sample and hold circuit.
  • the wiring DAT[1:h] is a wiring to which a data potential corresponding to the image data displayed on the display device 40 is applied.
  • the latch unit 90C has a function of storing and holding the potential of the wiring LAT1[1:n], triggered by a signal input via the wiring SW1, and outputting the potential to the wiring LAT2[1:n]. In other words, the latch unit 90C has a function of a sample-and-hold circuit. Note that the latch unit 90C may also have a function of resetting (initializing) the potential of the wiring LAT2[1:n] in response to a signal input via the wiring SW2, for example.
  • the source follower unit 90D has a function of outputting a potential corresponding to the potential of the wiring LAT2[1:n] to the wiring DL[1:n]. By lowering the output impedance, the source follower unit 90D can shorten the time during which the potential of the wiring DL[1:n] changes in response to a change in the potential of the wiring LAT2[1:n] even when the load (parasitic capacitance) of the wiring DL[1:n] is large. In other words, the source follower unit 90D has an impedance conversion function.
  • the source follower unit 90D may have a function of controlling the input from the wiring LAT2[1:n] in response to signals input via each of the wiring SW3 and the wiring SW4.
  • it may have a function of correcting the potential input from the wiring LAT2[1:n]. It may also have a function of controlling the output to the wiring DL[1:n] in response to signals input via each of the wiring SW5 and the wiring SW6. For example, it may have a function of precharging the wiring DL[1:n] to an arbitrary potential.
  • FIG. 48A is a circuit diagram for explaining a configuration example of the shift register unit 90A.
  • the shift register unit 90A has n/h register units 91.
  • the shift register unit 90A is electrically connected to n/h wirings SMP, a plurality of wirings CLK, a plurality of wirings PWC, and a wiring SP.
  • the n/h register units 91 are electrically connected to each other via the n/h wirings SR.
  • 48A illustrates a part of the shift register unit 90A, and shows register units 91_1, 91_w, and 91_w+1, wirings SR_1, SR_2, wirings SR_w-1 to SR_w+2, wirings SMP_1, SMP_w, and wirings SMP_w+1.
  • w is an integer between 1 and n/h.
  • FIG. 48B is a circuit diagram for explaining a configuration example of the register unit 91.
  • FIG. 48C is a circuit block corresponding to the register unit 91.
  • the register unit 91 can be applied to each of the register units 91_1 to 91_n/h. That is, for example, in the register unit 91_w, the wiring IN71 is electrically connected to the wiring SR_w-1, the wiring IN72 is electrically connected to the wiring SR_w+1, the wiring IN73 is electrically connected to one of the multiple wirings CLK, and the wiring OUT71 is electrically connected to the wiring SR_w. Furthermore, the wiring IN7A is electrically connected to one of the multiple wirings PWC, and the wiring OUT7A is electrically connected to the wiring SMP_w.
  • the wiring IN71 is electrically connected to the wiring SP.
  • the wiring VLD and the wiring VLS are omitted from the illustration in FIG. 48A and FIG. 48C. The same applies to register units 91_2 through 91_w-1 and register units 91_w+2 through 91_n/h.
  • the wiring OUT71 in the register unit 91_w-1 is electrically connected to the wiring IN71 in the register unit 91_w via the wiring SR_w-1
  • the wiring OUT71 in the register unit 91_w is electrically connected to the wiring IN71 in the register unit 91_w+1 via the wiring SR_w.
  • each of the register units 91_1 to 91_n/h is sequentially selected, and a desired potential can be applied to the wiring SMP_w electrically connected to the selected register unit 91_w.
  • the potential of the wiring VLS is applied to the wiring SMP_w electrically connected to the unselected register unit 91_w.
  • the register unit 91 shown in FIG. 48B includes transistors M71, M72, M73, M74, M75, and M76.
  • Transistor M71 has a function of bringing the wiring VLD and wiring NL71 into a conductive state or a non-conductive state depending on the potential of wiring IN71.
  • Transistor M72 has a function of bringing the wiring VLD and wiring NL72 into a conductive state or a non-conductive state depending on the potential of wiring IN72.
  • Transistor M73 has a function of bringing the wiring VLS and wiring NL71 into a conductive state or a non-conductive state depending on the potential of wiring NL72.
  • Transistor M74 has a function of bringing the wiring VLS and wiring NL72 into a conductive state or a non-conductive state depending on the potential of wiring IN71.
  • the transistor M75 has a function of bringing the wiring IN73 and the wiring OUT71 into a conductive state or a non-conductive state depending on the potential of the wiring NL71.
  • the transistor M76 has a function of bringing the wiring VLS and the wiring OUT71 into a conductive state or a non-conductive state depending on the potential of the wiring NL72.
  • the register unit 91 also includes a transistor M7A and a transistor M7B.
  • the transistor M7A has a function of bringing the wiring IN7A and the wiring OUT7A into a conductive state or a non-conductive state depending on the potential of the wiring NL71.
  • the transistor M7B has a function of bringing the wiring VLS and the wiring OUT7A into a conductive state or a non-conductive state depending on the potential of the wiring NL72.
  • FIG. 48D is a timing chart illustrating an example of the operation of the register unit 91 shown in FIG. 48B.
  • a potential H is applied to the wiring VLD and a potential L is applied to the wiring VLS. It is also assumed that either a potential H or a potential L is applied to each of the wirings IN71, IN72, IN73, and IN7A.
  • the timing chart shown in FIG. 48D shows the potential (potential H or potential L) applied to each of the wirings IN71, IN72, IN73, and IN7A during each operation period (periods T91 to T93). It also shows the change in the potential of each of the wirings NL71, NL72, OUT71, and OUT7A.
  • a potential L is applied to wiring IN71 and wiring IN72.
  • the potential of wiring NL72 is also assumed to be potential H. Therefore, a potential L is applied to wiring NL71.
  • transistors M75 and M7A are each in an off state (non-conductive state), and transistors M76 and M7B are each in an on state (conductive state). Therefore, regardless of the potentials (potential H or potential L) of wirings IN73 and wiring IN7A, a potential L is applied to wirings OUT71 and OUT7A. Note that in the following explanation of the operation, unless otherwise specified, the potential of each wiring is assumed to be maintained at the potential of the previous period.
  • a potential H is applied to wiring IN72, so that the potential of wiring NL72 becomes potential H and the potential of wiring NL71 becomes potential L. Then, transistors M75 and M7A are each turned off, and transistors M76 and M7B are each turned on. Therefore, regardless of the potentials (potential H or potential L) of wiring IN73 and wiring IN7A, potential L is applied to wiring OUT71 and wiring OUT7A. Note that even if potential L is applied to wiring IN72 after that, the potentials of wiring NL72 and wiring NL71 are maintained.
  • FIG. 48E is a circuit diagram illustrating a modified example of the register unit 91.
  • the register unit 91a shown in FIG. 48E differs from the register unit 91 in that it has a bootstrap circuit. That is, in addition to the register unit 91, the register unit 91a has a transistor M77 and a capacitor C71, as well as a transistor M7C and a capacitor C7A. Note that the capacitor C71 and the capacitor C7A are sometimes referred to as bootstrap capacitances.
  • the gate of transistor M77 is electrically connected to wiring VLD.
  • the gate of transistor M75 is electrically connected to wiring NL71 via the source and drain of transistor M77.
  • the gate of transistor M75 is electrically connected to wiring OUT71 via capacitor C71.
  • the gate of transistor M7C is electrically connected to the wiring VLD.
  • the gate of transistor M7A is electrically connected to the wiring NL71 via the source and drain of transistor M7C.
  • the gate of transistor M7A is electrically connected to the wiring OUT7A via capacitor C7A.
  • the transistor M75 when the transistor M75 transmits the potential H from the wiring IN73 to the wiring OUT71, a drop in potential occurs due to the threshold voltage. Therefore, by employing a bootstrap circuit as in the register unit 91a, the transistor M75 can maintain the on state due to capacitive coupling by the bootstrap capacitance. Therefore, the potential H can be transmitted to the wiring OUT71 without a drop in potential due to the threshold voltage.
  • the transistor M7A when the transistor M7A transmits the potential H from the wiring IN7A to the wiring OUT7A, a drop in potential occurs due to the threshold voltage. Therefore, by employing a bootstrap circuit as in the register unit 91a, the transistor M7A can be maintained in the on state by capacitive coupling due to the bootstrap capacitance. Therefore, the potential H can be transmitted to the wiring OUT7A without a drop in potential due to the threshold voltage.
  • FIG. 49 is a circuit diagram for explaining an example configuration of latch section 90B, latch section 90C, and source follower section 90D.
  • Latch section 90B has n latch unit sections 92.
  • Latch section 90C has n latch unit sections 93.
  • Source follower section 90D has n source follower unit sections 94.
  • a part of latch section 90B is excerpted to show latch unit section 92_1, latch unit section 92_h, latch unit section 92_n-h+1, and latch unit section 92_n.
  • a part of latch section 90C is excerpted to show latch unit section 93_1, latch unit section 93_h, latch unit section 93_n-h+1, and latch unit section 93_n.
  • a part of the source follower section 90D is excerpted to show the source follower unit section 94_1, the source follower unit section 94_h, the source follower unit section 94_n-h+1, and the source follower unit section 94_n.
  • a part of the wiring SMP[1:n/h] is excerpted to show the wiring SMP_1 and the wiring SMP_n/h.
  • a part of the wiring DAT[1:h] is excerpted to show the wiring DAT_1 and the wiring DAT_h.
  • a part of the wiring LAT1[1:n] is excerpted to show the wiring LAT1_1, the wiring LAT1_h, the wiring LAT1_n-h+1, and the wiring LAT1_n.
  • a part of the wiring LAT2[1:n] is excerpted to show the wiring LAT2_1, the wiring LAT2_h, the wiring LAT2_n-h+1, and the wiring LAT2_n.
  • a part of the wiring DL[1:n] is excerpted to show the wiring DL_1, the wiring DL_h, the wiring DL_n-h+1, and the wiring DL_n.
  • the n latch unit sections 92 are each electrically connected to n wirings LAT1. Also, the h latch unit sections 92 are electrically connected together to any one of the n/h wirings SMP. Also, each of the h latch unit sections 92 is electrically connected to h wirings DAT.
  • the latch unit section 92_1 is electrically connected to the wiring LAT1_1
  • the latch unit section 92_h is electrically connected to the wiring LAT1_h
  • the latch unit section 92_n-h+1 is electrically connected to the wiring LAT1_n-h+1
  • the latch unit section 92_n is electrically connected to the wiring LAT1_n.
  • latch unit section 92_1 and the latch unit section 92_h are electrically connected to the wiring SMP_1, and the latch unit section 92_n-h+1 and the latch unit section 92_n are electrically connected to the wiring SMP_n/h.
  • latch unit portion 92_1 and latch unit portion 92_n-h+1 are electrically connected to wiring DAT_1
  • latch unit portion 92_h and latch unit portion 92_n are electrically connected to wiring DAT_h.
  • the n latch unit sections 93 are each electrically connected to n wirings LAT1 and n wirings LAT2. They are also electrically connected to wirings SW1 and SW2.
  • the latch unit section 93_1 is electrically connected to wirings LAT1_1, LAT2_1, SW1, and SW2
  • the latch unit section 93_h is electrically connected to wirings LAT1_h, LAT2_h, SW1, and SW2
  • the latch unit section 93_n-h+1 is electrically connected to wirings LAT1_n-h+1, LAT2_n-h+1, SW1, and SW2
  • the latch unit section 93_n is electrically connected to wirings LAT1_n, LAT2_n, SW1, and SW2.
  • the n source follower unit parts 94 are each electrically connected to the n wirings LAT2 and the n wirings DL. They are also electrically connected to wirings SW3, SW4, SW5, and SW6.
  • the source follower unit section 94_1 is electrically connected to the wiring LAT2_1, the wiring DL_1, the wiring SW3, the wiring SW4, the wiring SW5, and the wiring SW6,
  • the source follower unit section 94_h is electrically connected to the wiring LAT2_h, the wiring DL_h, the wiring SW3, the wiring SW4, the wiring SW5, and the wiring SW6,
  • the source follower unit section 94_n-h+1 is electrically connected to the wiring LAT2_n-h+1, the wiring DL_n-h+1, the wiring SW3, the wiring SW4, the wiring SW5, and the wiring SW6, and the source follower unit section 94_n is electrically connected to the wiring LAT2_n, the wiring DL_n, the wiring SW3, the wiring SW4, the wiring SW5, and the wiring SW6,
  • FIG. 50A is a circuit diagram for explaining a configuration example of the latch unit section 92.
  • FIG. 50B is a circuit block corresponding to the latch unit section 92.
  • the latch unit section 92 can be applied to each of the latch unit sections 92_1 to 92_n. That is, for example, in the latch unit section 92_1, the wiring IN81 is electrically connected to the wiring DAT_1, the wiring SW81 is electrically connected to the wiring SMP_1, and the wiring OUT81 is electrically connected to the wiring LAT1_1.
  • the wiring IN81 is electrically connected to the wiring DAT_h
  • the wiring SW81 is electrically connected to the wiring SMP_n/h
  • the wiring OUT81 is electrically connected to the wiring LAT1_n.
  • the wiring VL81 is omitted from the illustration in FIG. 49 and FIG. 50B. Note that the same is true for the latch unit sections 92_2 to 92_n-1.
  • the latch unit section 92 shown in FIG. 50A has a transistor M81 and a capacitor C81.
  • the transistor M81 has a function of making the wiring IN81 and the wiring OUT81 conductive or non-conductive depending on the potential of the wiring SW81.
  • the capacitor C81 has a function of holding the potential difference (voltage) between the wiring OUT81 and the wiring VL81, for example, when the wiring OUT81 is in a floating state.
  • the latch unit section 92 has a function of storing the potential of the wiring IN81 in the wiring OUT81 according to the potential of the wiring SW81, and a function of holding the potential of the wiring OUT81. In other words, the latch unit section 92 has the function of a sample-and-hold circuit.
  • FIG. 50C is a circuit diagram for explaining a configuration example of the latch unit section 93.
  • FIG. 50D is a circuit block corresponding to the latch unit section 93.
  • the latch unit section 93 can be applied to each of the latch unit sections 93_1 to 93_n. That is, for example, in the latch unit section 93_1, the wiring IN82 is electrically connected to the wiring LAT1_1, the wiring SW82 is electrically connected to the wiring SW1, the wiring SW83 is electrically connected to the wiring SW2, and the wiring OUT82 is electrically connected to the wiring LAT2_1.
  • the wiring IN82 is electrically connected to the wiring LAT1_n
  • the wiring SW82 is electrically connected to the wiring SW1
  • the wiring SW83 is electrically connected to the wiring SW2
  • the wiring OUT82 is electrically connected to the wiring LAT2_n.
  • FIG. 49 and FIG. 50D the wiring VL82 and the wiring VL83 are omitted from illustration. The same applies to latch unit section 93_2 through latch unit section 93_n-1.
  • the latch unit section 93 shown in FIG. 50C includes a transistor M82, a transistor M83, and a capacitor C82.
  • the transistor M82 has a function of bringing the wiring IN82 and the wiring OUT82 into a conductive state or a non-conductive state depending on the potential of the wiring SW82.
  • the transistor M83 has a function of bringing the wiring VL83 and the wiring OUT82 into a conductive state or a non-conductive state depending on the potential of the wiring SW83.
  • the capacitor C82 has a function of holding the potential difference (voltage) between the wiring OUT82 and the wiring VL82 when, for example, the wiring OUT82 is in a floating state.
  • the latch unit section 93 has a function of storing the potential of the wiring IN82 in the wiring OUT82 according to the potential of the wiring SW82, and a function of holding the potential of the wiring OUT82. In other words, the latch unit section 93 has the function of a sample-and-hold circuit.
  • Figure 50E is a circuit diagram explaining an example of the configuration of the source follower unit section 94.
  • Figure 50F is a circuit block corresponding to the source follower unit section 94.
  • the source follower unit section 94 can be applied to each of the source follower unit sections 94_1 to 94_n. That is, for example, in the source follower unit section 94_1, the wiring IN83 is electrically connected to the wiring LAT2_1, the wiring SW84 is electrically connected to the wiring SW3, the wiring SW85 is electrically connected to the wiring SW4, the wiring SW86 is electrically connected to the wiring SW5, the wiring SW87 is electrically connected to the wiring SW6, and the wiring OUT83 is electrically connected to the wiring DL_1.
  • the wiring IN83 is electrically connected to the wiring LAT2_n
  • the wiring SW84 is electrically connected to the wiring SW3
  • the wiring SW85 is electrically connected to the wiring SW4
  • the wiring SW86 is electrically connected to the wiring SW5
  • the wiring SW87 is electrically connected to the wiring SW6, and the wiring OUT83 is electrically connected to the wiring DL_n.
  • the wirings VL8A, VL8B, VL84, and VL85 are omitted from the illustration in FIG. 49 and FIG. 50F. Note that the same is true for the source follower unit portions 94_2 to 94_n-1.
  • the source follower unit portion 94 shown in FIG. 50E includes transistors M8A, M8B, M84, M85, M86, M87, M88, and a capacitor C83.
  • the gate of transistor M8A is electrically connected to wiring NL81.
  • One of the source and drain of transistor M8A is electrically connected to one of the source and drain of transistor M8B and wiring NL82, and the other of the source and drain of transistor M8A is electrically connected to wiring VL8A.
  • the other of the source and drain of transistor M8B and the gate of transistor M8B are electrically connected to wiring VL8B.
  • the configuration of transistors M8A and M8B has a source follower function, with the gate of transistor M8A as an input terminal and one of the source and drain of transistor M8A as an output terminal.
  • each switch in the configuration of the semiconductor device 60S described in FIG. 29B is a transistor.
  • the wiring VL8A, wiring VL8B, wiring VL84, and wiring VL85 correspond to wirings that provide potentials such as VDD (potential H), VSS (potential L), and Vx.
  • the transistor M8A corresponds to the transistor M01 of the semiconductor device 60S described in FIG. 29B.
  • the transistor M8B corresponds to the transistor M02 of the semiconductor device 60S described in FIG. 29B.
  • the transistor M86 corresponds to the switch S01 of the semiconductor device 60S described in FIG. 29B.
  • the transistor M87 corresponds to the switch S02 of the semiconductor device 60S described in FIG. 29B.
  • the transistor M85 corresponds to the switch S07 of the semiconductor device 60S described in FIG. 29B.
  • the transistor M88 corresponds to the switch S08 of the semiconductor device 60S described in FIG. 29B.
  • the transistor M84 corresponds to the switch S09 of the semiconductor device 60S described in FIG. 29B.
  • the capacitor C83 corresponds to the capacitor C02 of the semiconductor device 60S described in FIG. 29B. Note that, in addition to the semiconductor device 60S, the semiconductor devices 60A to 60R can also be used as the source follower unit portion 94.
  • Transistor M84 has a function of bringing wiring NL82 and wiring IN83 into a conductive state or a non-conductive state depending on the potential of wiring SW85.
  • Transistor M85 has a function of bringing wiring VL84 and wiring NL81 into a conductive state or a non-conductive state depending on the potential of wiring SW87.
  • Transistor M88 has a function of bringing wiring IN83 and wiring NL83 into a conductive state or a non-conductive state depending on the potential of wiring SW84.
  • Capacitor C83 has a function of holding the potential difference (voltage) between wiring NL81 and wiring NL83, for example, when wiring NL81 is in a floating state.
  • Transistor M86 has a function of bringing the wiring NL82 and the wiring OUT83 into a conductive state or a non-conductive state depending on the potential of wiring SW86.
  • Transistor M87 has a function of bringing the wiring VL85 and the wiring OUT83 into a conductive state or a non-conductive state depending on the potential of wiring SW87.
  • FIG. 51 is a timing chart illustrating an example of the operation of the semiconductor device 90.
  • the multiple wirings CLK are four wirings, CLK_1, CLK_2, CLK_3, and CLK_4 (i.e., a four-phase clock signal is applied)
  • the multiple wirings PWC are four wirings, PWC_1, PWC_2, PWC_3, and PWC_4 (i.e., a four-phase clock signal is applied).
  • Either a potential H or a potential L is applied to each of the wirings CLK_1 to CLK_4, the wirings PWC_1 to PWC_4, and the wiring SP.
  • a potential H or a potential L is applied to each of the wirings SW1, SW2, SW3, SW4, SW5, and SW6.
  • a potential H is applied to the wiring VLD, and a potential L is applied to the wiring VLS.
  • a constant potential (for example, a potential between potential H and potential L) is applied to each of the wirings VL81, VL82, VL83, VL84, and VL85.
  • a constant potential (a potential for causing the source follower unit portion 94 to function as a source follower) is applied to each of the wirings VL8A and VL8B.
  • the timing chart shown in Figure 51 shows the potential (potential H or potential L) applied to each of wirings CLK_1 to CLK_4, wirings PWC_1 to PWC_4, and wiring SP during each operation period (period T9A and period T9B). It also shows the changes in the potential of each of wirings SMP[1] and wiring SMP[n/h]. It also shows the data potential Vd applied to wiring DAT[1:h]. It also shows the changes in the potential of each of wirings LAT1[1:h] and wiring LAT1[n-h+1:n]. It also shows the potential (potential H or potential L) applied to each of wirings SW1, wiring SW2, wiring SW3, wiring SW4, wiring SW5, and wiring SW6. Also shown is the change in potential of each of the wiring LAT2[1:h], the wiring LAT2[n-h+1:n], the wiring DL[1:h], and the wiring DL[n-h+1:n].
  • any one wire among n/h wires expressed by adding "[1:n/h]” may be added. That is, for example, when “[1]” is added, it represents the first wire, and when “[n/h]” is added, it represents the n/hth wire. That is, for example, the description “[1]” is equivalent to the description "[_1]”, and the description "[n/h]” is equivalent to the description "[_n/h]”.
  • period T9A signals are sequentially output to the wirings SMP[1] to SMP[n/h] by the shift register unit 90A. Then, the latch unit 90B uses the signals sequentially output to the wirings SMP[1] to SMP[n/h] as a trigger to store and hold the potential input via the wiring DAT[1:h], and outputs the potential to the wiring LAT1[1:n].
  • FIG. 51 shows how, in the period T9A, the signal output to the wiring SMP[1] is used as a trigger to store and hold the data potential Vd_1 input via the wiring DAT[1:h] and output to the wiring LAT1[1:h], and how, in the period T9A, the signal output to the wiring SMP[n/h] is used as a trigger to store and hold the data potential Vd_n/h input via the wiring DAT[1:h] and output to the wiring LAT1[n-h+1:n].
  • a potential L is applied to wiring SW1, wiring SW2, wiring SW3, wiring SW4, and wiring SW6, and a potential H is applied to wiring SW5.
  • period T9B first, a potential L is applied to the wiring SW5, and a potential H is applied to the wiring SW6. Then, the source follower unit 90D discharges the wiring DL[1:n] to the potential of the wiring VL85 (corresponding to the initialization operation 1 in FIG. 14A).
  • a potential H is applied to the wiring SW2, and after a certain period of time, a potential L is applied. During this period, the potential of the wiring LAT2[1:n] is reset (initialized) to the potential of the wiring VL83 by the latch unit 90C.
  • potential H is applied to wiring SW4, and after a certain period of time, potential L is applied.
  • the source follower unit 90D performs an operation to correct the potential input from wiring LAT2[1:n] (corresponding to initialization operation 2 in FIG. 14A).
  • a potential H is applied to the wiring SW1, and after a certain period of time, a potential L is applied. A potential L is also applied to the wiring SW6.
  • the latch unit 90C stores and holds the potentials of the wirings LAT1_1 to LAT1_n, and outputs the potentials to the wirings LAT2_1 to LAT2_n (corresponding to the initialization end operation in FIG. 14A).
  • a potential H is applied to the wiring SW3 and the wiring SW5.
  • the source follower unit 90D outputs a potential corresponding to the potential of the wirings LAT2_1 to LAT2_n to the wirings DL_1 to DL_n (corresponding to the signal output operation in FIG. 14A).
  • the semiconductor device 90 can be used in the display device 40.
  • the semiconductor device 90 can be used as part of a source driver in the display device 40.
  • the wirings DL_1 to DL_n correspond to the wirings DL in the case where the semiconductor device 20A is used in each of the pixels 41 arranged in n columns.
  • the number of data lanes input from outside the display device 40 can be made smaller than the number of columns n of the pixels 41. This makes it possible to reduce the size and cost of the display device, for example.
  • one aspect of the present invention is not limited to the configuration of the semiconductor device 90 described above, and the configuration may be changed as appropriate within the scope in which the display device described above can be realized.
  • [Series connection of transistors] 52A to 52C are circuit diagrams illustrating a series connection of transistors.
  • the transistors constituting the pixel circuit and the peripheral driver circuit may be single-gate transistors having one gate between the source and drain, or double-gate transistors.
  • Figure 52A shows an example of a circuit symbol for a double-gate transistor TrA.
  • Transistor TrA has a configuration in which transistors Tr1 and Tr2 are connected in series.
  • transistor TrA shown in FIG. 52A one of the source and drain of transistor Tr1 is electrically connected to terminal S.
  • the other of the source and drain of transistor Tr1 is electrically connected to one of the source and drain of transistor Tr2.
  • the other of the source and drain of transistor Tr2 is electrically connected to terminal D.
  • the gates of transistors Tr1 and Tr2 are electrically connected, and are also electrically connected to terminal G.
  • the transistor TrA shown in FIG. 52A has the function of switching the conductive or non-conductive state between terminals S and D by changing the potential of terminal G.
  • the transistor TrA which is a double-gate transistor, includes transistors Tr1 and Tr2 and functions as one transistor. That is, in FIG. 52A, one of the source and drain of the transistor TrA is electrically connected to terminal S, the other of the source and drain is electrically connected to terminal D, and the gate is electrically connected to terminal G.
  • the transistors constituting the pixel circuit and the peripheral drive circuit may be triple-gate transistors.
  • Figure 52B shows an example of a circuit symbol for a triple-gate transistor TrB.
  • Transistor TrB has a configuration in which transistors Tr1, Tr2, and Tr3 are connected in series.
  • transistor TrB shown in FIG. 52B one of the source and drain of transistor Tr1 is electrically connected to terminal S.
  • the other of the source and drain of transistor Tr1 is electrically connected to one of the source and drain of transistor Tr2.
  • the other of the source and drain of transistor Tr2 is electrically connected to one of the source and drain of transistor Tr3.
  • the other of the source and drain of transistor Tr3 is electrically connected to terminal D.
  • the gates of transistors Tr1, Tr2, and Tr3 are electrically connected, and are also electrically connected to terminal G.
  • the transistor TrB shown in FIG. 52B has a function of switching the conductive state or non-conductive state between the terminals S and D by changing the potential of the terminal G.
  • the transistor TrB which is a triple-gate transistor, includes the transistors Tr1, Tr2, and Tr3 and functions as one transistor. That is, in FIG. 52B, one of the source and drain of the transistor TrB is electrically connected to the terminal S, the other of the source and drain is electrically connected to the terminal D, and the gate is electrically connected to the terminal G.
  • the transistors constituting the pixel circuit and the peripheral drive circuit may be configured with four or more transistors connected in series.
  • the transistor TrC shown in FIG. 52C has a configuration in which six transistors (transistors Tr1 to Tr6) are connected in series. In the transistor TrC shown in FIG. 52C, the gates of the six transistors are electrically connected to each other and are also electrically connected to the terminal G.
  • the transistor TrC shown in FIG. 52C has the function of switching the conductive or non-conductive state between terminals S and D by changing the potential of terminal G.
  • the transistor TrC includes transistors Tr1 to Tr6 and functions as one transistor. That is, in FIG. 52C, one of the source and drain of the transistor TrC is electrically connected to terminal S, the other of the source and drain is electrically connected to terminal D, and the gate is electrically connected to terminal G.
  • Transistors that have multiple gates and are electrically connected are sometimes called “multi-gate transistors” or “multi-gate transistors.”
  • a transistor with a substantially long channel length can be realized. This makes it possible to reduce the off-state current and improve the drain withstand voltage (i.e., improve reliability).
  • high saturation characteristics can be obtained.
  • an ideal current source circuit and an active load with a very high resistance value can be realized. This makes it possible to realize, for example, a differential circuit and a current mirror circuit with good characteristics.
  • vertical OS transistors can be used as transistors constituting the various element circuits as described above.
  • the area occupied by the circuit can be reduced. This makes it possible to achieve, for example, a narrower frame, higher resolution, and higher definition for the display device.
  • the semiconductor device and display device according to one embodiment of the present invention are not limited to the semiconductor device and display device described in this embodiment. At least a part of the configuration examples and operation examples exemplified in this embodiment and the drawings corresponding thereto can be appropriately combined with other configuration examples, other operation examples, other drawings, and other embodiments described in this specification, etc.
  • One aspect of the present invention is a semiconductor device having a transistor and a first insulating layer.
  • the transistor has a first conductive layer, a second conductive layer having a region overlapping with the first conductive layer via the first insulating layer, a semiconductor layer, a gate insulating layer, and a gate electrode.
  • the second conductive layer has a first opening in a region overlapping with the first conductive layer.
  • the first insulating layer has a second opening that reaches the first conductive layer in a region overlapping with the first opening.
  • the semiconductor layer is in contact with the top surface of the first conductive layer, the side surface of the first insulating layer, and the side surface of the second conductive layer in the first opening and the second opening.
  • a gate insulating layer is provided on the semiconductor layer, and a gate electrode is provided on the gate insulating layer.
  • the first conductive layer functions as one of a source electrode and a drain electrode
  • the second conductive layer functions as the other. Since the source electrode, the layer having a channel formation region, and the drain electrode can be provided in an overlapping manner, the occupied area can be reduced.
  • the region of the semiconductor layer in contact with the first insulating layer functions as a channel formation region. This allows the channel length of the transistor to be made smaller than the limit resolution of the exposure device, resulting in a transistor with a large on-state current.
  • the semiconductor layer preferably contains a metal oxide.
  • the first insulating layer preferably uses a material that releases oxygen. This allows oxygen to be supplied from the first insulating layer to the semiconductor layer (particularly, the channel formation region), and reduces oxygen vacancies ( VO ) in the semiconductor layer.
  • the amount of oxygen supplied from the first insulating layer to the semiconductor layer is larger.
  • the first insulating layer has a large oxygen diffusion coefficient.
  • the first insulating layer has an oxygen diffusion coefficient of 5 ⁇ 10 ⁇ 12 cm 2 /sec or more at 350° C. This increases the diffusion rate of oxygen in the first insulating layer, and oxygen can be effectively supplied to the semiconductor layer. Therefore, even in a transistor having a short channel length, it is possible to achieve both good electrical characteristics and high reliability.
  • FIG. 53A A top view (also referred to as a plan view) of a semiconductor device 10 is shown in FIG. 53A.
  • FIG. 53B A cross-sectional view of a cut surface taken along dashed line A1-A2 in FIG. 53A is shown in FIG. 53B, and a cross-sectional view of a cut surface taken along dashed line B1-B2 in FIG. 53C is shown.
  • FIG. 53A some of the components are omitted in the top views of the semiconductor device in the following drawings.
  • the semiconductor device 10 has a transistor 100, a transistor 200, a capacitor 150, and an insulating layer 110.
  • the transistor 100, the transistor 200, and the capacitor 150 are provided on a substrate 102.
  • the transistor 100 and the transistor 200 have different structures.
  • the transistor 100, the transistor 200, and the capacitor 150 can be formed by sharing some of the processes.
  • the transistor 100 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 104 functions as a gate electrode (also referred to as a first gate electrode), and a part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer).
  • the conductive layer 112a functions as one of a source electrode and a drain electrode, and the conductive layer 112b functions as the other.
  • Each layer constituting the transistor 100 may have a single-layer structure or a stacked structure.
  • a conductive layer 112a is provided on the substrate 102, and an insulating layer 110 is provided on the conductive layer 112a.
  • the insulating layer 110 is provided so as to cover the upper and side surfaces of the conductive layer 112a.
  • the insulating layer 110 has an opening 141 that reaches the conductive layer 112a in the area where it overlaps with the conductive layer 112a. It can also be said that the conductive layer 112a is exposed in the opening 141.
  • a conductive layer 112b is provided on the insulating layer 110.
  • the conductive layer 112b has an area that overlaps with the conductive layer 112a via the insulating layer 110.
  • the conductive layer 112b has an opening 143 in the area that overlaps with the conductive layer 112a.
  • the opening 143 is provided in the area that overlaps with the opening 141.
  • Openings 141 and 143 have a cylindrical shape with a circular or roughly circular upper surface. This configuration can, for example, achieve finer design, higher integration, higher density, and smaller size of the semiconductor device. Note that the side surfaces of openings 141 and 143 are preferably perpendicular or roughly perpendicular to the upper surface of conductive layer 112a.
  • the semiconductor layer 108 is provided so as to cover the opening 141 and the opening 143.
  • the semiconductor layer 108 has a region in contact with the upper surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the upper surface of the conductive layer 112a.
  • the semiconductor layer 108 is electrically connected to the conductive layer 112a through the opening 141 and the opening 143.
  • the semiconductor layer 108 has a shape that conforms to the shapes of the upper surface and side surface of the conductive layer 112b, the side surface of the insulating layer 110, and the upper surface of the conductive layer 112a.
  • the semiconductor layer 108 has a region that overlaps with the conductive layer 112a through the insulating layer 110.
  • the insulating layer 110 has a region sandwiched between the conductive layer 112a and the semiconductor layer 108. In other words, it can also be said that a portion of the semiconductor layer 108 is provided inside the opening 141 and the opening 143.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source region and the drain region, and the region in contact with the conductive layer 112b functions as the other.
  • a channel formation region is provided between the source region and the drain region.
  • the insulating layer 106 is provided to cover the openings 141 and 143.
  • the insulating layer 106 is provided on the semiconductor layer 108, the conductive layer 112b, and the insulating layer 110.
  • the insulating layer 106 has an area that contacts the upper surface and side surfaces of the semiconductor layer 108, the upper surface and side surfaces of the conductive layer 112b, and the upper surface of the insulating layer 110.
  • the insulating layer 106 has a shape that follows the shapes of the upper surface and side surfaces of the semiconductor layer 108, the upper surface and side surfaces of the conductive layer 112b, and the upper surface of the insulating layer 110.
  • the conductive layer 104 is provided on the insulating layer 106 and has a region in contact with the upper surface of the insulating layer 106.
  • the conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106.
  • the conductive layer 104 has a shape that matches the shape of the upper surface of the insulating layer 106. Note that the conductive layer 104 may be configured to fill the openings 141 and 143.
  • the transistor 100 is a so-called top-gate transistor having a gate electrode above the semiconductor layer 108. Furthermore, since the bottom surface of the semiconductor layer 108 is in contact with the conductive layer 112a and the conductive layer 112b, which function as a source electrode and a drain electrode, the transistor 100 can be called a TGBC (Top Gate Bottom Contact) type transistor.
  • the source electrode and the drain electrode of the transistor 100 are located at different heights with respect to the surface of the substrate 102, which is the surface on which the transistor 100 is formed, and a drain current flows in a direction perpendicular or approximately perpendicular to the surface of the substrate 102. It can also be said that the drain current flows in the vertical direction or approximately vertical direction in the transistor 100. Therefore, the transistor that is one embodiment of the present invention can be called, for example, a vertical transistor, a vertical channel transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).
  • the channel length of the transistor 100 can be controlled by the thickness of the insulating layer 110 (specifically, the insulating layer 110b) provided between the conductive layer 112a and the conductive layer 112b. Therefore, a transistor having a channel length smaller than the limit resolution of the exposure device used to manufacture the transistor can be manufactured with high precision.
  • the characteristic variation between multiple transistors 100 is also reduced. This makes it possible to stabilize the operation of a semiconductor device including the transistor 100 and to increase its reliability. Furthermore, the reduced characteristic variation increases the degree of freedom in the circuit design of the semiconductor device, and the operating voltage can be reduced. This allows the power consumption of the semiconductor device to be reduced.
  • the transistor 100 can have a source electrode, a layer having a channel formation region, and a drain electrode that are stacked, so the area it occupies can be significantly reduced compared to a so-called planar type transistor in which the layer having the channel formation region is arranged in a planar shape.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 can each function as wiring, and the transistor 100 can be provided in a region where these wirings overlap. That is, in a circuit having the transistor 100 and the wiring, the area occupied by the transistor 100 and the wiring can be reduced. Therefore, the area occupied by the circuit can be reduced, and a small-sized semiconductor device can be obtained.
  • the transistor 200 includes a conductive layer 204, a conductive layer 212a, a conductive layer 212b, an insulating layer 106, a semiconductor layer 208, an insulating layer 120, and a conductive layer 202.
  • the conductive layer 204 functions as a gate electrode (also referred to as a first gate electrode), and a part of the insulating layer 106 functions as a gate insulating layer (also referred to as a first gate insulating layer).
  • the conductive layer 202 functions as a back gate electrode (also referred to as a second gate electrode), and a part of the insulating layer 120 functions as a back gate insulating layer (also referred to as a second gate insulating layer).
  • the conductive layer 212a functions as one of a source electrode and a drain electrode, and the conductive layer 212b functions as the other.
  • Each layer constituting the transistor 200 may have a single-layer structure or a stacked structure. Note that the transistor 200 does not necessarily have the conductive layer 202.
  • the entire region of the semiconductor layer 208 that overlaps with the gate electrode via the gate insulating layer between the source electrode and drain electrode functions as a channel formation region.
  • the semiconductor layer 208 has a pair of regions 208L that sandwich the channel formation region, and a pair of regions 208D on the outside of the pair.
  • Region 208L and region 208D are regions containing impurity elements.
  • the impurity elements may be one or more of hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases.
  • noble gases include helium, neon, argon, krypton, and xenon. It is particularly preferable to use one or more of boron, phosphorus, aluminum, magnesium, and silicon as the impurity elements.
  • an impurity element is supplied (also referred to as added or injected) to the semiconductor layer 208.
  • a region 208D is formed in a region of the semiconductor layer 208 that does not overlap with any of the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the insulating layer 106
  • a region 208L is formed in a region that does not overlap with any of the conductive layer 204, the conductive layer 212a, and the conductive layer 212b and overlaps with the insulating layer 106.
  • the region of the semiconductor layer 208 that contacts the conductive layer 212a and the region 208D adjacent to this region function as one of the source region and the drain region.
  • the region of the semiconductor layer 208 that contacts the conductive layer 212b and the region 208D adjacent to this region function as the other of the source region and the drain region.
  • a conductive layer 202 is provided on the insulating layer 110, and an insulating layer 120 is provided on the conductive layer 202.
  • the insulating layer 120 is provided so as to cover the upper and side surfaces of the conductive layer 202.
  • the insulating layer 120 has a portion that protrudes beyond the end of the conductive layer 202. The end of the insulating layer 120 contacts the upper surface of the insulating layer 110.
  • the semiconductor layer 208 is provided on the insulating layer 120.
  • the semiconductor layer 208 has a region that overlaps with the conductive layer 202 via the insulating layer 120.
  • the same material as the semiconductor layer 108 can be used for the semiconductor layer 208.
  • the semiconductor layer 208 can be formed in the same process as the semiconductor layer 108.
  • the semiconductor layer 108 and the semiconductor layer 208 can be formed by forming a film that will become the semiconductor layer 108 and the semiconductor layer 208 and processing the film.
  • An insulating layer 106 is provided on the semiconductor layer 208.
  • a part of the insulating layer 106 functions as a gate insulating layer for the transistor 100, and another part functions as a gate insulating layer for the transistor 200.
  • the insulating layer 106 has an opening 147a and an opening 147b in the area overlapping with the semiconductor layer 208.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b are provided on the insulating layer 106.
  • the conductive layer 204 has a region that overlaps with the semiconductor layer 208 through the insulating layer 106.
  • the conductive layer 204 also has a region that overlaps with the conductive layer 202 through the semiconductor layer 208.
  • the conductive layer 212a and the conductive layer 212b are provided so as to cover the opening 147a and the opening 147b.
  • the conductive layer 212a is electrically connected to the semiconductor layer 208 through the opening 147a
  • the conductive layer 212b is electrically connected to the semiconductor layer 208 through the opening 147b.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be made of the same material as the conductive layer 104.
  • the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same process as the conductive layer 104.
  • a film that will become the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed by forming the film and processing the film to form the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b.
  • Transistor 200 is a planar type transistor in which semiconductor layer 208 is arranged in a plane. It is also a so-called top-gate type transistor that has a gate electrode above semiconductor layer 208. For example, by adding an impurity element to semiconductor layer 208 using conductive layer 204, which functions as a gate electrode, as a mask, it is possible to form regions 208D that function as source and drain regions in a self-aligned manner. Transistor 200 can be said to be a TGSA (Top Gate Self-Aligned) type transistor.
  • TGSA Top Gate Self-Aligned
  • the channel length of the transistor 200 can be controlled by the length of the conductive layer 204. Therefore, the channel length of the transistor 200 is equal to or greater than the resolution limit of an exposure device used to fabricate the transistor. In other words, the channel length of the transistor 200 can be made longer than the channel length of the transistor 100. By making the channel length longer, a transistor with high saturation properties can be obtained.
  • the transistor 100 with a short channel length and the transistor 200 with a long channel length can be formed on the same substrate by sharing some of the processes.
  • a high-performance semiconductor device can be obtained by applying the transistor 100 to a transistor that requires a large on-state current and the transistor 200 to a transistor that requires high saturation.
  • a semiconductor device of one embodiment of the present invention when a semiconductor device of one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained.
  • a semiconductor device of one embodiment of the present invention when a semiconductor device of one embodiment of the present invention is applied to a driver circuit of a display device (e.g., one or both of a gate line driver circuit and a source line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.
  • the capacitor 150 has a conductive layer 112b and a conductive layer 202 that function as a pair of electrodes, and an insulating layer 120.
  • the conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 100 and functions as one of the pair of electrodes of the capacitor 150.
  • the conductive layer 202 functions as the back gate electrode of the transistor 200 and functions as the other of the pair of electrodes of the capacitor 150.
  • the region of the insulating layer 120 sandwiched between the conductive layer 112b and the conductive layer 202 functions as a dielectric of the capacitor 150.
  • 53A and other drawings show an example in which the capacitor 150 is composed of the conductive layer 112b, the conductive layer 202, and the insulating layer 120, but the configuration of the capacitor 150 is not particularly limited.
  • Other configurations of the capacitor 150 include, for example, an example in which the capacitor is composed of the conductive layer 212a (or the conductive layer 212b), the conductive layer 112b, and the insulating layer 106.
  • Another example is an example in which the capacitor is composed of the conductive layer 202, the conductive layer 112a, and the insulating layer 110.
  • the semiconductor device 10 does not need to have the capacitor 150.
  • the capacitor 150 composed of the conductive layer 112b, the conductive layer 202, and the insulating layer 120 is not provided, the conductive layer 112b and the conductive layer 202 may be formed in the same process.
  • the other of the source electrode and drain electrode of transistor 100 is electrically connected to one of the pair of electrodes of capacitor 150, and one of the source electrode and drain electrode of transistor 200 is electrically connected to the other of the pair of electrodes of capacitor 150, but the electrical connection relationship between transistor 100, transistor 200, and capacitor 150 is not particularly limited.
  • An insulating layer 195 is provided to cover the transistor 100, the transistor 200, and the capacitor 150.
  • the insulating layer 195 functions as a protective layer for the transistor 100, the transistor 200, and the capacitor 150.
  • the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited.
  • a semiconductor made of a single element or a compound semiconductor can be used.
  • semiconductors made of a single element include silicon and germanium.
  • compound semiconductors include gallium arsenide and silicon germanium.
  • Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. Note that these semiconductor materials may contain impurities as dopants.
  • the crystallinity of the semiconductor material used for the semiconductor layer 108 and the semiconductor layer 208 is not particularly limited, and any of an amorphous semiconductor, a single crystalline semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used.
  • the use of a single crystalline semiconductor or a semiconductor having crystallinity is preferable because it can suppress deterioration of the transistor characteristics.
  • the semiconductor layer 108 and the semiconductor layer 208 can each be made of silicon.
  • silicon examples include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • polycrystalline silicon examples include low temperature polysilicon (LTPS).
  • LTPS low temperature polysilicon
  • a transistor using amorphous silicon in the channel formation region can be formed on a large glass substrate and can be manufactured at low cost.
  • a transistor using polycrystalline silicon in the channel formation region has high field effect mobility and can operate at high speed.
  • a transistor using microcrystalline silicon in the channel formation region has higher field effect mobility and can operate at high speed than a transistor using amorphous silicon.
  • the semiconductor layer 108 and the semiconductor layer 208 each preferably contain a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties.
  • a metal oxide also called an oxide semiconductor
  • the band gap of the metal oxide used in the semiconductor layer 108 and the semiconductor layer 208 is preferably 2.0 eV or more, and more preferably 2.5 eV or more.
  • OS transistors have extremely high field-effect mobility compared to transistors using amorphous silicon.
  • OS transistors have an extremely small off-state current and can retain charge accumulated in a capacitor connected in series with the transistor for a long period of time.
  • the use of OS transistors can reduce the power consumption of a semiconductor device.
  • Transistor 100 53A to 53C, 54A, and 54B will be used to describe a detailed structure of the transistor 100.
  • FIGs. 54A and 54B are enlarged views of the transistor 100 shown in FIGs.
  • the insulating layer 110 preferably has one or more inorganic insulating films.
  • materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides.
  • oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, gallium zinc oxide, and hafnium aluminate.
  • nitrides include silicon nitride and aluminum nitride.
  • Examples of oxynitrides include silicon oxynitride, aluminum oxynitride, gallium oxynitride, yttrium oxynitride, and hafnium oxynitride.
  • Examples of nitride oxides include silicon nitride oxide and aluminum nitride oxide.
  • an oxynitride refers to a material whose composition contains more oxygen than nitrogen.
  • An oxynitride refers to a material whose composition contains more nitrogen than oxygen.
  • the insulating layer 110 has a region in contact with the semiconductor layer 108.
  • a metal oxide is used for the semiconductor layer 108
  • the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108 contains oxygen.
  • One or more of an oxide and an oxynitride can be used for the region of the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108.
  • the insulating layer 110 preferably has a laminated structure.
  • Figure 53B etc. shows an example in which the insulating layer 110 has an insulating layer 110a, an insulating layer 110b on insulating layer 110a, and an insulating layer 110c on insulating layer 110b.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region.
  • the insulating layer 110b preferably contains oxygen, and preferably uses one or more of the oxides and oxynitrides described above. Specifically, the insulating layer 110b can use one or both of silicon oxide and silicon oxynitride.
  • oxygen can be supplied to the semiconductor layer 108.
  • oxygen vacancies (V O ) are repaired and the oxygen vacancies (V O ) can be reduced. Therefore, a transistor having good electrical characteristics and high reliability can be obtained.
  • oxygen can be supplied to the insulating layer 110b by performing heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.
  • oxygen can be supplied to the insulating layer 110b by forming an oxide film on the upper surface of the insulating layer 110b by a sputtering method in an oxygen-containing atmosphere. The oxide film can then be removed.
  • the insulating layer 110b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • the substance diffuses easily in the insulating layer 110b. It can also be said that it is preferable that the diffusion coefficient of the substance in the insulating layer 110b is large. In particular, it is preferable that oxygen diffuses easily in the insulating layer 110b. In other words, it is preferable that the diffusion coefficient of oxygen in the insulating layer 110b is large.
  • the oxygen contained in the insulating layer 110b diffuses in the insulating layer 110b and is supplied to the semiconductor layer 108 via the interface between the insulating layer 110b and the semiconductor layer 108. By making the insulating layer 110b into which oxygen diffuses easily, the oxygen contained in the insulating layer 110b can be efficiently supplied to the semiconductor layer 108 (particularly the channel formation region).
  • the oxygen diffusion coefficient of the insulating layer 110b at 350° C. is preferably 5 ⁇ 10 ⁇ 12 cm 2 /sec or more, more preferably 1 ⁇ 10 ⁇ 11 cm 2 /sec or more, further preferably 5 ⁇ 10 ⁇ 11 cm 2 /sec or more, and further preferably 1 ⁇ 10 ⁇ 10 cm 2 /sec or more.
  • the diffusion coefficient can be calculated by, for example, thermal desorption spectroscopy (TDS). Alternatively, secondary ion mass spectrometry (SIMS) may be used.
  • the threshold voltage of the transistor shifts, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • cutoff current the drain current that flows when the gate voltage is 0 V may become large.
  • the threshold voltage may shift to the negative side, and the cutoff current may become large.
  • oxygen is supplied to at least the region of the semiconductor layer 108 that is in contact with the insulating layer 110b, that is, the channel formation region, and the oxygen vacancies (V O ) in the channel formation region can be reduced.
  • the shift in the threshold voltage is suppressed, and a transistor with both a small cutoff current and a large on-current can be obtained. Therefore, a semiconductor device with both low power consumption and high performance can be obtained.
  • the region of the semiconductor layer 108 in contact with the conductive layer 112a functions as one of the source and drain regions of the transistor 100, and the region in contact with the conductive layer 112b functions as the other.
  • the source and drain regions are regions with lower electrical resistance than the channel formation region.
  • the source and drain regions can also be said to be regions with a higher carrier concentration or a higher oxygen defect density than the channel formation region.
  • the insulating layer 110a is provided between the insulating layer 110b and the conductive layer 112a.
  • the insulating layer 110c is provided between the insulating layer 110b and the conductive layer 112b. It is preferable that the insulating layer 110a and the insulating layer 110c each emit little impurities (e.g., hydrogen and water) from themselves and are difficult for impurities to penetrate. This can prevent the impurities contained in the insulating layer 110a and the insulating layer 110c from diffusing into the channel formation region. Therefore, it is possible to obtain a transistor that exhibits good electrical characteristics and is highly reliable.
  • impurities e.g., hydrogen and water
  • the insulating layer 110a and the insulating layer 110c are preferably made of a film through which oxygen does not easily permeate. This can suppress the oxygen contained in the insulating layer 110b from diffusing to the conductive layer 112a through the insulating layer 110a. Similarly, the oxygen contained in the insulating layer 110b can be suppressed from diffusing to the conductive layer 112b through the insulating layer 110c. This can suppress the electrical resistance of the conductive layer 112a and the conductive layer 112b from increasing.
  • the oxygen contained in the insulating layer 110b is suppressed from diffusing to the insulating layer 110a side and the insulating layer 110c side, so that the amount of oxygen supplied from the insulating layer 110b to the channel formation region is increased, and oxygen vacancies (V O ) and V O H in the channel formation region can be reduced.
  • oxygen can be effectively supplied from the insulating layer 110b to the channel formation region. Note that a configuration in which one or both of the insulating layers 110a and 110c are not provided may also be used.
  • the insulating layer 110a and the insulating layer 110c each preferably contain nitrogen, and preferably use one or more of the above-mentioned nitrides and nitride oxides.
  • the insulating layer 110a and the insulating layer 110c each may use, for example, silicon nitride or silicon nitride oxide.
  • one or both of the insulating layer 110a and the insulating layer 110c may use one or more of an oxide and an oxynitride.
  • the insulating layer 110a and the insulating layer 110c each may use, for example, aluminum oxide. Note that the insulating layer 110a may use the same material as the insulating layer 110c, or a different material.
  • different materials refer to materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.
  • the thickness T110a of the insulating layer 110a can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 20 nm or more, 50 nm or more, or 70 nm or more, and can be less than 1 ⁇ m, 500 nm or less, 400 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, or 120 nm or less. As shown in FIG. 54B, the thickness T110a can be the shortest distance between the surface on which the insulating layer 110a is formed (here, the upper surface of the conductive layer 112a) and the lower surface of the insulating layer 110b in a cross-sectional view.
  • the thickness T110a of the insulating layer 110a When the thickness T110a of the insulating layer 110a is large, the amount of impurities released from the insulating layer 110a increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, when the thickness T110a is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112a side through the insulating layer 110a, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110a within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, the conductive layer 112a is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112a can be prevented from increasing.
  • the thickness T110c of the insulating layer 110c can be, for example, 3 nm or more, 5 nm or more, 10 nm or more, 15 nm or more, or 20 nm or more, and can be 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 150 nm or less, 120 nm or less, or 100 nm or less. As shown in FIG. 54B, the thickness T110c can be the shortest distance between the surface on which the insulating layer 110c is formed (here, the upper surface of the insulating layer 110b) and the lower surface of the conductive layer 112b in a cross-sectional view.
  • the thickness T110c of the insulating layer 110c When the thickness T110c of the insulating layer 110c is large, the amount of impurities released from the insulating layer 110c increases, and the amount of impurities diffusing into the channel formation region may increase. On the other hand, when the thickness T110c is small, oxygen contained in the insulating layer 110b may diffuse to the conductive layer 112b side through the insulating layer 110c, and the amount of oxygen supplied to the channel formation region may decrease. By setting the thickness T110c within the above range, oxygen vacancies (V O ) and V O H in the channel formation region can be reduced. In addition, the conductive layer 112b is oxidized by the oxygen contained in the insulating layer 110b, and the electrical resistance of the conductive layer 112b can be prevented from increasing.
  • At least one of the region of the semiconductor layer 108 in contact with the insulating layer 110a and the region in contact with the insulating layer 110c may be a region having a lower electrical resistance than the channel formation region (hereinafter also referred to as a low-resistance region).
  • the region may be a region having a higher carrier concentration or a higher oxygen defect density than the channel formation region.
  • impurities e.g., water and hydrogen
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112a (one of the source region and the drain region) and the channel formation region. Similarly, by using a material that releases impurities in the insulating layer 110c, the region in contact with the insulating layer 110c can be a low-resistance region.
  • the semiconductor layer 108 can be configured to have a low-resistance region between the region in contact with the conductive layer 112b (the other of the source region and the drain region) and the channel formation region.
  • the low resistance regions can function as buffer regions to reduce the drain electric field. These low resistance regions may also function as source or drain regions.
  • the conductive layer 112a functions as a drain electrode and the conductive layer 112b functions as a source electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110a into a low resistance region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and deterioration of the transistor can be suppressed.
  • the conductive layer 112a functions as a source electrode and the conductive layer 112b functions as a drain electrode, by making the region of the semiconductor layer 108 in contact with the insulating layer 110c into a low resistance region, a high electric field is unlikely to occur near the drain region, the generation of hot carriers is suppressed, and deterioration of the transistor can be suppressed.
  • the amount of impurities released from the insulating layers 110a and 110c is too large, the impurities may diffuse into the channel formation region. Even if a material that releases impurities is used for the insulating layers 110a and 110c, it is preferable that the amount of released impurities is small.
  • the insulating layer 110 has at least the insulating layer 110b.
  • the insulating layer 110 may have a structure that does not have either or both of the insulating layer 110a and the insulating layer 110c.
  • the insulating layer 110 may have a stacked structure of two layers, four or more layers, or a single layer structure.
  • the top surface shape of the openings 141 and 143 is not limited, and may be, for example, a circle, an ellipse, a triangle, a quadrangle (including a rectangle, a diamond, and a square), a pentagon, or other polygon, or a shape with rounded corners of these polygons.
  • the polygon may be either a concave polygon (a polygon with at least one interior angle exceeding 180 degrees) or a convex polygon (a polygon with all interior angles less than 180 degrees).
  • it is preferable that the top surface shape of the openings 141 and 143 is a circle.
  • the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 are arranged concentrically. This makes the distance between the conductive layer 104 and the semiconductor layer 108 uniform or approximately uniform, so that a gate electric field can be applied uniformly or approximately uniformly to the semiconductor layer 108.
  • the top shape of the opening 141 refers to the shape of the top end of the insulating layer 110 on the opening 141 side.
  • the top shape of the opening 143 refers to the shape of the bottom end of the conductive layer 112b on the opening 143 side.
  • the top surface shapes of openings 141 and 143 can be made to match or roughly match each other.
  • the bottom surface of conductive layer 112b refers to the surface on the insulating layer 110 side.
  • the top surface of insulating layer 110 refers to the surface on the conductive layer 112b side.
  • openings 141 and 143 do not have to be the same. Furthermore, when the top surface shapes of openings 141 and 143 are circular, openings 141 and 143 may or may not be concentric.
  • Figures 54A and 54B are enlarged views of the transistor 100 shown in Figures 53A and 53B.
  • the channel length L100 of the transistor 100 is indicated by a double-headed dashed arrow.
  • the channel length L100 of the transistor 100 corresponds to the length of the side of the insulating layer 110b on the opening 141 side in a cross-sectional view.
  • the channel length L100 is determined by the thickness T110b of the insulating layer 110b and the angle ⁇ 110 between the side of the insulating layer 110b on the opening 141 side and the surface on which the insulating layer 110b is to be formed (here, the upper surface of the insulating layer 110a). Therefore, the channel length L100 can be set to a value smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.
  • a transistor with an extremely small channel length that is difficult to realize with a conventional exposure device for mass production of flat panel displays for example, a minimum line width of about 2 ⁇ m or 1.5 ⁇ m.
  • a transistor with a channel length of less than 10 nm without using an extremely expensive exposure device used in cutting-edge LSI technology.
  • the channel length L100 can be, for example, 1 nm or more, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less.
  • the channel length L100 can be 100 nm or more and 1 ⁇ m or less.
  • the on-state current of the transistor 100 can be increased.
  • the transistor 100 By using the transistor 100, a circuit capable of high-speed operation can be manufactured. Furthermore, the area occupied by the circuit can be reduced. Therefore, a small-sized semiconductor device can be obtained. For example, when the semiconductor device of one embodiment of the present invention is applied to a large display device or a high-definition display device, even if the number of wirings is increased, signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • the channel length L100 can be controlled by adjusting the thickness T110b and angle ⁇ 110 of the insulating layer 110b. Note that in FIG. 54B, the thickness T110b of the insulating layer 110b is indicated by a double-headed arrow with a dashed line.
  • the thickness T110b of the insulating layer 110b can be, for example, 1 nm or more, 5 nm or more, 7 nm or more, or 10 nm or more, and can be less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less.
  • the side of the insulating layer 110 on the opening 141 side is preferably vertical or tapered.
  • the angle ⁇ 110 is preferably 90 degrees or less. By reducing the angle ⁇ 110, the coverage of the layer (e.g., the semiconductor layer 108) formed on the insulating layer 110 can be improved. Furthermore, the smaller the angle ⁇ 110, the larger the channel length L100 can be, and the larger the angle ⁇ 110, the smaller the channel length L100 can be.
  • the angle ⁇ 110 can be, for example, 30 degrees or more, 35 degrees or more, 40 degrees or more, 45 degrees or more, 50 degrees or more, 55 degrees or more, 60 degrees or more, 65 degrees or more, or 70 degrees or more, and 90 degrees or less, 85 degrees or less, or 80 degrees or less.
  • the angle ⁇ 110 may also be 75 degrees or less, 70 degrees or less, 65 degrees or less, or 60 degrees or less.
  • the shape of the side of the insulating layer 110 on the opening 141 side is shown as straight lines in cross section, but this is not a limitation of one embodiment of the present invention. In cross section, the shape of the side of the insulating layer 110 on the opening 141 side may be curved, or the side may have both straight and curved areas.
  • the conductive layer 112b is not provided inside the opening 141. Specifically, it is preferable that the conductive layer 112b does not have a region that contacts the side of the insulating layer 110 on the opening 141 side. If the conductive layer 112b is also provided inside the opening 141, the channel length L100 of the transistor 100 becomes shorter than the length of the side of the insulating layer 110b, which may make it difficult to control the channel length L100. Therefore, it is preferable that the top shape of the opening 143 matches the top shape of the opening 141, or that the opening 143 encompasses the opening 141 when viewed from above.
  • the width D141 of the opening 141 is indicated by a double-headed arrow with a dashed two-dot line.
  • Figure 54A shows an example in which the top surface shape of the opening 141 is circular.
  • the width D141 corresponds to the diameter of the circle
  • the channel width W100 of the transistor 100 is the length of the circumference of the circle.
  • the channel width W100 is ⁇ x D141. In this way, when the top surface shape of the opening 141 is circular, a transistor with a smaller channel width W100 can be realized compared to other shapes.
  • the maximum width of the top surface shape may be set as width D141.
  • the width D141 of the opening 141 may vary in the depth direction.
  • the average value of the diameter at the highest point of the insulating layer 110b (or insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these three diameters may be used as the width D141 of the opening 141.
  • the diameter of the opening 141 may be any one of the diameters at the highest point of the insulating layer 110b (or insulating layer 110) in a cross-sectional view, the diameter at the lowest point, and the diameter at the midpoint between these two diameters.
  • the width D141 of the opening 141 is equal to or greater than the limit resolution of the exposure device.
  • the width D141 can be, for example, 200 nm or more, 300 nm or more, 400 nm or more, or 500 nm or more, and less than 5 ⁇ m, 4.5 ⁇ m or less, 4 ⁇ m or less, 3.5 ⁇ m or less, 3 ⁇ m or less, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, or 1 ⁇ m or less.
  • the width D141 can be, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less.
  • the channel length L100 of the transistor 100 is preferably at least smaller than the channel width W100 of the transistor 100.
  • the channel length L100 of the transistor 100 is 0.1 times or more and 0.99 times or less, preferably 0.5 times or more and 0.8 times or less, of the channel width W100 of the transistor 100.
  • the insulating layers 110a and 110c are made of a material that releases less hydrogen.
  • the insulating layers 110a and 110c are made of a material that releases even a small amount of hydrogen, it is preferable that the thicknesses of these layers are thin.
  • the thickness T110a of the insulating layer 110a and the thickness T110c of the insulating layer 110c are 1 nm or more, 3 nm or more, or 5 nm or more, and preferably 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. This makes it possible to reduce the amount of impurities that diffuse into the channel formation region, and to provide a transistor that exhibits good electrical characteristics and is highly reliable even when the channel length L100 is short.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110b functions as a channel formation region
  • one embodiment of the present invention is not limited to this.
  • the region of the semiconductor layer 108 in contact with the insulating layer 110a may also function as a channel formation region.
  • the region in contact with the insulating layer 110c may also function as a channel formation region.
  • a step may be formed between the insulating layer 110 and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step.
  • Transistor 200 Next, a detailed structure of the transistor 200 will be described with reference to Figures 55A to 55C.
  • Figures 55A to 55C are enlarged views of the transistor 200 shown in Figures 53A to 53C.
  • the channel length of the transistor 200 is the length of the region where the semiconductor layer 208 and the conductive layer 204 overlap between a pair of regions 208D.
  • the channel length L200 of the transistor 200 is indicated by a dashed double-headed arrow.
  • the channel length L200 of the transistor 200 is determined by the length of the conductive layer 204, and is equal to or greater than the limit resolution of the exposure device used to fabricate the transistor.
  • the channel length L200 can be 1.5 ⁇ m or greater.
  • the conductive layer 202 which functions as the backgate electrode of the transistor 200, preferably extends beyond the end of the channel formation region.
  • the size of the conductive layer 202 is preferably larger than the size of the channel formation region.
  • the conductive layer 202 preferably has a portion that protrudes beyond the end of the conductive layer 204 in the channel length direction.
  • the portion of the semiconductor layer 208 that overlaps with the conductive layer 204 is described as a channel formation region, but in reality, a channel can also be formed in the portion that overlaps with the conductive layer 202 without overlapping with the conductive layer 204.
  • the channel width of the transistor 200 is the width of the region where the semiconductor layer 208 and the conductive layer 204 overlap in a direction perpendicular to the channel length direction.
  • the channel width W200 of the transistor 200 is indicated by a dashed double-headed arrow.
  • the channel length L100 of the transistor 100 can be set to a value smaller than the limit resolution of the exposure device, and the channel length L200 of the transistor 200 can be set to a value equal to or greater than the limit resolution of the exposure device.
  • the transistors 100 and 200 can be formed by sharing some of the steps. Specifically, the semiconductor layer 108 and the semiconductor layer 208 can be formed in the same step.
  • a part of the insulating layer 106 functions as a gate insulating layer of the transistor 100, and another part of the insulating layer 106 functions as a gate insulating layer of the transistor 200.
  • the conductive layer 104, the conductive layer 204, the conductive layer 212a, and the conductive layer 212b can be formed in the same step. Therefore, the productivity of the semiconductor device 10 can be increased and the manufacturing cost can be reduced.
  • the conductive layer 204 and the conductive layer 202 preferably protrude outward beyond the end of the semiconductor layer 208.
  • the entire channel width direction of the semiconductor layer 208 is covered by the conductive layer 204 and the conductive layer 202 via the insulating layer 106 and the insulating layer 120.
  • the semiconductor layer 208 can be electrically surrounded by an electric field generated by a pair of gate electrodes.
  • FIGS. 55A and 55C show a configuration in which conductive layer 204 and conductive layer 202 are not electrically connected.
  • a constant potential may be applied to one of the pair of gate electrodes, and a signal for driving transistor 200 may be applied to the other.
  • transistor 200 when transistor 200 is driven by a signal applied to the other gate electrode, the threshold voltage can be controlled by the potential applied to one gate electrode.
  • the conductive layer 204 and the conductive layer 202 may be electrically connected.
  • an electric field for inducing a channel in the semiconductor layer 208 can be effectively applied, and the on-current of the transistor 200 can be increased.
  • This also makes it possible to miniaturize the transistor 200.
  • an opening reaching the conductive layer 202 can be provided in the insulating layer 106 and the insulating layer 120, and the conductive layer 204 can be formed to cover the opening.
  • the conductive layer 202 may be electrically connected to the conductive layer 212a or the conductive layer 212b.
  • an opening reaching the conductive layer 202 may be provided in the insulating layer 120, and the conductive layer 212a or the conductive layer 212b may be formed to cover the opening.
  • the insulating layer 120 which is provided in contact with the upper and side surfaces of the conductive layer 202, can be made of a material that can be used for the insulating layer 110.
  • the insulating layer 120 preferably has a laminated structure.
  • FIG. 55B and other figures show that the insulating layer 120 has a laminated structure of an insulating layer 120a and an insulating layer 120b on the insulating layer 120a.
  • the insulating layers 120a and 120b can each be made of a material that can be used for the insulating layer 110.
  • oxygen can be supplied to the semiconductor layer 208, particularly to the channel formation region of the semiconductor layer 208.
  • the oxygen contained in the insulating layer 120b diffuses in the insulating layer 120b and is supplied to the semiconductor layer 208 through the interface between the insulating layer 120b and the semiconductor layer 208.
  • oxygen vacancies (V O ) are repaired and the oxygen vacancies (V O ) can be reduced. Therefore, a transistor exhibiting good electrical characteristics and high reliability can be obtained.
  • the oxygen diffusion coefficient of the insulating layer 120b at 350° C. is preferably 1 ⁇ 10 ⁇ 12 cm 2 /sec or more, and more preferably 5 ⁇ 10 ⁇ 12 cm 2 /sec or more.
  • the insulating layer 120b can be made of a material that can be used for the insulating layer 110b.
  • the insulating layer 120b preferably contains oxygen, and can be made of one or more of an oxide and an oxynitride.
  • the insulating layer 120b can be made of, for example, silicon oxide or silicon oxynitride.
  • the amount of oxygen supplied from the insulating layer 120b to the semiconductor layer 208 may be smaller than the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108.
  • the amount of oxygen released from the insulating layer 120b may be smaller than the amount of oxygen released from the insulating layer 110b.
  • the diffusion coefficient of the substance in the insulating layer 110b is larger than that in the insulating layer 120b.
  • the diffusion coefficient of oxygen in the insulating layer 110b is larger than that in the insulating layer 120b. This allows the transistor 100, even with a short channel length, to exhibit good electrical characteristics and be a highly reliable transistor.
  • the insulating layer 120a in contact with the conductive layer 202 is preferably made of a material that does not easily diffuse the metal elements contained in the conductive layer 202. This makes it possible to prevent the metal elements contained in the conductive layer 202 from diffusing into the channel formation region of the semiconductor layer 208 via the insulating layer 120.
  • the insulating layer 120a is preferably made of a material that can be used for the insulating layer 110a and the insulating layer 110c.
  • the insulating layer 120a preferably contains nitrogen, and one or more of a nitride and a nitride oxide can be used.
  • the insulating layer 120a can be made of, for example, silicon nitride.
  • the insulating layer 120a may be made of one or more of an oxide and an oxynitride.
  • the insulating layer 120a can be made of, for example, aluminum oxide. Note that the insulating layer 120a, the insulating layer 110a, and the insulating layer 110c may be made of the same material or different materials.
  • the insulating layer 120a releases little impurities (e.g., water and hydrogen) from itself. This makes it possible to prevent impurities contained in the insulating layer 120a from diffusing into the channel formation region of the semiconductor layer 208 via the insulating layer 120b, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.
  • impurities e.g., water and hydrogen
  • the insulating layer 120 is shown here as having a two-layer stacked structure, one embodiment of the present invention is not limited to this.
  • the insulating layer 120 may have a three or more layer stacked structure, or a single layer structure.
  • the insulating layer 120 is preferably provided in at least a region in contact with the channel formation region of the semiconductor layer 208 and is provided so as to cover the upper surface and side surfaces of the conductive layer 202.
  • FIG. 55B and other figures show a configuration in which the semiconductor layer 208 has a portion protruding from the end of the insulating layer 120.
  • the semiconductor layer 208 has a region in contact with the side surface of the insulating layer 120. A portion of the end of the semiconductor layer 208 is in contact with the upper surface of the insulating layer 120, and another portion is in contact with the upper surface of the insulating layer 110.
  • the insulating layer 120 may be provided in the region in which the semiconductor layer 208 is provided, and the entire lower surface of the semiconductor layer 208 is in contact with the upper surface of the insulating layer 120.
  • the thickness of the semiconductor layer 208 is uniform regardless of location, but one embodiment of the present invention is not limited to this.
  • the thickness may be different between the region of the semiconductor layer 208 that overlaps with the insulating layer 106 and the region that does not overlap. For example, when forming the openings 147a and 147b, a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 that does not overlap with the insulating layer 106 may be thinner than the thickness of the overlapping region.
  • the thickness may be different between the region of the semiconductor layer 208 that overlaps with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b and the region that does not overlap with any of these.
  • the conductive layer 212a and the conductive layer 212b are formed, a part of the semiconductor layer 208 is removed, and the thickness of the region of the semiconductor layer 208 that does not overlap with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b may be thinner than the thickness of the region that overlaps with any of them.
  • the thickness of the region of the semiconductor layer 208 that overlaps with the insulating layer 106, the region that overlaps with any of the insulating layer 106, the conductive layer 212a, and the conductive layer 212b, and the region that does not overlap with any of them may be different.
  • the region 208D has a lower electrical resistance than the channel formation region.
  • the region 208D can also be said to have a higher carrier concentration, a higher oxygen defect density, or a higher impurity concentration than the channel formation region.
  • Region 208L has the same or lower electrical resistance as the channel formation region. Region 208L can also be said to have the same or higher carrier concentration, the same or higher oxygen defect density, or the same or higher impurity concentration as the channel formation region. Furthermore, region 208L has the same or higher electrical resistance as region 208D. Region 208L can also be said to have the same or lower carrier concentration, the same or lower oxygen defect density, or the same or lower impurity concentration as region 208D.
  • Region 208L functions as a buffer region for alleviating the drain electric field.
  • Region 208L does not overlap with conductive layer 204, and therefore is a region in which a channel is hardly formed even when a gate voltage is applied to conductive layer 204.
  • Region 208L preferably has a higher carrier concentration than the channel formation region. This allows region 208L to function as an LDD (Lightly Doped Drain) region.
  • LDD Lightly Doped Drain
  • the carrier concentration in the semiconductor layer 208 is preferably distributed so that it is lowest in the channel formation region, and then increases in the order of region 208L and region 208D.
  • region 208L between the channel formation region and region 208D, the carrier concentration in the channel formation region can be kept extremely low, even if impurities such as hydrogen diffuse from region 208D during the manufacturing process.
  • the carrier concentration in region 208L does not have to be uniform, and may have a gradient in which the carrier concentration decreases from region 208D toward the channel formation region.
  • either or both of the hydrogen concentration and oxygen vacancy concentration in region 208L may have a gradient in which the concentration decreases from region 208D toward the channel formation region.
  • the impurity element When the impurity element is added to the semiconductor layer 208 to form the regions 208L and 208D, the impurity element may be supplied to the semiconductor layer 108 through the insulating layer 106 using the conductive layer 104 as a mask. As a result, the region 108L is formed in a region of the semiconductor layer 108 that does not overlap with the conductive layer 104. Note that in the transistor 100, a region of the semiconductor layer 108 that is in contact with the conductive layer 112b functions as a source region or a drain region. The region 108L is formed in a part of the source region or the drain region. Note that the concentration of the impurity element in the region 108L may be different from the concentration of the impurity element in the region 208L.
  • the region 108L may not be formed.
  • the conductive layer 104 extends to cover the end of the semiconductor layer 108, the entire semiconductor layer 108 is masked by the conductive layer 104, so that the impurity element is not supplied to the semiconductor layer 108 and the region 108L is not formed.
  • a portion of the end of conductive layer 212a and conductive layer 212b is located inside opening 147a and opening 147b.
  • a portion of the end of conductive layer 212a and conductive layer 212b contacts semiconductor layer 208 in opening 147a and opening 147b. This makes it possible to make the region in contact with conductive layer 212a adjacent to one of the pair of regions 208D, and similarly, to make the region in contact with conductive layer 212b adjacent to the other of the pair of regions 208D.
  • top surface shapes of openings 147a and 147b are not particularly limited.
  • the top surface shapes of openings 147a and 147b can be shapes that can be applied to openings 141 and 143.
  • the top surface shapes of openings 147a and 147b are shown as being rectangular with rounded corners, which is different from the top surface shapes of openings 141 and 143, but one aspect of the present invention is not limited to this.
  • the top surface shapes of openings 147a and 147b may be the same as the top surface shapes of openings 141 and 143.
  • the conductive layer 212a and the conductive layer 212b may be formed in a process different from that of the conductive layer 204.
  • the conductive layer 104 and the conductive layer 204 are formed over the insulating layer 106, and an impurity element is supplied to the semiconductor layer 208 using the conductive layer 204 as a mask to form a source region and a drain region.
  • An insulating layer 195 is formed over the conductive layer 104 and the conductive layer 204, and an opening reaching the source region and an opening reaching the drain region are formed in the insulating layer 106 and the insulating layer 195, and the conductive layer 212a and the conductive layer 212b can be formed so as to cover these openings.
  • Metal oxides that can be used for the semiconductor layer 108 and the semiconductor layer 208 will be specifically described.
  • metal oxides include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide preferably contains two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M of the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more of gallium and tin.
  • metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal element" described in this specification may include metalloid elements.
  • the semiconductor layer 108 and the semiconductor layer 208 may each be made of, for example, indium oxide (In oxide), indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide, or ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, or IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, or GZO), aluminum zinc oxide (Al-Zn oxide), or , or AZO), indium aluminum zinc oxide (In-Al-Zn oxide, or IAZO), indium tin zinc oxide (In-Sn-Zn oxide, or ITZO (registered trademark)), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, or IGZO), indium gallium
  • indium tin oxide containing silicon also written as ITSO
  • gallium tin oxide Ga-Sn oxide
  • aluminum tin oxide Al-Sn oxide
  • materials not containing Zn such as indium oxide, are suitable because they have high affinity with Si processes.
  • materials containing Zn are suitable because they can improve crystallinity.
  • the field effect mobility of the transistor can be increased.
  • a transistor with a large on-current can be realized.
  • the metal oxide may have one or more metal elements with a large periodic number instead of or in addition to indium.
  • metal elements with a large periodic number include metal elements belonging to the fifth period and metal elements belonging to the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may contain one or more nonmetallic elements.
  • the carrier concentration increases, the band gap decreases, etc., and the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline and the diffusion of impurities in the metal oxide can be suppressed. This suppresses fluctuations in the electrical characteristics of the transistor and increases its reliability.
  • the electrical characteristics and reliability of the transistors vary depending on the composition of the metal oxide applied to the semiconductor layer 108 and the semiconductor layer 208. Therefore, by varying the composition of the metal oxide depending on the electrical characteristics and reliability required of the transistor, a semiconductor device that combines excellent electrical characteristics and high reliability can be obtained.
  • the metal oxide is an In-M-Zn oxide
  • the atomic ratio of In in the In-M-Zn oxide is equal to or greater than the atomic ratio of M.
  • the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M.
  • element M contains multiple metal elements
  • the total proportion of the atomic numbers of the metal elements can be regarded as the proportion of the atomic number of element M.
  • the ratio of the number of indium atoms to the sum of the numbers of atoms of all metal elements contained may be referred to as the indium content. The same applies to other metal elements.
  • the on-state current or the field effect mobility of the transistor can be increased. Furthermore, by having the element M, the generation of oxygen vacancies (V 2 O 3 ) can be suppressed.
  • the element M is preferably one or more of the above elements, and more preferably one or more selected from aluminum, gallium, tin, and yttrium.
  • a metal oxide having a polycrystalline structure is used for the semiconductor layer 108 and the semiconductor layer 208, the grain boundaries become the recombination centers, and carriers are captured, which may reduce the on-current of the transistor.
  • a metal oxide having a composition that is likely to form a polycrystalline structure it is preferable to include an element that inhibits crystallization.
  • ITO indium tin oxide
  • ITSO indium tin oxide containing silicon
  • the silicon content (the ratio of the number of silicon atoms to the sum of the number of atoms of all metal elements contained) is preferably 1% or more and 20% or less, more preferably 3% or more and 20% or less, even more preferably 3% or more and 15% or less, and even more preferably 5% or more and 15% or less.
  • the composition of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed using, for example, energy dispersive X-ray spectrometry (EDX), X-ray photoelectron spectrometry (XPS), inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES).
  • EDX energy dispersive X-ray spectrometry
  • XPS X-ray photoelectron spectrometry
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • a combination of these techniques may be used for the analysis.
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide can be formed by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • the semiconductor layer 108 and the semiconductor layer 208 may each have a stacked structure having two or more metal oxide layers.
  • the two or more metal oxide layers in the semiconductor layer 108 and the semiconductor layer 208 may each have the same or approximately the same composition.
  • a stacked structure of metal oxide layers with the same composition for example, they can be formed using the same sputtering target, thereby reducing manufacturing costs.
  • the two or more metal oxide layers in each of the semiconductor layer 108 and the semiconductor layer 208 may have different compositions.
  • gallium, aluminum, or tin it is particularly preferable to use gallium, aluminum, or tin as the element M.
  • the element M in the first metal oxide layer and the second metal oxide layer may be the same or different from each other.
  • the first metal oxide layer and the second metal oxide layer may be IGZO layers having different compositions from each other.
  • a laminated structure of any one selected from indium oxide, indium gallium oxide, and IGZO and any one selected from IAZO, IAGZO, and ITZO (registered trademark) may be used.
  • first metal oxide layer having a first metal oxide and a second metal oxide layer having a second metal oxide when a laminate structure is formed of a first metal oxide layer having a first metal oxide and a second metal oxide layer having a second metal oxide, and the composition of the first metal oxide and the composition of the second metal oxide are the same or approximately the same, it may be difficult to clearly identify the boundary (interface) between the first metal oxide layer and the second metal oxide layer.
  • the semiconductor layer 108 and the semiconductor layer 208 are preferably made of a crystalline metal oxide.
  • Examples of the structure of a crystalline metal oxide include a CAAC (c-axis aligned crystal) structure, a polycrystalline structure, and a nano-crystalline (nc: nano-crystal) structure.
  • the density of defect states in the channel formation region can be reduced.
  • a metal oxide with low crystallinity a transistor capable of passing a large current can be realized.
  • the higher the substrate temperature during formation the more crystalline the metal oxide can be formed.
  • the substrate temperature during formation can be adjusted, for example, by the temperature of the stage on which the substrate is placed during formation.
  • the higher the ratio of the flow rate of oxygen gas to the total film formation gas used in formation (hereinafter also referred to as the oxygen flow rate ratio) or the higher the oxygen partial pressure in the processing chamber the more crystalline the metal oxide can be formed.
  • the crystallinity of the semiconductor layer 108 and the semiconductor layer 208 can be analyzed, for example, by an X-ray diffraction (XRD) pattern, a transmission electron microscope (TEM) image, or an electron diffraction (ED) pattern. Alternatively, the analysis may be performed by combining a plurality of these methods.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • V O H When a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to reduce V O H in the channel formation region as much as possible to make it highly pure or substantially highly pure.
  • it is important to remove impurities such as water and hydrogen in the metal oxide (sometimes referred to as dehydration or dehydrogenation treatment) and to supply oxygen to the metal oxide to repair oxygen vacancies (V O ).
  • impurities such as water and hydrogen in the metal oxide
  • V O repair oxygen vacancies
  • supplying oxygen to a metal oxide to repair oxygen vacancies (V O ) may be referred to as oxygen addition treatment.
  • the carrier concentration of the channel formation region is preferably 1 ⁇ 10 18 cm ⁇ 3 or less, more preferably less than 1 ⁇ 10 17 cm ⁇ 3 , further preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 12 cm ⁇ 3 .
  • the carrier concentration of the channel formation region can be, for example, 1 ⁇ 10 ⁇ 9 cm ⁇ 3 .
  • OS transistors have small variations in electrical characteristics due to radiation exposure, i.e., they have high resistance to radiation, and can therefore be used in environments where radiation may be present. It can also be said that OS transistors have high reliability against radiation.
  • OS transistors can be used in pixel circuits of X-ray flat panel detectors.
  • OS transistors can also be used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).
  • the semiconductor layer 108 and the semiconductor layer 208 may each have a layered material that functions as a semiconductor.
  • a layered material is a general term for a group of materials that have a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals bonds.
  • a layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of the layered material include graphene, silicene, and chalcogenides.
  • Chalcogenides are compounds containing chalcogen (an element belonging to Group 16).
  • Examples of the chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • MoS 2 molybdenum sulfide
  • MoSe 2 molybdenum selenide
  • MoTe 2 moly MoTe 2
  • tungsten sulfide typically WS 2
  • Each of the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, conductive layer 212b, and the conductive layer 202 may have a single-layer structure or a stacked structure of two or more layers.
  • Examples of materials that can be used for the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 include chromium, copper, aluminum, gold, silver, and the like. Examples include one or more of zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys containing one or more of the aforementioned metals.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 each contain one or more of copper, silver, gold, and aluminum.
  • a conductive material having a low resistance can be used, and in particular, copper or aluminum is preferable because of its excellent mass productivity.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 can each be made of a metal oxide (oxide conductor) having electrical conductivity.
  • oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called ITO containing silicon, or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide.
  • ITO In-Sn oxide
  • ITO In-Zn oxide
  • In-W oxide In-W-Zn oxide
  • In-Ti oxide In-Ti-Sn oxide
  • In-Sn-Si oxide also called ITO containing silicon, or ITSO
  • zinc oxide with added gallium and In-Ga-Zn oxide.
  • a metal oxide that has become a conductor can be called an oxide conductor.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 may each have a stacked structure of a conductive film containing the oxide conductor (metal oxide) described above and a conductive film containing a metal or an alloy. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced.
  • the conductive layers 112a, 112b, 104, 204, 212a, 212b, and 202 may each be a Cu-X alloy film (X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti).
  • X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti.
  • the conductive layer 112a, the conductive layer 112b, the conductive layer 104, the conductive layer 204, the conductive layer 212a, the conductive layer 212b, and the conductive layer 202 may be made of the same material or different materials.
  • the conductive layer 112a and the conductive layer 112b have a region in contact with the semiconductor layer 108.
  • a metal oxide is used as the semiconductor layer 108
  • an insulating oxide e.g., aluminum oxide
  • the conductive layer 112a and the conductive layer 112b are preferably made of, for example, titanium, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel. These are preferable because they are conductive materials that are difficult to oxidize, or materials that maintain low electrical resistance even when oxidized. Note that when the conductive layer 112a has a stacked structure, it is preferable to use a conductive material that is difficult to oxidize at least for the layer in contact with the semiconductor layer 108.
  • the conductive layer 112a and the conductive layer 112b can each be made of the oxide conductors described above. Specifically, conductive oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, or zinc oxide doped with gallium can be used.
  • conductive oxides such as indium oxide, zinc oxide, ITO, In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn oxide containing silicon, or zinc oxide doped with gallium can be used.
  • the conductive layers 112a and 112b may each be made of a nitride conductor.
  • nitride conductors include tantalum nitride and titanium nitride.
  • the conductive layer 112b is provided on the insulating layer 120b.
  • a conductive material that is not easily oxidized it is preferable to use a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material for the conductive layer 112b.
  • the amount of oxygen released from the insulating layer 120b is smaller than the amount of oxygen released from the insulating layer 110b. Therefore, there is little risk that the conductive layer 112b having an area in contact with the insulating layer 120b will be oxidized, and the electrical resistance of the conductive layer 112b will increase.
  • the conductive layer 112a, the conductive layer 112b, and the conductive layer 104 may each have a laminated structure.
  • the conductive layer 112a may have a two-layer structure. That is, the conductive layer 112a may have a laminated structure of, for example, a conductive layer 112a_1 (not shown) and a conductive layer 112a_2 (not shown) on the conductive layer 112a_1.
  • a conductive material that is not easily oxidized, a conductive material that maintains low electrical resistance even when oxidized, or an oxide conductive material is preferably used.
  • materials that can be used for the conductive layer 112a_2 see the description of the conductive layer 112a.
  • the material used is not particularly limited. For example, it is preferable to use a material having a lower electrical resistivity than the conductive layer 112a_2 for the conductive layer 112a_1. This can reduce the electrical resistance of the conductive layer 112a.
  • In-Sn-Si oxide (ITSO) can be used for the conductive layer 112a_2, and copper or tungsten can be used for the conductive layer 112a_1.
  • the thickness of the conductive layer 112a_1 and the thickness of the conductive layer 112a_2 may be the same or approximately the same, or may be different.
  • a material having a lower electrical resistivity than the conductive layer 112a_2 may be used for the conductive layer 112a_1, and the thickness of the conductive layer 112a_1 may be made thicker than the thickness of the conductive layer 112a_2. This can reduce the electrical resistance of the conductive layer 112a.
  • the end of the conductive layer 112a_2 may or may not coincide with the end of the conductive layer 112a_1.
  • the conductive layer 112a_2 can be provided so as to cover the conductive layer 112a_1. That is, the conductive layer 112a_2 contacts the top surface and side surface of the conductive layer 112a_1. It can also be said that the conductive layer 112a_2 has a portion that protrudes beyond the end of the conductive layer 112a_1.
  • the configuration of the conductive layer 112a described above can also be applied to other configuration examples.
  • the insulating layer 106 may have a single-layer structure or a stacked structure of two or more layers.
  • the insulating layer 106 preferably has one or more inorganic insulating films. Examples of materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides.
  • the insulating layer 106 can be made of any of the materials that can be used for the insulating layer 110.
  • the insulating layer 106 has a region in contact with the semiconductor layer 108 and the semiconductor layer 208.
  • a metal oxide is used for the semiconductor layer 108 and the semiconductor layer 208, it is preferable to use either the oxide or the oxynitride described above for at least the film that is in contact with the semiconductor layer 108 and the semiconductor layer 208 among the films that constitute the insulating layer 106. It is more preferable to use a film that releases oxygen when heated for the insulating layer 106.
  • the insulating layer 106 has a single-layer structure, it is preferable to use an oxide or an oxynitride for the insulating layer 106.
  • the insulating layer 106 can be made of silicon oxide or silicon oxynitride.
  • the insulating film in contact with the semiconductor layer 108 and the semiconductor layer 208 has an oxide or an oxynitride
  • the insulating film in contact with the conductive layer 104 and the conductive layer 204 has a nitride or a nitride oxide.
  • the oxide or oxynitride for example, silicon oxide or silicon oxynitride can be used.
  • silicon nitride or silicon nitride oxide silicon nitride or silicon nitride oxide can be used.
  • Silicon nitride and silicon nitride oxide have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be used as the insulating layer 106.
  • impurities e.g., water and hydrogen
  • the electrical characteristics of the transistor can be improved and the reliability can be increased.
  • the thickness of the gate insulating layer becomes thin, the leakage current may become large.
  • a material with a high relative dielectric constant also called a high-k material
  • high-k materials that can be used for the insulating layer 106 include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • the insulating layer 195 which functions as a protective layer for the transistor 100, the transistor 200, and the capacitor 150, is preferably made of a material that is difficult for impurities to diffuse into. By providing the insulating layer 195, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the semiconductor device. Examples of impurities include water and hydrogen.
  • the insulating layer 195 can be an insulating layer having an inorganic material or an insulating layer having an organic material.
  • an inorganic material such as oxide, oxynitride, nitride oxide, or nitride can be used for the insulating layer 195.
  • silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used.
  • one or more of acrylic resin and polyimide resin can be used as the organic material.
  • a photosensitive material may be used as the organic material. Two or more of the insulating films described above may be stacked.
  • the insulating layer 195 may have a stacked structure of an insulating layer having an inorganic material and an insulating layer having an organic material.
  • Substrate 102 There is no significant limitation on the material of the substrate 102, but it is necessary that the material has at least a heat resistance sufficient to withstand subsequent heat treatment.
  • the substrate 102 for example, a single crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, or an organic resin substrate may be used.
  • a semiconductor element may be provided on the substrate 102.
  • the shape of the semiconductor substrate and the insulating substrate may be circular or rectangular.
  • a flexible substrate may be used as the substrate 102, and the transistor 100 and the like may be formed directly on the flexible substrate.
  • a peeling layer may be provided between the substrate 102 and the transistor 100 and the like. By providing a peeling layer, after a semiconductor device is partially or entirely completed on the substrate, it can be separated from the substrate 102 and transferred to another substrate. In this case, the transistor 100 and the like can also be transferred to a substrate with poor heat resistance or a flexible substrate.
  • transistor 100 for at least one of the transistors constituting the semiconductor device 60.
  • transistor 200 may be used as the drive transistor and load transistor (transistor M01 and transistor M02), and capacitor 150 may be used as capacitor C01.
  • ⁇ Configuration Example 2> 56 is a cross-sectional view of a transistor 100A that can be used in a semiconductor device of one embodiment of the present invention.
  • the transistor 100A is different from the transistor 100 shown in FIG. 53B and the like mainly in that it has a back gate. Note that the above description of the transistor 100 can be referred to, and detailed description thereof will be omitted.
  • Transistor 100A has conductive layer 112a, conductive layer 103, insulating layer 107, insulating layer 110, semiconductor layer 108, conductive layer 112b, insulating layer 106, and conductive layer 104. Each layer constituting transistor 100A may have a single-layer structure or a multilayer structure.
  • the conductive layer 112a is provided on the substrate 102.
  • the conductive layer 112a functions as one of the source electrode and drain electrode of the transistor 100A.
  • the insulating layer 107 is located on the conductive layer 112a.
  • the insulating layer 107 is provided so as to cover the upper and side surfaces of the conductive layer 112a.
  • the conductive layer 103 is located on the insulating layer 107.
  • the conductive layer 112a and the conductive layer 103 are electrically insulated from each other by the insulating layer 107.
  • the conductive layer 103 has an opening 148 that reaches the insulating layer 107 in the area that overlaps with the conductive layer 112a.
  • the insulating layer 110 is provided on the insulating layer 107 and the conductive layer 103.
  • the insulating layer 110 is provided so as to cover the upper and side surfaces of the conductive layer 103 and the upper surface of the insulating layer 107.
  • the insulating layer 110 preferably has a laminated structure.
  • Figure 56 shows an example in which the insulating layer 110 has a laminated structure of an insulating layer 110a, an insulating layer 110b on insulating layer 110a, and an insulating layer 110c on insulating layer 110b.
  • the insulating layer 110a is located on the insulating layer 107 and the conductive layer 103.
  • the insulating layer 110a is provided so as to cover the upper and side surfaces of the conductive layer 103.
  • the insulating layer 110a is also provided so as to cover a portion of the opening 148.
  • the insulating layer 110a contacts the insulating layer 107 through the opening 148.
  • Insulating layer 110b is provided on insulating layer 110a, and insulating layer 110c is provided on insulating layer 110b.
  • An opening 141 is provided in insulating layer 107 and insulating layer 110, reaching conductive layer 112a.
  • the conductive layer 112b is located on the insulating layer 110c.
  • the conductive layer 112b has an opening 143 that overlaps with the opening 141.
  • the conductive layer 112b functions as the other of the source electrode and drain electrode of the transistor 100A.
  • the conductive layer 112b has a region that overlaps with the conductive layer 112a via the insulating layer 107 and the insulating layer 110.
  • the top surface shape of opening 148 refers to the shape of the top surface end portion on the opening 148 side of conductive layer 103, or the shape of the bottom surface end portion. Note that, like openings 141 and 143, there are no limitations on the top surface shape of opening 148.
  • opening 141 and opening 148 are preferably concentric. This allows the shortest distance between semiconductor layer 108 and conductive layer 103 in a cross-sectional view to be equal on the left and right sides of opening 141. Also, opening 141 and opening 148 may not be concentric.
  • the semiconductor layer 108 contacts the top surface of the conductive layer 112a, the side surface of the insulating layer 107, the side surface of the insulating layer 110, and the top surface and side surface of the conductive layer 112b.
  • the semiconductor layer 108 is provided so as to cover the opening 141 and the opening 143.
  • the semiconductor layer 108 is provided in contact with the insulating layer 107 and the side surface of the insulating layer 110 on the opening 141 side, and the end portion of the conductive layer 112b on the opening 143 side (which can also be said to be a part of the top surface and the side surface on the opening 143 side).
  • the semiconductor layer 108 contacts the conductive layer 112a through the opening 141 and the opening 143.
  • FIG. 56 an example is shown in which the end of the semiconductor layer 108 is in contact with the top surface of the conductive layer 112b, but one embodiment of the present invention is not limited to this.
  • the semiconductor layer 108 may cover the end of the conductive layer 112b, and the end of the semiconductor layer 108 may be in contact with the top surface of the insulating layer 110c.
  • the insulating layer 106 is located on the insulating layer 110c, the semiconductor layer 108, and the conductive layer 112b.
  • the insulating layer 106 is provided so as to cover the openings 141 and 143 via the semiconductor layer 108.
  • a portion of the insulating layer 106 functions as a gate insulating layer for the transistor 100A.
  • the conductive layer 104 is located on the insulating layer 106.
  • the conductive layer 104 overlaps with the semiconductor layer 108 via the insulating layer 106.
  • the conductive layer 104 functions as a gate electrode of the transistor.
  • transistor 100A there is a region in semiconductor layer 108 that overlaps with conductive layer 104 via insulating layer 106, and overlaps with conductive layer 103 via a portion of insulating layer 110 (particularly, insulating layer 110a and insulating layer 110b). In other words, there is a region in semiconductor layer 108 that is sandwiched between conductive layer 104 via insulating layer 106, and between conductive layer 103 via a portion of insulating layer 110 (particularly, insulating layer 110a and insulating layer 110b).
  • the conductive layer 103 functions as a back gate electrode of the transistor 100A.
  • a portion of the insulating layer 110 functions as a back gate insulating layer of the transistor 100A.
  • the potential on the back channel side of the semiconductor layer 108 is fixed, and the saturation of the transistor 100A can be increased.
  • the transistor 100A has a back gate electrode, the potential on the back channel side of the semiconductor layer 108 can be fixed, and a shift in the threshold voltage can be suppressed.
  • the threshold voltage of the transistor shifts, the drain current (hereinafter also referred to as the cutoff current) that flows when the gate voltage is 0 V may become large.
  • the cutoff current By suppressing the shift in the threshold voltage of the transistor 100A, a transistor with a small cutoff current can be obtained. Note that a small cutoff current may be referred to as normally off.
  • a step may be formed by the insulating layer 107, the insulating layer 110, and the conductive layer 112b, and the conductive layer 112a, and the semiconductor layer 108, the insulating layer 106, and the conductive layer 104 may be provided along the step.
  • 57A shows a vertical cross-sectional view of a transistor 100B1 that can be used in a semiconductor device of one embodiment of the present invention, the vertical cross-sectional view passing through the center of an opening 141.
  • FIG. 57B shows a cross-sectional view of the transistor 100B1, including the conductive layer 112b in an opening 143, as viewed from the top.
  • the transistor 100B1 differs from the transistor 100 shown in FIG. 53B etc. mainly in that the side of the insulating layer 110 on the opening 141 side is vertical. That is, the transistor 100B1 has a configuration in which the angle ⁇ 110 in FIG. 54B is 90 degrees.
  • the transistor 100B1 also differs from the transistor 100 shown in FIG. 53B etc. mainly in that the insulating layer 110 is a single layer, the conductive layer 104 is provided so as to fill the openings 141 and 143, and the conductive layer 104 extends to and covers the end of the semiconductor layer 108 (i.e., the region 108L is not formed). Note that the above description of the transistor 100 can be referred to, and detailed description will be omitted.
  • ⁇ Configuration Example 4> 58A shows a vertical cross-sectional view of a transistor 100B2 that can be used in a semiconductor device according to one embodiment of the present invention, the vertical cross-sectional view passing through the center of an opening 141 and including a conductive layer 112b.
  • FIG. 58B shows a cross-sectional view of a transverse cross-section of the transistor 100B2 including the conductive layer 112b in an opening 143 as viewed from the top side.
  • the transistor 100B2 is different from the transistor 100B1 mainly in that it does not include a conductive layer 112a, is provided over an insulating layer 105, includes conductive layers 112b1 and 112b2 instead of the conductive layer 112b, and has a different shape of the semiconductor layer 108.
  • the conductive layer 112b1 functions as one of a source electrode and a drain electrode, and the conductive layer 112b2 functions as the other.
  • the semiconductor layer 108 has a ring-shaped shape. Specifically, in the opening 141 and the opening 143, there is a region in contact with the side surface of the conductive layer 112b1, a region in contact with the side surface of the conductive layer 112b2, and a region in contact with the side surface of the insulating layer 110.
  • the semiconductor layer 108 is configured not to be in contact with the top surfaces of the conductive layer 112b1 and the conductive layer 112b2.
  • the semiconductor layer 108 having such a shape can be formed by processing, for example, by anisotropic etching.
  • the width H112b of the conductive layers 112b1 and 112b2 is smaller than the width D141 of the openings 141 and 143.
  • the circumferential direction of the openings 141 and 143 corresponds to the channel length direction of the transistor 100B2.
  • the semiconductor layer 108 since the semiconductor layer 108 has an annular shape, there are two current paths (i.e., channels) from the conductive layer 112b1 to the conductive layer 112b2. Note that the semiconductor layer 108 does not necessarily have to have an annular shape as long as it is configured to be in contact with both the conductive layers 112b1 and 112b2.
  • the channel length can be controlled by the shape and size of the opening 141 and the opening 143. For example, if the channel length is to be increased, the perimeter of the opening 141 and the opening 143 may be increased.
  • the opening 141 and the opening 143 are circular in the top view has been shown, one embodiment of the present invention is not limited to this.
  • the opening 141 and the opening 143 in the top view can be, for example, an ellipse or a rectangle with rounded corners.
  • a regular polygon such as an equilateral triangle, a square, or a regular pentagon, or a polygon other than a regular polygon, may also be used.
  • a concave polygon such as a star-shaped polygon, which is a polygon with at least one interior angle exceeding 180 degrees, can increase the channel width.
  • an ellipse, a polygon with rounded corners, or a closed curve combining straight lines and curves can be used.
  • the maximum width of the openings 141 and 143 may be calculated appropriately according to the shape of the top of the openings 141 and 143. For example, if the openings are square or rectangular when viewed from above, the maximum width of the openings 141 and 143 may be the length of the diagonal of the top of the openings 141 and 143.
  • the height of the semiconductor layer 108 is the channel width W100 of the transistor 100B2. Therefore, the channel width W100 of the transistor 100B2 can be controlled by the thickness of the insulating layer 110. Therefore, the channel width of the transistor 100B2 can be made to be a very fine structure below the exposure limit of photolithography (for example, 1 nm or more, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less).
  • the exposure limit of photolithography for example, 1 nm or more, 5 nm or more, 7 nm
  • the source electrode and drain electrode are located at the same height relative to the surface of the substrate 102 on which the transistor 100B2 is formed, and a drain current flows parallel or approximately parallel to the surface of the substrate 102. It can also be said that the drain current flows laterally or approximately laterally in the transistor 100B2. Therefore, the transistor 100B2, which is one embodiment of the present invention, can be called, for example, a VLFET (Vertical Lateral Field Effect Transistor).
  • VLFET Very Lateral Field Effect Transistor
  • Transistor 100B1 is a transistor that can achieve a very small channel length and a large channel width. Therefore, a high on-current can be realized.
  • transistor 100B2 is a transistor that can achieve a very small channel width and a large channel length. Therefore, for example, a moderate on-current can be realized, and in the saturation region, it becomes easy to finely control the drain current according to the gate voltage. In addition, for example, short channel effects such as drain induced barrier lowering (DIBL) can be reduced.
  • Transistor 100B1 and transistor 100B2 can share a part of the manufacturing process and can be separately manufactured on the same substrate. For example, in a display device, transistor 100B2 can be applied as a drive transistor for controlling the current flowing to a light-emitting element, and transistor 100B1 can be applied as a transistor that functions as a switch.
  • transistor 100B1 can be used as a transistor that functions as a switch
  • transistor 100B2 can be used as a driver transistor (transistor M01) and a load transistor (transistor M02).
  • the transistor 100B1 can be used as the transistor that functions as a switch, and the transistor 100B2 can be used as the drive transistor (transistor M01).
  • transistor 100B3 By configuring transistor 100B3 as shown in Figures 59A and 59B, not only the portion having a channel length according to the perimeter of opening 141 and opening 143, but also the semiconductor layer in the region in contact with insulating layer 105 can be used as the channel formation region. This allows the area occupied by the transistor to be further reduced.
  • 60A illustrates an equivalent circuit diagram of a transistor 100C that can be used in a semiconductor device of one embodiment of the present invention.
  • the transistor 100C is a group of transistors including transistors 100_1 to 100_p (p is an integer of 2 or more).
  • the transistors 100_1 to 100_p are connected in parallel, and the transistor 100C can be regarded as one transistor.
  • the gate electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • the source electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • the drain electrodes of transistors 100_1 to 100_p are electrically connected to each other.
  • FIG. 60A illustrates the transistors 100_1 to 100_p as n-channel transistors, one embodiment of the present invention is not limited to this.
  • the transistors 100_1 to 100_p may be p-channel transistors.
  • FIG. 60B shows an equivalent circuit diagram of a transistor 100C according to one embodiment of the present invention.
  • FIG. 60C shows a top view of the transistor 100C.
  • FIG. 61 shows a cross-sectional view of the cut surface taken along dashed line A3-A4 in FIG. 60C.
  • Transistor 100C includes transistors 100_1 to 100_4.
  • the structure of the transistor 100 described above can be applied to each of transistors 100_1 to 100_4. Note that although the transistor 100 is described here as an example, one embodiment of the present invention is not limited thereto. Any of transistors 100A, 100B1, and 100B2 may be applied to transistors 100_1 to 100_4.
  • the transistors 100_1 to 100_4 are arranged in two rows and two columns, but the arrangement of the transistors is not particularly limited.
  • the transistors 100_1 to 100_4 may be arranged in one row and four columns.
  • the transistors may or may not be arranged in a matrix.
  • Transistors 100_1 to 100_4 each have a conductive layer 104, an insulating layer 106, a semiconductor layer 108, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 104 functions as the gate electrodes of transistors 100_1 to 100_4.
  • a part of the insulating layer 106 functions as the gate insulating layer of transistors 100_1 to 100_4.
  • the conductive layer 112a functions as the other of the source and drain electrodes of transistors 100_1 to 100_4, and the conductive layer 112b functions as one of the source and drain electrodes.
  • openings 141_1 to 141_4 and openings 143_1 to 143_4 of transistors 100_1 to 100_4 can be referred to for openings 141 and 143, respectively, and will not be repeated.
  • the channel width of the transistor is the sum of the channel widths of the transistors 100_1 to 100_4.
  • the transistor 100C can be regarded as a transistor having a channel width of "D141 x ⁇ x 4" (see Figures 54A and 54B).
  • the transistor 100C which is composed of p transistors, can be regarded as a transistor having a channel width of "D141 x ⁇ x p". Note that the transistor 100C can be regarded as a transistor having a channel length L100 (see Figure 54B).
  • the channel width can be increased, and the on-current can be increased.
  • the channel width can be varied by adjusting the number (p) of transistors connected in parallel. Simply determine the number of transistors (p) to be connected in parallel to achieve the desired on-current.
  • 60C and other figures show a structure in which the transistors 100_1 to 100_4 share the semiconductor layer 108, but one embodiment of the present invention is not limited to this.
  • a structure in which the semiconductor layer 108 is separate for each of the transistors 100_1 to 100_4 may also be used.
  • the configuration of the transistor 100C shown in configuration example 5 can also be applied to other configuration examples.
  • the transistor 100C may be applied to one or more of the transistors included in the semiconductor device shown in Figures 53 to 58.
  • ⁇ Configuration Example 6> 62A illustrates an equivalent circuit diagram of a transistor 100D that can be used in a semiconductor device of one embodiment of the present invention.
  • the transistor 100D is a group of transistors including transistors 100_1 to 100_q (q is an integer of 2 or more).
  • the transistors 100_1 to 100_q are connected in series, and the transistor 100D can be regarded as one transistor.
  • FIG. 62A illustrates the transistors 100_1 to 100_q as n-channel transistors, one embodiment of the present invention is not limited to this.
  • the transistors 100_1 to 100_q may be p-channel transistors.
  • FIG. 62B shows an equivalent circuit diagram of a transistor 100D of one embodiment of the present invention.
  • FIG. 62C shows a top view of the transistor 100D.
  • FIG. 63 shows a cross-sectional view of the cut surface taken along dashed line A5-A6 in FIG. 62C.
  • Transistor 100D includes transistors 100_1 to 100_4.
  • the structure of the transistor 100 described above can be applied to each of transistors 100_1 to 100_4. Note that although the transistor 100 is described here as an example, one embodiment of the present invention is not limited thereto. Any of transistors 100A, 100B1, and 100B2 may be applied to transistors 100_1 to 100_4.
  • the transistors 100_1 to 100_4 are arranged in two rows and two columns, but the arrangement of the transistors is not particularly limited.
  • the transistors 100_1 to 100_4 may be arranged in one row and four columns.
  • the transistors may or may not be arranged in a matrix.
  • Transistor 100_1 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_1, a conductive layer 112a, and a conductive layer 112b.
  • the conductive layer 112a functions as one of the source electrode and drain electrode of transistor 100_1, and the conductive layer 112b functions as the other.
  • Transistor 100_2 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_2, a conductive layer 112a, and a conductive layer 112c.
  • the conductive layer 112a functions as one of a source electrode and a drain electrode of transistor 100_2, and the conductive layer 112c functions as the other.
  • the conductive layer 112a is shared between transistor 100_1 and transistor 100_2.
  • Transistor 100_3 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_3, a conductive layer 112c, and a conductive layer 112d.
  • the conductive layer 112c functions as one of a source electrode and a drain electrode of transistor 100_3, and the conductive layer 112d functions as the other.
  • the conductive layer 112c is shared between transistor 100_2 and transistor 100_3.
  • Transistor 100_4 has a conductive layer 104, an insulating layer 106, a semiconductor layer 108_4, a conductive layer 112d, and a conductive layer 112e.
  • the conductive layer 112d functions as one of a source electrode and a drain electrode of transistor 100_4, and the conductive layer 112e functions as the other.
  • the conductive layer 112d is shared between transistor 100_3 and transistor 100_4.
  • openings 141_1 to 141_4 and openings 143_1 to 143_4 of transistors 100_1 to 100_4 can be referred to for openings 141 and 143, respectively, and will not be repeated.
  • One of the source electrode and drain electrode of transistor 100_1 is electrically connected to one of the source electrode and drain electrode of transistor 100_2.
  • the other of the source electrode and drain electrode of transistor 100_2 is electrically connected to one of the source electrode and drain electrode of transistor 100_3.
  • the other of the source electrode and drain electrode of transistor 100_3 is electrically connected to one of the source electrode and drain electrode of transistor 100_4.
  • the channel length of the transistor is the sum of the channel lengths of the transistors 100_1 to 100_4.
  • the transistor 100D can be regarded as a transistor having a channel length of "L100 x 4" (see FIG. 54B).
  • the transistor 100D which is composed of q transistors, can be regarded as a transistor having a channel length of "L100 x q".
  • the transistor 100D can be regarded as a transistor having a channel width W100 (see FIGS. 54A and 54B).
  • the channel length can be made different by adjusting the number (q) of transistors connected in series.
  • the number (q) of transistors connected in series can be determined so as to achieve the desired saturation.
  • the configuration of the transistor 100D shown in configuration example 6 can also be applied to other configuration examples.
  • the transistor 100D may be applied to one or more of the transistors included in the semiconductor device shown in Figures 53 to 58.
  • Transistor 100D may also be applied to each transistor in transistor 100C. That is, a configuration may be created in which a group of transistors connected in parallel are further connected in series (hereinafter also referred to as a series-parallel connection). Alternatively, transistor 100C may also be applied to each transistor in transistor 100D. That is, a configuration may be created in which a group of transistors connected in series are further connected in parallel (hereinafter also referred to as a parallel-series connection).
  • one or both of the transistors 100C and 100D can be used as transistors that form a peripheral driver circuit.
  • the display device according to this embodiment can be, for example, a high-resolution display device or a large-sized display device.
  • the display device according to this embodiment can be, for example, a high-definition display device.
  • the semiconductor device of one embodiment of the present invention can be used in a display device or a module having the display device.
  • the module having the display device include a module in which a connector such as a flexible printed circuit (FPC) or a tape carrier package (TCP) is attached to the display device, or a module in which an integrated circuit (IC) is mounted by a chip on glass (COG) method, a chip on film (COF) method, or the like.
  • the display device of this embodiment may have a function as a touch panel.
  • various detection elements also called sensor elements
  • various detection elements that can detect the proximity or contact of a detectable object such as a finger can be applied to the display device.
  • Sensor types include, for example, capacitance type, resistive film type, surface acoustic wave type, infrared type, optical type, and pressure sensitive type.
  • Examples of the capacitance type include the surface capacitance type and the projected capacitance type.
  • Examples of the projected capacitance type include the self-capacitance type and the mutual capacitance type.
  • the mutual capacitance type is preferable because it allows simultaneous multi-point detection.
  • touch panels examples include out-cell, on-cell, and in-cell types.
  • an in-cell touch panel is one in which electrodes constituting a sensing element are provided on one or both of the substrate supporting the display element (also called a display device) and the opposing substrate.
  • FIG. 64A shows a perspective view of a display device 50A.
  • Display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together.
  • substrate 152 is indicated by a dashed line.
  • the display device 50A has a display unit 162, a connection unit 140, a circuit unit 164, a circuit unit 163, and a conductive layer 165.
  • FIG. 64A shows an example in which an FPC 172 is mounted on the display device 50A. Therefore, the configuration shown in FIG. 64A can also be said to be a display module having the display device 50A, an IC, and an FPC.
  • connection portion 140 is provided on the outside of the display portion 162.
  • the connection portion 140 can be provided along one or more sides of the display portion 162. There may be one or more connection portions 140.
  • Figure 64A shows an example in which the connection portion 140 is provided so as to surround the four sides of the display portion.
  • the connection portion 140 electrically connects the common electrode of the display element and the conductive layer, and can supply a potential to the common electrode.
  • the circuit unit 164 has, for example, a scanning line driver circuit (also called a gate driver or a scan driver).
  • the circuit unit 163 has, for example, a signal line driver circuit (also called a source driver or a data driver).
  • the conductive layer 165 has the function of supplying signals and power to the display portion 162, the circuit portion 164, and the circuit portion 163.
  • the signals and power are input to the conductive layer 165 from outside the display device 50A via the FPC 172.
  • the semiconductor device of one embodiment of the present invention can be used, for example, in at least one of the display portion 162, the circuit portion 164, and the circuit portion 163 of the display device 50A.
  • a semiconductor device when a semiconductor device according to one embodiment of the present invention is applied to a pixel circuit of a display device, the area occupied by the pixel circuit can be reduced, and a high-definition display device can be obtained.
  • a display device with a resolution of 300 ppi or more, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, or 3000 ppi or more can be realized.
  • a semiconductor device of one embodiment of the present invention when applied to a driver circuit of a display device (for example, one or both of a scanning line driver circuit and a signal line driver circuit), the area occupied by the driver circuit can be reduced, and a display device with a narrow frame can be obtained.
  • a driver circuit of a display device for example, one or both of a scanning line driver circuit and a signal line driver circuit
  • the semiconductor device of one embodiment of the present invention has good electrical characteristics, and therefore, when used in a display device, the reliability of the display device can be improved.
  • the display device 40 described in embodiment 1 can be applied to the display device 50A.
  • the display unit 162 corresponds to the display unit 42
  • the circuit unit 164 corresponds to the driver circuit unit 43
  • the circuit unit 163 corresponds to the driver circuit unit 44.
  • elements related to red light may be given the identification code "R”
  • elements related to green light may be given the identification code "G”
  • elements related to blue light may be given the identification code "B” to explain each of the different matters.
  • common matters may be explained without using the identification codes.
  • pixel 230R, pixel 230G, or pixel 230B when it is necessary to distinguish between multiple pixels 230, they may be referred to as pixel 230R, pixel 230G, or pixel 230B.
  • pixel 230 when it is necessary to distinguish between pixel 230R, pixel 230G, and pixel 230B, they may be simply referred to as pixel 230.
  • Pixel 230R, pixel 230G, and pixel 230B each have a display element and a circuit (pixel circuit) that controls the driving of the display element.
  • examples of the top surface shape of each subpixel include polygons such as triangles, quadrangles (including rectangles and squares), and pentagons, shapes with rounded corners of these polygons, ellipses, and circles.
  • the top surface shape of each subpixel corresponds to the top surface shape of the display area of the display element that each subpixel has.
  • the top surface shape and size of each subpixel can be determined independently.
  • the arrangements of pixels 230R, 230G, and 230B may be interchanged as appropriate.
  • the display elements and pixel circuits may have the same arrangement or different arrangements.
  • the pentile arrangement is a special pixel arrangement that artificially increases the resolution. For this reason, it is preferable to employ, for example, a stripe arrangement in a display device.
  • the area occupied by a pixel circuit can be reduced by applying, for example, the configuration of the transistor 100 described in embodiment 2 to some or all of the transistors that constitute the pixel circuit. Therefore, the pixel arrangement can be changed from the pentile arrangement to, for example, a stripe arrangement without reducing the resolution of the display device.
  • Various elements can be used as display elements, including liquid crystal elements and light-emitting elements.
  • Other elements that can be used include shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems) elements, or display elements that use microcapsule, electrophoresis, electrowetting, or electronic liquid powder (registered trademark) methods.
  • QLED Quantum-dot LED
  • QLED Quantum-dot LED
  • Display devices using liquid crystal elements include, for example, transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.
  • Modes that can be used in displays using liquid crystal elements include, for example, vertical alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane Switching) mode, TN (Twisted Nematic) mode, and ASM (Axially Symmetrically aligned Micro-cell) mode.
  • VA mode include the MVA (Multi-Domain Vertical Alignment) mode, the PVA (Patterned Vertical Alignment) mode, and the ASV (Advanced Super View) mode.
  • Liquid crystal materials that can be used in liquid crystal elements include, for example, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), ferroelectric liquid crystal, and antiferroelectric liquid crystal.
  • thermotropic liquid crystal low molecular weight liquid crystal
  • polymer liquid crystal polymer dispersed liquid crystal
  • PDLC Polymer Dispersed Liquid Crystal
  • PNLC Polymer Network Liquid Crystal
  • ferroelectric liquid crystal and antiferroelectric liquid crystal.
  • these liquid crystal materials exhibit a cholesteric phase, smectic phase, cubic phase, chiral nematic phase, isotropic phase, or blue phase.
  • either positive type liquid crystal or negative type liquid crystal may be used as the liquid crystal material, and can be selected according to the mode or design to be applied.
  • Light-emitting elements include, for example, self-emitting light-emitting elements such as LEDs (Light Emitting Diodes), organic EL (Electro Luminescence) elements (also called OLEDs (Organic LEDs)), and semiconductor lasers. LEDs can be, for example, mini LEDs or micro LEDs.
  • Light-emitting materials that light-emitting elements have include, for example, materials that emit fluorescence (fluorescent materials), materials that emit phosphorescence (phosphorescent materials), materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), and inorganic compounds (such as quantum dot materials).
  • fluorescent materials materials that emit fluorescence
  • phosphorescent materials materials that emit phosphorescence
  • TADF thermally activated delayed fluorescence
  • inorganic compounds such as quantum dot materials
  • the light-emitting element can emit light of infrared, red, green, blue, cyan, magenta, yellow, or white.
  • the color purity can be increased by providing the light-emitting element with a microcavity structure.
  • one electrode functions as an anode (also called an anode electrode) and the other electrode functions as a cathode (also called a cathode electrode).
  • one embodiment of the present invention is a display device using an organic EL element.
  • the display device of one embodiment of the present invention may be a top-emission type that emits light in a direction opposite to the substrate on which the light-emitting elements are formed, a bottom-emission type that emits light toward the substrate on which the light-emitting elements are formed, or a dual-emission type that emits light on both sides.
  • the semiconductor device can reduce the area occupied by the device, and therefore can increase the aperture ratio of pixels in a display device having a bottom emission structure.
  • a display device having an aperture ratio of 50% or more, 55% or more, or 60% or more can be realized.
  • aperture ratio refers to the ratio of the area through which light is emitted to the area of the pixel.
  • ⁇ Configuration Example 2 of Display Device> 65A shows an example of a cross section of the display device 50A when a part of a region including the FPC 172, a part of the circuit portion 164, a part of the display portion 162, a part of the connection portion 140, and a part of a region including an end portion are cut away. Note that the description of the circuit portion 164 can be referred to for the circuit portion 163.
  • the display device 50A shown in FIG. 65A has transistors 205D, 205R, 205G, 207G, 207B, light-emitting elements 130R, 130G, and 130B between substrate 151 and substrate 152.
  • Light-emitting element 130R is a display element in pixel 230R that emits red light
  • light-emitting element 130G is a display element in pixel 230G that emits green light
  • light-emitting element 130B is a display element in pixel 230B that emits blue light. Note that when describing matters common to light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B, they may be simply referred to as light-emitting element 130.
  • the display device 50A uses the SBS (Side By Side) structure.
  • SBS System By Side
  • the SBS structure allows the material and configuration to be optimized for each light-emitting element, which increases the freedom of material and configuration selection and makes it easier to improve the light emission intensity and reliability.
  • the display device 50A is a top emission type.
  • transistors and other components can be arranged so as to overlap the light-emitting region of the light-emitting element, which allows for a higher pixel aperture ratio than in a bottom emission type.
  • Transistors 205D, 205R, 205G, 207G, and 207B are all formed on substrate 151. These transistors can be manufactured using some of the same processes.
  • One or more of the above-mentioned transistors 100, 100A, 100B1, 100B2, 100C, 100D, and 200 can be applied to any one or more of transistors 205D, 205R, 205G, 207G, and 207B.
  • Figure 65A shows a configuration example in which the above-mentioned transistor 100 is applied to transistors 205D, 205R, and 205G, and the above-mentioned transistor 200 is applied to transistors 207G and 207B.
  • a high-definition display device can be obtained by using one or more of the above-mentioned transistors 100, 100A, 100B1, 100B2, 100C, and 100D as the transistors provided in the display portion 162.
  • the highly saturable transistor 200 can be used as the driving transistor of the light-emitting element 130. This allows the display device to be highly reliable.
  • the circuit portion 164 By using one or more of the above-mentioned transistors 100, 100A, 100B1, 100B2, 100C, and 100D in the circuit portion 164, a display device that operates at high speed can be obtained. Compared to the transistors provided in the display portion 162, the transistors provided in the circuit portion 164 may require a large on-state current. It is preferable to use a transistor with a short channel length in the circuit portion 164.
  • the circuit portion 164 can use one or more of the above-mentioned transistors 100, 100A, 100B1, 100B2, 100C, and 100D.
  • the occupied area can be reduced, and a display device with a narrow frame can be obtained.
  • a transistor 200 may be used in the circuit section 164.
  • the transistors included in the display device of this embodiment are not limited to only the transistors included in the semiconductor device of one embodiment of the present invention.
  • a transistor included in the semiconductor device of one embodiment of the present invention may be combined with a transistor having another structure.
  • the display device of this embodiment may include, for example, one or more of a planar transistor, a staggered transistor, and an inverted staggered transistor.
  • the transistors included in the display device of this embodiment may be either a top-gate type or a bottom-gate type.
  • gates may be provided above and below a semiconductor layer in which a channel is formed.
  • Transistor 205D, transistor 205R, transistor 205G, transistor 207G, and transistor 207B can be OS transistors.
  • the display device of this embodiment may have a Si transistor.
  • an OS transistor When a transistor operates in the saturation region, an OS transistor can reduce the change in current flowing from the drain to the source in response to a change in the gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the current flowing from the drain to the source can be precisely determined by changing the gate-source voltage, and the amount of current flowing to the light-emitting element can be controlled. This makes it possible to increase the number of gray levels in the pixel circuit.
  • an OS transistor can pass a more stable current (saturation current) than a Si transistor, even when the drain-source voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be passed to the light-emitting element, for example, even when there is variation in the current-voltage characteristics of the light-emitting element. In other words, when an OS transistor operates in the saturation region, the current that flows from the drain to the source hardly changes even when the drain-source voltage is changed, so the light-emitting intensity of the light-emitting element can be stabilized.
  • the transistors in the circuit portion 164 and the transistors in the display portion 162 may have the same structure or different structures.
  • the transistors in the circuit portion 164 may all have the same structure or may have two or more types.
  • the transistors in the display portion 162 may all have the same structure or may have two or more types.
  • All of the transistors in the display portion 162 may be OS transistors, all of the transistors in the display portion 162 may be Si transistors, or some of the transistors in the display portion 162 may be OS transistors and the rest may be Si transistors.
  • a display device with low power consumption and high driving capability can be realized.
  • a configuration in which an OS transistor is used as a transistor that functions as a switch for controlling the conduction or non-conduction between wirings, and an LTPS transistor is used as a transistor for controlling current can be given.
  • one of the transistors in the display unit 162 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor.
  • One of the source and drain of the drive transistor is electrically connected to the pixel electrode of the light-emitting element.
  • An LTPS transistor can be used for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.
  • the other one of the transistors in the display unit 162 functions as a switch for controlling the selection or non-selection of a pixel, and can also be called a selection transistor.
  • the gate of the selection transistor is electrically connected to a gate line (scanning line), and one of the source and drain is electrically connected to a source line (signal line).
  • an OS transistor as the selection transistor. This makes it possible to maintain the gradation of the pixel even if the refresh rate is significantly reduced (for example, 1 Hz or less), and therefore power consumption can be reduced by stopping the driver (drive circuit) when displaying a still image.
  • An insulating layer 195 is provided to cover transistors 205D, 205R, 205G, 207G, and 207B, and an insulating layer 235 is provided on insulating layer 195.
  • the light-emitting element 130R has a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R.
  • the light-emitting element 130R shown in FIG. 65A emits red (R) light.
  • the EL layer 113R has a light-emitting layer that emits red light.
  • the light-emitting element 130G has a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G.
  • the light-emitting element 130G shown in FIG. 65A emits green (G) light.
  • the EL layer 113G has a light-emitting layer that emits green light.
  • the light-emitting element 130B has a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B.
  • the light-emitting element 130B shown in FIG. 65A emits blue (B) light.
  • the EL layer 113B has a light-emitting layer that emits blue light.
  • FIG. 65A shows EL layers 113R, 113G, and EL layers 113B all having the same thickness, this is not limited to the above.
  • EL layers 113R, 113G, and EL layers 113B may each have a different thickness.
  • the pixel electrode 111R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.
  • the pixel electrode 111G is electrically connected to the conductive layer 112b of the transistor 205G
  • the pixel electrode 111B is electrically connected to the conductive layer 112b of the transistor 205B (not shown).
  • the ends of the pixel electrodes 111R, 111G, and 111B are covered with an insulating layer 237.
  • the insulating layer 237 functions as a partition wall.
  • the insulating layer 237 can be formed in a single layer structure or a multilayer structure using one or both of an inorganic insulating material and an organic insulating material.
  • the material that can be used for the insulating layer 195 and the material that can be used for the insulating layer 235 can be used for the insulating layer 237.
  • the insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Furthermore, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.
  • the insulating layer 237 is provided at least in the display section 162.
  • the insulating layer 237 may be provided not only in the display section 162, but also in the connection section 140 and the circuit section 164.
  • the insulating layer 237 may also be provided up to the edge of the display device 50A.
  • the common electrode 115 is a continuous film that is provided in common to the light-emitting elements 130R, 130G, and 130B.
  • the common electrode 115 that is shared by the multiple light-emitting elements is electrically connected to a conductive layer 123 provided in the connection portion 140.
  • a conductive layer 123 it is preferable to use a conductive layer that is made of the same material and formed in the same process as the pixel electrodes 111R, 111G, and 111B.
  • a conductive film that transmits visible light for the electrode from which light is extracted between the pixel electrode and the common electrode. It is also preferable to use a conductive film that reflects visible light for the electrode from which light is not extracted.
  • a conductive film that transmits visible light may also be used for the electrode on the side from which light is not extracted.
  • the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.
  • metals, alloys, electrically conductive compounds, and mixtures thereof can be appropriately used.
  • the material include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, as well as alloys containing these in appropriate combinations.
  • Examples of the material include indium tin oxide (In-Sn oxide, or ITO), In-Si-Sn oxide (ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide.
  • Examples of the material include alloys containing aluminum (aluminum alloys), such as an alloy of aluminum, nickel, and lanthanum (Al-Ni-La), and alloys containing silver, such as an alloy of silver, magnesium, and an alloy of silver, palladium, and copper (Ag-Pd-Cu, or APC).
  • Such materials include elements belonging to Group 1 or 2 of the periodic table (e.g., lithium, cesium, calcium, and strontium) not listed above, rare earth metals such as europium and ytterbium, alloys containing appropriate combinations of these, and graphene.
  • elements belonging to Group 1 or 2 of the periodic table e.g., lithium, cesium, calcium, and strontium
  • rare earth metals such as europium and ytterbium
  • alloys containing appropriate combinations of these e.
  • the light-emitting element preferably has a micro-optical resonator (microcavity) structure. Therefore, one of the pair of electrodes of the light-emitting element is preferably an electrode that is transparent and reflective to visible light (semi-transparent and semi-reflective electrode), and the other is preferably an electrode that is reflective to visible light (reflective electrode).
  • the light-emitting element have a microcavity structure, the light emitted from the light-emitting layer can be resonated between both electrodes, thereby intensifying the light emitted from the light-emitting element.
  • the light transmittance of the transparent electrode is 40% or more.
  • the visible light reflectance of the semi-transmissive/semi-reflective electrode is 10% or more and 95% or less, preferably 30% or more and 80% or less.
  • the visible light reflectance of the reflective electrode is 40% or more and less than 100%, preferably 70% or more and less than 100%.
  • the resistivity of these electrodes is preferably 1 ⁇ 10 ⁇ 2 ⁇ cm or less.
  • EL layer 113R, EL layer 113G, and EL layer 113B are each provided in an island shape.
  • the ends of adjacent EL layers 113R and 113G overlap, the ends of adjacent EL layers 113G and 113B overlap, and the ends of adjacent EL layers 113R and 113B overlap.
  • the ends of adjacent EL layers may overlap as shown in FIG. 65A, but this is not limited to this. In other words, adjacent EL layers may not overlap and may be separated from each other.
  • EL layer 113R, EL layer 113G, and EL layer 113B each have at least a light-emitting layer.
  • the light-emitting layer has one or more types of light-emitting material.
  • a material that emits light of a color such as blue, purple, blue-purple, green, yellow-green, yellow, orange, or red is appropriately used.
  • a material that emits near-infrared light can also be used as the light-emitting material.
  • Light-emitting materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.
  • the light-emitting layer may have one or more organic compounds (such as a host material and an assist material) in addition to the light-emitting substance (guest material).
  • one or more organic compounds such as a host material and an assist material
  • one or both of a substance with high hole transport properties (hole transport material) and a substance with high electron transport properties (electron transport material) may be used.
  • a bipolar substance a substance with high electron transport properties and hole transport properties
  • TADF material may be used as the one or more organic compounds.
  • the light-emitting layer preferably contains, for example, a phosphorescent material and a hole-transporting material and an electron-transporting material, which are a combination that easily forms an exciplex.
  • ExTET Exciplex-Triple Energy Transfer
  • the energy transfer becomes smooth and light emission can be efficiently obtained.
  • the EL layer may have one or more of a layer containing a substance with high hole injection properties (hole injection layer), a layer containing a material with hole transport properties (hole transport layer), a layer containing a substance with high electron blocking properties (electron blocking layer), a layer containing a substance with high electron injection properties (electron injection layer), a layer containing a material with electron transport properties (electron transport layer), and a layer containing a substance with high hole blocking properties (hole blocking layer).
  • the EL layer may contain one or both of a bipolar substance and a TADF material.
  • Either low molecular weight compounds or high molecular weight compounds can be used for the light emitting element, and it may contain an inorganic compound.
  • the layers constituting the light emitting element can be formed by a method such as a deposition method (including a vacuum deposition method), a transfer method, a printing method, an inkjet method, or a coating method.
  • the light-emitting element may have a single structure (a structure having only one light-emitting unit) or a tandem structure (a structure having multiple light-emitting units).
  • the light-emitting unit has at least one light-emitting layer.
  • the tandem structure is a structure in which multiple light-emitting units are connected in series via a charge-generating layer. When a voltage is applied between a pair of electrodes, the charge-generating layer has the function of injecting electrons into one of the two light-emitting units and injecting holes into the other.
  • the tandem structure makes it possible to obtain a light-emitting element that can emit light with high luminous intensity. Furthermore, the tandem structure can reduce the current required to obtain the same luminous intensity compared to the single structure, thereby improving reliability.
  • the tandem structure may also be called a stack structure.
  • EL layer 113R has a structure having multiple light-emitting units that emit red light
  • EL layer 113G has a structure having multiple light-emitting units that emit green light
  • EL layer 113B has a structure having multiple light-emitting units that emit blue light.
  • a protective layer 131 is provided on the light-emitting elements 130R, 130G, and 130B.
  • the protective layer 131 and the substrate 152 are bonded via an adhesive layer 142.
  • the substrate 152 is provided with a light-shielding layer 117.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting elements.
  • the space between the substrates 152 and 151 is filled with the adhesive layer 142, and a solid sealing structure is applied.
  • a hollow sealing structure in which the space is filled with an inert gas (such as nitrogen or argon) may be applied.
  • the adhesive layer 142 may be provided so as not to overlap with the light-emitting elements.
  • the space may also be filled with a resin different from the adhesive layer 142 provided in a frame shape.
  • the protective layer 131 is provided at least on the display section 162, and is preferably provided so as to cover the entire display section 162.
  • the protective layer 131 is preferably provided so as to cover not only the display section 162, but also the connection section 140 and the circuit section 164.
  • the protective layer 131 is also preferably provided up to the end of the display device 50A.
  • the connection section 197 has a portion where the protective layer 131 is not provided in order to electrically connect the FPC 172 and the conductive layer 166.
  • the reliability of the light-emitting elements can be improved.
  • the protective layer 131 may have a single layer structure or a laminated structure of two or more layers.
  • the conductivity of the protective layer 131 does not matter.
  • At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.
  • the protective layer 131 has an inorganic film, which prevents oxidation of the common electrode 115 and prevents impurities (such as moisture and oxygen) from entering the light-emitting element, thereby suppressing deterioration of the light-emitting element and improving the reliability of the display device.
  • An inorganic insulating film can be used for the protective layer 131.
  • materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Specific examples of these inorganic insulating films are as described above.
  • the protective layer 131 preferably contains a nitride or a nitride oxide, and more preferably contains a nitride.
  • the protective layer 131 may be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, IGZO, or the like.
  • the inorganic film preferably has a high resistance, specifically, a higher resistance than the common electrode 115.
  • the inorganic film may further contain nitrogen.
  • the protective layer 131 has high transparency to visible light.
  • ITO, IGZO, and aluminum oxide are preferable because they are inorganic materials that have high transparency to visible light.
  • the protective layer 131 may be, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film. By using such a laminated structure, it is possible to prevent impurities (such as water and oxygen) from entering the EL layer.
  • the protective layer 131 may have an organic film.
  • the protective layer 131 may have both an organic film and an inorganic film.
  • An example of an organic film that can be used for the protective layer 131 is an organic insulating film that can be used for the insulating layer 235.
  • connection portion 197 is provided in an area of the substrate 151 that does not overlap with the substrate 152.
  • the conductive layer 165 is electrically connected to the FPC 172 via the conductive layer 166 and the connection layer 242.
  • the conductive layer 165 is an example of a single-layer structure of a conductive layer obtained by processing the same conductive film as the conductive layer 112b.
  • the conductive layer 166 is an example of a single-layer structure of a conductive layer obtained by processing the same conductive film as the pixel electrodes 111R, 111G, and 111B.
  • the conductive layer 166 is exposed on the upper surface of the connection portion 197. This allows the connection portion 197 and the FPC 172 to be electrically connected via the connection layer 242.
  • the display device 50A is a top emission type. Light emitted by the light emitting elements is emitted towards the substrate 152. It is preferable to use a material that is highly transparent to visible light for the substrate 152.
  • the pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 115) contains a material that transmits visible light.
  • the light-shielding layer 117 can be provided between adjacent light-emitting elements, in the connection section 140, in the circuit section 164, etc.
  • a colored layer such as a color filter may be provided on the surface of substrate 152 facing substrate 151 or on protective layer 131. By providing a color filter over the light-emitting element, the color purity of the light emitted from the pixel can be increased.
  • a glass layer or a silica layer As the surface protection layer, it is possible to suppress the occurrence of surface contamination and scratches, which is preferable.
  • DLC diamond-like carbon
  • AlO x aluminum oxide
  • a polyester-based material a polycarbonate-based material, or the like
  • the substrates 151 and 152 may each be made of polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, and cellulose nanofiber. At least one of the substrates 151 and 152 may be made of glass having a thickness sufficient to provide flexibility.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • polyacrylonitrile resin acrylic resin
  • polyimide resin polymethyl methacrylate resin
  • PC
  • a substrate with high optical isotropy has small birefringence (it can also be said that the amount of birefringence is small).
  • films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.
  • curing adhesives such as photo-curing adhesives such as ultraviolet curing adhesives, reactive curing adhesives, heat curing adhesives, and anaerobic adhesives.
  • photo-curing adhesives such as ultraviolet curing adhesives, reactive curing adhesives, heat curing adhesives, and anaerobic adhesives.
  • These adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin.
  • materials with low moisture permeability such as epoxy resin are preferable.
  • Two-part mixed resins may also be used.
  • Adhesive sheets, etc. may also be used.
  • connection layer 242 an anisotropic conductive film (ACF) and an anisotropic conductive paste (ACP) can be used.
  • ACF anisotropic conductive film
  • ACP anisotropic conductive paste
  • FIG. 65B shows an example of a cross section of the display unit 162 of the display device 50B.
  • the display device 50B is mainly different from the display device 50A in that a light-emitting element having a common EL layer 113 and a colored layer (such as a color filter) are used in each subpixel of each color.
  • the configuration shown in FIG. 65B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in FIG. 65A. Note that in the following description of the display device, the description of the same parts as those of the display device described above may be omitted.
  • the display device 50B shown in FIG. 65B has a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light-emitting element 130R has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.
  • the light-emitting element 130G has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.
  • the light-emitting element 130B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.
  • Light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B each share EL layer 113 and common electrode 115.
  • a configuration in which a common EL layer 113 is provided for subpixels of each color can reduce the number of manufacturing steps compared to a configuration in which a different EL layer is provided for each subpixel of each color.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 65B emit white light.
  • the white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of the desired color.
  • a light-emitting element that emits white light preferably includes two or more light-emitting layers.
  • the emission colors of the two light-emitting layers are complementary to each other.
  • the emission colors of the three or more light-emitting layers are combined to emit white light from the light-emitting element as a whole.
  • the EL layer 113 preferably has, for example, a light-emitting layer having a light-emitting material that emits blue light, and a light-emitting layer having a light-emitting material that emits visible light with a longer wavelength than blue.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits yellow light, and a light-emitting layer that emits blue light.
  • the EL layer 113 preferably has, for example, a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light.
  • a tandem structure For light-emitting elements that emit white light, it is preferable to use a tandem structure. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow (Y) light and a light-emitting unit that emits blue (B) light, a two-stage tandem structure having a light-emitting unit that emits red (R) light and green (G) light and a light-emitting unit that emits blue light, a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light, and a light-emitting unit that emits blue light, or a three-stage tandem structure having, in this order, a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and red light, and a light-emitting unit that emits blue light, etc.
  • examples of the number of layers and color order of the light-emitting units include, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and X (light-emitting unit X), a three-layer structure of B, Y, and B, and a three-layer structure of B, X, and B.
  • Examples of the number of layers and color order of the light-emitting layers in light-emitting unit X include, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, and G, and a three-layer structure of R, G, and R.
  • another layer may be provided between the two light-emitting layers.
  • a light-emitting element configured to emit white light may emit light of a specific wavelength, such as red, green, or blue, with the light being enhanced.
  • the light emitting element 130R, the light emitting element 130G, and the light emitting element 130B shown in FIG. 65B emit blue light.
  • the EL layer 113 has one or more light emitting layers that emit blue light.
  • the blue light emitted by the light emitting element 130B can be extracted.
  • a color conversion layer is provided between the light emitting element 130R or the light emitting element 130G and the substrate 152, so that the blue light emitted by the light emitting element 130R or the light emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • the display device 50E shown in Fig. 66A is an example of a display device to which the MML (metal maskless) structure is applied. That is, the display device 50E has a light-emitting element manufactured without using a metal mask (or a fine metal mask). Note that the laminated structure from the substrate 151 to the insulating layer 235 and the laminated structure from the protective layer 131 to the substrate 152 are similar to those of the display device 50A, and therefore the description thereof will be omitted.
  • light-emitting elements with an MML (metal maskless) structure can be manufactured without using a metal mask. This makes it possible to realize a display device that exceeds the upper limit of resolution caused by the alignment accuracy of the metal mask. In addition, it is possible to eliminate the need for equipment related to the manufacture of metal masks and the process of cleaning the metal masks. In addition, it is possible to mass-produce display devices.
  • MML metal maskless
  • MML metal maskless
  • a display device that integrates minute light-emitting elements. Therefore, for example, without artificially increasing the resolution by applying a special pixel arrangement such as a pentile arrangement, it is possible to realize a display device that applies a so-called stripe arrangement in which R, G, and B are each arranged in one direction, and has a resolution of 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more.
  • light-emitting elements 130R, 130G, and 130B are provided on insulating layer 235.
  • the light-emitting element 130R has a conductive layer 124R on the insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130R shown in FIG. 66A emits red (R) light.
  • the layer 133R has a light-emitting layer that emits red light.
  • the layer 133R and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layers 124R and 126R can be referred to as a pixel electrode.
  • the light-emitting element 130G has a conductive layer 124G on the insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130G shown in FIG. 66A emits green (G) light.
  • the layer 133G has a light-emitting layer that emits green light.
  • the layer 133G and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layers 124G and 126G can be referred to as a pixel electrode.
  • the light-emitting element 130B has a conductive layer 124B on the insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114.
  • the light-emitting element 130B shown in FIG. 66A emits blue (B) light.
  • the layer 133B has a light-emitting layer that emits blue light.
  • the layer 133B and the common layer 114 can be collectively referred to as an EL layer.
  • one or both of the conductive layers 124B and 126B can be referred to as a pixel electrode.
  • layers provided in an island shape for each light-emitting element are indicated as layer 133B, layer 133G, or layer 133R, and a layer shared by a plurality of light-emitting elements is indicated as common layer 114.
  • layers 133R, 133G, and 133B may be referred to as island-shaped EL layers or EL layers formed in an island shape, without including common layer 114.
  • Layer 133R, layer 133G, and layer 133B are separated from each other.
  • the EL layer in an island shape for each light-emitting element, it is possible to suppress leakage current between adjacent light-emitting elements. This makes it possible to prevent unintended light emission caused by crosstalk, and to realize a display device with extremely high contrast.
  • layers 133R, 133G, and 133B are all shown to have the same thickness, but this is not limited to this. Layers 133R, 133G, and 133B may each have a different thickness.
  • the conductive layer 124R is electrically connected to the conductive layer 112b of the transistor 205R through openings provided in the insulating layer 106, the insulating layer 195, and the insulating layer 235.
  • the conductive layer 124G is electrically connected to the conductive layer 112b of the transistor 205G
  • the conductive layer 124B is electrically connected to the conductive layer 112b of the transistor 205B.
  • the conductive layers 124R, 124G, and 124B are formed to cover the openings provided in the insulating layer 235.
  • Layer 128 is embedded in the recesses of the conductive layers 124R, 124G, and 124B, respectively.
  • Layer 128 has the function of planarizing the recesses of conductive layer 124R, conductive layer 124G, and conductive layer 124B.
  • Conductive layer 126R, conductive layer 126G, and conductive layer 126B are provided on conductive layer 124R, conductive layer 124G, and conductive layer 124B, and layer 128, and are electrically connected to conductive layer 124R, conductive layer 124G, and conductive layer 124B. Therefore, the regions overlapping with the recesses of conductive layer 124R, conductive layer 124G, and conductive layer 124B can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased. It is preferable to use a conductive layer that functions as a reflective electrode for conductive layer 124R and conductive layer 126R.
  • Layer 128 may be an insulating layer or a conductive layer.
  • Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128.
  • layer 128 is preferably formed using an insulating material, and is particularly preferably formed using an organic insulating material.
  • the organic insulating material that can be used for insulating layer 237 described above can be applied to layer 128.
  • FIG. 66A shows an example in which the top surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited.
  • the top surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.
  • the height of the upper surface of layer 128 and the height of the upper surface of conductive layer 124R may be the same or approximately the same, or may be different from each other.
  • the height of the upper surface of layer 128 may be lower or higher than the height of the upper surface of conductive layer 124R.
  • the end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or may cover the side of the end of the conductive layer 124R.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape.
  • the ends of the conductive layer 124R and the conductive layer 126R preferably have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees.
  • the layer 133R provided along the side of the pixel electrode has an inclined portion.
  • the conductive layers 124G and 126G, as well as the conductive layers 124B and 126B, are similar to the conductive layers 124R and 126R, and therefore will not be described in detail.
  • conductive layer 126R The upper and side surfaces of conductive layer 126R are covered by layer 133R. Similarly, the upper and side surfaces of conductive layer 126G are covered by layer 133G, and the upper and side surfaces of conductive layer 126B are covered by layer 133B. Therefore, the entire area in which conductive layer 126R, conductive layer 126G, and conductive layer 126B are provided can be used as the light-emitting area of light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B, thereby increasing the aperture ratio of the pixel.
  • a portion of the top surface and the side surfaces of each of layers 133R, 133G, and 133B are covered with insulating layers 125 and 127.
  • a common layer 114 is provided on layers 133R, 133G, and 133B, as well as insulating layers 125 and 127, and a common electrode 115 is provided on common layer 114.
  • Common layer 114 and common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.
  • the insulating layer 237 shown in FIG. 65A and the like is not provided between the conductive layer 126R and the layer 133R.
  • the display device 50E does not have an insulating layer (also called a partition, bank, spacer, etc.) that contacts the pixel electrode and covers the upper end of the pixel electrode. This allows the distance between adjacent light-emitting elements to be extremely narrow. This allows a high-definition, high-resolution display device to be obtained.
  • a mask e.g., a photomask
  • a photomask for forming the insulating layer is not required, which reduces the manufacturing cost of the display device.
  • each of the layers 133R, 133G, and 133B has a light-emitting layer.
  • Each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer and a carrier block layer (hole block layer or electron block layer) on the light-emitting layer.
  • each of the layers 133R, 133G, and 133B preferably has a light-emitting layer, a carrier block layer on the light-emitting layer, and a carrier transport layer on the carrier block layer. Since the surfaces of the layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, by providing one or both of the carrier transport layer and the carrier block layer on the light-emitting layer, it is possible to suppress exposure of the light-emitting layer to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting element.
  • the common layer 114 has, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or may have a hole transport layer and a hole injection layer stacked together.
  • the common layer 114 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.
  • Insulating layer 125 covers the sides of layers 133R, 133G, and 133B via insulating layer 125.
  • the insulating layer 127 is provided on the insulating layer 125 so as to fill the recesses in the insulating layer 125. It is preferable that the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.
  • the gap between adjacent island-shaped layers can be filled, reducing the large unevenness of the surface on which layers (e.g., the carrier injection layer and the common electrode) are formed on the island-shaped layers, making it possible to make the surface flatter. This improves the coverage of the carrier injection layer, the common electrode, etc.
  • layers e.g., the carrier injection layer and the common electrode
  • the common layer 114 and the common electrode 115 are provided on the layers 133R, 133G, 133B, the insulating layer 125, and the insulating layer 127. Before the insulating layer 125 and the insulating layer 127 are provided, there is a step between the region where the pixel electrode and the island-shaped EL layer are provided and the region (region between the light-emitting elements) where the pixel electrode and the island-shaped EL layer are not provided.
  • the display device of one embodiment of the present invention has the insulating layer 125 and the insulating layer 127, so that the step can be flattened, and the coverage of the common layer 114 and the common electrode 115 can be improved. Therefore, poor connection due to step disconnection can be suppressed. In addition, the step can be suppressed from locally thinning the common electrode 115 and increasing the electrical resistance.
  • the upper surface of the insulating layer 127 preferably has a shape with high flatness.
  • the upper surface of the insulating layer 127 may have at least one of a flat surface, a convex curved surface, and a concave curved surface.
  • the upper surface of the insulating layer 127 preferably has a convex curved shape with a large radius of curvature.
  • An inorganic insulating film can be used for the insulating layer 125.
  • materials that can be used for the inorganic insulating film include oxides, nitrides, oxynitrides, and nitride oxides. Specific examples of these inorganic insulating films are as described above.
  • the insulating layer 125 may have a single-layer structure or a laminated structure. In particular, aluminum oxide is preferable because it has a high selectivity with respect to the EL layer in etching and has a function of protecting the EL layer in the formation of the insulating layer 127 described later.
  • the insulating layer 125 may have a laminated structure of a film formed by the ALD method and a film formed by the sputtering method.
  • the insulating layer 125 may have a laminated structure of, for example, an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.
  • the insulating layer 125 preferably has a function as a barrier insulating layer against at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of suppressing the diffusion of at least one of water and oxygen.
  • the insulating layer 125 preferably has a function of capturing or fixing (also called gettering) at least one of water and oxygen.
  • the insulating layer 125 preferably has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulating layer 125 and causing deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration or carbon concentration, or preferably both.
  • the insulating layer 127 provided on the insulating layer 125 has the function of flattening the unevenness of the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface on which the common electrode 115 is formed.
  • an insulating layer containing an organic material can be used as the insulating layer 127.
  • an organic material it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to acrylic polymers in a broad sense.
  • the insulating layer 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulating layer 127 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, and alcohol-soluble polyamide resin.
  • PVA polyvinyl alcohol
  • the photosensitive resin may be a photoresist.
  • the photosensitive organic resin may be either a positive-type material or a negative-type material.
  • the insulating layer 127 may be made of a material that absorbs visible light. By having the insulating layer 127 absorb the light emitted from the light-emitting element, it is possible to suppress leakage of light from the light-emitting element to an adjacent light-emitting element through the insulating layer 127 (stray light). This can improve the display quality of the display device. In addition, since the display quality can be improved without using a polarizing plate in the display device, it is possible to reduce the weight and thickness of the display device.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (such as polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials that can be used in color filters color filter materials.
  • by mixing color filter materials of three or more colors it is possible to create a resin layer that is black or close to black.
  • Fig. 66B shows an example of a cross section of the display unit 162 of the display device 50F.
  • the display device 50F is mainly different from the display device 50E in that a light-emitting element having a layer 133R, a layer 133G, and a layer 133B, and a colored layer (such as a color filter) are used in each subpixel of each color.
  • the configuration shown in Fig. 66B can be combined with the region including the FPC 172, the circuit portion 164, the laminated structure from the substrate 151 to the insulating layer 235 of the display unit 162, the connection portion 140, and the configuration of the end portion shown in Fig. 66A.
  • the display device 50F shown in FIG. 66B has a light-emitting element 130R, a light-emitting element 130G, a light-emitting element 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.
  • the light emitted by the light-emitting element 130R is extracted as red light to the outside of the display device 50F via the colored layer 132R.
  • the light emitted by the light-emitting element 130G is extracted as green light to the outside of the display device 50F via the colored layer 132G.
  • the light emitted by the light-emitting element 130B is extracted as blue light to the outside of the display device 50F via the colored layer 132B.
  • Light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B each have layer 133R, layer 133G, and layer 133B.
  • Layer 133R, layer 133G, and layer 133B are formed using the same material and in the same process.
  • Layer 133R, layer 133G, and layer 133B are separated from each other.
  • the light-emitting elements 130R, 130G, and 130B shown in FIG. 66B emit white light.
  • the white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, thereby obtaining light of the desired color.
  • the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B shown in FIG. 66B emit blue light.
  • the layer 133R, the layer 133G, and the layer 133B have one or more light-emitting layers that emit blue light.
  • the blue light emitted by the light-emitting element 130B can be extracted.
  • a color conversion layer is provided between the light-emitting element 130R or the light-emitting element 130G and the substrate 152, so that the blue light emitted by the light-emitting element 130R or the light-emitting element 130G can be converted into light with a longer wavelength, and red or green light can be extracted.
  • the carrier concentration of a channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably less than 1 ⁇ 10 17 cm ⁇ 3 , more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
  • the density of defect states in the oxide semiconductor may be reduced by reducing the impurity concentration in the oxide semiconductor.
  • a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Furthermore, charges captured in the trap states of the oxide semiconductor take a long time to disappear and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • impurities in an oxide semiconductor refer to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • an OS transistor may form a defect (hereinafter sometimes referred to as VOH ) in which hydrogen is introduced into an oxygen vacancy in an oxide semiconductor, and generate electrons that serve as carriers.
  • VOH a defect
  • the donor concentration in the channel formation region may increase.
  • the threshold voltage of an OS transistor may vary as the donor concentration in the channel formation region increases. For this reason, when an oxygen vacancy is present in a channel formation region of an oxide semiconductor, an OS transistor is likely to have normally-on characteristics (a drain current flows when a gate voltage is 0 V). Therefore, impurities, oxygen vacancies, and VOH are preferably reduced as much as possible in a channel formation region of an oxide semiconductor.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more.
  • the off-current (also referred to as Ioff) of the transistor can be reduced.
  • OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (reduced channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes written as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage when the drain current is changed by one order of magnitude while the drain voltage is constant in the subthreshold region.
  • Characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the conduction band bottom of the channel formation region is lowered due to the Conduction-Band-Lowering (CBL) effect, so that the energy difference between the conduction band bottom between the source region or drain region and the channel formation region can be reduced to 0.1 eV to 0.2 eV.
  • CBL Conduction-Band-Lowering
  • the OS transistor can also be considered to have an n + / n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ /n + accumulation-type non- junction transistor structure in which the channel formation region is an n ⁇ type region and the source region and the drain region are each an n + type region .
  • the OS transistor can have good electrical characteristics even when miniaturized or highly integrated.
  • the OS transistor can have good electrical characteristics even when the gate length is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less and 1 nm or more, 3 nm or more, or 5 nm or more.
  • the OS transistor can be used as a transistor with a shorter channel length than the Si transistor.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors have the excellent advantages of having a smaller off-state current than Si transistors and being capable of producing transistors with a short channel length.
  • the electronic device of this embodiment has a display device using a display device according to one embodiment of the present invention or a display device using a semiconductor device according to one embodiment of the present invention in a display portion.
  • the display device according to one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device can be used in the display portion of various electronic devices.
  • the semiconductor device of one embodiment of the present invention can be applied to portions other than the display portion of an electronic device.
  • the semiconductor device of one embodiment of the present invention in a control portion of an electronic device, it is possible to reduce power consumption, which is preferable.
  • Electronic devices include, for example, electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display device of one embodiment of the present invention can be used in electronic devices having a relatively small display area because it can increase the resolution.
  • electronic devices include wearable devices that can be worn on the wrist, such as wristwatch-type information terminals and bracelet-type information terminals, as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, glasses-type AR devices, SR (Substitutional Reality) devices, and MR (Mixed Reality) devices.
  • the display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (definition) of the display device of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, or 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date, or time, a function to execute various software (programs), a wireless communication function, and a function to read out programs or data recorded on a recording medium.
  • FIG. 67A to 67D An example of a wearable device that can be worn on the head will be described using Figures 67A to 67D.
  • These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content.
  • a function to display AR content a function to display AR content
  • VR content a function to display VR content
  • SR content a function to display SR content
  • MR content a function to display MR content
  • Electronic device 700A shown in FIG. 67A and electronic device 700B shown in FIG. 67B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display device can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.
  • Electronic device 700A and electronic device 700B can each project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visible through optical member 753. Therefore, electronic device 700A and electronic device 700B are each electronic devices capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector may be provided to which a cable through which a video signal and power supply potential can be connected.
  • Electronic device 700A and electronic device 700B are provided with batteries and can be charged wirelessly, wired, or both.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • Various touch sensors can be applied as the touch sensor module.
  • various types can be adopted, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, or an optical type.
  • a capacitance type or an optical type sensor it is preferable to apply to the touch sensor module.
  • a photoelectric conversion element When using an optical touch sensor, a photoelectric conversion element can be used as the light receiving element.
  • the active layer of the photoelectric conversion element can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in FIG. 67C and electronic device 800B shown in FIG. 67D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • a display device can be applied to the display portion 820. Therefore, the electronic device can display images with extremely high resolution. This allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform a three-dimensional display using parallax.
  • the electronic device 800A and the electronic device 800B can each be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that they have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.
  • the attachment unit 823 allows the user to attach the electronic device 800A or electronic device 800B to the head. Note that in FIG. 67C etc., an example is shown in which the attachment unit has a shape similar to the temples of glasses, but this is not limited thereto.
  • the attachment unit 823 only needs to be wearable by the user, and may be, for example, in the shape of a helmet or band.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having the vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio simply by wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies a video signal from a video output device, power for charging a battery provided in the electronic device, and the like.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with the earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 67A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 67C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may have an earphone unit.
  • the electronic device 700B shown in FIG. 67B has an earphone unit 727.
  • the earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • Part of the wiring connecting the earphone unit 727 and the control unit may be disposed inside the housing 721 or the attachment unit 723.
  • electronic device 800B shown in FIG. 67D has earphone unit 827.
  • earphone unit 827 and control unit 824 can be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or mounting unit 823.
  • earphone unit 827 and mounting unit 823 may have magnets. This allows earphone unit 827 to be fixed to mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • electronic devices according to one aspect of the present invention are suitable for both glasses-type devices (such as electronic device 700A and electronic device 700B) and goggle-type devices (such as electronic device 800A and electronic device 800B).
  • the electronic device of one embodiment of the present invention can transmit information to the earphones via wire or wirelessly.
  • the electronic device 6500 shown in FIG. 68A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508.
  • the display portion 6502 has a touch panel function.
  • the display device of one embodiment of the present invention can be applied to the display portion 6502.
  • FIG. 68B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a translucent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back in the area outside the display unit 6502, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted thereon while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • FIG 68C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • a display device can be applied to the display portion 7000.
  • the television set 7100 shown in FIG. 68C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated using operation keys or a touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via a modem it is also possible to perform one-way (only from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 68D shows an example of a notebook personal computer.
  • the notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214.
  • the display unit 7000 is built into the housing 7211.
  • a display device can be applied to the display portion 7000.
  • Figures 68E and 68F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 68E includes a housing 7301, a display unit 7000, and a speaker 7303. It can also include LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 68F shows digital signage 7400 attached to a cylindrical pole 7401.
  • Digital signage 7400 has a display unit 7000 that is provided along the curved surface of pole 7401.
  • a display device according to one embodiment of the present invention can be applied to the display portion 7000.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of an advertisement, for example.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411, such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can also be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • the electronic device shown in Figures 69A to 69G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared), and a microphone 9008.
  • operation keys 9005 including a power switch or an operation switch
  • connection terminal 9006 includes a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrare
  • a display device of one embodiment of the present invention can be applied to the display portion 9001.
  • the electronic devices shown in Figures 69A to 69G have various functions. For example, they can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing by various software (programs), a wireless communication function, and a function to read and process programs or data recorded on a recording medium.
  • the functions of the electronic devices are not limited to these, and they can have various functions.
  • the electronic devices may have multiple display units.
  • the electronic devices may have a camera or the like to capture still images or videos and store them on a recording medium (external or built into the camera), and a function to display the captured images on the display unit.
  • FIG. 69A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as a smartphone, for example.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • FIG. 69A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, or telephone calls, as well as the title, sender name, and date and time of e-mail or SNS. Other examples include the time, remaining battery power, and radio wave strength.
  • an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • Figure 69B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes.
  • a user can check the display without taking the mobile information terminal 9102 out of the pocket and decide whether or not to answer a call.
  • FIG. 69C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom of the housing 9000.
  • FIG. 69D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used, for example, as a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also make hands-free calls by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also transmit data to and from other information terminals and charge itself via a connection terminal 9006. Charging may be performed by wireless power supply.
  • FIG. 69E to 69G are perspective views showing a foldable mobile information terminal 9201.
  • FIG. 69E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • FIG. 69G is a perspective view of the mobile information terminal 9201 in a folded state
  • FIG. 69F is a perspective view of a state in the middle of changing from one of FIG. 69E and FIG. 69G to the other.
  • the mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent viewability of the display.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.
  • the content described in one embodiment can be applied to, combined with, or replaced with another content described in that embodiment (or even a part of the content) and/or the content described in one or more other embodiments (or even a part of the content).
  • a figure (or a part of it) described in one embodiment can be combined with another part of that figure, with another figure (or a part of it) described in that embodiment, and/or with one or more figures (or a part of it) described in another embodiment to form even more figures.
  • the components in the block diagrams are classified by function and shown as independent blocks.
  • it is difficult to separate components by function and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits.
  • the blocks in the block diagrams are not limited to the components described in the specification and may be rephrased appropriately depending on the situation.
  • the terms "one of the source or drain” (or first electrode or first terminal) and “the other of the source or drain” (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.
  • electrode and “wiring” used in this specification and elsewhere do not limit the functionality of these components.
  • an “electrode” may be used as part of a “wiring”, and vice versa.
  • the terms “electrode” and “wiring” also include cases where multiple “electrodes” or “wirings” are formed as a single unit.
  • Voltage refers to the potential difference from a reference potential, and if the reference potential is a ground voltage (earth voltage), for example, voltage can be interchanged with potential. Ground potential does not necessarily mean 0V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.
  • film and “layer” may be interchangeable depending on the circumstances.
  • conductive layer may be changed to the term “conductive film.”
  • insulating film may be changed to the term “insulating layer.”
  • a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows.
  • a switch refers to a device that has the function of selecting and switching the path through which a current flows.
  • the channel length refers to, for example, the distance between the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is on) and the gate overlap in a top view of the transistor, or in the region where the channel is formed.
  • the channel width refers to, for example, the length of the area where the semiconductor (or the part of the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the part where the source and drain face each other in the area where the channel is formed.
  • a and B are connected includes A and B being electrically connected.
  • a and B are electrically connected refers to a connection that allows transmission of an electrical signal between A and B. Therefore, it also includes the case where A and B are connected in a state where electrical signals can be transmitted through one or more objects.
  • Object refers to an element such as a switch or transistor, or a circuit including such an element.
  • a and B are electrically connected indicates that a transmission path of an electrical signal can be formed between A and B. Therefore, when "A and B are electrically connected,” it is not necessary to consider the operating state of the object between A and B.
  • a and B can be in a conductive state when the switch is in an on state, it is considered that "A and B are electrically connected" regardless of whether the switch is in an on state or an off state.
  • a and B are electrically connected includes A and B being directly connected.
  • a and B are directly connected refers to a state in which electrical signals can be transmitted between A and B via wiring (or electrodes) etc., without going through the above-mentioned object.

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