WO2024154283A1 - Gate drive circuit and semiconductor device - Google Patents

Gate drive circuit and semiconductor device Download PDF

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Publication number
WO2024154283A1
WO2024154283A1 PCT/JP2023/001454 JP2023001454W WO2024154283A1 WO 2024154283 A1 WO2024154283 A1 WO 2024154283A1 JP 2023001454 W JP2023001454 W JP 2023001454W WO 2024154283 A1 WO2024154283 A1 WO 2024154283A1
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Prior art keywords
circuit
voltage
potential
power supply
drive signal
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PCT/JP2023/001454
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French (fr)
Japanese (ja)
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隆 井上
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サンケン電気株式会社
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Priority to PCT/JP2023/001454 priority Critical patent/WO2024154283A1/en
Publication of WO2024154283A1 publication Critical patent/WO2024154283A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16—Modifications for eliminating interference voltages or currents

Definitions

  • the present invention relates to a gate drive circuit and a semiconductor device that drive a power semiconductor element.
  • power semiconductor elements e.g., insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and silicon carbide metal oxide semiconductor field effect transistors (SiC-MOSFETs)
  • IGBTs insulated gate bipolar transistors
  • MOSFETs metal oxide semiconductor field effect transistors
  • SiC-MOSFETs silicon carbide metal oxide semiconductor field effect transistors
  • a fixed power supply voltage is supplied to the gate drive circuit that generates the gate drive signal.
  • the voltage applied to the gate of a power semiconductor element is also generally applied with an amplitude between the ground level and the power supply voltage.
  • Patent Document 1 In order to reduce switching losses at turn-on, a gate drive circuit has been proposed that incorporates a conversion circuit that converts the supplied power supply voltage into a high converted voltage (see, for example, Patent Document 1). Patent Document 1 shortens the turn-on time and reduces switching losses by switching the power supply voltage of the drive circuit from a fixed supply voltage to a high converted voltage at turn-on.
  • the present invention was made in consideration of these problems, and its purpose is to provide a gate drive circuit that can drive a power semiconductor element with a gate drive signal with an appropriate profile both when turning on and off.
  • a gate drive circuit according to the present invention is a gate drive circuit that includes a drive signal generation circuit that generates a drive signal based on an input signal and drives a power semiconductor element by the generated drive signal, and includes a regulator circuit that converts a supplied input voltage into different high-potential converted voltage, medium-potential converted voltage, and low-potential converted voltage, respectively, and a power supply switching circuit that, when a transition instructing a turn-on of the input signal is detected, supplies the high-potential converted voltage as a power supply voltage of the drive signal generation circuit, and then supplies the medium-potential converted voltage after a preset first period has elapsed, and, when a transition instructing a turn-off of the input signal is detected, supplies the low-potential converted voltage as the power supply voltage of the drive signal generation circuit, and is characterized in that the drive signal generation circuit raises the drive signal with the high-potential converted voltage as an amplitude at the time of
  • the gate drive circuit of the present invention can apply a gate drive signal with an appropriate profile to a power semiconductor element both when turning on and off, shortening the turn-on time and reducing switching losses when turning on, while also reducing noise when turning off.
  • FIG. 1 is a diagram showing a configuration of a first embodiment of a gate drive circuit according to the present invention
  • 2 is a diagram showing a configuration of a drive signal generating circuit shown in FIG. 1
  • 2 is a waveform diagram showing the operation of the gate drive circuit shown in FIG. 1.
  • FIG. 11 is a diagram showing a configuration of a second embodiment of a gate drive circuit according to the present invention.
  • FIG. 13 is a diagram showing a configuration of a third embodiment of a gate drive circuit according to the present invention.
  • the gate drive circuit 1 of the first embodiment is a driver IC (semiconductor device) that drives a power semiconductor element Q10 (a voltage-driven element such as a SiC-MOSFET) built into a power semiconductor module 10.
  • the power semiconductor element Q10 is a SiC-MOSFET.
  • the power semiconductor module 10 may also have the gate drive circuit 1 built in.
  • the power semiconductor module 10 includes a gate drive signal input terminal T13 connected to the gate of the power semiconductor element Q10, a positive main terminal T11 connected to the drain of the power semiconductor element Q10, and a negative main terminal T12 connected to the source of the power semiconductor element Q10.
  • the gate drive circuit 1 includes a power supply input terminal T1 to which the positive electrode of the input voltage VIN is connected, a ground terminal T2 connected to a ground potential that is the same potential as the negative electrode of the input voltage VIN, an input terminal T3 that receives an input signal (a pulse signal such as a PWM signal) from a higher-level device such as a microcomputer or controller, and an output terminal T4 that outputs a gate drive signal Vgs that drives the power semiconductor element Q10.
  • a pulse signal such as a PWM signal
  • the gate drive circuit 1 includes a first regulator circuit 21 that converts the input voltage VIN supplied to the power supply input terminal T1 into a first conversion voltage V1.
  • the first conversion voltage V1 is set to a voltage that has a low on-resistance when the power semiconductor element Q10 is on and does not affect the life of the power semiconductor element Q10.
  • the gate drive circuit 1 includes a second regulator circuit 22 that converts the input voltage VIN supplied to the power supply input terminal T1 into a second conversion voltage V2 that is higher than the first conversion voltage V1, and a third regulator circuit 23 that converts the input voltage VIN supplied to the power supply input terminal T1 into a third conversion voltage V3 that is lower than the first conversion voltage V1.
  • the first regulator circuit 21, the second regulator circuit 22, and the third regulator circuit 23 may be linear regulator circuits or switching regulator circuits.
  • the gate drive circuit 1 includes a power supply switching circuit 3, a switching signal generating circuit 4, a drive signal generating circuit 5, and a drive circuit 6.
  • the power supply switching circuit 3 switches the power supply voltage Vreg_gs supplied to the drive signal generation circuit 5 and the drive circuit 6 between the first conversion voltage V1, the second conversion voltage V2, and the third conversion voltage V3 based on the on-time switching signal VINH and the off-time switching signal VINL generated by the switching signal generation circuit 4.
  • the power supply switching circuit 3 supplies the first conversion voltage V1 to the drive signal generation circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs.
  • the power supply switching circuit 3 supplies the second conversion voltage V2 to the drive signal generation circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs.
  • the power supply switching circuit 3 supplies the third conversion voltage V3 as the power supply voltage Vreg_gs to the drive signal generation circuit 5 and the drive circuit 6.
  • the power supply switching circuit 3 outputs a power supply switching signal Vch to the drive signal generating circuit 5, which notifies the timing when the power supply voltage Vreg_gs is switched from the first conversion voltage V1 to the second conversion voltage V2 and the timing when the power supply voltage Vreg_gs is switched from the first conversion voltage V1 to the third conversion voltage V3.
  • the power supply switching signal Vch can be configured, for example, as a pulse signal that becomes H level for a predetermined period of time at the timing when the conversion voltage is switched.
  • the switching signal generating circuit 4 generates an on-time switching signal VINH and an off-time switching signal VINL according to the input signal, and outputs them to the power supply switching circuit 3.
  • the switching signal generating circuit 4 sets both the on-time switching signal VINH and the off-time switching signal VINL to the L level.
  • the power supply switching circuit 3 supplies the first converted voltage V1 to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs.
  • the switching signal generating circuit 4 When the switching signal generating circuit 4 detects a transition of the input signal from L level (OFF) to H level (ON), it switches the on-time switching signal VINH to H level, and then switches it to L level after the preset first period P1 has elapsed.
  • the off-time switching signal VINL remains at L level.
  • the power supply switching circuit 3 supplies the second conversion voltage V2, which is higher than the first conversion voltage V1, to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs, and supplies the first conversion voltage V1 to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs after the first period P1 has elapsed.
  • the switching signal generating circuit 4 When the switching signal generating circuit 4 detects a transition of the input signal from H level (ON) to L level (OFF), it switches the off-time switching signal VINL to H level, and returns it to L level after the preset second period P2 has elapsed.
  • the on-time switching signal VINH remains at L level.
  • the power supply switching circuit 3 supplies the third conversion voltage V3, which is lower than the first conversion voltage V1, to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs, and after the second period P2 has elapsed, it supplies the first conversion voltage V1 to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs.
  • a series circuit consisting of a first switch element Q1 and a second switch element Q2 is connected between the power supply voltage Vreg_gs and the ground potential.
  • the first switch element Q1 is a P-type MOSFET
  • the second switch element Q2 is an N-type MOSFET.
  • the source of the first switch element Q1 is connected to the power supply voltage Vreg_gs
  • the drain of the first switch element Q1 is connected to the drain of the second switch element Q2
  • the source of the second switch element Q2 is connected to the ground potential.
  • the drive circuit 6 outputs the voltage signal at the connection point between the drain of the first switch element Q1 and the drain of the second switch element Q2 from the output terminal T4 as the gate drive signal Vgs.
  • the drive signal generation circuit 5 generates a drive signal that drives the drive circuit 6 (first switch element Q1, second switch element Q2) based on the input signal and the power supply switching signal Vch, and outputs the drive signal to the drive circuit 6.
  • the drive signal generating circuit 5 is composed of a signal generating block 51 and a delay block 52, as shown in FIG. 2, for example.
  • the signal generating block 51 and the delay block 52 operate at a voltage between the power supply voltage Vreg_gs and the ground potential.
  • the signal generation block 51 When the input signal transitions (H level to L level, or L level to H level), the signal generation block 51 generates a drive signal that transitions (H level to L level, or L level to H level) after the switching timing (from the first conversion voltage V1 to the second conversion voltage V2, or from the first conversion voltage V1 to the third conversion voltage V3) according to the power supply switching signal Vch.
  • delay block 52 When delay block 52 is configured with a CMOS inverter circuit, the higher the power supply voltage Vreg_gs, the faster the response speed will be, and the lower the power supply voltage Vreg_gs, the slower the response speed will be. In particular, when delay block 52 is configured with multiple CMOS inverter circuits, the delay differences of the elements are added together, so the effect of the value of power supply voltage Vreg_gs on the delay difference of the entire circuit becomes large.
  • the operation of the gate drive circuit 1 at the time of turn-on and turn-off will be described in detail with reference to FIG. First, the operation at the time of turn-on when the input signal transitions from L level to H level will be described.
  • the switching signal generating circuit 4 detects the transition of the input signal from L level to H level (time t1), it transitions the on-time switching signal VINH from L level to H level while maintaining the off-time switching signal VINL at L level.
  • the power supply switching circuit 3 supplies the second conversion voltage V2, which is higher than the first conversion voltage V1, as the power supply voltage Vreg_gs to the drive signal generating circuit 5 and the drive circuit 6.
  • the switching signal generating circuit 4 transitions the on-time switching signal VINH from H level to L level.
  • the on-time switching signal VINH transitions from H level to L level, both the on-time switching signal VINH and the off-time switching signal VINL become L level, and the power supply switching circuit 3 returns the power supply voltage Vreg_gs supplied to the drive signal generating circuit 5 and the drive circuit 6 to the first converted voltage V1.
  • the gate drive signal Vgs becomes the first converted voltage V1, which does not affect the life of the power semiconductor element Q10.
  • the first period P1 is set so that the amplitude of the gate drive signal Vgs is maintained at the second conversion voltage V2 at least until charging of the parasitic capacitance component of the power semiconductor element Q10 is completed.
  • the first period P1 is set so that the gate drive signal Vgs quickly returns to the first conversion voltage V1 after reaching the second conversion voltage V2.
  • the switching signal generating circuit 4 detects the transition of the input signal from H level to L level (time t3), it transitions the off-time switching signal VINL from L level to H level while maintaining the on-time switching signal VINH at L level.
  • the power supply switching circuit 3 supplies the third conversion voltage V3, which is lower than the first conversion voltage V1, as the power supply voltage Vreg_gs to the drive signal generating circuit 5 and the drive circuit 6.
  • the gate drive signal Vgs transitions from H level to L level due to the transition of the drive signal by the drive signal generating circuit 5 from H level to L level.
  • the amplitude of the transition of the gate drive signal Vgs from H level to L level is the third conversion voltage V3, which is lower than the first conversion voltage V1, so the dv/dt becomes gentler, and noise at turn-off can be reduced.
  • the switching signal generating circuit 4 transitions the off-time switching signal VINL from H level to L level.
  • the off-time switching signal VINL transitions from H level to L level, both the on-time switching signal VINH and the off-time switching signal VINL become L level, and the power supply switching circuit 3 returns the power supply voltage Vreg_gs supplied to the drive signal generating circuit 5 and the drive circuit 6 to the first conversion voltage V1.
  • the second period P2 is set so that the gate drive signal Vgs is maintained at the third conversion voltage V3 at least until the gate drive signal Vgs reaches 0V due to turning off.
  • the gate drive circuit 1 switches the power supply voltage Vreg_gs at each timing of turning on (falling) and turning off (falling) of the power semiconductor element Q10, thereby being able to drive the power semiconductor element Q10 with a gate drive signal Vgs of an appropriate profile, and solving problems that arise when turning on and off. In other words, it is possible to reduce not only switching loss when turning on, but also noise when turning off, reduce loss when the power semiconductor element is on, and ensure the lifespan of the power semiconductor element Q10.
  • a gate drive circuit 1a includes the configuration of the gate drive circuit 1 described above, and further includes a power supply output terminal T5 that outputs a power supply voltage Vreg_gs.
  • the power semiconductor module 10a incorporates a drive circuit 11 and has a gate drive signal input terminal T13, a positive main terminal T11, a negative main terminal T12, and a power supply input terminal T14 for the drive circuit 11.
  • Products with specifications such as the power semiconductor module 10a, which incorporates the drive circuit 11, have fixed turn-on and turn-off characteristics and are generally difficult to adjust from the outside depending on the usage environment and conditions.
  • the gate drive circuit 1a can supply the power supply voltage Vreg_gs from the power supply output terminal T5 to the power supply input terminal T14. Therefore, the gate drive circuit 1a can drive the power semiconductor element Q10 with a gate drive signal Vgs of an appropriate profile even for products with such specifications.
  • a gate drive circuit 1b according to the third embodiment includes, in addition to the configuration of the gate drive circuit 1 described above, a high potential switching terminal T6, a low potential switching terminal T7, and a switching selection terminal T8.
  • the high potential switching terminal T6 is a terminal for instructing the second regulator circuit 22a to switch the conversion voltage.
  • the second regulator circuit 22a when the high potential switching terminal T6 is unconnected or at L level, the second regulator circuit 22a is configured to be able to convert the input voltage VIN to the second conversion voltage V2, and when the high potential switching terminal T6 is at H level, the input voltage VIN to a fourth conversion voltage V4 higher than the second conversion voltage V2.
  • the second regulator circuit 22a may be configured to be able to convert to three or more types of high potentials (higher than the first conversion voltage V1). This allows the gate drive circuit 1b to select the power supply voltage Vreg_gs at turn-on from multiple high potentials, and the profile of the gate drive signal Vgs at turn-on can be further optimized.
  • the low potential switching terminal T7 is a terminal for instructing the third regulator circuit 23a to switch the conversion voltage.
  • the third regulator circuit 23a when the low potential switching terminal T7 is unconnected or at L level, the third regulator circuit 23a is configured to be able to convert the input voltage VIN to a third conversion voltage V3, and when the low potential switching terminal T7 is at H level, the input voltage VIN to a fifth conversion voltage V5 higher than the third conversion voltage V3.
  • the third regulator circuit 23a may be configured to be able to convert to three or more types of low potential (lower than the first conversion voltage V1). This allows the gate drive circuit 1b to select the power supply voltage Vreg_gs at the time of turn-off from among multiple low potentials, and the profile of the gate drive signal Vgs at the time of turn-off can be further optimized.
  • the switching selection terminal T8 is a terminal for selecting the switching operation of the power supply switching circuit 3a. For example, when the switching selection terminal T8 is not connected or is at L level, the power supply switching circuit 3a executes the switching operation of the first embodiment, and when the low potential switching terminal T7 is at H level, the switching operation is executed only at turn-on (or turn-off).
  • this embodiment is a gate drive circuit 1 that includes a drive signal generation circuit (drive signal generation circuit 5, drive circuit 6) that generates a drive signal (gate drive signal Vgs) based on an input signal, and drives a power semiconductor element Q10 by the generated gate drive signal Vgs, and includes regulator circuits (second regulator circuit 22, first regulator circuit 21, third regulator circuit 23) that convert a supplied input voltage VIN into different high-potential converted voltages (second converted voltage V2), medium-potential converted voltages (first converted voltage V1), and low-potential converted voltages (third converted voltage V3), and a transition circuit (transition circuit 24) that instructs turning on the power semiconductor element Q10 of the input signal.
  • a drive signal generation circuit drive signal generation circuit 5, drive circuit 6) that generates a drive signal (gate drive signal Vgs) based on an input signal, and drives a power semiconductor element Q10 by the generated gate drive signal Vgs
  • regulator circuits second regulator circuit 22, first regulator circuit 21, third regulator circuit 23
  • transition circuit 24 transition circuit that instructs turning on
  • a power supply switching circuit 3 that, when a transition of the input signal instructing to turn off the power semiconductor element Q10 is detected, supplies a second converted voltage V2 as the power supply voltage Vreg_gs of the drive signal generation circuit 5 and the drive circuit 6, and then supplies the first converted voltage V1 after a preset first period P1 has elapsed, and, when a transition of the input signal instructing to turn off the power semiconductor element Q10 is detected, supplies a third converted voltage V3 as the power supply voltage Vreg_gs of the drive signal generation circuit 5 and the drive circuit 6, and the drive signal generation circuit 5 and the drive circuit 6 raise the gate drive signal Vgs with the second converted voltage V2 as an amplitude at the time of turn-on, and lowers the gate drive signal Vgs with the second converted voltage V2 as an amplitude at the time of turn-off.
  • the gate drive circuit 1 can apply a gate drive signal Vgs with an appropriate profile to the power semiconductor element Q10 both at turn-on and turn-off, thereby shortening the turn-on time and reducing switching loss at turn-on as well as reducing noise at turn-off.
  • the first period P1 is set so that the amplitude of the gate drive signal Vgs is maintained at the second converted voltage V2 at least until charging of the parasitic capacitance component of the power semiconductor element Q10 is completed.
  • the gate drive circuit 1 can reduce the charging time for the parasitic capacitance component of the power semiconductor element Q10, and reduce the turn-on time.
  • this embodiment includes a drive circuit 6 in which a series circuit made up of a first switch element Q1 and a second switch element Q2 is connected between a power supply voltage Vreg_gs and a ground potential, and a drive signal generation circuit 5 that generates a drive signal for driving the first switch element Q1 and the second switch element Q2.
  • the drive signal generation circuit 5 has a delay block 52 made up of multiple stages of CMOS inverter circuits connected between the power supply voltage Vreg_gs and the ground potential. This configuration can improve the response at turn-on.
  • this embodiment includes a power supply output terminal T5 that outputs a power supply voltage Vreg_gs.
  • the gate drive circuit 1a can drive the power semiconductor element Q10 with a gate drive signal Vgs having an appropriate profile, even if the gate drive circuit 1a is a power semiconductor module 10a that includes a drive circuit 11 built therein.
  • this embodiment is provided with a high potential switching terminal T6 that instructs switching of the high potential conversion voltage converted by the second regulator circuit 22a, and the second regulator circuit 22a is capable of converting the high potential conversion voltage into a plurality of different potentials (second conversion voltage V2, fourth conversion voltage V4) depending on the state of the high potential switching terminal T6.
  • the gate drive circuit 1b can select the power supply voltage Vreg_gs at turn-on from among a plurality of high potentials, and the profile of the gate drive signal Vgs at turn-on can be further optimized.
  • this embodiment is provided with a low-potential switching terminal T7 that instructs switching of the low-potential converted voltage converted by the third regulator circuit 23a, and the third regulator circuit 23a is capable of converting the low-potential converted voltage into a plurality of different potentials (the third converted voltage V3, the fifth converted voltage V5) depending on the state of the low-potential switching terminal T7.
  • the gate drive circuit 1b can select the power supply voltage Vreg_gs at turn-off from among a plurality of low potentials, and the profile of the gate drive signal Vgs at turn-off can be further optimized.

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  • Power Conversion In General (AREA)

Abstract

Provided is a gate drive circuit that can drive a power semiconductor element Q10 using a gate drive signal of an appropriate profile both when turned on and when turned off.　The present invention comprises: a second regulator circuit 22, a first regulator circuit 21, and a third regulator circuit 23 that respectively convert input voltage VIN to a second conversion voltage V2, a first conversion voltage V1, and a third conversion voltage V3, the conversion voltages being different from one another; and a power supply switching circuit 3 that, when a transition instructing that an input signal be turned on is detected, supplies the second conversion voltage V2 as power supply voltage Vreg_gs of a drive-signal-generating circuit 5 and a drive circuit 6 and then supplies the first conversion voltage V1 after a preset first period has elapsed, and, when a transition instructing that the input signal be turned off is detected, supplies the third conversion voltage V3 as the power supply voltage Vreg_gs of the drive-signal-generating circuit 5 and the drive circuit 6.

Description

ゲートドライブ回路及び半導体装置Gate drive circuit and semiconductor device
　本発明は、パワー半導体素子を駆動するゲートドライブ回路及び半導体装置に関するものである。 The present invention relates to a gate drive circuit and a semiconductor device that drive a power semiconductor element.
　多くの電気機器は、電気エネルギーの変換や、モーター駆動等でパワー半導体素子（例えば、絶縁ゲートバイポーラトランジスタ（ＩＧＢＴ）、金属酸化物半導体電界効果トランジスタ（ＭＯＳＦＥＴ）、炭化ケイ素基板の金属酸化物半導体電界効果トランジスタ（ＳｉＣ－ＭＯＳＦＥＴ））が使用されている。パワー半導体素子の駆動は、ゲートに印加するゲート駆動信号によって行われる。パワー半導体素子は、ターンオン時間、ターンオフ時間等に応じて、スイッチング損失、寿命、遷移時のノイズが変化する。そのため、パワー半導体素子には、適正なプロファイルのゲート駆動信号を印加する必要がある。 Many electrical devices use power semiconductor elements (e.g., insulated gate bipolar transistors (IGBTs), metal oxide semiconductor field effect transistors (MOSFETs), and silicon carbide metal oxide semiconductor field effect transistors (SiC-MOSFETs)) for electrical energy conversion, motor drive, etc. Power semiconductor elements are driven by a gate drive signal applied to the gate. Power semiconductor elements vary in switching loss, lifespan, and noise during transitions depending on the turn-on time, turn-off time, etc. For this reason, it is necessary to apply a gate drive signal with an appropriate profile to power semiconductor elements.
　通常、ゲート駆動信号を生成するゲートドライブ回路には、固定された電源電圧が供給されている。パワー半導体素子のゲートへの印加電圧も、接地レベルと、電源電圧の間の振幅で印加されることが一般的である。 Normally, a fixed power supply voltage is supplied to the gate drive circuit that generates the gate drive signal. The voltage applied to the gate of a power semiconductor element is also generally applied with an amplitude between the ground level and the power supply voltage.
　ターンオン時のスイッチング損失を低減するため、供給されている電源電圧を高い変換電圧に変換する変換回路を内蔵するゲートドライブ回路が提案されている（例えば、特許文献１参照）。特許文献１は、ターンオン時において、駆動回路の電源電圧を固定供給電圧から、高い変換電圧に切り替えることで、ターンオン時間を短くし、スイッチング損失を低減している。 In order to reduce switching losses at turn-on, a gate drive circuit has been proposed that incorporates a conversion circuit that converts the supplied power supply voltage into a high converted voltage (see, for example, Patent Document 1). Patent Document 1 shortens the turn-on time and reduces switching losses by switching the power supply voltage of the drive circuit from a fixed supply voltage to a high converted voltage at turn-on.
米国特許第１０７９０８１８号明細書U.S. Pat. No. 1,079,0818
　しかしながら、先行技術では、ターンオフ時の課題について考慮されておらず、ターンオフ時に発生するノイズを低減できないという問題点があった。 However, the prior art did not take into consideration issues that occur when turning off, and had the problem of being unable to reduce noise that occurs when turning off.
　本発明は斯かる問題点を鑑みてなされたものであり、その目的とするところは、ターンオン時、ターンオフ時のいずれにおいても適正なプロファイルのゲート駆動信号でパワー半導体素子を駆動できるゲートドライブ回路を提供する点にある。 The present invention was made in consideration of these problems, and its purpose is to provide a gate drive circuit that can drive a power semiconductor element with a gate drive signal with an appropriate profile both when turning on and off.
　本発明に係るゲートドライブ回路は、上記の目的を達成するため、次のように構成される。
　本発明に係るゲートドライブ回路は、入力信号に基づいて駆動信号を生成する前記駆動信号生成回路を備え、生成した駆動信号によってパワー半導体素子を駆動するゲートドライブ回路であって、供給される入力電圧を異なる高電位変換電圧、中電位変換電圧、低電位変換電圧にそれぞれ変換するレギュレータ回路と、前記入力信号のターンオンを指示する遷移を検出した場合、前記駆動信号生成回路の電源電圧として前記高電位変換電圧を供給した後、予め設定された第１期間が経過した後に前記中電位変換電圧を供給し、前記入力信号のターンオフを指示する遷移を検出した場合、前記駆動信号生成回路の前記電源電圧として前記低電位変換電圧を供給する電源切換回路と、を具備し、前記駆動信号生成回路は、ターンオン時に前記高電位変換電圧を振幅として前記駆動信号を立上げ、ターンオフ時に前記低電位変換電圧を振幅として前記駆動信号を立下げることを特徴とする。 In order to achieve the above object, the gate drive circuit according to the present invention is configured as follows.
A gate drive circuit according to the present invention is a gate drive circuit that includes a drive signal generation circuit that generates a drive signal based on an input signal and drives a power semiconductor element by the generated drive signal, and includes a regulator circuit that converts a supplied input voltage into different high-potential converted voltage, medium-potential converted voltage, and low-potential converted voltage, respectively, and a power supply switching circuit that, when a transition instructing a turn-on of the input signal is detected, supplies the high-potential converted voltage as a power supply voltage of the drive signal generation circuit, and then supplies the medium-potential converted voltage after a preset first period has elapsed, and, when a transition instructing a turn-off of the input signal is detected, supplies the low-potential converted voltage as the power supply voltage of the drive signal generation circuit, and is characterized in that the drive signal generation circuit raises the drive signal with the high-potential converted voltage as an amplitude at the time of turn-on, and lowers the drive signal with the low-potential converted voltage as an amplitude at the time of turn-off.
　本発明のゲートドライブ回路は、ターンオン時、ターンオフ時のいずれにおいても適正なプロファイルのゲート駆動信号をパワー半導体素子に印加でき、ターンオン時間を短縮してターンオン時のスイッチング損失の低減が図れると共に、ターンオフ時のノイズの低減が図れる。 The gate drive circuit of the present invention can apply a gate drive signal with an appropriate profile to a power semiconductor element both when turning on and off, shortening the turn-on time and reducing switching losses when turning on, while also reducing noise when turning off.
本発明に係るゲートドライブ回路の第１の実施の形態の構成を示す図である。1 is a diagram showing a configuration of a first embodiment of a gate drive circuit according to the present invention; 図１に示すドライブ信号生成回路の構成を示す図である。2 is a diagram showing a configuration of a drive signal generating circuit shown in FIG. 1; 図１に示すゲートドライブ回路の動作を示す波形図である。2 is a waveform diagram showing the operation of the gate drive circuit shown in FIG. 1. 本発明に係るゲートドライブ回路の第２の実施の形態の構成を示す図である。FIG. 11 is a diagram showing a configuration of a second embodiment of a gate drive circuit according to the present invention. 本発明に係るゲートドライブ回路の第３の実施の形態の構成を示す図である。FIG. 13 is a diagram showing a configuration of a third embodiment of a gate drive circuit according to the present invention.
　以下に、本発明の好適な実施の形態を添付図面に基づいて説明する。 Below, a preferred embodiment of the present invention will be described with reference to the attached drawings.
（第１の実施の形態）
　第１の本実施の形態のゲートドライブ回路１は、図１を参照すると、パワー半導体モジュール１０に内蔵されたパワー半導体素子Ｑ１０（ＳｉＣ－ＭＯＳＦＥＴ等の電圧駆動型の素子）を駆動するドライバＩＣ（半導体装置）である。以下の説明では、パワー半導体素子Ｑ１０は、ＳｉＣ－ＭＯＳＦＥＴとする。パワー半導体モジュール１０は、ゲートドライブ回路１も内蔵させてもよい。 First Embodiment
1, the gate drive circuit 1 of the first embodiment is a driver IC (semiconductor device) that drives a power semiconductor element Q10 (a voltage-driven element such as a SiC-MOSFET) built into a power semiconductor module 10. In the following description, the power semiconductor element Q10 is a SiC-MOSFET. The power semiconductor module 10 may also have the gate drive circuit 1 built in.
　パワー半導体モジュール１０は、パワー半導体素子Ｑ１０のゲートに接続されたゲート駆動信号入力端子Ｔ１３と、パワー半導体素子Ｑ１０のドレインに接続された正側主端子Ｔ１１と、パワー半導体素子Ｑ１０のソースに接続された負側主端子Ｔ１２と、を備える。 The power semiconductor module 10 includes a gate drive signal input terminal T13 connected to the gate of the power semiconductor element Q10, a positive main terminal T11 connected to the drain of the power semiconductor element Q10, and a negative main terminal T12 connected to the source of the power semiconductor element Q10.
　ゲートドライブ回路１は、入力電圧ＶＩＮの正極が接続される電源入力端子Ｔ１と、入力電圧ＶＩＮの負極と同電位のグランド電位に接続されるグランド端子Ｔ２と、マイコン、コントローラ等の上位装置からの入力信号（ＰＷＭ信号等のパルス信号）を受け付ける入力端子Ｔ３と、パワー半導体素子Ｑ１０を駆動するゲート駆動信号Ｖｇｓを出力する出力端子Ｔ４と、を備える。 The gate drive circuit 1 includes a power supply input terminal T1 to which the positive electrode of the input voltage VIN is connected, a ground terminal T2 connected to a ground potential that is the same potential as the negative electrode of the input voltage VIN, an input terminal T3 that receives an input signal (a pulse signal such as a PWM signal) from a higher-level device such as a microcomputer or controller, and an output terminal T4 that outputs a gate drive signal Vgs that drives the power semiconductor element Q10.
　ゲートドライブ回路１は、電源入力端子Ｔ１に供給される入力電圧ＶＩＮを第１変換電圧Ｖ１に変換する第１レギュレータ回路２１を備える。第１変換電圧Ｖ１は、パワー半導体素子Ｑ１０のオン時にオン抵抗が低く、且つパワー半導体素子Ｑ１０の寿命に影響を与えない電圧に設定される。ゲートドライブ回路１は、電源入力端子Ｔ１に供給される入力電圧ＶＩＮを第１変換電圧Ｖ１よりも高い第２変換電圧Ｖ２に変換する第２レギュレータ回路２２と、電源入力端子Ｔ１に供給される入力電圧ＶＩＮを第１変換電圧Ｖ１よりも低い第３変換電圧Ｖ３に変換する第３レギュレータ回路２３と、を備える。第１レギュレータ回路２１、第２レギュレータ回路２２、第３レギュレータ回路２３は、リニアレギュレータ回路でもスイッチングレギュレータ回路でもよい。 The gate drive circuit 1 includes a first regulator circuit 21 that converts the input voltage VIN supplied to the power supply input terminal T1 into a first conversion voltage V1. The first conversion voltage V1 is set to a voltage that has a low on-resistance when the power semiconductor element Q10 is on and does not affect the life of the power semiconductor element Q10. The gate drive circuit 1 includes a second regulator circuit 22 that converts the input voltage VIN supplied to the power supply input terminal T1 into a second conversion voltage V2 that is higher than the first conversion voltage V1, and a third regulator circuit 23 that converts the input voltage VIN supplied to the power supply input terminal T1 into a third conversion voltage V3 that is lower than the first conversion voltage V1. The first regulator circuit 21, the second regulator circuit 22, and the third regulator circuit 23 may be linear regulator circuits or switching regulator circuits.
　ゲートドライブ回路１は、電源切換回路３と、切換信号生成回路４と、ドライブ信号生成回路５と、ドライブ回路６と、を備える。 The gate drive circuit 1 includes a power supply switching circuit 3, a switching signal generating circuit 4, a drive signal generating circuit 5, and a drive circuit 6.
　電源切換回路３は、切換信号生成回路４によって生成されるオン時切換信号ＶＩＮＨ及びオフ時切換信号ＶＩＮＬに基づいて、ドライブ信号生成回路５及びドライブ回路６に供給する電源電圧Ｖｒｅｇ＿ｇｓを第１変換電圧Ｖ１と第２変換電圧Ｖ２と第３変換電圧Ｖ３との何れかに切り換える。電源切換回路３は、オン時切換信号ＶＩＮＨがＬレベル且つオフ時切換信号ＶＩＮＬがＬレベルの場合、第１変換電圧Ｖ１を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給する。電源切換回路３は、オン時切換信号ＶＩＮＨがＨレベル且つオフ時切換信号ＶＩＮＬがＬレベルの場合、第２変換電圧Ｖ２を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給する。電源切換回路３は、オン時切換信号ＶＩＮＨがＬレベル且つオフ時切換信号ＶＩＮＬがＨレベルの場合、第３変換電圧Ｖ３を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給する。 The power supply switching circuit 3 switches the power supply voltage Vreg_gs supplied to the drive signal generation circuit 5 and the drive circuit 6 between the first conversion voltage V1, the second conversion voltage V2, and the third conversion voltage V3 based on the on-time switching signal VINH and the off-time switching signal VINL generated by the switching signal generation circuit 4. When the on-time switching signal VINH is at L level and the off-time switching signal VINL is at L level, the power supply switching circuit 3 supplies the first conversion voltage V1 to the drive signal generation circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs. When the on-time switching signal VINH is at H level and the off-time switching signal VINL is at L level, the power supply switching circuit 3 supplies the second conversion voltage V2 to the drive signal generation circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs. When the on-time switching signal VINH is at L level and the off-time switching signal VINL is at H level, the power supply switching circuit 3 supplies the third conversion voltage V3 as the power supply voltage Vreg_gs to the drive signal generation circuit 5 and the drive circuit 6.
　電源切換回路３は、電源電圧Ｖｒｅｇ＿ｇｓを第１変換電圧Ｖ１から第２変換電圧Ｖ２に切り換えたタイミングと、電源電圧Ｖｒｅｇ＿ｇｓを第１変換電圧Ｖ１から第３変換電圧Ｖ３に切り換えたタイミングとを通知する電源切換信号Ｖｃｈをドライブ信号生成回路５に出力する。電源切換信号Ｖｃｈは、例えば、変換電圧の切り換えタイミングで所定期間Ｈレベルとなるパルス信号で構成できる。 The power supply switching circuit 3 outputs a power supply switching signal Vch to the drive signal generating circuit 5, which notifies the timing when the power supply voltage Vreg_gs is switched from the first conversion voltage V1 to the second conversion voltage V2 and the timing when the power supply voltage Vreg_gs is switched from the first conversion voltage V1 to the third conversion voltage V3. The power supply switching signal Vch can be configured, for example, as a pulse signal that becomes H level for a predetermined period of time at the timing when the conversion voltage is switched.
　切換信号生成回路４は、入力信号に応じたオン時切換信号ＶＩＮＨ及びオフ時切換信号ＶＩＮＬを生成し、電源切換回路３に出力する。切換信号生成回路４は、入力信号がＬレベル（ＯＦＦ）、またはＨレベル（ＯＮ）に固定されている場合、オン時切換信号ＶＩＮＨ及びオフ時切換信号ＶＩＮＬのいずれもＬレベルとする。これにより、電源切換回路３は、第１変換電圧Ｖ１を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給する。 The switching signal generating circuit 4 generates an on-time switching signal VINH and an off-time switching signal VINL according to the input signal, and outputs them to the power supply switching circuit 3. When the input signal is fixed to the L level (OFF) or H level (ON), the switching signal generating circuit 4 sets both the on-time switching signal VINH and the off-time switching signal VINL to the L level. As a result, the power supply switching circuit 3 supplies the first converted voltage V1 to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs.
　切換信号生成回路４は、入力信号のＬレベル（ＯＦＦ）からＨレベル（ＯＮ）への遷移を検出すると、オン時切換信号ＶＩＮＨをＨレベルに切り換え、予め設定された第１期間Ｐ１が経過した後にＬレベルに切り換える。オフ時切換信号ＶＩＮＬは、Ｌレベルのままである。これにより、電源切換回路３は、第１変換電圧Ｖ１よりも高い第２変換電圧Ｖ２を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給し、第１期間Ｐ１が経過した後に第１変換電圧Ｖ１を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給する。 When the switching signal generating circuit 4 detects a transition of the input signal from L level (OFF) to H level (ON), it switches the on-time switching signal VINH to H level, and then switches it to L level after the preset first period P1 has elapsed. The off-time switching signal VINL remains at L level. As a result, the power supply switching circuit 3 supplies the second conversion voltage V2, which is higher than the first conversion voltage V1, to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs, and supplies the first conversion voltage V1 to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs after the first period P1 has elapsed.
　切換信号生成回路４は、入力信号のＨレベル（ＯＮ）からＬレベル（ＯＦＦ）への遷移を検出すると、オフ時切換信号ＶＩＮＬをＨレベルに切り換え、予め設定された第２期間Ｐ２が経過した後Ｌレベルに戻す。オン時切換信号ＶＩＮＨは、Ｌレベルのままである。これにより、電源切換回路３は、第１変換電圧Ｖ１よりも低い第３変換電圧Ｖ３を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給し、第２期間Ｐ２が経過した後第１変換電圧Ｖ１を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給する。 When the switching signal generating circuit 4 detects a transition of the input signal from H level (ON) to L level (OFF), it switches the off-time switching signal VINL to H level, and returns it to L level after the preset second period P2 has elapsed. The on-time switching signal VINH remains at L level. As a result, the power supply switching circuit 3 supplies the third conversion voltage V3, which is lower than the first conversion voltage V1, to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs, and after the second period P2 has elapsed, it supplies the first conversion voltage V1 to the drive signal generating circuit 5 and the drive circuit 6 as the power supply voltage Vreg_gs.
　ドライブ回路６は、第１スイッチ素子Ｑ１と第２スイッチ素子Ｑ２とからなる直列回路が電源電圧Ｖｒｅｇ＿ｇｓとグランド電位との間に接続されている。第１スイッチ素子Ｑ１は、Ｐ型のＭＯＳＦＥＴで、第２スイッチ素子Ｑ２は、Ｎ型のＭＯＳＦＥＴでそれぞれ構成される。第１スイッチ素子Ｑ１のソースが電源電圧Ｖｒｅｇ＿ｇｓに、第１スイッチ素子Ｑ１のドレインが第２スイッチ素子Ｑ２のドレインに、第２スイッチ素子Ｑ２のソースがグランド電位それぞれ接続される。ドライブ回路６は、第１スイッチ素子Ｑ１のドレインと第２スイッチ素子Ｑ２のドレインとの接続点の電圧信号をゲート駆動信号Ｖｇｓとして出力端子Ｔ４から出力する。 In the drive circuit 6, a series circuit consisting of a first switch element Q1 and a second switch element Q2 is connected between the power supply voltage Vreg_gs and the ground potential. The first switch element Q1 is a P-type MOSFET, and the second switch element Q2 is an N-type MOSFET. The source of the first switch element Q1 is connected to the power supply voltage Vreg_gs, the drain of the first switch element Q1 is connected to the drain of the second switch element Q2, and the source of the second switch element Q2 is connected to the ground potential. The drive circuit 6 outputs the voltage signal at the connection point between the drain of the first switch element Q1 and the drain of the second switch element Q2 from the output terminal T4 as the gate drive signal Vgs.
　ドライブ信号生成回路５は、入力信号と電源切換信号Ｖｃｈとに基づいてドライブ回路６（第１スイッチ素子Ｑ１、第２スイッチ素子Ｑ２）を駆動するドライブ信号を生成し、ドライブ回路６に出力する。 The drive signal generation circuit 5 generates a drive signal that drives the drive circuit 6 (first switch element Q1, second switch element Q2) based on the input signal and the power supply switching signal Vch, and outputs the drive signal to the drive circuit 6.
　ドライブ信号生成回路５は、例えば、図２に示すように、信号生成ブロック５１と、遅延ブロック５２と、で構成される。信号生成ブロック５１及び遅延ブロック５２は、電源電圧Ｖｒｅｇ＿ｇｓとグランド電位間の電圧で動作する。 The drive signal generating circuit 5 is composed of a signal generating block 51 and a delay block 52, as shown in FIG. 2, for example. The signal generating block 51 and the delay block 52 operate at a voltage between the power supply voltage Vreg_gs and the ground potential.
　信号生成ブロック５１は、入力信号が遷移（ＨレベルからＬレベル、もしくはＬレベルがＨレベル）すると、電源切換信号Ｖｃｈによって切り換えタイミング（第１変換電圧Ｖ１から第２変換電圧Ｖ２、第１変換電圧Ｖ１から第３変換電圧Ｖ３）後に遷移（ＨレベルからＬレベル、もしくはＬレベルがＨレベル）するドライブ信号を生成する。 When the input signal transitions (H level to L level, or L level to H level), the signal generation block 51 generates a drive signal that transitions (H level to L level, or L level to H level) after the switching timing (from the first conversion voltage V1 to the second conversion voltage V2, or from the first conversion voltage V1 to the third conversion voltage V3) according to the power supply switching signal Vch.
　遅延ブロック５２をＣＭＯＳインバーター回路で構成した場合、応答スピードは、電源電圧Ｖｒｅｇ＿ｇｓが高いほど速く動作し、低いほど遅く動作する。特に、遅延ブロック５２がＣＭＯＳインバーター回路の多段構成になっている場合、素子の遅延差が加算されるため、電源電圧Ｖｒｅｇ＿ｇｓの値による回路全体の遅延差への影響は、大きくなる。 When delay block 52 is configured with a CMOS inverter circuit, the higher the power supply voltage Vreg_gs, the faster the response speed will be, and the lower the power supply voltage Vreg_gs, the slower the response speed will be. In particular, when delay block 52 is configured with multiple CMOS inverter circuits, the delay differences of the elements are added together, so the effect of the value of power supply voltage Vreg_gs on the delay difference of the entire circuit becomes large.
　次に、ゲートドライブ回路１におけるターンオン時及びターンオフ時の動作について図３を参照して詳細に説明する。
　まず、入力信号がＬレベルからＨレベルに遷移するターンオン時の動作について説明する。切換信号生成回路４は、入力信号のＬレベルからＨレベルへの遷移を検出すると（時刻ｔ１）、オフ時切換信号ＶＩＮＬはＬレベルを維持した状態で、オン時切換信号ＶＩＮＨをＬレベルからＨレベルに遷移させる。オン時切換信号ＶＩＮＨのＬレベルからＨレベルへの遷移により、電源切換回路３は、第１変換電圧Ｖ１よりも高い第２変換電圧Ｖ２を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給する。これにより、ドライブ信号生成回路５及びドライブ回路６の駆動能力が上昇するため、ゲート駆動信号Ｖｇｓが急峻に立ち上がり、負荷となるパワー半導体素子Ｑ１０の寄生容量成分への充電時間が短縮され、ターンオン時間の短縮、しいてはターンオン時のスイッチング損失の低減が図れる。 Next, the operation of the gate drive circuit 1 at the time of turn-on and turn-off will be described in detail with reference to FIG.
First, the operation at the time of turn-on when the input signal transitions from L level to H level will be described. When the switching signal generating circuit 4 detects the transition of the input signal from L level to H level (time t1), it transitions the on-time switching signal VINH from L level to H level while maintaining the off-time switching signal VINL at L level. When the on-time switching signal VINH transitions from L level to H level, the power supply switching circuit 3 supplies the second conversion voltage V2, which is higher than the first conversion voltage V1, as the power supply voltage Vreg_gs to the drive signal generating circuit 5 and the drive circuit 6. This increases the driving capabilities of the drive signal generating circuit 5 and the drive circuit 6, so that the gate drive signal Vgs rises steeply, and the charging time to the parasitic capacitance component of the power semiconductor element Q10, which serves as a load, is shortened, thereby shortening the turn-on time and reducing the switching loss at the time of turn-on.
　切換信号生成回路４は、オン時切換信号ＶＩＮＨを時刻ｔ１でＨレベルに遷移させてから予め設定された第１期間Ｐ１が経過すると（時刻ｔ２）、オン時切換信号ＶＩＮＨをＨレベルからＬレベルに遷移させる。オン時切換信号ＶＩＮＨのＨレベルからＬレベルへの遷移により、オン時切換信号ＶＩＮＨ及びオフ時切換信号ＶＩＮＬのいずれもがＬレベルとなり、電源切換回路３は、ドライブ信号生成回路５及びドライブ回路６に供給する電源電圧Ｖｒｅｇ＿ｇｓを第１変換電圧Ｖ１に戻す。これにより、ゲート駆動信号Ｖｇｓは、パワー半導体素子Ｑ１０の寿命に影響を与えない第１変換電圧Ｖ１になる。 When a preset first period P1 has elapsed (time t2) since the on-time switching signal VINH was transitioned to H level at time t1, the switching signal generating circuit 4 transitions the on-time switching signal VINH from H level to L level. As the on-time switching signal VINH transitions from H level to L level, both the on-time switching signal VINH and the off-time switching signal VINL become L level, and the power supply switching circuit 3 returns the power supply voltage Vreg_gs supplied to the drive signal generating circuit 5 and the drive circuit 6 to the first converted voltage V1. As a result, the gate drive signal Vgs becomes the first converted voltage V1, which does not affect the life of the power semiconductor element Q10.
　第１期間Ｐ１は、少なくともパワー半導体素子Ｑ１０の寄生容量成分への充電が完了するまでは、ゲート駆動信号Ｖｇｓの振幅が第２変換電圧Ｖ２に維持されるように設定される。また、第１期間Ｐ１は、ゲート駆動信号Ｖｇｓが第２変換電圧Ｖ２に到達後に速やかに第１変換電圧Ｖ１に戻るように設定される。 The first period P1 is set so that the amplitude of the gate drive signal Vgs is maintained at the second conversion voltage V2 at least until charging of the parasitic capacitance component of the power semiconductor element Q10 is completed. In addition, the first period P1 is set so that the gate drive signal Vgs quickly returns to the first conversion voltage V1 after reaching the second conversion voltage V2.
　次に、入力信号がＨレベルからＬレベルに遷移するターンオフ時の動作について説明する。切換信号生成回路４は、入力信号のＨレベルからＬレベルへの遷移を検出すると（時刻ｔ３）、オン時切換信号ＶＩＮＨはＬレベルを維持した状態で、オフ時切換信号ＶＩＮＬをＬレベルからＨレベルに遷移させる。オフ時切換信号ＶＩＮＬのＬレベルからＨレベルへの遷移により、電源切換回路３は、第１変換電圧Ｖ１よりも低い第３変換電圧Ｖ３を電源電圧Ｖｒｅｇ＿ｇｓとしてドライブ信号生成回路５及びドライブ回路６に供給する。電源電圧Ｖｒｅｇ＿ｇｓが第３変換電圧Ｖ３に切り換わった後、ドライブ信号生成回路５によるドライブ信号のＨレベルからＬレベルへの遷移により、ゲート駆動信号ＶｇｓがＨレベルからＬレベルに遷移する。ゲート駆動信号ＶｇｓのＨレベルからＬレベルへの遷移の振幅は、第１変換電圧Ｖ１よりも低い第３変換電圧Ｖ３となるため、ｄｖ／ｄｔが緩やかになり、ターンオフ時のノイズの低減が図れる。 Next, the operation at the time of turn-off when the input signal transitions from H level to L level will be described. When the switching signal generating circuit 4 detects the transition of the input signal from H level to L level (time t3), it transitions the off-time switching signal VINL from L level to H level while maintaining the on-time switching signal VINH at L level. With the transition of the off-time switching signal VINL from L level to H level, the power supply switching circuit 3 supplies the third conversion voltage V3, which is lower than the first conversion voltage V1, as the power supply voltage Vreg_gs to the drive signal generating circuit 5 and the drive circuit 6. After the power supply voltage Vreg_gs is switched to the third conversion voltage V3, the gate drive signal Vgs transitions from H level to L level due to the transition of the drive signal by the drive signal generating circuit 5 from H level to L level. The amplitude of the transition of the gate drive signal Vgs from H level to L level is the third conversion voltage V3, which is lower than the first conversion voltage V1, so the dv/dt becomes gentler, and noise at turn-off can be reduced.
　切換信号生成回路４は、オフ時切換信号ＶＩＮＬを時刻ｔ３でＨレベルに遷移させてから予め設定された第２期間Ｐ２が経過すると（時刻ｔ４）、オフ時切換信号ＶＩＮＬをＨレベルからＬレベルに遷移させる。オフ時切換信号ＶＩＮＬのＨレベルからＬレベルへの遷移により、オン時切換信号ＶＩＮＨ及びオフ時切換信号ＶＩＮＬのいずれもがＬレベルとなり、電源切換回路３は、ドライブ信号生成回路５及びドライブ回路６に供給する電源電圧Ｖｒｅｇ＿ｇｓを第１変換電圧Ｖ１に戻す。 When the preset second period P2 has elapsed (time t4) since the off-time switching signal VINL was transitioned to H level at time t3, the switching signal generating circuit 4 transitions the off-time switching signal VINL from H level to L level. As the off-time switching signal VINL transitions from H level to L level, both the on-time switching signal VINH and the off-time switching signal VINL become L level, and the power supply switching circuit 3 returns the power supply voltage Vreg_gs supplied to the drive signal generating circuit 5 and the drive circuit 6 to the first conversion voltage V1.
　第２期間Ｐ２は、少なくともターンオフによってゲート駆動信号Ｖｇｓが０Ｖに到達するまでは、ゲート駆動信号Ｖｇｓが第３変換電圧Ｖ３に維持されるように設定される。 The second period P2 is set so that the gate drive signal Vgs is maintained at the third conversion voltage V3 at least until the gate drive signal Vgs reaches 0V due to turning off.
　以上のように、ゲートドライブ回路１は、パワー半導体素子Ｑ１０のターンオン（立下り）、ターンオフ（立下り）のタイミング毎に電源電圧Ｖｒｅｇ＿ｇｓの切換を行うことで、適正なプロファイルのゲート駆動信号Ｖｇｓでパワー半導体素子Ｑ１０を駆動でき、ターンオン時、ターンオフ時に発生する課題を解決できる。すなわち、ターンオン時のスイッチング損失低減だけでなく、ターンオフ時のノイズ低減、パワー半導体素子のオン時の損失低減、パワー半導体素子Ｑ１０の寿命の確保を実現することができる。 As described above, the gate drive circuit 1 switches the power supply voltage Vreg_gs at each timing of turning on (falling) and turning off (falling) of the power semiconductor element Q10, thereby being able to drive the power semiconductor element Q10 with a gate drive signal Vgs of an appropriate profile, and solving problems that arise when turning on and off. In other words, it is possible to reduce not only switching loss when turning on, but also noise when turning off, reduce loss when the power semiconductor element is on, and ensure the lifespan of the power semiconductor element Q10.
（第２の実施の形態）
　第２の実施の形態のゲートドライブ回路１ａは、図４を参照すると、上述のゲートドライブ回路１の構成に加え、電源電圧Ｖｒｅｇ＿ｇｓを出力する電源出力端子Ｔ５を備える。 Second Embodiment
Referring to FIG. 4, a gate drive circuit 1a according to the second embodiment includes the configuration of the gate drive circuit 1 described above, and further includes a power supply output terminal T5 that outputs a power supply voltage Vreg_gs.
　パワー半導体モジュール１０ａは、ドライブ回路１１を内蔵し、ゲート駆動信号入力端子Ｔ１３、正側主端子Ｔ１１、負側主端子Ｔ１２の他、ドライブ回路１１用の電源入力端子Ｔ１４を有している。ドライブ回路１１が内蔵されているパワー半導体モジュール１０ａのような仕様の製品は、ターンオン、ターンオフの特性が決まり、一般的に、使用環境、条件による外部からの調整が困難であるが、ゲートドライブ回路１ａは、電源出力端子Ｔ５から電源電圧Ｖｒｅｇ＿ｇｓを電源入力端子Ｔ１４に供給できる。従って、ゲートドライブ回路１ａは、このような仕様の製品に対しても、パワー半導体素子Ｑ１０を適正なプロファイルのゲート駆動信号Ｖｇｓで駆動できる。 The power semiconductor module 10a incorporates a drive circuit 11 and has a gate drive signal input terminal T13, a positive main terminal T11, a negative main terminal T12, and a power supply input terminal T14 for the drive circuit 11. Products with specifications such as the power semiconductor module 10a, which incorporates the drive circuit 11, have fixed turn-on and turn-off characteristics and are generally difficult to adjust from the outside depending on the usage environment and conditions. However, the gate drive circuit 1a can supply the power supply voltage Vreg_gs from the power supply output terminal T5 to the power supply input terminal T14. Therefore, the gate drive circuit 1a can drive the power semiconductor element Q10 with a gate drive signal Vgs of an appropriate profile even for products with such specifications.
（第３の実施の形態）
　第３の実施の形態のゲートドライブ回路１ｂは、図５を参照すると、上述のゲートドライブ回路１の構成に加え、高電位切換端子Ｔ６と、低電位切換端子Ｔ７と、切換選択端子Ｔ８と、を備える。 Third Embodiment
Referring to FIG. 5, a gate drive circuit 1b according to the third embodiment includes, in addition to the configuration of the gate drive circuit 1 described above, a high potential switching terminal T6, a low potential switching terminal T7, and a switching selection terminal T8.
　高電位切換端子Ｔ６は、第２レギュレータ回路２２ａに変換電圧の切り換えを指示するための端子である。第２レギュレータ回路２２ａは、例えば、高電位切換端子Ｔ６が無接続もしくはＬレベルである場合、入力電圧ＶＩＮを第２変換電圧Ｖ２に、高電位切換端子Ｔ６がＨレベルである場合、入力電圧ＶＩＮを第２変換電圧Ｖ２よりも高い第４変換電圧Ｖ４にそれぞれ変換可能に構成する。第２レギュレータ回路２２ａは、３種類以上の高電位（第１変換電圧Ｖ１よりも）に変換可能に構成してもよい。これにより、ゲートドライブ回路１ｂは、ターンオン時の電源電圧Ｖｒｅｇ＿ｇｓを複数の高電位の中から選択でき、ターンオン時におけるゲート駆動信号Ｖｇｓのプロファイルをより最適化にできる。 The high potential switching terminal T6 is a terminal for instructing the second regulator circuit 22a to switch the conversion voltage. For example, when the high potential switching terminal T6 is unconnected or at L level, the second regulator circuit 22a is configured to be able to convert the input voltage VIN to the second conversion voltage V2, and when the high potential switching terminal T6 is at H level, the input voltage VIN to a fourth conversion voltage V4 higher than the second conversion voltage V2. The second regulator circuit 22a may be configured to be able to convert to three or more types of high potentials (higher than the first conversion voltage V1). This allows the gate drive circuit 1b to select the power supply voltage Vreg_gs at turn-on from multiple high potentials, and the profile of the gate drive signal Vgs at turn-on can be further optimized.
　低電位切換端子Ｔ７は、第３レギュレータ回路２３ａに変換電圧の切り換えを指示するための端子である。第３レギュレータ回路２３ａは、例えば、低電位切換端子Ｔ７が無接続もしくはＬレベルである場合、入力電圧ＶＩＮを第３変換電圧Ｖ３に、低電位切換端子Ｔ７がＨレベルである場合、入力電圧ＶＩＮを第３変換電圧Ｖ３よりも高い第５変換電圧Ｖ５にそれぞれ変換可能に構成する。第３レギュレータ回路２３ａは、３種類以上の低電位（第１変換電圧Ｖ１よりも）に変換可能に構成してもよい。これにより、ゲートドライブ回路１ｂは、ターンオフ時の電源電圧Ｖｒｅｇ＿ｇｓを複数の低電位の中から選択でき、ターンオフ時におけるゲート駆動信号Ｖｇｓのプロファイルをより最適化にできる。 The low potential switching terminal T7 is a terminal for instructing the third regulator circuit 23a to switch the conversion voltage. For example, when the low potential switching terminal T7 is unconnected or at L level, the third regulator circuit 23a is configured to be able to convert the input voltage VIN to a third conversion voltage V3, and when the low potential switching terminal T7 is at H level, the input voltage VIN to a fifth conversion voltage V5 higher than the third conversion voltage V3. The third regulator circuit 23a may be configured to be able to convert to three or more types of low potential (lower than the first conversion voltage V1). This allows the gate drive circuit 1b to select the power supply voltage Vreg_gs at the time of turn-off from among multiple low potentials, and the profile of the gate drive signal Vgs at the time of turn-off can be further optimized.
　切換選択端子Ｔ８は、電源切換回路３ａの切換動作を選択するための端子である。電源切換回路３ａは、例えば、切換選択端子Ｔ８が無接続もしくはＬレベルである場合、第１の実施の形態の切換動作を実行し、低電位切換端子Ｔ７がＨレベルである場合、ターンオン時（もしくはターンオフ時）にのみ切換動作を実行する。 The switching selection terminal T8 is a terminal for selecting the switching operation of the power supply switching circuit 3a. For example, when the switching selection terminal T8 is not connected or is at L level, the power supply switching circuit 3a executes the switching operation of the first embodiment, and when the low potential switching terminal T7 is at H level, the switching operation is executed only at turn-on (or turn-off).
　以上説明したように、本実施の形態は、入力信号に基づいて駆動信号（ゲート駆動信号Ｖｇｓ）を生成する駆動信号生成回路（ドライブ信号生成回路５、ドライブ回路６）を備え、生成したゲート駆動信号Ｖｇｓによってパワー半導体素子Ｑ１０を駆動するゲートドライブ回路１であって、供給される入力電圧ＶＩＮを異なる高電位変換電圧（第２変換電圧Ｖ２）、中電位変換電圧（第１変換電圧Ｖ１）、低電位変換電圧（第３変換電圧Ｖ３）にそれぞれ変換するレギュレータ回路（第２レギュレータ回路２２、第１レギュレータ回路２１、第３レギュレータ回路２３）と、入力信号のパワー半導体素子Ｑ１０のターンオンを指示する遷移を検出した場合、ドライブ信号生成回路５及びドライブ回路６の電源電圧Ｖｒｅｇ＿ｇｓとして第２変換電圧Ｖ２を供給した後、予め設定された第１期間Ｐ１が経過した後に第１変換電圧Ｖ１を供給し、入力信号のパワー半導体素子Ｑ１０のターンオフを指示する遷移を検出した場合、ドライブ信号生成回路５及びドライブ回路６の電源電圧Ｖｒｅｇ＿ｇｓとして第３変換電圧Ｖ３を供給する電源切換回路３と、を具備し、ドライブ信号生成回路５及びドライブ回路６は、ターンオン時に第２変換電圧Ｖ２を振幅としてゲート駆動信号Ｖｇｓを立上げ、ターンオフ時に第２変換電圧Ｖ２を振幅としてゲート駆動信号Ｖｇｓを立下げる。
　この構成により、ゲートドライブ回路１は、ターンオン時、ターンオフ時のいずれにおいても適正なプロファイルのゲート駆動信号Ｖｇｓをパワー半導体素子Ｑ１０に印加でき、ターンオン時間を短縮してターンオン時のスイッチング損失の低減が図れると共に、ターンオフ時のノイズの低減が図れる。 As described above, this embodiment is a gate drive circuit 1 that includes a drive signal generation circuit (drive signal generation circuit 5, drive circuit 6) that generates a drive signal (gate drive signal Vgs) based on an input signal, and drives a power semiconductor element Q10 by the generated gate drive signal Vgs, and includes regulator circuits (second regulator circuit 22, first regulator circuit 21, third regulator circuit 23) that convert a supplied input voltage VIN into different high-potential converted voltages (second converted voltage V2), medium-potential converted voltages (first converted voltage V1), and low-potential converted voltages (third converted voltage V3), and a transition circuit (transition circuit 24) that instructs turning on the power semiconductor element Q10 of the input signal. a power supply switching circuit 3 that, when a transition of the input signal instructing to turn off the power semiconductor element Q10 is detected, supplies a second converted voltage V2 as the power supply voltage Vreg_gs of the drive signal generation circuit 5 and the drive circuit 6, and then supplies the first converted voltage V1 after a preset first period P1 has elapsed, and, when a transition of the input signal instructing to turn off the power semiconductor element Q10 is detected, supplies a third converted voltage V3 as the power supply voltage Vreg_gs of the drive signal generation circuit 5 and the drive circuit 6, and the drive signal generation circuit 5 and the drive circuit 6 raise the gate drive signal Vgs with the second converted voltage V2 as an amplitude at the time of turn-on, and lowers the gate drive signal Vgs with the second converted voltage V2 as an amplitude at the time of turn-off.
With this configuration, the gate drive circuit 1 can apply a gate drive signal Vgs with an appropriate profile to the power semiconductor element Q10 both at turn-on and turn-off, thereby shortening the turn-on time and reducing switching loss at turn-on as well as reducing noise at turn-off.
　さらに、本実施形態は、第１期間Ｐ１は、少なくともパワー半導体素子Ｑ１０の寄生容量成分への充電が完了するまでは、ゲート駆動信号Ｖｇｓの振幅が第２変換電圧Ｖ２に維持されるように設定される。
　この構成により、ゲートドライブ回路１は、パワー半導体素子Ｑ１０の寄生容量成分への充電時間を短縮でき、ターンオン時間の短縮できる。 Furthermore, in this embodiment, the first period P1 is set so that the amplitude of the gate drive signal Vgs is maintained at the second converted voltage V2 at least until charging of the parasitic capacitance component of the power semiconductor element Q10 is completed.
With this configuration, the gate drive circuit 1 can reduce the charging time for the parasitic capacitance component of the power semiconductor element Q10, and reduce the turn-on time.
　さらに、本実施形態は、第１スイッチ素子Ｑ１と第２スイッチ素子Ｑ２とからなる直列回路が電源電圧Ｖｒｅｇ＿ｇｓとグランド電位との間に接続されたドライブ回路６と、第１スイッチ素子Ｑ１と第２スイッチ素子Ｑ２を駆動するドライブ信号を生成するドライブ信号生成回路５と、備え、ドライブ信号生成回路５は、電源電圧Ｖｒｅｇ＿ｇｓとグランド電位との間に接続された複数段のＣＭＯＳインバーター回路で構成された遅延ブロック５２を有する。
　この構成により、ターンオン時の応答性を向上させることができる。 Furthermore, this embodiment includes a drive circuit 6 in which a series circuit made up of a first switch element Q1 and a second switch element Q2 is connected between a power supply voltage Vreg_gs and a ground potential, and a drive signal generation circuit 5 that generates a drive signal for driving the first switch element Q1 and the second switch element Q2. The drive signal generation circuit 5 has a delay block 52 made up of multiple stages of CMOS inverter circuits connected between the power supply voltage Vreg_gs and the ground potential.
This configuration can improve the response at turn-on.
　さらに、本実施形態は、電源電圧Ｖｒｅｇ＿ｇｓを出力する電源出力端子Ｔ５を備える。
　この構成により、ゲートドライブ回路１ａは、ドライブ回路１１を内蔵するパワー半導体モジュール１０ａであっても、パワー半導体素子Ｑ１０を適正なプロファイルのゲート駆動信号Ｖｇｓで駆動できる。 Furthermore, this embodiment includes a power supply output terminal T5 that outputs a power supply voltage Vreg_gs.
With this configuration, the gate drive circuit 1a can drive the power semiconductor element Q10 with a gate drive signal Vgs having an appropriate profile, even if the gate drive circuit 1a is a power semiconductor module 10a that includes a drive circuit 11 built therein.
　さらに、本実施形態は、第２レギュレータ回路２２ａが変換する高電位変換電圧の切り換えを指示する高電位切換端子Ｔ６を備え、第２レギュレータ回路２２ａは、高電位切換端子Ｔ６の状態に応じて高電位変換電圧を複数の異なる電位（第２変換電圧Ｖ２、第４変換電圧Ｖ４）に変換可能である。
　この構成により、ゲートドライブ回路１ｂは、ターンオン時の電源電圧Ｖｒｅｇ＿ｇｓを複数の高電位の中から選択でき、ターンオン時におけるゲート駆動信号Ｖｇｓのプロファイルをより最適化にできる。 Furthermore, this embodiment is provided with a high potential switching terminal T6 that instructs switching of the high potential conversion voltage converted by the second regulator circuit 22a, and the second regulator circuit 22a is capable of converting the high potential conversion voltage into a plurality of different potentials (second conversion voltage V2, fourth conversion voltage V4) depending on the state of the high potential switching terminal T6.
With this configuration, the gate drive circuit 1b can select the power supply voltage Vreg_gs at turn-on from among a plurality of high potentials, and the profile of the gate drive signal Vgs at turn-on can be further optimized.
　さらに、本実施形態は、第３レギュレータ回路２３ａが変換する低電位変換電圧の切り換えを指示する低電位切換端子Ｔ７を備え、第３レギュレータ回路２３ａは、低電位切換端子Ｔ７の状態に応じて低電位変換電圧を複数の異なる電位（第３変換電圧Ｖ３、第５変換電圧Ｖ５）に変換可能である。
　この構成により、ゲートドライブ回路１ｂは、ターンオフ時の電源電圧Ｖｒｅｇ＿ｇｓを複数の低電位の中から選択でき、ターンオフ時におけるゲート駆動信号Ｖｇｓのプロファイルをより最適化にできる。 Furthermore, this embodiment is provided with a low-potential switching terminal T7 that instructs switching of the low-potential converted voltage converted by the third regulator circuit 23a, and the third regulator circuit 23a is capable of converting the low-potential converted voltage into a plurality of different potentials (the third converted voltage V3, the fifth converted voltage V5) depending on the state of the low-potential switching terminal T7.
With this configuration, the gate drive circuit 1b can select the power supply voltage Vreg_gs at turn-off from among a plurality of low potentials, and the profile of the gate drive signal Vgs at turn-off can be further optimized.
　なお、本発明が上記各実施の形態に限定されず、本発明の技術思想の範囲内において、各実施の形態は適宜変更され得ることは明らかである。また、上記構成部材の数、位置、形状等は上記実施の形態に限定されず、本発明を実施する上で好適な数、位置、形状等にすることができる。なお、同一構成要素には、各図において、同一符号を付している。 It is clear that the present invention is not limited to the above-described embodiments, and that each embodiment can be modified as appropriate within the scope of the technical concept of the present invention. Furthermore, the number, position, shape, etc. of the above-described components are not limited to the above-described embodiments, and the number, position, shape, etc. can be any suitable number for implementing the present invention. The same components are denoted by the same reference numerals in each drawing.
１、１ａ、１ｂ　ゲートドライブ回路
３、３ａ　電源切換回路
４　切換信号生成回路
５　ドライブ信号生成回路
６　ドライブ回路
１０、１０ａ　パワー半導体モジュール
１１　ドライブ回路
２１　第１レギュレータ回路
２２、２２ａ　第２レギュレータ回路
２３、２３ａ　第３レギュレータ回路
５１　信号生成ブロック
５２　遅延ブロック Reference Signs List 1, 1a, 1b Gate drive circuits 3, 3a Power supply switching circuit 4 Switching signal generating circuit 5 Drive signal generating circuit 6 Drive circuits 10, 10a Power semiconductor module 11 Drive circuit 21 First regulator circuit 22, 22a Second regulator circuit 23, 23a Third regulator circuit 51 Signal generating block 52 Delay block

Claims (7)

  1. 　入力信号に基づいて駆動信号を生成する駆動信号生成回路を備え、生成した前記駆動信号によってパワー半導体素子を駆動するゲートドライブ回路であって、
    　供給される入力電圧を異なる高電位変換電圧、中電位変換電圧、低電位変換電圧にそれぞれ変換するレギュレータ回路と、
    　前記入力信号のターンオンを指示する遷移を検出した場合、前記駆動信号生成回路の電源電圧として前記高電位変換電圧を供給した後、予め設定された第１期間が経過した後に前記中電位変換電圧を供給し、前記入力信号のターンオフを指示する遷移を検出した場合、前記駆動信号生成回路の前記電源電圧として前記低電位変換電圧を供給する電源切換回路と、を具備し、
    　前記駆動信号生成回路は、ターンオン時に前記高電位変換電圧を振幅として前記駆動信号を立上げ、ターンオフ時に前記低電位変換電圧を振幅として前記駆動信号を立下げることを特徴とするゲートドライブ回路。     A gate drive circuit comprising a drive signal generation circuit that generates a drive signal based on an input signal, and drives a power semiconductor element by the generated drive signal,
    a regulator circuit for converting a supplied input voltage into a high-potential conversion voltage, a medium-potential conversion voltage, and a low-potential conversion voltage;
    a power supply switching circuit that, when detecting a transition instructing a turn-on of the input signal, supplies the high-potential converted voltage as a power supply voltage of the drive signal generating circuit, and then supplies the intermediate-potential converted voltage after a preset first period has elapsed, and, when detecting a transition instructing a turn-off of the input signal, supplies the low-potential converted voltage as the power supply voltage of the drive signal generating circuit;
    the drive signal generating circuit causes the drive signal to rise with the high potential converted voltage as an amplitude when turned on, and causes the drive signal to fall with the low potential converted voltage as an amplitude when turned off.
  2. 　前記第１期間は、少なくとも前記パワー半導体素子の寄生容量成分への充電が完了するまでは、前記駆動信号の振幅が前記高電位変換電圧に維持されるように設定されることを特徴とする請求項１に記載のゲートドライブ回路。 The gate drive circuit according to claim 1, characterized in that the first period is set so that the amplitude of the drive signal is maintained at the high potential conversion voltage at least until charging of the parasitic capacitance component of the power semiconductor element is completed.
  3. 　前記駆動信号生成回路は、
    　第１スイッチ素子と第２スイッチ素子とからなる直列回路が前記電源電圧とグランド電位との間に接続されたドライブ回路と、
    　前記第１スイッチ素子と前記第２スイッチ素子を駆動するドライブ信号を生成するドライブ信号生成回路と、備え、
    　前記ドライブ信号生成回路は、前記電源電圧と前記グランド電位との間に接続された複数段のＣＭＯＳインバーター回路で構成された遅延ブロックを有することを特徴とする請求項１又は２に記載のゲートドライブ回路。     The drive signal generating circuit includes:
    a drive circuit in which a series circuit including a first switch element and a second switch element is connected between the power supply voltage and a ground potential;
    a drive signal generating circuit that generates a drive signal for driving the first switch element and the second switch element;
    3. The gate drive circuit according to claim 1, wherein the drive signal generating circuit has a delay block configured with a multi-stage CMOS inverter circuit connected between the power supply voltage and the ground potential.
  4. 　前記電源電圧を出力する電源出力端子を備えることを特徴とする請求項１又は２に記載のゲートドライブ回路。 The gate drive circuit according to claim 1 or 2, characterized in that it is provided with a power supply output terminal that outputs the power supply voltage.
  5. 　前記レギュレータ回路が変換する前記高電位変換電圧の切り換えを指示する高電位切換端子を備え、
    　前記レギュレータ回路は、前記高電位切換端子の状態に応じて前記高電位変換電圧を複数の異なる電位に変換可能であることを特徴とする請求項１又は２に記載のゲートドライブ回路。     a high-potential switching terminal for instructing switching of the high-potential converted voltage converted by the regulator circuit;
    3. The gate drive circuit according to claim 1, wherein the regulator circuit is capable of converting the high-potential converted voltage into a plurality of different potentials according to a state of the high-potential switching terminal.
  6. 　前記レギュレータ回路が変換する前記低電位変換電圧の切り換えを指示する低電位切換端子を備え、
    　前記レギュレータ回路は、前記低電位切換端子の状態に応じて前記低電位変換電圧を複数の異なる電位に変換可能であることを特徴とする請求項１又は２に記載のゲートドライブ回路。     a low-potential switching terminal for instructing switching of the low-potential converted voltage converted by the regulator circuit;
    3. The gate drive circuit according to claim 1, wherein the regulator circuit is capable of converting the low-potential converted voltage into a plurality of different potentials according to a state of the low-potential switching terminal.
  7. 　請求項１又は２に記載ゲートドライブ回路が基板上に集積化されていることを特徴とする半導体装置。 A semiconductor device in which the gate drive circuit according to claim 1 or 2 is integrated on a substrate.
PCT/JP2023/001454 2023-01-19 2023-01-19 Gate drive circuit and semiconductor device WO2024154283A1 (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352748A (en) * 2000-06-05 2001-12-21 Denso Corp Gate drive circuit for semiconductor switching element
JP2006320087A (en) * 2005-05-11 2006-11-24 Toyota Motor Corp Driving device for voltage-driven semiconductor device
JP2019186992A (en) * 2018-04-03 2019-10-24 トヨタ自動車株式会社 Power conversion device
JP2020061595A (en) * 2018-10-04 2020-04-16 富士電機株式会社 Switching control circuit and power supply circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001352748A (en) * 2000-06-05 2001-12-21 Denso Corp Gate drive circuit for semiconductor switching element
JP2006320087A (en) * 2005-05-11 2006-11-24 Toyota Motor Corp Driving device for voltage-driven semiconductor device
JP2019186992A (en) * 2018-04-03 2019-10-24 トヨタ自動車株式会社 Power conversion device
JP2020061595A (en) * 2018-10-04 2020-04-16 富士電機株式会社 Switching control circuit and power supply circuit

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