WO2024154036A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024154036A1
WO2024154036A1 PCT/IB2024/050371 IB2024050371W WO2024154036A1 WO 2024154036 A1 WO2024154036 A1 WO 2024154036A1 IB 2024050371 W IB2024050371 W IB 2024050371W WO 2024154036 A1 WO2024154036 A1 WO 2024154036A1
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Prior art keywords
insulator
oxide semiconductor
conductor
oxide
transistor
Prior art date
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Ceased
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PCT/IB2024/050371
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
鎌田悦子
鎌田のぞみ
佐藤優一
大野敏和
手塚祐朗
高橋正弘
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to JP2024571283A priority Critical patent/JPWO2024154036A1/ja
Priority to CN202480008010.1A priority patent/CN120570082A/zh
Priority to KR1020257026213A priority patent/KR20250137608A/ko
Publication of WO2024154036A1 publication Critical patent/WO2024154036A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/70—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the floating gate being an electrode shared by two or more components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0158—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/834—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
    • H10K71/70—Testing, e.g. accelerated lifetime tests

Definitions

  • One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing the semiconductor device.
  • one embodiment of the present invention is not limited to the above technical field.
  • Examples of the technical field of one embodiment of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input/output devices (e.g., touch panels), driving methods thereof, or manufacturing methods thereof.
  • a semiconductor device refers to any device that can function by utilizing semiconductor characteristics.
  • Semiconductor elements such as transistors, as well as semiconductor circuits, arithmetic devices, and memory devices, are one embodiment of semiconductor devices.
  • Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, electronic devices, and the like may be said to have semiconductor devices.
  • a CPU is a collection of semiconductor elements that have semiconductor integrated circuits (at least transistors and capacitors) that are processed from semiconductor wafers and made into chips, and on which electrodes that serve as connection terminals are formed.
  • IC chips Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.
  • transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices).
  • ICs integrated circuits
  • image display devices also simply referred to as display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors, but oxide semiconductors are also attracting attention as other materials.
  • Patent Document 1 discloses a low-power consumption CPU that utilizes the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 2 discloses a memory device that can retain stored contents for a long period of time by utilizing the property of low leakage current of transistors using oxide semiconductors.
  • Patent Document 3 and Non-Patent Document 1 disclose a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple overlapping memory cells.
  • Patent Document 4 discloses a technique for increasing the density of integrated circuits by vertically arranging the channel of a transistor using an oxide semiconductor film.
  • An object of one embodiment of the present invention is to provide a semiconductor device with high reliability.
  • An object of one embodiment of the present invention is to provide a semiconductor device having good electrical characteristics.
  • An object of one embodiment of the present invention is to provide a semiconductor device with little variation in electrical characteristics of transistors.
  • An object of one embodiment of the present invention is to provide a semiconductor device with a large on-state current.
  • An object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated.
  • An object of one embodiment of the present invention is to provide a semiconductor device with a high operating speed.
  • An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.
  • An object of one embodiment of the present invention is to provide a new semiconductor device.
  • An object of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity.
  • An object of one embodiment of the present invention is to provide a method for manufacturing a new semiconductor device.
  • An object of one embodiment of the present invention is to provide a memory device that can be miniaturized or highly integrated.
  • An object of one embodiment of the present invention is to provide a memory device with a large storage capacity.
  • An object of one embodiment of the present invention is to provide a memory device with a high operating speed.
  • An object of one embodiment of the present invention is to provide a memory device with low power consumption.
  • An object of one embodiment of the present invention is to provide a novel memory device.
  • One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a conductor, a first insulator provided between the oxide semiconductor and the conductor, and a second insulator facing the first insulator with the oxide semiconductor interposed therebetween.
  • the first insulator has a function of capturing or fixing hydrogen.
  • the second insulator is in contact with at least a part of the oxide semiconductor and has a barrier property against hydrogen.
  • the hydrogen concentration of the oxide semiconductor is less than 1 ⁇ 10 19 atoms/cm 3 in at least a part of a region facing the conductor with the first insulator interposed therebetween.
  • the hydrogen concentration of the first insulator is 1 ⁇ 10 19 atoms/cm 3 or higher in at least a part of a region between the oxide semiconductor and the conductor. Note that the hydrogen concentrations of the oxide semiconductor and the first insulator are values measured by secondary ion mass spectrometry.
  • One embodiment of the present invention is a semiconductor device including an oxide semiconductor, a conductor, a first insulator provided between the oxide semiconductor and the conductor, a second insulator facing the first insulator with the oxide semiconductor interposed therebetween, a third insulator provided between the conductor and the first insulator, and a fourth insulator provided between the oxide semiconductor and the second insulator.
  • the first insulator and the fourth insulator have a function of capturing or fixing hydrogen.
  • the second insulator and the third insulator have a barrier property against hydrogen.
  • the hydrogen concentration of the oxide semiconductor is less than 1 ⁇ 10 19 atoms/cm 3 in at least a part of a region facing the conductor with the first insulator interposed therebetween.
  • the hydrogen concentration of the first insulator is 1 ⁇ 10 19 atoms/cm 3 or higher in at least a part of a region between the oxide semiconductor and the conductor. Note that the hydrogen concentrations of the oxide semiconductor and the first insulator are values measured by secondary ion mass spectrometry.
  • the first insulator contains hafnium and oxygen
  • the second insulator contains silicon and nitrogen.
  • the second insulator has an opening, the oxide semiconductor is provided inside the opening of the second insulator, and a channel is formed along the side of the opening of the second insulator.
  • the semiconductor device preferably further includes a fifth insulator having an opening, an oxide semiconductor is provided on the second insulator, the fifth insulator is provided on the oxide semiconductor, and the first insulator and the conductor are provided inside the opening of the fifth insulator.
  • Another embodiment of the present invention is a semiconductor device including an oxide semiconductor, a conductor, a first insulator provided between the oxide semiconductor and the conductor, a second insulator facing the first insulator with the oxide semiconductor interposed therebetween, and a third insulator provided between the conductor and the first insulator.
  • the first insulator has a function of capturing or fixing hydrogen.
  • the second insulator is in contact with at least a part of the oxide semiconductor.
  • the third insulator has a barrier property against hydrogen.
  • the hydrogen concentration of the oxide semiconductor is less than 1 ⁇ 10 19 atoms/cm 3 in at least a part of a region facing the conductor with the first insulator interposed therebetween.
  • the amount of oxygen molecules released from the second insulator is 1.0 ⁇ 10 14 molecules/cm 2 or more and less than 1.0 ⁇ 10 15 molecules/cm 2.
  • the hydrogen concentration of the oxide semiconductor is a value measured by secondary ion mass spectrometry.
  • the amount of released oxygen molecules is a value measured by thermal desorption spectrometry.
  • the hydrogen concentration of the first insulator be 1 ⁇ 10 atoms/cm or more in at least a part of a region between the oxide semiconductor and the conductor, and that the hydrogen concentration of the first insulator be a value measured by secondary ion mass spectrometry.
  • the first insulator contains hafnium and oxygen
  • the second insulator contains silicon and oxygen
  • the third insulator contains silicon and nitrogen.
  • the second insulator has an opening, the oxide semiconductor is provided inside the opening of the second insulator, and a channel is formed along the side of the opening of the second insulator.
  • the semiconductor device preferably further includes a fourth insulator having an opening, an oxide semiconductor is provided on the second insulator, a fourth insulator is provided on the oxide semiconductor, and a first insulator, a third insulator, and a conductor are provided inside the opening of the fourth insulator.
  • the second insulator has a region with a film thickness of 2 nm or more and 30 nm or less.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device having good electrical characteristics can be provided.
  • a semiconductor device with less variation in electrical characteristics of transistors can be provided.
  • a semiconductor device with large on-state current can be provided.
  • a semiconductor device that can be miniaturized or highly integrated can be provided.
  • a semiconductor device with high operating speed can be provided.
  • a semiconductor device with low power consumption can be provided.
  • a novel semiconductor device can be provided.
  • a method for manufacturing a semiconductor device with high productivity can be provided.
  • a method for manufacturing a novel semiconductor device can be provided.
  • a memory device that can be miniaturized or highly integrated can be provided.
  • a memory device with a large storage capacity can be provided.
  • a memory device with a high operating speed can be provided.
  • a memory device with low power consumption can be provided.
  • a novel memory device can be provided.
  • FIG. 1A, 1C, and 1E are perspective views showing an example of a structure
  • FIG. 1B, 1D, and 1F are cross-sectional views showing an example of a structure
  • FIG. 2 is a diagram illustrating the relationship between hydrogen and oxygen and the initial characteristics and reliability of a transistor.
  • 3A and 3D are perspective views illustrating the shape of an oxide semiconductor
  • FIGS. 3B, 3C, 3E, and 3F are cross-sectional views illustrating the shape of an oxide semiconductor.
  • 4A, 4C, and 4E are perspective views showing an example of a structure
  • FIGs. 4B, 4D, and 4F are cross-sectional views showing an example of a structure.
  • 5A and 5C are perspective views showing an example of a structure
  • 5B and 5D are cross-sectional views showing an example of the structure.
  • 6A, 6C, and 6E are perspective views showing an example of a structure
  • 6B, 6D, and 6F are cross-sectional views showing an example of a structure.
  • 7A and 7C are perspective views showing an example of a structure
  • Fig. 7B and Fig. 7D are cross-sectional views showing an example of the structure.
  • 8A, 8C, and 8E are perspective views showing an example of a structure
  • 8B, 8D, and 8F are cross-sectional views showing an example of a structure.
  • 9A to 9D are cross-sectional views showing an example of a structure.
  • Fig. 10A is a plan view showing an example of a semiconductor device
  • FIG. 10B to 10D are cross-sectional views showing an example of the semiconductor device.
  • 11A and 11B are cross-sectional views showing an example of a semiconductor device.
  • Fig. 12A is a plan view showing an example of a semiconductor device, and Figs. 12B to 12D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 13A is a plan view showing an example of a semiconductor device, and Figs. 13B to 13D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 14A is a plan view showing an example of a semiconductor device, and Fig. 14B and Fig. 14C are cross-sectional views showing an example of the semiconductor device.
  • Fig. 14A is a plan view showing an example of a semiconductor device, and Fig. 14B and Fig. 14C are cross-sectional views showing an example of the semiconductor device.
  • Fig. 14A is a plan view showing an example of a semiconductor device, and Fig. 14B
  • FIG. 15A is a plan view showing an example of a semiconductor device
  • Figs. 15B to 15D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 16A is a plan view showing an example of a semiconductor device
  • Figs. 16B to 16D are cross-sectional views showing an example of the semiconductor device.
  • 17A and 17B are cross-sectional views showing an example of a semiconductor device.
  • Fig. 18A is a plan view showing an example of a semiconductor device
  • Figs. 18B to 18D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 19A is a plan view showing an example of a semiconductor device
  • Figs. 19B to 19D are cross-sectional views showing an example of the semiconductor device.
  • FIG. 20A is a plan view showing an example of a semiconductor device
  • Fig. 20B to Fig. 20D are cross-sectional views showing an example of the semiconductor device
  • Fig. 21A is a plan view showing an example of a semiconductor device
  • Fig. 21B to Fig. 21D are cross-sectional views showing an example of the semiconductor device
  • 22A to 22D are cross-sectional views showing an example of a semiconductor device
  • Fig. 23A is a plan view showing an example of a semiconductor device
  • Fig. 23B to Fig. 23D are cross-sectional views showing an example of the semiconductor device
  • Fig. 24A is a plan view showing an example of a semiconductor device
  • FIG. 24D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 25A is a plan view showing an example of a semiconductor device
  • Fig. 25B to Fig. 25D are cross-sectional views showing an example of the semiconductor device.
  • 26A and 26B are plan and cross-sectional views illustrating an example of a semiconductor device.
  • Fig. 27A is a plan view showing an example of a semiconductor device
  • Fig. 27B to Fig. 27D are cross-sectional views showing an example of the semiconductor device.
  • 28A to 28E are cross-sectional views showing an example of a semiconductor device.
  • Fig. 29A is a plan view showing an example of a semiconductor device
  • FIG. 29D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 30A is a plan view showing an example of a semiconductor device
  • Fig. 30B to Fig. 30D are cross-sectional views showing an example of the semiconductor device.
  • Fig. 31A is a plan view showing an example of a semiconductor device
  • Fig. 31B to Fig. 31D are cross-sectional views showing an example of the semiconductor device.
  • FIG. 32 is a cross-sectional view showing an example of a semiconductor device.
  • 33A to 33E are cross-sectional views showing an example of a semiconductor device.
  • Fig. 34A is a plan view showing an example of a semiconductor device
  • Fig. 34B to Fig. 34D are cross-sectional views showing an example of the semiconductor device.
  • FIG. 35 is a block diagram illustrating an example of a storage device.
  • 36A and 36B are a schematic diagram and a circuit diagram showing an example of a memory device.
  • 37A and 37B are schematic diagrams showing an example of a storage device.
  • 38A to 38C are circuit diagrams showing an example of a memory device.
  • FIG. 39 is a circuit diagram showing an example of a memory device.
  • FIG. 40 is a cross-sectional view showing an example of a storage device.
  • FIG. 41 is a cross-sectional view showing an example of a storage device.
  • FIG. 42 is a cross-sectional view showing an example of a storage device.
  • 43A and 43B are diagrams showing an example of a semiconductor device.
  • 44A and 44B are diagrams showing an example of an electronic component.
  • FIGS. 45A and 45B are diagrams showing an example of electronic equipment
  • FIGS. 45C to 45E are diagrams showing an example of a mainframe computer.
  • FIG. 46 is a diagram showing an example of space equipment.
  • FIG. 47 is a diagram illustrating an example of a storage system applicable to a data center.
  • 48A and 48B show configuration examples of a display device.
  • FIG. 49 shows an example of the configuration of a display device.
  • FIG. 50 shows an example of the configuration of a display device.
  • FIG. 51 shows an example of the configuration of a display device.
  • 52A to 52C show examples of the configuration of a display device.
  • 53A and 53B show configuration examples of a display device.
  • 54A to 54D show configuration examples of electronic devices.
  • 55A to 55F show configuration examples of electronic devices.
  • FIG. 57 is a schematic diagram of a sample according to an embodiment.
  • 58A to 58C are diagrams showing the results of TDS analysis of a sample according to an embodiment.
  • 59A to 59C are diagrams showing Vsh calculated from the Id-Vg characteristics.
  • 60A to 60F are diagrams showing the stress time dependence of ⁇ Vsh.
  • 61A to 61C are diagrams showing ⁇ Vsh.
  • 62A and 62B show the results of SIMS analysis of the sample prepared in the example.
  • 63A and 63B show the results of SIMS analysis of the sample prepared in the example.
  • FIG. 64 is a diagram showing a calculation model.
  • 65A to 65F are diagrams showing a calculation model.
  • 66A to 66F are diagrams showing a calculation model.
  • 67A and 67B are perspective and cross-sectional views showing an example of a structure.
  • ordinal numbers “first” and “second” are used for convenience and do not limit the number of components or the order of the components (e.g., the order of processes or the order of stacking).
  • an ordinal number attached to a component in one place in this specification may not match an ordinal number attached to the same component in another place in this specification or in the claims.
  • film and “layer” can be interchanged depending on the circumstances.
  • conductive layer can be interchanged with the term “conductive film”.
  • insulating film can be interchanged with the term “insulating layer”.
  • conductor can be interchanged with the term “conductive layer” or the term “conductive film” depending on the circumstances.
  • insulator can be interchanged with the term “insulating layer” or the term “insulating film” depending on the circumstances.
  • oxide semiconductor can be interchanged with the term “oxide semiconductor layer” or the term “oxide semiconductor film” depending on the circumstances.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less. Therefore, it also includes cases in which the angle is -5 degrees or more and 5 degrees or less.
  • approximately parallel refers to a state in which two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less.
  • Perfect refers to a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, it also includes cases in which the angle is 85 degrees or more and 95 degrees or less.
  • approximately perpendicular refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.
  • Openings include, for example, grooves, slits, and recesses. Also, the area in which an opening is formed may be referred to as an opening.
  • the sidewalls of the insulator at the opening in the insulator are shown to be perpendicular or approximately perpendicular to the substrate surface or the surface on which the insulator is formed, but they may also be tapered.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined relative to the substrate surface or the surface to be formed. For example, there is a region in which the angle between the inclined side and the substrate surface or the surface to be formed (hereinafter, sometimes referred to as the taper angle) is less than 90°.
  • the side and substrate surface of the structure do not necessarily need to be completely flat, and may be approximately planar with a slight curvature, or approximately planar with fine irregularities.
  • a reverse tapered shape refers to a shape having a side or top that protrudes in a direction parallel to the substrate more than the bottom.
  • the term “same height” refers to a configuration in which the heights from a reference surface (for example, a flat surface such as a substrate surface) are equal in cross-sectional view.
  • a planarization process typically a chemical mechanical polishing (CMP) process
  • CMP chemical mechanical polishing
  • the surfaces treated in the CMP process have a configuration in which the heights from the reference surface are equal.
  • the heights of multiple layers may differ depending on the processing device, processing method, or material of the processed surface during the CMP process. In this specification, this case is also treated as "same height".
  • first layer and a second layer when there are two layers (here, a first layer and a second layer) with different heights relative to the reference surface, and the difference in height between the top surface of the first layer and the top surface of the second layer is 20 nm or less, this is also referred to as "same height”.
  • side edges coincide means that at least a portion of the contours of the stacked layers overlap when viewed in a plane. For example, this includes cases where the upper and lower layers are processed using the same mask pattern, or where a portion of the mask pattern is the same. However, strictly speaking, the contours may not overlap, and the contour of the upper layer may be located inside the contour of the lower layer, or the contour of the upper layer may be located outside the contour of the lower layer, in which case it is also referred to as "side edges coincide”.
  • the first film thickness and the second film thickness being the same means that the absolute value of the difference between the first film thickness and the second film thickness divided by the first film thickness is 0.1 or less. Alternatively, it means that the absolute value of the difference between the first film thickness and the second film thickness divided by the second film thickness is 0.1 or less.
  • distance A and distance B are the same means that the absolute value of the difference between distance A and distance B divided by distance A is 0.1 or less. Alternatively, it means that the absolute value of the difference between distance A and distance B divided by distance B is 0.1 or less.
  • Embodiment 1 a structure according to one embodiment of the present invention will be described.
  • the structure according to one embodiment of the present invention can be used for a semiconductor device having a transistor. Note that details of the semiconductor device including the structure according to one embodiment of the present invention will be described in Embodiment 2 and subsequent embodiments.
  • a structure according to one embodiment of the present invention includes an oxide semiconductor, a first insulator, a second insulator, and a conductor.
  • the oxide semiconductor is provided inside an opening of the first insulator.
  • the oxide semiconductor is sandwiched between the first insulators.
  • the first insulator has a barrier property against hydrogen, so that diffusion of hydrogen into the oxide semiconductor can be suppressed.
  • a second insulator having a function of capturing or fixing (also referred to as gettering) hydrogen is further provided between the oxide semiconductor and the first insulator.
  • the oxide semiconductor has a region facing the conductor through one or both of the first insulator and the second insulator.
  • the oxide semiconductor has a region overlapping with the conductor through one or both of the first insulator and the second insulator.
  • the first layer has an area where it overlaps with the second layer, it can also be said that the first layer faces the second layer in that area. Therefore, in this specification, the phrase "the first layer has an area where it overlaps with the second layer” can sometimes be rephrased as "the first layer has an area facing the second layer.”
  • Fig. 1A is a perspective view of a structure according to one embodiment of the present invention.
  • Fig. 1B is a cross-sectional view of the structure, which corresponds to a portion indicated by a dashed line B1-B2 in Fig. 1A.
  • the structure shown in Figures 1A and 1B has an oxide semiconductor 30, an insulator 21, an insulator 51, and a conductor 60.
  • At least a portion of the oxide semiconductor 30 has a cylindrical shape with a hollow portion.
  • the oxide semiconductor 30 has a region that has a cylindrical shape with a hollow portion.
  • An insulator 51 is provided in contact with the side surface of the hollow portion of the oxide semiconductor 30, and a conductor 60 is provided further inside the insulator 51. That is, at least a part of the insulator 51 and at least a part of the conductor 60 are provided inside the hollow portion of the oxide semiconductor 30.
  • the insulator 51 is provided between the oxide semiconductor 30 and the conductor 60. In other words, the conductor 60 has a region that faces the oxide semiconductor 30 via the insulator 51.
  • the insulator 21 is provided in contact with the outer side surface of the oxide semiconductor 30. That is, in FIG. 1A and FIG. 1B, the oxide semiconductor 30, the insulator 51, and the conductor 60 are provided in this order inside the opening of the insulator 21. At this time, the insulator 21 has a region that faces the insulator 51 via the oxide semiconductor 30.
  • the oxide semiconductor 30 can be used, for example, as a semiconductor layer of a transistor.
  • the conductor 60 can function as a gate electrode of the transistor.
  • the insulator 51 can function as a gate insulating film of the transistor.
  • At least a part of the region of the oxide semiconductor 30 facing the conductor 60 can function as a region where a channel is formed (also referred to as a channel formation region). More specifically, at least a part of the region of the oxide semiconductor 30 facing the conductor 60 via the insulator 51 can function as a channel formation region.
  • the gate insulating film may be called a gate insulating layer or a gate insulator.
  • a transistor using an oxide semiconductor for its semiconductor layer may have fluctuating electrical characteristics and poor reliability if oxygen vacancies ( VO ) and impurities are present in a channel formation region in the oxide semiconductor.
  • VO oxygen vacancies
  • impurities a defect in which hydrogen is introduced into the oxygen vacancy (hereinafter sometimes referred to as VOH ) may be formed, and electrons that serve as carriers may be generated.
  • VOH oxygen vacancies
  • the OS transistor is likely to have normally-on characteristics. Therefore, in the channel formation region in the oxide semiconductor, oxygen vacancies and hydrogen, which is one of the impurities, are preferably reduced as much as possible.
  • the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the channel formation region in the oxide semiconductor is made i-type (intrinsic) or substantially i-type.
  • the normally-on characteristic refers to a state in which a channel exists and current flows through the transistor even when no voltage is applied to the gate.
  • the normally-off characteristic refers to a state in which no current flows through the transistor when no potential is applied to the gate or when a ground potential is applied to the gate.
  • the vertical axis in FIG. 2 indicates the amount of oxygen supplied to the oxide semiconductor of the OS transistor (the amount of oxygen contained in the oxide semiconductor).
  • the amount of oxygen supplied to the oxide semiconductor becomes excessive toward the upper side of the vertical axis, and the amount of oxygen supplied to the oxide semiconductor becomes insufficient toward the lower side of the vertical axis.
  • the amount of oxygen supplied to the oxide semiconductor can be rephrased as the amount of oxygen released from an insulator provided in contact with the oxide semiconductor or the amount of oxygen released from an insulator provided near the oxide semiconductor.
  • the horizontal axis in FIG. 2 indicates the amount of hydrogen supplied to the oxide semiconductor of the OS transistor (the amount of hydrogen contained in the oxide semiconductor). The amount of hydrogen supplied to the oxide semiconductor becomes excessive toward the right side of the horizontal axis. Note that the amount of hydrogen supplied to the oxide semiconductor can be rephrased as the hydrogen concentration in the oxide semiconductor.
  • Figure 2 also shows a schematic diagram of the Id-Vg characteristics (drain current-gate voltage characteristics).
  • the vertical axis represents Id and the horizontal axis represents Vg.
  • the solid line represents the initial characteristics of the OS transistor, and the dashed line represents the Id-Vg characteristics of the OS transistor after a +GBT (Gate Bias-Temperature) stress test.
  • +GBT Gate Bias-Temperature
  • the amount of VOH in the oxide semiconductor increases.
  • the initial characteristics of the OS transistor are negatively shifted, and the OS transistor is likely to have normally-on characteristics.
  • negative drift degradation is likely to occur in the +GBT stress test.
  • the amount of negative drift degradation in the +GBT stress test increases. That is, by reducing the hydrogen concentration in the oxide semiconductor, as shown in 1) in FIG. 2, the OS transistor can have normally-off characteristics by suppressing a negative shift in the initial characteristics. Furthermore, negative drift degradation in the +GBT stress test can also be suppressed.
  • the hydrogen concentration in a channel formation region of the oxide semiconductor measured by secondary ion mass spectrometry is preferably less than 1 ⁇ 10 20 atoms/cm 3 , more preferably less than 5 ⁇ 10 19 atoms/cm 3 , still more preferably less than 1 ⁇ 10 19 atoms/cm 3 , still more preferably less than 5 ⁇ 10 18 atoms/cm 3 , still more preferably less than 1 ⁇ 10 18 atoms/cm 3 , and still more preferably less than 1 ⁇ 10 17 atoms/cm 3 .
  • the insulator 21 is preferably a barrier insulator against hydrogen.
  • the insulator 21 provided on the outside of the oxide semiconductor 30 has a barrier property against hydrogen, the diffusion of hydrogen into the oxide semiconductor 30 can be suppressed.
  • a barrier insulator refers to an insulator having barrier properties.
  • the barrier properties refer to a property that a corresponding substance is difficult to diffuse (also referred to as a property that a corresponding substance is difficult to permeate, a property that the permeability of a corresponding substance is low, or a function of suppressing the diffusion of a corresponding substance).
  • hydrogen refers to at least one of, for example, a hydrogen atom, a hydrogen molecule, and a substance bonded to hydrogen such as a water molecule and OH ⁇ .
  • impurities when impurities are described as a corresponding substance, they refer to impurities in a channel formation region or a semiconductor layer, unless otherwise specified, and refer to at least one of, for example, a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N 2 O, NO, NO 2 , etc.), a copper atom, etc.
  • oxygen when oxygen is described as a corresponding substance, it refers to at least one of, for example, an oxygen atom, an oxygen molecule, etc.
  • Barrier insulators against hydrogen include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride.
  • the insulator 21 contains silicon and nitrogen.
  • Silicon nitride that can be used as the insulator 21 has a barrier property against hydrogen if the film thickness is, for example, 2 nm or more.
  • the silicon nitride film thickness is preferably 3 nm or more, and more preferably 5 nm or more.
  • Silicon nitride has a barrier property against oxygen if the film thickness is, for example, 1 nm or more.
  • the silicon nitride film thickness is preferably 2 nm or more. In other words, silicon nitride formed with a film thickness that has a barrier property against hydrogen also has a barrier property against oxygen.
  • the shortest distance between the outer side of the oxide semiconductor 30 and the outer side of the adjacent oxide semiconductor 30 is the distance H.
  • the distance H can also be said to be the width of the insulator 21 in the B1-B2 direction. Since the insulator 21 preferably has a barrier property against hydrogen, when silicon nitride is used as the insulator 21, the distance H (the width of the insulator 21 in the B1-B2 direction) is preferably 2 nm or more, and more preferably 3 nm or more.
  • the upper limit of the distance H is not particularly limited, but from the viewpoint of miniaturization or high integration of the semiconductor device, it is preferably 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 10 nm or less, or 5 nm or less. Therefore, the insulator 21 preferably has a region where the distance H is 2 nm or more and 200 nm or less, and more preferably has a region where the distance H is 2 nm or more and 100 nm or less. Additionally, the insulator 21 preferably has an area where the distance H is 3 nm or more and 200 nm or less, and more preferably has an area where the distance H is 3 nm or more and 100 nm or less.
  • the insulator 21 when the insulator 21 has a barrier property against hydrogen, the insulator 21 also has a barrier property against oxygen. Furthermore, the insulator 21 has a region in contact with the oxide semiconductor 30. Therefore, when the insulator 21 has a barrier property against oxygen, oxygen is extracted from the oxide semiconductor 30, and the formation of an excessive amount of oxygen vacancies in the oxide semiconductor 30 can be suppressed.
  • the insulator 51 is preferably an insulator having a function of capturing or fixing hydrogen.
  • the hydrogen concentration in the oxide semiconductor 30 located inside the insulator 21 can be reduced.
  • the hydrogen in the oxide semiconductor 30 is captured or fixed by the insulator 51, so that the hydrogen concentration in the insulator 51 is high.
  • the hydrogen concentration in the insulator 51 is higher than the hydrogen concentration in the oxide semiconductor 30.
  • the oxide semiconductor 30 has a region in which the hydrogen concentration is lower than the hydrogen concentration in the insulator 51.
  • the hydrogen concentration in the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 19 atoms/cm 3 in the channel formation region
  • the hydrogen concentration in the insulator 51 obtained by SIMS is 1 ⁇ 10 19 atoms/cm 3 or more, preferably 1 ⁇ 10 20 atoms/cm 3 or more, in at least a part of the region between the oxide semiconductor 30 and the conductor 60 .
  • the ability to capture or adhere to the corresponding substance can also be said to have the property of making the corresponding substance less likely to diffuse. Therefore, the ability to capture or adhere to the corresponding substance can be rephrased as barrier properties.
  • Examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium, and oxides containing one or both of aluminum and hafnium.
  • Examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate). Silicon oxide may also be added to these oxides. In other words, these oxides may contain silicon.
  • Examples of insulators having the function of capturing or fixing hydrogen include oxides containing magnesium and silicon, oxides containing aluminum and silicon, and oxides containing hafnium and silicon (hafnium silicate).
  • the oxide preferably has oxygen atoms with dangling bonds. Such oxides may have the property of capturing or fixing hydrogen with dangling bonds.
  • the oxide preferably has an amorphous structure. This is because in oxides with an amorphous structure, some oxygen atoms have dangling bonds.
  • the oxide preferably has an amorphous structure, but may have crystalline regions formed in some parts.
  • the oxide may have grain boundaries. This is because in oxides with grain boundaries, some oxygen atoms near the grain boundaries may have dangling bonds.
  • the insulator 51 contains hafnium and oxygen.
  • hafnium oxide may have an amorphous structure. It may also have some crystalline regions. It may also have grain boundaries. For these reasons, hafnium oxide has the property of capturing or adhering hydrogen, making it suitable as an insulator 51.
  • the polycrystallization of hafnium oxide can be suppressed.
  • oxides containing hafnium and silicon tend to have an amorphous structure. Therefore, oxides containing hafnium and silicon have the property of capturing or fixing hydrogen, and are therefore suitable as the insulator 51.
  • the flatness of the film can be improved. Therefore, the film thickness distribution of the film provided on the insulator 51 can be made uniform.
  • the atomic ratio of silicon to hafnium is preferably greater than 0 and less than 2, more preferably greater than 0 and less than 1, and even more preferably greater than 0 and less than 0.5.
  • Hafnium oxide is also a high dielectric constant (high-k) material.
  • An oxide containing hafnium and silicon can also be a high dielectric constant (high-k) material depending on the silicon content. Therefore, when a structure according to one aspect of the present invention is used in a transistor, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. It is also possible to reduce the equivalent oxide thickness (EOT) of the insulator that functions as the gate insulator.
  • EOT equivalent oxide thickness
  • the width of the insulator 51 in the B1-B2 direction is preferably 0.5 nm to 15 nm, more preferably 0.5 nm to 12 nm, and even more preferably 0.5 nm to 10 nm. It is sufficient that at least a portion of the insulator 51 has a region with the above-mentioned width.
  • the width of the insulator 51 in the B1-B2 direction can also be referred to as the film thickness of the insulator 51.
  • an oxide semiconductor with few oxygen vacancies and impurities can be provided. Therefore, by using the structure in a transistor, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.
  • the structure having the above configuration when used in a transistor, the formation of oxygen vacancies in the channel formation region and the diffusion of hydrogen into the channel formation region can be suppressed. This makes it possible to suppress the variation in the amount of oxygen vacancies and hydrogen concentration in the channel formation region from transistor to transistor. Therefore, the variation in the electrical characteristics of the transistor can be reduced.
  • FIG. 1A and 1B show a configuration in which a barrier insulator against hydrogen is provided on the outside of the oxide semiconductor 30, but the present invention is not limited to this.
  • a barrier insulator against hydrogen may be provided on the inside of a hollow portion of the oxide semiconductor 30 in addition to the outside of the oxide semiconductor 30.
  • Figure 1C is a perspective view of a structure according to one embodiment of the present invention.
  • Figure 1D is a cross-sectional view of the structure, which also corresponds to the portion indicated by the dashed line B1-B2 in Figure 1C.
  • the insulator 52 is provided between the insulator 51 and the conductor 60. It is preferable to use a barrier insulator against hydrogen as the insulator 52. With this configuration, the oxide semiconductor 30 can be sandwiched between the barrier insulators against hydrogen. For example, it is possible to suppress the diffusion of hydrogen contained in the conductor 60 into the oxide semiconductor 30. Therefore, the diffusion of hydrogen into the oxide semiconductor 30 can be further suppressed.
  • the insulator 52 preferably has a barrier property against hydrogen.
  • the width of the insulator 52 in the B1-B2 direction is preferably 2 nm or more, more preferably 3 nm or more.
  • the upper limit of the width of the insulator 52 in the B1-B2 direction is not particularly limited, but from the viewpoint of miniaturization or high integration of the semiconductor device and improvement of the productivity of the semiconductor device, it is preferably 20 nm or less, 10 nm or less, or 5 nm or less.
  • the insulator 52 preferably has a region with a width in the B1-B2 direction of 2 nm or more and 10 nm or less, more preferably a region with a width in the B1-B2 direction of 2 nm or more and 5 nm or less.
  • the insulator 52 preferably has a region with a width in the B1-B2 direction of 3 nm or more and 10 nm or less, more preferably a region with a width in the B1-B2 direction of 3 nm or more and 5 nm or less.
  • the width of the insulator 52 in the B1-B2 direction can also be called the film thickness of the insulator 52.
  • the insulator 52 when the insulator 52 has a barrier property against hydrogen, the insulator 52 also has a barrier property against oxygen. Furthermore, the insulator 52 has a region in contact with the conductor 60. Therefore, since the insulator 52 has a barrier property against oxygen, it is possible to prevent oxygen contained in the oxide semiconductor 30 or the insulator 51 from diffusing into the conductor 60 and oxidizing the conductor 60. It is also possible to prevent oxygen contained in the oxide semiconductor 30 from diffusing into the conductor 60 and forming oxygen vacancies in the oxide semiconductor 30.
  • the width of the insulator 52 in the B1-B2 direction is not limited to the above because the insulator 21 suppresses the diffusion of hydrogen into the oxide semiconductor 30.
  • the width of the insulator 52 in the B1-B2 direction may be 0.1 nm or more and less than 3 nm, or 0.1 nm or more and less than 2 nm.
  • the insulator 51 and the insulator 52 can each function as a gate insulating film of the transistor.
  • the structures shown in Figs. 1A and 1B and the structures shown in Figs. 1C and 1D can be formed, for example, by providing an oxide semiconductor 30 or the like inside an opening in an insulator 21.
  • an oxide semiconductor 30, an insulator 51, and a conductor 60 are provided in this order inside an opening in an insulator 21.
  • an oxide semiconductor 30, an insulator 51, an insulator 52, and a conductor 60 are provided in this order inside an opening in an insulator 21.
  • the present invention is not limited to this.
  • the insulator 21 may be provided inside an opening in an insulator different from the insulator 21.
  • Figure 1E is a perspective view of a structure according to one embodiment of the present invention.
  • Figure 1F is a cross-sectional view of the structure, which is also a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in Figure 1E.
  • the insulator 21 in the B1-B2 direction is within the range of the width of the insulator 52 in the B1-B2 direction described above.
  • the structure shown in Figures 1E and 1F allows for a wider range of material options for the insulator having an opening in which the oxide semiconductor 30 and the like are provided.
  • a material with a low dielectric constant can be used as the insulator 24.
  • the parasitic capacitance generated between the conductors can be reduced.
  • a conductor can be provided instead of the insulator 24.
  • the oxide semiconductor 30 can be sandwiched between the two conductors.
  • the insulator having the opening where the oxide semiconductor 30 and the like are provided also serves as a barrier insulator against hydrogen, so there is no need to provide a separate barrier insulator against hydrogen. Therefore, the manufacturing process of a semiconductor device including the structure can be simplified, and productivity can be improved.
  • FIGS. 3A and 3D are perspective views illustrating the shape of the oxide semiconductor 30.
  • FIGS. 3B, 3C, 3E, and 3F are cross-sectional views illustrating the shape of the oxide semiconductor 30.
  • the oxide semiconductor 30 and the insulator 21 are illustrated.
  • a part of the insulator 21 is illustrated by a dashed line.
  • the upper surface of the oxide semiconductor 30 may be flush with the upper surface of the insulator 21.
  • the oxide semiconductor 30 may be cylindrical with a hollow portion as shown in FIG. 3B.
  • the oxide semiconductor 30 may be cylindrical with a bottom as shown in FIG. 3C.
  • the oxide semiconductor 30 may be cylindrical with a groove.
  • FIG. 3A shows a configuration in which the top surface of the oxide semiconductor 30 is flush with the top surface of the insulator 21.
  • the present invention is not limited to this.
  • a part of the oxide semiconductor 30 may be located above the insulator 21.
  • the oxide semiconductor 30 may have a region that contacts the top surface of the insulator 21.
  • the oxide semiconductor 30 may have a cylindrical shape with a hollow portion as shown in FIG. 3E. Or, as shown in FIG. 3F, it may have a cylindrical shape with a bottom.
  • 3D to 3F show a configuration in which the oxide semiconductor 30 has a region in contact with the upper surface of the insulator 21, but the present invention is not limited to this.
  • the oxide semiconductor 30 may be in contact with at least a portion of the upper surface of a layer provided on the insulator 21.
  • the layer may have an opening that overlaps with the opening of the insulator 21.
  • the layer may be an insulator, a semiconductor, or a conductor.
  • the insulator may have a structure in which multiple types selected from an insulator, a semiconductor, and a conductor are stacked.
  • FIG. 3 shows a configuration in which the lower surface of the oxide semiconductor 30 is flush with the lower surface of the insulator 21, the present invention is not limited to this.
  • the lower surface of the oxide semiconductor 30 may be located higher than the lower surface of the insulator 21, or may be located lower than the lower surface of the insulator 21.
  • the outer side surface of the oxide semiconductor 30 and the inner side surface of the oxide semiconductor 30 are perpendicular or approximately perpendicular to the substrate surface (not shown), but the present invention is not limited to this.
  • the outer side surface of the oxide semiconductor 30 and the inner side surface of the oxide semiconductor 30 may have a tapered shape or an inverse tapered shape.
  • ⁇ Configuration Example 2> The structure described in the above-mentioned ⁇ Configuration Example 1> has a region where the oxide semiconductor 30 and the insulator 21 are in contact with each other. However, the present invention is not limited to this. If the oxide semiconductor 30 is provided inside an opening of the insulator 21, the oxide semiconductor 30 and the insulator 21 do not need to be in contact with each other.
  • the differences from the above-mentioned description of ⁇ Configuration Example 1> will be mainly described, and the same description will be referred to for the overlapping parts, and may be omitted.
  • Figure 4A is a perspective view of a structure according to one embodiment of the present invention.
  • Figure 4B is a cross-sectional view of the structure, which also corresponds to the portion indicated by the dashed line B1-B2 in Figure 4A.
  • the structure shown in Figures 4A and 4B has an oxide semiconductor 30, an insulator 21, an insulator 22, an insulator 51, and a conductor 60.
  • the structure shown in Figures 4A and 4B differs from the structure shown in Figures 1A and 1B mainly in that it has an insulator 22.
  • the insulator 22 is provided between the insulator 21 and the oxide semiconductor 30.
  • the insulator 22 is preferably an insulator having a function of capturing or fixing hydrogen.
  • the insulator 22 can be made of a material applicable to the insulator 51.
  • the oxide semiconductor 30 can be sandwiched between insulators that capture or fix hydrogen.
  • the oxide semiconductor 30 sandwiched between the insulators that capture or fix hydrogen can be surrounded by a barrier insulator against hydrogen.
  • the hydrogen concentration in the oxide semiconductor 30 can be further reduced.
  • a part of the hydrogen in the oxide semiconductor 30 is captured or fixed by the insulator 51.
  • Another part of the hydrogen in the oxide semiconductor 30 is captured or fixed by the insulator 22.
  • the hydrogen concentration in the insulator 51 and the hydrogen concentration in the insulator 22 are high.
  • the hydrogen concentration in the insulator 51 and the hydrogen concentration in the insulator 22 are higher than the hydrogen concentration in the oxide semiconductor 30.
  • an oxide semiconductor with few oxygen vacancies and impurities can be provided. Therefore, by using the structure in a transistor, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.
  • the structure having the above configuration when used in a transistor, the formation of oxygen vacancies in the channel formation region and the diffusion of hydrogen into the channel formation region can be suppressed. This makes it possible to suppress the variation in the amount of oxygen vacancies and hydrogen concentration in the channel formation region from transistor to transistor. Therefore, the variation in the electrical characteristics of the transistor can be reduced.
  • insulator 22 having the function of capturing or fixing hydrogen is provided inside the insulator 21
  • an insulator 52 may be provided instead of the insulator 51, as shown in Figs. 4C and 4D.
  • the oxide semiconductor 30 can be sandwiched between barrier insulators against hydrogen.
  • the diffusion of hydrogen contained in the conductor 60 into the oxide semiconductor 30 can be suppressed. Therefore, the diffusion of hydrogen into the oxide semiconductor 30 can be further suppressed.
  • Fig. 4C is a perspective view of a structure according to one embodiment of the present invention.
  • Fig. 4D is a cross-sectional view of the structure, and is also a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in Fig. 4C.
  • FIG. 4E is a perspective view of a structure according to one embodiment of the present invention.
  • FIG. 4F is a cross-sectional view of the structure, and is also a cross-sectional view corresponding to the portion indicated by the dashed line B1-B2 in FIG. 4E.
  • the structure shown in FIG. 4E and FIG. 4F is mainly different from the structure shown in FIG. 1C and FIG. 1D in that it has an insulator 52.
  • the structure shown in FIG. 4E and FIG. 4F is also a modified example of the structure shown in FIG. 1C and FIG. 1D.
  • the structure shown in FIG. 4E and FIG. 4F can be formed, for example, by providing an oxide semiconductor 30 or the like inside an opening of the insulator 21. Specifically, inside an opening of the insulator 21, the insulator 22, the oxide semiconductor 30, the insulator 51, the insulator 52, and the conductor 60 are provided in this order. At this time, the insulator 52 is provided between the conductor 60 and the insulator 51.
  • the insulator 21 may be provided, for example, inside an opening of an insulator different from the insulator 21.
  • Figure 5A is a perspective view of a structure according to one embodiment of the present invention.
  • Figure 5B is a cross-sectional view of the structure, which also corresponds to the portion indicated by the dashed line B1-B2 in Figure 5A.
  • FIG. 5A and 5B differs from the structure shown in Figures 4E and 4F mainly in that it has an insulator 24.
  • the differences from the above description will be mainly explained, and for overlapping parts, the above description will be referred to and explanations may be omitted.
  • the width of the insulator 21 in the B1-B2 direction is within the range of the width of the insulator 52 in the B1-B2 direction described above.
  • the configuration shown in Figures 5A and 5B can expand the range of material options for the insulator (insulator 24 in this case) having an opening in which the oxide semiconductor 30 and the like are provided.
  • the configuration shown in Figures 4A and 4B, etc. can eliminate the need to provide a separate barrier insulator against hydrogen, since the insulator (insulator 21 in this case) having an opening in which the oxide semiconductor 30 and the like are provided also serves as a barrier insulator against hydrogen. This can simplify the manufacturing process of a semiconductor device including the structure, thereby improving productivity.
  • an insulator has an opening in which the oxide semiconductor 30 and the like are disposed, but the present invention is not limited to this.
  • a conductor may have an opening in which the oxide semiconductor 30 and the like are disposed.
  • Figure 5C is a perspective view of a structure according to one embodiment of the present invention.
  • Figure 5D is a cross-sectional view of the structure, which also corresponds to the portion indicated by the dashed line B1-B2 in Figure 5C.
  • an insulator 21, an insulator 22, an oxide semiconductor 30, an insulator 51, an insulator 52, and a conductor 60 are provided in this order.
  • the conductor 15 has a region facing the oxide semiconductor 30 via the insulators 21 and 22.
  • the conductor 15 also has a region facing the conductor 60 via the oxide semiconductor 30.
  • the oxide semiconductor 30 has a region located between the conductor 60 and the conductor 15.
  • the oxide semiconductor 30 can be used, for example, as a semiconductor layer of a transistor.
  • the conductor 60 can function as a first gate electrode of the transistor.
  • the insulators 51 and 52 can function as a first gate insulating film of the transistor.
  • the conductor 15 can function as a second gate electrode of the transistor.
  • the insulators 21 and 22 can function as a second gate insulating film of the transistor.
  • At least a part of the region of the oxide semiconductor 30 located between the conductor 60 and the conductor 15 can function as a channel formation region.
  • the threshold voltage (Vth) of the transistor can be controlled by changing the potential applied to the conductor 15 independently of the potential applied to the conductor 60.
  • applying a negative potential (a potential lower than the source potential) to one of the conductor 15 and the conductor 60 can increase the Vth of the transistor and reduce the off-current. Therefore, applying a negative potential to one of the conductor 15 and the conductor 60 can reduce the drain current when the potential applied to the other of the conductor 15 and the conductor 60 is 0 V, compared to not applying a negative potential to one of the conductor 15 and the conductor 60.
  • conductor 15 may be electrically connected to conductor 60.
  • conductor 15 and conductor 60 By connecting conductor 15 and conductor 60 and applying the same potential, it is possible to increase the on-current, reduce the initial characteristic variation, suppress the deterioration of electrical characteristics in a -GBT stress test, and suppress the variation in the on-current rise voltage at different drain voltages.
  • the oxide semiconductor 30 is provided so as to be located between the conductor 60 and the conductor 15. Note that the present invention is not limited to this.
  • a structure according to one embodiment of the present invention may have at least one of the conductor 60 and the conductor 15. Note that the structure having the conductor 60 has been described with reference to FIG. 1A and FIG. 1B, etc. Hereinafter, the structure having the conductor 15 will be described with reference to FIG. 6A to FIG. 7D.
  • Figure 6A is a perspective view of another example of a structure according to one embodiment of the present invention.
  • Figure 6B is a cross-sectional view of the structure, which also corresponds to the portion indicated by the dashed line B1-B2 in Figure 6A.
  • the structure shown in Figures 6A and 6B has an oxide semiconductor 30, a conductor 15, an insulator 21, an insulator 22, an insulator 51, an insulator 52, and an insulator 75.
  • the structure shown in Figures 6A and 6B differs from the structure shown in Figures 5C and 5D mainly in that it has an insulator 75 instead of a conductor 60.
  • the insulator 75 is provided inside the opening of the insulator 52.
  • the insulator 75 has an area in contact with the insulator 52.
  • the insulator 75 can be a single layer or a multilayer insulator as described in the [Insulator] section of the second embodiment described below.
  • the oxide semiconductor 30 can be used, for example, as a semiconductor layer of a transistor.
  • the conductor 15 can function as a gate electrode of the transistor.
  • the insulators 21 and 22 can function as a gate insulating film of the transistor. At least a part of the region of the oxide semiconductor 30 that faces the conductor 15 via the insulators 21 and 22 can function as a channel formation region.
  • the oxide semiconductor 30 can be sandwiched between insulators (insulator 22 and insulator 51 in this example) that capture or fix hydrogen. Furthermore, the oxide semiconductor 30 sandwiched between the insulators that capture or fix hydrogen can be sandwiched between barrier insulators against hydrogen (insulator 21 and insulator 52 in this example). Thus, the hydrogen concentration in the oxide semiconductor 30 can be further reduced. At this time, a part of the hydrogen in the oxide semiconductor 30 is captured or fixed by the insulator 51. Another part of the hydrogen in the oxide semiconductor 30 is captured or fixed by the insulator 22. Thus, the hydrogen concentration in the insulator 51 and the hydrogen concentration in the insulator 22 are increased. For example, the hydrogen concentration in the insulator 51 and the hydrogen concentration in the insulator 22 are higher than the hydrogen concentration in the oxide semiconductor 30.
  • insulators 22 and 51 may be provided.
  • insulator 22 is provided but insulator 51 is not provided
  • Figures 6E and 6F a configuration may be used in which insulator 51 is provided but insulator 22 is not provided.
  • the oxide semiconductor 30 when the oxide semiconductor 30 is surrounded by a barrier insulator against hydrogen (e.g., insulator 21), the insulator 52 may not be provided.
  • a barrier insulator against hydrogen e.g., insulator 21
  • the oxide semiconductor 30 has a region in contact with the insulator 75.
  • an insulator 75 is provided inside the opening of the oxide semiconductor 30.
  • the oxide semiconductor 30 may not have an opening depending on the area of the opening of the insulator 22 in a plan view, the film thickness of the oxide semiconductor 30, and the like. In this case, it is not necessary to provide the insulator 75. Even in this case, the oxide semiconductor 30 can be sandwiched between insulators that capture or fix hydrogen (insulator 22 in this case). Furthermore, the oxide semiconductor 30 sandwiched between insulators that capture or fix hydrogen can be sandwiched between barrier insulators against hydrogen (insulator 21 in this case). Therefore, the hydrogen concentration in the oxide semiconductor 30 can be reduced.
  • ⁇ Configuration Example 3> In the above-mentioned ⁇ Configuration Example 1> and ⁇ Configuration Example 2>, a configuration has been described in which the oxide semiconductor 30 is provided inside the opening of the insulator 21. Note that the present invention is not limited to this.
  • the structure may have a configuration in which the oxide semiconductor 30 is sandwiched between a pair of barrier insulators against hydrogen.
  • differences from the above-mentioned ⁇ Configuration Example 1> and ⁇ Configuration Example 2> will be mainly described, and overlapping parts will be referred to and may not be described.
  • FIG. 9A is a cross-sectional view of a structure according to one embodiment of the present invention.
  • the structure shown in FIG. 9A has an insulator 21, an oxide semiconductor 30 on the insulator 21, an insulator 51 on the oxide semiconductor 30, an insulator 52 on the insulator 51, and a conductor 60 on the insulator 52.
  • the structure shown in FIG. 9A can also be called a laminate.
  • the oxide semiconductor 30 can be used, for example, as a semiconductor layer of a transistor.
  • the conductor 60 can function as a gate electrode of the transistor.
  • the insulators 51 and 52 can function as gate insulating films of the transistor. At least a part of the region of the oxide semiconductor 30 that overlaps with the conductor 60 can function as a channel formation region.
  • the oxide semiconductor 30 is provided between the insulator 21 and the insulator 52. As described above, it is preferable to use a barrier insulator against hydrogen for the insulators 21 and 52. This allows the oxide semiconductor 30 to be sandwiched between the barrier insulators against hydrogen. This makes it possible to suppress the diffusion of hydrogen from above the insulator 52 and below the insulator 21 into the oxide semiconductor 30.
  • the film thickness of insulator 21 and the film thickness of insulator 52 are within the range of the width of insulator 52 in the B1-B2 direction described in ⁇ Configuration Example 1>.
  • an insulator 51 is provided between the oxide semiconductor 30 and the insulator 52.
  • an insulator having the function of capturing or fixing hydrogen as the insulator 51. This makes it possible to reduce the hydrogen concentration in the oxide semiconductor 30 located between the insulator 21 and the insulator 52.
  • an oxide semiconductor with few oxygen vacancies and impurities can be provided. Therefore, by using the structure in a transistor, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.
  • the structure having the above configuration when used in a transistor, the formation of oxygen vacancies in the channel formation region and the diffusion of hydrogen into the channel formation region can be suppressed. This makes it possible to suppress the variation in the amount of oxygen vacancies and hydrogen concentration in the channel formation region from transistor to transistor. Therefore, the variation in the electrical characteristics of the transistor can be reduced.
  • FIG. 9A shows a configuration in which the insulator 21 and the oxide semiconductor 30 are in contact with each other.
  • the present invention is not limited to this. If the oxide semiconductor 30 is sandwiched between barrier insulators against hydrogen, the insulator 21 and the oxide semiconductor 30 do not need to be in contact with each other.
  • an insulator 22 may be provided between the insulator 21 and the oxide semiconductor 30 without providing the insulator 51.
  • an insulator having the function of capturing or fixing hydrogen as the insulator 22. Even with such a configuration, the hydrogen concentration in the oxide semiconductor 30 can be reduced.
  • an insulator 22 may be provided as an insulator having the function of capturing or fixing hydrogen. With such a configuration, the hydrogen concentration in the oxide semiconductor 30 can be further reduced.
  • FIG. 9D shows a cross-sectional view of a structure in which the conductor 15 is provided below the insulator 21.
  • the conductor 60 when the oxide semiconductor 30 is used as a semiconductor layer of a transistor, the conductor 60 can function as a first gate electrode of the transistor.
  • the insulators 51 and 52 can function as a first gate insulating film of the transistor.
  • the conductor 15 can function as a second gate electrode of the transistor.
  • the insulators 21 and 22 can function as a second gate insulating film of the transistor.
  • At least a part of a region of the oxide semiconductor 30 located between the conductor 60 and the conductor 15 can function as a channel formation region.
  • the potential applied to the conductor 15 may be changed independently of the potential applied to the conductor 60, without being linked to the potential applied to the conductor 60.
  • the conductor 15 may be connected to the conductor 60.
  • ⁇ Configuration Example 4> In the above-mentioned ⁇ Configuration Example 1> and ⁇ Configuration Example 2>, the case where the oxide semiconductor 30 has a cylindrical region with a hollow portion has been described. Note that the present invention is not limited to this.
  • the oxide semiconductor 30 may be in contact with at least a part of the side wall of the opening in which the oxide semiconductor 30 is provided.
  • differences from the above-mentioned ⁇ Configuration Example 1> and ⁇ Configuration Example 2> will be mainly described, and overlapping portions will be referred to and may not be described.
  • Figure 8A is a perspective view of a structure according to one embodiment of the present invention.
  • Figure 8B is a cross-sectional view of the structure, which also corresponds to the portion indicated by the dashed line B1-B2 in Figure 8A.
  • the structure shown in Figures 8A and 8B has an oxide semiconductor 30, an insulator 21, an insulator 51, and a conductor 60.
  • the structure shown in Figures 8A and 8B differs from the structure shown in Figures 1A and 1B mainly in the shape of the oxide semiconductor 30.
  • the oxide semiconductor 30, the insulator 51, and the conductor 60 are provided inside an opening in the insulator 21.
  • the insulator 21 has a region in contact with the oxide semiconductor 30 and a region in contact with the insulator 51.
  • a part of the side surface of the insulator 21 contacts the oxide semiconductor 30, and another part of the side surface of the insulator 21 contacts the insulator 51.
  • the oxide semiconductor 30 contacts a part of the sidewall of the opening in the insulator 21. As shown in FIG. 8B, the oxide semiconductor 30 contacts the bottom of the opening in the insulator 21. In other words, the bottom surface of the oxide semiconductor 30 in the opening contacts the surface on which the insulator 21 is to be formed.
  • the oxide semiconductor 30 also has a region that faces the conductor 60 via the insulator 51.
  • the oxide semiconductor 30 can be used, for example, as a semiconductor layer of a transistor.
  • the conductor 60 can function as a gate electrode of the transistor.
  • the insulator 51 can function as a gate insulating film of the transistor. At least a part of the region of the oxide semiconductor 30 that faces the conductor 60 via the insulator 51 can function as a channel formation region.
  • the oxide semiconductor 30 can be surrounded on three sides by an insulator (insulator 51 in this case) that captures or fixes hydrogen. Furthermore, the oxide semiconductor 30 sandwiched between the insulators that capture or fix hydrogen can be surrounded by a barrier insulator against hydrogen (insulator 21 in this case). Therefore, the hydrogen concentration in the oxide semiconductor 30 can be reduced.
  • an oxide semiconductor with few oxygen vacancies and impurities can be provided. Therefore, by using the structure in a transistor, the electrical characteristics of the transistor can be improved, and the reliability of the transistor can be improved.
  • the structure having the above configuration when used in a transistor, the formation of oxygen vacancies in the channel formation region and the diffusion of hydrogen into the channel formation region can be suppressed. This makes it possible to suppress the variation in the amount of oxygen vacancies and hydrogen concentration in the channel formation region from transistor to transistor. Therefore, the variation in the electrical characteristics of the transistor can be reduced.
  • the opening of the insulator 21 has a rectangular shape with rounded corners in plan view.
  • the maximum width of the opening may be calculated appropriately according to the shape of the top of the opening.
  • the maximum width of the opening may be the length of the diagonal or the distance between the opposing sides when the top of the opening is regarded as a rectangle.
  • the present invention is not limited to this.
  • the opening may have a substantially circular shape such as a circle or an ellipse, a polygonal shape, or a polygonal shape with rounded corners in plan view.
  • the conductor 60 is in contact with the insulator 51.
  • the insulator 21 is in contact with the oxide semiconductor 30 and the insulator 51.
  • one aspect of the present invention is not limited to this.
  • an insulator 52 may be provided between a conductor 60 and an insulator 51.
  • a barrier insulator against hydrogen as the insulator 52, the oxide semiconductor 30 can be sandwiched between barrier insulators against hydrogen (here, the insulators 21 and 52).
  • an insulator 22 may be provided between the oxide semiconductor 30 and the insulator 51 and the insulator 21.
  • the oxide semiconductor 30 can be sandwiched between the insulators that capture or fix hydrogen (here, the insulators 22 and 51).
  • a semiconductor device having good electrical characteristics can be provided.
  • a highly reliable semiconductor device can be provided.
  • a semiconductor device with less variation in the electrical characteristics of transistors can be provided.
  • a semiconductor device with a large on-current can be provided.
  • Embodiment 2 10A to 26B, an example of a semiconductor device according to one embodiment of the present invention will be described.
  • the semiconductor device according to one embodiment of the present invention has the structure described in Embodiment 1.
  • Fig. 10A to Fig. 10D are plan views and cross-sectional views of a semiconductor device including a transistor 200A.
  • Fig. 10A is a plan view of the semiconductor device.
  • Fig. 10B to Fig. 10D are cross-sectional views of the semiconductor device.
  • Fig. 10B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in Fig. 10A.
  • Fig. 10C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in Fig. 10A. Note that some elements are omitted in the plan view of Fig. 10A for clarity.
  • arrows indicating the X-direction, Y-direction, and Z-direction may be attached.
  • the "X-direction” is the direction along the X-axis, and the forward direction and the reverse direction may not be distinguished unless explicitly stated. The same applies to the "Y-direction” and "Z-direction”.
  • the X-direction, Y-direction, and Z-direction are directions that intersect with each other.
  • the X-direction, Y-direction, and Z-direction are directions that are perpendicular to each other.
  • one of the X-direction, Y-direction, and Z-direction may be called the "first direction” or “first direction”.
  • the other may be called the “second direction” or “second direction”.
  • the remaining one may be called the "third direction” or "third direction”.
  • the semiconductor device shown in Figures 10A to 10D has an insulator 210 on a substrate (not shown), a transistor 200A on the insulator 210, an insulator 280 on the insulator 210, and an insulator 283 on the transistor 200A.
  • the insulator 210 functions as an interlayer film.
  • Transistor 200A has a conductor 220, a conductor 240 on insulator 280, an oxide semiconductor 230, an insulator 251 on oxide semiconductor 230, an insulator 252 on insulator 251, and a conductor 260 on insulator 252.
  • the insulator 280 and the conductor 240 have an opening 290 that reaches the conductor 220.
  • the bottom of the opening 290 is the top surface of the conductor 220
  • the side walls of the opening 290 are the side surfaces of the insulator 280 and the conductor 240.
  • the opening 290 includes an opening in the insulator 280 and an opening in the conductor 240. In other words, the opening in the area where the insulator 280 overlaps with the conductor 220 is a part of the opening 290, and the opening in the area where the conductor 240 overlaps with the conductor 220 is another part of the opening 290.
  • At least some of the components of the transistor 200A are arranged in the opening 290.
  • the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 are each arranged so that at least a portion of them is located in the opening 290.
  • the portions of the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290.
  • the oxide semiconductor 230 is provided to cover the bottom and sidewalls of the opening 290
  • the insulator 251 is provided to cover the oxide semiconductor 230
  • the insulator 252 is provided to cover the insulator 251
  • the conductor 260 is provided to fill the recess of the insulator 252 that reflects the shape of the opening 290.
  • oxide semiconductor 230 functions as a semiconductor layer
  • conductor 260 functions as a gate electrode
  • insulators 251 and 252 function as gate insulators
  • conductor 220 functions as one of the source electrode and drain electrode
  • conductor 240 functions as the other of the source electrode and drain electrode.
  • the oxide semiconductor 230 is provided inside the opening of the insulator 280.
  • the transistor 200A has a configuration in which one of the source electrode and the drain electrode (here, the conductor 220) is located on the lower side and the other of the source electrode and the drain electrode (here, the conductor 240) is located on the upper side, so that the current flows in the vertical direction. In other words, a channel is formed along the side of the opening of the insulator 280.
  • the transistor 200A it is preferable to use a metal oxide (also called an oxide semiconductor) that functions as a semiconductor for the oxide semiconductor 230 including the channel formation region. In this case, the transistor 200A becomes an OS transistor.
  • a metal oxide also called an oxide semiconductor
  • the channel formation region of an OS transistor is preferably a high-resistance region with a low carrier concentration. Therefore, the channel formation region of an OS transistor is preferably i-type (intrinsic) or substantially i-type.
  • the source and drain regions of an OS transistor are preferably regions having more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, thereby increasing the carrier concentration and lowering the resistance. That is, the source and drain regions of an OS transistor are preferably n-type regions having a higher carrier concentration and lower resistance than the channel formation region.
  • 10A to 10D has a configuration in which an oxide semiconductor 230, an insulator 251, an insulator 252, and a conductor 260 are provided in this order inside an opening of an insulator 280. That is, the semiconductor device shown in FIG. 10A to 10D has the structure described with reference to FIG. 1C and FIG. 1D. Therefore, the oxide semiconductor 230, the insulator 280, the insulator 251, the insulator 252, and the conductor 260 in the configurations shown in FIG. 10A to 10D correspond to the oxide semiconductor 30, the insulator 21, the insulator 51, the insulator 52, and the conductor 60 in the configurations shown in FIG. 1C and FIG. 1D described in embodiment 1, respectively.
  • the insulator 280 it is preferable to use a barrier insulator against hydrogen.
  • an insulator applicable to the insulator 21 described in embodiment 1 can be used.
  • the insulator 251 it is preferable to use an insulator having a function of capturing or fixing hydrogen.
  • As the insulator 251 it is preferable to use an insulator applicable to the insulator 51 described in embodiment 1.
  • the insulator 252 it is preferable to use a barrier insulator against hydrogen.
  • the insulator 252 it is possible to use an insulator applicable to the insulator 52 described in embodiment 1.
  • the sidewalls of the opening 290 are preferably perpendicular to the top surface of the insulator 210. This configuration allows for miniaturization or high integration of the semiconductor device.
  • the opening 290 is provided so that the sidewall of the opening 290 is perpendicular to the upper surface of the insulator 210, but the present invention is not limited thereto.
  • the sidewall of the opening 290 may be tapered.
  • the coverage of the oxide semiconductor 230, the insulator 251, the insulator 252, and the like can be improved, and defects such as voids can be reduced.
  • the angle between the side surface of the insulator 280 at the opening 290 and the upper surface of the insulator 210 is preferably 45 degrees or more and less than 90 degrees. Alternatively, it is preferably 45 degrees or more and 75 degrees or less. Alternatively, it is preferably 45 degrees or more and 65 degrees or less.
  • the sidewall of the opening 290 may have an inverse tapered shape.
  • the angle between the side surface of the insulator 280 at the opening 290 and the top surface of the insulator 210 may be greater than 90 degrees.
  • the oxide semiconductor 230 has a region that contacts the side surface of the conductor 240 in the opening 290 and a region that contacts at least a portion of the top surface of the conductor 240. In this way, the oxide semiconductor 230 contacts not only the side surface but also the top surface of the conductor 240, so that the area in which the oxide semiconductor 230 and the conductor 240 contact each other can be increased. In addition, the oxide semiconductor 230 has a region that contacts the top surface of the conductor 220 exposed in the opening 290 and a region that contacts the side surface of the insulator 280 in the opening 290.
  • a portion of the oxide semiconductor 230 is located outside the opening 290, i.e., above the conductor 240.
  • Figure 10B shows a configuration in which the oxide semiconductor 230 is divided in the X direction
  • the present invention is not limited to this.
  • the oxide semiconductor 230 may be provided extending in the X direction. Note that even in this case, the oxide semiconductor 230 is divided in the Y direction.
  • FIG. 10C shows a configuration in which the side end of the oxide semiconductor 230 is located inside the side end of the conductor 240.
  • the present invention is not limited to this.
  • a structure in which the side end of the oxide semiconductor 230 and the side end of the conductor 240 coincide in the Y direction may be used.
  • a structure in which the side end of the oxide semiconductor 230 is located outside the side end of the conductor 240 may be used.
  • the insulator 251 is provided in contact with the top surface of the oxide semiconductor 230.
  • the insulator 251 has a region in contact with the top surface of the conductor 240, a region in contact with the side surface of the conductor 240, and a region in contact with the insulator 280.
  • Insulator 252 is provided in contact with the upper surface of insulator 251.
  • a part of the insulator 251 and a part of the insulator 252 are located outside the opening 290, that is, on the conductor 240 and the insulator 280.
  • the insulators 251 and 252 preferably cover the side end of the oxide semiconductor 230. This can prevent the conductor 260 and the oxide semiconductor 230 from shorting out.
  • the insulators 251 and 252 preferably cover the side end of the conductor 240. This can prevent the conductor 260 and the conductor 240 from shorting out.
  • the conductor 260 is provided in contact with the upper surface of the insulator 252.
  • a portion of the conductor 260 is located outside the opening 290, i.e., above the conductor 240 and the insulator 280.
  • the side end of the conductor 260 is located inside the side end of the oxide semiconductor 230. This makes it possible to prevent a short circuit between the conductor 260 and the oxide semiconductor 230.
  • the side end of the conductor 260 may coincide with the side end of the oxide semiconductor 230, or may be located outside the side end of the oxide semiconductor 230.
  • the conductor 260 is provided so as to fill the opening 290, but the present invention is not limited to this.
  • a recess reflecting the shape of the opening 290 may be formed in the conductor 260, and a part of the recess may be located in the opening 290.
  • the recess may be filled with an inorganic insulating material or the like.
  • the conductor 240 has an opening in a region overlapping with the conductor 220.
  • the conductor 240 is not provided inside the opening of the insulator 280.
  • the conductor 240 does not have a region in contact with the side surface of the insulator 280 in the opening 290.
  • the opening of the conductor 240 and the opening of the insulator 280 can be formed at the same time.
  • the film thickness distribution of the oxide semiconductor 230 provided inside the opening 290 can be made uniform. Furthermore, it is possible to prevent the oxide semiconductor 230 from being divided by the step between the conductor 240 and the insulator 280.
  • 10B and 10C show a configuration in which the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 are flush with each other, but the present invention is not limited to this.
  • the side surface of the conductor 240 in the opening 290 and the side surface of the insulator 280 in the opening 290 may be discontinuous.
  • the inclination of the side surface of the conductor 240 in the opening 290 and the inclination of the side surface of the insulator 280 in the opening 290 may be different from each other.
  • the angle between the side surface of the conductor 240 in the opening 290 and the upper surface of the insulator 210 is smaller than the angle between the side surface of the insulator 280 in the opening 290 and the upper surface of the insulator 210.
  • the oxide semiconductor 230 has a first region and a second region and a third region disposed so as to sandwich the first region.
  • the second region is a region in contact with the conductor 220 of the oxide semiconductor 230. At least a part of the second region functions as one of the source region and drain region of the transistor 200A.
  • the third region is a region in contact with the conductor 240 of the oxide semiconductor 230. At least a part of the third region functions as the other of the source region and drain region of the transistor 200A.
  • the first region is a region between the second region and the third region of the oxide semiconductor 230. At least a part of the first region functions as a channel formation region of the transistor 200A. That is, the channel formation region of the transistor 200A is located in a region of the oxide semiconductor 230 between the conductor 220 and the conductor 240. It can also be said that the channel formation region of the transistor 200A is located in a region of the oxide semiconductor 230 that is in contact with the insulator 280 or in a region in the vicinity of the insulator 280.
  • FIG. 10D shows a cross-sectional view in the XY plane including the insulator 280.
  • the insulator 280 contacts the entire outer periphery of the oxide semiconductor 230. Therefore, the channel formation region of the transistor 200A can be formed on the entire outer periphery of the portion of the oxide semiconductor 230 that is formed in the same layer as the insulator 280.
  • FIG. 10D can also be said to be a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor 230.
  • the channel length of the transistor 200A is the distance between the source region and the drain region. In other words, it can be said that the channel length of the transistor 200A is determined by the thickness of the insulator 280 on the conductor 220.
  • the channel length L of the transistor 200A is indicated by a dashed double-headed arrow.
  • the channel length L is the distance between the end of the region where the oxide semiconductor 230 and the conductor 220 contact each other and the end of the region where the oxide semiconductor 230 and the conductor 240 contact each other in a cross-sectional view.
  • the channel length L corresponds to the length of the side surface of the insulator 280 on the opening 290 side in a cross-sectional view.
  • the channel length is limited by the exposure limit of photolithography, making further miniaturization difficult, but in the present invention, the channel length can be set by the film thickness of the insulator 280. Therefore, the channel length of the transistor 200A can be made into a very fine structure below the exposure limit of photolithography (for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more). This increases the on-current of the transistor 200A, improving the frequency characteristics.
  • the exposure limit of photolithography for example, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, 20 nm or less, or 10 nm or less, and 0.1 nm or more, 1 nm or more, or 5 nm or more.
  • a channel formation region, a source region, and a drain region can be formed in the opening 290.
  • the semiconductor device of one embodiment of the present invention is used in a memory device, the memory capacity per unit area can be increased.
  • the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 are arranged concentrically. Therefore, the side surface of the conductor 260 arranged at the center faces the side surface of the oxide semiconductor 230 through the insulators 251 and 252. That is, in a plan view, the entire circumference of the oxide semiconductor 230 becomes a channel formation region.
  • the channel width of the transistor 200A is determined by the outer periphery length of the oxide semiconductor 230. That is, it can be said that the channel width of the transistor 200A is determined by the maximum width of the opening 290 (maximum diameter when the opening 290 is circular in a plan view). In FIGS.
  • the maximum width D of the opening 290 is indicated by a double-headed arrow of a two-dot chain line.
  • the channel width W of the transistor 200A is indicated by a double-dot chain line arrow.
  • the maximum width D of the opening 290 is set by the exposure limit of photolithography.
  • the maximum width D of the opening 290 is set by the film thickness of each of the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 provided in the opening 290.
  • the maximum width D of the opening 290 is, for example, 5 nm or more, 10 nm or more, or 20 nm or more, and is preferably 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular in plan view, the maximum width D of the opening 290 corresponds to the diameter of the opening 290, and the channel width W can be calculated as "D x ⁇ ".
  • the channel length L of the transistor 200A is preferably at least smaller than the channel width W of the transistor 200A.
  • the channel length L of the transistor 200A according to one embodiment of the present invention is 0.1 to 0.99 times, preferably 0.5 to 0.8 times, the channel width W of the transistor 200A. With such a configuration, a transistor having good electrical characteristics and high reliability can be realized.
  • the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 are arranged concentrically. This makes the distance between the conductor 260 and the oxide semiconductor 230 approximately uniform, so that a gate electric field can be applied to the oxide semiconductor 230 approximately uniformly.
  • the opening 290 may be approximately circular, such as an ellipse, polygonal, such as a rectangle, or polygonal, such as a rectangle, with rounded corners, in plan view.
  • the maximum width of the opening 290 may be calculated appropriately according to the shape of the top of the opening 290. For example, if the opening is rectangular in plan view, the maximum width of the opening 290 may be the length of the diagonal line at the top of the opening 290.
  • the metal oxides described in the [Metal Oxides] section below can be used in a single layer or a stacked layer.
  • the composition in the vicinity includes a range of ⁇ 30% of the desired atomic ratio. It is also preferable to use gallium as the element M.
  • the oxide semiconductor 230 may not contain the element M.
  • the metal oxide used as the oxide semiconductor 230 may be an In-Zn oxide.
  • indium oxide may be used as the oxide semiconductor 230.
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • EDX energy dispersive X-ray spectroscopy
  • XPS X-ray photoelectron spectroscopy
  • ICP-MS inductively coupled plasma mass spectrometry
  • ICP-AES inductively coupled plasma-atomic emission spectrometry
  • the actual content may differ from the content obtained by analysis due to the influence of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.
  • the metal oxide can be formed preferably by sputtering or atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the composition of the formed metal oxide may differ from the composition of the sputtering target.
  • the zinc content in the formed metal oxide may decrease to about 50% compared to the sputtering target.
  • Examples of the ALD method include the Thermal ALD method, in which the reaction between the precursor and reactant is carried out using only thermal energy, and the Plasma Enhanced ALD (PEALD) method, in which a plasma-excited reactant is used.
  • Thermal ALD method in which the reaction between the precursor and reactant is carried out using only thermal energy
  • PEALD Plasma Enhanced ALD
  • the ALD method can deposit atoms one layer at a time, and therefore has the following advantages: extremely thin films can be formed; films can be formed on structures with high aspect ratios or surfaces with large steps; films can be formed with few defects such as pinholes; films can be formed with excellent coverage; and films can be formed at low temperatures.
  • the PEALD method may be preferable because it can form films at lower temperatures by using plasma.
  • some precursors used in the ALD method contain elements such as carbon or chlorine.
  • films formed by the ALD method may contain more elements such as carbon or chlorine than films formed by other film formation methods. Note that the quantification of these elements can be performed using XPS or SIMS.
  • the metal oxide film formation method of one embodiment of the present invention uses the ALD method, but adopts one or both of the conditions of a high substrate temperature during film formation and the implementation of an impurity removal process, and therefore the amount of carbon and chlorine contained in the film may be smaller than when the ALD method is used without applying these.
  • the ALD method is a film formation method in which a film is formed by a reaction on the surface of a workpiece, unlike a film formation method in which particles released from a target are deposited. Therefore, it is a film formation method that is not easily affected by the shape of the workpiece and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow film formation speed, it may be preferable to use it in combination with other film formation methods such as a sputtering method or a CVD method, which have a fast film formation speed.
  • the metal oxide has a layered structure of a first metal oxide and a second metal oxide
  • a method of forming a film of the first metal oxide using a sputtering method and forming a film of the second metal oxide on the first metal oxide using an ALD method can be mentioned.
  • the first metal oxide has a crystal part
  • the second metal oxide may grow as a crystal with the crystal part as a nucleus.
  • the ALD method can control the composition of the film obtained by adjusting the amount of raw material gas introduced.
  • the ALD method can form a film of any composition by adjusting the amount of raw material gas introduced, the number of introductions (also called the number of pulses), the time required for one pulse (also called the pulse time), etc.
  • the ALD method can form a film whose composition changes continuously by changing the raw material gas while forming the film.
  • the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation and pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.
  • the method for forming the oxide semiconductor film that becomes the oxide semiconductor 230 is not particularly limited.
  • the oxide semiconductor film may be formed using a CVD method, an MBE method, a PLD method, or the like.
  • the oxide semiconductor 230 preferably has crystallinity.
  • oxide semiconductors having crystallinity include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductor, single crystal oxide semiconductor, and the like. It is preferable to use CAAC-OS or nc-OS as the oxide semiconductor 230, and it is particularly preferable to use CAAC-OS.
  • the CAAC-OS preferably has multiple layered crystal regions with the c-axis oriented in the normal direction to the surface on which it is formed.
  • the oxide semiconductor 230 preferably has layered crystals that are approximately parallel to the sidewall of the opening 290, particularly to the side surface of the insulator 280. With this structure, the layered crystals of the oxide semiconductor 230 are formed approximately parallel to the channel length direction of the transistor, thereby increasing the on-state current of the transistor.
  • CAAC-OS is a metal oxide that has a highly crystalline and dense structure and has few impurities and defects (e.g., oxygen vacancies).
  • a temperature e.g. 400° C. or higher and 600° C. or lower
  • the CAAC-OS can be made to have a more crystalline and dense structure. In this way, the density of the CAAC-OS can be further increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.
  • the oxide semiconductor 230 by using a crystalline oxide such as CAAC-OS as the oxide semiconductor 230, it is possible to suppress the extraction of oxygen from the oxide semiconductor 230 by the source electrode or the drain electrode. As a result, even when heat treatment is performed, oxygen can be suppressed from being extracted from the oxide semiconductor 230, and the transistor is stable against high temperatures (so-called thermal budget) in the manufacturing process.
  • a crystalline oxide such as CAAC-OS
  • the crystallinity of the oxide semiconductor 230 can be analyzed, for example, by X-ray diffraction (XRD), a transmission electron microscope (TEM), or electron diffraction (ED). Alternatively, the analysis may be performed by combining a plurality of these techniques.
  • XRD X-ray diffraction
  • TEM transmission electron microscope
  • ED electron diffraction
  • the oxide semiconductor 230 and the conductor 220 come into contact with each other, a metal compound or oxygen vacancy is formed, and the second region of the oxide semiconductor 230 becomes low in resistance.
  • the contact resistance between the oxide semiconductor 230 and the conductor 220 becomes low, and thus the contact resistance between the oxide semiconductor 230 and the conductor 220 can be reduced.
  • the oxide semiconductor 230 and the conductor 240 come into contact with each other, the third region of the oxide semiconductor 230 becomes low in resistance. Therefore, the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced.
  • the oxide semiconductor 230 may have a laminated structure of multiple oxide layers with different chemical compositions.
  • the oxide semiconductor 230 may have a structure in which multiple types of metal oxides selected from those described in the [Metal Oxide] section below are appropriately laminated.
  • the oxide semiconductor 230 may have a layered structure of an oxide semiconductor 230a and an oxide semiconductor 230b on the oxide semiconductor 230a.
  • the conductivity of the material used for oxide semiconductor 230a is preferably different from the conductivity of the material used for oxide semiconductor 230b.
  • the oxide semiconductor 230a can be made of a material having a higher conductivity than the oxide semiconductor 230b.
  • a material having a high conductivity for the oxide semiconductor 230a in contact with the conductor 220 and the conductor 240 that function as a source electrode or a drain electrode the contact resistance between the oxide semiconductor 230 and the conductor 220 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, and a transistor with a large on-state current can be obtained.
  • the threshold voltage of the transistor may shift, and the drain current (hereinafter also referred to as cutoff current) that flows when the gate voltage is 0 V may become large.
  • the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230a for the oxide semiconductor 230b.
  • the transistor 200A is an n-channel transistor, the threshold voltage can be increased, and the transistor can have a small cutoff current. Note that a small cutoff current may be referred to as a normally-off transistor.
  • the oxide semiconductor 230 As described above, by forming the oxide semiconductor 230 into a stacked structure and using a material having a higher conductivity than the oxide semiconductor 230b for the oxide semiconductor 230a, a transistor that is normally off and has a large on-state current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.
  • the carrier concentration of the oxide semiconductor 230a is preferably higher than that of the oxide semiconductor 230b. Increasing the carrier concentration of the oxide semiconductor 230a increases the conductivity, and the contact resistance between the oxide semiconductor 230 and the conductor 220 and the contact resistance between the oxide semiconductor 230 and the conductor 240 can be reduced, resulting in a transistor with a large on-state current. Reducing the carrier concentration of the oxide semiconductor 230b decreases the conductivity, resulting in a normally-off transistor.
  • the oxide semiconductor 230a is made of a material having a higher conductivity than the oxide semiconductor 230b, but the present invention is not limited to this.
  • the oxide semiconductor 230a may be made of a material having a lower conductivity than the oxide semiconductor 230b.
  • a configuration can be made in which the carrier concentration of the oxide semiconductor 230a is lower than the carrier concentration of the oxide semiconductor 230b.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a is preferably different from the band gap of the second metal oxide used in the oxide semiconductor 230b.
  • the difference between the band gap of the first metal oxide and the band gap of the second metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b. This can reduce the contact resistance between the oxide semiconductor 230 and the conductor 220 and the contact resistance between the oxide semiconductor 230 and the conductor 240, and can provide a transistor with a large on-state current.
  • the transistor 200A is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • the band gap of the first metal oxide is smaller than the band gap of the second metal oxide, but the present invention is not limited to this.
  • the band gap of the first metal oxide can be larger than the band gap of the second metal oxide.
  • the band gap of the first metal oxide used in the oxide semiconductor 230a can be smaller than the band gap of the second metal oxide used in the oxide semiconductor 230b.
  • the composition of the first metal oxide is preferably different from the composition of the second metal oxide.
  • the band gap can be controlled.
  • the content of element M in the first metal oxide is preferably lower than the content of element M in the second metal oxide.
  • the first metal oxide and the second metal oxide are In-M-Zn oxides
  • the first metal oxide may not contain the element M.
  • the first metal oxide used in the oxide semiconductor 230a may be an In-Zn oxide
  • the second metal oxide used in the oxide semiconductor 230b may be an In-M-Zn oxide.
  • the first metal oxide may be an In-Zn oxide
  • the second metal oxide may be an In-Ga-Zn oxide.
  • the content of element M in the first metal oxide is lower than the content of element M in the second metal oxide, but one embodiment of the present invention is not limited to this.
  • the content of element M in the first metal oxide may be higher than the content of element M in the second metal oxide. Note that it is sufficient that the first metal oxide and the second metal oxide have different compositions, and the contents of elements other than element M may be different.
  • the thickness of the oxide semiconductor 230 is preferably 1 nm or more, 3 nm or more, or 5 nm or more, and 20 nm or less, 15 nm or less, 12 nm or less, or 10 nm or less.
  • each layer (here, oxide semiconductor 230a and oxide semiconductor 230b) constituting the oxide semiconductor 230 may be determined so that the thickness of the oxide semiconductor 230 falls within the above-mentioned range.
  • the thickness of the oxide semiconductor 230a can be determined so that the contact resistance between the oxide semiconductor 230a and the conductor 220 and the contact resistance between the oxide semiconductor 230a and the conductor 240 fall within the required range.
  • the thickness of the oxide semiconductor 230b can be determined so that the threshold voltage of the transistor falls within the required range. Note that the thickness of the oxide semiconductor 230a may be the same as or different from the thickness of the oxide semiconductor 230b.
  • the oxide semiconductor 230a and the oxide semiconductor 230b may have a different ratio of the film thickness at the portion where the top surface of the conductor 240 is to be formed to the film thickness at the portion where the side surface of the conductor 240 and the side surface of the insulator 280 are to be formed.
  • the oxide semiconductor 230 has a two-layer structure of an oxide semiconductor 230a and an oxide semiconductor 230b, but the present invention is not limited to this.
  • the oxide semiconductor 230 may have a three or more layer structure.
  • the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a, an oxide semiconductor 230b on the oxide semiconductor 230a, and an oxide semiconductor 230c on the oxide semiconductor 230b.
  • an oxide semiconductor 230c may be provided between the conductor 260 and the oxide semiconductor 230b.
  • the atomic ratio of element M to In is preferably greater than the atomic ratio of element M to In in the metal oxide used for the oxide semiconductor 230b.
  • the insulator 280 has a function of suppressing the diffusion of hydrogen and oxygen, and therefore the oxide semiconductor 230a may not be provided.
  • the oxide semiconductor 230 may have a stacked structure of the oxide semiconductor 230b and the oxide semiconductor 230c on the oxide semiconductor 230b.
  • the oxide semiconductor 230a may not be provided.
  • the oxide semiconductor film that becomes the oxide semiconductor 230b is formed using an ALD method or a CVD method
  • the oxide semiconductor 230a may not be provided.
  • damage to the insulator 280 is reduced and the diffusion of elements contained in the insulator 280 into the oxide semiconductor film can be suppressed.
  • the threshold voltage of the transistor 200A may shift and the cutoff current may become large. Specifically, when the transistor 200A is an n-channel transistor, the threshold voltage may become low. Therefore, it is preferable to use a material with lower conductivity than the oxide semiconductor 230b for the oxide semiconductor 230c. As a result, when the transistor 200A is an n-channel transistor, the threshold voltage can be increased and the transistor can have a small cutoff current.
  • the oxide semiconductor 230b As described above, by using a material having a higher conductivity than the oxide semiconductor 230c as the oxide semiconductor 230b, a normally-off transistor with a large on-state current can be obtained. Therefore, a semiconductor device that achieves both low power consumption and high performance can be obtained.
  • the carrier concentration of the oxide semiconductor 230b is preferably higher than that of the oxide semiconductor 230c.
  • the conductivity is increased, and a transistor with a large on-state current can be obtained.
  • the conductivity is decreased, and a normally-off transistor can be obtained.
  • the oxide semiconductor 230b is made of a material having a higher conductivity than the oxide semiconductor 230c; however, one embodiment of the present invention is not limited to this.
  • the oxide semiconductor 230b may be made of a material having a lower conductivity than the oxide semiconductor 230c.
  • the carrier concentration of the oxide semiconductor 230b may be lower than the carrier concentration of the oxide semiconductor 230c.
  • the band gap of the second metal oxide used in the oxide semiconductor 230b is preferably different from the band gap of the third metal oxide used in the oxide semiconductor 230c.
  • the difference between the band gap of the second metal oxide and the band gap of the third metal oxide is preferably 0.1 eV or more, more preferably 0.2 eV or more, and even more preferably 0.3 eV or more.
  • the band gap of the second metal oxide used in the oxide semiconductor 230b can be smaller than the band gap of the third metal oxide used in the oxide semiconductor 230c.
  • a transistor with a large on-state current can be obtained.
  • the transistor 200A is an n-channel transistor, the threshold voltage can be increased, and the transistor can be a normally-off transistor.
  • the band gap of the second metal oxide is smaller than the band gap of the third metal oxide, but one embodiment of the present invention is not limited to this.
  • the band gap of the second metal oxide may be larger than the band gap of the third metal oxide.
  • the first metal oxide used in the oxide semiconductor 230a and the third metal oxide used in the oxide semiconductor 230c may have the same composition or different compositions.
  • the insulator 251 is preferably an insulator having a function of capturing or fixing hydrogen.
  • hydrogen contained in the oxide semiconductor 230 can be captured or fixed more effectively.
  • the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • hafnium oxide, an oxide containing hafnium and silicon, or aluminum oxide may be used as the insulator 251.
  • the insulator 251 may have an amorphous structure. Note that the insulators described in the [Insulator] section below may be used as the insulator 251 in a single layer or a stacked layer.
  • the insulator 252 contains at least nitrogen and silicon. Note that the insulator 252 may be a single layer or a stack of insulators described in the [Insulator] section below.
  • the thickness of the insulator 251 is preferably within the range of the width of the insulator 51 in the B1-B2 direction as described in embodiment 1.
  • the thickness of the insulator 252 is preferably within the range of the width of the insulator 52 in the B1-B2 direction as described in embodiment 1.
  • the conductor 260 may be a single layer or a multilayer of the conductors described in the section [Conductor] below.
  • the conductor 260 may be a highly conductive material such as tungsten.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen as the conductor 260.
  • conductive materials include conductive materials that contain nitrogen (e.g., titanium nitride or tantalum nitride) and conductive materials that contain oxygen (e.g., ruthenium oxide). This makes it possible to suppress a decrease in the conductivity of the conductor 260.
  • the conductor 260 may have a laminated structure.
  • the conductor 260 may have a laminated structure of a conductor 260a and a conductor 260b on the conductor 260a.
  • titanium nitride may be used as the conductor 260a
  • tungsten may be used as the conductor 260b.
  • the conductor 260 is shown as having a two-layer laminate structure of conductor 260a and conductor 260b, but the present invention is not limited to this.
  • the conductor 260 may also have a laminate structure of three or more layers.
  • the conductors described in the section [Conductor] below can be used in a single layer or multilayer.
  • the conductor 220 it is preferable to use a conductive material that is difficult to oxidize, or a conductive material that has the function of suppressing the diffusion of oxygen.
  • titanium nitride or tantalum nitride can be used.
  • the conductor 220 since the conductor 220 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen described in the section on [Conductor] described later. By using a conductive material containing oxygen as the conductor 220, the conductor 220 can maintain its conductivity even if it absorbs oxygen. In addition, even when an insulator containing oxygen such as hafnium oxide is used as the insulator 210, the conductor 220 is preferable because it can maintain its conductivity.
  • indium tin oxide also referred to as ITO
  • indium tin oxide with added silicon also referred to as ITSO
  • indium zinc oxide also referred to as IZO (registered trademark)
  • ITO indium tin oxide
  • ITSO indium tin oxide with added silicon
  • IZO indium zinc oxide
  • the conductor 220 may have a laminated structure.
  • the conductor 220 may have a laminated structure of a conductor 220a and a conductor 220b on the conductor 220a.
  • titanium nitride may be used as the conductor 220a
  • tantalum nitride may be used as the conductor 220b.
  • the titanium nitride is in contact with the insulator 210
  • the tantalum nitride is in contact with the oxide semiconductor 230.
  • an oxide insulator is used for the insulator 210
  • titanium nitride may be used as the conductor 220a
  • tungsten may be used as the conductor 220b.
  • the conductor 220 may have a three or more layered structure in which a conductor containing a highly conductive material is sandwiched between conductors containing a metal element different from the conductor.
  • a conductor containing a highly conductive material is sandwiched between conductors containing a metal element different from the conductor.
  • a conductive material containing tungsten, copper, or aluminum as a main component may be used as a highly conductive material.
  • the conductor 220 has a structure in which titanium nitride, tungsten on titanium nitride, and indium tin oxide with added silicon on tungsten are stacked.
  • FIG. 10B and 10C show a configuration in which the upper surface of the conductor 220 is flat, but the present invention is not limited to this.
  • a configuration may be used in which a recess overlapping the opening 290 is formed on the upper surface of the conductor 220.
  • the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 so as to fill the recess, it is possible to easily apply the gate electric field of the conductor 260 up to the vicinity of the conductor 220 of the oxide semiconductor 230.
  • the contact area between the oxide semiconductor 230 and the conductor 220 can be increased, and the contact resistance between the oxide semiconductor 230 and the conductor 220 can be reduced. Therefore, the on-current of the transistor 200A can be improved.
  • the conductors described in the section [Conductor] below can be used in a single layer or a laminated layer.
  • ruthenium is a material that has good contact resistance with the oxide semiconductor 230, and therefore can be preferably used.
  • the oxide of ruthenium also has conductivity, it has good conductivity even when the surface is oxidized during the manufacturing process, and therefore can be preferably used.
  • a conductive material with high conductivity such as tungsten, may be used as the conductor 240.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen may be used as the conductor 240.
  • a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen may be used as the conductor 240.
  • titanium nitride or tantalum nitride may be used. With such a configuration, it is possible to suppress excessive oxidation of the conductor 240 by the oxide semiconductor 230.
  • the conductor 240 may have a laminated structure.
  • the conductor 240 may have a laminated structure of a conductor 240a and a conductor 240b on the conductor 240a.
  • ruthenium may be used as the conductor 240a
  • titanium nitride or tantalum nitride may be used as the conductor 240b.
  • the sheet resistance of the oxide semiconductor 230 in the region in contact with the layer may be reduced.
  • the carrier concentration may be increased. Therefore, the resistance of the oxide semiconductor 230 in the region in contact with the conductor 240 can be reduced in a self-aligned manner. Therefore, a transistor with a large on-current can be obtained.
  • ruthenium may be used as the conductor 240a
  • indium zinc oxide may be used as the conductor 240b.
  • the sheet resistance of the oxide semiconductor 230 in the region in contact with the layer may be reduced.
  • the carrier concentration may be increased. Therefore, the resistance of the oxide semiconductor 230 in the region in contact with the conductor 240 can be reduced in a self-aligned manner. Therefore, a transistor with a large on-current can be obtained.
  • titanium nitride or tantalum nitride may be used as the conductor 240a, and tungsten may be used as the conductor 240b.
  • tungsten may be used as the conductor 240b.
  • the conductor 240a may be formed using a conductive material with high conductivity
  • the conductor 240b may be formed using a conductive material containing oxygen.
  • a conductive material containing oxygen as the conductor 240b in contact with the insulator 251, it is possible to prevent the oxygen in the insulator 251 from diffusing into the conductor 240a.
  • the insulator 210 preferably has a low dielectric constant because it functions as an interlayer film. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance between wirings can be reduced.
  • a single layer or a stack of insulators containing a material with a low dielectric constant, as described in the [Insulator] section below, can be used. Silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • the concentration of impurities such as water and hydrogen in the insulator 210 is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 230.
  • the insulator 280 is preferably a barrier insulator against hydrogen. With such a structure, the diffusion of hydrogen into the oxide semiconductor 230 can be suppressed. In addition, the concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 230. Note that the insulator 280 may be a single layer or a stack of insulators described in the [Insulator] section described later.
  • the insulator 283 is preferably a barrier insulator against hydrogen. This can prevent hydrogen from diffusing from above the insulator 283 to the oxide semiconductor 230.
  • a silicon nitride film and a silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulator 283.
  • the insulator 283 It is particularly preferable to use silicon nitride deposited by a sputtering method as the insulator 283.
  • the insulator 283 contains silicon and nitrogen.
  • the sputtering method does not require the use of molecules containing hydrogen in the deposition gas, so the hydrogen concentration in the insulator 283 can be reduced.
  • silicon nitride with high density can be formed.
  • an insulator having a function of capturing hydrogen or fixing hydrogen may be used as the insulator 283.
  • diffusion of hydrogen from above the insulator 283 to the oxide semiconductor 230 can be suppressed, and further hydrogen contained in the oxide semiconductor 230 can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • magnesium oxide, aluminum oxide, hafnium oxide, an oxide containing hafnium and silicon, or the like can be used.
  • the insulator 283 may also have a laminated structure of an insulator that has the function of capturing or fixing hydrogen, and a barrier insulator against hydrogen.
  • the insulator 283 may be a laminated film of aluminum oxide and silicon nitride on the aluminum oxide.
  • 10A to 10D show a configuration in which the insulator 280 and the oxide semiconductor 230 are in contact with each other at the opening 290, but the present invention is not limited to this.
  • an insulator having a function of capturing or fixing hydrogen may be provided between the insulator 280 and the oxide semiconductor 230.
  • Figures 12A to 12D show another example of a semiconductor device according to an embodiment of the present invention.
  • Figure 12A is a plan view of the semiconductor device.
  • Figures 12B to 12D are cross-sectional views of the semiconductor device.
  • Figure 12B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 12A.
  • Figure 12C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 12A.
  • Figure 12D is a cross-sectional view in the XY plane including the insulator 280. Note that some elements are omitted from the plan view of Figure 12A for clarity.
  • the semiconductor device shown in Figures 12A to 12D differs from the semiconductor device shown in Figures 10A to 10D in that it has an insulator 222.
  • differences from the contents explained using Figures 10A to 10D will be mainly explained, and overlapping parts will be referred to and explanations may be omitted.
  • the insulator 222 is provided between the insulator 280 and the oxide semiconductor 230.
  • the portions of the insulator 222, the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290.
  • the insulator 222 is provided to cover the sidewall of the opening 290
  • the oxide semiconductor 230 is provided to cover the side surface of the insulator 222 and the bottom of the opening 290
  • the insulator 251 is provided to cover the oxide semiconductor 230
  • the insulator 252 is provided to cover the insulator 251
  • the conductor 260 is provided to fill the recess of the insulator 252 that reflects the shape of the opening 290.
  • the semiconductor device shown in FIG. 12A to 12D has the structure described with reference to FIG. 4E and FIG. 4F. Therefore, the oxide semiconductor 230, the insulator 280, the insulator 222, the insulator 251, the insulator 252, and the conductor 260 in the configurations shown in FIG. 12A to 12D correspond to the oxide semiconductor 30, the insulator 21, the insulator 22, the insulator 51, the insulator 52, and the conductor 60 in the configurations shown in FIG. 4E and FIG. 4F described in embodiment 1, respectively.
  • the insulator 222 is preferably an insulator having a function of capturing or fixing hydrogen.
  • An insulator applicable to the insulator 22 described in embodiment 1 can be used as the insulator 222.
  • This allows a structure in which the oxide semiconductor 230 is sandwiched between insulators (here, the insulator 251 and the insulator 222) having a function of capturing or fixing hydrogen, and a barrier insulator against hydrogen (here, the insulator 280) is provided on the outside. With this structure, diffusion of hydrogen into the oxide semiconductor 230 can be suppressed, and the hydrogen concentration in the oxide semiconductor 230 can be further reduced.
  • the thickness of the insulator 222 is preferably within the range of the width of the insulator 51 in the B1-B2 direction as described in embodiment 1.
  • 12B to 12D show a configuration in which the insulator 222 is provided between the insulator 280 and the oxide semiconductor 230. Note that the present invention is not limited to this as long as the insulator 222 is provided in contact with the oxide semiconductor 230 or in the vicinity of the oxide semiconductor 230.
  • Figures 13A to 13D show another example of a semiconductor device according to one embodiment of the present invention.
  • Figure 13A is a plan view of the semiconductor device.
  • Figures 13B to 13D are cross-sectional views of the semiconductor device.
  • Figure 13B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 13A.
  • Figure 13C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 13A.
  • Figure 13D is a cross-sectional view in the XY plane including the insulator 280. Note that some elements are omitted from the plan view of Figure 13A for clarity.
  • the semiconductor device shown in Figures 13A to 13D differs from the semiconductor device shown in Figures 12A to 12D in that the insulator 222 is disposed below the insulator 280 and the conductor 220.
  • the semiconductor device shown in Figures 13A to 13D also differs from the semiconductor device shown in Figures 10A to 10D in that the insulator 222 is provided between the insulator 210 and the insulator 280 and the conductor 220.
  • the differences from the contents explained using Figures 10A to 10D or Figures 12A to 12D will be mainly explained, and the overlapping parts will be referred to and explanations may be omitted.
  • the insulator 222 is provided on the insulator 210, below the insulator 280 and the conductor 220.
  • the insulator 222 is provided on the insulator 210, and the conductor 220 and the insulator 280 are provided on the insulator 222.
  • hydrogen in the oxide semiconductor 230 can diffuse to the insulator 222 via the conductor 220 and can be captured or fixed. Therefore, the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • the conductor 240 is shown as a single layer in Figs. 13B and 13C, the present invention is not limited to this.
  • the conductor 240 may have a two-layer laminate structure of conductor 240a and conductor 240b.
  • the conductor 240 may have a laminate structure of three or more layers.
  • 12B to 12D show a configuration in which the insulator 222 is provided between the insulator 280 and the oxide semiconductor 230, but the present invention is not limited to this.
  • an insulator having a function of capturing or fixing hydrogen and a barrier insulator against hydrogen may be provided between the insulator 280 and the oxide semiconductor 230.
  • Figures 15A to 15D show another example of a semiconductor device according to an embodiment of the present invention.
  • Figure 15A is a plan view of the semiconductor device.
  • Figures 15B to 15D are cross-sectional views of the semiconductor device.
  • Figure 15B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 15A.
  • Figure 15C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 15A.
  • Figure 15D is a cross-sectional view in the XY plane including the insulator 280. Note that some elements are omitted from the plan view of Figure 15A for clarity.
  • the semiconductor device shown in Figures 15A to 15D differs from the semiconductor device shown in Figures 12A to 12D in that it has an insulator 221. Also, the semiconductor device shown in Figures 15A to 15D differs from the semiconductor device shown in Figures 10A to 10D in that it has an insulator 221 and an insulator 222.
  • the differences from the contents explained using Figures 10A to 10D or Figures 12A to 12D will be mainly explained, and the overlapping parts will be referred to and explanations may be omitted.
  • the insulator 221 is provided between the insulator 280 and the insulator 222.
  • the portions of the insulator 221, the insulator 222, the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290.
  • the insulator 221 is provided to cover the side wall of the opening 290
  • the insulator 222 is provided to cover the side surface of the insulator 221
  • the oxide semiconductor 230 is provided to cover the side surface of the insulator 222 and the bottom of the opening 290
  • the insulator 251 is provided to cover the oxide semiconductor 230
  • the insulator 252 is provided to cover the insulator 251
  • the conductor 260 is provided to fill the recess of the insulator 252 that reflects the shape of the opening 290.
  • the insulator 221 is preferably a barrier insulator against hydrogen. This allows a structure in which the oxide semiconductor 230 is sandwiched between insulators (here, the insulator 251 and the insulator 222) that have a function of capturing or fixing hydrogen, and a barrier insulator against hydrogen (here, the insulator 221) is provided on the outside. With this structure, diffusion of hydrogen into the oxide semiconductor 230 can be suppressed, and the hydrogen concentration in the oxide semiconductor 230 can be further reduced.
  • the thickness of the insulator 221 is preferably within the range of the width of the insulator 52 in the B1-B2 direction as described in embodiment 1.
  • silicon nitride As the insulator 221.
  • silicon nitride that can be used for the insulator 221 also has barrier properties against oxygen.
  • the insulator 221 contacts the side surface of the conductor 240 at the opening 290. Therefore, by using silicon nitride for the insulator 221 that contacts the conductor 240, oxidation of the conductor 240 can be suppressed.
  • the material used for the insulator 280 is not limited to the material applicable to the insulator 21 described in embodiment 1.
  • the insulator 280 may be formed using a material with a low relative dielectric constant. By forming the insulator 280 using a material with a low relative dielectric constant, the insulator 280 can function as an interlayer film. Therefore, the parasitic capacitance generated between the wirings can be reduced.
  • the semiconductor device shown in Figures 15A to 15D has the structure described with reference to Figures 5A and 5B.
  • the oxide semiconductor 230, the insulator 280, the insulator 221, the insulator 222, the insulator 251, the insulator 252, and the conductor 260 correspond to the oxide semiconductor 30, the insulator 24, the insulator 21, the insulator 22, the insulator 51, the insulator 52, and the conductor 60 in the configurations shown in Figures 5A and 5B described in embodiment 1, respectively.
  • Insulator 280 is shown as a single layer in Figures 15B and 15C, but the present invention is not limited to this. Insulator 280 may have a laminated structure.
  • Figures 16A to 16D show another example of a semiconductor device according to one embodiment of the present invention.
  • Figure 16A is a plan view of the semiconductor device.
  • Figures 16B to 16D are cross-sectional views of the semiconductor device.
  • Figure 16B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 16A.
  • Figure 16C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 16A. Note that in the plan view of Figure 16A, some elements have been omitted for clarity.
  • the insulator 280 may have a layered structure of an insulator 280a, an insulator 280b on the insulator 280a, and an insulator 280c on the insulator 280b.
  • Figure 16D is a cross-sectional view in the XY plane including the insulator 280b.
  • the insulator 280a has a region in contact with the upper surface of the insulator 210, a region in contact with the side surface of the conductor 220, and a region in contact with the upper surface of the conductor 220.
  • the insulator 280c has a region in contact with the lower surface of the conductor 240.
  • the insulator 280b may be formed using, for example, a material with a low dielectric constant.
  • a material with a low dielectric constant By forming the insulator 280b using a material with a low dielectric constant, the parasitic capacitance generated between wirings can be reduced.
  • silicon oxide or silicon oxynitride can be used as the insulator 280b.
  • insulator 280b When an insulator containing oxygen is used as insulator 280b, it is preferable to use a barrier insulator against oxygen, as described in the [Insulator] section below, for insulators 280a and 280c.
  • insulator 280a between insulator 280b and conductor 220, it is possible to prevent conductor 220 from being oxidized and the resistance of conductor 220 from increasing.
  • insulator 280c between insulator 280b and conductor 240, it is possible to prevent conductor 240 from being oxidized and the resistance of conductor 240 from increasing.
  • the insulator 280a and the insulator 280c may each be a barrier insulator against hydrogen, as described in the [Insulator] section below. This allows the insulator 280b to be surrounded by barrier insulators against hydrogen (here, the insulator 280a, the insulator 280c, and the insulator 221). This can suppress the diffusion of hydrogen contained in the insulator 280b to the oxide semiconductor 230.
  • the silicon nitride film and the silicon nitride oxide film each have the characteristics of releasing little impurities (e.g., water and hydrogen) from themselves and being difficult for oxygen and hydrogen to permeate, and therefore can be suitably used for the insulator 280a and the insulator 280c. Note that the insulator 280a and the insulator 280c may be made of the same material or different materials.
  • the insulator 280a may be an insulator having a function of capturing or fixing hydrogen. With such a structure, it is possible to suppress diffusion of hydrogen from below the insulator 280a to the oxide semiconductor 230, and further to capture or fix hydrogen contained in the oxide semiconductor 230. Thus, the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • the insulator 280a may be made of magnesium oxide, aluminum oxide, hafnium oxide, or an oxide containing hafnium and silicon.
  • the insulator 280a may be made of a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.
  • the insulator 280c may be made of an insulator having a function of capturing or fixing hydrogen.
  • silicon nitride can be used for the insulators 280a and 280c
  • silicon oxide can be used for the insulator 280b.
  • each of the insulators 280a and 280c contains at least silicon and nitrogen.
  • the insulator 280b contains at least silicon and oxygen.
  • the insulator 280c may be formed without performing planarization treatment on the insulator 280b. By not performing planarization treatment, the manufacturing cost can be reduced and the production yield can be increased.
  • the insulators 280a, 280b, and 280c can be formed successively without exposure to the atmospheric environment.
  • the insulators 280a to 280c By forming the insulators 280a to 280c without exposing them to the atmospheric environment, it is possible to prevent impurities or moisture from the atmospheric environment from adhering to the insulators 280a to 280c, and it is possible to keep the vicinity of the interface between the insulators 280a and 280b and the vicinity of the interface between the insulators 280b and 280c clean.
  • Figures 16B and 16C show a configuration in which the insulator 280 has a three-layer laminated structure, the present invention is not limited to this.
  • the insulator 280 may have a two-layer or four or more layer laminated structure.
  • an insulator 251 having a function of capturing or fixing hydrogen is provided in contact with the oxide semiconductor 230. Therefore, when the insulators 280a, 280c, and 252 have barrier properties against hydrogen and the hydrogen concentration in the insulator 280b is sufficiently reduced, it may not be necessary to provide the insulators 221 and 222, as shown in FIG. 17A.
  • the insulator 280b is in contact with at least a portion of the oxide semiconductor 230.
  • the insulator 280b is preferably an insulator containing oxygen.
  • the insulator 280b preferably has a region with a higher oxygen content than at least one of the insulators 280a and 280c.
  • the insulator 280b preferably has a region with a higher oxygen content than each of the insulators 280a and 280c. Increasing the oxygen content of the insulator 280b makes it easier to form an i-type region in the oxide semiconductor 230 near the insulator 280b.
  • oxygen can be supplied to the oxide semiconductor 230.
  • oxygen is supplied from the insulator 280b to the oxide semiconductor 230, particularly to the channel formation region of the oxide semiconductor 230, oxygen vacancies and VOH in the oxide semiconductor 230 can be reduced, and the transistor can have favorable electrical characteristics and high reliability.
  • the amount of released oxygen molecules from the insulator 280b is preferably equal to or greater than 1.0 ⁇ 10 14 molecules/cm 2 and less than 1.0 ⁇ 10 15 molecules/cm 2.
  • the amount of released oxygen molecules can be measured by thermal desorption spectrometry.
  • the channel length of the transistor 200A is short, the influence of oxygen vacancies in the channel formation region and VOH on the electrical characteristics and reliability is particularly large. Therefore, by sufficiently reducing the hydrogen concentration in the oxide semiconductor 230 and then optimizing the amount of oxygen supplied to the oxide semiconductor 230, a transistor with a short channel length having favorable electrical characteristics and high reliability can be realized.
  • the insulator 280b is preferably formed by a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • a deposition method such as a sputtering method or a plasma enhanced chemical vapor deposition (PECVD) method.
  • PECVD plasma enhanced chemical vapor deposition
  • oxygen supplied to the oxide semiconductor 230 for example, after forming the insulator 280b, heat treatment in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere may be performed.
  • oxygen may be supplied by forming an oxide film in an oxygen atmosphere on the upper surface of the insulator 280b by a sputtering method. The oxide film may then be removed. By performing such a process, oxygen can be supplied to the insulator 280b, and the amount of oxygen supplied to the oxide semiconductor 230 can be increased.
  • the amount of oxygen supplied to the oxide semiconductor 230 is to be reduced, it is preferable to provide one or both of the insulators 221 and 222. With this configuration, even when the amount of oxygen released by the insulator 280b is large, the supply of an excessive amount of oxygen to the oxide semiconductor 230 can be suppressed.
  • the amount of oxygen supplied to the region of the oxide semiconductor 230 that is in contact with the insulator 280a and the region that is in contact with the insulator 280c is smaller than that to the region that is in contact with the insulator 280b. Therefore, the region of the oxide semiconductor 230 that is in contact with the insulator 280a and the region that is in contact with the insulator 280c may have low resistance.
  • the thickness of the insulator 280a the range of the second region that functions as one of the source region and the drain region can be controlled.
  • the thickness of the insulator 280c the range of the third region that functions as the other of the source region and the drain region can be controlled. Therefore, the thicknesses of the insulators 280a and 280c may be appropriately set according to the characteristics required for the transistor 200A.
  • 10B and 10C show a configuration in which an insulator 251 and an insulator 252 are provided between an oxide semiconductor 230 and a conductor 260.
  • the oxide semiconductor 230 has a region in contact with the insulator 251.
  • the insulator 252 is provided between the conductor 260 and the insulator 251. Note that the present invention is not limited to this.
  • an insulator 253 may be provided between the oxide semiconductor 230 and the insulator 251.
  • the insulator 253 is preferably made of a material with a low dielectric constant, as described in the [Insulator] section below. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 253 contains at least oxygen and silicon. This configuration can reduce the parasitic capacitance between the conductor 260 and the conductor 240. It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 253 is reduced.
  • the insulator 252 When the insulator 253 is provided, it is preferable that the insulator 252 also has a barrier property against oxygen.
  • the insulator 252 is provided between the insulator 253 and the conductor 260. Therefore, the oxygen contained in the insulator 253 can be prevented from diffusing into the conductor 260, and oxidation of the conductor 260 can be suppressed. In addition, a decrease in the amount of oxygen supplied to the first region of the oxide semiconductor 230 can be suppressed.
  • an insulator 254 may be further provided between the oxide semiconductor 230 and the insulator 253.
  • the insulator 254 is preferably a barrier insulator against oxygen described in the section [Insulator] below.
  • the insulator 254 has a region in contact with the oxide semiconductor 230.
  • the insulator 254 has a barrier property against oxygen, it is possible to suppress oxygen from being released from the oxide semiconductor 230 during heat treatment or the like. Thus, it is possible to suppress the formation of oxygen vacancies in the oxide semiconductor 230. This can improve the electrical characteristics and reliability of the transistor 200A.
  • aluminum oxide is preferably used as the insulator 254.
  • the insulator 254 contains at least oxygen and aluminum. Note that aluminum oxide has a function of capturing or fixing hydrogen, and is therefore suitable as the insulator 254 in contact with the oxide semiconductor 230.
  • the film thicknesses of the insulators 253 and 254 are each thin.
  • the film thicknesses of the insulators 253 and 254 are each preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. Note that it is sufficient that the insulators 253 and 254 each have a region with the above-mentioned film thickness in at least a portion.
  • the film thicknesses of insulator 254, insulator 253, insulator 251, and insulator 252 are 1 nm, 2 nm, 2 nm, and 1 nm, respectively.
  • the films In order to make the film thickness of the insulators 251 to 254 as thin as described above, it is preferable to form the films by the ALD method. In addition, in order to provide the insulators 251 to 254 inside the opening 290, it is preferable to form the films by the ALD method.
  • FIGS. 10B to 10D show a configuration in which the gate insulator has a two-layer stacked structure of insulators 251 and 252
  • FIG. 17A shows a configuration in which the gate insulator has a three-layer stacked structure of insulators 251 to 253
  • FIG. 17B shows a configuration in which the gate insulator has a four-layer stacked structure of insulators 251 to 254, but the present invention is not limited to this.
  • the gate insulator may have a single layer or a stacked structure of five or more layers. In this case, each layer included in the gate insulator may be appropriately selected from insulators 251 to 254.
  • Fig. 18A to Fig. 18D are plan views and cross-sectional views of a semiconductor device having a transistor 200D.
  • Fig. 18A is a plan view of the semiconductor device.
  • Fig. 18B to Fig. 18D are cross-sectional views of the semiconductor device.
  • Fig. 18B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in Fig. 18A.
  • Fig. 18C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in Fig. 18A. Note that some elements are omitted in the plan view of Fig. 18A for clarity.
  • the semiconductor device shown in Figures 18A to 18D has an insulator 210 on a substrate (not shown), a transistor 200D on the insulator 210, an insulator 280 on the insulator 210, an insulator 281 on the insulator 280, an insulator 251 on the transistor 200D, an insulator 252 on the insulator 251, and an insulator 275 on the insulator 252.
  • Transistor 200D has a conductor 220, a conductor 260 on insulator 280, a conductor 240 on insulator 281, and an insulator 221, an insulator 222, and an oxide semiconductor 230 on conductor 220.
  • the insulator 280, the conductor 260, the insulator 281, and the conductor 240 have openings 291 that reach the conductor 220. That is, the openings 291 are provided in a region that overlaps with the conductor 220 in a plan view.
  • the bottom of the openings 291 is the top surface of the conductor 220
  • the side walls of the openings 291 are the side surfaces of the insulator 280, the conductor 260, the insulator 281, and the conductor 240.
  • the openings 291 include an opening in the insulator 280, an opening in the conductor 260, an opening in the insulator 281, and an opening in the conductor 240.
  • insulator 221, insulator 222, and oxide semiconductor 230 are each arranged such that at least a portion of them is located in opening 291.
  • the portions of the insulator 221, the insulator 222, and the oxide semiconductor 230 that are arranged in the opening 291 are provided to reflect the shape of the opening 291.
  • the insulators 221 and 222 are provided to cover the side walls of the opening 291
  • the oxide semiconductor 230 is provided to cover the side surfaces of the insulators 221 and 222 and the bottom of the opening 291.
  • each of the insulators 251, 252, and 275 is arranged so that at least a portion thereof is located in the opening 291. Furthermore, the portions of the insulators 251, 252, and 275 arranged in the opening 291 are provided to reflect the shape of the opening 291.
  • the insulator 251 is provided to cover the oxide semiconductor 230
  • the insulator 252 is provided to cover the insulator 251
  • the insulator 275 is provided to fill the recess of the insulator 252 that reflects the shape of the opening 291.
  • the oxide semiconductor 230 functions as a semiconductor layer
  • the conductor 260 functions as a gate electrode
  • the insulators 221 and 222 function as gate insulators
  • the conductor 220 functions as one of the source electrode and the drain electrode
  • the conductor 240 functions as the other of the source electrode and the drain electrode.
  • the transistor 200D has a configuration in which one of the source electrode and the drain electrode is located below and the other of the source electrode and the drain electrode is located above, so that the current flows in the vertical direction. In other words, a channel is formed along the side of the opening 291.
  • FIG. 18D shows a cross-sectional view in the XY plane including the conductor 260.
  • the channel formation region of the transistor 200D can be formed in the oxide semiconductor 230 located inside the conductor 260.
  • the channel formation region of the transistor 200D can be formed in the oxide semiconductor 230 facing the conductor 260.
  • FIG. 18D can also be said to be a cross-sectional view in the XY plane including the channel formation region of the oxide semiconductor 230.
  • the transistor 200D it is preferable to use a metal oxide (also called an oxide semiconductor) that functions as a semiconductor for the oxide semiconductor 230 including the channel formation region. In this case, the transistor 200D becomes an OS transistor.
  • a metal oxide also called an oxide semiconductor
  • the insulator 275 can be one of the insulators described in the [Insulator] section below.
  • barrier insulator against hydrogen it is preferable to use a barrier insulator against hydrogen as the insulator 281. This allows the oxide semiconductor 230 to be sandwiched between barrier insulators against hydrogen (here, the insulators 281 and 252) even in regions other than inside the opening 291.
  • the semiconductor device shown in FIG. 18A to 18D has the structure described with reference to FIG. 6A and FIG. 6B. Therefore, the oxide semiconductor 230, the conductor 260, the insulator 221, the insulator 222, the insulator 251, the insulator 252, and the insulator 275 in the configurations shown in FIG.
  • 18A to 18D correspond to the oxide semiconductor 30, the conductor 15, the insulator 21, the insulator 22, the insulator 51, the insulator 52, and the insulator 75 in the configurations shown in FIG. 6A and FIG. 6A described in embodiment 1, respectively.
  • the oxide semiconductor 230 is sandwiched between barrier insulators against hydrogen (here, the insulator 221 and the insulator 252).
  • barrier insulators against hydrogen here, the insulator 221 and the insulator 252.
  • the present invention is not limited to this.
  • the semiconductor device of one embodiment of the present invention may have a structure in which one of the insulator 222 and the insulator 251 is provided. In other words, the other of the insulator 222 and the insulator 251 is not provided.
  • the semiconductor device may have a structure in which the insulator 222 is provided but the insulator 251 is not provided. In this case, the oxide semiconductor 230 has a region in contact with the insulator 252.
  • the semiconductor device may have a structure in which the insulator 251 is provided but the insulator 222 is not provided. In this case, the oxide semiconductor 230 has a region in contact with the insulator 221.
  • the semiconductor device of one embodiment of the present invention may have a structure in which the oxide semiconductor 230 is in contact with the bottom surface of the conductor 240.
  • Figures 21A to 21D are plan and cross-sectional views of a semiconductor device having a transistor 200D.
  • Figure 21A is a plan view of the semiconductor device.
  • Figures 21B to 21D are cross-sectional views of the semiconductor device.
  • Figure 21B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 21A.
  • Figure 21C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 21A.
  • Figure 21D is a cross-sectional view in the XY plane including the conductor 260. Note that some elements are omitted from the plan view of Figure 21A to clarify the figure.
  • the semiconductor device shown in Figures 21A to 21D has an insulator 210 on a substrate (not shown), a transistor 200D on the insulator 210, an insulator 280 on the insulator 210, an insulator 281 on the insulator 280, and an insulator 283 on the transistor 200D.
  • Transistor 200D has a conductor 220, a conductor 260 on insulator 280, a conductor 240 on insulator 281, insulators 221, 222, and oxide semiconductor 230 on conductor 220, an insulator 275 on oxide semiconductor 230, and a conductor 240 on oxide semiconductor 230 and on insulator 275.
  • the conductor 240 is provided above the insulator 281. Above the insulator 281, the conductor 240 has a region in contact with the top surface of the oxide semiconductor 230 and the top surface of the insulator 275. The conductor 240 does not have an opening that reaches the conductor 220. In other words, the opening 291 includes an opening provided in the insulator 280, an opening provided in the conductor 260, and an opening provided in the insulator 281.
  • the oxide semiconductor 230 has a region in contact with the upper surface of the insulator 281, a region in contact with the side surface of the insulator 222, a region in contact with the side surface of the insulator 275, and a region in contact with the lower surface of the conductor 240.
  • the oxide semiconductor 230 also has a recess that reflects the shape of the opening 291.
  • the insulator 275 is provided so as to be located between the oxide semiconductor 230 and the conductor 240.
  • the insulator 275 is provided so as to fill the recess of the oxide semiconductor 230.
  • the insulator 275 has a region that is in contact with the recess of the oxide semiconductor 230.
  • a film that releases oxygen when heated is preferably used for the insulator 275.
  • the insulator 275 releases oxygen due to heat applied during a manufacturing process of the transistor 200D, so that oxygen can be supplied to the oxide semiconductor 230.
  • Supplying oxygen from the insulator 275 to the oxide semiconductor 230, particularly to a channel formation region of the oxide semiconductor 230, can reduce oxygen vacancies and VOH in the oxide semiconductor 230, thereby enabling a transistor to have favorable electrical characteristics and high reliability.
  • the semiconductor device shown in FIG. 21A to 21D has the structure described with reference to FIG. 7A and FIG. 7B. Therefore, the oxide semiconductor 230, the conductor 260, the insulator 221, the insulator 222, and the insulator 275 in the configuration shown in FIG. 21 correspond to the oxide semiconductor 30, the conductor 15, the insulator 21, the insulator 22, and the insulator 75 in the configuration shown in FIG. 7A and FIG. 7A described in embodiment 1, respectively.
  • the insulator 281 is shown as a single layer, but the present invention is not limited thereto.
  • the insulator 281 may have a stacked structure.
  • the insulator 281 may have a stacked structure of an insulator 281a and an insulator 281b on the insulator 281a.
  • the insulator described in the [Insulator] section described later can be used as the insulator 281a.
  • the productivity of the semiconductor device can be improved by forming an insulating film to be the insulator 281a by a method with a high film formation rate (for example, a sputtering method or a CVD method).
  • the insulator 221 is provided so as to be in contact with the side wall of the opening 291, but the present invention is not limited thereto.
  • the insulator 221 may have a region in contact with the upper surface of the insulator 281.
  • the insulator 221 may be provided so as to be in contact with the upper surface of the insulator 281 and the side surface of the insulator 281 in the opening 291.
  • the insulator 221 may have an opening that reaches the conductor 220 in the opening 291.
  • the insulator 222 may be provided so as to be in contact with the upper surface of the insulator 221.
  • the insulator 222 may have an opening that reaches the conductor 220 in the opening 291.
  • the oxide semiconductor 230 is in contact with an insulator that captures or fixes hydrogen even above the insulator 281, so that the hydrogen concentration in the oxide semiconductor 230 can be reduced.
  • 21A to 21D show a configuration in which an insulator 275 is provided in a recess in the oxide semiconductor 230, but the present invention is not limited to this.
  • the area of the opening in the conductor 260 in a plan view may be reduced so that the oxide semiconductor 230 does not have a recess (see FIG. 23). In this case, it is not necessary to provide the insulator 275.
  • a gap may be provided between the oxide semiconductor 230 and the conductor 240.
  • the insulator 275 is not provided.
  • the gap contains, for example, one or more selected from air, nitrogen, oxygen, carbon dioxide, and a group 18 element.
  • 23A to 23D has a configuration in which an insulator 221, an insulator 222, and an oxide semiconductor 230 are provided in this order inside an opening of a conductor 260. That is, the semiconductor device shown in FIG. 23A to 23D has the structure described with reference to FIG. 7C and FIG. 7D. Therefore, the oxide semiconductor 230, the conductor 260, the insulator 221, and the insulator 222 in the configurations shown in FIG. 23A to 23D correspond to the oxide semiconductor 30, the conductor 15, the insulator 21, and the insulator 22 in the configurations shown in FIG. 7C and FIG. 7D described in embodiment 1, respectively.
  • Fig. 24A to Fig. 24D are plan views and cross-sectional views of a semiconductor device having a transistor 200E.
  • Fig. 24A is a plan view of the semiconductor device.
  • Fig. 24B to Fig. 24D are cross-sectional views of the semiconductor device.
  • Fig. 24B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in Fig. 24A.
  • Fig. 24C is a cross-sectional view of a portion indicated by a dashed line A3-A4 in Fig. 24A.
  • Fig. 24D is a cross-sectional view in the XY plane including the insulator 280. Note that in the plan view of Fig. 24A, some elements are omitted for clarity.
  • the semiconductor device shown in Figures 24A to 24D has an insulator 210 on a substrate (not shown), a transistor 200E on the insulator 210, an insulator 280 on the insulator 210, and an insulator 283 on the transistor 200E.
  • Transistor 200E has conductor 242a and conductor 242b on insulator 280, oxide semiconductor 230, insulator 251 on oxide semiconductor 230, insulator 252 on insulator 251, and conductor 260 on insulator 252.
  • the semiconductor device shown in Figures 24A to 24D differs from the semiconductor device shown in Figures 10A to 10D in the shape of the oxide semiconductor 230.
  • the semiconductor device shown in Figures 24A to 24D also differs from the semiconductor device shown in Figures 10A to 10D in that it does not have a conductor 220 and has conductors 242a and 242b instead of conductor 240.
  • differences from the content described using Figures 10A to 10D will be mainly described, and overlapping parts will be referred to and may not be described.
  • the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 are provided inside the opening 290 of the insulator 280.
  • the side surface of the insulator 280 has a region in contact with the oxide semiconductor 230 and a region in contact with the insulator 251.
  • the oxide semiconductor 230 has a region that contacts the bottom of the opening 290.
  • the bottom surface of the oxide semiconductor 230 in the opening 290 contacts the insulator 210.
  • the conductor 242a and the conductor 242b are separated by an opening 290.
  • the conductors described in the [Conductor] section below can be used as the conductors 242a and 242b in a single layer or a laminated layer.
  • oxide semiconductor 230 functions as a semiconductor layer
  • conductor 260 functions as a gate electrode
  • insulators 251 and 252 function as gate insulators
  • conductor 242a functions as one of the source electrode and drain electrode
  • conductor 242b functions as the other of the source electrode and drain electrode.
  • 24A to 24D has a configuration in which an oxide semiconductor 230, an insulator 251, an insulator 252, and a conductor 260 are provided in this order inside an opening of an insulator 280. That is, the semiconductor device shown in FIG. 24A to 24D has the structure described with reference to FIG. 8C and FIG. 8D. Therefore, the oxide semiconductor 230, the insulator 280, the insulator 251, the insulator 252, and the conductor 260 in the configurations shown in FIG. 24A to 24D correspond to the oxide semiconductor 30, the insulator 21, the insulator 51, the insulator 52, and the conductor 60 in the configurations shown in FIG. 8C and FIG. 8D described in embodiment 1, respectively.
  • the oxide semiconductor 230 is provided so that at least a portion thereof is located inside the opening 290.
  • the transistor 200E has a configuration in which a current flows from one of the source electrode and the drain electrode (e.g., the conductor 242a) to the other of the source electrode and the drain electrode (e.g., the conductor 242b). That is, the channel length of the transistor 200E (length L indicated by a double arrow in FIG. 24B) is the sum of twice the length of the sidewall of the opening 290 and the length of the bottom of the opening 290. The length of the sidewall of the opening 290 corresponds to the depth of the opening 290.
  • the length of the bottom of the opening 290 is also the shortest distance from the conductor 242a to the conductor 242b, for example.
  • the channel length (length L) of the transistor 200E can be adjusted by the depth of the opening 290 and the length of the bottom of the opening 290. For example, when miniaturizing or increasing the integration density of a semiconductor device while lengthening the channel length, it is advisable to increase the depth of the opening 290.
  • the channel width of the transistor 200E corresponds to the width of the oxide semiconductor 230 in the Y direction in a plan view. Therefore, it is preferable that the channel width of the transistor 200E is smaller than the width of the bottom of the opening 290.
  • 24B to 24D show a configuration in which the oxide semiconductor 230 and the insulator 251 are in contact with the insulator 280 in the opening 290, but the present invention is not limited to this.
  • an insulator having a function of capturing or fixing hydrogen may be provided between the oxide semiconductor 230 and the insulator 251 and the insulator 280.
  • Figures 25A to 25D show another example of a semiconductor device.
  • Figure 25A is a plan view of a semiconductor device having a transistor 200E.
  • Figures 25B to 25D are cross-sectional views of the semiconductor device.
  • Figure 25B is a cross-sectional view of the portion indicated by the dashed line A1-A2 in Figure 25A.
  • Figure 25C is a cross-sectional view of the portion indicated by the dashed line A3-A4 in Figure 25A.
  • Figure 25D is a cross-sectional view in the XY plane including the insulator 280. Note that some elements are omitted from the plan view of Figure 25A to clarify the figure.
  • the semiconductor device shown in Figures 25A to 25D differs from the semiconductor device shown in Figures 24A to 24D in that it has an insulator 222.
  • differences from the content explained using Figures 24A to 24D will be mainly explained, and overlapping parts will be referred to and explanations may be omitted.
  • the insulator 222 is provided between the oxide semiconductor 230 and the insulator 251 and the insulator 280.
  • the portions of the insulator 222, the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 that are arranged in the opening 290 are provided to reflect the shape of the opening 290.
  • the insulator 222 is provided to cover the sidewall of the opening 290
  • the oxide semiconductor 230 is provided to cover a portion of the side surface of the insulator 222 and a portion of the bottom of the opening 290
  • the insulator 251 is provided to cover the other portion of the side surface of the insulator 222, the other portion of the bottom of the opening 290
  • the oxide semiconductor 230 is provided to cover the insulator 251
  • the conductor 260 is provided to cover the insulator 252.
  • the 25A to 25D has a configuration in which the insulator 222, the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 are provided in this order inside the opening of the insulator 280. That is, the semiconductor device shown in FIG. 25A to 25D has the structure described with reference to FIG. 8E and FIG. 8F. Therefore, the oxide semiconductor 230, the insulator 280, the insulator 222, the insulator 251, the insulator 252, and the conductor 260 in the configurations shown in FIG. 25A to 25D correspond to the oxide semiconductor 30, the insulator 21, the insulator 22, the insulator 51, the insulator 52, and the conductor 60 in the configurations shown in FIG. 8E and FIG. 8F described in embodiment 1, respectively.
  • the oxide semiconductor 230 can be sandwiched between insulators (here, the insulator 222 and the insulator 251) that capture or fix hydrogen.
  • the transistor 200E shown in FIGS. 24A to 24D can be manufactured on the same layer (insulator 210 here) as the transistor 200A shown in FIGS. 10A to 10D. That is, the transistor 200E can be manufactured at the same time through the manufacturing process of the transistor 200A.
  • the semiconductor device of one embodiment of the present invention has an excellent effect that transistors with different channel lengths can be freely designed on the same layer by changing the thickness of the insulating layer and pattern formation.
  • FIG. 26A is a plan view of the semiconductor device.
  • FIG. 26B is a cross-sectional view of the semiconductor device, and is a cross-sectional view of a portion indicated by the dashed line A5-A6 in FIG. 26A.
  • the substrate on which the transistor is formed for example, an insulating substrate, a semiconductor substrate, or a conductive substrate may be used.
  • a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as an yttria stabilized zirconia substrate), a resin substrate, etc. are available.
  • a semiconductor substrate made of silicon or germanium, or a compound semiconductor substrate made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide, etc. are available.
  • a semiconductor substrate having an insulating region inside the aforementioned semiconductor substrate for example, an SOI (Silicon On Insulator) substrate, etc. are available.
  • the conductive substrate there is a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, etc. are available.
  • a substrate having a metal nitride, a substrate having a metal oxide, etc. are available.
  • a substrate in which a conductor or a semiconductor is provided on an insulating substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductive substrate, etc. are available.
  • a substrate provided with elements may be used.
  • the elements provided on the substrate include a capacitor element, a resistor element, a switch element, a light-emitting element, a memory element, and the like.
  • Insulator examples include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides, each of which has insulating properties.
  • Examples of materials with a high dielectric constant include aluminum oxide, gallium oxide, hafnium oxide, tantalum oxide, zirconium oxide, hafnium zirconium oxide, oxides having aluminum and hafnium, oxynitrides having aluminum and hafnium, oxides having silicon and hafnium, oxynitrides having silicon and hafnium, and nitrides having silicon and hafnium.
  • materials with a low relative dielectric constant include inorganic insulating materials such as silicon oxide, silicon oxynitride, and silicon nitride oxide, and resins such as polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, and acrylic.
  • inorganic insulating materials with a low relative dielectric constant include silicon oxide with added fluorine, silicon oxide with added carbon, and silicon oxide with added carbon and nitrogen. Another example is silicon oxide with vacancies. These silicon oxides may contain nitrogen.
  • the electrical characteristics of a transistor using a metal oxide can be stabilized by surrounding the transistor with an insulator having a function of suppressing the permeation of impurities and oxygen.
  • an insulator having a function of suppressing the permeation of impurities and oxygen for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer.
  • metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide
  • metal nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride can be used.
  • Insulators in contact with a semiconductor such as a gate insulator, or insulators provided near a semiconductor layer are preferably insulators having a region containing oxygen that is desorbed by heating (hereinafter, sometimes referred to as excess oxygen).
  • excess oxygen oxygen vacancies in the semiconductor layer can be reduced by providing an insulator having a region containing excess oxygen in contact with a semiconductor layer or in the vicinity of the semiconductor layer.
  • Examples of insulators that are likely to form a region containing excess oxygen include silicon oxide, silicon oxynitride, and silicon oxide with vacancies.
  • examples of the barrier insulator against oxygen include oxides containing one or both of aluminum and hafnium, oxides containing hafnium and silicon (hafnium silicate), magnesium oxide, gallium oxide, gallium zinc oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide.
  • examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate).
  • a barrier insulator against oxygen and a barrier insulator against hydrogen can be said to be a barrier insulator against either or both of oxygen and hydrogen.
  • the conductor it is preferable to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements.
  • a nitride of the alloy or an oxide of the alloy may be used as the alloy containing the above-mentioned metal elements as a component.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, etc.
  • a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.
  • conductive materials containing nitrogen such as nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing ruthenium, nitrides containing tantalum and aluminum, or nitrides containing titanium and aluminum
  • conductive materials containing oxygen such as ruthenium oxide, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel
  • materials containing metal elements such as titanium, tantalum, or ruthenium are preferred because they are conductive materials that are difficult to oxidize, conductive materials that have a function of suppressing oxygen diffusion, or materials that maintain conductivity even when oxygen is absorbed.
  • examples of conductive materials containing oxygen include indium oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, indium tin oxide containing titanium oxide, indium tin oxide to which silicon has been added, indium zinc oxide, and indium zinc oxide containing tungsten oxide.
  • a conductive film formed using a conductive material containing oxygen may be called an oxide conductive film.
  • conductive materials primarily composed of tungsten, copper, or aluminum are preferred because they have high conductivity.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element and a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.
  • a metal oxide is used for the channel formation region of a transistor, it is preferable to use a layered structure in which a material containing the above-mentioned metal element and a conductive material containing oxygen are combined for the conductor that functions as the gate electrode. In this case, it is preferable to provide the conductive material containing oxygen on the channel formation region side. By providing the conductive material containing oxygen on the channel formation region side, oxygen desorbed from the conductive material is easily supplied to the channel formation region.
  • a conductor functioning as a gate electrode it is preferable to use a conductive material containing oxygen and a metal element contained in the metal oxide in which the channel is formed.
  • the conductive material containing the metal element and nitrogen described above may also be used.
  • a conductive material containing nitrogen such as titanium nitride or tantalum nitride, may also be used.
  • Indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide with added silicon may also be used.
  • Indium gallium zinc oxide containing nitrogen may also be used.
  • Metal oxides may have lattice defects.
  • Lattice defects include point defects such as atomic vacancies and heteroatoms, line defects such as dislocations, surface defects such as grain boundaries, and volume defects such as voids.
  • Factors that cause the generation of lattice defects include a deviation in the ratio of the number of atoms of the constituent elements (an excess or deficiency of constituent atoms) and impurities.
  • the metal oxide used in the semiconductor layer of a transistor When a metal oxide is used in the semiconductor layer of a transistor, lattice defects in the metal oxide can cause carrier generation or capture. Therefore, if a metal oxide with many lattice defects is used in the semiconductor layer of a transistor, the electrical characteristics of the transistor may become unstable. Therefore, it is preferable that the metal oxide used in the semiconductor layer of a transistor has few lattice defects.
  • the types of lattice defects likely to exist in metal oxides and the amount of lattice defects present vary depending on the structure of the metal oxide or the method of forming the metal oxide film.
  • Non-single crystal structures include, for example, CAAC structures, polycrystalline structures, nc structures, pseudo-amorphous (a-like) structures, and amorphous structures.
  • A-like structures have a structure between the nc structures and the amorphous structures. The classification of crystal structures will be described later.
  • metal oxides having an a-like structure and metal oxides having an amorphous structure have voids or low-density regions. That is, metal oxides having an a-like structure and metal oxides having an amorphous structure have lower crystallinity than metal oxides having an nc structure and metal oxides having a CAAC structure. In addition, metal oxides having an a-like structure have a higher hydrogen concentration in the metal oxide than metal oxides having an nc structure and metal oxides having a CAAC structure. Therefore, lattice defects are easily generated in metal oxides having an a-like structure and metal oxides having an amorphous structure.
  • a metal oxide with high crystallinity for the semiconductor layer of the transistor.
  • a metal oxide having a CAAC structure or a metal oxide having a single crystal structure By using such a metal oxide for the transistor, a transistor with good electrical characteristics can be realized. In addition, a highly reliable transistor can be realized.
  • a metal oxide for the channel formation region of a transistor, which increases the on-state current of the transistor.
  • the crystal has a crystal structure in which multiple layers (for example, a first layer, a second layer, and a third layer) are stacked. That is, the crystal has a layered crystal structure (also called a layered crystal or layered structure). In this case, the c-axis of the crystal is oriented in the direction in which the multiple layers are stacked.
  • metal oxides having the crystal include single crystal oxide semiconductors and CAAC-OS (c-axis aligned crystalline oxide semiconductors).
  • the c-axis of the crystal in the normal direction to the surface on which the metal oxide is formed or the film surface. This allows the multiple layers to be arranged parallel or approximately parallel to the surface on which the metal oxide is formed or the film surface. In other words, the multiple layers extend in the channel length direction.
  • the above three-layered crystal structure has the following structure.
  • the first layer has an atomic coordination structure of an oxygen octahedron with the metal of the first layer at the center.
  • the second layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the second layer at the center.
  • the third layer has an atomic coordination structure of an oxygen trigonal bipyramid or tetrahedron with the metal of the third layer at the center.
  • Examples of the crystal structure of the above crystal include a YbFe 2 O 4 type structure, a Yb 2 Fe 3 O 7 type structure, and modified structures thereof.
  • each of the first layer to the third layer is preferably composed of one metal element or multiple metal elements having the same valence, and oxygen.
  • the valence of the one or multiple metal elements constituting the first layer is preferably the same as the valence of the one or multiple metal elements constituting the second layer.
  • the first layer and the second layer may have the same metal element.
  • the valence of the one or multiple metal elements constituting the first layer is different from the valence of the one or multiple metal elements constituting the third layer.
  • the crystallinity of the metal oxide can be improved, and the carrier mobility of the metal oxide can be increased. Therefore, by using the metal oxide in the channel formation region of a transistor, the on-state current of the transistor can be increased, and the electrical characteristics of the transistor can be improved.
  • Examples of the metal oxide of one embodiment of the present invention include indium oxide, gallium oxide, and zinc oxide.
  • the metal oxide of one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn).
  • the metal oxide preferably has two or three elements selected from indium, element M, and zinc.
  • the element M is a metal element or semi-metal element having a high bond energy with oxygen, for example, a metal element or semi-metal element having a higher bond energy with oxygen than indium.
  • the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony.
  • the element M in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably gallium.
  • the metal oxide of one embodiment of the present invention preferably has one or more selected from indium, gallium, and zinc.
  • metal elements and metalloid elements may be collectively referred to as “metal elements", and the "metal element” described in this specification and the like may include metalloid elements.
  • indium zinc oxide indium tin oxide
  • indium titanium oxide In-Ti oxide
  • indium gallium oxide In-Ga oxide
  • indium gallium aluminum oxide In-Ga-Al oxide
  • indium gallium tin oxide In-Ga-Sn oxide
  • gallium zinc oxide Ga-Zn oxide, also referred to as GZO
  • aluminum zinc oxide Al-Zn oxide, also referred to as AZO
  • indium a examples of the usable materials include aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to
  • the field effect mobility of the transistor can be increased.
  • the metal oxide may have one or more kinds of metal elements having a higher period number in the periodic table instead of indium.
  • the metal oxide may have one or more kinds of metal elements having a higher period number in the periodic table in addition to indium.
  • Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and metal elements belonging to the sixth period.
  • the metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.
  • the metal oxide may also contain one or more nonmetallic elements.
  • the field effect mobility of the transistor may be increased.
  • nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.
  • the metal oxide becomes highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed. Therefore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, and reliability can be improved.
  • the transistor can obtain a large on-current and high frequency characteristics.
  • In-Ga-Zn oxide may be used as an example of a metal oxide.
  • the metal oxide film formation method of the present invention it is preferable to deposit atoms one layer at a time.
  • the ALD method is used, so that it is easy to form a metal oxide having the above-mentioned layered crystal structure.
  • a transistor with high field-effect mobility can be realized.
  • a highly reliable transistor can be realized.
  • a miniaturized or highly integrated transistor can be realized. For example, a transistor with a channel length of 2 nm to 30 nm can be manufactured.
  • an oxide semiconductor having a low carrier concentration is preferably used for the channel formation region of the transistor.
  • the carrier concentration of the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably 1 ⁇ 10 17 cm ⁇ 3 or less, more preferably 1 ⁇ 10 15 cm ⁇ 3 or less, more preferably 1 ⁇ 10 13 cm ⁇ 3 or less, more preferably 1 ⁇ 10 11 cm ⁇ 3 or less, and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more. Note that in order to reduce the carrier concentration of the oxide semiconductor film, it is only necessary to reduce the impurity concentration in the oxide semiconductor film and reduce the density of defect states.
  • a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor film has a low density of defect states, and therefore may also have a low density of trap states.
  • the charge trapped in the trap states of the oxide semiconductor takes a long time to disappear and may behave as if it were a fixed charge. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • an impurity in an oxide semiconductor refers to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and further preferably 3.0 eV or more.
  • the off-state current (also referred to as Ioff) of the transistor can be reduced.
  • OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (channel length is reduced).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes referred to as S value), and an increase in leakage current.
  • S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
  • characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the OS transistor can also be regarded as having an n + / n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ /n + accumulation-type non-junction transistor structure in which the channel formation region is an n ⁇ type region and the source region and drain region are n + type regions.
  • the OS transistor can have good electrical characteristics even when miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the channel length or gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, and 1 nm or more, 3 nm or more, or 5 nm or more.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.
  • the carbon concentration in a channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and further preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the silicon concentration in the channel formation region of the oxide semiconductor measured by SIMS is 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 3 ⁇ 10 18 atoms/cm 3 or less, and still more preferably 1 ⁇ 10 18 atoms/cm 3 or less.
  • the nitrogen concentration in a channel formation region of an oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 20 atoms/cm 3 or less, preferably 5 ⁇ 10 19 atoms/cm 3 or less, more preferably 1 ⁇ 10 19 atoms/cm 3 or less, more preferably 5 ⁇ 10 18 atoms/cm 3 or less, more preferably 1 ⁇ 10 18 atoms/cm 3 or less, and further preferably 5 ⁇ 10 17 atoms/cm 3 or less.
  • Hydrogen contained in the oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy.
  • an electron serving as a carrier may be generated.
  • some of the hydrogen may bond to oxygen bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable that hydrogen in a channel formation region of the oxide semiconductor is reduced as much as possible.
  • the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is less than 1 ⁇ 10 20 atoms/cm 3 , preferably less than 5 ⁇ 10 19 atoms/cm 3 , more preferably less than 1 ⁇ 10 19 atoms/cm 3 , more preferably less than 5 ⁇ 10 18 atoms/cm 3 , more preferably less than 1 ⁇ 10 18 atoms/cm 3 , and further preferably less than 1 ⁇ 10 17 atoms/cm 3 .
  • the concentration of the alkali metal or the alkaline earth metal in a channel formation region of the oxide semiconductor obtained by SIMS is set to 1 ⁇ 10 18 atoms/cm 3 or less, preferably 2 ⁇ 10 16 atoms/cm 3 or less.
  • the oxide semiconductor 230 can be rephrased as a semiconductor layer including a channel formation region of a transistor.
  • a semiconductor material that can be used for the semiconductor layer is not limited to the above-mentioned metal oxides.
  • a semiconductor material having a band gap (a semiconductor material that is not a zero-gap semiconductor) may be used for the semiconductor layer.
  • a semiconductor of a single element, a compound semiconductor, or a layered material (also referred to as an atomic layer material, a two-dimensional material, or the like) is preferably used for the semiconductor material.
  • layered material is a general term for a group of materials having a layered crystal structure.
  • a layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces.
  • Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity.
  • Examples of semiconductor elements that can be used in the semiconductor material include silicon and germanium.
  • Examples of silicon that can be used in the semiconductor layer include single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon.
  • Examples of polycrystalline silicon include low temperature polysilicon (LTPS).
  • Compound semiconductors that can be used for the semiconductor material include silicon carbide, silicon germanium, gallium arsenide, indium phosphide, boron nitride, and boron arsenide.
  • the boron nitride that can be used for the semiconductor layer preferably includes an amorphous structure.
  • the boron arsenide that can be used for the semiconductor layer preferably includes crystals with a cubic structure.
  • Examples of layered materials include graphene, silicene, boron carbonitride, and chalcogenides.
  • boron carbonitride carbon atoms, nitrogen atoms, and boron atoms are arranged in a hexagonal lattice structure on a plane.
  • Chalcogenides are compounds that contain chalcogen. Chalcogen is a general term for elements that belong to Group 16, and includes oxygen, sulfur, selenium, tellurium, polonium, and livermorium.
  • Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides.
  • transition metal chalcogenide that functions as a semiconductor.
  • transition metal chalcogenides that can be used as the semiconductor layer include molybdenum sulfide (representatively MoS 2 ), molybdenum selenide (representatively MoSe 2 ), molybdenum tellurium (representatively MoTe 2 ), tungsten sulfide (representatively WS 2 ), tungsten selenide (representatively WSe 2 ), tungsten tellurium (representatively WTe 2 ), hafnium sulfide (representatively HfS 2 ), hafnium selenide (representatively HfSe 2 ), zirconium sulfide (representatively ZrS 2 ), and zirconium selenide (representatively ZrSe 2 ).By applying the above-mentioned transition metal chalcogen
  • Embodiment 3 27A to 34D, a structure example of a semiconductor device according to one embodiment of the present invention will be described.
  • the semiconductor device according to one embodiment of the present invention has the structure described in Embodiment 1.
  • a in each figure shows a plan view of the semiconductor device.
  • B in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A1-A2 in A in each figure, and is also a cross-sectional view in the channel length direction of the transistor.
  • C in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A3-A4 in A in each figure, and is also a cross-sectional view in the channel width direction of the transistor.
  • D in each figure is a cross-sectional view corresponding to the portion indicated by the dashed line A5-A6 in A in each figure.
  • dashed line A1-A2 is perpendicular to the dashed line A3-A4 and the dashed line A5-A6, and the dashed line A3-A4 and the dashed line A5-A6 are parallel to each other.
  • the plan view A in each figure some elements are omitted to clarify the figure.
  • Figures 27A to 27D are plan views and cross-sectional views of a semiconductor device including a transistor 200B.
  • Transistor 200B has an insulator 216 on insulator 214, a conductor 215 embedded in insulator 216, an insulator 221 on insulator 216 and conductor 215, an insulator 222 on insulator 221, an oxide semiconductor 230 on insulator 222, conductor 242a and conductor 242b on oxide semiconductor 230, an insulator 251 on oxide semiconductor 230, an insulator 252 on insulator 251, and a conductor 260 on insulator 252.
  • oxide semiconductor 230 functions as a semiconductor layer
  • conductor 260 functions as a first gate electrode (upper gate electrode)
  • insulators 251 and 252 function as first gate insulators
  • conductor 215 functions as a second gate electrode (lower gate electrode)
  • insulators 221 and 222 function as second gate insulators
  • conductor 242a functions as one of the source electrode and drain electrode
  • conductor 242b functions as the other of the source electrode and drain electrode.
  • a channel formation region and a source region and a drain region are formed to sandwich the channel formation region. At least a part of the channel formation region overlaps with the conductor 260.
  • the source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region can be interchanged.
  • the concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may change continuously within each region, not necessarily in a stepwise manner. In other words, the concentrations of impurity elements such as hydrogen and nitrogen may decrease in a region closer to the channel formation region.
  • the transistor 200B it is preferable to use a metal oxide (also called an oxide semiconductor) that functions as a semiconductor for the oxide semiconductor 230 including the channel formation region.
  • a metal oxide also called an oxide semiconductor
  • the transistor 200B is an OS transistor.
  • the channel formation region of an OS transistor is preferably a high-resistance region with a low carrier concentration. Therefore, the channel formation region of an OS transistor is preferably i-type (intrinsic) or substantially i-type.
  • the source and drain regions of an OS transistor are preferably regions having more oxygen vacancies, more VOH , or a higher concentration of impurities such as hydrogen, nitrogen, or metal elements than the channel formation region, thereby increasing the carrier concentration and lowering the resistance. That is, the source and drain regions of an OS transistor are preferably n-type regions having a higher carrier concentration and lower resistance than the channel formation region.
  • the conductor 215, the insulator 221, the insulator 222, the oxide semiconductor 230, the insulator 251, the insulator 252, and the conductor 260 in the configurations shown in FIGS. 27A to 27D correspond to the conductor 15, the insulator 21, the insulator 22, the oxide semiconductor 30, the insulator 51, the insulator 52, and the conductor 60 in the configuration shown in FIG. 9D described in embodiment 1, respectively.
  • the insulator 251 in contact with the top surface and side surface of the channel formation region of the oxide semiconductor 230 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. As a result, VOH in the channel formation region can be reduced and the channel formation region can be made i-type or substantially i-type.
  • the contents of the insulator 51 described in Embodiment 1 can be referred to.
  • the insulator 251 is not in contact with the source region or the drain region of the oxide semiconductor 230; therefore, the source region and the drain region have a higher hydrogen concentration or a larger amount of VOH than the channel formation region.
  • the source region and the drain region can have a higher carrier concentration and a lower resistance than the channel formation region.
  • the insulator 222 in contact with the bottom surface of the channel formation region of the oxide semiconductor 230 preferably has a function of capturing or fixing hydrogen. This can reduce the hydrogen concentration in the channel formation region of the oxide semiconductor 230. As a result, VOH in the channel formation region can be reduced and the channel formation region can be made i-type or substantially i-type.
  • the contents of the insulator 22 described in Embodiment 1 can be referred to.
  • hafnium oxide or an oxide containing hafnium and silicon can be used as the insulator 251 and the insulator 222.
  • Hafnium oxide is also a high dielectric constant (high-k) material, and an oxide containing hafnium and silicon becomes a high dielectric constant (high-k) material depending on the silicon content. Therefore, it is possible to reduce the first gate potential applied during transistor operation while maintaining the physical thickness of the first gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the first gate insulator. Similarly, it is possible to reduce the second gate potential applied during transistor operation while maintaining the physical thickness of the second gate insulator. In addition, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the second gate insulator.
  • EOT equivalent oxide thickness
  • the thickness of the insulator 222 is preferably within the range of the width of the insulator 51 in the B1-B2 direction as described in embodiment 1. Note that the thicker the insulator that has the function of capturing or fixing hydrogen, the more hydrogen it can capture or fix. Therefore, the thickness of the insulator 222 is not limited to the above. For example, the thickness of the insulator 222 may be 2 nm or more and 30 nm or less, or 3 nm or more and 30 nm or less. It is sufficient that the insulator 222 has a region of the above thickness in at least a portion.
  • the insulator 252 located above the channel formation region of the oxide semiconductor 230 is preferably a barrier insulator against hydrogen. This can suppress diffusion of hydrogen contained in a structure provided above the insulator 252 to the channel formation region of the oxide semiconductor 230. As a result, VOH in the channel formation region can be reduced and the channel formation region can be made i-type or substantially i-type.
  • the contents of the insulator 52 described in Embodiment 1 can be referred to.
  • the insulator 221 located below the channel formation region of the oxide semiconductor 230 is preferably a barrier insulator against hydrogen.
  • the insulator 221 is preferably a barrier insulator against oxygen.
  • the insulator 221 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 216.
  • the insulator 221 When the insulator 221 is formed using such a material, the insulator 221 functions as a layer that suppresses the release of oxygen from the oxide semiconductor 230 to the substrate side and the diffusion of impurities such as hydrogen from the periphery of the transistor 200B to the oxide semiconductor 230. Therefore, by providing the insulator 221, it is possible to suppress the diffusion of impurities such as hydrogen into the inside of the transistor 200B and to suppress the generation of oxygen vacancies in the oxide semiconductor 230. In addition, it is possible to suppress the reaction of the conductor 215 with the oxygen contained in the oxide semiconductor 230.
  • insulator 22 For the material and configuration used for the insulator 221, please refer to the details of the insulator 21 described in embodiment 1.
  • An insulator 280 is provided on the conductor 242a and the conductor 242b. That is, the insulator 280 is provided on the oxide semiconductor 230. An insulator 251, an insulator 252, and a conductor 260 are embedded inside an opening provided in the insulator 280. An insulator 283 is provided on the insulator 280, the insulator 251, the insulator 252, and the conductor 260.
  • one side end of the conductor 242a preferably coincides with one side end of the oxide semiconductor 230
  • one side end of the conductor 242b preferably coincides with the other side end of the oxide semiconductor 230.
  • the oxide semiconductor 230 and the conductive layers to be the conductor 242a and the conductor 242b may be processed together into an island shape. In this way, the semiconductor device of one embodiment of the present invention can be manufactured with good productivity.
  • the conductor 215 is arranged so as to overlap the oxide semiconductor 230 and the conductor 260.
  • the conductor 215 is preferably provided by being embedded in an opening formed in the insulator 216.
  • the conductor 215 is preferably provided extending in the channel width direction as shown in Figures 27A and 27C. With this configuration, the conductor 215 functions as a wiring when multiple transistors are provided.
  • the conductor 215 may have a single-layer structure or a laminated structure.
  • the conductor 215 has conductor 215a and conductor 215b.
  • the conductor 215a is provided in contact with the bottom surface and side wall of the opening.
  • the conductor 215b is provided so as to fill the recess of the conductor 215a formed along the opening.
  • the height of the upper surface of the conductor 215 is the same as the height of the upper surface of the insulator 216.
  • the conductor 215 is preferably larger than the area of the oxide semiconductor 230 that does not overlap with the conductors 242a and 242b. As shown in FIG. 27C, the conductor 215 preferably extends to an area outside the end of the oxide semiconductor 230 in the channel width direction. In other words, the conductor 215 and the conductor 260 preferably overlap with an insulator on the outside of the side surface of the oxide semiconductor 230 in the channel width direction. With this structure, the channel formation region of the oxide semiconductor 230 can be electrically surrounded by the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 215 functioning as the second gate electrode.
  • the transistor structure in which the electric field of at least the first gate electrode electrically surrounds the channel formation region is called a surrounded channel (S-channel) structure.
  • the S-channel structure disclosed in this specification has a structure different from the Fin type structure and the planar type structure.
  • the S-channel structure disclosed in this specification can also be considered as a type of Fin type structure.
  • the Fin type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides of the channel (specifically, two, three, or four sides, etc.).
  • the channel formation region can be electrically surrounded.
  • the S-channel structure is a structure that electrically surrounds the channel formation region, and therefore can be said to be substantially equivalent to a GAA (gate all around) structure or a LGAA (lateral gate all around) structure.
  • the channel formation region formed at or near the interface between the oxide semiconductor 230 and the gate insulator can be the entire bulk of the oxide semiconductor 230. Therefore, it is possible to improve the density of the current flowing through the transistor, and therefore it is expected to improve the on-current of the transistor or the field effect mobility of the transistor.
  • the conductor 215 is extended to function as wiring.
  • the present invention is not limited to this, and a conductor that functions as wiring may be provided below the conductor 215.
  • the conductor 215 may be shared by multiple transistors.
  • the conductor 215 may function as a second gate electrode.
  • the threshold voltage (Vth) of the transistor 200B can be controlled by changing the potential applied to the conductor 215 independently of the potential applied to the conductor 260.
  • applying a negative potential to the conductor 215 can increase the Vth of the transistor 200B and reduce the off-current. Therefore, applying a negative potential to the conductor 215 can reduce the drain current when the potential applied to the conductor 260 is 0 V, compared to when no negative potential is applied.
  • the electrical resistivity of the conductor 215 is designed taking into consideration the potential applied to the conductor 215, and the film thickness of the conductor 215 is set to match the electrical resistivity.
  • the film thickness of the insulator 216 is approximately the same as that of the conductor 215.
  • the insulator 216 functions as an interlayer film, it is preferable that the insulator 216 has a lower dielectric constant than the insulator 222. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.
  • an insulator containing a material with a low dielectric constant as described in the [Insulator] section of embodiment 2 can be used in a single layer or a stacked layer. Silicon oxide and silicon oxynitride are preferable because they are thermally stable. In addition, the top surfaces of the insulators 216 may each be planarized.
  • the concentration of impurities such as water and hydrogen in the insulator 216 is reduced. This can suppress the intrusion of impurities such as water and hydrogen into the channel formation region of the oxide semiconductor 230.
  • the conductor 260 may be a single-layer structure or a multi-layer structure.
  • the conductor 260 is disposed inside an opening formed in the insulator 280. Inside the opening, the conductor 260 is provided so as to cover the top surface of the insulator 222, the side surface of the oxide semiconductor 230, and the top surface of the oxide semiconductor 230 via the insulators 251 and 252. The top surface of the conductor 260 is at the same height as the top surfaces of the insulators 251, 252, and 280.
  • the conductor 260 is provided extending in the channel width direction. With this configuration, when multiple transistors are provided, the conductor 260 functions as wiring.
  • a curved surface may be formed between the side surface of the oxide semiconductor 230 and the top surface of the oxide semiconductor 230.
  • the end of the side surface and the end of the top surface may be curved (hereinafter, also referred to as rounded).
  • the radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide semiconductor 230 in the region overlapping with the conductor 242a or conductor 242b, or smaller than half the length of the region not having the curved surface.
  • the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm.
  • Such a shape can improve the coverage of the oxide semiconductor 230 with the insulator 251, the insulator 252, and the conductor 260.
  • the conductor 260 is shown as having a two-layer structure.
  • the conductor 260 preferably has a conductor 260a and a conductor 260b arranged on the conductor 260a.
  • the conductor 260a is preferably arranged so as to wrap around the bottom and side surfaces of the conductor 260b.
  • the conductors described in the [Conductor] section of embodiment 2 can be used as the conductors 242a and 242b, either in a single layer or in a laminated layer.
  • a conductive material with high conductivity, such as tungsten can be used as the conductors 242a and 242b.
  • the conductors 242a and 242b are made of a conductive material that is difficult to oxidize or a conductive material that has a function of suppressing the diffusion of oxygen.
  • a conductive material that is difficult to oxidize titanium nitride or tantalum nitride can be used.
  • each of the conductors 242a and 242b contains at least a metal and nitrogen. With this structure, excessive oxidation of the conductors 242a and 242b by the oxide semiconductor 230 can be suppressed.
  • conductor 242a and the conductor 242b are each shown as a single layer in Figures 27B and 27C, the present invention is not limited to this.
  • Each of the conductor 242a and the conductor 242b may have a laminated structure.
  • the conductor 242a and the conductor 242b each have a two-layer structure
  • a conductive material that is difficult to oxidize such as a metal nitride, or a conductive material that has a function of suppressing oxygen diffusion, as the lower layer (layer in contact with the oxide semiconductor 230) of each of the conductor 242a and the conductor 242b.
  • This can prevent the conductor 242a and the conductor 242b from being excessively oxidized by the oxygen contained in the oxide semiconductor 230. Therefore, a decrease in the conductivity of the conductor 242a and the conductor 242b can be suppressed.
  • the upper layers of the conductor 242a and the conductor 242b are preferably conductors such as metal layers that have higher conductivity than the lower layers of the conductor 242a and the conductor 242b.
  • conductors such as metal layers that have higher conductivity than the lower layers of the conductor 242a and the conductor 242b.
  • a conductor applicable to the conductor 215b may be used as the upper layers of the conductor 242a and the conductor 242b. This allows the conductor 242a and the conductor 242b to function as wiring or electrodes with high conductivity. In this way, a semiconductor device can be provided in which the conductor 242a and the conductor 242b that function as wiring or electrodes are provided in contact with the upper surface of the oxide semiconductor 230 that functions as an active layer.
  • titanium nitride or tantalum nitride may be used as the lower layer of each of the conductors 242a and 242b, and tungsten may be used as the upper layer of each of the conductors 242a and 242b.
  • tungsten may be used as the upper layer of each of the conductors 242a and 242b.
  • 27A to 27C show a structure in which an insulator 251 and an insulator 252 are provided between an oxide semiconductor 230 and a conductor 260.
  • the oxide semiconductor 230 has a region in contact with the insulator 251. Note that the present invention is not limited to this.
  • an insulator 253 may be provided between the oxide semiconductor 230 and the insulator 222 and the insulator 251.
  • FIG. 28A is an enlarged cross-sectional view of the transistor 200B in the channel width direction.
  • the insulator 253 is preferably made of a material with a low dielectric constant as described in the [Insulator] section of embodiment 2. This configuration can reduce the parasitic capacitance between the conductor 260 and the conductor 242a or conductor 242b. It is also preferable that the concentration of impurities such as water and hydrogen in the insulator 253 is reduced. For the material and configuration of the insulator 253, the details of the insulator 253 described in embodiment 2 can be referred to.
  • the insulator 252 further has a barrier property against oxygen.
  • the insulator 252 is provided between the insulator 253 and the conductor 260. Therefore, the oxygen contained in the insulator 253 can be prevented from diffusing to the conductor 260, and the oxidation of the conductor 260 can be suppressed. In addition, the oxygen contained in the channel formation region of the oxide semiconductor 230 can be prevented from diffusing to the conductor 260, and the formation of oxygen vacancies in the channel formation region can be suppressed.
  • FIG. 28B is an enlarged cross-sectional view of the transistor 200B in the channel width direction.
  • FIG. 28C is an enlarged cross-sectional view of the transistor 200B in the channel width direction.
  • the insulator 254 is preferably a barrier insulator against oxygen described in the [Insulator] section of embodiment 2.
  • the insulator 254 has a region in contact with the oxide semiconductor 230.
  • the insulator 254 has a barrier property against oxygen, and thus can suppress the desorption of oxygen from the oxide semiconductor 230 during heat treatment or the like. Thus, the formation of oxygen vacancies in the oxide semiconductor 230 can be suppressed. This can improve the electrical characteristics and reliability of the transistor 200B.
  • the insulator 254 is in contact with the side surfaces of the conductor 242a and the conductor 242b, the side surfaces of the conductor 242a and the conductor 242b can be suppressed from being oxidized and an oxide film can be suppressed from being formed on the side surfaces. This can suppress the decrease in on-state current or the decrease in field effect mobility of the transistor 200B.
  • the contents of the insulator 254 described in embodiment 2 can be referred to.
  • the insulators 251 to 254 function as part of the gate insulator.
  • the insulators 251 to 254 are provided inside an opening formed in the insulator 280 together with the conductor 260. In order to miniaturize the transistor 200B, it is preferable that the thicknesses of the insulators 251 to 254 are each thin.
  • the thickness of the insulator 251 is preferably within the range of the width of the insulator 51 in the B1-B2 direction as described in embodiment 1.
  • the thickness of the insulator 252 is preferably within the range of the width of the insulator 52 in the B1-B2 direction as described in embodiment 1.
  • the film thickness of the insulator 253 and the insulator 254 is preferably 0.1 nm or more and 10 nm or less, more preferably 0.1 nm or more and 5 nm or less, more preferably 0.5 nm or more and 5 nm or less, more preferably 1 nm or more and less than 5 nm, and even more preferably 1 nm or more and 3 nm or less. Note that it is sufficient that the insulator 253 and the insulator 254 each have a region with the above-mentioned film thickness in at least a portion.
  • the first gate insulator has a two-layer structure of insulators 251 and 252, a three-layer structure of insulators 251 to 253, or a four-layer structure of insulators 251 to 254; however, the present invention is not limited to this.
  • the first gate insulator can have at least one of the insulators 251 to 254.
  • the channel formation region of the oxide semiconductor 230 is sandwiched between insulators (here, insulators 221 and 252) that have barrier properties against hydrogen, so an insulator may be provided between the oxide semiconductor 230 and the insulator 221.
  • an insulator 224 may be provided between the oxide semiconductor 230 and the insulator 222.
  • the insulator 224 is in contact with at least a portion of the oxide semiconductor 230.
  • the insulator 224 has a region that faces the insulator 251 with the oxide semiconductor 230 interposed therebetween.
  • the oxide semiconductor 230 is provided on the insulator 224.
  • FIG. 28D is an enlarged cross-sectional view of the transistor 200B in the channel width direction.
  • the insulator 224 is preferably an insulator containing oxygen, and more preferably a film that releases oxygen when heated.
  • the insulator 224 releases oxygen due to heat applied during a manufacturing process of the transistor 200B, so that oxygen can be supplied to the oxide semiconductor 230.
  • oxygen can be supplied to the oxide semiconductor 230.
  • the insulator 224 is preferably made of a material that can be used for the insulator 280b described in Embodiment 2.
  • the amount of released oxygen molecules from the insulator 224 is preferably greater than or equal to 1.0 ⁇ 10 14 molecules/cm 2 and less than 1.0 ⁇ 10 15 molecules/cm 2.
  • the amount of released oxygen molecules can be measured by thermal desorption spectrometry.
  • the oxide semiconductor 230 is shown as a single layer, but the present invention is not limited to this.
  • the oxide semiconductor 230 may have a stacked structure of multiple oxide layers with different chemical compositions.
  • the oxide semiconductor 230 may have a structure in which multiple types of metal oxides selected from those described in the [Metal Oxide] section of embodiment 2 are appropriately stacked.
  • the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a on the insulator 222 and an oxide semiconductor 230b on the oxide semiconductor 230a.
  • the oxide semiconductor 230a below the oxide semiconductor 230b, it is possible to suppress the diffusion of impurities from a structure formed below the oxide semiconductor 230a to the oxide semiconductor 230b.
  • FIG. 28E is an enlarged cross-sectional view of the transistor 200B in the channel width direction.
  • the oxide semiconductor 230 has a two-layer structure of the oxide semiconductor 230a and the oxide semiconductor 230b is shown, but the present invention is not limited to this.
  • the oxide semiconductor 230 may have a stacked structure of, for example, three or more layers.
  • the contents of the oxide semiconductor 230 described in embodiment 2 can be referred to.
  • microwave treatment in an atmosphere containing oxygen with the conductor 242a and the conductor 242b provided on the oxide semiconductor 230.
  • microwave processing refers to processing using a device having a power source that generates high-density plasma using microwaves.
  • microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • Microwave processing can also be called microwave-excited high-density plasma processing.
  • oxygen gas By performing microwave treatment in an atmosphere containing oxygen, oxygen gas can be turned into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be made to act. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the channel formation region.
  • microwaves or high frequency waves such as RF can also be irradiated onto the channel formation region.
  • VOH in the channel formation region can be split into oxygen vacancies ( VOH ) and hydrogen (H), the hydrogen can be removed from the channel formation region, and the oxygen vacancies can be compensated for with oxygen. Therefore, the hydrogen concentration, oxygen vacancies, and VOH in the channel formation region can be reduced, and the carrier concentration can be lowered.
  • the effects of microwaves, high frequency waves such as RF, oxygen plasma, and the like are shielded by the conductor 242a and the conductor 242b and do not reach the source and drain regions. Furthermore, the effects of oxygen plasma can be reduced by the insulator 280 provided to cover the oxide semiconductor 230, the conductor 242a, and the conductor 242b. As a result, reduction in VOH and excessive supply of oxygen are not generated in the source and drain regions during microwave treatment, and therefore a decrease in carrier concentration can be prevented.
  • the insulating film that becomes the insulator 251 it is preferable to perform microwave treatment in an atmosphere containing oxygen.
  • microwave treatment in an atmosphere containing oxygen through the insulator 251 in this manner, oxygen can be efficiently injected into the channel formation region.
  • the insulator 251 so as to be in contact with the side surface of the conductor 242a, the side surface of the conductor 242b, and the surface of the channel formation region, it is possible to prevent the injection of more oxygen than necessary into the channel formation region and to prevent oxidation of the side surfaces of the conductor 242a and the conductor 242b.
  • the oxygen injected into the channel formation region can take various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions with unpaired electrons).
  • the oxygen injected into the channel formation region can take any one or more of the above forms, and is particularly preferably oxygen radicals.
  • the film quality of the insulator 251 can be improved, thereby improving the reliability of the transistor 200B.
  • oxygen vacancies and VOH can be selectively removed in the channel formation region to make the channel formation region i-type or substantially i-type. Furthermore, excessive supply of oxygen to the source region or drain region can be suppressed, and the state of the n-type region before the microwave treatment can be maintained. This suppresses fluctuations in the electrical characteristics of the transistor 200B, and suppresses variations in the electrical characteristics of the transistor 200B within the substrate surface.
  • oxygen can be efficiently supplied to the channel formation region, making the channel formation region an i-type region. Furthermore, since the amount of oxygen supplied to the source region and drain region is smaller than that to the channel formation region, it is possible to prevent a decrease in the carrier concentration in the source region and drain region.
  • the insulator 280 is preferably a barrier insulator against hydrogen. Since the insulator 280 has a region in contact with the source region of the oxide semiconductor 230 and a region in contact with the drain region, the diffusion of hydrogen contained in the source region and drain region of the oxide semiconductor 230 to the outside can be suppressed, and a reduction in the hydrogen concentration in the source region and drain region can be suppressed. Therefore, the source region and drain region can be made n-type.
  • silicon nitride can be used as the insulator 280.
  • the insulator 280 contains silicon and nitrogen. Since the side and top surfaces of the conductor 242a and the conductor 242b are in contact with the insulator 280, by using silicon nitride as the insulator 280, it is possible to prevent the conductor 242a and the conductor 242b from being oxidized, increasing their resistivity and reducing the on-current.
  • the concentration of impurities such as water and hydrogen in the insulator 280 is reduced.
  • Insulator 280 is shown as a single layer in Figs. 27B to 27D, but the present invention is not limited to this.
  • Insulator 280 may have a laminated structure.
  • insulator 280 may have a laminated structure of insulator 280a and insulator 280b on insulator 280a.
  • silicon nitride as the insulator 280a, more preferably silicon nitride formed by the ALD method, and even more preferably silicon nitride formed by the PEALD method.
  • the ALD method has excellent step coverage and excellent thickness uniformity, so it is suitable for forming thin films and coating surfaces with high aspect ratios.
  • a silicon nitride film is formed by using the PEALD method
  • a precursor containing a halogen such as fluorine, chlorine, bromine, iodine, etc.
  • a plasma treatment is performed in an atmosphere containing a nitriding agent such as N2 , N2O , NH3 , NO, NO2 , or N2O2 , thereby forming a high-quality silicon nitride film.
  • silicon nitride formed by a sputtering method as the insulator 280b. This has a higher film formation rate than the ALD method, and therefore can improve productivity.
  • silicon nitride has a barrier property against hydrogen if its thickness is, for example, 2 nm or more, and has a high barrier property against hydrogen if its thickness is, for example, 3 nm or more. Therefore, when the insulator 280a is formed using a silicon nitride film having a thickness of 2 nm or more, preferably 3 nm or more, the material applicable to the insulator 280b does not have to be a barrier insulator against hydrogen.
  • the insulator 280b may be formed using a material applicable to the insulator 280b described in embodiment 2.
  • an insulator containing oxygen may be used.
  • the insulator 280b preferably has a region with a higher oxygen content than the insulator 280a.
  • the insulator 280b preferably has a region with a higher oxygen content than the insulator 280a. Increasing the oxygen content of the insulator 280b makes it easier to form an i-type region in the oxide semiconductor 230 near the insulator 280b.
  • the insulator 280a is provided between the insulator 280b and the source and drain regions, the amount of oxygen supplied to the source or drain region of the oxide semiconductor 230 can be reduced even when an insulator containing oxygen is used as the insulator 280b.
  • the semiconductor device has a structure that suppresses hydrogen from being mixed into the transistor 200B.
  • an insulator having a function of suppressing hydrogen diffusion is provided so as to cover one or both of the top and bottom of the transistor 200B.
  • examples of the insulator include the insulator 214 and the insulator 283.
  • the insulator 214 provided under the transistor 200B may have a structure similar to that of the insulator 283.
  • one or both of the insulator 214 and the insulator 283 function as a barrier insulator that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 200B to the transistor 200B. Therefore, it is preferable that one or both of the insulator 214 and the insulator 283 have an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N 2 O, NO, NO 2 , etc.), and copper atoms (through which the above impurities are difficult to permeate).
  • one or both of the insulator 214 and the insulator 283 have an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules, etc.) (through which the above oxygen is difficult to permeate).
  • oxygen for example, at least one of oxygen atoms and oxygen molecules, etc.
  • the insulator 214 and the insulator 283 are preferably insulators having a function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.
  • the insulator 283 preferably has high hydrogen barrier properties. This can suppress the diffusion of impurities such as water and hydrogen from an interlayer insulating film arranged above the insulator 283 to the transistor 200B.
  • the oxygen contained in the insulator 280 can be suppressed from diffusing above the transistor 200B.
  • the insulator 283 is provided so as to contact the upper surface of the insulator 280b, the upper surface of the insulator 251, the upper surface of the insulator 252, and the upper surface of the conductor 260, but the present invention is not limited to this.
  • the insulator 282 may be provided between the insulator 283 and the insulator 280b, the insulator 251, the insulator 252, and the conductor 260.
  • the insulator 282 is preferably an insulator capable of adding oxygen to the insulator 280.
  • the insulator 282 contains at least oxygen and aluminum.
  • the insulator 282 or an insulating film to be the insulator 282 is preferably formed by a sputtering method, and more preferably formed in an oxygen-containing atmosphere by a sputtering method. By forming the insulator 282 in an oxygen-containing atmosphere by a sputtering method, oxygen can be added to the insulator 280 while the insulator 282 is being formed. This allows the insulator 280 to contain excess oxygen.
  • a metal oxide having an amorphous structure may have oxygen atoms with dangling bonds, and may have the property of capturing or fixing hydrogen at the dangling bonds.
  • a metal oxide having an amorphous structure may have oxygen atoms with dangling bonds, and may have the property of capturing or fixing hydrogen at the dangling bonds.
  • the insulator 282 is preferably an amorphous structure, but may have a polycrystalline structure in part.
  • the insulator 282 may also have a multi-layer structure in which an amorphous structure layer and a polycrystalline structure layer are stacked.
  • the insulator 282 may have a stacked structure in which a polycrystalline structure layer is formed on an amorphous structure layer.
  • Insulator 282 is shown as a single layer in Figures 30B to 30D, but the present invention is not limited to this. Insulator 282 may have a laminated structure.
  • the insulator 280 is provided so as to contact the upper surface of the conductor 242a and the upper surface of the conductor 242b, but the present invention is not limited to this.
  • the insulator 271a may be provided between the conductor 242a and the insulator 280, and the insulator 271b may be provided between the conductor 242b and the insulator 280.
  • the insulator 271a may be provided on the conductor 242a
  • the insulator 271b may be provided on the conductor 242b.
  • the insulators 271a and 271b function as etching stoppers that protect the conductors 242a and 242b, respectively. Therefore, as shown in Figures 30B and 30D, in a cross-sectional view of the transistor 200B, it is preferable that the side end of the insulator 271a coincides with the side end of the conductor 242a, and the side end of the insulator 271b coincides with the side end of the conductor 242b.
  • the insulators 271a and 271b are inorganic insulators that protect the conductors 242a and 242b, respectively.
  • the insulators 271a and 271b are in contact with the conductors 242a and 242b, respectively, it is preferable that they are inorganic insulators that do not easily oxidize the conductors 242a and 242b. Therefore, it is preferable that the insulators 271a and 271b each have a stacked structure of a first insulator and a second insulator on the first insulator.
  • the first insulator of the insulator 271a and the first insulator of the insulator 271b each use a nitride insulator that is applicable to the insulator 252 so that the conductors 242a and 242b are not easily oxidized.
  • the second insulator of the insulator 271a and the second insulator of the insulator 271b use an oxide insulator that is applicable to the insulator 253.
  • silicon nitride can be used as the first insulator of insulator 271a and the first insulator of insulator 271b
  • silicon oxide can be used as the second insulator of insulator 271a and the second insulator of insulator 271b.
  • the insulating layer that becomes the insulator 271a and the insulator 271b functions as a mask for the conductive layer that becomes the conductor 242a and the conductor 242b, so the conductive layer does not have a curved surface between the side surface and the top surface.
  • the ends where the side surface and the top surface of the conductor 242a and the conductor 242b intersect are angular.
  • the cross-sectional areas of the conductor 242a and the conductor 242b are larger than when the ends have a curved surface.
  • the channel formation region can be made i-type or substantially i-type, and the source region and drain region can be made n-type, and a semiconductor device with good electrical characteristics can be provided. Furthermore, by using the above configuration, the semiconductor device can have good electrical characteristics even when miniaturized or highly integrated. Furthermore, by miniaturizing the transistor 200B, the high-frequency characteristics can be improved. Specifically, the cutoff frequency can be improved.
  • insulator 251 contacts the side surface of insulator 280 at the opening provided in insulator 280, but the present invention is not limited to this configuration.
  • an insulator may be provided between insulator 251 and insulator 280 at the opening.
  • Figs. 31A to 31D are plan views and cross-sectional views of a semiconductor device having a transistor 200C.
  • Fig. 32 shows an enlarged cross-sectional view of the transistor 200C in the channel length direction.
  • Transistor 200C shown in Figures 31A to 31D is also a modified example of transistor 200B shown in Figures 27A to 27D. Specifically, transistor 200C shown in Figures 31A to 31D differs mainly from transistor 200B shown in Figures 27A to 27D in that it has an insulator 255.
  • transistor 200C shown in Figures 31A to 31D differs mainly from transistor 200B shown in Figures 27A to 27D in that it has an insulator 255.
  • conductor 242a and conductor 242b are each shown as having a two-layer structure.
  • Conductor 242a has a layered structure of conductor 242a1 and conductor 242a2 on conductor 242a1.
  • Conductor 242b has a layered structure of conductor 242b1 and conductor 242b2 on conductor 242b1.
  • Conductor 242a1 and conductor 242b1 correspond to the lower layers of conductor 242a and conductor 242b, respectively, and conductor 242a2 and conductor 242b2 correspond to the upper layers of conductor 242a and conductor 242b, respectively.
  • the insulator 255 is disposed inside an opening formed in the insulator 280, and contacts the side of the insulator 280, the side of the conductor 242a2, the side of the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, and the top surface of the insulator 222 in the opening.
  • the insulator 255 can be said to be formed in a sidewall shape in contact with the side wall of the opening formed in the insulator 280.
  • the side wall of the opening corresponds to, for example, the side of the insulator 280, etc. in the opening.
  • Insulator 251 also contacts the side of insulator 255.
  • the insulator 255 preferably has a barrier property against oxygen.
  • the side surfaces of the conductor 242a and the conductor 242b can be prevented from being oxidized and an oxide film can be prevented from being formed on the side surfaces. This can prevent a decrease in the on-state current or a decrease in the field effect mobility of the transistor 200C.
  • the opening in the insulator 280 overlaps with the region between the conductors 242a2 and 242b2.
  • the side of the insulator 280 at the opening coincides with the side of the conductor 242a2 and the side of the conductor 242b2.
  • parts of the conductors 242a1 and 242b1 are formed to protrude inwardly from the opening.
  • the part of the conductor 242a1 on whose upper surface the insulator 255 is formed protrudes further toward the conductor 260 than the conductor 242a2.
  • the part of the conductor 242b1 on whose upper surface the insulator 255 is formed protrudes further toward the conductor 260 than the conductor 242b2.
  • the insulator 255 contacts another portion of the upper surface of the conductor 242a1, another portion of the upper surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. Furthermore, the insulator 251 contacts the upper surface of the oxide semiconductor 230, the side surface of the conductor 242a1, the side surface of the conductor 242b1, and the side surface of the insulator 255.
  • the insulator 255 is formed in a sidewall shape by anisotropic etching in contact with the side wall of the opening in the insulator 280.
  • the insulator 255 is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and has the function of protecting the conductor 242a2 and the conductor 242b2.
  • the insulator 255 also functions as a mask when separating the conductor 242a1 and the conductor 242b1. Therefore, as shown in FIG. 32, in a cross-sectional view of the transistor 200C, it is preferable that the side end of the insulator 255 coincides with the side end of the conductor 242a1 and the side end of the conductor 242b1.
  • insulator 255 is formed in contact with the side surface of conductor 242a2 and the side surface of conductor 242b2, excessive oxidation of conductor 242a2 and conductor 242b2 can be prevented. Furthermore, even when microwave treatment is performed after separating conductor 242a1 and conductor 242b1, the formation of an oxide film on the side surface of conductor 242a and conductor 242b can be suppressed.
  • insulator 255 The portions of insulator 255, insulator 251, insulator 252, and conductor 260 that are placed in an opening in insulator 280 are provided to reflect the shape of the opening.
  • insulator 251 is provided to cover insulator 255 and the bottom and sidewalls of the opening
  • insulator 252 is provided to cover insulator 251
  • conductor 260 is provided to fill the recess in insulator 252.
  • the thickness of the insulator 255 is preferably 0.5 nm to 20 nm, more preferably 0.5 nm to 10 nm, and even more preferably 0.5 nm to 3 nm.
  • the insulator 255 only needs to have a region with the above thickness in at least a portion.
  • the insulator 255 is provided in contact with the side wall of the opening formed in the insulator 280, it is preferable to form the insulator 255 using an ALD method or the like, which has good coverage. If the thickness of the insulator 255 is excessively thick, the time required for forming the insulator 255 by the ALD method will be longer and productivity will decrease, so it is preferable to set the thickness of the insulator 255 to about the above range.
  • the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2.
  • the difference between the distance L1 and the distance L2 is equal to twice the film thickness of the insulator 255.
  • the distance L1 is equal to the distance L2 obtained by adding twice the film thickness of the insulator 255.
  • the film thickness of the insulator 255 refers to the width in the A1-A2 direction of at least a part of the insulator 255.
  • the insulator 255 may have a laminated structure of two or more layers. In this case, at least one layer may be the inorganic insulator that is not easily oxidized.
  • the second insulator of the insulator 255 may be made of the inorganic insulator that is not easily oxidized
  • the first insulator of the insulator 255 may be made of an insulator that is applicable to the insulator 253 (e.g., silicon oxide, etc.).
  • the first insulator of the insulator 255 has a lower dielectric constant than the second insulator of the insulator 255. In this way, by making the insulator 255 into a two-layer structure and increasing the film thickness, the distance between the conductor 260 and the conductor 242a or conductor 242b can be increased, and the parasitic capacitance can be reduced.
  • an insulator 253 may be provided between the oxide semiconductor 230 and the insulator 222 and the insulator 251 (see FIG. 33A).
  • insulator 253 may be provided between insulator 251 and insulator 252. (See FIG. 33B.)
  • an insulator 253 and an insulator 254 may be provided between the oxide semiconductor 230 and the insulator 222 and the insulator 251 (see FIG. 33C).
  • an insulator 224 may be provided between the oxide semiconductor 230 and the insulator 222 (see FIG. 33D).
  • the oxide semiconductor 230 may have a stacked structure of an oxide semiconductor 230a on the insulator 222 and an oxide semiconductor 230b on the oxide semiconductor 230a (see FIG. 33E).
  • Insulator 280 is shown as a single layer in Figs. 31B to 31D, but the present invention is not limited to this.
  • Insulator 280 may have a laminated structure.
  • insulator 280 may have a laminated structure of insulator 280a and insulator 280b on insulator 280a.
  • the region of the insulator 280a that does not overlap with the oxide semiconductor 230 contacts the insulator 222, the side end of the insulator 280a contacts the insulator 255, and the upper end of the insulator 255, the upper end of the insulator 251, and the upper end of the insulator 252 contact the insulator 283.
  • the insulator 280b is separated from the oxide semiconductor 230 by the insulator 280a, the insulator 280b is separated from the insulator 251 by the insulator 255, the conductor 260 is separated from the insulator 251 by the insulator 252, and the conductor 242a2 and the conductor 242b2 are separated from the insulator 251 by the insulator 255.
  • an insulator 282 may be provided between the insulator 283 and the insulator 280b, the insulator 251, the insulator 252, and the conductor 260.
  • an insulator 271a may be provided between the conductor 242a and the insulator 280, and an insulator 271b may be provided between the conductor 242b and the insulator 280.
  • the semiconductor device according to this embodiment has an OS transistor. Since the off-state current of the OS transistor is small, a semiconductor device with low power consumption can be realized. Furthermore, since the OS transistor has high frequency characteristics, a semiconductor device with high operating speed can be realized. Furthermore, by using an OS transistor, a semiconductor device with good electrical characteristics, a semiconductor device with little variation in the electrical characteristics of the transistors, a semiconductor device with large on-state current, and a semiconductor device with high reliability can be realized.
  • a configuration example of a memory device using a memory cell having a transistor described in the above embodiment is described.
  • a configuration example of a memory device is described in which a layer having a functional circuit that has a function of amplifying and outputting a data potential held in the memory cell is provided between layers having stacked memory cells.
  • FIG. 35 illustrates a block diagram of a storage device of one embodiment of the present invention.
  • the memory device 600 shown in FIG. 35 has a drive circuit 621 and a memory array 620.
  • the memory array 620 has a plurality of memory cells 610 and a functional layer 650 having a plurality of functional circuits 651.
  • the memory array 620 has a plurality of memory cells 610 arranged in a matrix of m rows and n columns (m and n are each independently an integer of 2 or more). Also, in FIG. 35, an example is shown in which a functional circuit 651 is provided for each wiring BL that functions as a bit line, and an example is shown in which the functional layer 650 has a plurality of functional circuits 651 provided corresponding to the n wirings BL.
  • the memory cell 610 in the first row and first column is indicated as memory cell 610[1,1] and the memory cell 610 in the mth row and nth column is indicated as memory cell 610[m,n].
  • an arbitrary row may be indicated as row i.
  • An arbitrary column may be indicated as column j.
  • i is an integer between 1 and m
  • j is an integer between 1 and n.
  • the memory cell 610 in the ith row and jth column is indicated as memory cell 610[i,j].
  • the memory array 620 also includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction.
  • the first wiring WL (first row) is indicated as wiring WL[1]
  • the mth wiring WL (mth row) is indicated as wiring WL[m].
  • the first wiring PL (first row) is indicated as wiring PL[1]
  • the mth wiring PL (mth row) is indicated as wiring PL[m].
  • the first wiring BL (first column) is indicated as wiring BL[1]
  • the nth wiring BL (nth column) is indicated as wiring BL[n].
  • the multiple memory cells 610 in the i-th row are electrically connected to the wiring WL (wiring WL[i]) in the i-th row and the wiring PL (wiring PL[i]) in the i-th row.
  • the multiple memory cells 610 in the j-th column are electrically connected to the wiring BL (wiring BL[j]) in the j-th column.
  • DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory) can be applied to the memory array 620.
  • DOSRAM is a RAM having 1T (transistor) 1C (capacitor) type memory cells, and refers to a memory in which the access transistor is an OS transistor.
  • the current flowing between the source and drain that is, the leakage current, is extremely small.
  • DOSRAM can hold a charge corresponding to the data held in the capacitance element (capacitor) for a long time. Therefore, DOSRAM can reduce the frequency of refresh operations compared to DRAM composed of transistors (Si transistors) having silicon in the channel formation region. As a result, it is possible to achieve low power consumption.
  • the frequency characteristics of OS transistors are high, reading and writing of the storage device can be performed at high speed. This makes it possible to provide a storage device with high operating speed.
  • the frequency of the refresh operation needs to be about once per 60 msec.
  • the frequency of the refresh operation can be about once per 10 sec, which is 10 or more times or 100 or more times the frequency of the refresh operation.
  • the frequency of the refresh operation can be set to once per 1 sec to 100 sec, preferably once per 5 sec to 50 sec.
  • multiple memory arrays 620[1] to 620[m] can be stacked.
  • the memory arrays 620[1] to 620[m] of the memory array 620 can be arranged in the vertical direction of the substrate surface on which the driver circuit 621 is provided, thereby improving the memory density of the memory cells 610.
  • the wiring BL functions as a bit line for writing and reading data.
  • the wiring WL functions as a word line for controlling the on/off (conducting or non-conducting) of an access transistor that functions as a switch.
  • the wiring PL functions as a constant potential line connected to a capacitance element. Note that a wiring CL (not shown) can be provided separately as a wiring that has the function of transmitting a backgate potential to the backgate of the OS transistor that is the access transistor.
  • the wiring PL may also have a function of transmitting a backgate potential.
  • the memory cells 610 in each of the memory arrays 620[1] to 620[m] are connected to the functional circuit 651 via wiring BL.
  • the wiring BL can be arranged in a vertical direction to the substrate surface on which the driver circuit 621 is provided.
  • the length of the wiring between the memory array 620 and the functional circuit 651 can be shortened. Therefore, the signal propagation distance between the two circuits connected to the bit line can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay.
  • the functional circuit 651 has a function of amplifying the data potential held in the memory cell 610 and outputting it to the sense amplifier 646 of the driver circuit 621 via the wiring GBL (not shown) described later.
  • This configuration allows a slight potential difference in the wiring BL to be amplified when reading data.
  • the wiring GBL can be arranged in the vertical direction of the substrate surface on which the driver circuit 621 is provided, similar to the wiring BL.
  • the wiring BL is provided in contact with the semiconductor layer of the transistor included in the memory cell 610.
  • the wiring BL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 610.
  • the wiring BL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the memory cell 610.
  • the wiring BL can be said to be a wiring for electrically connecting one of the source or drain of the transistor included in the memory cell 610 in each layer of the memory array 620 to the functional circuit 651 in the vertical direction.
  • the memory array 620 can be stacked on the drive circuit 621. By stacking the drive circuit 621 and the memory array 620, the signal propagation distance between the drive circuit 621 and the memory array 620 can be shortened. This reduces the resistance and parasitic capacitance between the drive circuit 621 and the memory array 620, thereby reducing power consumption and signal delay. In addition, the storage device 600 can be made smaller.
  • the functional circuit 651 can be freely arranged on a circuit using Si transistors, similar to the memory arrays 620[1] to 620[m], by configuring the functional circuit 651 with OS transistors, similar to the transistors in the memory cell 610 of the DOSRAM, and can be easily integrated.
  • the functional circuit 651 By configuring the functional circuit 651 to amplify signals, the circuits in the subsequent stage, such as the sense amplifier 646, can be miniaturized, and the memory device 600 can be miniaturized.
  • the drive circuit 621 has a PSW 622 (power switch), a PSW 623, and a peripheral circuit 631.
  • the peripheral circuit 631 has a peripheral circuit 641, a control circuit 632, and a voltage generation circuit 633.
  • each circuit, signal, and voltage can be selected or removed as needed. Alternatively, other circuits or other signals may be added.
  • Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and signal RDA is an output signal to the outside.
  • Signal CLK is a clock signal.
  • signals BW, CE, and GW are control signals.
  • Signal CE is a chip enable signal
  • signal GW is a global write enable signal
  • signal BW is a byte write enable signal.
  • Signal ADDR is an address signal.
  • Signal WDA is write data
  • signal RDA is read data.
  • Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 632.
  • the control circuit 632 is a logic circuit that has the function of controlling the overall operation of the memory device 600. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 600. Alternatively, the control circuit 632 generates a control signal for the peripheral circuit 641 so that this operation mode is executed.
  • the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 600.
  • the control circuit 632 generates a control signal for the peripheral circuit 641 so that this operation mode is executed.
  • the voltage generation circuit 633 has a function of generating a negative voltage.
  • the signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 633. For example, when an H-level signal is given to the signal WAKE, the signal CLK is input to the voltage generation circuit 633, and the voltage generation circuit 633 generates a negative voltage.
  • the peripheral circuit 641 is a circuit for writing and reading data to the memory cells 610.
  • the peripheral circuit 641 is also a circuit for outputting various signals for controlling the functional circuit 651.
  • the peripheral circuit 641 has a row decoder 642, a row driver 643, a column decoder 644, a column driver 645, a sense amplifier 646, an input circuit 647, and an output circuit 648.
  • the row decoder 642 and the column decoder 644 have the function of decoding the signal ADDR.
  • the row decoder 642 is a circuit for specifying the row to be accessed
  • the column decoder 644 is a circuit for specifying the column to be accessed.
  • the row driver 643 has the function of selecting the wiring WL specified by the row decoder 642.
  • the column driver 645 has the function of writing data to the memory cell 610, the function of reading data from the memory cell 610, the function of retaining the read data, etc.
  • the input circuit 647 has a function of holding a signal WDA.
  • the data held by the input circuit 647 is output to the column driver 645.
  • the output data of the input circuit 647 is the data (Din) to be written to the memory cell 610.
  • the data (Dout) read from the memory cell 610 by the column driver 645 is output to the output circuit 648.
  • the output circuit 648 has a function of holding Dout.
  • the output circuit 648 has a function of outputting Dout to the outside of the memory device 600.
  • the data output from the output circuit 648 is the signal RDA.
  • PSW622 has a function of controlling the supply of VDD to the peripheral circuit 631.
  • PSW623 has a function of controlling the supply of VHM to the row driver 643.
  • the high power supply voltage of the memory device 600 is VDD
  • the low power supply voltage is GND (ground potential).
  • VHM is a high power supply voltage used to set the word line to a high level, and is higher than VDD.
  • the on/off of PSW622 is controlled by signal PON1, and the on/off of PSW623 is controlled by signal PON2.
  • the number of power domains to which VDD is supplied in the peripheral circuit 631 is one, but it is also possible to have multiple power domains. In this case, a power switch can be provided for each power domain.
  • the memory array 620 having memory arrays 620[1] to 620[m] (m is an integer of 2 or more) and a functional layer 650 can be provided by stacking multiple layers of memory arrays 620 on a driving circuit 621. By stacking multiple layers of memory arrays 620, the memory density of the memory cells 610 can be increased.
  • the memory array 620 provided in the first layer is shown as memory array 620[1]
  • the memory array 620 provided in the second layer is shown as memory array 620[2]
  • the memory array 620 provided in the fifth layer is shown as memory array 620[5].
  • Also shown in FIG. 36A are wiring WL, wiring CL, and wiring PL extending in the X direction, and wiring BL extending in the Z direction (the direction perpendicular to the substrate surface on which the drive circuit is provided). Note that to make the drawing easier to understand, some of the wiring WL and wiring PL of each memory array 620 have been omitted.
  • Figure 36B is a schematic diagram illustrating a configuration example of a functional circuit 651 connected to the wiring BL illustrated in Figure 36A, and memory cells 610 included in memory arrays 620[1] to 620[5] connected to the wiring BL.
  • Figure 36B also illustrates a wiring GBL provided between the functional circuit 651 and the driver circuit 621.
  • a configuration in which multiple memory cells (memory cells 610) are electrically connected to one wiring BL is also referred to as a "memory string.”
  • the wiring GBL may be illustrated with a thick line to improve visibility.
  • Figure 36B illustrates an example of a circuit configuration of a memory cell 610 connected to wiring BL.
  • the memory cell 610 includes a transistor 611 and a capacitor 612.
  • the transistor 611, the capacitor 612, and each wiring may also be referred to as wiring BL[1] and wiring WL[1], for example.
  • the transistor 611 corresponds to the transistors 200A to 200E described in the above embodiment. Note that although the transistor 611 illustrated in Figure 36B has a backgate, it may not have a backgate.
  • one of the source and drain of the transistor 611 is connected to the wiring BL.
  • the other of the source and drain of the transistor 611 is connected to one electrode of the capacitor 612.
  • the other electrode of the capacitor 612 is connected to the wiring PL.
  • the gate of the transistor 611 is connected to the wiring WL.
  • the backgate of the transistor 611 is connected to the wiring CL.
  • the wiring PL is a wiring that provides a constant potential to maintain the potential of the capacitor 612.
  • the wiring CL is a constant potential to control the threshold voltage of the transistor 611.
  • the wiring PL and the wiring CL may be at the same potential. In this case, by connecting the two wirings, the number of wirings connected to the memory cell 610 can be reduced.
  • FIG. 37A shows a schematic diagram of a memory device 600 in which a functional circuit 651 and memory arrays 620[1] to 620[m] are repeated as a unit 670. Note that although one wiring GBL is shown in FIG. 37A, the wiring GBL may be provided as appropriate depending on the number of functional circuits 651 provided in the functional layer 650.
  • the wiring GBL is provided in contact with the semiconductor layer of the transistor included in the functional circuit 651.
  • the wiring GBL is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the functional circuit 651.
  • the wiring GBL is provided in contact with a conductor that is provided in contact with a region that functions as the source or drain of the semiconductor layer of the transistor included in the functional circuit 651.
  • the wiring GBL can be said to be a wiring for electrically connecting one of the source and drain of the transistor included in the functional circuit 651 in the functional layer 650 to the driver circuit 621 in the vertical direction.
  • the repeating unit 670 including the functional circuit 651 and the memory arrays 620[1] to 620[m] may be further stacked.
  • the memory device 600A of one embodiment of the present invention can have repeating units 670[1] to 670[p] (p is an integer of 2 or more) as illustrated in FIG. 37B.
  • the wiring GBL is connected to the functional layer 650 of the repeating unit 670.
  • the wiring GBL may be provided as appropriate depending on the number of functional circuits 651.
  • OS transistors are stacked, and wiring that functions as a bit line is arranged in a direction perpendicular to the substrate surface on which the driver circuit 621 is provided.
  • the wiring that functions as a bit line extending from the memory array 620 in a direction perpendicular to the substrate surface can be shortened. Therefore, the parasitic capacitance of the bit line can be significantly reduced.
  • a functional layer 650 having a functional circuit 651 that has a function of amplifying and outputting a data potential held in a memory cell 610 is provided in a layer in which a memory array 620 is provided.
  • a slight potential difference in a wiring BL that functions as a bit line when reading data can be amplified to drive a sense amplifier 646 in a driver circuit 621. Since circuits such as a sense amplifier can be miniaturized, the memory device 600 can be miniaturized. In addition, the memory device can be operated even if the capacitance of a capacitor 612 in the memory cell 610 is reduced.
  • the semiconductor device according to the present invention can also be used for a single-layer memory device having only memory array 620[1].
  • the present invention is not limited to this.
  • a 3T1C type memory cell may be used in a storage device.
  • the memory cell shown in FIG. 38A has transistors 611a, 611b, and 611c, and a capacitive element 612a.
  • the transistors 611a, 611b, and 611c can have the same configuration as the transistor 611
  • the capacitive element 612a can have the same configuration as the capacitive element 612.
  • a RAM with such a configuration may be called NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM).
  • one of the source and drain of the transistor 611a is electrically connected to one of the electrodes of the capacitor 612a and the first gate of the transistor 611b.
  • One of the source and drain of the transistor 611b is electrically connected to one of the source and drain of the transistor 611c.
  • wiring may be provided as appropriate to the first gate of the transistor 611a, the other of the source and drain of the transistor 611a, the second gate of the transistor 611a, the other of the source and drain of the transistor 611b, the second gate of the transistor 611b, the first gate of the transistor 611c, the other of the source and drain of the transistor 611c, the second gate of the transistor 611c, and the other of the electrode of the capacitor 612a.
  • the structure of the memory device can also be modified as appropriate in accordance with these wirings.
  • the transistor 611c may be omitted, and the configuration may include only the transistors 611a and 611b and the capacitor element 612a.
  • the parasitic capacitance of the transistors 611a and 611b is sufficiently large, a configuration without the capacitor element 612a may be used, as shown in FIG. 38C.
  • the memory cell is composed of only the transistors 611a and 611b.
  • FIG. 39 a configuration example of the functional circuit 651 described in FIG. 35 to FIG. 37B and a configuration example of the sense amplifier 646 included in the memory array 620 and the driver circuit 621 will be described.
  • the driver circuit 621 connected to the wiring GBL (wiring GBL_A, wiring GBL_B) connected to the functional circuit 651 (functional circuit 651A, functional circuit 651B) connected to the memory cell 610 (memory cell 610A, memory cell 610B) connected to the different wiring BL (wiring BL_A, wiring BL_B) is illustrated.
  • a precharge circuit 671A, a precharge circuit 671B, a switch circuit 672A, a switch circuit 672B, and a write/read circuit 673 are illustrated.
  • Transistors 652a, 652b, 653a, 653b, 654a, 654b, 655a, and 655b are illustrated as functional circuits 651A and 651B.
  • the transistors 652a, 652b, 653a, 653b, 654a, 654b, 655a, and 655b illustrated in FIG. 39 are OS transistors, similar to the transistor 611 included in the memory cell 610.
  • the functional layer 650 including the functional circuit 651 can be stacked in the same manner as the memory arrays 620[1] to 620[m].
  • the wiring BL_A is connected to the gate of the transistor 652a, and the wiring BL_B is connected to the gate of the transistor 652b.
  • the wiring GBL_A is connected to one of the sources and drains of the transistors 653a and 654a.
  • the wiring GBL_B is connected to one of the sources and drains of the transistors 653b and 654b.
  • the wirings GBL_A and GBL_B are provided vertically like the wirings BL_A and BL_B, and are connected to the transistors of the driver circuit 621. As shown in FIG. 39, the selection signal MUX, the control signal WE, or the control signal RE is applied to the gates of the transistors 653a, 653b, 654a, 654b, 655a, and 655b, respectively.
  • the transistors 681_1 to 681_6 and 682_1 to 682_4 constituting the sense amplifier 646, precharge circuit 671A, and precharge circuit 671B shown in FIG. 39 are composed of Si transistors.
  • the switches 683A to 683D constituting the switch circuit 672A and switch circuit 672B can also be composed of Si transistors.
  • One of the sources or drains of the transistors 653a, 653b, 654a, and 654b is connected to the transistors or switches constituting the precharge circuit 671A, precharge circuit 671B, sense amplifier 646, and switch circuit 672A.
  • the precharge circuit 671A has n-channel transistors 681_1 to 681_3.
  • the precharge circuit 671A is a circuit for precharging the wiring BL_A and the wiring BL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between a high power supply potential (VDD) and a low power supply potential (VSS) in response to a precharge signal provided to the precharge line PCL1.
  • VDD high power supply potential
  • VSS low power supply potential
  • the precharge circuit 671B has n-channel transistors 681_4 to 681_6.
  • the precharge circuit 671B is a circuit for precharging the wiring GBL_A and the wiring GBL_B to an intermediate potential VPC that corresponds to a potential VDD/2 between VDD and VSS in response to a precharge signal provided to the precharge line PCL2.
  • the sense amplifier 646 has p-channel transistors 682_1 and 682_2 and n-channel transistors 682_3 and 682_4 connected to the wiring VHH or wiring VLL.
  • the wiring VHH or wiring VLL is a wiring that has a function of providing VDD or VSS.
  • the transistors 682_1 to 682_4 are transistors that form an inverter loop.
  • the potentials of the precharged wirings BL_A and BL_B change by selecting the memory cells 610A and 610B, and the potentials of the wirings GBL_A and GBL_B are set to VDD or VSS in response to the change.
  • the potentials of the wirings GBL_A and GBL_B can be output to the outside via the switches 683C and 683D, and the write/read circuit 673.
  • the wirings BL_A and BL_B, and the wirings GBL_A and GBL_B correspond to bit line pairs.
  • the write/read circuit 673 controls the writing of data signals according to the signal EN_data.
  • the switch circuit 672A is a circuit for controlling the conduction state between the sense amplifier 646 and the wiring GBL_A and wiring GBL_B.
  • the switch circuit 672A is switched on or off under the control of the switching signal CSEL1.
  • the switches 683A and 683B are n-channel transistors, the switching signal CSEL1 is turned on at a high level and turned off at a low level.
  • the switch circuit 672B is a circuit for controlling the conduction state between the write/read circuit 673 and the bit line pair connected to the sense amplifier 646.
  • the switch circuit 672B is switched on or off under the control of the switching signal CSEL2.
  • the switches 683C and 683D may be the same as the switches 683A and 683B.
  • the memory device 600 can be configured to connect the memory cell 610, the functional circuit 651, and the sense amplifier 646 via wiring BL and wiring GBL that are arranged in the vertical direction, which is the shortest distance.
  • the number of functional layers 650 having transistors that constitute the functional circuit 651 is increased, the load of the wiring BL is reduced, thereby shortening the write time and making it easier to read data.
  • each transistor in the functional circuits 651A and 651B is controlled in response to control signals WE, RE, and a selection signal MUX.
  • Each transistor can output the potential of the wiring BL to the driver circuit 621 via the wiring GBL in response to the control signal and selection signal.
  • the functional circuits 651A and 651B can function as sense amplifiers composed of OS transistors. With this configuration, a slight potential difference in the wiring BL can be amplified during reading to drive the sense amplifier 646 using Si transistors.
  • the X direction is parallel to the channel width direction of the illustrated transistor
  • the Y direction is perpendicular to the X direction
  • the Z direction is perpendicular to the X and Y directions.
  • the memory cell 610 includes a transistor 611 and a capacitor 612.
  • An insulator 285 is provided over the transistor 611, and an insulator 284 is provided over the insulator 285.
  • the insulator 285 and the insulator 284 may be made of an insulator applicable to the insulator 216.
  • the transistor 611 has a similar structure to the transistor 200B described in the previous embodiment, and the same components are denoted by the same reference numerals. For details of the transistor 200B, the previous embodiment can be referred to.
  • a conductor 240 (conductor 240a and conductor 240b) is provided in contact with one of the source electrode and drain electrode (conductor 242b) of the transistor 611.
  • the conductor 240 is provided to extend in the Z direction and functions as a wiring BL.
  • the capacitor 612 has a conductor 453 on the conductor 242a, an insulator 454 on the conductor 453, and a conductor 460 (conductor 460a and conductor 460b) on the insulator 454.
  • conductor 453, insulator 454, and conductor 460 are disposed inside the openings provided in insulators 280, 283, and 285, respectively.
  • the ends of conductor 453, insulator 454, and conductor 460 are located at least on insulator 283, and preferably on insulator 285.
  • Insulator 454 is provided so as to cover the end of conductor 453. This allows electrical insulation between conductor 453 and conductor 460.
  • the memory device can be miniaturized or highly integrated.
  • the conductor 453 has a region that functions as one electrode (lower electrode) of the capacitor 612.
  • the insulator 454 has a region that functions as a dielectric of the capacitor 612.
  • the conductor 460 has a region that functions as the other electrode (upper electrode) of the capacitor 612.
  • the upper part of the conductor 260 can be extended to function as the wiring PL shown in Figures 36A and 36B.
  • the capacitor 612 constitutes a MIM (Metal-Insulator-Metal) capacitor.
  • the conductor 242a overlapping the oxide semiconductor 230 functions as an electrode electrically connected to the conductor 453 of the capacitor 612.
  • the conductor 453 and the conductor 460 of the capacitor 612 can be formed using various conductors that can be used for the conductor 215 or the conductor 260, respectively.
  • the conductor 453 and the conductor 460 are preferably formed using a film formation method with good coating properties, such as an ALD method or a CVD method.
  • the conductor 453 can be made of titanium nitride or tantalum nitride formed using an ALD method or a CVD method.
  • the upper surface of the conductor 242a contacts the lower surface of the conductor 453.
  • the contact resistance between the conductor 453 and the conductor 242a can be reduced.
  • titanium nitride formed by ALD or CVD can be used as the conductor 460a
  • tungsten formed by CVD can be used as the conductor 460b. Note that if the adhesion of tungsten to the insulator 454 is sufficiently high, a single layer structure of tungsten formed by CVD can be used as the conductor 460.
  • the insulator 454 of the capacitor 612 is preferably made of a high dielectric constant (high-k) material as described in the previous embodiment. By using such a high-k material, the insulator 454 can be made thick enough to suppress leakage current and the capacitance of the capacitor 612 can be sufficiently ensured.
  • the insulator 454 is preferably formed by a film formation method with good coating properties, such as an ALD method or a CVD method.
  • insulators made of the above materials in a laminated structure, and it is preferable to use a laminated structure of a material with a high relative dielectric constant (high-k) and a material with a higher dielectric strength than the high relative dielectric constant (high-k).
  • high-k high relative dielectric constant
  • an insulator laminated in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used as the insulator 454.
  • an insulator laminated in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used.
  • an insulating film laminated in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used.
  • an insulator with a relatively high dielectric strength such as aluminum oxide in a laminated structure the dielectric strength is improved and electrostatic breakdown of the capacitance element 612 can be suppressed.
  • a material that can have ferroelectricity may be used as the insulator 454.
  • materials that can have ferroelectricity include metal oxides such as hafnium oxide, zirconium oxide, and HfZrO x (X is a real number greater than 0).
  • materials that can have ferroelectricity include a material obtained by adding an element J1 (here, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to hafnium oxide.
  • the ratio of the number of atoms of hafnium to the number of atoms of the element J1 can be set appropriately, and for example, the ratio of the number of atoms of hafnium to the number of atoms of the element J1 may be set to 1:1 or close to 1:1.
  • materials that can have ferroelectricity include a material obtained by adding an element J2 (here, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) to zirconium oxide.
  • the ratio of the number of zirconium atoms to the number of atoms of element J2 can be set appropriately, for example, the ratio of the number of zirconium atoms to the number of atoms of element J2 may be set to 1:1 or close to 1.
  • piezoelectric ceramics having a perovskite structure such as lead titanate (PbTiO x ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuthate tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used.
  • examples of materials that may have ferroelectricity include metal nitrides having element M1, element M2, and nitrogen.
  • element M1 is one or more selected from aluminum, gallium, indium, etc.
  • element M2 is one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. It should be noted that the ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Also, metal oxides having element M1 and nitrogen may have ferroelectricity even if they do not contain element M2.
  • examples of materials that may have ferroelectricity include materials in which element M3 is added to the above metal nitride.
  • element M3 is one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc.
  • the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set appropriately.
  • examples of materials that can have ferroelectricity include perovskite-type oxynitrides such as SrTaO 2 N and BaTaO 2 N, and GaFeO 3 with a ⁇ -alumina structure.
  • metal oxides and metal nitrides are given as examples, but the present invention is not limited to these.
  • metal oxynitrides in which nitrogen is added to the above-mentioned metal oxides, or metal oxynitrides in which oxygen is added to the above-mentioned metal nitrides, etc. may be used.
  • the insulator 454 can have a layered structure made of multiple materials selected from the materials listed above.
  • the crystal structure (characteristics) of the materials listed above can change not only depending on the film formation conditions but also on various processes, in this specification, not only materials that exhibit ferroelectricity are called ferroelectrics, but also materials that can have ferroelectricity.
  • a ferroelectric material is an insulator that is polarized when an electric field is applied from the outside, and the polarization remains even when the electric field is reduced to zero. For this reason, a nonvolatile memory element can be formed using a capacitance element (hereinafter sometimes referred to as a ferroelectric capacitor) that uses this material as a dielectric.
  • a nonvolatile memory element using a ferroelectric capacitor is sometimes called a FeRAM (Ferroelectric Random Access Memory), a ferroelectric memory, etc.
  • a ferroelectric memory has a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to one terminal of the ferroelectric capacitor. Therefore, when a ferroelectric capacitor is used as the capacitance element 612, the memory device shown in this embodiment functions as a ferroelectric memory.
  • the insulators 280, 283, and 285 function as barrier insulators, it is preferable to set the film thickness according to the barrier properties required for the semiconductor device.
  • the film thickness of the conductor 260 that functions as a gate electrode is determined according to the film thickness of the insulator 280, it is preferable to set the film thickness of the insulator 280 according to the film thickness of the conductor 260 required for the semiconductor device.
  • the thickness of the insulator 285 may be set in the range of 50 nm to 250 nm, and the depth of the opening may be set to approximately 150 nm to 350 nm.
  • the capacitor 612 can have a sufficient capacitance, and the height of one layer in a semiconductor device in which multiple memory cell layers are stacked can be prevented from becoming excessively high.
  • a configuration may be used in which the capacitance of the capacitor provided in each memory cell is different in each of the multiple memory cell layers. In this configuration, for example, the thickness of the insulator 285 provided in each memory cell layer may be different.
  • the sidewall of the opening may be perpendicular or approximately perpendicular to the top surface of the insulator 222, or may be tapered.
  • the coverage of the conductor 453 or the like provided in the opening of the insulator 285 or the like can be improved, and defects such as voids can be reduced.
  • the conductor 242b provided so as to overlap the oxide semiconductor 230 functions as wiring electrically connected to the conductor 240.
  • the upper surface and side end of the conductor 242b are electrically connected to the conductor 240 extending in the Z direction.
  • the upper surface and side end of the conductor 242b are in contact with the conductor 240.
  • the conductor 240 By directly contacting the conductor 240 with at least one of the upper surface and side end of the conductor 242b, there is no need to provide a separate electrode for connection, and the area occupied by the memory array can be reduced. In addition, the integration density of memory cells is improved, and the memory capacity of the storage device can be increased. Note that it is preferable that the conductor 240 contacts a part of the upper surface and the side end of the conductor 242b. By contacting multiple surfaces of the conductor 242b with the conductor 240, the contact resistance between the conductor 240 and the conductor 242b can be reduced.
  • the conductor 240 is disposed within openings formed in the insulators 216, 221, 222, 280, 283, 285, and 284.
  • the insulator 241 is provided in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner walls of the openings of the insulators 216, 221, 222, 280, 283, 285, and 284. The insulator 241 is also formed on the side surface of the oxide semiconductor 230, which is formed to protrude inward of the opening. Here, at least a portion of the conductor 242b is exposed from the insulator 241 and is in contact with the conductor 240. In other words, the conductor 240 is provided so as to fill the inside of the opening through the insulator 241.
  • the top of the insulator 241 formed below the conductor 242b is preferably located below the top surface of the conductor 242b.
  • This configuration allows the conductor 240 to be in contact with at least a portion of the side end of the conductor 242b.
  • the insulator 241 formed below the conductor 242b preferably has a region in contact with the side surface of the oxide semiconductor 230. This configuration can prevent impurities such as water and hydrogen contained in the insulator 280 from being mixed into the oxide semiconductor 230 through the conductor 240.
  • the sidewall of the opening may be perpendicular or approximately perpendicular to the upper surface of the insulator 222, or may be tapered. By making the sidewall tapered, the coverage of the insulator 241 and the like provided in the opening is improved.
  • the memory device 600 has a driver circuit 621, which is a layer having transistors 310 and the like, a functional layer 650, which is a layer having transistors 652, 653, 654, 655, and the like on the driver circuit 621, and memory arrays 620[1] to 620[m] on the functional layer 650.
  • the transistor 652 corresponds to the transistors 652a and 652b
  • the transistor 653 corresponds to the transistors 653a and 653b
  • the transistor 654 corresponds to the transistors 654a and 654b
  • the transistor 655 corresponds to the transistors 655a and 655b.
  • Figure 41 illustrates a transistor 310 included in the driver circuit 621.
  • the transistor 310 is provided over a substrate 311 and includes a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes a part of the substrate 311, and a low-resistance region 314a and a low-resistance region 314b that function as a source region or a drain region.
  • the transistor 310 may be a p-channel transistor or an n-channel transistor.
  • a single crystal silicon substrate can be used as the substrate 311.
  • the semiconductor region 313 (part of the substrate 311) in which the channel is formed has a convex shape.
  • the side and top surface of the semiconductor region 313 are covered with a conductor 316 via an insulator 315.
  • the conductor 316 may be made of a material that adjusts the work function.
  • Such a transistor 310 is also called a FIN type transistor because it uses the convex portion of the semiconductor substrate.
  • an insulator that contacts the upper part of the convex portion and functions as a mask for forming the convex portion may be provided.
  • a semiconductor film having a convex shape may be formed by processing an SOI substrate.
  • transistor 310 shown in FIG. 41 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • a wiring layer having an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design.
  • a conductor having the function of a plug or wiring may be given the same symbol as a group of multiple structures. Also, in this specification, the wiring and the plug electrically connected to the wiring may be integrated. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film.
  • Conductors 328 and the like are embedded in the insulators 320 and 322.
  • Conductors 330 and the like are embedded in the insulators 324 and 326.
  • the conductors 328 and 330 function as contact plugs or wiring.
  • the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape underneath.
  • the top surface of the insulator 322 may be planarized by a CMP process to enhance flatness.
  • Insulators that can be used as interlayer films include insulating oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, and metal nitride oxides.
  • the parasitic capacitance that occurs between wiring can be reduced. Therefore, it is best to select the material according to the function of the insulator.
  • FIG. 41 illustrates transistors 652, 653, and 655 in the functional layer 650.
  • the transistors 652, 653, and 655 have the same configuration as the transistor 611 in the memory cell 610.
  • the transistors 652, 653, and 655 have their sources and drains connected in series.
  • An insulator 208 is provided on the transistors 652, 653, and 655, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided on the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided on the insulator 210, and an insulator 214 is provided on the insulator 212. A part of the conductor 240 provided in the memory array 620[1] is embedded in the openings formed in the insulators 212 and 214.
  • the insulators 208 and 210 can use an insulator applicable to the insulator 216. Furthermore, the insulator 212 can use an insulator applicable to the insulator 283. Furthermore, the insulator 214 can use an insulator applicable to the insulator 282.
  • the bottom surface of the conductor 207 is in contact with the top surface of the conductor 260 of the transistor 652.
  • the top surface of the conductor 207 is in contact with the bottom surface of the conductor 209.
  • the top surface of the conductor 209 is in contact with the bottom surface of the conductor 240 provided in the memory array 620[1].
  • Each of the memory arrays 620[1] to 620[m] includes a plurality of memory cells 610.
  • the conductor 240 of each memory cell 610 is electrically connected to the conductor 240 in the layer above and the conductor 240 in the layer below.
  • the conductor 240 is shared between adjacent memory cells 610.
  • the configuration on the right side and the configuration on the left side are arranged symmetrically with respect to the conductor 240.
  • multiple memory arrays 620[1] to 620[m] can be stacked.
  • the memory arrays 620[1] to 620[m] of the memory array 620 can be arranged in the vertical direction of the substrate surface on which the driver circuit 621 is provided, thereby improving the memory density of the memory cells 610.
  • the memory array 620 can also be manufactured by repeatedly using the same manufacturing process in the vertical direction. The memory device 600 can reduce the manufacturing cost of the memory array 620.
  • the memory cell shown in FIG. 42 includes a transistor 310, a transistor 200 provided above the transistor 310, and a capacitor 400 provided above the transistor 310 and the transistor 200. Note that any of the transistors 200A to 200E described in the previous embodiment can be used as the transistor 200.
  • the transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. Since the off-state current of the transistor 200 is small, the use of the transistor 200 in a memory device makes it possible to retain stored contents for a long period of time. In other words, since no refresh operation is required or the frequency of refresh operation is extremely low, the power consumption of the memory device can be sufficiently reduced.
  • the wiring 1001 is electrically connected to the source of the transistor 310, and the wiring 1002 is electrically connected to the drain of the transistor 310.
  • the wiring 1003 is electrically connected to one of the source and drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200.
  • the gate of the transistor 310 and the other of the source and drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 400, and the wiring 1005 is electrically connected to the other electrode of the capacitor 400.
  • the memory device shown in FIG. 42 can be arranged in a matrix to form a memory cell array.
  • the transistor 310 For the configuration of the transistor 310, the contents described above in ⁇ Configuration example of memory device 600> can be referred to. Note that the transistor 310 shown in FIG. 42 is just an example, and the structure is not limited thereto, and an appropriate transistor can be used depending on the circuit configuration or driving method.
  • the capacitor 400 has a conductor 410 that functions as a first electrode, a conductor 420 that functions as a second electrode, and an insulator 430 that functions as a dielectric.
  • Each of the conductors 410 and 420 can be a single layer or a laminate of the conductors described in the [Conductor] section of the previous embodiment.
  • the conductor 412 can be formed, for example, at the same time as the conductor 410. Note that the conductor 412 functions as a plug or wiring that electrically connects to the capacitor 400, the transistor 200, or the transistor 310.
  • the conductor 412 and the conductor 410 are shown to have a single-layer structure, but the present invention is not limited to this structure and may have a stacked structure of two or more layers.
  • a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.
  • the insulator 430 is preferably an insulator that can be used as the insulator 283 shown in the above embodiment.
  • the insulator 430 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, or the like, and can be provided as a stacked layer or a single layer.
  • the capacitance element 400 can ensure sufficient capacitance by having an insulator with a high dielectric constant (high-k), and the capacitance element 400 can have improved dielectric strength by having an insulator with high dielectric strength, thereby suppressing electrostatic breakdown of the capacitance element 400.
  • a material with high dielectric strength such as silicon oxynitride
  • high-k high dielectric constant
  • high-dielectric constant (high-k) materials materials with a high relative dielectric constant
  • examples of high-dielectric constant (high-k) materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.
  • materials with high dielectric strength include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with voids, and resin.
  • a wiring layer having interlayer films, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers may be provided depending on the design.
  • an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order as an interlayer film.
  • a capacitor 400 or a conductor 328 and a conductor 330 electrically connected to the transistor 200 are embedded in the insulator 320, the insulator 322, the insulator 324, and the insulator 326.
  • a wiring layer may be provided on the insulator 326 and the conductor 330.
  • the insulator 350, the insulator 352, and the insulator 354 are stacked in this order.
  • the conductor 356 is formed on the insulator 350, the insulator 352, and the insulator 354.
  • the conductor 356 functions as a plug or wiring.
  • conductor 213 is embedded in insulator 210, insulator 212, insulator 214, and insulator 216. Note that conductor 213 functions as a plug or wiring that electrically connects to capacitor 400 or transistor 310.
  • a conductor 218 is embedded in the insulator 216.
  • the conductor 218 may be provided so as to be in contact with a portion of the side surface and the top surface of the conductor 213.
  • the conductor 218 may be provided so as to be in contact with a portion of the conductor 213 exposed from the insulator 214.
  • the conductor 218 may be formed, for example, at the same time as the conductor (conductor 215) that constitutes the transistor 200. This simplifies the manufacturing process of the memory device and improves productivity.
  • the conductor 218 functions as a plug or wiring that electrically connects to the capacitor 400, the transistor 200, or the transistor 310. Furthermore, an insulator 450 is provided over the conductor 420 and the insulator 430.
  • the chip 1200 shown in Figures 43A and 43B has multiple circuits (systems) implemented. This technology of integrating multiple circuits (systems) on a single chip is sometimes called a system on chip (SoC).
  • SoC system on chip
  • the chip 1200 has a CPU 1211, a GPU 1212, one or more analog calculation units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc.
  • Bumps (not shown) are provided on the chip 1200, which are connected to the first surface of the package substrate 1201, as shown in FIG. 43B.
  • a plurality of bumps 1202 are provided on the back surface of the first surface of the package substrate 1201, which are connected to the motherboard 1203.
  • the motherboard 1203 may be provided with a storage device such as a DRAM 1221 or a flash memory 1222.
  • a storage device such as a DRAM 1221 or a flash memory 1222.
  • the DOSRAM described in the above embodiment can be used for the DRAM 1221. This allows the DRAM 1221 to consume less power, operate at a higher speed, and have a larger capacity.
  • the CPU 1211 preferably has multiple CPU cores.
  • the GPU 1212 preferably has multiple GPU cores.
  • the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data.
  • a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200.
  • the memory may be the DOSRAM described above.
  • the GPU 1212 is suitable for parallel calculation of a large amount of data, and may be used for image processing or multiply-and-accumulate operations. By providing the GPU 1212 with an image processing circuit or a multiply-and-accumulate circuit using the OS transistor described in the previous embodiment, it becomes possible to perform image processing or multiply-and-accumulate operations with low power consumption.
  • the wiring between the CPU 1211 and GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of the calculation results from the GPU 1212 to the CPU 1211 after calculation in the GPU 1212 can be performed quickly.
  • the analog calculation unit 1213 has one or both of an A/D (analog/digital) conversion circuit and a D/A (digital/analog) conversion circuit.
  • the analog calculation unit 1213 may also be provided with the above-mentioned product-sum calculation circuit.
  • the memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.
  • the interface 1215 has an interface circuit with externally connected devices such as a display device, a speaker, a microphone, a camera, and a controller. Controllers include a mouse, a keyboard, and a game controller. Examples of such interfaces that can be used include a Universal Serial Bus (USB) and a High-Definition Multimedia Interface (HDMI (registered trademark)).
  • USB Universal Serial Bus
  • HDMI High-Definition Multimedia Interface
  • the network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.
  • LAN Local Area Network
  • circuits can be formed in chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the manufacturing process, and chip 1200 can be manufactured at low cost.
  • the package substrate 1201 on which the chip 1200 having the GPU 1212 is provided, the motherboard 1203 on which the DRAM 1221 and the flash memory 1222 are provided can be referred to as a GPU module 1204.
  • the GPU module 1204 has a chip 1200 using SoC technology, so its size can be reduced. In addition, since it excels in image processing, it is suitable for use in portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game consoles.
  • the product-sum calculation circuit using the GPU 1212 can execute techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), so the chip 1200 can be used as an AI chip, and the GPU module 1204 can be used as an AI system module.
  • DNN deep neural networks
  • CNN convolutional neural networks
  • RNN recurrent neural networks
  • DBM deep Boltzmann machines
  • DBN deep belief networks
  • FIG. 44A shows a perspective view of a substrate (mounting substrate 704) on which an electronic component 700 is mounted.
  • the electronic component 700 shown in FIG. 44A has a semiconductor device 710 in a mold 711. In FIG. 44A, some parts are omitted in order to show the inside of the electronic component 700.
  • the electronic component 700 has lands 712 on the outside of the mold 711. The lands 712 are electrically connected to electrode pads 713, and the electrode pads 713 are electrically connected to the semiconductor device 710 via wires 714.
  • the electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounting substrate 704.
  • the semiconductor device 710 also has a drive circuit layer 715 and a memory layer 716.
  • the memory layer 716 is configured by stacking a plurality of memory cell arrays.
  • the stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In the monolithic stacked configuration, each layer can be connected without using a through electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as a Cu-Cu direct bonding.
  • a so-called on-chip memory configuration can be formed in which the memory is formed directly on the processor.
  • the on-chip memory configuration makes it possible to increase the speed of the operation of the interface between the processor and the memory.
  • the memory as an on-chip memory, it is possible to reduce the size of the connection wiring, etc., compared to technologies that use through electrodes such as TSVs, and it is also possible to increase the number of connection pins. Increasing the number of connection pins enables parallel operation, making it possible to improve the memory bandwidth (also called memory bandwidth).
  • the memory cell arrays in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked.
  • OS transistors By forming the memory cell arrays in a monolithic stacked configuration, it is possible to improve either or both of the memory bandwidth and the memory access latency.
  • the bandwidth is the amount of data transferred per unit time
  • the access latency is the time from access to the start of data exchange.
  • Si transistors when Si transistors are used for the memory layer 716, it is difficult to form a monolithic stacked configuration compared to OS transistors. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked configuration.
  • the semiconductor device 710 may also be referred to as a die.
  • a die refers to a chip piece obtained during the manufacturing process of a semiconductor chip by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and cutting it into a dice shape.
  • Semiconductor materials that can be used for the die include, for example, silicon (Si), silicon carbide (SiC), and gallium nitride (GaN).
  • Si silicon
  • SiC silicon carbide
  • GaN gallium nitride
  • a die obtained from a silicon substrate also called a silicon wafer
  • a silicon die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.
  • Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module).
  • Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and multiple semiconductor devices 710 provided on interposer 731.
  • Electronic component 730 shows an example in which semiconductor device 710 is used as a high bandwidth memory (HBM).
  • Semiconductor device 735 can be used in integrated circuits such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA).
  • CPU central processing unit
  • GPU graphics processing unit
  • FPGA field programmable gate array
  • the package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate.
  • the interposer 731 may be, for example, a silicon interposer or a resin interposer.
  • the interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches.
  • the multiple wirings are provided in a single layer or multiple layers.
  • the interposer 731 also functions to electrically connect the integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732.
  • the interposer may be called a "rewiring substrate” or "intermediate substrate.”
  • a through electrode may be provided in the interposer 731, and the integrated circuits and the package substrate 732 may be electrically connected using the through electrode.
  • a TSV may be used as the through electrode.
  • the interposer on which the HBM is mounted is required to have fine, high-density wiring. Therefore, it is preferable to use a silicon interposer for the interposer on which the HBM is mounted.
  • silicon interposers In addition, in SiP and MCM using silicon interposers, deterioration in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. In addition, since the surface of the silicon interposer is highly flat, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use silicon interposers in 2.5D packages (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.
  • a composite structure may be formed by combining a memory cell array stacked using TSVs and a monolithic stacking memory cell array.
  • a heat sink may be provided overlapping the electronic component 730.
  • electrodes 733 may be provided on the bottom of the package substrate 732.
  • FIG. 44B shows an example in which the electrodes 733 are formed from solder balls. By providing solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved.
  • the electrodes 733 may also be formed from conductive pins. By providing conductive pins in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.
  • the electronic component 730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA.
  • mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).
  • FIG. 45A a perspective view of an electronic device 6500 is shown in FIG. 45A.
  • the electronic device 6500 shown in FIG. 45A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a memory device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like.
  • the electronic device 6600 shown in FIG. 45B is an information terminal that can be used as a notebook personal computer.
  • the electronic device 6600 includes a housing 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display portion 6615, a control device 6616, and the like.
  • the control device 6616 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6615, the control device 6616, and the like. Note that the use of the semiconductor device of one embodiment of the present invention for the above-described control device 6509 and the control device 6616 is preferable because power consumption can be reduced.
  • Fig. 45C shows a perspective view of the large scale computer 5600.
  • the large scale computer 5600 shown in Fig. 45C has a rack 5610 housing a plurality of rack-mounted computers 5620.
  • the large scale computer 5600 may also be called a supercomputer.
  • the computer 5620 can have the configuration shown in the perspective view in FIG. 45D, for example.
  • the computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals.
  • a PC card 5621 is inserted into the slot 5631.
  • the PC card 5621 has connection terminals 5623, 5624, and 5625, each of which is connected to the motherboard 5630.
  • the PC card 5621 shown in FIG. 45E is an example of a processing board equipped with a CPU, a GPU, a storage device, and the like.
  • the PC card 5621 has a board 5622.
  • the board 5622 also has a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629.
  • FIG. 45E illustrates semiconductor devices other than the semiconductor devices 5626, 5627, and 5628, but for those semiconductor devices, please refer to the description of the semiconductor devices 5626, 5627, and 5628 described below.
  • connection terminal 5629 has a shape that allows it to be inserted into the slot 5631 of the motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630.
  • An example of the standard for the connection terminal 5629 is PCIe.
  • Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB, SATA (Serial ATA), and SCSI (Small Computer System Interface). In addition, when a video signal is output from connection terminals 5623, 5624, and 5625, examples of standards for each include HDMI (registered trademark).
  • the semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.
  • the semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5627 include an FPGA, a GPU, and a CPU.
  • the electronic component 730 can be used as the semiconductor device 5627.
  • the semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring provided on the board 5622 using a reflow method.
  • Examples of the semiconductor device 5628 include a memory device.
  • the electronic component 700 can be used as the semiconductor device 5628.
  • the mainframe computer 5600 can also function as a parallel computer. By using the mainframe computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for artificial intelligence learning and inference, for example.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment, such as equipment for processing and storing data.
  • the semiconductor device of one embodiment of the present invention can include an OS transistor.
  • the OS transistor has small changes in electrical characteristics due to radiation exposure.
  • the OS transistor has high resistance to radiation and can be preferably used in an environment where radiation may be incident.
  • the OS transistor can be preferably used in outer space.
  • Figure 46 shows an artificial satellite 6800 as an example of space equipment.
  • the artificial satellite 6800 has a body 6801, a solar panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807.
  • a planet 6804 is shown in outer space.
  • outer space refers to an altitude of 100 km or more, for example, but the outer space described in this specification may also include the thermosphere, mesosphere, and stratosphere.
  • the secondary battery 6805 may be provided with a battery management system (also called BMS) or a battery control circuit.
  • BMS battery management system
  • the use of OS transistors in the above-mentioned battery management system or battery control circuit is preferable because it has low power consumption and high reliability even in space.
  • outer space is an environment with radiation levels 100 times higher than on Earth.
  • radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, and meson rays.
  • the solar panel 6802 When sunlight is irradiated onto the solar panel 6802, the power required for the operation of the satellite 6800 is generated. However, for example, in a situation where the solar panel is not irradiated with sunlight, or where the amount of sunlight irradiating the solar panel is small, the amount of power generated is small. Therefore, there is a possibility that the power required for the operation of the satellite 6800 will not be generated. In order to operate the satellite 6800 even in a situation where the generated power is small, it is advisable to provide the satellite 6800 with a secondary battery 6805. Note that the solar panel may be called a solar cell module.
  • the artificial satellite 6800 can generate a signal.
  • the signal is transmitted via the antenna 6803, and can be received, for example, by a receiver installed on the ground or by another artificial satellite.
  • the position of the receiver that received the signal can be measured.
  • the artificial satellite 6800 can constitute a satellite positioning system.
  • the control device 6807 has a function of controlling the artificial satellite 6800.
  • the control device 6807 is configured using, for example, one or more of a CPU, a GPU, and a storage device.
  • the control device 6807 is preferably a semiconductor device according to one embodiment of the present invention.
  • an OS transistor Compared to a Si transistor, an OS transistor has smaller fluctuations in electrical characteristics due to radiation exposure. In other words, an OS transistor has high reliability even in an environment where radiation may be incident, and can be preferably used.
  • the artificial satellite 6800 can also be configured to have a sensor.
  • the artificial satellite 6800 can have the function of detecting sunlight reflected off an object on the ground.
  • the artificial satellite 6800 can have a thermal infrared sensor, the artificial satellite 6800 can have the function of detecting thermal infrared rays emitted from the earth's surface. From the above, the artificial satellite 6800 can have the function of, for example, an earth observation satellite.
  • an artificial satellite is illustrated as an example of space equipment, but the present invention is not limited thereto.
  • the semiconductor device of one embodiment of the present invention can be suitably used in space equipment such as a spaceship, a space capsule, and a space probe.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the advantages of being able to achieve a wider memory bandwidth and having higher radiation resistance.
  • the semiconductor device can be suitably used in a storage system applied to a data center or the like.
  • the data center is required to perform long-term data management, such as ensuring the immutability of data.
  • long-term data management such as ensuring the immutability of data.
  • a semiconductor device By using a semiconductor device according to one embodiment of the present invention in a storage system applied to a data center, it is possible to reduce the power required to store data and to miniaturize the semiconductor device that stores the data. This makes it possible to miniaturize the storage system, miniaturize the power source for storing data, and reduce the scale of cooling equipment. This makes it possible to save space in the data center.
  • the semiconductor device of one embodiment of the present invention consumes less power, and therefore heat generation from the circuit can be reduced. This reduces adverse effects of heat generation on the circuit itself, peripheral circuits, and modules. Furthermore, by using the semiconductor device of one embodiment of the present invention, a data center that operates stably even in a high-temperature environment can be realized. This improves the reliability of the data center.
  • Figure 47 shows a storage system applicable to a data center.
  • the storage system 6900 shown in Figure 47 has multiple servers 6901sb as hosts 6901 (illustrated as Host Computer). It also has multiple storage devices 6903md as storage 6903 (illustrated as Storage).
  • the host 6901 and storage 6903 are shown connected via a storage area network 6904 (illustrated as SAN: Storage Area Network) and a storage control circuit 6902 (illustrated as Storage Controller).
  • SAN Storage Area Network
  • the host 6901 corresponds to a computer that accesses data stored in the storage 6903.
  • the hosts 6901 may be connected to each other via a network.
  • Storage 6903 uses flash memory to reduce data access speed, i.e. the time required to store and output data, but this time is significantly longer than the time required by DRAM, which can be used as cache memory within the storage.
  • data access speed i.e. the time required to store and output data
  • DRAM dynamic random access memory
  • storage systems usually provide cache memory within the storage to reduce the time required to store and output data.
  • the above-mentioned cache memory is used in the storage control circuit 6902 and the storage 6903. Data exchanged between the host 6901 and the storage 6903 is stored in the cache memory in the storage control circuit 6902 and the storage 6903, and then output to the host 6901 or the storage 6903.
  • OS transistors as transistors for storing data in the above-mentioned cache memory and configuring them to hold a potential corresponding to the data, it is possible to reduce the frequency of refreshing and reduce power consumption.
  • configuring the memory cell array in a stacked manner it is possible to reduce the size.
  • the application of the semiconductor device of one embodiment of the present invention to any one or more selected from electronic components, electronic devices, mainframe computers, space equipment, and data centers is expected to have an effect of reducing power consumption. Therefore, while energy demand is expected to increase with the improvement in performance or high integration of semiconductor devices, the use of the semiconductor device of one embodiment of the present invention can also reduce emissions of greenhouse gases such as carbon dioxide (CO 2 ). In addition, the semiconductor device of one embodiment of the present invention is effective as a measure against global warming because of its low power consumption.
  • CO 2 greenhouse gases
  • a display device to which the transistor of one embodiment of the present invention is applied can be a display device with extremely high resolution.
  • the display device of one embodiment of the present invention can be used in the display portion of a wristwatch-type or bracelet-type information terminal (wearable device), as well as in the display portion of a head-mounted display (HMD), a VR device such as a head-mounted display, and a glasses-type AR device that can be worn on the head.
  • Display module 48A shows a perspective view of a display module 580.
  • the display module 580 includes a display device 500A and an FPC 590.
  • the display panel included in the display module 580 is not limited to the display device 500A, and may be a display device 500B or a display device 500C described later.
  • the display module 580 has a substrate 591 and a substrate 592.
  • the display module 580 has a display unit 581.
  • the display unit 581 is an area that displays an image.
  • Figure 48B shows a perspective view that shows a schematic configuration on the substrate 591 side.
  • a circuit portion 582, a pixel circuit portion 583 on the circuit portion 582, and a pixel portion 584 on the pixel circuit portion 583 are stacked.
  • a terminal portion 585 for connecting to an FPC 590 is provided in a portion of the substrate 591 that does not overlap with the pixel portion 584.
  • the terminal portion 585 and the circuit portion 582 are electrically connected by a wiring portion 586 that is composed of multiple wirings.
  • the pixel section 584 has a number of pixels 584a arranged periodically. An enlarged view of one pixel 584a is shown on the right side of FIG. 48B.
  • the pixel 584a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.
  • the pixel circuit section 583 has a number of pixel circuits 583a arranged periodically. Each pixel circuit 583a is a circuit that controls the light emission of three light-emitting devices in one pixel 584a.
  • One pixel circuit 583a may be configured to have three circuits that control the light emission of one light-emitting device.
  • the pixel circuit 583a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitance element for each light-emitting device. At this time, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.
  • the circuit portion 582 has a circuit that drives each pixel circuit 583a of the pixel circuit portion 583.
  • a gate line driver circuit and a source line driver circuit.
  • it may have at least one of an arithmetic circuit, a memory circuit, a power supply circuit, etc.
  • a transistor provided in the circuit portion 582 may constitute a part of the pixel circuit 583a.
  • the pixel circuit 583a may be composed of a transistor included in the pixel circuit portion 583 and a transistor included in the circuit portion 582.
  • the FPC 590 functions as wiring for supplying video signals, power supply potential, etc. from the outside to the circuit section 582.
  • An IC may also be mounted on the FPC 590.
  • the display module 580 can be configured such that one or both of the pixel circuit section 583 and the circuit section 582 are provided overlappingly under the pixel section 584, so that the aperture ratio (effective display area ratio) of the display section 581 can be extremely high.
  • the aperture ratio of the display section 581 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less.
  • the pixels 584a can be arranged at an extremely high density, so that the resolution of the display section 581 can be extremely high.
  • the pixels 584a are arranged in the display section 581 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20000 ppi or less, or 30000 ppi or less.
  • Such a display module 580 has extremely high resolution and can therefore be suitably used in VR devices such as head-mounted displays, or glasses-type AR devices. For example, even in a configuration in which the display section of the display module 580 is viewed through a lens, the display module 580 has an extremely high resolution display section 581, so that even if the display section is enlarged with a lens, the pixels are not visible, and a highly immersive display can be achieved.
  • the display module 580 is not limited to this, and can be suitably used in electronic devices with relatively small display sections.
  • the display module 580 can be suitably used in the display section of a wearable electronic device such as a wristwatch.
  • a display device 500A shown in FIG. 49 includes a substrate 201, a light-emitting element 110R, a light-emitting element 110G, a light-emitting element 110B, a capacitor 140, and a transistor 520.
  • Substrate 201 corresponds to substrate 591 in FIG. 48A.
  • the transistor 520 is a vertical channel transistor in which an oxide semiconductor is used for the semiconductor layer in which the channel is formed.
  • the transistor 520 includes an oxide semiconductor 230, an insulator 251, an insulator 252, a conductor 260, a conductor 240, and a conductor 220.
  • transistor 520 The various transistors exemplified in embodiment 2 or embodiment 3 can be applied to transistor 520.
  • An insulator 210 is provided on the substrate 201.
  • the insulator 210 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 201 to the transistor 520 and prevents oxygen from being released from the oxide semiconductor 230 toward the insulator 210.
  • a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.
  • a conductor 220 is provided on the insulator 210, an insulator 280 is provided on the insulator 210 and the conductor 220, and a conductor 240 is provided on the insulator 280.
  • An opening is provided in the insulator 280, and an oxide semiconductor 230, an insulator 251, an insulator 252, and a conductor 260 are provided in the opening.
  • An insulating layer 164 is provided to cover the conductor 260.
  • the insulating layer 164 functions as an interlayer insulating layer.
  • a barrier layer may be provided between the insulating layer 164 and the insulating layer 154 to prevent impurities such as water or hydrogen from diffusing from the insulating layer 164 to the transistor 520.
  • As the barrier layer an insulating film similar to the insulator 210 can be used.
  • the plug 174 electrically connected to one side of the conductor 240 is provided so as to be embedded in the insulating layer 164.
  • the plug 174 preferably has a conductive layer 174a covering the side of the opening of the insulating layer 164 and part of the upper surface of the conductor 240, and a conductive layer 174b in contact with the upper surface of the conductive layer 174a.
  • a capacitor 140 is provided on the insulating layer 164.
  • the capacitor 140 has a conductive layer 141, a conductive layer 145, and an insulating layer 143 located between them.
  • the conductive layer 141 functions as one electrode of the capacitor 140
  • the conductive layer 145 functions as the other electrode of the capacitor 140
  • the insulating layer 143 functions as a dielectric of the capacitor 140.
  • the conductive layer 141 is provided on the insulating layer 164 and is embedded in the insulating layer 154.
  • the conductive layer 141 is electrically connected to the conductor 240 of the transistor 520 by a plug 174.
  • the insulating layer 143 is provided to cover the conductive layer 141.
  • the conductive layer 145 is provided in a region that overlaps with the conductive layer 141 via the insulating layer 143.
  • An insulating layer 155a is provided covering the capacitor 140, an insulating layer 155b is provided on the insulating layer 155a, and an insulating layer 155c is provided on the insulating layer 155b.
  • Insulating layers 155a, 155b, and 155c can each preferably be made of an inorganic insulating film.
  • a silicon oxide film for insulating layers 155a and 155c and a silicon nitride film for insulating layer 155b. This allows insulating layer 155b to function as an etching protection film.
  • an example is shown in which part of insulating layer 155c is etched to form a recess, but insulating layer 155c does not necessarily have to have a recess.
  • Light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B are provided on insulating layer 155c.
  • Light-emitting element 110R has pixel electrode 111R, organic layer 112R, common layer 114, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111G, organic layer 112G, common layer 114, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111B, organic layer 112B, common layer 114, and common electrode 113.
  • Common layer 114 and common electrode 113 are provided in common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.
  • the organic layer 112R of the light-emitting element 110R has a light-emitting organic compound that emits at least red light.
  • the organic layer 112G of the light-emitting element 110G has a light-emitting organic compound that emits at least green light.
  • the organic layer 112B of the light-emitting element 110B has a light-emitting organic compound that emits at least blue light.
  • the organic layer 112R, the organic layer 112G, and the organic layer 112B can each be called an EL layer, and have at least a layer (light-emitting layer) that contains a light-emitting organic compound.
  • the display device 500A a different light-emitting device is created for each emitted color, so there is little change in chromaticity between light emitted at low and high luminance.
  • the organic layers 112R, 112G, and 112B are spaced apart from each other, the occurrence of crosstalk between adjacent subpixels can be suppressed even in a high-definition display panel. This makes it possible to realize a display panel that is both high-definition and has high display quality.
  • an insulating layer 125 In the area between adjacent light-emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.
  • the pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductor 240 of the transistor 520 by the plug 156 embedded in the insulating layers 155a, 155b, and 155c, the conductive layer 141 embedded in the insulating layer 154, and the plug 174.
  • the height of the top surface of the insulating layer 155c is the same as the height of the top surface of the plug 156.
  • Various conductive materials can be used for the plug.
  • a protective layer 121 is provided on the light-emitting elements 110R, 110G, and 110B.
  • a substrate 170 is attached to the protective layer 121 by an adhesive layer 171.
  • Display device 500B A display device having a configuration partially different from that described above will be described below, but the same configuration as the above will be referred to and the description thereof may be omitted.
  • the display device 500B shown in FIG. 50 shows an example in which a transistor 520A, which is a planar type transistor in which a semiconductor layer is formed on a flat surface, and a transistor 520B, which is a vertical channel type transistor, are stacked.
  • the transistor 520B has a similar configuration to the transistor 520 in the display device 500A.
  • Transistor 520A has an oxide semiconductor 230, an insulator 251, an insulator 252, a conductor 260, a pair of conductors 242, an insulator 222, an insulator 221, and a conductor 215.
  • An insulator 214 is provided on the substrate 201.
  • the insulator 214 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 201 to the transistor 520 and prevents oxygen from being released from the oxide semiconductor 230 toward the insulator 214.
  • a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film, can be used.
  • An insulator 216 is provided on the insulator 214, a conductor 215 is provided so as to be embedded in the insulator 216, an insulator 221 is provided on the insulator 216 and on the conductor 215, and an insulator 222 is provided on the insulator 221.
  • the conductor 215 functions as a first gate electrode of the transistor 520A, and a portion of each of the insulators 221 and 222 functions as a first gate insulating layer.
  • the top surface of the insulator 216 is preferably planarized.
  • the oxide semiconductor 230 is provided over the insulator 222.
  • the oxide semiconductor 230 preferably has a metal oxide (also referred to as an oxide semiconductor) film that exhibits semiconductor characteristics.
  • the pair of conductors 242 are provided in contact with the oxide semiconductor 230 and function as a source electrode and a drain electrode.
  • An insulator 280 is provided to cover the top and side surfaces of the pair of conductors 242 and the side surfaces of the oxide semiconductor 230.
  • the insulator 280 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the oxide semiconductor 230 and prevents oxygen from being released from the oxide semiconductor 230.
  • An opening is provided in the insulator 280 that reaches the oxide semiconductor 230.
  • An insulator 251, an insulator 252, and a conductor 260 are embedded inside the opening.
  • the insulator 251 is in contact with the top surface of the oxide semiconductor 230.
  • the conductor 260 functions as a second gate electrode, and the insulator 251 and the insulator 252 function as a second gate insulating layer.
  • the top surface of the conductor 260, the top surface of the insulator 251, the top surface of the insulator 252, and the top surface of the insulator 280 are planarized so that they are all at the same height, and an insulator 283 is provided to cover them.
  • the insulator 283 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 520.
  • the insulator 283 can be an insulating film similar to the insulator 214 described above.
  • Transistor 520 has a configuration in which a semiconductor layer in which a channel is formed is sandwiched between two gates.
  • the two gates may be connected and the transistor may be driven by supplying the same signal to them.
  • the threshold voltage of the transistor may be controlled by supplying a potential to one of the two gates for controlling the threshold voltage and a potential to drive the other.
  • a display device 500C shown in FIG. 51 has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a vertical channel transistor 520 .
  • the transistor 310 has a channel formation region in the substrate 311.
  • the substrate 311 can be, for example, a semiconductor substrate such as a single crystal silicon substrate.
  • the transistor 310 has a part of the substrate 311, a conductor 316, a low resistance region 314, an insulator 315, and an insulator 317.
  • the conductor 316 functions as a gate electrode.
  • the insulator 315 is located between the substrate 311 and the conductor 316 and functions as a gate insulating layer.
  • the low resistance region 314 is a region in which the substrate 311 is doped with impurities, and functions as one of the source and drain.
  • the insulator 317 is provided to cover the side surface of the conductor 316.
  • an element isolation layer 318 is provided between two adjacent transistors 310 so as to be embedded in the substrate 311.
  • This embodiment can be implemented in combination with at least a portion of the other embodiments described in this specification.
  • Embodiment 8 In this embodiment, a structural example of a display device that can be used for a display device manufactured using a transistor according to one embodiment of the present invention will be described.
  • the display device described below can be used for the pixel portion 584 in the above-described Embodiment 3, or the like.
  • One embodiment of the present invention is a display device having a light-emitting element (also called a light-emitting device).
  • the display device has two or more pixels that emit light of different colors. Each pixel has a light-emitting element. Each light-emitting element has a pair of electrodes and an EL layer between them.
  • the light-emitting element is preferably an organic EL element (organic electroluminescent element). Two or more light-emitting elements that emit different light colors each have an EL layer containing a different light-emitting material.
  • a full-color display device can be realized by having three types of light-emitting elements that emit red (R), green (G), or blue (B) light.
  • the shape and position of the island-shaped organic film deviate from the design, making it difficult to achieve high resolution and a high aperture ratio of the display device.
  • the contour of the layer may become blurred and the thickness of the edge may become thin.
  • the thickness of the island-shaped light-emitting layer may vary depending on the location.
  • an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from the adjacent light-emitting layer.
  • the EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM).
  • FMM fine metal mask
  • the EL layer can be made separately, it is possible to realize a display device that is extremely vivid, has high contrast, and has high display quality.
  • the EL layer may be processed into a fine pattern using both a metal mask and photolithography.
  • a part or the whole of the EL layer can be physically separated. This makes it possible to suppress leakage current between light-emitting elements via a layer shared between adjacent light-emitting elements (also called a common layer). This makes it possible to prevent crosstalk caused by unintended light emission, and to realize a display device with extremely high contrast. In particular, a display device with high current efficiency at low luminance can be realized.
  • One aspect of the present invention can be a display device that combines a white-emitting light-emitting element and a color filter.
  • light-emitting elements of the same configuration can be applied to light-emitting elements provided in pixels (subpixels) that emit light of different colors, and all layers can be common layers. Furthermore, a part or all of each EL layer may be divided by photolithography. This suppresses leakage current through the common layer, and a display device with high contrast can be realized.
  • leakage current through the intermediate layer can be effectively prevented, and a display device that combines high brightness, high definition, and high contrast can be realized.
  • an insulating layer that covers at least the side surface of the island-shaped light-emitting layer.
  • the insulating layer may be configured to cover a part of the upper surface of the island-shaped EL layer.
  • a material that has barrier properties against water and oxygen For example, an inorganic insulating film that does not easily diffuse water or oxygen can be used. This makes it possible to suppress deterioration of the EL layer and realize a highly reliable display device.
  • FIG. 52A shows a schematic top view of a display device 100 according to one embodiment of the present invention.
  • the display device 100 includes a plurality of light-emitting elements 110R that exhibit red light, a plurality of light-emitting elements 110G that exhibit green light, and a plurality of light-emitting elements 110B that exhibit blue light, over a substrate 101.
  • the symbols R, G, and B are assigned within the light-emitting regions of the light-emitting elements in order to easily distinguish between the light-emitting elements.
  • Light emitting elements 110R, 110G, and 110B are each arranged in a matrix.
  • Figure 52A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and arrangement methods such as an S stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be applied, and a pentile arrangement, diamond arrangement, etc. may also be used.
  • the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B for example, it is preferable to use an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode).
  • the light-emitting material possessed by the EL element include a material that emits fluorescence (fluorescent material), a material that emits phosphorescence (phosphorescent material), and a material that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) material).
  • TADF thermally activated delayed fluorescence
  • the light-emitting material possessed by the EL element not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.
  • FIG. 52A also shows a connection electrode 111C that is electrically connected to the common electrode 113.
  • the connection electrode 111C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 113.
  • the connection electrode 111C is provided outside the display area where the light-emitting elements 110R and the like are arranged.
  • connection electrode 111C can be provided along the outer periphery of the display area. For example, it may be provided along one side of the outer periphery of the display area, or it may be provided over two or more sides of the outer periphery of the display area. In other words, if the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be a strip shape (rectangle), an L-shape, a U-shape (square bracket shape), a square shape, or the like.
  • Figures 52B and 52C are schematic cross-sectional views corresponding to dashed lines A1-A2 and A3-A4 in Figure 52A, respectively.
  • Figure 52B shows schematic cross-sectional views of light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B
  • Figure 52C shows a schematic cross-sectional view of connection portion 130 where connection electrode 111C and common electrode 113 are connected.
  • Light-emitting element 110R has pixel electrode 111R, organic layer 112R, common layer 114, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111G, organic layer 112G, common layer 114, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111B, organic layer 112B, common layer 114, and common electrode 113.
  • Common layer 114 and common electrode 113 are provided in common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B.
  • the organic layer 112R of the light-emitting element 110R has a light-emitting organic compound that emits at least red light.
  • the organic layer 112G of the light-emitting element 110G has a light-emitting organic compound that emits at least green light.
  • the organic layer 112B of the light-emitting element 110B has a light-emitting organic compound that emits at least blue light.
  • the organic layer 112R, the organic layer 112G, and the organic layer 112B can each be called an EL layer, and have at least a layer (light-emitting layer) that contains a light-emitting organic compound.
  • light-emitting element 110R when describing matters common to light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, they may be referred to as light-emitting element 110.
  • components distinguished by alphabets such as organic layer 112R, organic layer 112G, and organic layer 112B, they may be described using symbols without the alphabet.
  • the organic layer 112 and the common layer 114 can each independently have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer.
  • the organic layer 112 can have a laminated structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 can have an electron injection layer.
  • the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are provided for each light-emitting element.
  • the common electrode 113 and common layer 114 are provided as a continuous layer common to each light-emitting element.
  • a conductive film having translucency to visible light is used for either one of the pixel electrodes or the common electrode 113, and a conductive film having reflective properties is used for the other.
  • a protective layer 121 is provided on the common electrode 113, covering the light-emitting elements 110R, 110G, and 110B.
  • the protective layer 121 has the function of preventing impurities such as water from diffusing from above into each light-emitting element.
  • the end of the pixel electrode 111 is preferably tapered.
  • the organic layer 112 provided along the end of the pixel electrode 111 can also be tapered.
  • the coverage of the organic layer 112 provided over the end of the pixel electrode 111 can be improved.
  • foreign matter for example, also called dust or particles
  • the organic layer 112 is processed into an island shape by photolithography. Therefore, the angle between the top surface and the side surface of the organic layer 112 at its ends is close to 90 degrees. On the other hand, an organic film formed using FMM or the like tends to become gradually thinner closer to the ends. For example, the top surface is formed in a slope over a range of 1 ⁇ m to 10 ⁇ m to the ends, making it difficult to distinguish between the top surface and the side surface.
  • an insulating layer 125 Between two adjacent light-emitting elements are an insulating layer 125, a resin layer 126, and a layer 128.
  • the resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the area between the two organic layers 112.
  • the resin layer 126 has a smooth convex upper surface shape, and a common layer 114 and a common electrode 113 are provided covering the upper surface of the resin layer 126.
  • the resin layer 126 functions as a planarization film that fills in the step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent the phenomenon in which the common electrode 113 is divided by the step at the end of the organic layer 112 (also called step disconnection), and the common electrode on the organic layer 112 is insulated.
  • the resin layer 126 can also be called an LFP (Local Filling Planarization) layer.
  • An insulating layer containing an organic material can be suitably used as the resin layer 126.
  • acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins can be used as the resin layer 126.
  • organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used as the resin layer 126.
  • a photosensitive resin can be used as the resin layer 126.
  • a photoresist can be used as the photosensitive resin.
  • a positive type material or a negative type material can be used as the photosensitive resin.
  • the resin layer 126 may contain a material that absorbs visible light.
  • the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light.
  • the resin layer 126 may be, for example, a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.
  • the insulating layer 125 is provided in contact with the side surface of the organic layer 112.
  • the insulating layer 125 is also provided to cover the upper end portion of the organic layer 112.
  • a portion of the insulating layer 125 is also provided in contact with the upper surface of the substrate 101.
  • the insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from contacting the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact with each other, the organic layer 112 may be dissolved by the organic solvent used in forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surface of the organic layer 112.
  • the insulating layer 125 may be an insulating layer containing an inorganic material.
  • an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film may be used for the insulating layer 125.
  • the insulating layer 125 may have a single layer structure or a laminated structure.
  • the oxide insulating film examples include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film.
  • the nitride insulating film include a silicon nitride film and an aluminum nitride film.
  • the oxynitride insulating film examples include a silicon oxynitride film and an aluminum oxynitride film.
  • nitride oxide insulating film examples include a silicon nitride oxide film and an aluminum nitride oxide film.
  • an inorganic insulating film such as an aluminum oxide film or a metal oxide film such as a hafnium oxide film or a silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 with few pinholes and excellent function of protecting the EL layer can be formed.
  • oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • nitride oxide refers to a material whose composition contains more nitrogen than oxygen
  • silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen
  • silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen
  • the insulating layer 125 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. It is preferable to form the insulating layer 125 by an ALD method, which has good coverage.
  • a reflective film e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.
  • a reflective film may be provided between the insulating layer 125 and the resin layer 126, and the light emitted from the light-emitting layer may be reflected by the reflective film. This can improve the light extraction efficiency.
  • Layer 128 is a portion of a protective layer (also called a mask layer or a sacrificial layer) that protects organic layer 112 when the organic layer 112 is etched.
  • the material that can be used for insulating layer 125 can be used for layer 128. In particular, it is preferable to use the same material for layer 128 and insulating layer 125 because the same processing equipment can be used.
  • inorganic insulating films such as aluminum oxide films, metal oxide films such as hafnium oxide films, and silicon oxide films formed by the ALD method have few pinholes, so they have excellent functionality for protecting the EL layer and can be suitably used for the insulating layer 125 and layer 128.
  • the protective layer 121 can have, for example, a single-layer structure or a laminated structure including at least an inorganic insulating film.
  • the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film.
  • a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide may be used as the protective layer 121.
  • the protective layer 121 may be a laminated film of an inorganic insulating film and an organic insulating film.
  • an organic insulating film is sandwiched between a pair of inorganic insulating films.
  • the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties.
  • the upper surface of the protective layer 121 is flat, it is preferable that when a structure (e.g., a color filter, a touch sensor electrode, or a lens array) is provided above the protective layer 121, the influence of the uneven shape caused by the structure below can be reduced.
  • a structure e.g., a color filter, a touch sensor electrode, or a lens array
  • Figure 52C shows a connection portion 130 where the connection electrode 111C and the common electrode 113 are electrically connected.
  • connection portion 130 an opening is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C.
  • the connection electrode 111C and the common electrode 113 are electrically connected in the opening.
  • FIG. 52C shows a connection portion 130 that electrically connects the connection electrode 111C and the common electrode 113
  • the common electrode 113 may be provided on the connection electrode 111C via the common layer 114.
  • the electrical resistivity of the material used for the common layer 114 is sufficiently low and the common layer 114 can be formed thin, so there are many cases where no problem occurs even if the common layer 114 is located at the connection portion 130. This allows the common electrode 113 and the common layer 114 to be formed using the same shielding mask, thereby reducing manufacturing costs.
  • Figure 53A shows a schematic cross-sectional view of the display device 100a.
  • the display device 100a differs from the display device 100 described above mainly in that the light-emitting element has a different configuration and in that it has a colored layer.
  • the display device 100a has a light-emitting element 110W that emits white light.
  • the light-emitting element 110W has a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113.
  • the organic layer 112W emits white light.
  • the organic layer 112W can be configured to include two or more types of light-emitting materials whose emitted light colors are complementary to each other.
  • the organic layer 112W can be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. It may also be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.
  • the organic layers 112W are separated between two adjacent light-emitting elements 110W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 110W via the organic layers 112W, and to suppress crosstalk caused by the leakage current. This makes it possible to realize a display device with high contrast and color reproducibility.
  • An insulating layer 122 that functions as a planarizing film is provided on the protective layer 121, and colored layers 116R, 116G, and 116B are provided on the insulating layer 122.
  • the insulating layer 122 can be an organic resin film or an inorganic insulating film with a flattened upper surface.
  • the insulating layer 122 forms the surface on which the colored layers 116R, 116G, and 116B are formed. Therefore, by making the upper surface of the insulating layer 122 flat, the thickness of the colored layers 116R, etc. can be made uniform, thereby improving the color purity. Note that if the thickness of the colored layers 116R, etc. is not uniform, the amount of light absorbed varies depending on the location of the colored layer 116R, which may result in a decrease in color purity.
  • FIG. 53B shows a schematic cross-sectional view of the display device 100b.
  • Light-emitting element 110R has pixel electrode 111, conductive layer 115R, organic layer 112W, and common electrode 113.
  • Light-emitting element 110G has pixel electrode 111, conductive layer 115G, organic layer 112W, and common electrode 113.
  • Light-emitting element 110B has pixel electrode 111, conductive layer 115B, organic layer 112W, and common electrode 113.
  • Conductive layer 115R, conductive layer 115G, and conductive layer 115B each have light-transmitting properties and function as optical adjustment layers.
  • a microresonator (microcavity) structure By using a film that reflects visible light for the pixel electrode 111 and a film that is both reflective and transparent to visible light for the common electrode 113, a microresonator (microcavity) structure can be realized.
  • a microresonator (microcavity) structure By adjusting the thicknesses of the conductive layers 115R, 115G, and 115B so as to provide optimal optical path lengths, even when an organic layer 112 that emits white light is used, light with different wavelengths that are intensified can be obtained from the light-emitting elements 110R, 110G, and 110B.
  • colored layers 116R, 116G, and 116B are provided on the optical paths of light-emitting elements 110R, 110G, and 110B, respectively, to obtain light with high color purity.
  • an insulating layer 123 is provided to cover the ends of the pixel electrode 111 and the conductive layer 115.
  • the insulating layer 123 preferably has a tapered end.
  • the organic layer 112W and the common electrode 113 are each provided as a continuous film common to each light-emitting element. This configuration is preferable because it can greatly simplify the manufacturing process of the display device.
  • the pixel electrode 111 has an end shape that is nearly vertical. This allows a steeply inclined portion to be formed on the surface of the insulating layer 123, and a thin portion can be formed in the part of the organic layer 112W that covers this portion, or a part of the organic layer 112W can be separated. Therefore, it is possible to suppress leakage current through the organic layer 112W that occurs between adjacent light-emitting elements without processing the organic layer 112W by a photolithography method or the like.
  • This embodiment can be implemented in combination with at least a portion of the other embodiments described in this specification.
  • the electronic device of this embodiment has a display panel (display device) in which the transistor of one embodiment of the present invention is applied to a display portion.
  • the display device of one embodiment of the present invention can easily achieve high definition and high resolution, and can also achieve high display quality. Therefore, the display device can be used in the display portion of various electronic devices.
  • Examples of electronic devices include television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, and other electronic devices with relatively large screens, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and audio playback devices.
  • the display panel of one embodiment of the present invention can be used favorably in electronic devices having a relatively small display area because it is possible to increase the resolution.
  • electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.
  • the display panel of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • an extremely high resolution such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K (3840 x 2160 pixels), or 8K (7680 x 4320 pixels).
  • HD 1280 x 720 pixels
  • FHD (1920 x 1080 pixels
  • WQHD 2560 x 1440 pixels
  • WQXGA 2560 x 1600 pixels
  • 4K 3840 x 2160 pixels
  • 8K 8K
  • the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or more, preferably 300 ppi or more, more preferably 500 ppi or more, more preferably 1000 ppi or more, more preferably 2000 ppi or more, more preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 7000 ppi or more.
  • the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.
  • the electronic device of this embodiment may have a sensor (including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • a sensor including the function of sensing, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).
  • the electronic device of this embodiment can have various functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.
  • a function to display various information still images, videos, text images, etc.
  • a touch panel function a function to display a calendar, date or time, etc.
  • a function to execute various software (programs) a wireless communication function
  • a function to read out programs or data recorded on a recording medium etc.
  • FIG. 54A to 54D An example of a wearable device that can be worn on the head will be described using Figures 54A to 54D.
  • These wearable devices have one or both of the functions of displaying AR content and VR content. Note that these wearable devices may also have the function of displaying SR or MR content in addition to AR and VR.
  • Electronic device 700A shown in FIG. 54A and electronic device 700B shown in FIG. 54B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.
  • a display panel according to one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can display images with extremely high resolution.
  • Each of the electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on the transmitted image visually recognized through the optical member 753. Therefore, each of the electronic devices 700A and 700B is an electronic device capable of AR display.
  • Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.
  • an acceleration sensor such as a gyro sensor
  • the communication unit has a wireless communication device, and can supply video signals and the like via the wireless communication device.
  • a connector can be provided to which a cable through which a video signal and a power supply potential can be connected.
  • electronic device 700A and electronic device 700B are provided with batteries, which can be charged wirelessly and/or wired.
  • the housing 721 may be provided with a touch sensor module.
  • the touch sensor module has a function of detecting that the outer surface of the housing 721 is touched.
  • the touch sensor module can detect a tap operation or a slide operation by the user and execute various processes. For example, a tap operation can execute processes such as pausing or resuming a video, and a slide operation can execute processes such as fast-forwarding or rewinding. Furthermore, by providing a touch sensor module on each of the two housings 721, the range of operations can be expanded.
  • touch sensors can be used as the touch sensor module.
  • various types can be adopted, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type.
  • a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element).
  • the active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.
  • Electronic device 800A shown in FIG. 54C and electronic device 800B shown in FIG. 54D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.
  • a display panel according to one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided. This allows the user to feel a high sense of immersion.
  • the display unit 820 is provided inside the housing 821 at a position that can be seen through the lens 832. In addition, by displaying different images on the pair of display units 820, it is also possible to perform three-dimensional display using parallax.
  • Each of the electronic devices 800A and 800B can be considered electronic devices for VR.
  • a user wearing the electronic device 800A or the electronic device 800B can view the image displayed on the display unit 820 through the lens 832.
  • Electric device 800A and electronic device 800B each preferably have a mechanism that can adjust the left-right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. Also, it is preferable that they have a mechanism that adjusts the focus by changing the distance between lens 832 and display unit 820.
  • the mounting unit 823 allows the user to mount the electronic device 800A or electronic device 800B on the head. Note that in FIG. 54C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 only needs to be wearable by the user, and may be shaped like a helmet or band, for example.
  • the imaging unit 825 has a function of acquiring external information.
  • the data acquired by the imaging unit 825 can be output to the display unit 820.
  • An image sensor can be used for the imaging unit 825.
  • multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.
  • a distance measuring sensor capable of measuring the distance to an object
  • the imaging unit 825 is one aspect of the detection unit.
  • the detection unit for example, an image sensor or a distance image sensor such as a LIDAR (Light Detection and Ranging) can be used.
  • LIDAR Light Detection and Ranging
  • the electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone.
  • a vibration mechanism that functions as a bone conduction earphone.
  • a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This makes it possible to enjoy video and audio simply by wearing the electronic device 800A without the need for separate audio equipment such as headphones, earphones, or speakers.
  • Each of the electronic devices 800A and 800B may have an input terminal.
  • the input terminal can be connected to a cable that supplies a video signal from a video output device or the like, and power for charging a battery provided within the electronic device.
  • the electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750.
  • the earphone 750 has a communication unit (not shown) and has a wireless communication function.
  • the earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function.
  • the electronic device 700A shown in FIG. 54A has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device 800A shown in FIG. 54C has a function of transmitting information to the earphone 750 through the wireless communication function.
  • the electronic device may also have an earphone unit.
  • Electronic device 700B shown in FIG. 54B has earphone unit 727.
  • earphone unit 727 and the control unit may be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.
  • electronic device 800B shown in FIG. 54D has earphone unit 827.
  • earphone unit 827 and control unit 824 can be configured to be connected to each other by wire.
  • Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or mounting unit 823.
  • earphone unit 827 and mounting unit 823 may have magnets. This allows earphone unit 827 to be fixed to mounting unit 823 by magnetic force, which is preferable as it makes storage easier.
  • the electronic device may have an audio output terminal to which earphones or headphones can be connected.
  • the electronic device may also have one or both of an audio input terminal and an audio input mechanism.
  • a sound collection device such as a microphone can be used as the audio input mechanism.
  • the electronic device may be endowed with the functionality of a so-called headset.
  • both glasses-type devices such as electronic device 700A and electronic device 700B
  • goggle-type devices such as electronic device 800A and electronic device 800B
  • the electronic device 6500 shown in FIG. 55A is a portable information terminal that can be used as a smartphone.
  • the electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like.
  • the display portion 6502 has a touch panel function.
  • the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.
  • a display panel of one embodiment of the present invention can be applied to the display portion 6502.
  • Figure 55B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.
  • a transparent protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.
  • the display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).
  • a part of the display panel 6511 is folded back, and the FPC 6515 is connected to the folded back part.
  • An IC 6516 is mounted on the FPC 6515.
  • the FPC 6515 is connected to a terminal provided on a printed circuit board 6517.
  • the flexible display of one embodiment of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized.
  • the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small.
  • a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.
  • Figure 55C shows an example of a television device.
  • a display unit 7000 is built into a housing 7101.
  • the housing 7101 is supported by a stand 7103.
  • the television device 7100 shown in FIG. 55C can be operated using an operation switch provided on the housing 7101 and a separate remote control 7111.
  • the display unit 7000 may be provided with a touch sensor, and the television device 7100 may be operated by touching the display unit 7000 with a finger or the like.
  • the remote control 7111 may have a display unit that displays information output from the remote control 7111.
  • the channel and volume can be operated by the operation keys or touch panel provided on the remote control 7111, and the image displayed on the display unit 7000 can be operated.
  • the television device 7100 is configured to include a receiver and a modem.
  • the receiver can receive general television broadcasts.
  • by connecting to a wired or wireless communication network via the modem it is also possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.
  • FIG. 55D shows an example of a laptop personal computer.
  • the laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like.
  • a display portion 7000 is incorporated in the housing 7211.
  • the control device 7216 includes, for example, one or more of a CPU, a GPU, and a storage device.
  • the semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like.
  • the use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.
  • Figures 55E and 55F show an example of digital signage.
  • the digital signage 7300 shown in FIG. 55E has a housing 7301, a display unit 7000, a speaker 7303, and the like. It can also have LED lamps, operation keys (including a power switch or an operation switch), connection terminals, various sensors, a microphone, and the like.
  • Figure 55F shows a digital signage 7400 attached to a cylindrical pole 7401.
  • the digital signage 7400 has a display unit 7000 that is provided along the curved surface of the pole 7401.
  • the larger the display unit 7000 the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it catches people's attention, which can increase the advertising effectiveness of, for example, advertisements.
  • a touch panel By applying a touch panel to the display unit 7000, not only can images or videos be displayed on the display unit 7000, but the user can also intuitively operate it, which is preferable. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.
  • the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user.
  • advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411.
  • the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.
  • the digital signage 7300 or the digital signage 7400 can be made to execute a game using the screen of the information terminal 7311 or the information terminal 7411 as an operating means (controller). This allows an unspecified number of users to participate in and enjoy the game at the same time.
  • a display panel of one embodiment of the present invention can be applied to the display portion 7000.
  • the electronic device shown in Figures 56A to 56G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to sense, detect, or measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared), a microphone 9008, etc.
  • the electronic device shown in Figures 56A to 56G has various functions. For example, it can have a function of displaying various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, etc.
  • the functions of the electronic device are not limited to these, and it can have various functions.
  • the electronic device may have multiple display units.
  • the electronic device may have a camera or the like to capture still images or videos and store them on a recording medium (external or built into the camera), a function of displaying the captured images on the display unit, etc.
  • FIG. 56A is a perspective view showing a mobile information terminal 9101.
  • the mobile information terminal 9101 can be used as a smartphone, for example.
  • the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like.
  • the mobile information terminal 9101 can display text and image information on multiple surfaces.
  • FIG. 56A shows an example in which three icons 9050 are displayed.
  • Information 9051 shown in a dashed rectangle can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming e-mail, SNS, telephone calls, etc., the title of e-mail or SNS, the sender's name, the date and time, the remaining battery level, and radio wave strength.
  • an icon 9050 or the like may be displayed at the position where the information 9051 is displayed.
  • Figure 56B is a perspective view showing a mobile information terminal 9102.
  • the mobile information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001.
  • information 9052, information 9053, and information 9054 are each displayed on different sides.
  • a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is stored in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether or not to answer a call.
  • Figure 56C is a perspective view showing a tablet terminal 9103.
  • the tablet terminal 9103 is capable of executing various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games, for example.
  • the tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of the housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.
  • FIG 56D is a perspective view showing a wristwatch-type mobile information terminal 9200.
  • the mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark).
  • the display surface of the display unit 9001 is curved, and display can be performed along the curved display surface.
  • the mobile information terminal 9200 can also perform hands-free conversation by communicating with, for example, a headset capable of wireless communication.
  • the mobile information terminal 9200 can also perform data transmission with other information terminals and charge itself via the connection terminal 9006. Note that charging may be performed by wireless power supply.
  • FIG. 56E to 56G are perspective views showing a foldable mobile information terminal 9201.
  • FIG. 56E is a perspective view of the mobile information terminal 9201 in an unfolded state
  • FIG. 56G is a perspective view of the mobile information terminal 9201 in a folded state
  • FIG. 56F is a perspective view of the mobile information terminal 9201 in a state in the middle of changing from one of FIG. 56E and FIG. 56G to the other.
  • the mobile information terminal 9201 has excellent portability when folded, and excellent display visibility due to a seamless wide display area when unfolded.
  • the display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055.
  • the display unit 9001 can be bent with a radius of curvature of 0.1 mm or more and 150 mm or less.
  • This embodiment can be implemented in combination with at least a portion of the other embodiments described in this specification.
  • samples were prepared and each sample was subjected to TDS analysis.
  • samples including transistors equivalent to the transistors described in embodiment 2 were prepared and the electrical characteristics and reliability of the transistors were evaluated.
  • sample 1B sample 1C, and samples 2A to 2C.
  • Sample 1B, sample 1C, and sample 2A to sample 2C each have a substrate 901, an insulator 902 on the substrate 901, an insulator 903 on the insulator 902, and an insulator 904 on the insulator 903.
  • a silicon substrate was prepared as substrate 901.
  • the insulator 902 was a silicon oxide film with a thickness of 100 nm, which was formed by oxidizing the silicon substrate by thermal oxidation.
  • a silicon oxide film formed by a sputtering method was used as the insulator 904. Note that the thickness of the silicon oxide film was 20 nm in Samples 1B and 1C, and 60 nm in Samples 2A to 2C.
  • a first aluminum oxide film having a thickness of 5 nm was formed on the insulator 904 by a sputtering method, and a second aluminum oxide film having a thickness of 5 nm was formed on the first aluminum oxide film by a sputtering method.
  • a CMP process was performed to remove the first aluminum oxide film and the second aluminum oxide film.
  • the deposition conditions for the first aluminum oxide film were a temperature of 200° C., a pressure of 0.4 Pa, an oxygen flow ratio (O 2 /(O 2 +Ar)) of 83%, a power of 5 kW, and an RF bias power of 1.86 W/cm 2.
  • the deposition conditions for the second aluminum oxide film were an RF bias power of 0.62 W/cm 2 , and the rest were the same as the deposition conditions for the first aluminum oxide film.
  • a third aluminum oxide film with a thickness of 10 nm was formed on the insulator 904 by a sputtering method.
  • the third aluminum oxide film was removed by CMP processing.
  • the deposition conditions for the third aluminum oxide film were the same as those for the second aluminum oxide film.
  • samples 1B, 1C, and 2A to 2C were produced.
  • a high-precision thermal desorption analyzer "EMD-WA1000S” manufactured by Electron Science Corporation was used, and the heating rate was set to 30° C./min.
  • the lower limit of the temperature range was set to the temperature at which degassing could be confirmed (approximately 40°C or higher). Therefore, the amount of oxygen molecules released below the measurement limit is not included.
  • Figures 58A to 58C The results of the TDS analysis are shown in Figures 58A to 58C.
  • the vertical axis indicates the amount of released oxygen molecules ( O2 released amount) [molecules/ cm2 ].
  • Figure 58A shows the amount of released oxygen molecules in Sample 2A
  • Figure 58B shows the amount of released oxygen molecules in Samples 1B and 2B
  • Figure 58C shows the amount of released oxygen molecules in Samples 1C and 2C.
  • sample 2A released the greatest amount of oxygen molecules, followed by sample 2B, and sample 2C released the least amount of oxygen molecules. Also, the amount of oxygen molecules released from sample 1B was greater than the amount of oxygen molecules released from sample 1C. It was also possible to calculate the amount of oxygen molecules released from samples 1C and 2C.
  • a sample (temporarily designated as Sample 1A) having the same configuration as Sample 2A except for the thickness of the silicon oxide film being 20 nm was not prepared, but the amount of released oxygen molecules in Sample 1A is estimated to be greater than the amount of released oxygen molecules in Sample 1B based on the magnitude relationship between the amounts of released oxygen molecules in Samples 2A to 2C. For example, the amount of released oxygen molecules in Sample 1A is estimated to be greater than 1.5 ⁇ 10 molecules/ cm2 .
  • the insulator 904 is an insulating film containing excess oxygen, regardless of whether an aluminum oxide film is formed on the insulator 904. It was also found that the amount of oxygen released from the insulator 904 can be adjusted depending on the film formation conditions of the aluminum oxide film formed on the insulator 904. Therefore, by providing the insulator 904 in contact with an oxide semiconductor in which a channel is formed, oxygen can be supplied to the oxide semiconductor. By providing the insulator 904 near the oxide semiconductor in which a channel is formed, oxygen can be supplied to the oxide semiconductor.
  • samples 3A to 3C and samples 4A to 4C used to evaluate the electrical characteristics and reliability.
  • Each sample includes a transistor.
  • a cross-sectional view of a transistor included in each sample is shown in Figure 17B.
  • the conductor 220 (conductor 220a and conductor 220b) was provided on the silicon oxide film.
  • the conductor 220a was formed using a laminated film of a titanium nitride film formed by sputtering and a tungsten film formed by sputtering.
  • the conductor 220b was formed using an ITSO film formed by sputtering.
  • the silicon nitride film and the tungsten film were formed successively using a multi-chamber sputtering device without exposure to the outside air.
  • the insulator 280a was a silicon nitride film with a thickness of 5 nm formed by the ALD method.
  • the insulator 280b was a silicon oxide film formed by the sputtering method.
  • a CMP process was performed to flatten the upper surface of the insulator 280b. By performing the CMP process, the thickness of the insulator 280b on the conductor 220 was set to 20 nm.
  • a first aluminum oxide film having a thickness of 5 nm was formed on the insulator 280b by a sputtering method, and a second aluminum oxide film having a thickness of 5 nm was formed on the first aluminum oxide film by a sputtering method.
  • a CMP process was performed to remove the first aluminum oxide film and the second aluminum oxide film.
  • the deposition conditions for the first aluminum oxide film were the same as those for the first aluminum oxide film used in the above-mentioned sample 2A.
  • the deposition conditions for the second aluminum oxide film were the same as those for the second aluminum oxide film used in the above-mentioned sample 2A.
  • a third aluminum oxide film with a thickness of 10 nm was formed on the insulator 280b by sputtering. Next, the third aluminum oxide film was removed by CMP processing. The deposition conditions for the third aluminum oxide film were the same as those for the third aluminum oxide film used for samples 1B and 2B.
  • the insulator 280c is a silicon nitride film with a thickness of 10 nm, formed by sputtering.
  • the conductor 240 was formed using an ITSO film with a thickness of 20 nm, deposited by sputtering.
  • the opening 290 was formed so that its maximum width was 200 nm in diameter. In samples 4A to 4C, the opening 290 was formed so that its maximum width was 60 nm in diameter.
  • the oxide semiconductor 230b was formed using an oxide film having a thickness of 5 nm, which was formed by an ALD method.
  • the precursors used for forming the metal oxide film were triethylindium (TEI), triethylgallium (TEG), and diethylzinc (DEZ).
  • TEI triethylindium
  • TOG triethylgallium
  • DEZ diethylzinc
  • ozone (O 3 ) and oxygen (O 2 ) were used as oxidizing agents.
  • the metal oxide film was an In—Ga—Zn oxide film.
  • the insulator 254 was formed using an aluminum oxide film with a thickness of 1 nm formed by the ALD method.
  • the insulator 253 was formed using a silicon oxide film with a thickness of 2 nm formed by the ALD method.
  • the insulator 251 was formed using a hafnium oxide film with a thickness of 2 nm formed by the ALD method.
  • the insulator 252 was formed using a silicon nitride film with a thickness of 1 nm formed by the ALD method.
  • the conductor 260a was formed using a titanium nitride film with a thickness of 5 nm, which was deposited by metal CVD.
  • the conductor 260b was formed using a tungsten film with a thickness of 20 nm, which was deposited by sputtering.
  • the insulator 283 is a silicon nitride film with a thickness of 5 nm, formed by sputtering.
  • samples including transistors were fabricated.
  • Id-Vg drain current-gate voltage
  • a shift value Vsh was calculated from the obtained Id-Vg characteristics.
  • the shift value Vsh is the gate voltage (Vg) at the intersection of the tangent of the maximum slope of the drain current (Id) expressed in logarithm and the axis of 1 ⁇ 10 ⁇ 12 A in the Id-Vg characteristics of the transistor.
  • ⁇ Vsh which will be described later, is the amount of fluctuation in the shift value.
  • Figures 59A to 59C are graphs plotting shift values Vsh calculated from the acquired Id-Vg characteristics.
  • the vertical axis represents Vsh [V].
  • Figure 59A shows the results for the transistors included in Sample 3A and the transistors included in Sample 4A
  • Figure 59B shows the results for the transistors included in Sample 3B and the transistors included in Sample 4B
  • Figure 59C shows the results for the transistors included in Sample 3C and the transistors included in Sample 4C.
  • Reliability evaluation was performed on three selected transistors in each of the samples (samples 3A to 3C and samples 4A to 4C) to investigate the stress time dependency.
  • the reliability evaluation was performed by a +GBT (Gate Bias Temperature) stress test. Specifically, the set temperature was 125° C., the drain voltage and source voltage were 0 V, and the gate voltage was +1.98 V, and ⁇ Vsh, which is the change in Vsh due to the stress time, was evaluated. The stress time was 20 hours.
  • Figures 60A to 60F are graphs showing the stress time dependence of ⁇ Vsh.
  • the horizontal axis shows stress time (Time) [hr]
  • the vertical axis shows ⁇ Vsh [mV].
  • Figure 60A shows the results of three transistors included in Sample 3A
  • Figure 60B shows the results of three transistors included in Sample 3B
  • Figure 60C shows the results of three transistors included in Sample 3C
  • Figure 60D shows the results of three transistors included in Sample 4A
  • Figure 60E shows the results of three transistors included in Sample 4B
  • Figure 60F shows the results of three transistors included in Sample 4C.
  • Figures 61A to 61C are graphs plotting ⁇ Vsh after a stress time of 20 hours has elapsed.
  • the vertical axis represents ⁇ Vsh after a stress time of 20 hours has elapsed ( ⁇ Vsh@20hr) [mV].
  • Figure 61A shows the results for the transistors included in Sample 3A and the transistors included in Sample 4A
  • Figure 61B shows the results for the transistors included in Sample 3B and the transistors included in Sample 4B
  • Figure 61C shows the results for the transistors included in Sample 3C and the transistors included in Sample 4C.
  • the amount of positive drift degradation in the +GBT stress test tends to increase as the amount of oxygen supplied to the oxide semiconductor increases.
  • the amount of oxygen molecules released from the insulator in contact with the oxide semiconductor is preferably 1.0 ⁇ 10 14 molecules/cm 2 or more and less than 1.0 ⁇ 10 15 molecules/cm 2 .
  • samples 5A to 5D having a laminate containing hafnium oxide were prepared and subjected to SIMS analysis.
  • a silicon oxide film having a thickness of 100 nm was formed on a silicon substrate by thermal oxidation treatment, and a first silicon nitride film (referred to as 1st-SiNx) having a thickness of 20 nm was formed on the silicon oxide film by sputtering.
  • the silicon oxide film was an oxide film formed using hydrogen chloride.

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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JP2018133550A (ja) * 2016-07-26 2018-08-23 株式会社半導体エネルギー研究所 半導体装置
WO2020174315A1 (ja) * 2019-02-28 2020-09-03 株式会社半導体エネルギー研究所 半導体装置、および半導体装置の作製方法

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JP2018133550A (ja) * 2016-07-26 2018-08-23 株式会社半導体エネルギー研究所 半導体装置
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