WO2024143385A1 - ＳｉＣ半導体装置 - Google Patents

ＳｉＣ半導体装置 Download PDF

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Publication number
WO2024143385A1
WO2024143385A1 PCT/JP2023/046706 JP2023046706W WO2024143385A1 WO 2024143385 A1 WO2024143385 A1 WO 2024143385A1 JP 2023046706 W JP2023046706 W JP 2023046706W WO 2024143385 A1 WO2024143385 A1 WO 2024143385A1
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region
layer
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regions
thickness
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PCT/JP2023/046706
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to DE112023004912.2T priority Critical patent/DE112023004912T5/de
Priority to JP2024567876A priority patent/JPWO2024143385A1/ja
Priority to CN202380088507.4A priority patent/CN120419308A/zh
Publication of WO2024143385A1 publication Critical patent/WO2024143385A1/ja
Priority to US19/243,725 priority patent/US20250318214A1/en
Anticipated expiration legal-status Critical
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Definitions

  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape in a plan view seen from the vertical direction Z (hereinafter simply referred to as "plan view").
  • the vertical direction Z is also the thickness direction of the chip 2 and the normal direction of the first main surface 3 (second main surface 4).
  • the first main surface 3 and the second main surface 4 may be formed in a square or rectangular shape in a plan view.
  • the chip 2 (first main surface 3 and second main surface 4) has an off angle ⁇ off inclined at a predetermined angle in a predetermined off direction Doff with respect to the c-plane of the SiC single crystal.
  • the c-axis ((0001) axis) of the SiC single crystal is inclined by the off angle ⁇ off from the vertical axis toward the off direction Doff.
  • the c-plane of the SiC single crystal is inclined by the off angle ⁇ off with respect to the horizontal plane.
  • the n-type impurity concentration of the first layer 8 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the first layer 8 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the first layer 8 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the first layer 8 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the SiC semiconductor device 1A includes a peripheral region 11 that is set outside the active region 10 in the chip 2.
  • the peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a planar view.
  • the peripheral region 11 extends in a band shape along the active region 10 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 10.
  • the multiple first regions 14 are arranged at intervals in the first array direction Da1 in the first layer 8, and are each formed in a strip shape extending in the first extension direction De1.
  • the first extension direction De1 is a direction that intersects or is perpendicular to the first array direction Da1.
  • the multiple first regions 14 are formed in a stripe shape extending in the first extension direction De1
  • the multiple first drift regions 16 are formed in a stripe shape extending in the first extension direction De1.
  • the multiple first regions 14 have an off direction Doff and an off angle ⁇ off that are approximately the same as the off direction Doff and the off angle ⁇ off of the first axis channel CH1. In other words, the multiple first regions 14 are inclined by the off angle ⁇ off from the vertical axis toward the off direction Doff.
  • the first upper end 14b may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a portion (upper end) of the first layer 8.
  • the first upper end 14b may be substantially coincident with the upper end of the first layer 8 and connected to the second layer 9.
  • the distance between the upper end of the first layer 8 and the first upper end 14b may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper end of the first layer 8 and the first upper end 14b may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the first regions 14 each have a first width W1.
  • the first width W1 is the width along the first arrangement direction Da1 of the first regions 14. It is preferable that the first width W1 is less than the first thickness T1 of the first layer 8. Of course, the first width W1 may be equal to or greater than the first thickness T1. It is preferable that the first width W1 is less than the second thickness T2 of the second layer 9. Of course, the first width W1 may be equal to or greater than the second thickness T2.
  • the first width W1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 may have a value belonging to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the first region thickness TR1 is preferably 1 ⁇ m or more.
  • the first region thickness TR1 is preferably 5 ⁇ m or less.
  • the first region thickness TR1 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 is less than the first thickness T1 of the first layer 8, and that the first region thickness TR1 is greater than the first width W1.
  • each of the multiple first regions 14 has a first aspect ratio TR1/W1 that extends in a vertically elongated columnar shape along the first axial channel CH1.
  • the first aspect ratio TR1/W1 is the ratio of the first region thickness TR1 to the first width W1.
  • the first region thickness TR1 is greater than the first thickness T1.
  • the first aspect ratio TR1/W1 may be greater than 1 and less than or equal to 100.
  • the first regions 14 are formed at intervals of a first pitch P1 in the first arrangement direction Da1. It is preferable that the first pitch P1 is less than the first thickness T1 of the first layer 8. Of course, the first pitch P1 may be equal to or greater than the first thickness T1. It is preferable that the first pitch P1 is less than the second thickness T2 of the second layer 9. Of course, the first pitch P1 may be equal to or greater than the second thickness T2.
  • the first pitch P1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch P1 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch P1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second regions 15 are formed in the second layer 9 at intervals in the horizontal direction, and define a plurality of n-type second drift regions 17, each of which is made up of a part of the second layer 9.
  • the multiple second regions 15 and the second layer 9 form a second superjunction structure SJ2.
  • the state of charge balance means that, for multiple adjacent second regions 15, the depletion layer extending from one second pn junction and the depletion layer extending from the other second pn junction are connected within the multiple second drift regions 17.
  • the second regions 15 are formed in the second layer 9 so as to overlap the first regions 14 in the stacking direction. Specifically, the second regions 15 are arranged at intervals in the second layer 9 in a second array direction Da2 different from the first array direction Da1, and are each formed in a band shape extending in a second extension direction De2 different from the first extension direction De1.
  • the second array direction Da2 is a direction that intersects with the first array direction Da1
  • the second extension direction De2 is a direction that intersects with the first extension direction De1.
  • the second extension direction De2 is a direction that intersects or is perpendicular to the second array direction Da2.
  • the multiple second regions 15 are formed in stripes extending in the second extension direction De2
  • the multiple second drift regions 17 are formed in stripes extending in the second extension direction De2.
  • the multiple second regions 15 intersect with the multiple first regions 14 in a planar view.
  • the multiple second drift regions 17 are connected in a lattice pattern to the multiple first drift regions 16 at the boundary between the first layer 8 and the second layer 9, and together with the multiple first drift regions 16 form a single three-dimensional lattice-shaped drift region 13.
  • the multiple second drift regions 17 form a three-dimensional lattice-shaped current path together with the multiple first drift regions 16.
  • the second regions 15 are made up of channeling regions (second channeling regions) that extend along the second axis channel CH2 in the second layer 9 in a cross-sectional view.
  • the second regions 15 are impurity regions that are introduced parallel or nearly parallel to the region (second axis channel CH2) surrounded by atomic rows along the low-index crystal axis in the second layer 9, and extend at an angle with respect to the first main surface 3.
  • the second regions 15 have an off direction Doff and an off angle ⁇ off that are approximately equal to the off direction Doff and the off angle ⁇ off of the second axis channel CH2. In other words, the second regions 15 are inclined by the off angle ⁇ off from the vertical axis toward the off direction Doff.
  • the second regions 15 each have a second lower end 15a at the lower end of the second layer 9 and a second upper end 15b at the upper end of the second layer 9.
  • the second lower end 15a is located in a region on the lower end side of the second layer 9 relative to the intermediate part of the thickness range of the second layer 9, and the second upper end 15b is located in a region on the upper end side of the second layer 9 relative to the intermediate part of the thickness range of the second layer 9.
  • the second regions 15 each consist of a single impurity region having a thickness (depth) that crosses the intermediate part of the second layer 9 along the second axial channel CH2.
  • the second lower end 15a may be formed with a gap from the lower end to the upper end of the second layer 9, and may face the first layer 8 (plurality of first regions 14) across a portion (lower end) of the second layer 9.
  • the second lower end 15a may be substantially coincident with the lower end of the second layer 9 and connected to the first layer 8.
  • the distance between the lower end of the second layer 9 and the second lower end 15a may be 0 ⁇ m or more and 2 ⁇ m or less.
  • the distance between the lower end of the second layer 9 and the second lower end 15a may have a value that belongs to any one of the ranges of 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the second upper end 15b may be formed at a distance from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the second layer 9 across a part (upper end) of the second layer 9.
  • the space between the first main surface 3 and the second upper end 15b of the second layer 9 may be used as a region for forming a device structure (other impurity regions, etc.).
  • the second upper end 15b may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).
  • the distance between the upper end of the second layer 9 and the second upper end 15b may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper end of the second layer 9 and the second upper end 15b may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the second regions 15 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration (peak value) of the second regions 15 may be equal to or more than the p-type impurity concentration (peak value) of the first region 14.
  • the p-type impurity concentration (peak value) of the second regions 15 may be less than the p-type impurity concentration (peak value) of the first region 14.
  • the p-type impurity concentration (peak value) of the second regions 15 may be approximately equal to the p-type impurity concentration (peak value) of the first region 14.
  • the second region thickness TR2 may be less than the first thickness T1 of the first layer 8.
  • the second region thickness TR2 may be greater than the first thickness T1.
  • the second region thickness TR2 may be approximately equal to the first thickness T1.
  • the second region thickness TR2 may be less than the first region thickness TR1 of the first region 14.
  • the second region thickness TR2 may be greater than the first region thickness TR1.
  • the second region thickness TR2 may be approximately equal to the first region thickness TR1.
  • the second region thickness TR2 is preferably 1 ⁇ m or more.
  • the second region thickness TR2 is preferably 5 ⁇ m or less.
  • the second region thickness TR2 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • a superjunction structure SJ having a two-layer structure is shown.
  • a superjunction structure SJ having a stacked structure of three or more layers may also be adopted.
  • a stack section 7 having a stacked structure of three or more layers may be formed, and a column region 12 having a stacked structure of three or more layers may be formed.
  • the third and subsequent semiconductor layers in the stack 7 are formed in the same configuration as the second layer 9.
  • the regions formed in the odd-numbered (2n+1: n is a natural number equal to or greater than 1) semiconductor layers are formed in the same configuration as the first region 14, and the regions formed in the even-numbered (2n+2) semiconductor layers are formed in the same configuration as the second region 15.
  • the (n+2)th region of the column region 12 is formed in the (n+2)th semiconductor layer in the same relationship as the (n+1)th region to the nth region.
  • the first arrangement direction Da1 of the first regions 14 may be the m-axis direction (first direction X), and the first extension direction De1 of the first regions 14 may be the a-axis direction (second direction Y).
  • first direction X the first direction
  • the multiple first regions 14 extend in the substantially vertical direction Z in a cross-sectional view seen from the a-plane of the SiC single crystal.
  • the multiple first regions 14 are inclined by substantially the off angle ⁇ off from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane of the SiC single crystal.
  • the first extension direction De1 intersects with the off direction Doff, so that the first regions 14 are inclined from the vertical axis toward the off direction Doff by approximately the off angle ⁇ off in a cross-sectional view seen from the a-plane of the SiC single crystal and in a cross-sectional view seen from the m-plane of the SiC single crystal.
  • the multiple second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction, and are perpendicular to the multiple first regions 14.
  • the sum of the absolute value of the first extension angle ⁇ 1 and the absolute value of the second extension angle ⁇ 2 is approximately a right angle (approximately 90°).
  • a region having a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more is defined as the second region 15 and is shown as a graph.
  • the values of the impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the second region 15 based on the concentration gradient, and are not shown with the intention of uniquely limiting the configuration of the second region 15.
  • the impurity concentration, thickness, etc. are adjusted to various values depending on the implantation conditions of the trivalent element (dose amount, implantation temperature, implantation energy, etc.), etc.
  • Peak portion 21 is a portion having a peak value P (maximum value) of the p-type impurity concentration. Peak portion 21 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend).
  • the depth position of peak portion 21 is 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • the gradually decreasing portion 23 is a portion that forms the second lower end 15a of the second region 15.
  • the gradually decreasing portion 23 has a concentration decrease rate that is greater than the concentration decrease rate in the gradual portion 22, and is a portion where the p-type impurity concentration gradually decreases from the gradual portion 22 toward the lower end of the second layer 9.
  • the concentration decrease rate per unit thickness of the gradually decreasing portion 23 is greater than the concentration decrease rate per unit thickness of the gradual portion 22.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual portion 22 to 1 ⁇ 10 15 cm -3 .
  • the second region 15 (380 KeV) has a second region thickness TR2 of 2.2 ⁇ m or more and 2.4 ⁇ m or less, and has a second lower end 15a spaced from the lower end to the upper end of the second layer 9, and a second upper end 15b spaced from the upper end (first main surface 3) of the second layer 9 to the lower end side (first layer 8 side).
  • the distance between the lower end of the second layer 9 and the second lower end 15a is 0.5 ⁇ m or more and 0.8 ⁇ m or less.
  • the distance between the upper end of the second layer 9 and the second upper end 15b of the second region 15 is 0.01 ⁇ m or more and 0.2 ⁇ m or less.
  • the p-type impurity concentration of the second region 15 has a concentration gradient from the second upper end 15b to the second lower end 15a, similar to the example of FIG. 11A, that includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23.
  • the gradually increasing portion 20 also increases gradually from the second upper end 15b of the second region 15 to the peak portion 21 at a relatively steep rate of increase.
  • the depth position of the peak portion 21 is 0.6 ⁇ m or more and 1 ⁇ m or less.
  • the second lower end 15a has an extension that crosses the boundary between the first layer 8 and the second layer 9 and extends into the first layer 8.
  • the extension of the second lower end 15a has a thickness of 1.4 ⁇ m or more and 1.8 ⁇ m or less based on the upper end of the first layer 8.
  • the distance between the upper end of the second layer 9 and the second upper end 15b of the second region 15 is 0.7 ⁇ m or more and 1 ⁇ m or less.
  • the gradual portion 22 has a thickness of 1.5 ⁇ m or more and 1.8 ⁇ m or less, and has a concentration decrease rate of 50% or less in this thickness range.
  • the gradual portion 22 crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. That is, the extension of the second region 15 includes a part of the gradual portion 22.
  • the p-type impurity concentration of the gradual portion 22 is within a concentration range of 2 ⁇ 10 16 cm ⁇ 3 or more and 4 ⁇ 10 16 cm ⁇ 3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual portion 22 to 1 ⁇ 10 15 cm ⁇ 3 .
  • the p-type impurity concentration of second region 15 has a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 at any implantation energy.
  • the second region thickness TR2 (depth) of second region 15 increases with increasing implantation energy.
  • the depth position of second upper end 15b of second region 15 relative to the upper end of second layer 9 increases with increasing implantation energy.
  • a second region 15 having a slow portion 22 with a thickness of 0.5 ⁇ m to 2 ⁇ m is formed in a second layer 9 having a relatively large thickness (for example, a thickness of 1 ⁇ m to 5 ⁇ m). Therefore, a second region 15 having a charge balance is formed with fewer steps than the steps required when the random injection method is adopted.
  • the p-type impurity concentration (concentration gradient) of each second region 15 is the sum of the p-type impurity concentrations (concentration gradients) of the multiple impurity regions (second regions 15).
  • the p-type impurity concentration of each second region 15 has a concentration gradient (sum of concentration gradients) obtained by superimposing at least two of the five graphs shown in Figures 11A to 11E.
  • the upper limit of the implantation energy for the channeling implantation method is 2000 KeV, but the second region 15 can also be formed with an implantation energy greater than 2000 KeV. In this case, a relatively thick second region 15 is formed at a position deeper than the concentration gradient shown in Figure 11E.
  • the amount of trivalent elements passing through the upper end of the second layer 9 increases, and the range of the free space on the upper end side (i.e., the distance between the first main surface 3 and the second region 15) expands, making it more difficult to design the column region 12.
  • the size of the ion accelerator may reach several tens of meters, which is considered to be unrealistic from the standpoint of cost-effectiveness (installation space and capital investment).
  • first to twelfth embodiment examples of the column region 12 are shown with reference to Figures 13 to 33.
  • the column region 12 according to the first to third basic embodiments may have at least one of the multiple features shown in the first to twelfth embodiment examples.
  • the column region 12 according to the first to third basic embodiments may have a feature that combines multiple (two or more) features shown in the first to twelfth embodiment examples.
  • the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 of the second layer 9.
  • the second region thickness TR2 is also greater than the first thickness T1 of the first layer 8.
  • the second region thickness TR2 is also greater than the first region thickness TR1 of the first region 14.
  • the second region thickness TR2 may be less than the second thickness T2.
  • the second region thickness TR2 may be less than the first region thickness TR1.
  • the second region thickness TR2 may be less than the first region thickness TR1.
  • the first region 14 has a first region thickness TR1 that is greater than the first thickness T1 of the first layer 8.
  • the first region thickness TR1 is also greater than the second thickness T2 of the second layer 9.
  • the first region thickness TR1 is also greater than the second region thickness TR2 of the second region 15.
  • the first region thickness TR1 may be less than the first thickness T1.
  • the first region thickness TR1 may be less than the second thickness T2.
  • the first region thickness TR1 may be less than the second region thickness TR2.
  • FIG. 21 is a cross-sectional perspective view showing the column region 12 according to the fifth embodiment.
  • FIG. 22 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 21.
  • the column region 12 according to the fifth embodiment has a shape obtained by modifying the first region 14 according to the fourth embodiment.
  • the second region 15 according to the fifth embodiment has a shape similar to that of the second region 15 according to the second embodiment.
  • the second region 15 according to the fifth embodiment may have a shape similar to that of the second region 15 according to the third embodiment.
  • the first region 14 may have a shape similar to any one of the shapes of the first region 14 according to the first to fifth embodiment examples.
  • the first region 14 has a shape similar to the shape of the first region 14 according to the fourth embodiment example.
  • the second region 15 may have a shape similar to any one of the shapes of the second region 15 according to the first to fifth embodiment examples.
  • the second region 15 has a shape similar to the shape of the second region 15 according to the fourth embodiment example (second embodiment example).
  • the intermediate regions 25 are formed in the first layer 8 in a region between the upper end of the first layer 8 and the first upper end 14b of the first region 14.
  • the intermediate regions 25 are preferably located on the upper end side of the first layer 8 relative to the middle part of the thickness range of the first layer 8.
  • the intermediate regions 25 may be exposed from the upper end of the first layer 8, or may be formed at intervals from the upper end to the lower end side of the first layer 8.
  • Each intermediate region 25 may be formed in a horizontally elongated columnar shape extending in the horizontal direction in a cross-sectional view. Of course, each intermediate region 25 may be formed in a vertically elongated columnar shape extending in the vertical direction Z.
  • the intermediate regions 25 form intermediate pn junctions having charge balance together with the first layer 8.
  • the intermediate regions 25 form part of the first superjunction structure SJ1 together with the first drift regions 16.
  • the state of having charge balance means that, for adjacent intermediate regions 25, the depletion layer extending from one intermediate pn junction and the depletion layer extending from the other intermediate pn junction are connected within the first drift regions 16.
  • the region element 25a does not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 in a range of 0.5 ⁇ m.
  • each intermediate region 25 has multiple peak portions 21 (peak value P) according to the number of multiple region elements 25a in the thickness direction of the first layer 8.
  • the p-type impurity concentration of the intermediate region 25 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the intermediate region 25 may be the same as the trivalent element of the first region 14, etc., or may be a different species from the trivalent element of the first region 14, etc.
  • the trivalent element of the intermediate region 25 may be at least one of boron, aluminum, gallium, and indium.
  • the intermediate width WM is approximately equal to the first width W1 of the first region 14.
  • the intermediate width WM may be greater than or equal to the first width W1, or less than the first width W1. It is preferable that the intermediate width WM is greater than or equal to 1 ⁇ m. It is preferable that the intermediate width WM is less than or equal to 5 ⁇ m.
  • the intermediate pitch PM may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the intermediate pitch PM may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the intermediate pitch PM is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second region 15 preferably has an extension located within the first layer 8 and is connected to the intermediate region 25 within the first layer 8.
  • the second region 15 preferably is electrically connected to the first region 14 via the intermediate region 25 within the first layer 8.
  • the second region 15 forms one drift region 13 that extends continuously in the stacking direction together with the first region 14 and the intermediate region 25.
  • the extension of the second region 15 may be connected to both the intermediate region 25 and the first region 14 within the first layer 8.
  • the concentration gradient in the region between the first region 14 and the second region 15 is mitigated by the intermediate region 25, improving the accuracy of the charge balance.
  • the first region 14 is exposed from the upper end of the first layer 8.
  • the first region 14 does not have part or all of the first gradually increasing portion 20A.
  • Figure 26 shows an example in which the first region 14 does not have all of the first gradually increasing portion 20A and the first peak portion 21A. That is, in this example, the first upper end 14b includes the first gradual portion 22A exposed from the upper end of the first layer 8.
  • the second region 15 has an extension located within the first layer 8 and is connected to the first region 14 within the first layer 8.
  • the concentration gradient formed in the region between the first region 14 and the second region 15 is mitigated by the exposed portion of the first region 14, improving the accuracy of the charge balance.
  • the upper end of the first layer 8 may be partially removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the upper end of the first layer 8 is an etched surface, and the first region 14 is exposed from the etched surface.
  • the second layer 9 is laminated on top of the etched surface of the first layer 8.
  • FIG. 27 is a cross-sectional perspective view showing the column region 12 according to the eighth embodiment.
  • FIG. 28 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 27.
  • the column region 12 according to the eighth embodiment has a form obtained by modifying the second region 15 according to the first to seventh embodiments.
  • the first region 14 according to the eighth embodiment may have a form similar to any one of the forms of the first region 14 according to the first to seventh embodiments.
  • the first region 14 according to the seventh embodiment is shown.
  • FIG. 29 is a cross-sectional perspective view showing the column region 12 according to the ninth embodiment.
  • FIG. 30 is a cross-sectional perspective view showing the column region 12 according to the tenth embodiment.
  • the stacked portion 7 may have a stacked structure including a buffer layer 26, a first layer 8, and a second layer 9 stacked in this order from the base layer 6 side.
  • the buffer layer 26 may be referred to as a "buffer SiC layer", a "buffer region”, etc.
  • the buffer axis channel CHBu is composed of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the buffer axis channel CHBu extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the buffer axis channel CHBu is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the buffer layer 26 has a buffer thickness TBu.
  • the buffer thickness TBu is preferably less than the base thickness TB.
  • the buffer thickness TBu is preferably 1 ⁇ m or more.
  • the buffer thickness TBu is preferably 5 ⁇ m or less.
  • the buffer thickness TBu may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first thickness T1 of the first layer 8 is preferably greater than the buffer thickness TBu.
  • the first thickness T1 may be less than the buffer thickness TBu.
  • the first thickness T1 may be approximately equal to the buffer thickness TBu.
  • the second thickness T2 of the second layer 9 is preferably greater than the buffer thickness TBu.
  • the second thickness T2 may be less than the buffer thickness TBu.
  • the second thickness T2 may be approximately equal to the buffer thickness TBu.
  • the first lower end 14a may have an extension that crosses the boundary between the buffer layer 26 and the first layer 8 and is located within the buffer layer 26. Since the first axial channel CH1 is approximately coincident with the buffer axial channel CHBu, the extension of the first lower end 14a is formed along the buffer axial channel CHBu within the buffer layer 26.
  • Figure 31 is a cross-sectional perspective view showing a column region 12 according to an eleventh embodiment.
  • a superjunction structure SJ having a stacked structure of three or more layers may be adopted.
  • Figure 31 shows a stacked portion 7 having a three-layer structure and a column region 12 having a three-layer structure.
  • the laminated portion 7 includes an n-type third layer 27 made of single crystal SiC laminated on the second layer 9.
  • the third layer 27 may be referred to as a "third SiC layer", a "third semiconductor layer”, or the like.
  • the second layer 9 forms the middle portion of the chip 2 and forms part of the first to fourth side surfaces 5A to 5D.
  • the third layer 27 extends in a layered manner in the horizontal direction, forms the first main surface 3, and forms part of the first to fourth side surfaces 5A to 5D.
  • the third layer 27 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the second layer 9.
  • the third layer 27 has a lower end and an upper end.
  • the lower end of the third layer 27 is the starting point of crystal growth, and the upper end of the third layer 27 is the end point of crystal growth. Since the third layer 27 is grown continuously from the second layer 9, the lower end of the third layer 27 coincides with the upper end of the second layer 9.
  • the boundary between the second layer 9 and the third layer 27 is not necessarily visible, and can be indirectly evaluated and/or determined from other configurations or elements.
  • the third layer 27 has an off direction Doff and an off angle ⁇ off that are approximately the same as the off direction Doff and the off angle ⁇ off of the second layer 9.
  • the third axis channel CH3 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the third axis channel CH3 extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the third axis channel CH3 is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the n-type impurity concentration of the third layer 27 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the third layer 27 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the third layer 27 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the third layer 27 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the third layer 27 has a third thickness T3.
  • the third thickness T3 is preferably less than the base thickness TB.
  • the third thickness T3 may be approximately equal to the second thickness T2, may be greater than or equal to the second thickness T2, or may be less than the second thickness T2.
  • the third thickness T3 may be approximately equal to the first thickness T1, may be greater than or equal to the first thickness T1, or may be less than the first thickness T1.
  • the third thickness T3 is preferably 1 ⁇ m or more.
  • the third thickness T3 is preferably 5 ⁇ m or less.
  • the third thickness T3 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the column region 12 includes a third region 28 formed in the third layer 27.
  • the third regions 28 are formed horizontally at intervals in the third layer 27, and define a plurality of n-type third drift regions 29 each made of a part of the third layer 27.
  • the third regions 28 form a plurality of third pn junctions having charge balance together with the third drift regions 29.
  • the multiple third regions 28 and the third layer 27 form a third superjunction structure SJ3.
  • the state of charge balance means that, for multiple adjacent third regions 28, the depletion layer extending from one third pn junction and the depletion layer extending from the other third pn junction are connected within the multiple third drift regions 29.
  • the third regions 28 are formed in the third layer 27 so as to overlap the second regions 15 in the stacking direction. Specifically, the third regions 28 are arranged at intervals in the third layer 27 in a third array direction Da3 different from the second array direction Da2, and are each formed in a band shape extending in a third extension direction De3 different from the second extension direction De2. In other words, the third regions 28 are formed in stripes extending in the third extension direction De3, and the third drift regions 29 are formed in stripes extending in the third extension direction De3.
  • the multiple third regions 28 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and may face either one or both of the first regions 14 and the first drift region 16 in the stacking direction.
  • the third array direction Da3 may be different from the first array direction Da1.
  • the third extension direction De3 may be different from the first extension direction De1.
  • the multiple third regions 28 may intersect (for example, perpendicular to) the multiple first regions 14 in a planar view.
  • the multiple third regions 28 are made up of channeling regions (third channeling regions) that extend along the third axis channel CH3 in the third layer 27 in a cross-sectional view.
  • the third regions 28 are impurity regions that are introduced parallel or nearly parallel to the region (third axis channel CH3) surrounded by the atomic rows along the low-index crystal axis in the third layer 27, and extend at an angle with respect to the first main surface 3.
  • the third regions 28 each have a third lower end 28a at the lower end of the third layer 27 and a third upper end 28b at the upper end of the third layer 27.
  • the third lower end 28a is located in a region on the lower end side of the third layer 27 relative to the intermediate part of the thickness range of the third layer 27, and the third upper end 28b is located in a region on the upper end side of the third layer 27 relative to the intermediate part of the thickness range of the third layer 27.
  • the third regions 28 each consist of a single impurity region having a thickness (depth) that crosses the intermediate part of the third layer 27 along the third axial channel CH3.
  • the third lower end 28a may be formed with a gap from the lower end of the third layer 27 toward the upper end, and may face the second layer 9 across a portion (lower end) of the third layer 27.
  • the third lower end 28a may be substantially coincident with the lower end of the third layer 27 and connected to the second layer 9.
  • the distance between the lower end of the third layer 27 and the third lower end 28a may be 0 ⁇ m or more and 2 ⁇ m or less.
  • the distance between the lower end of the third layer 27 and the third lower end 28a may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the p-type impurity concentration of the third region 28 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the third region 28 is adjusted by a trivalent element that is heavier than carbon. In other words, the third region 28 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the third region 28 is adjusted by aluminum.
  • the third width W3 may be greater than or equal to the first width W1 of the first region 14, or less than the first width W1. It is preferable that the third width W3 is approximately equal to the first width W1.
  • the third width W3 may be greater than or equal to the second width W2 of the second region 15, or less than the second width W2. It is preferable that the third width W3 is approximately equal to the second width W2.
  • the multiple third regions 28 each have a third region thickness TR3.
  • the third region thickness TR3 may be less than the third thickness T3 of the third layer 27.
  • the third region thickness TR3 may be greater than the third thickness T3.
  • the third region thickness TR3 may be approximately equal to the third thickness T3.
  • the third region thickness TR3 may be less than the first thickness T1 of the first layer 8. The third region thickness TR3 may be greater than the first thickness T1. The third region thickness TR3 may be approximately equal to the first thickness T1. The third region thickness TR3 may be less than the second thickness T2 of the second layer 9. The third region thickness TR3 may be greater than the second thickness T2. The third region thickness TR3 may be approximately equal to the second thickness T2.
  • the third region thickness TR3 is preferably 1 ⁇ m or more.
  • the third region thickness TR3 is preferably 5 ⁇ m or less.
  • the third region thickness TR3 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the third width W3 is less than the third thickness T3 of the third layer 27, and that the third region thickness TR3 is greater than the third width W3.
  • each of the multiple third regions 28 has a third aspect ratio TR3/W3 that extends in a vertically elongated columnar shape along the third axial channel CH3.
  • the third aspect ratio TR3/W3 is the ratio of the third region thickness TR3 to the third width W3.
  • the third region thickness TR3 is greater than the third thickness T3.
  • the third aspect ratio TR3/W3 may be greater than 1 and less than or equal to 100.
  • the third regions 28 are formed at intervals of a third pitch P3 in the third arrangement direction Da3. It is preferable that the third pitch P3 is less than the third thickness T3 of the third layer 27. Of course, the third pitch P3 may be equal to or greater than the third thickness T3. It is preferable that the third pitch P3 is less than the first thickness T1 of the first layer 8. Also, it is preferable that the third pitch P3 is less than the second thickness T2 of the second layer 9. Of course, the third pitch P3 may be equal to or greater than the first thickness T1. Also, the third pitch P3 may be equal to or greater than the second thickness T2.
  • the third pitch P3 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the third pitch P3 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the third pitch P3 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • FIG. 32 is a cross-sectional perspective view showing the column region 12 according to the twelfth embodiment.
  • the stacked portion 7 in this example includes a top layer 30 of n-type single crystalline SiC stacked on the second layer 9.
  • the top layer 30 is formed to separate the first main surface 3 from the column region 12.
  • the top layer 30 also forms at least a part of the region between the first main surface 3 and the second upper ends 15b of the multiple second regions 15.
  • the top layer 30 may be considered to be a portion that forms the upper ends of the second layer 9.
  • the top layer 30 has an n-type conductivity, but the conductivity type of the top layer 30 can be adjusted as appropriate depending on the properties of the device structure formed on the first main surface 3. Therefore, the conductivity type of the top layer 30 does not necessarily need to be limited to n-type, and may be p-type.
  • the body regions 32 are each formed in a region between the first main surface 3 and the second upper ends 15b of the second regions 15.
  • the body regions 32 are preferably formed on the first main surface 3 side relative to the intermediate portion of the thickness range of the second layer 9, and are preferably exposed from the first main surface 3.
  • the body regions 32 are preferably connected to the corresponding second regions 15 (second upper ends 15b).
  • the SiC semiconductor device 1A includes multiple gate structures 35 of a planar electrode type arranged on the first main surface 3 in the active region 10.
  • the gate structures 35 may be referred to as "planar gate structures.”
  • the multiple gate structures 35 are arranged at intervals on the first main surface 3 so as to overlap at least one body region 32 (channel) in the stacking direction.
  • a gate potential is applied to the multiple gate structures 35 as a control potential.
  • the multiple gate structures 35 control the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.
  • the multiple field regions 38 are preferably formed at a pitch different from the second pitch P2 of the second region 15 (the first pitch P1 of the first region 14). It is particularly preferable that the pitch of the multiple field regions 38 is larger than the second pitch P2 (the first pitch P1). Of course, the pitch of the multiple field regions 38 may be smaller than the second pitch P2 (the first pitch P1). Also, the pitch of the multiple field regions 38 may be approximately equal to the second pitch P2 (the first pitch P1).
  • the SiC semiconductor device 1A includes an interlayer insulating film 40 covering the first main surface 3.
  • the interlayer insulating film 40 may be referred to as an "insulating film,” an "interlayer film,” an “intermediate insulating film,” or the like.
  • the interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 includes a silicon oxide film made of an oxide of the chip 2 (second layer 9).
  • the source pad 47 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10.
  • the source pad 47 may be disposed at a distance from the peripheral region 11 toward the active region 10.
  • the source pad 47 is formed in a polygonal shape having a recess that is recessed along the gate pad 45 in a plan view.
  • the source pad 47 may also be formed in a rectangular shape in a plan view.
  • the source pad 47 penetrates the interlayer insulating film 40 through a plurality of contact openings 43, and is electrically connected to a plurality of body regions 32, a plurality of source regions 33, and a plurality of contact regions 34. In other words, the source pad 47 is electrically connected to the column region 12 through a plurality of body regions 32.
  • the SiC semiconductor device 1A includes a drain pad 48 covering the second main surface 4.
  • the drain pad 48 is an electrode to which a drain potential is applied from the outside.
  • the drain pad 48 may be referred to as a "drain pad electrode", a “third pad electrode”, etc.
  • the drain pad 48 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.
  • the drain pad 48 is electrically connected to the first layer 8 (the multiple first drift regions 16) and the second layer 9 (the multiple second drift regions 17) via the base layer 6.
  • the breakdown voltage that can be applied between the source pad 47 and the drain pad 48 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to any one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 36 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment.
  • the multiple gate structures 35 according to the first embodiment extend along the second extension direction De2 of the multiple second regions 15.
  • the multiple gate structures 35 according to the second embodiment extend in a direction other than the second extension direction De2 so as to intersect with the multiple second regions 15.
  • each body region 32 may face multiple first drift regions 16 in the stacking direction.
  • the multiple body regions 32 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.
  • the arrangement direction and extension direction of the multiple body regions 32 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple gate structures 35 may face the multiple first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may face the multiple first regions 14 in the stacking direction. The multiple gate structures 35 may face the multiple first drift regions 16 in a one-to-one correspondence in the stacking direction.
  • each gate structure 35 may face multiple first drift regions 16 in the stacking direction.
  • the multiple gate structures 35 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.
  • the arrangement direction and extension direction of the multiple gate structures 35 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14 (body regions 32). Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the arrangement direction of the multiple gate structures 35 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2.
  • the extension direction of the multiple gate structures 35 may be a direction other than the first extension direction De1 and the second extension direction De2.
  • the multiple gate structures 35 may intersect both the multiple first regions 14 and the multiple second regions 15 in a planar view. In this case, a configuration in which the arrangement direction of the multiple gate structures 35 is one of the a-axis direction and the m-axis direction, and the extension direction of the multiple gate structures 35 is the other of the a-axis direction and the m-axis direction, is not prevented.
  • the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°.
  • the angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the multiple gate structures 35 are each arranged to straddle two adjacent body regions 32, and each cover the multiple source regions 33 located in one and the other body region 32. In addition, the multiple gate structures 35 each face the multiple second regions 15 (second regions 15) and the multiple second drift regions 17 in the stacking direction.
  • FIG 37 is a schematic diagram showing a wafer 50 used in the manufacture of SiC semiconductor device 1A.
  • Wafer 50 is a substrate for base layer 6 and contains SiC single crystal.
  • Wafer 50 is formed in a flat disk shape. Of course, wafer 50 may also be formed in a flat rectangular parallelepiped shape.
  • Wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting first wafer main surface 51 and second wafer main surface 52.
  • the wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal.
  • the mark 54 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 51 in a plan view.
  • a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like.
  • Each device region 55 corresponds to the SiC semiconductor device 1A.
  • Each of the plurality of device regions 55 is set to have a rectangular shape in a plan view.
  • FIG. 38 is a flow chart showing an example of a method for manufacturing a SiC semiconductor device 1A.
  • FIG. 39A to FIG. 39H are cross-sectional perspective views showing an example of a method for manufacturing a SiC semiconductor device 1A.
  • FIG. 40A to FIG. 40B are schematic diagrams for explaining the crystal orientation measurement process.
  • FIG. 41A to FIG. 41B are schematic diagrams for explaining the ion implantation process.
  • FIG. 39A to FIG. 39H show cross-sectional perspective views of a portion of an active region 10 of one device region 55.
  • step S1 in FIG. 38 the aforementioned wafer 50 preparation process is performed (step S1 in FIG. 38).
  • a determination process is performed as to whether or not an n-type buffer layer 26 (see FIG. 29 and FIG. 30) formation process is performed (step S2 in FIG. 38). If a buffer layer 26 is to be formed (step S2 in FIG. 38: YES), the buffer layer 26 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth (step S3 in FIG. 38). If a buffer layer 26 formation process is not performed (step S2 in FIG. 38: NO), this process is omitted.
  • the X-ray diffraction device 57 includes an irradiation unit 58 and a detection unit 59, and performs the rocking curve measurement method.
  • the irradiation unit 58 irradiates the incident X-ray L1 having a predetermined incident angle ⁇ with respect to the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).
  • the incident angle ⁇ is defined as the angle between the incident X-ray L1 and the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).
  • the rocking curve measurement method is performed only at one location (e.g., the center) of the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50). If in-plane variation in the off angle ⁇ off is expected, the rocking curve measurement method may be performed at multiple locations (e.g., the center and peripheral areas) of the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50).
  • the fourth measurement point Po4 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the second direction Y (the side toward the mark 54).
  • the fifth measurement point Po5 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the first direction X (to the left of the mark 54).
  • the measurement results of the incident angle ⁇ , diffraction angle 2 ⁇ , and off angle ⁇ off at the first to fifth measurement points Po1 to Po5 are shown in the following Table 1.
  • the off angle ⁇ off is calculated using the incident angle ⁇ and diffraction angle 2 ⁇ by the formula " ⁇ -(2 ⁇ 1/2)".
  • the average value of the off angle ⁇ off of the first to fifth measurement points Po1 to Po5 was 4.036°, and the standard deviation of these off angles ⁇ off was 0.009° ( ⁇ 0.01°). From this, it can be understood that the in-plane variation of the off angle ⁇ off occurring at the upper end of the first layer 8 (first wafer main surface 51 of wafer 50) is extremely small, and is not enough to interfere with the channeling implantation process.
  • the measurement point may be any one or more (all) of the first to fifth measurement points Po1 to Po5.
  • the measurement point may be only the first measurement point Po1.
  • the off angle ⁇ off may be measured at multiple points on the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50) and an implantation angle may be set in the channeling implantation process according to the in-plane variation of the off angle ⁇ off.
  • the manufacturing man-hours manufactured costs
  • the in-plane error of the first region 14 formed in the first layer 8 is appropriately suppressed.
  • the off-angle ⁇ off of the first layer 8 is approximately equal to the off-angle ⁇ off of the wafer 50 and the off-angle ⁇ off of the buffer layer 26. Therefore, the crystal orientation measurement process may be performed on the wafer 50 or the buffer layer 26 prior to the formation process of the first layer 8. However, from the standpoint of ensuring accuracy, it is preferable that the crystal orientation measurement process be performed on the first layer 8.
  • a step of forming a first mask 60 having a predetermined pattern is carried out (step S6 in FIG. 38).
  • the first mask 60 is preferably an organic mask (resist mask).
  • the first mask 60 is disposed on the upper end of the first layer 8, and has a plurality of first openings 61 that expose areas in the first layer 8 where a plurality of first regions 14 are to be formed.
  • the multiple first openings 61 are formed at intervals in the first array direction Da1, and are each partitioned into bands extending in the first extension direction De1.
  • a process for forming a plurality of first regions 14 is carried out (step S7 in FIG. 38).
  • the process for forming a plurality of first regions 14 includes a channeling injection process of a trivalent element (p-type impurity) into the first layer 8.
  • the first layer 8 (wafer 50) has an off angle ⁇ off inclined at a predetermined angle in a predetermined off direction Doff with respect to the first wafer main surface 51.
  • the channeling injection process is carried out based on data (information) of the off angle ⁇ off.
  • a trivalent element is introduced into the first layer 8 with a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle ⁇ off) (see also FIG. 12).
  • a trivalent element is implanted along the vertical direction Z perpendicular to the upper end of the first layer 8 (first wafer main surface 51).
  • the trivalent element is introduced along a direction in which the atomic rows are relatively dense in plan view, so the trivalent element collides with the atomic rows at a relatively shallow depth position. Therefore, the atomic rows prevent the introduction of the trivalent element into the first layer 8 at a relatively deep depth position. As a result, a first region 14 that does not have a slow portion 22 is formed (see also FIG. 12).
  • the injection angle of the trivalent element into the first layer 8 is controlled, and the trivalent element is introduced into the first layer 8 along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined injection energy (also refer to FIGS. 11A to 11E).
  • a predetermined injection energy also refer to FIGS. 11A to 11E.
  • the wafer 50 may be supported horizontally and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • the wafer 50 may be supported tilted by the off angle ⁇ off from the horizontal and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • a plurality of first regions 14 having a predetermined thickness are formed at a predetermined depth (see also Figures 11A to 11E).
  • the implantation energy of the trivalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection temperature of the trivalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the trivalent element is introduced along the first axial channel CH1, in which the atomic rows are relatively sparse in plan view.
  • the trivalent element travels through the first axial channel CH1 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the first layer 8.
  • the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.
  • a trivalent element belonging to the heavy elements heavier than carbon is introduced into the first layer 8.
  • the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium).
  • the trivalent element is aluminum.
  • the first extension direction De1 may be the a-axis direction or the m-axis direction.
  • the first extension direction De1 may be a direction other than the a-axis direction or the m-axis direction.
  • the trivalent element is introduced into the first layer 8 through the multiple first openings 61 at an angle of approximately the off angle ⁇ off with respect to the upper end of the first layer 8 in a cross-sectional view along the first array direction Da1.
  • first extension direction De1 is a direction other than the a-axis direction and the m-axis direction (see also Figures 10A to 10C, etc.), there is no need to strictly control the alignment misalignment of the multiple first regions 14 with respect to the crystal orientation of the SiC single crystal.
  • the trivalent element may be electrically activated by an annealing method, and at the same time, lattice defects and the like that have occurred in the first layer 8 may be repaired.
  • the annealing temperature for the first layer 8 may be 500°C or higher and 2000°C or lower. This forms a first superjunction structure SJ1 at the same time that a plurality of first regions 14 are formed. After the step of forming a plurality of first regions 14, the first mask 60 is removed.
  • a determination step is performed as to whether or not a thickness adjustment step for the first layer 8 is to be performed (step S8 in FIG. 38). If the thickness of the first layer 8 is to be adjusted (step S8 in FIG. 38: YES), the first layer 8 is thinned from the upper end side (step S9 in FIG. 38).
  • the thickness adjustment process may include a step of exposing the first regions 14 from the upper end of the first layer 8 (see also Figures 25 to 28, etc.). In other words, the thickness adjustment process may include a step of removing part or all of the first gradually increasing portions 20A of the first regions 14. If the thickness adjustment process is not performed (Step S8 in Figure 38: NO), this step is omitted.
  • the process of forming the multiple intermediate regions 25 includes placing a mask (not shown) having a predetermined pattern on the upper end of the first layer 8.
  • the mask (not shown) is preferably an organic mask (resist mask).
  • the mask (not shown) has multiple openings that expose the areas in the first layer 8 where the multiple first regions 14 are formed.
  • the multiple openings are formed at intervals in the first direction X, and are each partitioned into bands extending in the second direction Y.
  • the process of forming the multiple intermediate regions 25 includes a process of introducing a trivalent element into the first layer 8 with a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle ⁇ off) by a random implantation method through a mask (not shown) (see also FIG. 12).
  • the trivalent element may be introduced into the first layer 8 once or multiple times.
  • a step of forming a second mask 62 having a predetermined pattern is performed (step S13 in FIG. 38).
  • the second mask 62 is preferably an organic mask (resist mask).
  • the second mask 62 is disposed on the upper end of the first layer 8, and has a plurality of second openings 63 that expose areas in the first layer 8 where a plurality of second regions 15 are to be formed.
  • the multiple second openings 63 are formed at intervals in a second arrangement direction Da2 different from the first arrangement direction Da1, and are each partitioned into bands extending in a second extension direction De2 different from the first extension direction De1.
  • a process for forming a plurality of second regions 15 is carried out (step S14 in FIG. 38).
  • the process for forming a plurality of second regions 15 includes a channeling injection process of a trivalent element (p-type impurity) into the second layer 9.
  • the channeling injection process is carried out based on the data (information) of the off angle ⁇ off described above.
  • the injection angle of the trivalent element into the second layer 9 is controlled, and the trivalent element is introduced into the second layer 9 along the second axial channel CH2 (the c-axis of the SiC single crystal in this embodiment) with a predetermined injection energy (see also Figures 11A to 11E).
  • a predetermined injection energy see also Figures 11A to 11E.
  • the wafer 50 may be supported horizontally and the trivalent element may be introduced into the second layer 9 along the second axial channel CH2.
  • the wafer 50 may be supported tilted by the off angle ⁇ off from the horizontal and the trivalent element may be introduced into the second layer 9 along the second axial channel CH2.
  • a plurality of second regions 15 having a predetermined thickness are formed at a predetermined depth (see also Figures 11A to 11E).
  • the second extension direction De2 is also a direction other than the a-axis direction and the m-axis direction.
  • the multiple first regions 14 have a first extension angle ⁇ 1 inclined toward one side of the m-axis with respect to the a-axis
  • the multiple second regions 15 have a second extension angle ⁇ 2 toward the other side of the m-axis with respect to the a-axis.
  • FIG. 42 is a plan view showing a SiC semiconductor device 1B according to the second embodiment.
  • FIG. 43 is a cross-sectional view taken along line XLIII-XLIII shown in FIG. 42.
  • FIG. 44 is a plan view showing an example layout of chip 2.
  • FIG. 45 is a perspective view showing an example layout of chip 2.
  • the active surface 71 may be referred to as the "first surface portion,” the outer peripheral surface 72 as the “second surface portion,” the first to fourth connection surfaces 73A to 73D as the “connection surface portions,” and the active plateau 74 as the “mesa portion.”
  • the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D may be considered to be components of the chip 2 (first main surface 3).
  • the outer peripheral surface 72 is formed in the outer peripheral region 11. In other words, the outer peripheral surface 72 is formed outside the active surface 71.
  • the outer peripheral surface 72 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) relative to the active surface 71. Specifically, in this embodiment, the outer peripheral surface 72 is recessed to a depth less than the thickness of the second layer 9 so as to expose the second layer 9.
  • the outer peripheral surface 72 extends in a band shape along the active surface 71 in a plan view, and is formed in a ring shape (specifically a square ring shape) surrounding the active surface 71.
  • the SiC semiconductor device 1B includes a p-type body region 32 formed in the surface layer of the first main surface 3 (active surface 71).
  • the body region 32 is formed in a layer extending along the active surface 71.
  • the body region 32 may be formed over the entire active surface 71 and exposed from the first to fourth connection surfaces 73A to 73D.
  • the body region 32 is formed at a distance from the lower end of the second layer 9 toward the active surface 71, and overlaps the column region 12 (the multiple second regions 15) in the stacking direction.
  • the body region 32 is preferably formed at a distance from the depth position of the outer peripheral surface 72 toward the active surface 71, and is exposed from the first main surface 3.
  • the body region 32 is formed in the region between the active surface 71 and the second upper ends 15b of the multiple second regions 15.
  • the body region 32 is preferably connected to the multiple second regions 15 (the second upper ends 15b).
  • body region 32 does not have gradual portion 22 having a thickness of 0.5 ⁇ m or more, and has a concentration gradient including gradually increasing portion 20, peak portion 21, and gradually decreasing portion 23 within a range of 0.5 ⁇ m.
  • Body region 32 may have a peak value of a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the multiple gate structures 35 are arranged at intervals inward from the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 in the active region 10.
  • the multiple gate structures 35 are arranged at intervals in the second array direction Da2, and are each formed in a strip shape extending in the second extension direction De2. That is, in this embodiment, the multiple gate structures 35 are arranged in stripes extending along the multiple second regions 15, and intersect with the multiple first regions 14 and the multiple first drift regions 16 in the stacking direction.
  • the second array direction Da2 is the m-axis direction (first direction X), and the second extension direction De2 is the a-axis direction (second direction Y).
  • the array direction and extension direction of the multiple gate structures 35 are changed according to the second array direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second array direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction.
  • the second array direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple gate structures 35 are arranged offset from the multiple second regions 15 toward the multiple second drift regions 17. Specifically, the multiple gate structures 35 penetrate the body region 32 at intervals from the multiple second regions 15, and are arranged in a one-to-one correspondence within the multiple second drift regions 17. In other words, the multiple gate structures 35 are arranged alternately with the multiple second regions 15 along the second array direction Da2, and face the multiple second regions 15 in the horizontal direction.
  • the multiple gate structures 35 are formed at intervals from the lower ends of the multiple second drift regions 17 toward the active surface 71, and face the multiple first regions 14 and the multiple first drift regions 16 across parts of the multiple second drift regions 17. It is preferable that the multiple gate structures 35 are formed at intervals from the intermediate portions of the thickness ranges of the multiple second regions 15 toward the active surface 71. Of course, the multiple gate structures 35 may be formed at a depth position that crosses the intermediate portions of the thickness ranges of the multiple second regions 15.
  • Each gate structure 35 has a trench width WT in the arrangement direction (first direction X in this embodiment) and a trench depth DT in the vertical direction Z.
  • the trench width WT is less than the second pitch P2 (first pitch P1).
  • the trench depth DT is less than the second thickness T2 of the second layer 9. It is preferable that the trench depth DT is approximately equal to the aforementioned peripheral depth DO. Of course, the trench depth DT may be greater than or equal to the peripheral depth DO, or may be less than the peripheral depth DO.
  • the trench depth DT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, and 4 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of an oxide of the chip 2.
  • the buried electrode 77 is embedded in the trench 75 with the insulating film 76 in between, and faces the channel with the insulating film 76 in between.
  • the buried electrode 77 may include p-type or n-type conductive polysilicon.
  • the SiC semiconductor device 1B includes a plurality of source regions 33 formed on both sides of a plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71).
  • the plurality of source regions 33 are formed in a surface layer portion of the body region 32.
  • the plurality of source regions 33 have a higher n-type impurity concentration (peak value) than the second layer 9 (second drift region 17).
  • the plurality of source regions 33 may have an n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the multiple source regions 33 extend in a band shape along the corresponding gate structures 35 in a plan view.
  • the multiple source regions 33 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the second drift region 17 across a portion of the body region 32 in the stacking direction.
  • the multiple source regions 33, together with the multiple second drift regions 17 located directly below, define a channel (current path) that extends along the wall surface of the corresponding gate structure 35.
  • the multiple source regions 33 may face the second region 15 across a portion of the body region 32 in the stacking direction.
  • the multiple source regions 33 may be formed at intervals from the second region 15 to the second drift region 17 side (gate structure 35 side) so as not to face the second region 15 in the stacking direction.
  • the plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32.
  • the p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second regions 15.
  • the plurality of contact regions 34 may have a p-type impurity concentration (peak value) of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the multiple contact regions 34 may face the second drift region 17 across a portion of the body region 32 in the stacking direction.
  • the multiple contact regions 34 may be formed at intervals from the second drift region 17 toward the second region 15 so as not to face the second drift region 17 in the stacking direction.
  • the bottom of the well region 78 is located closer to the lower end of the second layer 9 than the bottom wall of the gate structure 35. It is preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the second lower ends 15a of the second regions 15. It is particularly preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the intermediate portions of the thickness ranges of the second regions 15.
  • the multiple field regions 38 are arranged at intervals from the periphery of the active surface 71 (first to fourth connection surfaces 73A to 73D) and the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). Specifically, the multiple field regions 38 are arranged at intervals from the well region 78 to the periphery side of the outer circumferential surface 72.
  • the multiple field regions 38 extend in a band shape along the active surface 71 in a plan view, and are formed in a ring shape (specifically, a square ring shape) surrounding the active surface 71.
  • the multiple field regions 38 are formed at intervals from the bottom of the second layer 9 toward the outer circumferential surface 72, and face the first layer 8 with a part of the second layer 9 in between.
  • the multiple field regions 38 are located closer to the lower end of the second layer 9 than the bottom of the gate structure 35.
  • the first insulating film 41 covers the well region 78 and the multiple field regions 38 on the outer peripheral surface 72.
  • the first insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D.
  • the first insulating film 41 may be formed at a distance inward from the periphery of the outer peripheral surface 72, exposing the second layer 9 from the periphery of the outer peripheral surface 72.
  • the first insulating film 41 covers the well region 78 on the first to fourth connection surfaces 73A to 73D.
  • the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 covers the multiple gate structures 35 in the active region 10.
  • the second insulating film 42 covers the multiple field regions 38 and well regions 78 in the outer peripheral region 11, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 is continuous with the first to fourth side surfaces 5A to 5D.
  • the second insulating film 42 may be formed at a distance inward from the periphery of the outer peripheral surface 72, and the second layer 9 may be exposed from the periphery of the outer peripheral surface 72 together with the first insulating film 41.
  • the SiC semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40.
  • the plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (buried electrodes 77), and a plurality of contact openings 43 that expose a plurality of source regions 33.
  • the plurality of contact openings 43 for the source regions 33 are formed in the regions between the plurality of adjacent gate structures 35, and expose the plurality of source regions 33 and the plurality of contact regions 34.
  • the SiC semiconductor device 1B includes a sidewall structure 79 disposed in the interlayer insulating film 40 so as to cover at least one of the first to fourth connection surfaces 73A to 73D.
  • the sidewall structure 79 is disposed on the first insulating film 41 and is covered by the second insulating film 42.
  • the sidewall structure 79 reduces the step formed between the active surface 71 and the outer peripheral surface 72.
  • the sidewall structure 79 is formed in a band shape extending along at least one of the first to fourth connection surfaces 73A to 73D.
  • the sidewall structure 79 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 73A to 73D so as to surround the active surface 71 in a plan view.
  • the sidewall structure 79 may have a portion that extends in a film-like manner along the outer peripheral surface 72, and a portion that extends in a film-like manner along the first to fourth connection surfaces 73A to 73D.
  • the sidewall structure 79 is formed at a distance from the innermost field region 38 toward the active surface 71, and faces the well region 78 in the horizontal direction and stacking direction, sandwiching the first insulating film 41 therebetween.
  • the sidewall structure 79 may face the body region 32, sandwiching the first insulating film 41 therebetween.
  • the SiC semiconductor device 1B includes a gate pad 45, a plurality of gate wirings 46, a source pad 47, and a drain pad 48.
  • the drain pad 48 is formed in the same manner as in the first embodiment.
  • the gate pad 45 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view.
  • the gate pad 45 is disposed in a region close to the center of one side of the active surface 71 (the second connection surface 73B in this embodiment) in a plan view.
  • the gate pad 45 may also be disposed at a corner of the active surface 71 or in the center of the active surface 71 in a plan view.
  • the multiple gate wirings 46 are arranged on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view.
  • the multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.
  • the first gate wiring 46A is pulled out from the gate pad 45 toward the first connection surface 73A and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, perpendicular to) a portion (specifically, one end) of the multiple gate structures 35.
  • the first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35 (buried electrodes 77).
  • the second gate wiring 46B is pulled out from the gate pad 45 toward the third connection surface 73C and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, perpendicular to) a portion (specifically, the other end) of the multiple gate structures 35.
  • the second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other end of the multiple gate structures 35 (buried electrodes 77).
  • the source pad 47 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view.
  • the source pad 47 penetrates the interlayer insulating film 40 via a plurality of contact openings 43, and is electrically connected to the body region 32, the plurality of source regions 33, and the plurality of contact regions 34. In other words, the source pad 47 is electrically connected to the column region 12 via the body region 32.
  • FIG. 49 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment.
  • the multiple gate structures 35 according to the first embodiment described above were arranged shifted from the column region 12 (multiple second regions 15) toward the multiple second drift regions 17.
  • the multiple gate structures 35 according to the second embodiment are arranged so as to overlap the multiple second regions 15 in the stacking direction.
  • the multiple gate structures 35 overlap the multiple second regions 15 in a one-to-one correspondence in the stacking direction.
  • the multiple gate structures 35 each have a bottom wall connected to a corresponding second region 15. Specifically, the multiple gate structures 35 are formed wider than the corresponding second region 15, and each have a bottom wall connected to the corresponding second region 15 and a side wall connected to the corresponding second drift region 17.
  • the buried electrodes 77 face the corresponding second regions 15 across the insulating film 76 in the stacking direction, and face the corresponding second drift regions 17 across the insulating film 76 in the horizontal direction.
  • the aforementioned multiple source regions 33 and multiple contact regions 34 each face the corresponding second drift regions 17 across a portion of the body region 32 in the stacking direction.
  • FIG. 50 is a cross-sectional perspective view showing a gate structure 35 according to a third embodiment.
  • the multiple gate structures 35 according to the third embodiment each have a layout that does not require consideration of misalignment with respect to the multiple second regions 15.
  • the multiple gate structures 35 may face the multiple first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may face the multiple first regions 14 in the stacking direction. The multiple gate structures 35 may face the multiple first drift regions 16 in a one-to-one correspondence in the stacking direction.
  • each gate structure 35 may face multiple first drift regions 16 in the stacking direction.
  • the multiple gate structures 35 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.
  • the arrangement direction and extension direction of the multiple gate structures 35 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the arrangement direction of the multiple gate structures 35 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2.
  • the extension direction of the multiple gate structures 35 may be a direction other than the first extension direction De1 and the second extension direction De2.
  • the multiple gate structures 35 may intersect both the multiple first regions 14 and the multiple second regions 15 in a planar view.
  • the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°.
  • the angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the buried electrode 77 faces the second regions 15 and the second drift regions 17 across the insulating film 76 in the stacking direction and horizontal direction.
  • the source regions 33 and contact regions 34 described above face the second regions 15 and the second drift regions 17 across a portion of the body region 32 in the stacking direction.
  • FIG. 51 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment.
  • the multiple gate structures 35 according to the fourth embodiment each have a configuration that contributes to narrowing the pitch.
  • the multiple gate structures 35 according to the fourth embodiment are particularly effective in realizing a narrower pitch in the column region 12 (multiple second regions 15).
  • FIG. 51 shows an example in which the gate structure 35 according to the first embodiment described above is replaced with the gate structure 35 according to the fourth embodiment, but the configuration of the gate structure 35 according to the fourth embodiment is also applicable to the configurations of the gate structures 35 according to the second and third embodiments.
  • the multiple gate structures 35 each include a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80.
  • the trench 75 has a form similar to that of the first embodiment.
  • the insulating film 76 is formed at a distance from the first main surface 3 (active surface 71) to the bottom wall side of the trench 75, exposing a surface portion of the first main surface 3 (active surface 71) at the opening end of the trench 75. It is preferable that the upper end of the insulating film 76 is located on the first main surface 3 side relative to the intermediate depth range of the trench 75.
  • the buried electrode 77 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the opening end of the trench 75.
  • the buried electrode 77 exposes the surface portion of the first main surface 3 (active surface 71) and the upper end of the insulating film 76 at the opening end of the trench 75. It is preferable that the upper end of the buried electrode 77 is located on the first main surface 3 side relative to the middle part of the depth range of the trench 75.
  • the upper end of the buried insulator 80 is preferably located on the first main surface 3 side relative to the intermediate portion of the depth range of the trench 75.
  • the buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the buried insulator 80 preferably includes a silicon oxide film.
  • the aforementioned multiple source regions 33 are each formed in a region between multiple adjacent gate structures 35 in the surface layer portion of the first main surface 3 (active surface 71).
  • the multiple source regions 33 are arranged at intervals along the multiple gate structures 35 so as to be connected to the multiple gate structures 35 located on both sides.
  • the multiple source regions 33 arranged along one sidewall of the gate structure 35 face the multiple source regions 33 arranged along the other sidewall of the gate structure 35 in a one-to-one correspondence.
  • the multiple source regions 33 are arranged in a matrix in a planar view.
  • the multiple contact regions 34 on one side may face the regions between the multiple source regions 33 on the other side (i.e., the multiple source regions 33) in a one-to-one correspondence.
  • the multiple contact regions 34 may be arranged in a staggered pattern in a planar view.
  • the multiple contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 between them.
  • the first insulating film 41 covers the peripheral portion of the active surface 71 and exposes the multiple gate structures 35 collectively in the inner portion of the active surface 71. Specifically, the first insulating film 41 is connected to the insulating film 76 at both ends of the multiple gate structures 35, exposing the buried electrodes 77. The first insulating film 41 also covers the outer peripheral surface 72 and the first to fourth connection surfaces 73A to 73D in the same manner as in the first embodiment.
  • the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D across the first insulating film 41.
  • the second insulating film 42 covers the peripheral portion of the active surface 71, exposing the multiple gate structures 35 collectively at the inner portion of the active surface 71.
  • the second insulating film 42 penetrates into the trench 75 from above the first main surface 3 (active surface 71) at both ends of the multiple gate structures 35, and is connected to the buried insulator 80 within the trench 75.
  • the aforementioned gate pad 45, the aforementioned multiple gate wirings 46, and the aforementioned drain pad 48 have the same configuration as in the first embodiment.
  • the aforementioned source pad 47 penetrates into the single contact opening 43 from above the interlayer insulating film 40, and collectively covers the inner parts (buried insulator 80) of the multiple gate structures 35, the multiple source regions 33, and the multiple contact regions 34 within the single contact opening 43.
  • the source pad 47 is electrically insulated from the multiple gate structures 35 (buried electrodes 77) by the buried insulator 80, and is electrically connected to the multiple source regions 33 and multiple contact regions 34 at the first main surface 3 (active surface 71).
  • the source pad 47 has a buried portion buried in the trench 75. The buried portion of the source pad 47 faces the buried electrode 77 within the trench 75 with the buried insulator 80 in between, and is electrically connected to the multiple source regions 33 and multiple contact regions 34 at the opening end of the trench 75.
  • the multiple gate structures 35 each include a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80.
  • the trench 75 has a similar configuration to that of the first embodiment.
  • the insulating film 76 includes an upper insulating film 81 and a lower insulating film 82.
  • the upper insulating film 81 may include a silicon oxide film. It is preferable that the upper insulating film 81 includes a silicon oxide film made of an oxide of the chip 2.
  • the upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value that belongs to any one of the following ranges: 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the lower insulating film 82 covers the wall surface on the bottom wall side of the trench 75 relative to the bottom of the body region 32.
  • the lower insulating film 82 covers the second drift region 17.
  • the coverage area of the lower insulating film 82 relative to the second drift region 17 is larger than the coverage area of the upper insulating film 81 relative to the body region 32.
  • the lower insulating film 82 may include a silicon oxide film.
  • the lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.
  • the lower insulating film 82 has a thickness greater than that of the upper insulating film 81.
  • the thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.
  • the lower insulating film 82 may have a thickness of 100 nm or more and 500 nm or less.
  • the thickness of the lower insulating film 82 may have a value that belongs to any one of the following ranges: 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less, and 450 nm or more and 500 nm or less.
  • the aforementioned multiple source regions 33 have portions exposed from the sidewall of trench 75 at the opening end of trench 75, and face upper electrode 83 and buried insulator 80 across upper insulating film 81.
  • the aforementioned multiple contact regions 34 have portions exposed from the sidewall of trench 75 at the opening end of trench 75, and face upper electrode 83 and buried insulator 80 across upper insulating film 81.
  • the interlayer insulating film 90 has a contact opening 91 that exposes the active region 10.
  • the contact opening 91 has an opening wall surface positioned above the innermost field region 38, exposing the entire active region 10 and the inner edge of the innermost field region 38.
  • the width of the surface region 95 may be greater than the width of the multiple first regions 14, and the pitch of the surface region 95 may be less than the pitch of the multiple first regions 14.
  • the width of the surface region 95 may be greater than the width of the multiple first regions 14, and the pitch of the surface region 95 may be greater than the pitch of the multiple first regions 14.
  • the width of the multiple surface regions 95 may be approximately equal to the width of the multiple first regions 14.
  • the pitch of the multiple surface regions 95 may be approximately equal to the pitch of the multiple first regions 14.
  • the multiple surface regions 95 are arranged at intervals in the first arrangement direction Da1 of the first region 14 and extend in the first extension direction De1 of the first region 14.
  • the first arrangement direction Da1 is the m-axis direction
  • the first extension direction De1 is the a-axis direction.
  • the arrangement direction and extension direction of the multiple surface regions 95 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the a-axis direction, and the first extension direction De1 may be the m-axis direction.
  • the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction
  • the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 each contain a SiC single crystal.
  • at least one or all of the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • a wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon.
  • Examples of single crystals of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga 2 O 3 ).
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 may be made of the same type of single crystal or different types of single crystals.
  • the aforementioned channeling injection process (the process of injecting impurities into regions with sparse atomic rows) can also be applied to single crystals that form a cubic crystal.
  • the single crystal of the wide band gap semiconductor may be a cubic crystal or a hexagonal crystal.
  • these axial channels are formed by regions surrounded by atomic rows that are aligned along the low-index crystal axes of the cubic crystal axes.
  • the low-index crystal axis of a cubic crystal is a crystal axis in which the absolute values of "h", "k” and “l” in the Miller indices (h, k, l) are all 2 or less (preferably 1 or less).
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26 and the top layer 30 may contain single crystal silicon.
  • an n-type base layer 6 is shown.
  • a p-type base layer 6 may be adopted.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.
  • a semiconductor device (1A, 1B, 1C) including a first layer (8) of a first conductivity type (n type) including a semiconductor single crystal and having a first axial channel (CH1) along the stacking direction, a second layer (9) of a first conductivity type (n type) including a semiconductor single crystal and having a second axial channel (CH2) along the stacking direction and stacked on the first layer (8), a first region (14) of a second conductivity type (p type) extending along the first axial channel (CH1) in the first layer (8) in a cross-sectional view and extending in a first extension direction (De1) in a planar view, and a second region (15) of a second conductivity type (p type) extending along the second axial channel (CH2) in the second layer (9) in a cross-sectional view and extending in a second extension direction (De2) intersecting the first extension direction (De1) so as to intersect the first region (14) in a planar view.
  • p-type second conductivity type

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Bipolar Transistors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
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JP2020150182A (ja) * 2019-03-14 2020-09-17 富士電機株式会社 超接合炭化珪素半導体装置および超接合炭化珪素半導体装置の製造方法
JP2022090527A (ja) * 2020-12-07 2022-06-17 株式会社デンソー 電界効果トランジスタの製造方法
WO2022163082A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

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