WO2024143380A1 - ＳｉＣ半導体装置 - Google Patents

ＳｉＣ半導体装置 Download PDF

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Publication number
WO2024143380A1
WO2024143380A1 PCT/JP2023/046701 JP2023046701W WO2024143380A1 WO 2024143380 A1 WO2024143380 A1 WO 2024143380A1 JP 2023046701 W JP2023046701 W JP 2023046701W WO 2024143380 A1 WO2024143380 A1 WO 2024143380A1
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region
layer
regions
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thickness
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PCT/JP2023/046701
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English (en)
French (fr)
Japanese (ja)
Inventor
誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to EP23912158.5A priority Critical patent/EP4645392A1/en
Priority to JP2024567871A priority patent/JPWO2024143380A1/ja
Priority to DE112023004902.5T priority patent/DE112023004902T5/de
Priority to CN202380089479.8A priority patent/CN120457786A/zh
Publication of WO2024143380A1 publication Critical patent/WO2024143380A1/ja
Priority to US19/251,831 priority patent/US20250338546A1/en
Anticipated expiration legal-status Critical
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Definitions

  • Patent document 1 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.
  • the present disclosure provides a novel SiC semiconductor device.
  • the present disclosure provides a SiC semiconductor device including a first conductivity type SiC layer having a main surface, an active region set in an inner portion of the main surface, an outer peripheral region set in a peripheral portion of the main surface, and a second conductivity type column region formed in the SiC layer at intervals in the horizontal direction along the main surface and including a plurality of impurity regions located in both the active region and the outer peripheral region.
  • the present disclosure provides a semiconductor device including a first conductivity type semiconductor layer including a main surface and having an axial channel along a thickness direction, an impurity region of a second conductivity type extending along the axial channel within the semiconductor layer, a body region of the second conductivity type formed in a region on the main surface side of the impurity region, a trench penetrating the body region in the main surface, a buried electrode disposed closer to the bottom wall of the trench than the main surface, and a gate structure having a buried insulator disposed closer to the bottom wall of the trench than the main surface and covering the buried electrode.
  • FIG. 1 is a plan view showing a SiC semiconductor device according to the first embodiment.
  • FIG. 2A is a cross-sectional view taken along line IIA-IIA shown in FIG.
  • FIG. 2B is a cross-sectional view taken along line IIB-IIB shown in FIG.
  • FIG. 3A is a plan view showing an example of the layout of a chip (first layer).
  • FIG. 3B is a plan view showing an example of the layout of the chip (second layer).
  • FIG. 4A is a perspective view showing a chip together with a decorative pattern according to the first embodiment.
  • FIG. 4B is a perspective view showing a chip together with a decorative pattern according to the first embodiment.
  • FIG. 5 is a perspective view of a main part showing a decorative pattern.
  • FIG. 19 is a cross-sectional perspective view showing a column region according to the third embodiment.
  • FIG. 20 is a graph showing an example of the concentration gradient in the column region shown in FIG.
  • FIG. 21 is a cross-sectional perspective view showing a column region according to the fourth embodiment.
  • FIG. 22 is a graph showing an example of the concentration gradient in the column region shown in FIG.
  • FIG. 23 is a cross-sectional perspective view showing a column region according to the fifth embodiment.
  • FIG. 24 is a graph showing an example of the concentration gradient in the column region shown in FIG.
  • FIG. 25 is a cross-sectional perspective view showing a column region according to the sixth embodiment.
  • FIG. 26 is a graph showing an example of the concentration gradient in the column region shown in FIG. FIG.
  • the second side 5B is connected to the first side 5A
  • the third side 5C is connected to the second side 5B
  • the fourth side 5D is connected to the first side 5A and the third side 5C.
  • the first side 5A and the third side 5C extend in a first direction X along the first main surface 3 and face a second direction Y that intersects (specifically, is perpendicular to) the first direction X.
  • the second side 5B and the fourth side 5D extend in the second direction Y and face the first direction X.
  • the a-plane is a crystal plane perpendicular to the a-axis direction
  • the m-plane is a crystal plane perpendicular to the m-axis direction.
  • the first direction X may be the m-axis direction of the SiC single crystal
  • the second direction Y may be the a-axis direction of the SiC single crystal.
  • the first to fourth side surfaces 5A to 5D may each be a ground surface.
  • the first to fourth side surfaces 5A to 5D may each be a cleavage surface.
  • the base layer 6 has a base thickness TB.
  • the base thickness TB may be 5 ⁇ m or more and 300 ⁇ m or less.
  • the base thickness TB may have a value belonging to any one of the following ranges: 5 ⁇ m or more and 50 ⁇ m or less, 50 ⁇ m or more and 100 ⁇ m or less, 100 ⁇ m or more and 150 ⁇ m or less, 150 ⁇ m or more and 200 ⁇ m or less, 200 ⁇ m or more and 250 ⁇ m or less, and 250 ⁇ m or more and 300 ⁇ m or less.
  • the base thickness TB is preferably 50 ⁇ m or more and 250 ⁇ m or less.
  • the first axis channel CH1 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the first axis channel CH1 extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the first axis channel CH1 is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the first layer 8 has an n-type impurity concentration adjusted by at least one pentavalent element.
  • the n-type impurity concentration of the first layer 8 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the first layer 8 contains a pentavalent element other than phosphorus.
  • the n-type impurity concentration of the first layer 8 is preferably adjusted with at least nitrogen.
  • the first layer 8 preferably contains nitrogen and a pentavalent element other than nitrogen.
  • the first layer 8 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.
  • the first layer 8 has a first thickness T1.
  • the first thickness T1 is preferably less than the base thickness TB.
  • the first thickness T1 is preferably 1 ⁇ m or more.
  • the first thickness T1 is preferably 5 ⁇ m or less.
  • the first thickness T1 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the second layer 9 is laminated on the first layer 8.
  • the second layer 9 extends horizontally in a layered manner, forming the first main surface 3 and forming part of the first to fourth side surfaces 5A to 5D.
  • the second layer 9 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the first layer 8.
  • the second layer 9 has a lower end and an upper end.
  • the lower end of the second layer 9 is the starting point of crystal growth, and the upper end of the second layer 9 is the end point of crystal growth. Since the second layer 9 is grown continuously from the first layer 8, the lower end of the second layer 9 coincides with the upper end of the first layer 8.
  • the boundary between the first layer 8 and the second layer 9 is not necessarily visible, and may be indirectly evaluated and/or determined from other configurations or elements.
  • the second layer 9 has an off-direction Doff and an off-angle ⁇ off that are approximately the same as the off-direction Doff and off-angle ⁇ off of the first layer 8.
  • the second layer 9 has a second axial channel CH2 that runs along the stacking direction.
  • the second axial channel CH2 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the second layer 9, and is surrounded by atomic rows that run along the crystal axis that extends in the stacking direction (crystal growth direction).
  • the second axis channel CH2 is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a planar view. It is preferable that the second axis channel CH2 is a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • the second axis channel CH2 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the second axis channel CH2 extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the second axis channel CH2 is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the n-type impurity concentration of the second layer 9 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the second layer 9 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the second layer 9 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the second layer 9 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the n-type impurity concentration of the second layer 9 is preferably approximately equal to the n-type impurity concentration of the first layer 8.
  • the n-type impurity concentration of the second layer 9 may be different from the n-type impurity concentration of the first layer 8.
  • the n-type impurity concentration (peak value) of the second layer 9 may be higher than the n-type impurity concentration (peak value) of the first layer 8, or may be lower than the n-type impurity concentration (peak value) of the first layer 8.
  • the second layer 9 has an n-type impurity concentration adjusted by at least one pentavalent element.
  • the n-type impurity concentration of the second layer 9 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the second layer 9 contains a pentavalent element other than phosphorus.
  • the second layer 9 has a second thickness T2.
  • the second thickness T2 is preferably less than the base thickness TB.
  • the second thickness T2 may be approximately equal to the first thickness T1 or may be different from the first thickness T1.
  • the second thickness T2 may be greater than the first thickness T1 or may be less than the first thickness T1.
  • the SiC semiconductor device 1A includes an active region 10 set in the chip 2.
  • the active region 10 is set in the inner part of the chip 2 at a distance from the periphery of the chip 2 (first to fourth side faces 5A to 5D) in a plan view.
  • the active region 10 is set in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view.
  • the planar area of the active region 10 is preferably 50% to 90% of the planar area of the first main surface 3.
  • the SiC semiconductor device 1A includes a peripheral region 11 that is set outside the active region 10 in the chip 2.
  • the peripheral region 11 is provided in a region between the periphery of the chip 2 and the active region 10 in a planar view.
  • the peripheral region 11 extends in a band shape along the active region 10 in a planar view, and is set in a polygonal ring shape (a square ring in this embodiment) that surrounds the active region 10.
  • the SiC semiconductor device 1A includes a decorative pattern PT according to a first embodiment formed on at least one of the first to fourth side surfaces 5A to 5D.
  • the decorative pattern PT makes it easier to identify or estimate the internal configuration of the device from the external appearance of the chip 2, and to distinguish between the product and another product, thereby improving the convenience of the SiC semiconductor device 1A.
  • the decorative pattern PT may be identified by non-destructive testing (visual inspection) of the chip 2.
  • the decorative pattern PT includes at least one (in this embodiment, multiple) first mark Mk1 and at least one (in this embodiment, multiple) second mark Mk2.
  • the decorative pattern PT does not necessarily have to include both the first mark Mk1 and the second mark Mk2 at the same time, and may consist of only one of the first mark Mk1 and the second mark Mk2.
  • each of the multiple first marks Mk1 is made of a p-type impurity region exposed from the first side surface 5A.
  • the multiple first marks Mk1 are each formed in a portion of the first side surface 5A that is made of the laminated portion 7. Specifically, the multiple first marks Mk1 are formed in a region on the laminated portion 7 side of the base layer 6, exposing the base layer 6 from the first side surface 5A.
  • the multiple first marks Mk1 are formed on the first side 5A so as to be biased toward a lower range on the lower side of the laminated portion 7 in the thickness direction relative to an upper range on the upper side of the laminated portion 7 in the thickness direction. If the upper range is defined as the first thickness range, the lower range is defined as the second thickness range. If the lower range is defined as the first thickness range, the upper range is defined as the second thickness range. The upper range is the portion of the first to fourth sides 5A to 5D consisting of the second layer 9, and the lower range is the portion of the first to fourth sides 5A to 5D consisting of the first layer 8.
  • the multiple first marks Mk1 are arranged at intervals in the first direction X in the lower range, and define multiple n-type first spaces Sp1, each consisting of a part of the laminate 7.
  • the multiple first marks Mk1 are each formed in a portion of the first side 5A consisting of the first layer 8, and the multiple first spaces Sp1 each consist of a part of the first layer 8.
  • the multiple first marks Mk1 form pn junctions with the multiple first spaces Sp1.
  • SEM Sccanning Electron Microscope
  • TEM Transmission Electron Microscope
  • EBIC Electro Beam Induced Current
  • the multiple first marks Mk1 are formed in an area on the first layer 8 (lower range) side relative to the second layer 9 (upper range). Therefore, the multiple first marks Mk1 expose a portion made of the second layer 9 on the first side surface 5A, and face the first main surface 3 across the second layer 9. The multiple first marks Mk1 expose the entire area of the portion made of the second layer 9 on the first side surface 5A. In other words, the multiple first marks Mk1 are not formed on the second layer 9. On the other hand, the multiple first spaces Sp1 are connected to the portion made of the second layer 9 on the first side surface 5A.
  • the first marks Mk1 each extend in a vertically elongated columnar shape along the stacking direction, and together with the first spaces Sp1 on the first side surface 5A, form a stripe mark extending in the stacking direction.
  • the first marks Mk1 extend along the first axial channel CH1 on the surface layer of the first side surface 5A.
  • the multiple first marks Mk1 each have a lower end on the lower end side of the first layer 8 and an upper end on the upper end side of the first layer 8.
  • the lower ends of the multiple first marks Mk1 are located in a region on the lower end side of the first layer 8 relative to the intermediate part of the thickness range of the first layer 8
  • the upper ends of the multiple first marks Mk1 are located in a region on the upper end side of the first layer 8 relative to the intermediate part of the thickness range of the first layer 8.
  • the multiple first marks Mk1 each consist of a single impurity region having a thickness (depth) that crosses the intermediate part of the first layer 8 along the thickness direction.
  • the lower ends of the multiple first marks Mk1 may be formed at intervals from the lower end to the upper end of the first layer 8, and may face the base layer 6 across a portion (lower end) of the first layer 8. In other words, the multiple first marks Mk1 may expose the entire area of the portion of the first side 5A that is made of the base layer 6. The lower ends of the multiple first marks Mk1 may be approximately coincident with the lower end of the first layer 8 and connected to the base layer 6.
  • the lower ends of the multiple first marks Mk1 may have extensions that cross the boundary between the base layer 6 and the first layer 8 and are located within the base layer 6.
  • the extensions of the multiple first marks Mk1 are located on the surface layer portion on the upper end side of the base layer 6, exposing almost the entire area of the portion consisting of the base layer 6 on the first side surface 5A. It is preferable that the extensions of the multiple first marks Mk1 are formed on the laminate portion 7 side rather than the middle part of the thickness range of the base layer 6.
  • the upper end of the first mark Mk1 may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a part (upper end) of the first layer 8.
  • the upper end of the first mark Mk1 may be approximately coincident with the upper end of the first layer 8 and connected to the second layer 9.
  • the second marks Mk2 are formed on at least one side of the first to fourth sides 5A to 5D that is different from the first marks Mk1.
  • the second marks Mk2 are formed on either or both (both in this embodiment) of the second side 5B and the fourth side 5D that extend in the second direction Y.
  • the configuration on the fourth side 5D side is similar to the configuration on the second side 5B side, so the configuration on the second side 5B side will be described below.
  • the configuration on the fourth side 5D side can be obtained by replacing "second side 5B" with "fourth side 5D" in the following description.
  • the multiple second marks Mk2 each consist of a p-type impurity region exposed from the second side surface 5B.
  • the multiple second marks Mk2 are each formed in a portion of the second side surface 5B that consists of the laminated portion 7. Specifically, the multiple second marks Mk2 are formed in a region on the laminated portion 7 side of the base layer 6, exposing the base layer 6 from the second side surface 5B.
  • the multiple second marks Mk2 are formed on the second side surface 5B so as to be biased toward the upper range relative to the lower range.
  • the multiple second marks Mk2 are arranged at intervals in the second direction Y in the upper range, and define multiple n-type second spaces Sp2 each consisting of a part of the laminate 7.
  • the multiple second marks Mk2 are each formed in a portion of the second layer 9 on the second side surface 5B, and the multiple second spaces Sp2 each consist of a part of the second layer 9.
  • the multiple second marks Mk2 form a pn junction with the multiple second spaces Sp2.
  • the second marks Mk2 are formed in a thickness range different from the thickness range of the first marks Mk1 and in an arrangement direction different from the arrangement direction of the first marks Mk1.
  • the second spaces Sp2 are formed in a thickness range different from the thickness range of the first spaces Sp1 and in an arrangement direction different from the arrangement direction of the first spaces Sp1.
  • the multiple second marks Mk2 are formed in an area on the second layer 9 (upper range) side relative to the first layer 8 (lower range) and face the base layer 6 across the first layer 8.
  • the multiple second marks Mk2 expose the portion of the first layer 8 on the second side 5B.
  • the multiple second spaces Sp2 are each connected to the portion of the first layer 8 on the second side 5B.
  • the second marks Mk2 each extend in a vertically elongated columnar shape along the stacking direction, and together with the second spaces Sp2 on the second side surface 5B, form a stripe mark extending in the stacking direction.
  • the second marks Mk2 extend to the second axial channel CH2 on the surface portion of the second side surface 5B.
  • the second marks Mk2 each have a lower end on the lower end side of the second layer 9 and an upper end on the upper end side of the second layer 9.
  • the lower ends of the second marks Mk2 are located in a region on the lower end side of the second layer 9 relative to the intermediate part of the thickness range of the second layer 9, and the upper ends of the second marks Mk2 are located in a region on the upper end side of the second layer 9 relative to the intermediate part of the thickness range of the second layer 9.
  • the second marks Mk2 each consist of a single impurity region having a thickness (depth) that crosses the intermediate part of the second layer 9 along the thickness direction.
  • the lower end of the second mark Mk2 may be formed at a distance from the lower end to the upper end of the second layer 9, facing the first layer 8 across a portion (lower end) of the second layer 9.
  • the multiple second marks Mk2 may expose the entire area of the portion made of the first layer 8 on the second side surface 5B.
  • the lower end of the second mark Mk2 may be approximately coincident with the lower end of the first layer 8 and connected to the first layer 8.
  • the lower end of the second mark Mk2 may have an extension that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.
  • the extensions of the multiple second marks Mk2 are located on the surface layer portion on the upper end side of the first layer 8, and expose almost the entire area of the portion consisting of the first layer 8 on the second side surface 5B.
  • the upper end of the second mark Mk2 may be formed at a distance from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the second layer 9 across a part (upper end) of the second layer 9.
  • the upper end of the second mark Mk2 may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).
  • the SiC semiconductor device 1A may include a decorative pattern PT according to a second embodiment formed on at least one of the first to fourth side surfaces 5A to 5D.
  • the decorative pattern PT according to the second embodiment includes a first difference mark Md1 in addition to the configuration according to the first embodiment.
  • the first different mark Md1 is formed on either or both of the first side surface 5A and the third side surface 5C in a thickness range different from that of the first mark Mk1 and in a layout different from that of the first mark Mk1.
  • FIG. 6A shows an example in which the first different mark Md1 is formed on the first side surface 5A.
  • the configuration on the third side surface 5C side can be obtained by replacing "first side surface 5A" with "third side surface 5C" in the following explanation.
  • the first difference mark Md1 is made of a p-type impurity region exposed from the first side surface 5A.
  • the first difference mark Md1 is formed in a portion of the first side surface 5A that is made of the laminated portion 7. Specifically, the first difference mark Md1 is formed in a region on the laminated portion 7 side of the base layer 6, exposing the base layer 6 from the first side surface 5A.
  • the first difference mark Md1 is formed in an upper range relative to a lower range, and overlaps at least one first mark Mk1 in the thickness direction.
  • the first difference mark Md1 extends in a band shape in the upper range in the first direction X, and overlaps multiple first marks Mk1 in the thickness direction.
  • the first difference mark Md1 extends from a corner on one side of the first side 5A to a corner on the other side of the first side 5A in the first direction X, and is exposed from the corner on one side and the corner on the other side of the first side 5A. In other words, the first difference mark Md1 overlaps all of the first marks Mk1 in the thickness direction.
  • the first difference mark Md1 has a portion exposed from a corner of the second side surface 5B and a corner of the fourth side surface 5D.
  • the first difference mark Md1 is formed at a corner of the second side surface 5B (fourth side surface 5D) at a distance in the second direction Y from the outermost second mark Mk2, and faces the outermost second mark Mk2 in the second direction Y.
  • the first difference mark Md1 is formed in a portion of the first side surface 5A made of the second layer 9, and defines a plurality of first spaces Sp1 together with the plurality of first marks Mk1.
  • the first difference mark Md1 has a lower end on the lower end side of the second layer 9 and an upper end on the upper end side of the second layer 9.
  • the lower end of the first difference mark Md1 is located in a region on the lower end side of the second layer 9 with respect to the intermediate part of the thickness range of the second layer 9, and the upper end of the first difference mark Md1 is located in a region on the upper end side of the second layer 9 with respect to the intermediate part of the thickness range of the second layer 9.
  • the first difference mark Md1 consists of a single impurity region having a thickness (depth) that crosses the intermediate part of the second layer 9 along the thickness direction.
  • the lower end of the first difference mark Md1 may be formed at a distance from the multiple first marks Mk1 toward the upper end (first main surface 3) of the second layer 9, and may face the multiple first marks Mk1 (multiple first spaces Sp1) across a part (lower end) of the second layer 9.
  • the lower end of the first difference mark Md1 may be approximately coincident with the lower end of the first layer 8.
  • the lower end of the first difference mark Md1 may be formed at a distance from the upper ends of the first marks Mk1 toward the upper end of the second layer 9, and may face the first marks Mk1 across a portion (lower end) of the second layer 9.
  • the lower ends of the first difference marks Md1 may be connected to the upper ends of the first marks Mk1 (first spaces Sp1).
  • the lower end of the first difference mark Md1 may have an extension that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.
  • the lower end (extension) of the first difference mark Md1 may be connected to multiple first marks Mk1 within the first layer 8.
  • the lower end (extension) of the first difference mark Md1 may be formed at a distance from the multiple first marks Mk1 toward the upper end of the second layer 9.
  • the upper end of the first difference mark Md1 may be formed at a distance from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the second layer 9 across a portion (upper end) of the second layer 9.
  • the upper end of the first difference mark Md1 may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).
  • the SiC semiconductor device 1A may include a decorative pattern PT according to a third embodiment formed on at least one of the first to fourth side surfaces 5A to 5D.
  • the decorative pattern PT according to the third embodiment includes a second difference mark Md2 in addition to the configuration according to the first embodiment.
  • the second different mark Md2 is formed on either or both of the second side surface 5B and the fourth side surface 5D in a thickness range different from that of the second mark Mk2 and in a layout different from that of the second mark Mk2.
  • FIG. 6B shows an example in which the second different mark Md2 is formed on the second side surface 5B.
  • the configuration on the fourth side surface 5D side can be obtained by replacing "second side surface 5B" with "fourth side surface 5D" in the following explanation.
  • the second difference mark Md2 is made of a p-type impurity region exposed from the second side surface 5B.
  • the second difference mark Md2 is formed in a portion of the second side surface 5B that is made of the laminated portion 7. Specifically, the second difference mark Md2 is formed in a region on the laminated portion 7 side of the base layer 6, exposing the base layer 6 from the second side surface 5B.
  • the second difference mark Md2 is formed in a lower range relative to the upper range, and overlaps at least one second mark Mk2 in the thickness direction.
  • the second difference mark Md2 extends in a band shape in the lower range in the second direction Y, and overlaps multiple second marks Mk2 in the thickness direction.
  • the second difference mark Md2 extends from a corner on one side of the second side 5B to a corner on the other side of the second side 5B in the second direction Y, and is exposed from the corner on one side and the corner on the other side of the second side 5B. In other words, the second difference mark Md2 overlaps all of the second marks Mk2 in the thickness direction.
  • the second difference mark Md2 has a portion exposed from a corner of the first side surface 5A and a corner of the third side surface 5C.
  • the second difference mark Md2 is formed at a corner of the first side surface 5A (third side surface 5C) at a distance in the first direction X from the outermost first mark Mk1, and faces the outermost first mark Mk1 in the first direction X.
  • the second difference mark Md2 is formed in a portion of the second side surface 5B made of the first layer 8, and defines a plurality of second spaces Sp2 together with the plurality of second marks Mk2.
  • the second difference mark Md2 has a lower end on the lower end side of the first layer 8 and an upper end on the upper end side of the first layer 8.
  • the lower end of the second difference mark Md2 is located in a region on the lower end side of the first layer 8 with respect to the intermediate part of the thickness range of the first layer 8
  • the upper end of the second difference mark Md2 is located in a region on the upper end side of the first layer 8 with respect to the intermediate part of the thickness range of the first layer 8.
  • the second difference mark Md2 consists of a single impurity region having a thickness (depth) that crosses the intermediate part of the first layer 8 along the first axial channel CH1.
  • the lower end of the second difference mark Md2 may be formed at a distance from the lower end of the first layer 8 (i.e., base layer 6) toward the upper end (second layer 9) of the first layer 8, and may face the base layer 6 across a part (lower end) of the first layer 8.
  • the lower end of the second difference mark Md2 may be approximately coincident with the lower end of the first layer 8 and connected to the base layer 6.
  • the lower end of the second difference mark Md2 may have an extension that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.
  • the upper end of the second difference mark Md2 may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face multiple second marks Mk2 across a portion (upper end) of the first layer 8.
  • the upper end of the second difference mark Md2 may be exposed from the upper end of the first layer 8 (i.e., the first main surface 3).
  • the upper end of the second difference mark Md2 may be connected to the lower ends of the second marks Mk2.
  • the upper end of the second difference mark Md2 may be formed at a distance from the lower ends of the second marks Mk2 toward the lower end of the first layer 8, and may face the second marks Mk2 across a part (lower end) of the first layer 8.
  • the SiC semiconductor device 1A may include a decorative pattern PT according to a fourth embodiment formed on at least one of the first to fourth side surfaces 5A to 5D.
  • the decorative pattern PT according to the fourth embodiment includes the first difference mark Md1 according to the second embodiment and the second difference mark Md2 according to the third embodiment in addition to the configuration according to the first embodiment.
  • the second difference mark Md2 extends in a thickness range different from the thickness range of the first difference mark Md1 and in an extension direction different from the extension direction of the first difference mark Md1.
  • the SiC semiconductor device 1A may include a decorative pattern PT according to a fifth embodiment formed on at least one of the first to fourth side surfaces 5A to 5D.
  • the decorative pattern PT according to the fifth embodiment has a configuration in which the positional relationship between the multiple first marks Mk1 and the multiple second marks Mk2 is swapped.
  • the multiple first marks Mk1 are arranged at intervals in the second direction Y in the lower range of the second side surface 5B, and define multiple n-type first spaces Sp1 each consisting of a part of the laminated portion 7.
  • the multiple first marks Mk1 are each formed in a portion of the second side surface 5B consisting of the first layer 8, and the multiple first spaces Sp1 each consist of a part of the first layer 8.
  • the configuration of the first mark Mk1 (first space Sp1) in the fifth embodiment is similar to the configuration of the first mark Mk1 (first space Sp1) in the first embodiment, except that it is formed on the second side surface 5B.
  • the multiple second marks Mk2 are arranged at intervals in the first direction X in the upper range of the first side surface 5A, and define multiple n-type second spaces Sp2 each consisting of a part of the laminated portion 7.
  • the multiple second marks Mk2 are each formed in a portion of the first side surface 5A consisting of the second layer 9, and the multiple second spaces Sp2 each consist of a part of the second layer 9.
  • the configuration of the second mark Mk2 (second spaces Sp2) in the fifth embodiment is similar to the configuration of the second mark Mk2 (second spaces Sp2) in the first embodiment, except that it is formed on the first side surface 5A.
  • the configuration of the decorative pattern PT according to the second to fourth embodiments can also be applied to the decorative pattern PT according to the fifth embodiment.
  • the first difference mark Md1 is formed in the upper area of the second side surface 5B.
  • the second difference mark Md2 is formed in the lower area of the first side surface 5.
  • the SiC semiconductor device 1A includes a p-type column region 12 formed in the stacked portion 7 at least in the active region 10.
  • the column region 12 may also be referred to as a "column layer,” a “pillar layer (region),” a “p-type layer (region),” a “p-type zone,” or the like.
  • the column region 12 is formed in a three-dimensional lattice shape within the stacked portion 7, and defines a three-dimensional lattice-shaped n-type drift region 13 made up of a part of the stacked portion 7.
  • the column region 12 is formed in at least one of the multiple semiconductor layers that make up the stacked portion 7, and forms a superjunction structure SJ with the drift region 13 within the stacked portion 7.
  • the column region 12 has a stacked structure that includes multiple p-type first regions 14 and multiple p-type second regions 15.
  • the first regions 14 are formed in the first layer 8 at intervals in the horizontal direction, and define a plurality of n-type first drift regions 16, each of which is made up of a part of the first layer 8.
  • the first regions 14, together with the first drift regions 16, form a plurality of first pn junctions having charge balance.
  • a state of charge balance means a state in which, for multiple adjacent first regions 14, the depletion layer extending from one first pn junction and the depletion layer extending from the other first pn junction are connected within the multiple first drift regions 16.
  • the multiple first regions 14 are arranged at intervals in the first array direction Da1 in the first layer 8, and are each formed in a strip shape extending in the first extension direction De1.
  • the first extension direction De1 is a direction that intersects or is perpendicular to the first array direction Da1.
  • the multiple first regions 14 are formed in a stripe shape extending in the first extension direction De1
  • the multiple first drift regions 16 are formed in a stripe shape extending in the first extension direction De1.
  • the multiple first regions 14 are extended from the active region 10 to the peripheral region 11 (see FIG. 3A). That is, the multiple first regions 14 are extended from a portion of the first layer 8 located within the active region 10 to a portion of the first layer 8 located within the peripheral region 11.
  • the multiple first regions 14 are also arranged at intervals in the first array direction Da1 in the peripheral region 11, and are each formed in a band shape extending in the first extension direction De1.
  • the multiple first regions 14 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each has a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).
  • the portions of the multiple first regions 14 exposed from the first side surface 5A form multiple first marks Mk1 on the first side surface 5A
  • the portions of the multiple first regions 14 exposed from the third side surface 5C form multiple first marks Mk1 on the third side surface 5C.
  • the multiple first regions 14 include either or both of the multiple first marks Mk1 as exposed portions exposed from the first side surface 5A and the multiple first marks Mk1 as exposed portions exposed from the third side surface 5C.
  • the multiple first marks Mk1 are each formed using a portion (exposed portion) of the multiple first regions 14.
  • the layout (exposed locations and arrangement direction) of the multiple first marks Mk1 on the first side 5A (third side 5C) is appropriately adjusted depending on the layout (first arrangement direction Da1 and first extension direction De1) of the multiple first regions 14.
  • the multiple first marks Mk1 do not necessarily need to be formed continuously from the main body portions of the multiple first regions 14, but may be formed as separate portions separated from the main body portions of the multiple first regions 14. In this case, it is preferable that the multiple first marks Mk1 are separated from the main body portions of the multiple first regions 14 in the outer circumferential region 11.
  • the explanation for the first region 14 also applies to the first mark Mk1 (the portion of the first region 14 exposed from the first side surface 5A/third side surface 5C).
  • the first regions 14 are made up of channeling regions (first channeling regions) that extend along the first axis channel CH1 in the first layer 8 in a cross-sectional view.
  • the first regions 14 are impurity regions that are introduced parallel or nearly parallel to the region (first axis channel CH1) surrounded by atomic rows along the low-index crystal axis in the first layer 8, and extend at an angle with respect to the first main surface 3.
  • the multiple first regions 14 have an off direction Doff and an off angle ⁇ off that are approximately the same as the off direction Doff and the off angle ⁇ off of the first axis channel CH1. In other words, the multiple first regions 14 are inclined by the off angle ⁇ off from the vertical axis toward the off direction Doff.
  • the distance between the lower end of the first layer 8 and the first lower end 14a may be 0 ⁇ m or more and 2 ⁇ m or less.
  • the distance between the lower end of the first layer 8 and the first lower end 14a may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the first lower end 14a may have an extension that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.
  • the thickness of the extension of the first lower end 14a based on the upper end of the base layer 6 may be greater than 0 ⁇ m and less than 2 ⁇ m.
  • the thickness of the extension of the first lower end 14a may have a value that belongs to any one of the following ranges: greater than 0 ⁇ m and less than 0.5 ⁇ m, 0.5 ⁇ m or more and less than 1 ⁇ m, 1 ⁇ m or more and less than 1.5 ⁇ m, and 1.5 ⁇ m or more and less than 2 ⁇ m.
  • the first upper end 14b may be formed at a distance from the upper end of the first layer 8 (i.e., the second layer 9) toward the lower end, and may face the upper end of the first layer 8 across a portion (upper end) of the first layer 8.
  • the first upper end 14b may be substantially coincident with the upper end of the first layer 8 and connected to the second layer 9.
  • the distance between the upper end of the first layer 8 and the first upper end 14b may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper end of the first layer 8 and the first upper end 14b may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the plurality of first regions 14 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the first region 14 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the first region 14 is adjusted by a trivalent element belonging to the heavy elements heavier than carbon. In other words, the first region 14 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the first region 14 is adjusted by aluminum.
  • the first regions 14 each have a first width W1.
  • the first width W1 is the width along the first arrangement direction Da1 of the first regions 14. It is preferable that the first width W1 is less than the first thickness T1 of the first layer 8. Of course, the first width W1 may be equal to or greater than the first thickness T1. It is preferable that the first width W1 is less than the second thickness T2 of the second layer 9. Of course, the first width W1 may be equal to or greater than the second thickness T2.
  • the first width W1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 may have a value belonging to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the multiple first regions 14 each have a first region thickness TR1 (first region depth).
  • the first region thickness TR1 may be less than the first thickness T1 of the first layer 8.
  • the first region thickness TR1 may be greater than the first thickness T1.
  • the first region thickness TR1 may be approximately equal to the first thickness T1.
  • the first region thickness TR1 may be less than the second thickness T2 of the second layer 9.
  • the first region thickness TR1 may be greater than the second thickness T2.
  • the first region thickness TR1 may be approximately equal to the second thickness T2.
  • the first region thickness TR1 is preferably 1 ⁇ m or more.
  • the first region thickness TR1 is preferably 5 ⁇ m or less.
  • the first region thickness TR1 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first width W1 is less than the first thickness T1 of the first layer 8, and that the first region thickness TR1 is greater than the first width W1.
  • each of the multiple first regions 14 has a first aspect ratio TR1/W1 that extends in a vertically elongated columnar shape along the first axial channel CH1.
  • the first aspect ratio TR1/W1 is the ratio of the first region thickness TR1 to the first width W1.
  • the first region thickness TR1 is greater than the first thickness T1.
  • the first aspect ratio TR1/W1 may be greater than 1 and less than or equal to 100.
  • the first regions 14 are formed at intervals of a first pitch P1 in the first arrangement direction Da1. It is preferable that the first pitch P1 is less than the first thickness T1 of the first layer 8. Of course, the first pitch P1 may be equal to or greater than the first thickness T1. It is preferable that the first pitch P1 is less than the second thickness T2 of the second layer 9. Of course, the first pitch P1 may be equal to or greater than the second thickness T2.
  • the first pitch P1 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch P1 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first pitch P1 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second regions 15 are formed in the second layer 9 at intervals in the horizontal direction, and define a plurality of n-type second drift regions 17, each of which is made up of a part of the second layer 9.
  • the second regions 15 and the second layer 9 form a second superjunction structure SJ2.
  • the charge balance state means that, for adjacent second regions 15, the depletion layer extending from one second pn junction and the depletion layer extending from the other second pn junction are connected within the second drift regions 17.
  • the second regions 15 are formed in the second layer 9 so as to overlap the first regions 14 in the stacking direction. Specifically, the second regions 15 are arranged at intervals in the second layer 9 in a second array direction Da2 different from the first array direction Da1, and are each formed in a band shape extending in a second extension direction De2 different from the first extension direction De1.
  • the second array direction Da2 is a direction that intersects with the first array direction Da1
  • the second extension direction De2 is a direction that intersects with the first extension direction De1.
  • the second extension direction De2 is a direction that intersects or is perpendicular to the second array direction Da2.
  • the multiple second regions 15 are formed in stripes extending in the second extension direction De2
  • the multiple second drift regions 17 are formed in stripes extending in the second extension direction De2.
  • the multiple second regions 15 intersect with the multiple first regions 14 in a planar view.
  • the multiple second drift regions 17 are connected in a lattice pattern to the multiple first drift regions 16 at the boundary between the first layer 8 and the second layer 9, and together with the multiple first drift regions 16 form a single three-dimensional lattice-shaped drift region 13.
  • the multiple second drift regions 17 form a three-dimensional lattice-shaped current path together with the multiple first drift regions 16.
  • the multiple second regions 15 are extended from the active region 10 to the peripheral region 11 (see FIG. 3B). That is, the multiple second regions 15 are extended from a portion of the second layer 9 located within the active region 10 to a portion of the second layer 9 located within the peripheral region 11.
  • the multiple second regions 15 are also arranged at intervals in the second array direction Da2 in the peripheral region 11, and are each formed in a strip shape extending in the second extension direction De2. That is, the multiple second regions 15 intersect with the multiple first regions 14 in the peripheral region 11 as well.
  • the multiple second regions 15 extend from the outer peripheral region 11 toward either or both of the second side surface 5B and the fourth side surface 5D (both in this embodiment), and each has a portion exposed from either or both of the second side surface 5B and the fourth side surface 5D (both in this embodiment).
  • the portions of the multiple second regions 15 exposed from the second side surface 5B form multiple second marks Mk2 on the second side surface 5B
  • the portions of the multiple second regions 15 exposed from the fourth side surface 5D form multiple second marks Mk2 on the fourth side surface 5D.
  • the multiple second regions 15 include either or both of the multiple second marks Mk2 as exposed portions exposed from the second side surface 5B and the multiple second marks Mk2 as exposed portions exposed from the fourth side surface 5D.
  • the multiple second marks Mk2 are each formed using a portion (exposed portion) of the multiple second regions 15.
  • the layout (exposed locations and arrangement direction) of the multiple second marks Mk2 on the second side 5B (fourth side 5D) is appropriately adjusted depending on the layout (second arrangement direction Da2 and second extension direction De2) of the multiple second regions 15.
  • the second marks Mk2 do not necessarily need to be formed continuously from the main body portions of the second regions 15, but may be formed as separate portions separated from the main body portions of the second regions 15. In this case, it is preferable that the second marks Mk2 are separated from the main body portions of the second regions 15 in the outer circumferential region 11.
  • the explanation for the second region 15 also applies to the second marks Mk2 (portions of the second region 15 exposed from the second side surface 5B/fourth side surface 5D).
  • the second regions 15 are made up of channeling regions (second channeling regions) that extend along the second axis channel CH2 in the second layer 9 in a cross-sectional view.
  • the second regions 15 are impurity regions that are introduced parallel or nearly parallel to the region (second axis channel CH2) surrounded by atomic rows along the low-index crystal axis in the second layer 9, and extend at an angle with respect to the first main surface 3.
  • the second regions 15 have an off direction Doff and an off angle ⁇ off that are approximately equal to the off direction Doff and the off angle ⁇ off of the second axis channel CH2. In other words, the second regions 15 are inclined by the off angle ⁇ off from the vertical axis toward the off direction Doff.
  • the second regions 15 each have a second lower end 15a at the lower end of the second layer 9 and a second upper end 15b at the upper end of the second layer 9.
  • the second lower end 15a is located in a region on the lower end side of the second layer 9 relative to the intermediate part of the thickness range of the second layer 9, and the second upper end 15b is located in a region on the upper end side of the second layer 9 relative to the intermediate part of the thickness range of the second layer 9.
  • the second regions 15 each consist of a single impurity region having a thickness (depth) that crosses the intermediate part of the second layer 9 along the second axial channel CH2.
  • the second lower end 15a may be formed with a gap from the lower end to the upper end of the second layer 9, and may face the first layer 8 (plurality of first regions 14) across a portion (lower end) of the second layer 9.
  • the second lower end 15a may be substantially coincident with the lower end of the second layer 9 and connected to the first layer 8.
  • the distance between the lower end of the second layer 9 and the second lower end 15a may be 0 ⁇ m or more and 2 ⁇ m or less.
  • the distance between the lower end of the second layer 9 and the second lower end 15a may have a value that belongs to any one of the ranges of 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the second lower end 15a may have an extension that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.
  • the thickness of the extension of the second lower end 15a based on the upper end of the first layer 8 may be greater than 0 ⁇ m and less than 2 ⁇ m.
  • the thickness of the extension of the second lower end 15a may have a value that belongs to any one of the following ranges: greater than 0 ⁇ m and less than 0.5 ⁇ m, 0.5 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, and 1.5 ⁇ m to 2 ⁇ m.
  • the second upper end 15b may be formed at a distance from the upper end of the second layer 9 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the second layer 9 across a part (upper end) of the second layer 9.
  • the space between the first main surface 3 and the second upper end 15b of the second layer 9 may be used as a region for forming a device structure (other impurity regions, etc.).
  • the second upper end 15b may be exposed from the upper end of the second layer 9 (i.e., the first main surface 3).
  • the distance between the upper end of the second layer 9 and the second upper end 15b may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper end of the second layer 9 and the second upper end 15b may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the second regions 15 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration (peak value) of the second regions 15 may be equal to or more than the p-type impurity concentration (peak value) of the first region 14.
  • the p-type impurity concentration (peak value) of the second regions 15 may be less than the p-type impurity concentration (peak value) of the first region 14.
  • the p-type impurity concentration (peak value) of the second regions 15 may be approximately equal to the p-type impurity concentration (peak value) of the first region 14.
  • the p-type impurity concentration of the second region 15 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the second region 15 is adjusted by a trivalent element that is heavier than carbon. In other words, the second region 15 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the second region 15 is adjusted by aluminum.
  • Each of the multiple second regions 15 has a second width W2.
  • the second width W2 is the width along the second arrangement direction Da2 of the second regions 15. It is preferable that the second width W2 is less than the second thickness T2 of the second layer 9. Of course, the second width W2 may be greater than or equal to the second thickness T2.
  • the second width W2 is preferably less than the first thickness T1 of the first layer 8. Of course, the second width W2 may be greater than or equal to the first thickness T1. The second width W2 is preferably approximately equal to the first width W1 of the first region 14. Of course, the second width W2 may be greater than or equal to the first width W1, or may be less than the first width W1.
  • the second width W2 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the second width W2 may have a value belonging to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the second width W2 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second regions 15 each have a second region thickness TR2 (region depth).
  • the second region thickness TR2 may be less than the second thickness T2 of the second layer 9.
  • the second region thickness TR2 may be greater than the second thickness T2.
  • the second region thickness TR2 may be approximately equal to the second thickness T2.
  • the second region thickness TR2 may be less than the first thickness T1 of the first layer 8.
  • the second region thickness TR2 may be greater than the first thickness T1.
  • the second region thickness TR2 may be approximately equal to the first thickness T1.
  • the second region thickness TR2 may be less than the first region thickness TR1 of the first region 14.
  • the second region thickness TR2 may be greater than the first region thickness TR1.
  • the second region thickness TR2 may be approximately equal to the first region thickness TR1.
  • the second region thickness TR2 is preferably 1 ⁇ m or more.
  • the second region thickness TR2 is preferably 5 ⁇ m or less.
  • the second region thickness TR2 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • each of the multiple second regions 15 has a second aspect ratio TR2/W2 that extends in a vertically elongated columnar shape along the second axial channel CH2.
  • the second aspect ratio TR2/W2 is the ratio of the second region thickness TR2 to the second width W2.
  • the second region thickness TR2 is greater than the second thickness T2.
  • the second aspect ratio TR2/W2 may be greater than 1 and less than or equal to 100.
  • the second regions 15 are formed at intervals of a second pitch P2 in the second arrangement direction Da2. It is preferable that the second pitch P2 is less than the second thickness T2 of the second layer 9. Of course, the second pitch P2 may be equal to or greater than the second thickness T2 of the second layer 9. It is preferable that the second pitch P2 is less than the first thickness T1 of the first layer 8. Of course, the second pitch P2 may be equal to or greater than the first thickness T1.
  • the second pitch P2 may be approximately equal to the first pitch P1, or may be different from the first pitch P1.
  • the second pitch P2 may be greater than the first pitch P1, or may be smaller than the first pitch P1.
  • the second pitch P2 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the second pitch P2 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the second pitch P2 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • a superjunction structure SJ having a two-layer structure is shown.
  • a superjunction structure SJ having a stacked structure of three or more layers may also be adopted.
  • a stack section 7 having a stacked structure of three or more layers may be formed, and a column region 12 having a stacked structure of three or more layers may be formed.
  • the third and subsequent semiconductor layers in the stack 7 are formed in the same configuration as the second layer 9.
  • the regions formed in the odd-numbered (2n+1: n is a natural number equal to or greater than 1) semiconductor layers are formed in the same configuration as the first region 14 (first mark Mk1), and the regions formed in the even-numbered (2n+2) semiconductor layers are formed in the same configuration as the second region 15 (second mark Mk2).
  • the (n+2)th region of the column region 12 is formed in the (n+2)th semiconductor layer in the same relationship as the (n+1)th region to the nth region.
  • the decorative pattern PT (multiple first marks Mk1 and multiple second marks Mk2) is formed in a layout according to the example layout of the first region 14 and the second region 15 shown below.
  • FIG. 8A is a plan view showing a first layout example of the column region 12 according to the first basic form.
  • FIG. 8B is a plan view showing a second layout example of the column region 12 according to the first basic form.
  • the first region 14 is indicated by a dashed line, and the second region 15 is indicated by hatching.
  • the first arrangement direction Da1 of the first regions 14 may be the a-axis direction (first direction X), and the first extension direction De1 of the first regions 14 may be the m-axis direction (second direction Y).
  • first direction X the first direction
  • second direction Y the first extension direction De1 intersects (specifically, is perpendicular to) the off-direction Doff of the first layer 8
  • the multiple first regions 14 are inclined by approximately the off angle ⁇ off from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane ((1-100) plane) of the SiC single crystal.
  • the m-plane of the SiC single crystal is a crystal plane perpendicular to the m-axis direction.
  • the multiple second regions 15 may be perpendicular to the multiple first regions 14 in a planar view. That is, the second arrangement direction Da2 of the second regions 15 may be the m-axis direction (second direction Y), and the second extension direction De2 of the second regions 15 may be the a-axis direction (first direction X).
  • the second arrangement direction Da2 coincides with the first extension direction De1 and is perpendicular to the first arrangement direction Da1. Also, the second extension direction De2 coincides with the first arrangement direction Da1 and is perpendicular to the first extension direction De1.
  • the multiple second regions 15 extend in approximately the vertical direction Z in a cross-sectional view seen from the a-plane ((11-20) plane) of the SiC single crystal.
  • the a-plane of the SiC single crystal is perpendicular to the a-axis direction.
  • the multiple second regions 15 are inclined by approximately the off angle ⁇ off from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane of the SiC single crystal.
  • the second regions 15 may intersect the first regions 14 non-orthogonally in a planar view. That is, the second arrangement direction Da2 of the second regions 15 may be a direction other than the m-axis direction and the a-axis direction, and the second extension direction De2 of the second regions 15 may be a direction other than the m-axis direction and the a-axis direction.
  • the second arrangement direction Da2 intersects with both the first arrangement direction Da1 and the first extension direction De1
  • the second extension direction De2 intersects with both the first arrangement direction Da1 and the first extension direction De1.
  • the second extension direction De2 intersects with the off-direction Doff of the second layer 9.
  • the second extension direction De2 may be inclined from the a-axis toward one side (left side of the paper) or the other side (right side of the paper) of the m-axis in a plan view.
  • the second regions 15 have a second extension direction De2 that forms an extension angle ⁇ a with the a-axis when the a-axis is set as the reference (0°).
  • the absolute value of the extension angle ⁇ a may be greater than 0° and less than 90°.
  • the extension angle ⁇ a may have a value that falls within any one of the following ranges: greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the absolute value of the extension angle ⁇ a is typically set to a value that falls within any one of the following ranges: 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the column region 12 may have the configuration shown in Figures 9, 10A, and 10B.
  • Figure 9 is a cross-sectional perspective view showing a second basic configuration of the column region 12.
  • Figures 10A and 10B are plan views showing first and second layout examples of the column region 12 according to the second basic configuration.
  • the first region 14 is indicated by a dashed line
  • the second region 15 is indicated by hatching.
  • the first arrangement direction Da1 of the first regions 14 may be the m-axis direction (first direction X), and the first extension direction De1 of the first regions 14 may be the a-axis direction (second direction Y).
  • the multiple first regions 14 extend in the substantially vertical direction Z in a cross-sectional view seen from the a-plane of the SiC single crystal.
  • the multiple first regions 14 are inclined by substantially the off angle ⁇ off from the vertical axis toward the off-direction Doff in a cross-sectional view seen from the m-plane of the SiC single crystal.
  • the second regions 15 may be orthogonal to the first regions 14 in a plan view. That is, the second array direction Da2 of the second regions 15 may be the a-axis direction (second direction Y), and the second extension direction De2 of the second regions 15 may be the m-axis direction (first direction X). In this case, the second array direction Da2 coincides with the first extension direction De1 and is orthogonal to the first array direction Da1. Also, the second extension direction De2 coincides with the first array direction Da1 and is orthogonal to the first extension direction De1.
  • the second extension direction De2 intersects (specifically, is perpendicular to) the off direction Doff of the second layer 9, so that the second regions 15 are inclined by approximately the off angle ⁇ off from the vertical axis toward the off direction Doff in a cross-sectional view seen from the m-plane of the SiC single crystal.
  • the second regions 15 may intersect the first regions 14 non-orthogonally in a planar view. That is, the second array direction Da2 of the second regions 15 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 of the second regions 15 may be a direction other than the a-axis direction and the m-axis direction.
  • the second array direction Da2 intersects with both the first array direction Da1 and the first extension direction De1
  • the second extension direction De2 intersects with both the first array direction Da1 and the first extension direction De1.
  • the second extension direction De2 intersects with the off direction Doff of the second layer 9.
  • the second extension direction De2 may be inclined from the a-axis toward one side (left side of the paper) or the other side (right side of the paper) of the m-axis in a plan view.
  • the second regions 15 have a second extension direction De2 that forms an extension angle ⁇ a with the a-axis when the a-axis is set as the reference (0°).
  • the absolute value of the extension angle ⁇ a may be greater than 0° and less than 90°.
  • the extension angle ⁇ a may have a value that falls within any one of the following ranges: greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the absolute value of the extension angle ⁇ a is typically set to a value that falls within any one of the following ranges: 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the column region 12 may have the configurations shown in Figures 11, 12A, 12B, and 12C.
  • Figure 11 is a cross-sectional perspective view showing a third basic configuration of the column region 12.
  • Figures 12A, 12B, and 12C are plan views showing first, second, and third layout examples of the column region 12 according to the third basic configuration.
  • the first region 14 is indicated by dashed lines, and the second region 15 is indicated by hatching.
  • the first arrangement direction Da1 of the first regions 14 is a direction other than the a-axis direction (first direction X) and the m-axis direction (second direction Y), and the first extension direction De1 of the first regions 14 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple first regions 14 may intersect both the a-axis direction and the m-axis direction.
  • Figures 12A to 12C show an example in which the first regions 14 are inclined toward one side of the m-axis (the left side of the paper) with respect to the a-axis.
  • the first extension direction De1 intersects with the off direction Doff, so that the first regions 14 are inclined from the vertical axis toward the off direction Doff by approximately the off angle ⁇ off in a cross-sectional view seen from the a-plane of the SiC single crystal and in a cross-sectional view seen from the m-plane of the SiC single crystal.
  • the first extension direction De1 forms a first extension angle ⁇ 1 with the a-axis when the a-axis is set as the reference (0°).
  • the absolute value of the first extension angle ⁇ 1 may be greater than 0° and less than 90°.
  • the first extension angle ⁇ 1 may have a value that belongs to any one of the following ranges: greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the absolute value of the first extension angle ⁇ 1 is typically set to a value that falls within one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • FIG. 12A shows a layout example in which the absolute value of the first extension angle ⁇ 1 is approximately 45°
  • FIG. 12B shows a layout example in which the absolute value of the first extension angle ⁇ 1 is approximately 30°
  • FIG. 12C shows a layout example in which the absolute value of the first extension angle ⁇ 1 is approximately 60°.
  • the first arrangement direction Da1 of the second regions 15 may be a direction other than the a-axis direction (first direction X) and the m-axis direction (second direction Y), and the first extension direction De1 of the second regions 15 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple second regions 15 may intersect both the a-axis direction and the m-axis direction.
  • the second regions 15 are inclined toward the other side of the m-axis (the right side of the paper) with the a-axis as a reference.
  • the second extension direction De2 intersects with the off direction Doff, so that the second regions 15 are inclined from the vertical axis toward the off direction Doff by approximately the off angle ⁇ off in the cross-sectional view seen from the a-plane and the cross-sectional view seen from the m-plane of the SiC single crystal.
  • the second extension direction De2 forms a second extension angle ⁇ 2 with the a-axis when the a-axis is used as the reference (0°). If the first extension angle ⁇ 1 is defined as a "positive value”, the second extension angle ⁇ 2 is a "negative value”. On the other hand, if the first extension angle ⁇ 1 is defined as a "negative value”, the second extension angle ⁇ 2 is a "positive value”.
  • the absolute value of the second extension angle ⁇ 2 may be greater than 0° and less than 90°.
  • the second extension angle ⁇ 2 may have a value that falls within any one of the following ranges: greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the absolute value of the second extension angle ⁇ 2 is typically set to a value belonging to any one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the absolute value of the second extension angle ⁇ 2 is preferably approximately equal to the absolute value of the first extension angle ⁇ 1.
  • the multiple second regions 15 have a layout that is approximately line-symmetric with the multiple first regions 14 with respect to the a-axis in a plan view per unit area (i.e., a partial plan view).
  • the multiple second regions 15 have a layout that is approximately point-symmetric with the multiple first regions 14 with respect to the vertical axis in a plan view per unit area (i.e., a partial plan view).
  • FIG. 12A shows a layout example in which the absolute value of the second extension angle ⁇ 2 is approximately 45° ( ⁇ 1)
  • FIG. 12B shows a layout example in which the absolute value of the second extension angle ⁇ 2 is approximately 30° ( ⁇ 1)
  • FIG. 12C shows a layout example in which the absolute value of the second extension angle ⁇ 2 is approximately 60° ( ⁇ 1).
  • the second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction, and are perpendicular to the first regions 14.
  • the sum of the absolute value of the first extension angle ⁇ 1 and the absolute value of the second extension angle ⁇ 2 is approximately a right angle (approximately 90°).
  • the second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction, and intersect with the first regions 14 non-orthogonally.
  • the sum of the absolute value of the first extension angle ⁇ 1 and the absolute value of the second extension angle ⁇ 2 is an acute angle (approximately 60°).
  • the second regions 15 extend in a direction intersecting both the a-axis direction and the m-axis direction, and intersect with the first regions 14 non-orthogonally.
  • the sum of the absolute value of the first extension angle ⁇ 1 and the absolute value of the second extension angle ⁇ 2 is an obtuse angle (approximately 120°).
  • the absolute value of the second extension angle ⁇ 2 may be greater than the absolute value of the first extension angle ⁇ 1, or may be less than the absolute value of the first extension angle ⁇ 1.
  • the multiple second regions 15 may have a layout that is asymmetrical with the multiple first regions 14 about the a-axis in a plan view per unit area (i.e., a partial plan view).
  • the multiple second regions 15 may have a layout that is asymmetrical with the multiple first regions 14 about the vertical axis in a plan view per unit area (i.e., a partial plan view).
  • the concentration gradient of the p-type impurity concentration in the first region 14 and the concentration gradient of the p-type impurity concentration in the second region 15 will be specifically explained. Since the concentration gradient of the first region 14 and the concentration gradient of the second region 15 are almost similar, the concentration gradient of the second region 15 will be exemplified below.
  • the concentration gradient of the first region 14 can be explained by substituting "first layer 8" with “base layer 6", “second layer 9” with “first layer 8”, “second region 15 (second lower end 15a and second upper end 15b)” with “first region 14 (first lower end 14a and first upper end 14b)” and “second axial channel CH2" with “first axial channel CH1” as necessary in the following explanation.
  • the relative or absolute positional relationship of the second region 15 with respect to the first layer 8 and second layer 9 applies mutatis mutandis to the relative or absolute positional relationship of the first region 14 with respect to the base layer 6 and first layer 8.
  • FIGS. 13A to 13E are graphs showing an example of the concentration gradient in the second region 15 (first region 14).
  • FIG. 14 is a graph showing a comparative example of the concentration gradient in the second region 15 (first region 14).
  • the vertical axis indicates the p-type impurity concentration in the second region 15, and the horizontal axis indicates the depth along the second axial channel CH2 with the upper end (first main surface 3) of the second layer 9 as the reference (zero point).
  • a region having a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more is defined as second region 15 and is shown as a graph.
  • the values of impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of second region 15 based on the concentration gradient, and are not shown with the intention of uniquely limiting the configuration of second region 15.
  • the impurity concentration, thickness, etc. are adjusted to various values depending on the implantation conditions of the trivalent element (dose amount, implantation temperature, implantation energy, etc.), etc.
  • FIGS. 13A to 13E are graphs showing the case where the second region 15 is formed by the channeling implantation method.
  • Each of the graphs shows the concentration gradient of the second region 15 when a predetermined trivalent element (here, aluminum) is introduced into the second layer 9 parallel or nearly parallel to the second axial channel CH2 with an implantation energy of 190 KeV (FIG. 13A), 380 KeV (FIG. 13B), 650 KeV (FIG. 13C), 960 KeV (FIG. 13D), or 2000 KeV (FIG. 13E).
  • the second thickness T2 of the second layer 9 is about 3 ⁇ m, and the dose of the trivalent element is 1 ⁇ 10 13 cm ⁇ 2 .
  • Fig. 14 is a graph showing the case where the second region 15 is formed by the random implantation method.
  • Fig. 14 shows the concentration gradient of the second region 15 when a predetermined trivalent element (here, aluminum) is introduced into the second layer 9 in a random direction by implantation energy of 190 KeV, 380 KeV, 650 KeV, 960 KeV, or 2000 KeV.
  • the random direction is a direction (for example, the vertical direction Z) that is not parallel (almost parallel) to the second axial channel CH2.
  • the second thickness T2 of the second layer 9 is about 3 ⁇ m, and the dose of the trivalent element is 1 x 10 13 cm -2 .
  • the second region 15 (190 KeV) has a second region thickness TR2 of 1.5 ⁇ m or more and 1.8 ⁇ m or less, and has a second lower end 15a spaced from the lower end of the second layer 9 toward the upper end, and a second upper end 15b exposed from the upper end (first main surface 3) of the second layer 9.
  • the distance between the lower end of the second layer 9 and the second lower end 15a is 1.2 ⁇ m or more and 1.5 ⁇ m or less.
  • the p-type impurity concentration of the second region 15 has a concentration gradient from the upper end to the lower end of the second layer 9, including a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23.
  • the gradually increasing portion 20 is a portion that forms the second upper end portion 15b of the second region 15, and is a portion where the p-type impurity concentration gradually increases from the second upper end portion 15b toward the lower end side of the second layer 9 to the peak portion 21 at a relatively steep rate of increase.
  • Peak portion 21 is a portion having a peak value P (maximum value) of the p-type impurity concentration. Peak portion 21 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend).
  • the depth position of peak portion 21 is 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • the gradual portion 22 is formed in a region closer to the second lower end 15a than the peak portion 21, and is a portion where the impurity concentration gradually decreases at a relatively gradual rate of decrease.
  • the gradual portion 22 is a portion that maintains a constant p-type impurity concentration in a certain depth range, and forms the main body of the second region 15.
  • the p-type impurity concentration of the gradual portion 22 gradually decreases in a concentration range that is less than the p-type impurity concentration of the peak portion 21.
  • the gradual portion 22 is defined by a portion having a concentration drop rate of 50% or less in a thickness range of at least 0.5 ⁇ m.
  • the gradual portion 22 has a thickness of 0.7 ⁇ m or more and 0.8 ⁇ m or less, and has a concentration drop rate of 50% or less in the thickness range.
  • the p-type impurity concentration of the gradual portion 22 is within a concentration range of 4.5 ⁇ 10 16 cm -3 or more and 9 ⁇ 10 16 cm -3 or less.
  • the gradually decreasing portion 23 is a portion that forms the second lower end 15a of the second region 15.
  • the gradually decreasing portion 23 has a concentration decrease rate that is greater than the concentration decrease rate in the gradual portion 22, and is a portion where the p-type impurity concentration gradually decreases from the gradual portion 22 toward the lower end of the second layer 9.
  • the concentration decrease rate per unit thickness of the gradually decreasing portion 23 is greater than the concentration decrease rate per unit thickness of the gradual portion 22.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual portion 22 to 1 ⁇ 10 15 cm -3 .
  • the second region 15 (380 KeV) has a second region thickness TR2 of 2.2 ⁇ m or more and 2.4 ⁇ m or less, and has a second lower end 15a spaced from the lower end to the upper end of the second layer 9, and a second upper end 15b spaced from the upper end (first main surface 3) of the second layer 9 to the lower end side (first layer 8 side).
  • the distance between the lower end of the second layer 9 and the second lower end 15a is 0.5 ⁇ m or more and 0.8 ⁇ m or less.
  • the distance between the upper end of the second layer 9 and the second upper end 15b of the second region 15 is 0.01 ⁇ m or more and 0.2 ⁇ m or less.
  • the p-type impurity concentration of the second region 15 has a concentration gradient from the upper end to the lower end of the second layer 9, similar to the example of FIG. 13A, which includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23.
  • the gradually increasing portion 20 also increases gradually from the second upper end 15b toward the lower end side of the second layer 9 to the peak portion 21 at a relatively steep rate of increase.
  • the depth position of the peak portion 21 is 0.3 ⁇ m or more and 0.7 ⁇ m or less.
  • the gradual decrease portion 22 has a thickness of 0.8 ⁇ m or more and 1.1 ⁇ m or less, and has a concentration decrease rate of 50% or less within this thickness range.
  • the p-type impurity concentration of the gradual decrease portion 22 is within a concentration range of 3.5 ⁇ 10 16 cm -3 or more and 7 ⁇ 10 16 cm -3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual decrease portion 22 to 1 ⁇ 10 15 cm -3 .
  • the second region 15 (650 KeV) has a second region thickness TR2 of 2.5 ⁇ m or more and 2.8 ⁇ m or less, and has a second lower end 15a spaced from the lower end to the upper end of the second layer 9, and a second upper end 15b spaced from the upper end (first main surface 3) of the second layer 9 to the lower end side (first layer 8 side).
  • the distance between the lower end of the second layer 9 and the second lower end 15a is 0.01 ⁇ m or more and 0.1 ⁇ m or less.
  • the distance between the upper end of the second layer 9 and the second upper end 15b of the second region 15 is 0.1 ⁇ m or more and 0.4 ⁇ m or less.
  • the p-type impurity concentration of the second region 15 has a concentration gradient that includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 from the second upper end 15b to the second lower end 15a, as in the example of FIG. 13A.
  • the gradually increasing portion 20 also increases gradually from the second upper end 15b of the second region 15 to the peak portion 21 at a relatively steep rate of increase.
  • the depth position of the peak portion 21 is 0.6 ⁇ m or more and 1 ⁇ m or less.
  • the gradual decrease portion 22 has a thickness of 1 ⁇ m or more and 1.3 ⁇ m or less, and has a concentration decrease rate of 50% or less within this thickness range.
  • the p-type impurity concentration of the gradual decrease portion 22 is within a concentration range of 3 ⁇ 10 16 cm -3 or more and 6 ⁇ 10 16 cm -3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual decrease portion 22 to 1 ⁇ 10 15 cm -3 .
  • the second region 15 (960 KeV) has a second region thickness TR2 of 3.1 ⁇ m or more and 3.3 ⁇ m or less, and has a second upper end 15b spaced from the upper end (first main surface 3) of the second layer 9 toward the lower end (first layer 8 side), and a second lower end 15a located within the first layer 8.
  • the second lower end 15a has an extension that crosses the boundary between the first layer 8 and the second layer 9 and extends into the first layer 8.
  • the extension of the second lower end 15a has a thickness of 0.4 ⁇ m or more and 0.7 ⁇ m or less based on the upper end of the first layer 8.
  • the distance between the upper end of the second layer 9 and the second upper end 15b of the second region 15 is 0.3 ⁇ m or more and 0.6 ⁇ m or less.
  • the p-type impurity concentration of the second region 15 has a concentration gradient that includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 from the second upper end 15b to the second lower end 15a, as in the example of FIG. 13A.
  • the gradually increasing portion 20 also increases gradually from the second upper end 15b of the second region 15 to the peak portion 21 at a relatively steep rate of increase.
  • the depth position of the peak portion 21 is 0.7 ⁇ m or more and 1.3 ⁇ m or less.
  • the gradual decrease portion 22 has a thickness of 1.3 ⁇ m or more and 1.7 ⁇ m or less, and has a concentration decrease rate of 50% or less within this thickness range.
  • the p-type impurity concentration of the gradual decrease portion 22 is within a concentration range of 2.2 ⁇ 10 16 cm -3 or more and 4.5 ⁇ 10 16 cm -3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual decrease portion 22 to 1 ⁇ 10 15 cm -3 .
  • the second region 15 (2000 KeV) has a second region thickness TR2 of 3.5 ⁇ m or more and 3.8 ⁇ m or less, and has a second upper end 15b spaced from the upper end (first main surface 3) of the second layer 9 toward the lower end (first layer 8 side), and a second lower end 15a located within the first layer 8.
  • the second lower end 15a has an extension that crosses the boundary between the first layer 8 and the second layer 9 and extends into the first layer 8.
  • the extension of the second lower end 15a has a thickness of 1.4 ⁇ m or more and 1.8 ⁇ m or less based on the upper end of the first layer 8.
  • the distance between the upper end of the second layer 9 and the second upper end 15b of the second region 15 is 0.7 ⁇ m or more and 1 ⁇ m or less.
  • the p-type impurity concentration of the second region 15 has a concentration gradient that includes a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 from the second upper end 15b to the second lower end 15a, as in the example of FIG. 13A.
  • the gradually increasing portion 20 also increases gradually from the second upper end 15b of the second region 15 to the peak portion 21 at a relatively steep rate of increase.
  • the depth position of the peak portion 21 is 1.3 ⁇ m or more and 1.9 ⁇ m or less.
  • the gradual portion 22 has a thickness of 1.5 ⁇ m or more and 1.8 ⁇ m or less, and has a concentration decrease rate of 50% or less in this thickness range.
  • the gradual portion 22 crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8. That is, the extension of the second region 15 includes a part of the gradual portion 22.
  • the p-type impurity concentration of the gradual portion 22 is within a concentration range of 2 ⁇ 10 16 cm ⁇ 3 or more and 4 ⁇ 10 16 cm ⁇ 3 or less.
  • the p-type impurity concentration of the gradually decreasing portion 23 gradually decreases from the gradual portion 22 to 1 ⁇ 10 15 cm ⁇ 3 .
  • the p-type impurity concentration of second region 15 has a gradually increasing portion 20, a peak portion 21, a gradual portion 22, and a gradually decreasing portion 23 at any implantation energy.
  • the second region thickness TR2 (depth) of second region 15 increases with increasing implantation energy.
  • the depth position of second upper end 15b of second region 15 relative to the upper end of second layer 9 increases with increasing implantation energy.
  • the thickness of the gradually increasing portion 20, the peak portion 21, the gradual portion 22, and the gradually decreasing portion 23 all increase with increasing implantation energy.
  • the peak value P of the second region 15 decreases with increasing implantation energy. This is because the trivalent element is introduced into deeper regions with increasing implantation energy, increasing the p-type impurity concentration in these deep regions.
  • the slow portion 22 occupies a thickness range of at least 1/4 of the second region 15 (second region thickness TR2) and is located within the second layer 9. Specifically, the proportion of the slow portion 22 in the second region 15 is at least 1/3. The proportion of the slow portion 22 in the second region 15 is typically at most 1/2 (less than 1/2). The proportion of the slow portion 22 in the second region 15 may be at least 1/2.
  • the second region 15 had a gradual increase portion 20, a peak portion 21 (peak value P), and a gradual decrease portion 23 in the range of 0.5 ⁇ m, but did not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more.
  • the depth position of the peak portion 21 (peak value P) relative to the upper end of the second layer 9 increased with increasing injection energy, but the second region thickness TR2 of the second region 15 was less than 2 ⁇ m at any injection energy. In other words, even if the injection energy was increased, the second region thickness TR2 did not fluctuate significantly.
  • the second region 15 consisting of a single impurity region for the second layer 9 having a relatively large second thickness T2 (for example, a second thickness T2 of 1 ⁇ m or more).
  • a second thickness T2 for example, a second thickness T2 of 1 ⁇ m or more.
  • SiC single crystals have physical properties that make it difficult for impurities to diffuse. Therefore, the above problem is generally solved by the multi-epitaxial growth method or the multi-stage random injection method.
  • a process of introducing a trivalent element into an epitaxial layer having a relatively small thickness (for example, less than 1 ⁇ m) by random injection is repeated multiple times.
  • the number of epitaxial growth steps and the number of random injection steps increase, making the manufacturing process more complicated.
  • a process is carried out in which a trivalent element is introduced in multiple stages at different depth positions using multiple injection energies.
  • the trivalent element is introduced into the second layer 9 at five injection energies (190 KeV, 380 KeV, 650 KeV, and 960 KeV).
  • the trivalent element can be introduced to the desired depth position, but the depth position at which the trivalent element can be introduced is shallow. Therefore, the number of epitaxial growth steps and the number of random injection steps must be increased, resulting in the same problems as in the multi-epitaxial growth method.
  • a second region 15 having a slow portion 22 with a thickness of 0.5 ⁇ m to 2 ⁇ m is formed in a second layer 9 having a relatively large thickness (for example, a thickness of 1 ⁇ m to 5 ⁇ m). Therefore, a second region 15 having a charge balance is formed with fewer steps than the steps required when the random injection method is adopted.
  • each second region 15 is made up of an integrated region of multiple impurity regions (second regions 15) formed in the second layer 9 along the second axial channel CH2 so as to cross the middle part of the second layer 9.
  • the p-type impurity concentration (concentration gradient) of each second region 15 is the sum of the p-type impurity concentrations (concentration gradients) of the multiple impurity regions (second regions 15).
  • the p-type impurity concentration of each second region 15 has a concentration gradient (sum of concentration gradients) obtained by superimposing at least two of the five graphs shown in Figures 13A to 13E.
  • the upper limit of the implantation energy for the channeling implantation method is 2000 KeV, but the second region 15 can also be formed with an implantation energy greater than 2000 KeV. In this case, a relatively thick second region 15 is formed at a position deeper than the concentration gradient shown in Figure 13E.
  • the amount of trivalent elements passing through the upper end of the second layer 9 increases, and the range of the free space on the upper end side (i.e., the distance between the first main surface 3 and the second region 15) expands, making it more difficult to design the column region 12.
  • the size of the ion accelerator may reach several tens of meters, which is considered to be unrealistic from the standpoint of cost-effectiveness (installation space and capital investment).
  • the injection energy when forming a relatively thick column region 12 by channeling injection, it is preferable to limit the injection energy to 2000 KeV or less and increase the number of layers in the stack 7 (the number of layers in the superjunction structure SJ).
  • first to twelfth embodiment examples of the column region 12 are shown with reference to Figures 15 to 35.
  • the column region 12 according to the first to third basic embodiments may have at least one of the multiple features shown in the first to twelfth embodiment examples.
  • the column region 12 according to the first to third basic embodiments may have a feature that combines multiple (two or more) features shown in the first to twelfth embodiment examples.
  • the "gradual increase portion 20”, “peak portion 21 (peak value P)”, “slow portion 22” and “gradual decrease portion 23" of the first region 14 are referred to as the “first gradual increase portion 20A”, “first peak portion 21A (first peak value PA)", “first slow portion 22A” and “first gradual decrease portion 23A”.
  • the “gradual increase portion 20”, “peak portion 21 (peak value P)”, “slow portion 22” and “gradual decrease portion 23" of the second region 15 are referred to as the “second gradual increase portion 20B", “second peak portion 21B (second peak value PB)”, “second slow portion 22B” and “second gradual decrease portion 23B”.
  • FIG. 15 is a cross-sectional perspective view showing the column region 12 according to the first embodiment.
  • FIG. 16 is a graph showing an example of the concentration gradient of the column region 12 shown in FIG. 15.
  • the first region 14 has a first region thickness TR1 that is less than the first thickness T1 of the first layer 8, and is formed within the first layer 8 with a space from both the lower end and the upper end of the first layer 8.
  • the first lower end 14a of the first region 14 is formed with a space from the lower end (base layer 6) of the first layer 8 toward the upper end, and faces the base layer 6 with a part of the first layer 8 (lower end) in between.
  • the first upper end 14b of the first region 14 is formed at a distance from the upper end (second layer 9) of the first layer 8 toward the lower end, and faces the second layer 9 across a part (upper end) of the first layer 8.
  • the first gradually increasing portion 20A, the first peak portion 21A, the first gradual portion 22A, and the first gradually decreasing portion 23A of the first region 14 are located within the first layer 8.
  • the first layer 8 has a first thickness T1 of 3 ⁇ m
  • the first region 14 is formed in the first layer 8 by an implantation energy of 650 KeV.
  • the first region 14 may be formed by an implantation energy of 650 KeV or less.
  • the second region 15 has a second region thickness TR2 that is less than the second thickness T2 of the second layer 9, and is formed within the second layer 9 at a distance from both the lower end and the upper end of the second layer 9. Specifically, the second lower end 15a of the second region 15 is formed at a distance from the lower end (first layer 8) of the second layer 9 toward the upper end, and faces the first layer 8 with a part of the second layer 9 (lower end) in between.
  • the second upper end 15b of the second region 15 is formed at a distance from the upper end (first main surface 3) of the second layer 9 toward the lower end, and faces the first main surface 3 across a part (upper end) of the second layer 9.
  • the second gradually increasing portion 20B, the second peak portion 21B, the second gradual portion 22B, and the second gradually decreasing portion 23B of the second region 15 are located within the second layer 9.
  • the second layer 9 has a second thickness T2 of 3 ⁇ m
  • the second region 15 is formed in the second layer 9 with an implantation energy of 650 KeV.
  • the second region 15 may be formed with an implantation energy of 650 KeV or less.
  • the implantation energy for the second region 15 may be different from the implantation energy for the first region 14.
  • the second region thickness TR2 of the second region 15 may be different from the first region thickness TR1 of the first region 14.
  • the second region thickness TR2 may be less than the first region thickness TR1 or may be greater than the first region thickness TR1.
  • FIG. 17 is a cross-sectional perspective view showing the column region 12 according to the second embodiment.
  • FIG. 18 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 17.
  • the column region 12 according to the second embodiment has a form obtained by modifying the second region 15 according to the first embodiment.
  • the form of the first region 14 according to the second embodiment is similar to that of the first region 14 according to the first embodiment.
  • the second region 15 is formed in the second layer 9 with a gap between the upper end and the lower end of the second layer 9, and has a portion that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.
  • the second lower end 15a of the second region 15 has an extension that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.
  • the extension of the second lower end 15a is formed along the first axial channel CH1 within the first layer 8.
  • the extension of the second lower end 15a is preferably located on the upper end side of the first layer 8 relative to the intermediate part of the thickness range of the first layer 8.
  • the extension of the second lower end 15a is connected to the first region 14 (first upper end 14b) within the first layer 8.
  • a portion (extension) of the second region 15 is provided in the space between the upper end of the first layer 8 and the first upper end 14b of the first region 14, and the first region 14 and the second region 15 form a single column region 12 that extends continuously in a three-dimensional lattice pattern. This improves the accuracy of the charge balance.
  • the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 of the second layer 9.
  • the second region thickness TR2 is also greater than the first thickness T1 of the first layer 8.
  • the second region thickness TR2 is also greater than the first region thickness TR1 of the first region 14.
  • the second region thickness TR2 may be less than the second thickness T2.
  • the second region thickness TR2 may be less than the first region thickness TR1.
  • the second region thickness TR2 may be less than the first region thickness TR1.
  • the second gradually increasing portion 20B, the second peak portion 21B, the second gradually decreasing portion 22B and the second gradually decreasing portion 23B of the second region 15 are located in the second layer 9. At least a portion of the second gradually decreasing portion 23B is located in the first layer 8. That is, the extension of the second lower end portion 15a includes the second gradually decreasing portion 23B. Of course, a portion of the second gradually decreasing portion 22B may be located in the first layer 8 (see FIG. 13E). That is, the extension of the second lower end portion 15a may include a portion of the second gradually decreasing portion 22B and the second gradually decreasing portion 23B.
  • the second layer 9 has a first thickness T1 of 3 ⁇ m
  • the second region 15 is formed in the second layer 9 by an implantation energy of 960 KeV.
  • the second region 15 may be formed by an implantation energy of 960 KeV or more.
  • the second thickness T2 may be greater than 3 ⁇ m and less than or equal to 5 ⁇ m.
  • the second region 15 connected to the first region 14 is formed in the first layer 8 by an implantation energy of 960 KeV or more (see also FIGS. 13F to 13E).
  • FIG. 19 is a cross-sectional perspective view showing the column region 12 according to the third embodiment.
  • FIG. 20 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 19.
  • the column region 12 according to the third embodiment has a shape obtained by modifying the second region 15 according to the second embodiment.
  • the first region 14 according to the third embodiment has a shape similar to that of the first region 14 according to the first embodiment.
  • the second region 15 in the second embodiment is formed in the second layer 9 having a second thickness T2 that is approximately equal to the first thickness T1 of the first layer 8.
  • the second region 15 in the third embodiment is formed in the second layer 9 having a second thickness T2 that is less than the first thickness T1 of the first layer 8.
  • the second region 15 has a second region thickness TR2 that is greater than the second thickness T2 of the second layer 9.
  • the second layer 9 has a second thickness T2 of less than 3 ⁇ m (here, 2 ⁇ m), and the second region 15 is formed in the second layer 9 by an implantation energy of 650 KeV.
  • the second region 15 may also be formed by an implantation energy of 650 KeV or less.
  • the second thickness T2 may be 1 ⁇ m or more and 2 ⁇ m or less.
  • a second region 15 that is connected to the first region 14 is formed in the first layer 8 by an implantation energy of 190 KeV or more (see also Figures 13A to 13E).
  • the second thickness T2 may be 2 ⁇ m or more and less than 3 ⁇ m.
  • a second region 15 that is connected to the first region 14 is formed in the first layer 8 by an implantation energy of 380 KeV or more (see also Figures 13B to 13E).
  • the concentration gradient formed at the connection between the first region 14 and the second region 15 is mitigated, improving the accuracy of the charge balance. Furthermore, with the second layer 9 having a relatively small second thickness T2, the second region 15 connected to the first region 14 can be formed with a relatively small injection energy. Therefore, manufacturing costs are reduced.
  • the first region thickness TR1 (implantation energy) of the first region 14 and the second region thickness TR2 (implantation energy) of the second region 15 can be set to be the same, while a second region 15 connected to the first region 14 can be formed within the first layer 8.
  • the second thickness T2 of the second layer 9 can be set to be less than the first thickness T1 of the first layer 8, and a second region 15 having a second region thickness TR2 greater than the second thickness T2 can be formed.
  • FIG. 21 is a cross-sectional perspective view showing the column region 12 according to the fourth embodiment.
  • FIG. 22 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 21.
  • the column region 12 according to the fourth embodiment has a shape obtained by modifying the first region 14 according to the second embodiment.
  • the second region 15 according to the fourth embodiment has a shape similar to that of the second region 15 according to the second embodiment.
  • the second region 15 according to the fourth embodiment may have a shape similar to that of the second region 15 according to the third embodiment.
  • the first region 14 is formed in the first layer 8 with a gap between the upper end and the lower end of the first layer 8, and has a portion that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.
  • the first lower end 14a of the first region 14 has an extension that crosses the boundary between the base layer 6 and the first layer 8 and is located within the base layer 6.
  • the extension of the first lower end 14a is formed along the base axial channel CHB within the base layer 6. It is preferable that the extension of the first lower end 14a is located on the upper end side of the base layer 6 relative to the intermediate part of the thickness range of the base layer 6. The extension of the first lower end 14a is connected to the base layer 6 within the base layer 6.
  • the first region 14 has a first region thickness TR1 that is greater than the first thickness T1 of the first layer 8.
  • the first region thickness TR1 is also greater than the second thickness T2 of the second layer 9.
  • the first region thickness TR1 is also greater than the second region thickness TR2 of the second region 15.
  • the first region thickness TR1 may be less than the first thickness T1.
  • the first region thickness TR1 may be less than the second thickness T2.
  • the first region thickness TR1 may be less than the second region thickness TR2.
  • the first increasing portion 20A, the first peak portion 21A, the first gradual portion 22A and the first decreasing portion 23A of the first region 14 are located in the first layer 8. At least a portion of the first decreasing portion 23A is located in the base layer 6. That is, the extension of the first lower end 14a includes the first decreasing portion 23A. Of course, a portion of the first gradual portion 22A may be located in the base layer 6 (see FIG. 13E). That is, the extension of the first lower end 14a may include a portion of the first gradual portion 22A and the first decreasing portion 23A.
  • the first layer 8 has a first thickness T1 of 3 ⁇ m
  • the first region 14 is formed in the first layer 8 by an implantation energy of 960 KeV.
  • the first region 14 may be formed by an implantation energy of 960 KeV or more.
  • the first thickness T1 may be greater than 3 ⁇ m and less than or equal to 5 ⁇ m.
  • the first region 14 is formed by an implantation energy of 960 KeV or more, which is partially located in the base layer 6 (see also FIGS. 13F-13E).
  • FIG. 23 is a cross-sectional perspective view showing the column region 12 according to the fifth embodiment.
  • FIG. 24 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 23.
  • the column region 12 according to the fifth embodiment has a shape obtained by modifying the first region 14 according to the fourth embodiment.
  • the second region 15 according to the fifth embodiment has a shape similar to that of the second region 15 according to the second embodiment.
  • the second region 15 according to the fifth embodiment may have a shape similar to that of the second region 15 according to the third embodiment.
  • the first layer 8 has a first thickness T1 of 3 ⁇ m, and the first region 14 is formed in the first layer 8 by an implantation energy of 960 KeV or more.
  • the first layer 8 has a first thickness T1 of less than 3 ⁇ m, and the first region 14 is formed in the first layer 8 by an implantation energy of 650 KeV or more.
  • the first region 14 has a first region thickness TR1 that is greater than the first thickness T1 in this example.
  • the first thickness T1 is less than the second thickness T2 of the second layer 9 in this example.
  • the first thickness T1 may be 1 ⁇ m or more and 2 ⁇ m or less.
  • the first region 14 is formed partially located within the base layer 6 by implantation energy of 190 KeV or more (see also Figures 13A to 13E).
  • the first thickness T1 may be 2 ⁇ m or more and less than 3 ⁇ m.
  • the first region 14 is formed partially located within the base layer 6 by implantation energy of 380 KeV or more (see also Figures 13B to 13E).
  • FIG. 25 is a cross-sectional perspective view showing a column region 12 according to a sixth embodiment.
  • FIG. 26 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 25.
  • the column region 12 includes a p-type intermediate region 25 interposed between the first region 14 and the second region 15, in addition to the first region 14 and the second region 15.
  • the first region 14 may have a shape similar to any one of the shapes of the first region 14 according to the first to fifth embodiment examples.
  • the first region 14 has a shape similar to the shape of the first region 14 according to the fourth embodiment example.
  • the second region 15 may have a shape similar to any one of the shapes of the second region 15 according to the first to fifth embodiment examples.
  • the second region 15 has a shape similar to the shape of the second region 15 according to the fourth embodiment example (second embodiment example).
  • the intermediate regions 25 are formed in the surface layer portion on the upper end side of the first layer 8 so as to be positioned at least at multiple intersections between the multiple first regions 14 and the multiple second regions 15, and overlap the corresponding first regions 14 and second regions 15 in the stacking direction.
  • the intermediate regions 25 are arranged at intervals in the first arrangement direction Da1 so as to overlap the multiple first regions 14 in a one-to-one correspondence in the stacking direction, and are each formed in a band shape extending in the first extension direction De1.
  • the first arrangement direction Da1 is the a-axis direction (first direction X), and the first extension direction De1 is the m-axis direction (second direction Y).
  • the arrangement direction and extension direction of the multiple intermediate regions 25 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction.
  • the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction
  • the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the intermediate regions 25, together with the first regions 14, are drawn out from the active region 10 to the peripheral region 11.
  • the intermediate regions 25 are drawn out from a portion of the first layer 8 located within the active region 10 to a portion of the first layer 8 located within the peripheral region 11.
  • the intermediate regions 25 are also arranged at intervals in the first array direction Da1 in the peripheral region 11, and are each formed in a strip shape extending in the first extension direction De1.
  • the multiple intermediate regions 25 extend from the peripheral region 11 toward either or both of the first side 5A and the third side 5C (both in this embodiment), and each has a portion exposed from either or both of the first side 5A and the third side 5C (both in this embodiment).
  • the portions of the multiple intermediate regions 25 exposed from the first side surface 5A form a portion (upper end portion) of the multiple first marks Mk1 on the first side surface 5A
  • the portions of the multiple intermediate regions 25 exposed from the third side surface 5C form a portion (upper end portion) of the multiple first marks Mk1 on the third side surface 5C.
  • the multiple intermediate regions 25 include either or both of the portions (upper end portions) of the multiple first marks Mk1 as exposed portions exposed from the first side surface 5A and the portions (upper end portions) of the multiple first marks Mk1 as exposed portions exposed from the third side surface 5C.
  • the multiple first marks Mk1 are each formed using the multiple first regions 14 and the multiple intermediate regions 25.
  • the layout (exposed locations and arrangement direction) of the multiple first marks Mk1 on the first side 5A (third side 5C) is also appropriately adjusted depending on the layout (first arrangement direction Da1 and first extension direction De1) of the multiple first regions 14 and the multiple intermediate regions 25.
  • the multiple first marks Mk1 do not necessarily need to be formed continuously from the main body portions of the multiple intermediate regions 25, but may be formed as separate portions separated from the main body portions of the multiple intermediate regions 25. In this case, it is preferable that the multiple first marks Mk1 are separated from the main body portions of the multiple intermediate regions 25 in the outer circumferential region 11.
  • the multiple intermediate regions 25 do not necessarily have to form part (upper end) of the multiple first marks Mk1.
  • the multiple intermediate regions 25 may be formed in the inner part of the first layer 8 at a distance from the first to fourth side faces 5A to 5D in a plan view.
  • the explanation for the intermediate regions 25 also applies to the first mark Mk1 (the portions of the intermediate regions 25 exposed from the first side face 5A/third side face 5C).
  • the intermediate regions 25 are formed in the first layer 8 in a region between the upper end of the first layer 8 and the first upper end 14b of the first region 14.
  • the intermediate regions 25 are preferably located on the upper end side of the first layer 8 relative to the middle part of the thickness range of the first layer 8.
  • the intermediate regions 25 may be exposed from the upper end of the first layer 8, or may be formed at intervals from the upper end to the lower end side of the first layer 8.
  • Each intermediate region 25 may be formed in a horizontally elongated columnar shape extending in the horizontal direction in a cross-sectional view. Of course, each intermediate region 25 may be formed in a vertically elongated columnar shape extending in the vertical direction Z.
  • the intermediate regions 25 form intermediate pn junctions having charge balance together with the first layer 8.
  • the intermediate regions 25 form part of the first superjunction structure SJ1 together with the first drift regions 16.
  • the state of having charge balance means that, for adjacent intermediate regions 25, the depletion layer extending from one intermediate pn junction and the depletion layer extending from the other intermediate pn junction are connected within the first drift regions 16.
  • each intermediate region 25 may include a single or multiple area elements 25a.
  • FIG. 26 shows an example in which each intermediate region 25 includes multiple (two) area elements 25a.
  • the single area element 25a is formed in the area between the upper end of the first layer 8 and the first upper end 14b of the first region 14, and is connected to the first upper end 14b of the first region 14.
  • the multiple region elements 25a are each formed at different depth positions in the region between the upper end of the first layer 8 and the first upper end 14b of the first region 14. In this case, the multiple region elements 25a are each formed so as to be connected to each other in the stacking direction. Also, at least the bottom region element 25a is connected to the first upper end 14b of the first region 14.
  • the region element 25a is composed of a random impurity region introduced into the surface layer of the first layer 8 by a random injection method into the first layer 8 (see also FIG. 14). In other words, the region element 25a is not formed in the second layer 9. Furthermore, the region element 25a has a thickness in the direction along the first axial channel CH1 that is less than the first region thickness TR1 of the first region 14. Furthermore, the thickness of the region element 25a is less than the second region thickness TR2 of the second region 15.
  • the region element 25a does not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more, and has a concentration gradient including a gradually increasing portion 20, a peak portion 21, and a gradually decreasing portion 23 in a range of 0.5 ⁇ m.
  • each intermediate region 25 has multiple peak portions 21 (peak value P) according to the number of multiple region elements 25a in the thickness direction of the first layer 8.
  • the region element 25a may have a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less as a peak value P.
  • Fig. 26 shows an example in which the peak value P of the p-type impurity concentration of the region element 25a is 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 17 cm ⁇ 3 or less.
  • the p-type impurity concentration of the intermediate region 25 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the intermediate region 25 may be the same as the trivalent element of the first region 14, etc., or may be a different species from the trivalent element of the first region 14, etc.
  • the trivalent element of the intermediate region 25 may be at least one of boron, aluminum, gallium, and indium.
  • the intermediate regions 25 each have an intermediate width WM.
  • the intermediate width WM is a width along the first arrangement direction Da1. It is preferable that the intermediate width WM is less than the first thickness T1 of the first layer 8. Of course, the intermediate width WM may be equal to or greater than the first thickness T1. It is preferable that the intermediate width WM is less than the second thickness T2 of the second layer 9. Of course, the intermediate width WM may be equal to or greater than the second thickness T2.
  • the intermediate width WM is approximately equal to the first width W1 of the first region 14.
  • the intermediate width WM may be greater than or equal to the first width W1, or less than the first width W1. It is preferable that the intermediate width WM is greater than or equal to 1 ⁇ m. It is preferable that the intermediate width WM is less than or equal to 5 ⁇ m.
  • the intermediate width WM may have a value falling within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the intermediate regions 25 each have an intermediate thickness TM.
  • the intermediate thickness TM is preferably equal to or greater than the distance between the upper end of the first layer 8 and the first upper end 14b of the first region 14.
  • the intermediate thickness TM may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the intermediate thickness TM may have a value that falls within any one of the ranges of 0.1 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the intermediate regions 25 are formed at an intermediate pitch PM interval in the first arrangement direction Da1. It is preferable that the intermediate pitch PM is approximately equal to the first pitch P1 of the first region 14. Of course, the intermediate pitch PM may be equal to or greater than the first pitch P1, or may be less than the first pitch P1. For clarity, an intermediate pitch PM greater than the first pitch P1 is shown in FIG. 25.
  • the intermediate pitch PM may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the intermediate pitch PM may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the intermediate pitch PM is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the second region 15 preferably has an extension located within the first layer 8 and is connected to the intermediate region 25 within the first layer 8.
  • the second region 15 preferably is electrically connected to the first region 14 via the intermediate region 25 within the first layer 8.
  • the second region 15 forms one drift region 13 that extends continuously in the stacking direction together with the first region 14 and the intermediate region 25.
  • the extension of the second region 15 may be connected to both the intermediate region 25 and the first region 14 within the first layer 8.
  • the concentration gradient in the region between the first region 14 and the second region 15 is mitigated by the intermediate region 25, improving the accuracy of the charge balance.
  • FIG. 27 is a cross-sectional perspective view showing the column region 12 according to the seventh embodiment.
  • FIG. 28 is a graph showing an example of the concentration gradient of the column region 12 shown in FIG. 27.
  • the column region 12 according to the seventh embodiment has a shape obtained by modifying the first region 14 according to the first to sixth embodiments.
  • the second region 15 according to the seventh embodiment may have a shape similar to any one of the shapes of the second region 15 according to the first to sixth embodiments.
  • the first region 14 is exposed from the upper end of the first layer 8.
  • the first region 14 does not have part or all of the first gradually increasing portion 20A.
  • Figure 28 shows an example in which the first region 14 does not have all of the first gradually increasing portion 20A and the first peak portion 21A. That is, in this example, the first upper end 14b includes the first gradual portion 22A exposed from the upper end of the first layer 8.
  • the first region 14 has a first peak value PA at the upper end of the first layer 8, and has a concentration gradient that gradually decreases toward the lower end of the first layer 8.
  • the first upper end 14b includes a part of the first gradually increasing portion 20A or a part of the first peak portion 21A, and a part of the first gradually increasing portion 20A or a part of the first peak portion 21A may be exposed from the upper end of the first layer 8.
  • the second region 15 has an extension located within the first layer 8 and is connected to the first region 14 within the first layer 8.
  • the concentration gradient formed in the region between the first region 14 and the second region 15 is mitigated by the exposed portion of the first region 14, improving the accuracy of the charge balance.
  • Such a configuration can be obtained by partially removing the upper end of the first layer 8 after the formation of the first region 14 until part or all of the first gradually increasing portion 20A of the first region 14 disappears.
  • the upper end of the first layer 8 may be partially removed by a grinding method.
  • the grinding method may be a mechanical polishing method and/or a chemical mechanical polishing method.
  • the upper end of the first layer 8 is composed of a ground surface, and the first region 14 is exposed from the ground surface.
  • the second layer 9 is laminated on top of the ground surface of the first layer 8.
  • the upper end of the first layer 8 may be partially removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the upper end of the first layer 8 is an etched surface, and the first region 14 is exposed from the etched surface.
  • the second layer 9 is laminated on top of the etched surface of the first layer 8.
  • FIG. 29 is a cross-sectional perspective view showing the column region 12 according to the eighth embodiment.
  • FIG. 30 is a graph showing an example of a concentration gradient in the column region 12 shown in FIG. 29.
  • the column region 12 according to the eighth embodiment has a form obtained by modifying the second region 15 according to the first to seventh embodiments.
  • the first region 14 according to the eighth embodiment may have a form similar to any one of the forms of the first region 14 according to the first to seventh embodiments.
  • the first region 14 according to the seventh embodiment is shown.
  • the second region 15 is exposed from the upper end (first main surface 3) of the second layer 9.
  • the second region 15 does not have part or all of the second gradually increasing portion 20B.
  • Figure 30 shows an example in which the second region 15 does not have all of the second gradually increasing portion 20B and the second peak portion 21B. That is, in this example, the second upper end 15b includes the second gradual portion 22B exposed from the upper end of the second layer 9.
  • the second region 15 has a second peak value PB at the upper end of the second layer 9, and has a concentration gradient that gradually decreases toward the lower end of the second layer 9.
  • the second upper end 15b includes a part of the second gradually increasing portion 20B or a part of the second peak portion 21B, and a part of the second gradually increasing portion 20B or a part of the second peak portion 21B may be exposed from the upper end of the second layer 9.
  • the configuration in which the second region 15 is exposed from the upper end of the second layer 9 is effective when a device structure is formed using the second layer 9 (first main surface 3) and the second region 15 is used to adjust the electrical characteristics of the device structure.
  • Such a configuration can be obtained by partially removing the upper end of the second layer 9 after the formation of the second region 15 until part or all of the second gradually increasing portion 20B of the second region 15 disappears.
  • the upper end (first main surface 3) of the second layer 9 may be partially removed by a grinding method.
  • the grinding method may be a mechanical polishing method and/or a chemical mechanical polishing method.
  • the upper end of the second layer 9 is composed of a ground surface, and the second region 15 is exposed from the ground surface.
  • the upper end (first main surface 3) of the second layer 9 may be partially removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the upper end of the second layer 9 is made of an etched surface, and the second region 15 is exposed from the etched surface.
  • Fig. 31 is a cross-sectional perspective view showing the column region 12 according to the ninth embodiment.
  • Fig. 32 is a cross-sectional perspective view showing the column region 12 according to the tenth embodiment.
  • the stacked portion 7 may have a stacked structure including a buffer layer 26, a first layer 8, and a second layer 9 stacked in this order from the base layer 6 side.
  • the buffer layer 26 may be referred to as a "buffer SiC layer", a "buffer region”, etc.
  • the buffer layer 26 includes SiC single crystals and has n-type conductivity.
  • the buffer layer 26 is stacked on the base layer 6.
  • the buffer layer 26 extends in a layered manner in the horizontal direction, forming the middle part of the chip 2 and forming part of the first to fourth side surfaces 5A to 5D.
  • the buffer layer 26 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the base layer 6.
  • the buffer layer 26 has a lower end and an upper end.
  • the lower end of the buffer layer 26 is the starting point of crystal growth, and the upper end of the buffer layer 26 is the end point of crystal growth. Since the buffer layer 26 is grown continuously from the base layer 6, the lower end of the buffer layer 26 coincides with the upper end of the base layer 6.
  • the boundary between the base layer 6 and the buffer layer 26 is not necessarily visible, and can be indirectly evaluated and/or determined from other configurations and elements.
  • the buffer layer 26 has an off-direction Doff and an off-angle ⁇ off that are approximately the same as the off-direction Doff and off-angle ⁇ off of the base layer 6.
  • the buffer layer 26 has a buffer axis channel CHBu along the stacking direction.
  • the buffer axis channel CHBu is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the buffer layer 26, and is surrounded by atomic rows along the crystal axis that extends in the stacking direction (crystal growth direction).
  • the buffer axis channel CHBu is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a plan view. It is preferable that the buffer axis channel CHBu is a region surrounded by atomic rows along the low-index crystal axis among the crystal axes.
  • the buffer axis channel CHBu is composed of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the buffer axis channel CHBu extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the buffer axis channel CHBu is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the n-type impurity concentration of the buffer layer 26 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the buffer layer 26 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the buffer layer 26 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the buffer layer 26 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the buffer layer 26 has an n-type impurity concentration adjusted with at least one pentavalent element.
  • the n-type impurity concentration of the buffer layer 26 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the buffer layer 26 contains a pentavalent element other than phosphorus.
  • the n-type impurity concentration of the buffer layer 26 is preferably adjusted with at least nitrogen.
  • the buffer layer 26 preferably contains nitrogen and a pentavalent element other than nitrogen.
  • the buffer layer 26 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.
  • the buffer layer 26 has a buffer thickness TBu.
  • the buffer thickness TBu is preferably less than the base thickness TB.
  • the buffer thickness TBu is preferably 1 ⁇ m or more.
  • the buffer thickness TBu is preferably 5 ⁇ m or less.
  • the buffer thickness TBu may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the first layer 8 is stacked on the buffer layer 26, and the second layer 9 is stacked on the first layer 8.
  • the first layer 8 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the buffer layer 26, and has n-type conductivity. Therefore, the first layer 8 has an off-direction Doff and an off-angle ⁇ off that are approximately equal to the off-direction Doff and off-angle ⁇ off of the buffer layer 26.
  • the first axis channel CH1 approximately coincides with the buffer axis channel CHBu.
  • the first thickness T1 of the first layer 8 is preferably greater than the buffer thickness TBu.
  • the first thickness T1 may be less than the buffer thickness TBu.
  • the first thickness T1 may be approximately equal to the buffer thickness TBu.
  • the second thickness T2 of the second layer 9 is preferably greater than the buffer thickness TBu.
  • the second thickness T2 may be less than the buffer thickness TBu.
  • the second thickness T2 may be approximately equal to the buffer thickness TBu.
  • the first region 14 has a shape similar to any one of the shapes of the first region 14 in the first to eighth embodiment examples, and is formed in the first layer 8.
  • the second region 15 has a shape similar to any one of the shapes of the first region 14 in the first to eighth embodiment examples, and is formed in the second layer 9.
  • the first lower end 14a of the first region 14 may be formed with a gap from the lower end to the upper end of the first layer 8, and may face the buffer layer 26 across a part (lower end) of the first layer 8.
  • the entire area of the first region 14 (first gradually increasing portion 20A, first peak portion 21A, first gradually decreasing portion 22A, and first gradually decreasing portion 23A) may be located within the first layer 8.
  • the first lower end 14a may be approximately coincident with the lower end of the first layer 8 and connected to the buffer layer 26.
  • the first lower end 14a may have an extension that crosses the boundary between the buffer layer 26 and the first layer 8 and is located within the buffer layer 26. Since the first axial channel CH1 is approximately coincident with the buffer axial channel CHBu, the extension of the first lower end 14a is formed along the buffer axial channel CHBu within the buffer layer 26.
  • the extension of the first lower end 14a is preferably located on the upper end side of the buffer layer 26 relative to the middle part of the thickness range of the buffer layer 26.
  • the extension of the first lower end 14a includes the first gradually tapering portion 23A.
  • the extension of the first lower end 14a may include a part of the first gradual portion 22A and the first gradually tapering portion 23A.
  • Figure 33 is a cross-sectional perspective view showing a column region 12 according to an eleventh embodiment.
  • a superjunction structure SJ having a stacked structure of three or more layers may be adopted.
  • Figure 33 shows a stacked portion 7 having a three-layer structure and a column region 12 having a three-layer structure.
  • the laminated portion 7 includes an n-type third layer 27 made of single crystal SiC laminated on the second layer 9.
  • the third layer 27 may be referred to as a "third SiC layer", a "third semiconductor layer”, or the like.
  • the second layer 9 forms the middle portion of the chip 2 and forms part of the first to fourth side surfaces 5A to 5D.
  • the third layer 27 extends in a layered manner in the horizontal direction, forms the first main surface 3, and forms part of the first to fourth side surfaces 5A to 5D.
  • the third layer 27 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the second layer 9.
  • the third layer 27 has a lower end and an upper end.
  • the lower end of the third layer 27 is the starting point of crystal growth, and the upper end of the third layer 27 is the end point of crystal growth. Since the third layer 27 is grown continuously from the second layer 9, the lower end of the third layer 27 coincides with the upper end of the second layer 9.
  • the boundary between the second layer 9 and the third layer 27 is not necessarily visible, and can be indirectly evaluated and/or determined from other configurations or elements.
  • the third layer 27 has an off direction Doff and an off angle ⁇ off that are approximately the same as the off direction Doff and the off angle ⁇ off of the second layer 9.
  • the third layer 27 has a third axis channel CH3 along the stacking direction.
  • the third axis channel CH3 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the third layer 27, and is surrounded by atomic rows along the crystal axis that extends in the stacking direction (crystal growth direction).
  • the third axis channel CH3 is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a planar view. It is preferable that the third axis channel CH3 is a region surrounded by atomic rows along the low-index crystal axis among the crystal axes.
  • the third axis channel CH3 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the third axis channel CH3 extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the third axis channel CH3 is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the n-type impurity concentration of the third layer 27 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the third layer 27 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the third layer 27 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the third layer 27 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the third layer 27 has an n-type impurity concentration adjusted by at least one pentavalent element.
  • the n-type impurity concentration of the third layer 27 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the third layer 27 contains a pentavalent element other than phosphorus.
  • the n-type impurity concentration of the third layer 27 is preferably adjusted with at least nitrogen.
  • the third layer 27 preferably contains nitrogen and a pentavalent element other than nitrogen.
  • the third layer 27 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.
  • the third layer 27 has a third thickness T3.
  • the third thickness T3 is preferably less than the base thickness TB.
  • the third thickness T3 may be approximately equal to the second thickness T2, may be greater than or equal to the second thickness T2, or may be less than the second thickness T2.
  • the third thickness T3 may be approximately equal to the first thickness T1, may be greater than or equal to the first thickness T1, or may be less than the first thickness T1.
  • the third thickness T3 is preferably 1 ⁇ m or more.
  • the third thickness T3 is preferably 5 ⁇ m or less.
  • the third thickness T3 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the column region 12 includes a third region 28 formed in the third layer 27.
  • the third regions 28 are formed horizontally at intervals in the third layer 27, and define a plurality of n-type third drift regions 29 each made of a part of the third layer 27.
  • the third regions 28 form a plurality of third pn junctions having charge balance together with the third drift regions 29.
  • the multiple third regions 28 and the third layer 27 form a third superjunction structure SJ3.
  • the state of charge balance means that, for multiple adjacent third regions 28, the depletion layer extending from one third pn junction and the depletion layer extending from the other third pn junction are connected within the multiple third drift regions 29.
  • the third regions 28 are formed in the third layer 27 so as to overlap the second regions 15 in the stacking direction. Specifically, the third regions 28 are arranged at intervals in the third layer 27 in a third array direction Da3 different from the second array direction Da2, and are each formed in a band shape extending in a third extension direction De3 different from the second extension direction De2. In other words, the third regions 28 are formed in stripes extending in the third extension direction De3, and the third drift regions 29 are formed in stripes extending in the third extension direction De3.
  • the multiple third regions 28 intersect with the multiple second regions 15 in a planar view. Therefore, the multiple third drift regions 29 are connected to the multiple second drift regions 17 at the boundary between the second layer 9 and the third layer 27, and together with the multiple first drift regions 16 and the multiple second drift regions 17, form a single three-dimensional lattice-shaped drift region 13.
  • the third array direction Da3 may coincide with the first array direction Da1. Furthermore, the third extension direction De3 may coincide with the first extension direction De1. In other words, the third regions 28 may extend in the same direction as the first regions 14 in a plan view. In this case, the third regions 28 may face the first regions 14 in a one-to-one correspondence in the stacking direction.
  • the multiple third regions 28 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and may face either one or both of the first regions 14 and the first drift region 16 in the stacking direction.
  • the third array direction Da3 may be different from the first array direction Da1.
  • the third extension direction De3 may be different from the first extension direction De1.
  • the multiple third regions 28 may intersect (for example, perpendicular to) the multiple first regions 14 in a planar view.
  • the multiple third regions 28 are drawn from the active region 10 to the peripheral region 11. That is, the multiple third regions 28 are drawn from a portion of the third layer 27 located within the active region 10 to a portion of the third layer 27 located within the peripheral region 11.
  • the multiple third regions 28 are also arranged at intervals in the third array direction Da3 in the peripheral region 11, and are each formed in a band shape extending in the third extension direction De3.
  • the multiple third regions 28 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each has a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).
  • the portions of the multiple third regions 28 exposed from the first side surface 5A form multiple third marks (not shown) on the first side surface 5A, and the portions of the multiple third regions 28 exposed from the third side surface 5C form multiple third marks on the third side surface 5C.
  • the multiple third regions 28 include either or both of multiple third marks as exposed portions exposed from the first side surface 5A and multiple third marks as exposed portions exposed from the third side surface 5C.
  • the multiple third marks are each formed using a portion (exposed portion) of the multiple third regions 28.
  • the multiple third marks partition multiple third spaces on the first side surface 5A (third side surface 5C).
  • the multiple third marks and multiple third spaces are formed on the first side surface 5A (third side surface 5C) in the same layout as the multiple first marks Mk1 and multiple first spaces Sp1.
  • the description of the multiple first marks Mk1 applies to the description of the multiple third marks (multiple third spaces).
  • the layout (exposed locations and arrangement direction) of the multiple third marks on the first side 5A (third side 5C) is appropriately adjusted depending on the layout (third arrangement direction Da3 and third extension direction De3) of the multiple third regions 28.
  • the multiple third marks do not necessarily need to be formed continuously from the main body portions of the multiple third regions 28, but may be formed as separate portions separated from the main body portions of the multiple third regions 28. In this case, it is preferable that the multiple third marks are separated from the main body portions of the multiple third regions 28 in the outer circumferential region 11.
  • the explanation for the third region 28 also applies to the third mark (the portion of the third region 28 exposed from the first side surface 5A/third side surface 5C).
  • the multiple third regions 28 are made up of channeling regions (third channeling regions) that extend along the third axis channel CH3 in the third layer 27 in a cross-sectional view.
  • the third regions 28 are impurity regions that are introduced parallel or nearly parallel to the region (third axis channel CH3) surrounded by the atomic rows along the low-index crystal axis in the third layer 27, and extend at an angle with respect to the first main surface 3.
  • the third regions 28 each have a third lower end 28a at the lower end of the third layer 27 and a third upper end 28b at the upper end of the third layer 27.
  • the third lower end 28a is located in a region on the lower end side of the third layer 27 relative to the intermediate part of the thickness range of the third layer 27, and the third upper end 28b is located in a region on the upper end side of the third layer 27 relative to the intermediate part of the thickness range of the third layer 27.
  • the third regions 28 each consist of a single impurity region having a thickness (depth) that crosses the intermediate part of the third layer 27 along the third axial channel CH3.
  • the third lower end 28a may be formed with a gap from the lower end of the third layer 27 toward the upper end, and may face the second layer 9 across a portion (lower end) of the third layer 27.
  • the third lower end 28a may be substantially coincident with the lower end of the third layer 27 and connected to the second layer 9.
  • the distance between the lower end of the third layer 27 and the third lower end 28a may be 0 ⁇ m or more and 2 ⁇ m or less.
  • the distance between the lower end of the third layer 27 and the third lower end 28a may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the third lower end 28a may have an extension that crosses the boundary between the second layer 9 and the third layer 27 and is located within the second layer 9.
  • the thickness of the extension of the third lower end 28a based on the upper end of the second layer 9 may be greater than 0 ⁇ m and less than 2 ⁇ m.
  • the thickness of the extension of the third lower end 28a may have a value that belongs to any one of the following ranges: greater than 0 ⁇ m and less than 0.5 ⁇ m, 0.5 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, and 1.5 ⁇ m to 2 ⁇ m.
  • the third upper end 28b may be formed at a distance from the upper end of the third layer 27 (i.e., the first main surface 3) toward the lower end, and may face the upper end of the third layer 27 across a portion (upper end) of the third layer 27.
  • the third upper end 28b may be exposed from the upper end of the third layer 27 (i.e., the first main surface 3).
  • the distance between the upper end of the third layer 27 and the third upper end 28b may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the distance between the upper end of the third layer 27 and the third upper end 28b may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the plurality of third regions 28 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration (peak value) of the third regions 28 may be equal to or more than the p-type impurity concentration (peak value) of the first region 14.
  • the p-type impurity concentration (peak value) of the third regions 28 may be less than the p-type impurity concentration (peak value) of the first region 14. It is preferable that the p-type impurity concentration (peak value) of the third regions 28 is approximately equal to the p-type impurity concentration (peak value) of the first region 14.
  • the p-type impurity concentration of the third region 28 is preferably adjusted by at least one trivalent element. It is particularly preferable that the p-type impurity concentration of the third region 28 is adjusted by a trivalent element that is heavier than carbon. In other words, the third region 28 preferably contains a trivalent element other than boron (at least one of aluminum, gallium, and indium). In this embodiment, the p-type impurity concentration of the third region 28 is adjusted by aluminum.
  • the third regions 28 each have a third width W3.
  • the third width W3 is a width along the third arrangement direction Da3. It is preferable that the third width W3 is less than the third thickness T3 of the third layer 27. Of course, the third width W3 may be equal to or greater than the third thickness T3. It is preferable that the third width W3 is less than the first thickness T1 of the first layer 8. Of course, the third width W3 may be equal to or greater than the first thickness T1. It is preferable that the third width W3 is less than the second thickness T2 of the second layer 9. Of course, the third width W3 may be equal to or greater than the second thickness T2.
  • the third width W3 may be greater than or equal to the first width W1 of the first region 14, or less than the first width W1. It is preferable that the third width W3 is approximately equal to the first width W1.
  • the third width W3 may be greater than or equal to the second width W2 of the second region 15, or less than the second width W2. It is preferable that the third width W3 is approximately equal to the second width W2.
  • the third width W3 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the third width W3 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the third width W3 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the multiple third regions 28 each have a third region thickness TR3.
  • the third region thickness TR3 may be less than the third thickness T3 of the third layer 27.
  • the third region thickness TR3 may be greater than the third thickness T3.
  • the third region thickness TR3 may be approximately equal to the third thickness T3.
  • the third region thickness TR3 may be less than the first thickness T1 of the first layer 8. The third region thickness TR3 may be greater than the first thickness T1. The third region thickness TR3 may be approximately equal to the first thickness T1. The third region thickness TR3 may be less than the second thickness T2 of the second layer 9. The third region thickness TR3 may be greater than the second thickness T2. The third region thickness TR3 may be approximately equal to the second thickness T2.
  • the third region thickness TR3 is preferably 1 ⁇ m or more.
  • the third region thickness TR3 is preferably 5 ⁇ m or less.
  • the third region thickness TR3 may have a value that falls within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the third width W3 is less than the third thickness T3 of the third layer 27, and that the third region thickness TR3 is greater than the third width W3.
  • each of the multiple third regions 28 has a third aspect ratio TR3/W3 that extends in a vertically elongated columnar shape along the third axial channel CH3.
  • the third aspect ratio TR3/W3 is the ratio of the third region thickness TR3 to the third width W3.
  • the third region thickness TR3 is greater than the third thickness T3.
  • the third aspect ratio TR3/W3 may be greater than 1 and less than or equal to 100.
  • the third regions 28 are formed at intervals of a third pitch P3 in the third arrangement direction Da3. It is preferable that the third pitch P3 is less than the third thickness T3 of the third layer 27. Of course, the third pitch P3 may be equal to or greater than the third thickness T3. It is preferable that the third pitch P3 is less than the first thickness T1 of the first layer 8. Also, it is preferable that the third pitch P3 is less than the second thickness T2 of the second layer 9. Of course, the third pitch P3 may be equal to or greater than the first thickness T1. Also, the third pitch P3 may be equal to or greater than the second thickness T2.
  • the third pitch P3 may be approximately equal to the first pitch P1 or may be different from the first pitch P1.
  • the third pitch P3 may be greater than the first pitch P1 or may be smaller than the first pitch P1.
  • the third pitch P3 may be approximately equal to the second pitch P2 or may be different from the second pitch P2.
  • the third pitch P3 may be greater than the second pitch P2 or may be smaller than the second pitch P2.
  • the third pitch P3 may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the third pitch P3 may have a value that belongs to any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the third pitch P3 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • FIG. 34 is a cross-sectional perspective view showing the column region 12 according to the twelfth embodiment.
  • the stacked portion 7 in this example includes a top layer 30 of n-type single crystalline SiC stacked on the second layer 9.
  • the top layer 30 is formed to separate the first main surface 3 from the column region 12.
  • the top layer 30 also forms at least a part of the region between the first main surface 3 and the second upper ends 15b of the multiple second regions 15.
  • the top layer 30 may be considered to be a portion that forms the upper ends of the second layer 9.
  • the top layer 30 has an n-type conductivity, but the conductivity type of the top layer 30 can be adjusted as appropriate depending on the properties of the device structure formed on the first main surface 3. Therefore, the conductivity type of the top layer 30 does not necessarily need to be limited to n-type, and may be p-type.
  • the top layer 30 is laminated on the second layer 9.
  • the top layer 30 extends in a layered manner in the horizontal direction, forming the first main surface 3 and forming parts of the first to fourth side surfaces 5A to 5D.
  • the top layer 30 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the second layer 9.
  • the top layer 30 is grown continuously from the second layer 9, so that the bottom end of the top layer 30 coincides with the top end of the second layer 9.
  • the boundary between the top layer 30 and the second layer 9 is not necessarily visible, and can be indirectly evaluated and/or determined from other configurations or elements.
  • the top layer 30 has an off-direction Doff and an off-angle ⁇ off that are approximately the same as the off-direction Doff and the off-angle ⁇ off of the second layer 9.
  • the top layer 30 has a top axis channel CHT along the stacking direction.
  • the top axis channel CHT is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the top layer 30, and is surrounded by atomic rows along the crystal axis that extends in the stacking direction (crystal growth direction).
  • the top axis channel CHT is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a planar view. It is preferable that the top axis channel CHT is a region surrounded by atomic rows along the low-index crystal axis among the crystal axes.
  • the top axis channel CHT is composed of a region surrounded by atomic rows along the c-axis of the SiC single crystal.
  • the top axis channel CHT extends along the c-axis and has an off-direction Doff and an off-angle ⁇ off.
  • the top axis channel CHT is inclined from the vertical axis toward the off-direction Doff by the off-angle ⁇ off.
  • the n-type impurity concentration of the top layer 30 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the top layer 30 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the n-type impurity concentration of the top layer 30 may be approximately equal to the n-type impurity concentration of the first layer 8 (second layer 9).
  • the n-type impurity concentration of the top layer 30 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the top layer 30 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the top layer 30 has an n-type impurity concentration adjusted by at least one pentavalent element.
  • the n-type impurity concentration of the top layer 30 may be adjusted by at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the top layer 30 contains a pentavalent element other than phosphorus.
  • the n-type impurity concentration of the top layer 30 is preferably adjusted with at least nitrogen.
  • the top layer 30 preferably contains nitrogen and a pentavalent element other than nitrogen.
  • the top layer 30 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.
  • the top layer 30 has a top thickness TT.
  • the top thickness TT is preferably less than the base thickness TB.
  • the top thickness TT is preferably less than the first thickness T1 (second thickness T2).
  • the top thickness TT may be greater than or equal to the first thickness T1 (second thickness T2).
  • the top thickness TT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the top thickness TT may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • FIG. 35 is a plan view showing a main portion of the active region 10.
  • FIG. 36 is a cross-sectional perspective view showing a gate structure 35 according to the first embodiment.
  • FIG. 36 illustrates a configuration in which a column region 12 according to the second embodiment is applied to a column region 12 according to the first basic embodiment.
  • FIG. 36 may also apply a configuration in which any one or more of the column regions 12 according to the first to twelfth embodiments are applied to any one of the column regions 12 according to the first to third basic embodiments.
  • the SiC semiconductor device 1A includes a MIS structure 31 (Metal Insulator Semiconductor structure) as an example of a device structure formed in the active region 10.
  • the MIS structure 31 may also be referred to as a "field effect transistor structure.”
  • the MIS structure 31 is formed in the second layer 9 (first main surface 3).
  • the MIS structure 31 is formed in the top layer 30 (first main surface 3).
  • the form in this case can be obtained by replacing "second layer 9" with "top layer 30" as necessary in the following description.
  • the following configuration is described as a component of the SiC semiconductor device 1A, but is also a component of the MIS structure 31.
  • the SiC semiconductor device 1A includes a plurality of p-type body regions 32 formed in the active region 10.
  • the plurality of body regions 32 are formed in the surface layer portion of the first main surface 3 so as to overlap the plurality of second regions 15 in the stacking direction.
  • the plurality of body regions 32 are arranged at intervals in the second array direction Da2 so as to overlap the plurality of second regions 15 in a one-to-one correspondence in the stacking direction, and are each formed in a band shape extending in the second extension direction De2.
  • the second array direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X).
  • the array direction and extension direction of the multiple body regions 32 are changed according to the second array direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second array direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction.
  • the second array direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.
  • the body regions 32 are each formed in a region between the first main surface 3 and the second upper ends 15b of the second regions 15.
  • the body regions 32 are preferably formed on the first main surface 3 side relative to the intermediate portion of the thickness range of the second layer 9, and are preferably exposed from the first main surface 3.
  • the body regions 32 are preferably connected to the corresponding second regions 15 (second upper ends 15b).
  • the body regions 32 are each formed to be wider than the second region 15 directly below, and are formed at intervals from the adjacent second regions 15 toward the second region 15 directly below.
  • the body regions 32 expose a portion of the second drift region 17 from the region of the first main surface 3 between the adjacent second regions 15.
  • the body regions 32 are made of random impurity regions introduced into the surface layer of the second layer 9 by a random implantation method into the second layer 9 (see also FIG. 14). Therefore, the body regions 32 have a thickness in the direction along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the body regions 32 is less than the first region thickness TR1 of the first region 14.
  • the body regions 32 unlike the second region 15 etc., do not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more, and have a concentration gradient including a gradually increasing portion 20, a peak portion 21 and a gradually decreasing portion 23 within a range of 0.5 ⁇ m.
  • the body regions 32 may have a peak value of a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the plurality of body regions 32 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the body region 32 may be the same as the trivalent element of the second region 15, etc., or may be a different species from the trivalent element of the second region 15, etc.
  • the trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium.
  • the SiC semiconductor device 1A includes one or more n-type source regions 33 formed in the surface layer portion of the body regions 32 in the active region 10.
  • the source regions 33 (two in this embodiment) are formed at intervals in the surface layer portion of each body region 32.
  • the source regions 33 have an n-type impurity concentration higher than the n-type impurity concentration of the second layer 9 (the second drift regions 17).
  • the source regions 33 may have a peak n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the multiple source regions 33 may each extend in a band shape along the extension direction of the corresponding body region 32. Of course, the multiple source regions 33 may be formed at intervals along the extension direction of the corresponding body region 32. The multiple source regions 33 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the periphery of the corresponding body region 32. The multiple source regions 33, together with the multiple second drift regions 17, define a channel (current path) along the first main surface 3 at the periphery of the body region 32.
  • the SiC semiconductor device 1A includes one or more p-type contact regions 34 formed in the surface layer of each of the body regions 32 in the active region 10.
  • the contact region 34 may be referred to as a "backgate region.”
  • one contact region 34 is formed in a region between adjacent source regions 33 in the surface layer of each body region 32.
  • the plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32.
  • the p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second regions 15.
  • the plurality of contact regions 34 may have a p-type impurity concentration (peak value) of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the multiple contact regions 34 may each extend in a band shape along the extension direction of the corresponding body region 32. Of course, the multiple contact regions 34 may be formed at intervals along the extension direction of the corresponding body region 32. The multiple contact regions 34 are formed at intervals from the bottom of the corresponding body region 32 toward the first main surface 3, and are formed at intervals inward from the peripheral portion of the corresponding body region 32.
  • the SiC semiconductor device 1A includes multiple gate structures 35 of a planar electrode type arranged on the first main surface 3 in the active region 10.
  • the gate structures 35 may be referred to as "planar gate structures.”
  • the multiple gate structures 35 are arranged at intervals on the first main surface 3 so as to overlap at least one body region 32 (channel) in the stacking direction.
  • a gate potential is applied to the multiple gate structures 35 as a control potential.
  • the multiple gate structures 35 control the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.
  • the multiple gate structures 35 are arranged at intervals in the second array direction Da2 and are each formed in a strip shape extending in the second extension direction De2.
  • the second array direction Da2 is the m-axis direction (second direction Y)
  • the second extension direction De2 is the a-axis direction (first direction X).
  • the arrangement direction and extension direction of the multiple gate structures 35 are changed according to the second arrangement direction Da2 and second extension direction De2 of the multiple second regions 15 (body regions 32). Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction. Also, the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple gate structures 35 are arranged offset from the multiple second regions 15 toward the multiple second drift regions 17, and overlap the multiple second drift regions 17 in a one-to-one correspondence in the stacking direction.
  • the multiple gate structures 35 are each arranged to straddle two adjacent body regions 32, and each cover the multiple source regions 33 located in one and the other body regions 32.
  • Each of the multiple gate structures 35 has a stacked structure including a gate insulating film 36 arranged on the first main surface 3 and a gate electrode 37 arranged on the gate insulating film 36.
  • the gate insulating film 36 may include a silicon oxide film.
  • the gate electrode 37 may include conductive polysilicon.
  • Either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as to partially overlap the second region 15 in the stacking direction.
  • either or both of the gate insulating film 36 and the gate electrode 37 may be arranged so as not to partially overlap the second region 15 in the stacking direction.
  • Figure 37 is a perspective view showing the configuration of the outer peripheral region 11.
  • Figure 38A is a cross-sectional view in the first direction X showing a main part of the outer peripheral region 11.
  • Figure 38B is a cross-sectional view in the second direction Y showing a main part of the outer peripheral region 11.
  • the column region 12 is omitted from Figure 37.
  • the SiC semiconductor device 1A includes at least one (preferably 2 to 20) p-type field region 38 formed in the surface layer of the first main surface 3 in the peripheral region 11.
  • the number of the multiple field regions 38 is typically 4 to 8.
  • the multiple field regions 38 are formed in an electrically floating state and relieve the electric field within the chip 2 at the periphery of the first main surface 3.
  • the number, width, depth, p-type impurity concentration, etc. of the field regions 38 are arbitrary and can take various values depending on the electric field to be relieved.
  • the multiple field regions 38 are formed at intervals in the region between the periphery of the chip 2 and the active region 10.
  • the multiple field regions 38 are formed in a band shape extending along the active region 10 in a planar view.
  • Each of the multiple field regions 38 has a portion extending in a band shape in the first direction X and a portion extending in a band shape in the second direction Y.
  • the multiple field regions 38 are formed in a ring shape (specifically, a square ring shape) surrounding the active region 10 in a planar view.
  • the multiple field regions 38 overlap the column regions 12 in the stacking direction in the outer periphery region 11. That is, the multiple field regions 38 are formed in a region above multiple intersections of the multiple first regions 14 and the multiple second regions 15.
  • the multiple field regions 38 intersect with the multiple second regions 15 in the portion extending in the first extension direction De1 in a plan view, and intersect with the multiple first regions 14 in the portion extending in the second extension direction De2.
  • the multiple field regions 38 are formed in the second layer 9 at intervals from the lower end of the second layer 9 toward the first main surface 3, and each form a pn junction with the second layer 9. It is preferable that the multiple field regions 38 have bottoms located on the first main surface 3 side relative to the intermediate part of the thickness range of the second layer 9. It is particularly preferable that the bottoms of the multiple field regions 38 are located on the first main surface 3 side relative to the intermediate part of the thickness range of the second region 15.
  • the bottoms of the multiple field regions 38 may be located closer to the second lower end 15a of the second region 15 than the depth position of the second upper end 15b of the second region 15.
  • the multiple field regions 38 may be connected to the multiple second regions 15 in the portion extending along the second extension direction De2.
  • the multiple field regions 38 may be formed at a horizontal distance from the multiple second regions 15 in the portion extending along the second extension direction De2, and may not be connected to the multiple second regions 15.
  • the bottoms of the multiple field regions 38 may be located closer to the first main surface 3 than the depth position of the second upper end 15b of the second region 15.
  • the bottoms of the multiple field regions 38 may be located closer to the first main surface 3 than the depth position of the second upper end 15b of the second region 15.
  • the field regions 38 may have a thickness approximately equal to the thickness of the body regions 32. In this case, the field regions 38 may be formed simultaneously with the body regions 32. Of course, the field regions 38 may have a thickness greater than the thickness of the body regions 32. The field regions 38 may also have a thickness less than the thickness of the body regions 32.
  • the multiple field regions 38 are made of random impurity regions introduced into the surface layer of the second layer 9 by a random implantation method for the second layer 9 (see also FIG. 14). Therefore, the multiple field regions 38 have a thickness in the direction along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the multiple field regions 38 is less than the first region thickness TR1 of the first region 14.
  • the field regions 38 unlike the second region 15 etc., do not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more, and have a concentration gradient in a range of 0.5 ⁇ m that includes a gradually increasing portion 20, a peak portion 21 and a gradually decreasing portion 23.
  • the field regions 38 may have a peak value of a p-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the p-type impurity concentration of the field region 38 may be approximately equal to the p-type impurity concentration of the body region 32.
  • the p-type impurity concentration of the multiple field regions 38 may be higher than the p-type impurity concentration of the multiple body regions 32.
  • the p-type impurity concentration of the multiple field regions 38 may be lower than the p-type impurity concentration of the multiple body regions 32.
  • the p-type impurity concentration of the multiple field regions 38 is preferably adjusted by at least one type of trivalent element.
  • the trivalent element of the field region 38 may be the same type as the trivalent element of the second region 15, etc., or may be a different type from the trivalent element of the second region 15, etc.
  • the trivalent element of the field region 38 may be at least one type of boron, aluminum, gallium, and indium.
  • the field regions 38 preferably have a width different from the second width W2 of the second region 15 (the first width W1 of the first region 14). In other words, the electric field relaxation effect of the field regions 38 is preferably adjusted separately from the column region 12.
  • the width of the multiple field regions 38 is greater than the second width W2 (first width W1) of the second region 15.
  • the width of the multiple field regions 38 may be smaller than the second width W2 (first width W1).
  • the width of the column region 12 may be approximately equal to the second width W2 (first width W1).
  • the multiple field regions 38 are preferably formed at a pitch different from the second pitch P2 of the second region 15 (the first pitch P1 of the first region 14). It is particularly preferable that the pitch of the multiple field regions 38 is larger than the second pitch P2 (the first pitch P1). Of course, the pitch of the multiple field regions 38 may be smaller than the second pitch P2 (the first pitch P1). Also, the pitch of the multiple field regions 38 may be approximately equal to the second pitch P2 (the first pitch P1).
  • the SiC semiconductor device 1A includes an interlayer insulating film 40 covering the first main surface 3.
  • the interlayer insulating film 40 may be referred to as an "insulating film,” an "interlayer film,” an “intermediate insulating film,” or the like.
  • the interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 41 includes a silicon oxide film made of an oxide of the chip 2 (second layer 9).
  • the first insulating film 41 selectively covers the first main surface 3 in the active region 10 and the peripheral region 11.
  • the first insulating film 41 covers the region outside the gate insulating film 36 in the active region 10 and is connected to the gate insulating film 36.
  • the first insulating film 41 covers a plurality of field regions 38 in the peripheral region 11.
  • the first insulating film 41 is continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D). Therefore, the first insulating film 41 overlaps with the second marks Mk2 (second regions 15) on the periphery of the first main surface 3.
  • the first insulating film 41 may be formed at a distance inward from the periphery of the first main surface 3, exposing the second layer 9 from the periphery of the first main surface 3.
  • the second insulating film 42 is laminated on the first insulating film 41.
  • the second insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the interlayer insulating film 40 preferably includes a silicon oxide film.
  • the second insulating film 42 covers the first main surface 3 in the active region 10 and the peripheral region 11, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 covers the gate structures 35 in the active region 10.
  • the second insulating film 42 covers the field regions 38 in the peripheral region 11, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 is continuous with the periphery of the first main surface 3.
  • the second insulating film 42 may overlap the second marks Mk2 (the second regions 15) on the periphery of the first main surface 3, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 may be formed at a distance inward from the periphery of the first main surface 3, and may expose the periphery of the first main surface 3 together with the first insulating film 41.
  • the SiC semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40.
  • the plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (gate electrodes 37), and a plurality of contact openings 43 that expose a plurality of source regions 33.
  • the plurality of contact openings 43 for the source regions 33 are formed in the regions between the plurality of adjacent gate structures 35, and expose the plurality of source regions 33 and the plurality of contact regions 34.
  • the SiC semiconductor device 1A includes a gate pad 45 disposed on the interlayer insulating film 40.
  • the gate pad 45 is an electrode to which a gate potential is applied from the outside.
  • the gate pad 45 may be referred to as a "gate pad electrode", a "first pad electrode”, etc.
  • the gate pad 45 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.
  • the gate pad 45 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10.
  • the gate pad 45 may be disposed at a distance from the peripheral region 11 toward the active region 10.
  • the gate pad 45 is disposed on the periphery of the active region 10 in a plan view.
  • the gate pad 45 is arranged in a region along the center of the first side surface 5A on the periphery of the active region 10.
  • the gate pad 45 may be arranged in a region along any of the centers of the first to fourth side surfaces 5A to 5D.
  • the gate pad 45 may be arranged at any corner of the active region 10 in a planar view.
  • the gate pad 45 may be arranged in the center of the active region 10 in a planar view.
  • the gate pad 45 is formed in a rectangular shape in a planar view.
  • the SiC semiconductor device 1A includes at least one gate wiring 46 (multiple in this embodiment) that is drawn from the gate pad 45 onto the interlayer insulating film 40.
  • the gate wiring 46 may be referred to as a "wiring", "wiring electrode”, etc.
  • the multiple gate wirings 46 may have a layered structure including a Ti-based metal film and an Al-based metal film that are layered in this order from the interlayer insulating film 40 side.
  • the multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.
  • the first gate wiring 46A is pulled out from the gate pad 45 toward the second side surface 5B and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) a portion (specifically, one end) of the multiple gate structures 35.
  • the first gate wiring 46A penetrates the interlayer insulating film 40 via multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35.
  • the second gate wiring 46B is pulled out from the gate pad 45 toward the fourth side surface 5D and extends in a line along the periphery of the active region 10 so as to intersect (specifically, perpendicular to) a portion (specifically, the other end) of the multiple gate structures 35.
  • the second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other end of the multiple gate structures 35.
  • the SiC semiconductor device 1A includes a source pad 47 disposed on the interlayer insulating film 40 at a distance from the gate pad 45 and the gate wiring 46.
  • the source pad 47 is an electrode to which a source potential is applied from the outside.
  • the source pad 47 may be referred to as a "source pad electrode", a "second pad electrode”, etc.
  • the source pad 47 may have a layered structure including a Ti-based metal film and an Al-based metal film layered in this order from the interlayer insulating film 40 side.
  • the source pad 47 is disposed on a portion of the interlayer insulating film 40 that covers the active region 10.
  • the source pad 47 may be disposed at a distance from the peripheral region 11 toward the active region 10.
  • the source pad 47 is formed in a polygonal shape having a recess that is recessed along the gate pad 45 in a plan view.
  • the source pad 47 may also be formed in a rectangular shape in a plan view.
  • the source pad 47 penetrates the interlayer insulating film 40 through a plurality of contact openings 43, and is electrically connected to a plurality of body regions 32, a plurality of source regions 33, and a plurality of contact regions 34. In other words, the source pad 47 is electrically connected to the column region 12 through a plurality of body regions 32.
  • the SiC semiconductor device 1A includes a drain pad 48 covering the second main surface 4.
  • the drain pad 48 is an electrode to which a drain potential is applied from the outside.
  • the drain pad 48 may be referred to as a "drain pad electrode", a “third pad electrode”, etc.
  • the drain pad 48 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.
  • the drain pad 48 is electrically connected to the first layer 8 (the multiple first drift regions 16) and the second layer 9 (the multiple second drift regions 17) via the base layer 6.
  • the drain pad 48 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2.
  • the drain pad 48 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.
  • the breakdown voltage that can be applied between the source pad 47 and the drain pad 48 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less.
  • the breakdown voltage may have a value that belongs to any one of the following ranges: 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.
  • FIG. 39 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment.
  • the multiple gate structures 35 according to the first embodiment extend along the second extension direction De2 of the multiple second regions 15.
  • the multiple gate structures 35 according to the second embodiment extend in a direction other than the second extension direction De2 so as to intersect with the multiple second regions 15.
  • the multiple body regions 32 described above extend in a direction other than the second extension direction De2 so as to intersect with the multiple second regions 15 in the stacking direction.
  • the multiple body regions 32 are arranged at intervals in the first array direction Da1 of the first region 14 and extend in the first extension direction De1 of the first region 14.
  • the multiple body regions 32 are perpendicular to the multiple second regions 15.
  • the first array direction Da1 is the a-axis direction (first direction X)
  • the first extension direction De1 is the m-axis direction (second direction Y).
  • the multiple body regions 32 may face the multiple first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each body region 32 may face the multiple first regions 14 in the stacking direction. The multiple body regions 32 may face the multiple first drift regions 16 in a one-to-one correspondence in the stacking direction.
  • each body region 32 may face multiple first drift regions 16 in the stacking direction.
  • the multiple body regions 32 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.
  • the arrangement direction and extension direction of the multiple body regions 32 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the arrangement direction of the multiple body regions 32 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2.
  • the extension direction of the multiple body regions 32 may be a direction other than the first extension direction De1 and the second extension direction De2.
  • the multiple body regions 32 may intersect both the multiple first regions 14 and the multiple second regions 15 in a planar view. In this case, a configuration in which the arrangement direction of the multiple body regions 32 is one of the a-axis direction and the m-axis direction and the extension direction of the multiple body regions 32 is the other of the a-axis direction and the m-axis direction is not prevented.
  • the angle (absolute value) between the extension direction of the body region 32 and the second extension direction De2 may be greater than 0° and less than 90°.
  • the angle (absolute value) of the body region 32 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the angle (absolute value) of the body region 32 may be set to a value belonging to any one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the aforementioned multiple source regions 33 and multiple contact regions 34 are formed along the extension direction of the corresponding body region 32, and face the multiple second regions 15 and multiple second drift regions 17, respectively, across a portion of the body region 32 that corresponds to the stacking direction.
  • the multiple gate structures 35 are arranged at intervals in the first array direction Da1 of the first region 14 and extend in the first extension direction De1 of the first region 14. In other words, the multiple gate structures 35 are perpendicular to the multiple second regions 15.
  • the first array direction Da1 is the a-axis direction (first direction X)
  • the first extension direction De1 is the m-axis direction (second direction Y).
  • the multiple gate structures 35 may face the multiple first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may face the multiple first regions 14 in the stacking direction. The multiple gate structures 35 may face the multiple first drift regions 16 in a one-to-one correspondence in the stacking direction.
  • each gate structure 35 may face multiple first drift regions 16 in the stacking direction.
  • the multiple gate structures 35 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.
  • the arrangement direction and extension direction of the multiple gate structures 35 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14 (body regions 32). Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the arrangement direction of the multiple gate structures 35 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2.
  • the extension direction of the multiple gate structures 35 may be a direction other than the first extension direction De1 and the second extension direction De2.
  • the multiple gate structures 35 may intersect both the multiple first regions 14 and the multiple second regions 15 in a planar view. In this case, a configuration in which the arrangement direction of the multiple gate structures 35 is one of the a-axis direction and the m-axis direction, and the extension direction of the multiple gate structures 35 is the other of the a-axis direction and the m-axis direction, is not prevented.
  • the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°.
  • the angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the multiple gate structures 35 are each arranged to straddle two adjacent body regions 32, and each cover the multiple source regions 33 located in one and the other body region 32. In addition, the multiple gate structures 35 each face the multiple second regions 15 (second regions 15) and the multiple second drift regions 17 in the stacking direction.
  • Figure 40 is a schematic diagram showing a wafer 50 used in the manufacture of the SiC semiconductor device 1A.
  • the wafer 50 is a substrate for the base layer 6 and contains a SiC single crystal.
  • the wafer 50 is formed in a flat disk shape. Of course, the wafer 50 may also be formed in a flat rectangular parallelepiped shape.
  • the wafer 50 has a first wafer main surface 51 on one side, a second wafer main surface 52 on the other side, and a wafer side surface 53 connecting the first wafer main surface 51 and the second wafer main surface 52.
  • the first wafer main surface 51 corresponds to the upper end of the base layer 6, and the second wafer main surface 52 corresponds to the lower end of the base layer 6.
  • the first wafer main surface 51 and the second wafer main surface 52 are formed by the c-plane of the SiC single crystal.
  • the first wafer main surface 51 is formed by the silicon surface of the SiC single crystal, and the second wafer main surface 52 is formed by the carbon surface of the SiC single crystal.
  • the wafer 50 (the first wafer main surface 51 and the second wafer main surface 52) has the off-direction Doff and off-angle ⁇ off described above.
  • the wafer 50 has a mark 54 on the wafer side surface 53 that indicates the crystal orientation of the SiC single crystal.
  • the mark 54 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape (e.g., a tapered shape) toward the center of the first wafer main surface 51 in a plan view.
  • the mark 54 may include either or both of a first orientation flat extending in the m-axis direction and a second orientation flat extending in the a-axis direction.
  • the mark 54 may include either or both of an orientation notch recessed in the m-axis direction and an orientation notch recessed in the a-axis direction.
  • Figure 40 shows an orientation flat extending in the a-axis direction in a plan view.
  • a plurality of device regions 55 and a plurality of cutting lines 56 are set on the wafer 50 by alignment marks or the like.
  • Each device region 55 corresponds to the SiC semiconductor device 1A.
  • Each of the plurality of device regions 55 is set to have a rectangular shape in a plan view.
  • the multiple device regions 55 are set in a matrix along the first direction X and the second direction Y in a plan view.
  • the multiple device regions 55 are each set at intervals inward from the periphery of the first wafer main surface 51 in a plan view.
  • the multiple cutting lines 56 are set in a lattice extending along the first direction X and the second direction Y to partition the multiple device regions 55.
  • FIG. 41 is a flow chart showing an example of a method for manufacturing a SiC semiconductor device 1A.
  • FIG. 42A to FIG. 42H are cross-sectional perspective views showing an example of a method for manufacturing a SiC semiconductor device 1A.
  • FIG. 43A to FIG. 43B are schematic diagrams for explaining the crystal orientation measurement process.
  • FIG. 44A to FIG. 44B are schematic diagrams for explaining the ion implantation process.
  • FIG. 42A to FIG. 42H show cross-sectional perspective views of a portion of an active region 10 of one device region 55.
  • step S1 in FIG. 41 the aforementioned wafer 50 preparation process is performed (step S1 in FIG. 41).
  • a determination process is performed as to whether or not an n-type buffer layer 26 (see FIG. 31 and FIG. 32) formation process is performed (step S2 in FIG. 41). If a buffer layer 26 is to be formed (step S2 in FIG. 41: YES), the buffer layer 26 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth (step S3 in FIG. 41). If a buffer layer 26 formation process is not performed (step S2 in FIG. 41: NO), this process is omitted.
  • a step of forming an n-type first layer 8 is performed (step S4 in FIG. 41). If the step of forming the buffer layer 26 is omitted, the first layer 8 is formed starting from the first wafer main surface 51 (wafer 50) by epitaxial growth. If the buffer layer 26 is formed, the first layer 8 is formed starting from the buffer layer 26 by epitaxial growth. In this case, the first layer 8 may be formed by continuous crystal growth from the buffer layer 26 using the step of forming the buffer layer 26 after the step of forming the buffer layer 26.
  • the crystal orientation of the first layer 8 includes a process for measuring the off angle ⁇ off of the first layer 8. In other words, this process includes a process for measuring the crystal orientation of the first axis channel CH1 of the first layer 8.
  • the wafer 50 is cut from an ingot (SiC ingot), which is a crystalline mass, but there is a risk that an error will occur in the off-angle ⁇ off due to process error. If an error occurs in the off-angle ⁇ off of the wafer 50, a process error will also occur in the off-angle ⁇ off of the first layer 8, which will become an obstacle during the channeling implantation process. Therefore, it is preferable that data (information) on the off-angle ⁇ off is obtained prior to the channeling implantation process, and the channeling implantation process is carried out based on the data (information) on the off-angle ⁇ off.
  • the crystal orientation of the first layer 8 is measured by an X-ray diffraction method (the so-called ⁇ -2 ⁇ measurement method) using an X-ray diffraction device 57.
  • the X-ray diffraction device 57 may also be referred to as an "XRD (X-ray Diffraction) device.”
  • the X-ray diffraction device 57 includes an irradiation unit 58 and a detection unit 59, and performs the rocking curve measurement method.
  • the irradiation unit 58 irradiates the incident X-ray L1 having a predetermined incident angle ⁇ with respect to the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).
  • the incident angle ⁇ is defined as the angle between the incident X-ray L1 and the upper end of the first layer 8 (the first wafer main surface 51 of the wafer 50).
  • the detector 59 is positioned at an angular position of diffraction angle 2 ⁇ ( ⁇ is the Bragg angle) relative to the irradiation position of the incident X-rays L1 on the wafer 50, and detects the diffracted X-rays L2.
  • the diffraction angle 2 ⁇ is the angle between the incident direction of the incident X-rays L1 and the diffraction direction of the diffracted X-rays L2.
  • the diffraction angle 2 ⁇ is fixed and the incident angle ⁇ is varied within a small angular range to measure a rocking curve that represents the intensity of the diffracted X-ray L2 (the intensity profile of the diffracted X-ray L2).
  • the rocking curve has the intensity of the diffracted X-ray L2 on the vertical axis and the incident angle ⁇ on the horizontal axis.
  • the incident angle ⁇ is determined as the angle position at which the intensity of the diffracted X-ray L2 reaches its peak value.
  • the rocking curve measurement method is performed only at one location (e.g., the center) of the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50). If in-plane variation in the off angle ⁇ off is expected, the rocking curve measurement method may be performed at multiple locations (e.g., the center and peripheral areas) of the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50).
  • FIG. 43B shows the measurement points when the rocking curve measurement method is performed on multiple points (here, five points) on the upper end of the first layer 8.
  • the off angle ⁇ off of the first layer 8 is set to about 4° here.
  • the first to fifth measurement points Po1 to Po5 are shown.
  • the first measurement point Po1 is set in the center of the first layer 8.
  • the second measurement point Po2 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to one side in the second direction Y (the opposite side from the mark 54).
  • the third measurement point Po3 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to one side in the first direction X (to the right of the mark 54).
  • the fourth measurement point Po4 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the second direction Y (the side toward the mark 54).
  • the fifth measurement point Po5 is set on the periphery of the first layer 8 at a distance from the first measurement point Po1 to the other side in the first direction X (to the left of the mark 54).
  • the measurement results of the incident angle ⁇ , diffraction angle 2 ⁇ , and off angle ⁇ off at the first to fifth measurement points Po1 to Po5 are shown in the following Table 1.
  • the off angle ⁇ off is calculated using the incident angle ⁇ and diffraction angle 2 ⁇ by the formula " ⁇ -(2 ⁇ 1/2)".
  • the average value of the off angle ⁇ off of the first to fifth measurement points Po1 to Po5 was 4.036°, and the standard deviation of these off angles ⁇ off was 0.009° ( ⁇ 0.01°). From this, it can be understood that the in-plane variation of the off angle ⁇ off occurring at the upper end of the first layer 8 (first wafer main surface 51 of wafer 50) is extremely small, and is not enough to interfere with the channeling implantation process.
  • the measurement point may be any one or more (all) of the first to fifth measurement points Po1 to Po5.
  • the measurement point may be only the first measurement point Po1. Reducing the number of measurement points (number of measurements) reduces the manufacturing man-hours (manufacturing costs).
  • the off angle ⁇ off may be measured at multiple points on the upper end of the first layer 8 (first wafer main surface 51 of the wafer 50) and an implantation angle may be set in the channeling implantation process according to the in-plane variation of the off angle ⁇ off.
  • the manufacturing man-hours manufactured costs
  • the in-plane error of the first region 14 formed in the first layer 8 is appropriately suppressed.
  • the off-angle ⁇ off of the first layer 8 is approximately equal to the off-angle ⁇ off of the wafer 50 and the off-angle ⁇ off of the buffer layer 26. Therefore, the crystal orientation measurement process may be performed on the wafer 50 or the buffer layer 26 prior to the formation process of the first layer 8. However, from the standpoint of ensuring accuracy, it is preferable that the crystal orientation measurement process be performed on the first layer 8.
  • a step of forming a first mask 60 having a predetermined pattern is carried out (step S6 in FIG. 41).
  • the first mask 60 is preferably an organic mask (resist mask).
  • the first mask 60 is disposed on the upper end of the first layer 8, and has a number of first openings 61 that expose areas of the first layer 8 where a number of first regions 14 are to be formed.
  • the multiple first openings 61 are formed at intervals in the first array direction Da1 over the entire surface of the upper end of the first layer 8, and are each partitioned into stripes extending in the first extension direction De1.
  • the multiple first openings 61 cross the multiple device regions 55 and the multiple lines to be cut 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple lines to be cut 56 in a stripe pattern.
  • the multiple first openings 61 expose both the portion of the upper end of the first layer 8 that is located within the active region 10 and the portion that is located within the peripheral region 11 in each device region 55.
  • the process for forming a plurality of first regions 14 includes a channeling injection process of a trivalent element (p-type impurity) into the first layer 8.
  • the first layer 8 (wafer 50) has an off angle ⁇ off inclined at a predetermined angle in a predetermined off direction Doff with respect to the first wafer main surface 51.
  • the channeling injection process is carried out based on data (information) of the off angle ⁇ off.
  • a trivalent element is introduced into the first layer 8 with a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle ⁇ off) (see also Figure 14).
  • a trivalent element is implanted along the vertical direction Z perpendicular to the upper end of the first layer 8 (first wafer main surface 51).
  • the trivalent element is introduced along a direction in which the atomic rows are relatively dense in plan view, so the trivalent element collides with the atomic rows at a relatively shallow depth position. Therefore, the atomic rows prevent the introduction of the trivalent element into the first layer 8 at a relatively deep depth position. As a result, a first region 14 that does not have a slow portion 22 is formed (see also FIG. 14).
  • the implantation angle of the trivalent element into the first layer 8 is controlled, and the trivalent element is introduced into the first layer 8 along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined implantation energy (also refer to FIGS. 13A to 13E).
  • a predetermined implantation energy also refer to FIGS. 13A to 13E.
  • the wafer 50 may be supported horizontally and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • the wafer 50 may be supported tilted by the off angle ⁇ off from the horizontal and the trivalent element may be introduced into the first layer 8 along the first axial channel CH1.
  • a plurality of first regions 14 having a predetermined thickness are formed at a predetermined depth (see also Figures 13A to 13E).
  • the implantation energy of the trivalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection temperature of the trivalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the first axial channel CH1 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • the trivalent element is introduced along the first axial channel CH1, in which the atomic rows are relatively sparse in plan view.
  • the trivalent element travels through the first axial channel CH1 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the first layer 8.
  • the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.
  • a trivalent element belonging to the heavy elements heavier than carbon is introduced into the first layer 8.
  • the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium).
  • the trivalent element is aluminum.
  • the first extension direction De1 may be the a-axis direction or the m-axis direction.
  • the first extension direction De1 may be a direction other than the a-axis direction or the m-axis direction.
  • the trivalent element is introduced into the first layer 8 through the multiple first openings 61 at an angle of approximately the off angle ⁇ off with respect to the upper end of the first layer 8 in a cross-sectional view along the first array direction Da1.
  • the trivalent element is introduced into the first layer 8 through the multiple first openings 61 almost perpendicular to the upper end of the first layer 8 in a cross-sectional view along the first array direction Da1. This prevents the multiple first regions 14 from being formed in the first layer 8 in an inclined position. In addition, the wall surfaces of the multiple first openings 61 are prevented from becoming a shield against the entrance path of the trivalent element.
  • first extension direction De1 is a direction other than the a-axis direction and the m-axis direction (see also Figures 12A to 12C, etc.), there is no need to strictly control the alignment misalignment of the multiple first regions 14 with respect to the crystal orientation of the SiC single crystal.
  • the trivalent element may be electrically activated by an annealing method, and at the same time, lattice defects and the like that have occurred in the first layer 8 may be repaired.
  • the annealing temperature for the first layer 8 may be 500°C or higher and 2000°C or lower. This forms a first superjunction structure SJ1 at the same time as forming a plurality of first regions 14.
  • the first regions 14 are arranged at intervals in the first arrangement direction Da1 across the entire area of the first layer 8, and are each formed to extend in a strip shape in the first extension direction De1. In other words, the first regions 14 are formed in stripes so as to cross the device regions 55 and the cutting lines 56 in the first extension direction De1. After the process of forming the first regions 14, the first mask 60 is removed.
  • a determination step is performed as to whether or not a thickness adjustment step for the first layer 8 is to be performed (step S8 in FIG. 41). If the thickness of the first layer 8 is to be adjusted (step S8 in FIG. 41: YES), the first layer 8 is thinned from the upper end side (step S9 in FIG. 41).
  • the thickness adjustment process may include a process of partially removing the upper end of the first layer 8 by a grinding method.
  • the grinding method may be a mechanical polishing method and/or a chemical mechanical polishing method.
  • the thickness adjustment process may include a process of partially removing the upper end of the first layer 8 by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the thickness adjustment process may include a step of exposing the first regions 14 from the upper end of the first layer 8 (see also Figures 27 to 30, etc.). In other words, the thickness adjustment process may include a step of removing part or all of the first gradually increasing portions 20A of the first regions 14. If the thickness adjustment process is not performed (Step S8 in Figure 41: NO), this step is omitted.
  • Step S10 in Figure 41 a determination step is performed as to whether or not a process for forming multiple intermediate regions 25 (see also Figures 25 and 26) is to be performed (Step S10 in Figure 41). If multiple intermediate regions 25 are to be formed (Step S10 in Figure 41: YES), multiple intermediate regions 25 are formed in the surface layer portion of the first layer 8 (Step S11 in Figure 41).
  • the process of forming the multiple intermediate regions 25 includes placing a mask (not shown) having a predetermined pattern on the upper end of the first layer 8.
  • the mask (not shown) is preferably an organic mask (resist mask).
  • the mask (not shown) has multiple openings that each expose an area in the first layer 8 where the multiple first regions 14 are formed.
  • the multiple openings are formed at intervals in the first array direction Da1 over the entire surface of the upper end of the first layer 8, and are each partitioned into stripes extending in the first extension direction De1.
  • the multiple openings cross the multiple device regions 55 and the multiple lines to be cut 56 in the first extension direction De1, exposing the multiple device regions 55 and the multiple lines to be cut 56 in a striped pattern.
  • the multiple openings expose both the portion of the upper end of the first layer 8 that is located within the active region 10 and the portion that is located within the peripheral region 11 in each device region 55.
  • the process of forming the multiple intermediate regions 25 includes a process of introducing a trivalent element into the first layer 8 at a predetermined implantation energy in a direction intersecting the first axial channel CH1 (off angle ⁇ off) by a random implantation method through a mask (not shown) (see also FIG. 14).
  • the trivalent element may be introduced into the first layer 8 once or multiple times. When the trivalent element is introduced multiple times, the trivalent element may be introduced in multiple stages at different depth positions in the first layer 8 with multiple implantation energies.
  • the intermediate regions 25 are arranged at intervals in the first arrangement direction Da1 across the entire area of the first layer 8, and are each formed to extend in a strip shape in the first extension direction De1. In other words, the intermediate regions 25 are formed in stripes so as to cross the device regions 55 and the cutting lines 56 in the first extension direction De1. After the process of forming the intermediate regions 25, the mask (not shown) is removed.
  • the process of forming the multiple intermediate regions 25 may be performed consecutively from the process of forming the multiple first regions 14. In this case, the multiple intermediate regions 25 may be formed using the above-mentioned first mask 60.
  • a process for forming the second layer 9 is carried out (step S12 in FIG. 41).
  • the second layer 9 is formed starting from the first layer 8 by epitaxial growth.
  • a process for measuring the crystal orientation (off angle ⁇ off) of the second layer 9 may be carried out by a method similar to step S4 in FIG. 41 (also see FIGS. 43A and 43B).
  • the second mask 62 is preferably an organic mask (resist mask).
  • the second mask 62 is disposed on the upper end of the second layer 9 and has a number of second openings 63 that expose areas of the second layer 9 where a number of second regions 15 are to be formed.
  • the second openings 63 are formed at intervals in a second arrangement direction Da2 different from the first arrangement direction Da1 over the entire surface of the upper end of the second layer 9, and are each partitioned into strips extending in a second extension direction De2 different from the first extension direction De1.
  • the second openings 63 cross the device regions 55 and the lines to be cut 56 in the second extension direction De2, exposing the device regions 55 and the lines to be cut 56 in a stripe pattern.
  • the second openings 63 expose both a portion of the upper end of the second layer 9 that is located within the active region 10 and a portion that is located within the peripheral region 11 in each device region 55.
  • a process for forming a plurality of second regions 15 is carried out (step S14 in FIG. 41).
  • the process for forming a plurality of second regions 15 includes a channeling injection process of a trivalent element (p-type impurity) into the second layer 9.
  • the channeling injection process is carried out based on the data (information) of the off angle ⁇ off described above.
  • the injection angle of the trivalent element into the second layer 9 is controlled, and the trivalent element is introduced into the second layer 9 along the second axial channel CH2 (the c-axis of the SiC single crystal in this embodiment) with a predetermined injection energy (see also Figures 13A to 13E).
  • a predetermined injection energy see also Figures 13A to 13E.
  • the wafer 50 may be supported horizontally and the trivalent element may be introduced into the second layer 9 along the second axial channel CH2.
  • the wafer 50 may be supported tilted by the off angle ⁇ off from the horizontal and the trivalent element may be introduced into the second layer 9 along the second axial channel CH2.
  • a plurality of second regions 15 having a predetermined thickness are formed at a predetermined depth (see also Figures 13A to 13E).
  • the implantation energy of the trivalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the injection energy for the second region 15 may be approximately equal to the injection energy for the first region 14, or may be different from the injection energy for the first region 14.
  • the injection energy for the second region 15 may be equal to or greater than the injection energy for the first region 14.
  • the injection energy for the second region 15 may also be less than the injection energy for the first region 14.
  • the injection temperature of the trivalent element may be adjusted in the range of 0°C to 1500°C.
  • the injection temperature may have a value that belongs to any one of the following ranges: 0°C to 25°C, 25°C to 50°C, 50°C to 100°C, 100°C to 250°C, 250°C to 500°C, 500°C to 750°C, 750°C to 1000°C, 1000°C to 1250°C, and 1250°C to 1500°C.
  • the injection temperature for the second region 15 may be approximately equal to the injection temperature for the first region 14, or may be different from the injection temperature for the first region 14.
  • the injection temperature for the second region 15 may be equal to or higher than the injection temperature for the first region 14. Also, the injection temperature for the second region 15 may be lower than the injection temperature for the first region 14.
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the second axial channel CH2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • the trivalent element is introduced along the second axial channel CH2, in which the atomic rows are relatively sparse in plan view.
  • the trivalent element travels through the second axial channel CH2 while repeatedly undergoing small-angle scattering due to the channeling effect, and reaches a relatively deep position in the second layer 9.
  • the probability of the trivalent element colliding with the atomic rows of the SiC single crystal is reduced.
  • a trivalent element belonging to the heavy elements heavier than carbon is introduced into the second layer 9.
  • the trivalent element is a trivalent element other than boron (at least one of aluminum, gallium, and indium).
  • the trivalent element is aluminum.
  • the second extension direction De2 may be the a-axis direction or the m-axis direction.
  • the second extension direction De2 may be a direction other than the a-axis direction or the m-axis direction.
  • the trivalent element is introduced into the second layer 9 through the second openings 63 at an angle of approximately the off angle ⁇ off with respect to the upper end of the second layer 9 in a cross-sectional view along the second arrangement direction Da2.
  • the second extension direction De2 is a direction other than the a-axis direction and the m-axis direction (see also Figures 12A to 12C, etc.), there is no need to strictly control the alignment misalignment of the multiple second regions 15 with respect to the crystal orientation of the SiC single crystal.
  • the second extension direction De2 is also a direction other than the a-axis direction and the m-axis direction.
  • the multiple first regions 14 have a first extension angle ⁇ 1 inclined toward one side of the m-axis with respect to the a-axis
  • the multiple second regions 15 have a second extension angle ⁇ 2 toward the other side of the m-axis with respect to the a-axis.
  • the absolute value of the second extension angle ⁇ 2 may be different from the absolute value of the first extension angle ⁇ 1.
  • the condition of the relative injection angle of the trivalent element in the process of forming the second region 15 is different from the condition of the relative injection angle of the trivalent element in the process of forming the first region 14. Therefore, the shielding area of the multiple second openings 63 with respect to the incident path of the trivalent element is different from the shielding area of the multiple first openings 61 with respect to the incident path of the trivalent element.
  • the process error of the multiple second regions 15 caused by the shadowing of the multiple second openings 63 is different from the process error of the multiple first regions 14 caused by the shadowing of the multiple first openings 61. Therefore, it is preferable that the absolute value of the second extension angle ⁇ 2 is approximately equal to the absolute value of the first extension angle ⁇ 1. In this case, the process error of the multiple second regions 15 is approximately the same as the process error of the multiple first regions 14. Therefore, the accuracy of the charge balance is improved.
  • the first extension angle ⁇ 1 may be +45° ⁇ 5° and the second extension angle ⁇ 2 may be -45° ⁇ 5° (see FIG. 12A).
  • the first extension angle ⁇ 1 may be +30° ⁇ 5° and the second extension angle ⁇ 2 may be -30° ⁇ 5° (see FIG. 12B).
  • the first extension angle ⁇ 1 may be +60° ⁇ 5° and the second extension angle ⁇ 2 may be -60° ⁇ 5° (see FIG. 12C).
  • the trivalent element may be electrically activated by an annealing method, and at the same time, lattice defects and the like that have occurred in the second layer 9 may be repaired.
  • the annealing temperature for the second layer 9 may be 500°C or higher and 2000°C or lower. This forms a plurality of second regions 15 and at the same time forms the second superjunction structure SJ2.
  • the second regions 15 are arranged at intervals in the second array direction Da2 across the entire second layer 9, and are each formed to extend in a strip shape in the second extension direction De2. In other words, the second regions 15 are formed in stripes that cross the device regions 55 and the cutting lines 56 in the second extension direction De2.
  • the annealing method for the second regions 15 may also serve as the annealing method for the first regions 14 described above. In this case, the annealing method for the first regions 14 before the process of forming the second regions 15 may be omitted.
  • a determination step is performed as to whether or not a thickness adjustment step for the second layer 9 is to be performed (step S15 in FIG. 41). If the thickness of the second layer 9 is to be adjusted (step S15 in FIG. 41: YES), the second layer 9 is thinned from the upper end side (step S16 in FIG. 41).
  • the thickness adjustment process may include a process of partially removing the upper end of the second layer 9 by a grinding method.
  • the grinding method may be a mechanical polishing method and/or a chemical mechanical polishing method.
  • the thinning process of the second layer 9 may include a process of partially removing the upper end of the second layer 9 by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the thickness adjustment process may include a step of exposing the second regions 15 from the upper end of the second layer 9 (see also Figures 27 to 30, etc.). In other words, the thickness adjustment process may include a step of removing part or all of the second gradually increasing portions 20B of the second regions 15. If the thickness adjustment process is not performed (Step S15 in Figure 41: NO), this step is omitted.
  • a determination step is performed as to whether or not a further superjunction structure SJ formation step is to be performed on the second layer 9 (step S17 in FIG. 41). For example, if a formation step of a third superjunction structure SJ3 (see also FIG. 33) is to be performed (step S17 in FIG. 41: YES), a third layer 27 is formed on the second layer 9 through steps similar to steps S12 to S14 in FIG. 41, and multiple third regions 28 are formed in the third layer 27 (step S18 in FIG. 41).
  • step S11 in FIG. 41 a process similar to step S11 in FIG. 41 may be carried out to form a plurality of intermediate regions 25 in the surface layer portion of the second layer 9 (see also FIGS. 25 and 26). If the process of forming the further superjunction structure SJ is not carried out (step S17 in FIG. 41: NO), this process is omitted.
  • a determination step is performed as to whether or not the top layer 30 (see also FIG. 34) formation step is performed (step S19 in FIG. 41). If the top layer 30 formation step is performed (step S19 in FIG. 41: YES), the top layer 30 is formed starting from the second layer 9 by epitaxial growth (step S20 in FIG. 41). If the top layer 30 formation step is not performed (step S19 in FIG. 41: NO), this step is omitted.
  • the MIS structure 31, multiple field regions 38, interlayer insulating film 40, gate pad 45, gate wiring 46, source pad 47, drain pad 48, etc. are formed (step S21 in FIG. 41).
  • the wafer 50 is cut along the multiple planned cutting lines 56.
  • the portions of the multiple first regions 14 located on the multiple planned cutting lines 56 are exposed from the first side 5A (third side 5C) as multiple first marks Mk1.
  • the portions of the multiple intermediate regions 25 located on the multiple planned cutting lines 56 are exposed from the first side 5A (third side 5C) as parts (upper ends) of the multiple first marks Mk1.
  • the portions of the multiple second regions 15 located on the multiple planned cutting lines 56 are exposed from the second side 5B (fourth side 5D) as multiple second marks Mk2.
  • the step of cutting the wafer 50 may include a step of cutting the wafer 50.
  • the wafer 50 is cut along a plurality of intended cutting lines 56 by a dicing blade. This forms a chip 2 having first to fourth side surfaces 5A to 5D each made of a ground surface.
  • the process of cutting the wafer 50 may include a process of cleaving the wafer 50.
  • a plurality of modified layers (damage layers) are formed inside the wafer 50 along a plurality of intended cutting lines 56 by a laser light irradiation method, and the wafer 50 is cleaved along the plurality of intended cutting lines 56 starting from the plurality of modified layers.
  • the multiple modified layers are formed in the thickness range of the wafer 50 (base layer 6) relative to the thickness range of the laminated portion 7. Specifically, it is preferable that the multiple modified layers are formed in the wafer 50 (base layer 6) at intervals from the thickness range of the laminated portion 7 toward the second wafer main surface 52 of the wafer 50.
  • multiple modified layers are formed (remain) on the portions of the first to fourth side surfaces 5A to 5D that are made of the base layer 6 after cleavage. This makes it possible to prevent the multiple modified layers from overlapping the decorative pattern PT (the multiple first marks Mk1 and the multiple second marks Mk2). This improves the visibility of the decorative pattern PT. In addition, the electrical influence that the multiple modified layers have on the multiple first regions 14 and the multiple second regions 15 via the decorative pattern PT is reduced.
  • the first to fourth side surfaces 5A to 5D each consist of a cleavage surface and each have a plurality of modified layers. Therefore, the plurality of modified layers may be regarded as one component of the SiC semiconductor device 1A (chip 2).
  • step S2 may be determined in advance at the stage of the wafer 50 preparation step (step S1 in FIG. 41).
  • the SiC semiconductor device 1A may be manufactured along a predetermined manufacturing line. Through steps including those described above, multiple SiC semiconductor devices 1A are manufactured from one wafer 50.
  • Figure 45 is a plan view showing a SiC semiconductor device 1B relating to the second embodiment.
  • Figure 46A is a cross-sectional view taken along line XLVIA-XLVIA shown in Figure 45.
  • Figure 46B is a cross-sectional view taken along line XLVIB-XLVIB shown in Figure 45.
  • Figure 47A is a plan view showing an example layout of chip 2 (first layer 8).
  • Figure 47B is a plan view showing an example layout of chip 2 (second layer 9).
  • Figure 48 is a perspective view showing an example layout of chip 2.
  • the SiC semiconductor device 1B includes a chip 2, a base layer 6, a stacked portion 7 (a first layer 8 and a second layer 9), an active region 10, and a peripheral region 11, similar to the SiC semiconductor device 1A.
  • the SiC semiconductor device 1B includes an active surface 71, an outer surface 72, and first to fourth connecting surfaces 73A to 73D formed on the first main surface 3.
  • the active surface 71, the outer surface 72, and the first to fourth connecting surfaces 73A to 73D define an active plateau 74 on the first main surface 3.
  • the active surface 71 may be referred to as the "first surface portion,” the outer peripheral surface 72 as the “second surface portion,” the first to fourth connection surfaces 73A to 73D as the “connection surface portions,” and the active plateau 74 as the “mesa portion.”
  • the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D may be considered to be components of the chip 2 (first main surface 3).
  • the active surface 71 is formed in the active region 10. That is, the active surface 71 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3.
  • the active surface 71 has a flat surface extending in the first direction X and the second direction Y.
  • the active surface 71 is formed by a c-plane (Si-plane).
  • the active surface 71 is formed in a quadrangle shape having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.
  • the outer peripheral surface 72 is formed in the outer peripheral region 11. In other words, the outer peripheral surface 72 is formed outside the active surface 71.
  • the outer peripheral surface 72 is recessed in the thickness direction of the chip 2 (toward the second main surface 4) relative to the active surface 71. Specifically, in this embodiment, the outer peripheral surface 72 is recessed to a depth less than the thickness of the second layer 9 so as to expose the second layer 9.
  • the outer peripheral surface 72 extends in a band shape along the active surface 71 in a plan view, and is formed in a ring shape (specifically a square ring shape) surrounding the active surface 71.
  • the outer peripheral surface 72 has a flat surface extending in the first direction X and the second direction Y, and is formed approximately parallel to the active surface 71.
  • the outer peripheral surface 72 is formed by a c-plane (Si-plane).
  • the outer peripheral surface 72 is continuous with the first to fourth side surfaces 5A to 5D.
  • the outer peripheral surface 72 has a peripheral depth DO.
  • the peripheral depth DO may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the peripheral depth DO may have a value that falls within any one of the ranges of 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the peripheral depth DO is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the first to fourth connection surfaces 73A to 73D extend in the vertical direction Z and connect the active surface 71 and the outer peripheral surface 72.
  • the first connection surface 73A is located on the first side surface 5A side
  • the second connection surface 73B is located on the second side surface 5B side
  • the third connection surface 73C is located on the third side surface 5C side
  • the fourth connection surface 73D is located on the fourth side surface 5D side.
  • the first connection surface 73A and the third connection surface 73C extend in the first direction X and face the second direction Y.
  • the second connection surface 73B and the fourth connection surface 73D extend in the second direction Y and face the first direction X.
  • the first to fourth connection surfaces 73A to 73D may extend approximately vertically between the active surface 71 and the outer peripheral surface 72 so as to define a quadrangular prism-shaped active plateau 74.
  • the first to fourth connection surfaces 73A to 73D may be inclined obliquely downward from the active surface 71 toward the outer peripheral surface 72 so as to define a quadrangular pyramid-shaped active plateau 74.
  • the active plateau 74 is defined in a protruding shape in the second layer 9 on the first main surface 3.
  • the active plateau 74 is formed only in the second layer 9 and not in the first layer 8.
  • SiC semiconductor device 1B like SiC semiconductor device 1A, includes a decorative pattern PT according to the first embodiment on first to fourth side surfaces 5A to 5D.
  • the decorative pattern PT includes a plurality of first marks Mk1 and a plurality of second marks Mk2.
  • the multiple first marks Mk1 and multiple second marks Mk2 are each formed in the same manner as in the case of the SiC semiconductor device 1A.
  • the multiple first marks Mk1 are preferably formed at intervals from the outer peripheral surface 72 to the lower end side of the first layer 8.
  • the multiple second marks Mk2 are preferably exposed from the upper end of the outer peripheral surface 72.
  • the multiple second marks Mk2 may have a thickness less than the thickness of the multiple first marks Mk1.
  • the multiple second marks Mk2 may have a thickness greater than or equal to the thickness of the multiple first marks Mk1.
  • the SiC semiconductor device 1B may include the decorative pattern PT according to the second to fifth embodiment examples.
  • the decorative pattern PT includes the first difference mark Md1 (see Figures 6A and 6C, etc.)
  • the first difference mark Md1 is interposed in the area between the outer peripheral surface 72 and the multiple first marks Mk1 and is exposed from the outer peripheral surface 72.
  • the decorative pattern PT includes the second difference mark Md2 (see Figures 6B and 6C, etc.), it is preferable that the second difference mark Md2 is formed at a distance from the outer peripheral surface 72 toward the lower end of the first layer 8, and faces the outer peripheral surface 72 with multiple second marks Mk2 in between.
  • the SiC semiconductor device 1B includes a p-type column region 12 formed in the stack portion 7 in the active region 10.
  • the column region 12 is formed in the same layout as in the SiC semiconductor device 1A. That is, the multiple first regions 14 are formed in the first layer 8 in the same layout as the multiple first regions 14 in the SiC semiconductor device 1A, and define multiple first drift regions 16.
  • the multiple second regions 15 are formed in the second layer 9 in the same layout as the multiple second regions 15 in the SiC semiconductor device 1A, and define multiple second drift regions 17.
  • the column region 12 may have at least one of the multiple features shown in the first to twelfth embodiment examples.
  • the column region 12 may have a feature that combines multiple (two or more) features shown in the first to twelfth embodiment examples described above.
  • the first regions 14 are each formed within an area surrounded by at least the periphery of the active surface 71 (the first to fourth connection surfaces 73A to 73D) in a plan view. In this embodiment, the first regions 14 are pulled out from the active region 10 across the area directly below the first to fourth connection surfaces 73A to 73D to the peripheral region 11 (see FIG. 47A).
  • the multiple first regions 14 are drawn out from a portion of the first layer 8 facing the active surface 71 to a portion of the first layer 8 facing the outer peripheral surface 72.
  • the multiple first regions 14 are also arranged at intervals in the first arrangement direction Da1 in the outer peripheral region 11, and are each formed in a strip shape extending in the first extension direction De1.
  • the multiple first regions 14 are formed at intervals from the outer peripheral surface 72 to the lower end side of the first layer 8 in the outer peripheral region 11, and face the outer peripheral surface 72 with the second layer 9 in between.
  • the multiple first regions 14 extend from the outer peripheral region 11 toward either or both of the first side surface 5A and the third side surface 5C (both in this embodiment), and each has a portion exposed from either or both of the first side surface 5A and the third side surface 5C (both in this embodiment).
  • the portions of the multiple first regions 14 exposed from the first side surface 5A form multiple first marks Mk1 on the first side surface 5A
  • the portions of the multiple first regions 14 exposed from the third side surface 5C form multiple first marks Mk1 on the third side surface 5C.
  • the second regions 15 are each formed within an area surrounded by at least the periphery of the active surface 71 (the first to fourth connection surfaces 73A to 73D) in a plan view. In this embodiment, the second regions 15 extend from a portion of the second layer 9 located within the active region 10 to a portion of the second layer 9 located in the peripheral region 11.
  • the portions of the second regions 15 located in the outer peripheral region 11 may have a thickness less than that of the first regions 14. Of course, the portions of the second regions 15 located in the outer peripheral region 11 may have a thickness greater than or equal to that of the first regions 14.
  • the second lower ends 15a of the second regions 15 are located in a region closer to the lower end of the second layer 9 than the depth position of the outer peripheral surface 72 in the thickness direction of the second layer 9.
  • the second upper ends 15b of the second regions 15 are located in a region closer to the active surface 71 than the outer peripheral surface 72 in the thickness direction of the second layer 9.
  • the multiple second regions 15 are exposed from at least one of the first to fourth connection surfaces 73A to 73D that is perpendicular to the second extension direction De2. In this embodiment, the multiple second regions 15 are exposed from both the second connection surface 73B and the fourth connection surface 73D.
  • the second region 15 may be exposed from the entire area of the first connection surface 73A.
  • the third connection surface 73C is formed along the second extension direction De2 from the middle of the second region 15, the second region 15 may be exposed from the entire area of the third connection surface 73C.
  • the multiple second regions 15 may be exposed from either one or both of the first connection surface 73A and the third connection surface 73C. In these cases, the second regions 15 may be exposed from the entire area of either one or both of the second connection surface 73B and the fourth connection surface 73D.
  • the second regions 15 are also arranged at intervals in the second arrangement direction Da2 in the outer peripheral region 11, and are each formed in a band shape extending in the second extension direction De2.
  • the second regions 15 are exposed from the outer peripheral surface 72 in the outer peripheral region 11.
  • the multiple second regions 15 extend from the outer peripheral region 11 toward either or both (both in this embodiment) the second side surface 5B and the fourth side surface 5D, and each has a portion exposed from either or both (both in this embodiment) the second side surface 5B and the fourth side surface 5D.
  • the portions of the multiple second regions 15 exposed from the second side surface 5B form multiple second marks Mk2 on the second side surface 5B
  • the portions of the multiple second regions 15 exposed from the fourth side surface 5D form multiple second marks Mk2 on the fourth side surface 5D.
  • FIG. 49 is a plan view showing a main portion of the active region 10.
  • FIG. 50 is a cross-sectional perspective view showing a gate structure 35 according to the first embodiment.
  • the SiC semiconductor device 1B includes a MIS structure 31 formed in the active region 10. The following components are described as components of the SiC semiconductor device 1B, but are also components of the MIS structure 31.
  • the SiC semiconductor device 1B includes a p-type body region 32 formed in the surface layer of the first main surface 3 (active surface 71).
  • the body region 32 is formed in a layer extending along the active surface 71.
  • the body region 32 may be formed over the entire active surface 71 and exposed from the first to fourth connection surfaces 73A to 73D.
  • the body region 32 is formed at a distance from the lower end of the second layer 9 toward the active surface 71, and overlaps the column region 12 (the multiple second regions 15) in the stacking direction.
  • the body region 32 is preferably formed at a distance from the depth position of the outer peripheral surface 72 toward the active surface 71, and is exposed from the first main surface 3.
  • the body region 32 is formed in the region between the active surface 71 and the second upper ends 15b of the multiple second regions 15.
  • the body region 32 is preferably connected to the multiple second regions 15 (the second upper ends 15b).
  • the body region 32 is composed of a random impurity region introduced into the surface layer of the second layer 9 by a random implantation method into the second layer 9 (see also FIG. 14). Therefore, the body region 32 has a thickness in the direction along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the body region 32 is less than the first region thickness TR1 of the first region 14.
  • body region 32 does not have gradual portion 22 having a thickness of 0.5 ⁇ m or more, and has a concentration gradient including gradually increasing portion 20, peak portion 21, and gradually decreasing portion 23 within a range of 0.5 ⁇ m.
  • Body region 32 may have a peak value of a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the body region 32 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the body region 32 may be the same as the trivalent element of the second region 15, etc., or may be a different species from the trivalent element of the second region 15, etc.
  • the trivalent element of the body region 32 may be at least one of boron, aluminum, gallium, and indium.
  • the body region 32 may be formed by utilizing a part of the p-type top layer 30.
  • the SiC semiconductor device 1B includes a plurality of trench electrode type gate structures 35 formed on the first main surface 3 (active surface 71) in the active region 10.
  • the gate structures 35 may be referred to as "trench gate structures.”
  • a gate potential is applied to the plurality of gate structures 35 as a control potential.
  • the plurality of gate structures 35 control the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.
  • the multiple gate structures 35 are arranged at intervals inward from the periphery (first to fourth connection surfaces 73A to 73D) of the active surface 71 in the active region 10.
  • the multiple gate structures 35 are arranged at intervals in the second array direction Da2 and are each formed in a strip shape extending in the second extension direction De2. That is, in this embodiment, the multiple gate structures 35 are arranged in stripes extending along the multiple second regions 15 and intersect with the multiple first regions 14 and the multiple first drift regions 16 in the stacking direction.
  • the second array direction Da2 is the m-axis direction (second direction Y), and the second extension direction De2 is the a-axis direction (first direction X).
  • the array direction and extension direction of the multiple gate structures 35 are changed according to the second array direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second array direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction.
  • the second array direction Da2 may be a direction other than the a-axis direction and the m-axis direction, and the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple gate structures 35 are arranged offset from the multiple second regions 15 toward the multiple second drift regions 17. Specifically, the multiple gate structures 35 penetrate the body region 32 at intervals from the multiple second regions 15, and are arranged in a one-to-one correspondence within the multiple second drift regions 17. In other words, the multiple gate structures 35 are arranged alternately with the multiple second regions 15 along the second array direction Da2, and face the multiple second regions 15 in the horizontal direction.
  • the multiple gate structures 35 are formed at intervals from the lower ends of the multiple second drift regions 17 toward the active surface 71, and face the multiple first regions 14 and the multiple first drift regions 16 across parts of the multiple second drift regions 17. It is preferable that the multiple gate structures 35 are formed at intervals from the intermediate portions of the thickness ranges of the multiple second regions 15 toward the active surface 71. Of course, the multiple gate structures 35 may be formed at a depth position that crosses the intermediate portions of the thickness ranges of the multiple second regions 15.
  • Each gate structure 35 has a trench width WT in the arrangement direction (second direction Y in this embodiment) and a trench depth DT in the vertical direction Z.
  • the trench width WT is less than the second pitch P2 (first pitch P1).
  • the trench depth DT is less than the second thickness T2 of the second layer 9. It is preferable that the trench depth DT is approximately equal to the aforementioned peripheral depth DO.
  • the trench depth DT may be greater than or equal to the peripheral depth DO, or may be less than the peripheral depth DO.
  • the trench width WT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench width WT may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, and 4 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • Each gate structure 35 includes a trench 75, an insulating film 76, and a buried electrode 77.
  • the trench 75 is formed in the active surface 71 and defines the wall surface of the gate structure 35.
  • the insulating film 76 covers the wall surface of the trench 75.
  • the insulating film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 76 includes a silicon oxide film made of an oxide of the chip 2.
  • the buried electrode 77 is embedded in the trench 75 with the insulating film 76 in between, and faces the channel with the insulating film 76 in between.
  • the buried electrode 77 may include p-type or n-type conductive polysilicon.
  • the SiC semiconductor device 1B includes a plurality of source regions 33 formed on both sides of a plurality of gate structures 35 in a surface layer portion of the first main surface 3 (active surface 71).
  • the plurality of source regions 33 are formed in a surface layer portion of the body region 32.
  • the plurality of source regions 33 have a higher n-type impurity concentration (peak value) than the second layer 9 (second drift region 17).
  • the plurality of source regions 33 may have an n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the multiple source regions 33 extend in a band shape along the corresponding gate structures 35 in a plan view.
  • the multiple source regions 33 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the second drift region 17 across a portion of the body region 32 in the stacking direction.
  • the multiple source regions 33, together with the multiple second drift regions 17 located directly below, define a channel (current path) that extends along the wall surface of the corresponding gate structure 35.
  • the multiple source regions 33 may face the second region 15 across a portion of the body region 32 in the stacking direction.
  • the multiple source regions 33 may be formed at intervals from the second region 15 to the second drift region 17 side (gate structure 35 side) so as not to face the second region 15 in the stacking direction.
  • the SiC semiconductor device 1A includes a plurality of contact regions 34 formed in the surface portion of the first main surface 3 (active surface 71) in the region between the plurality of gate structures 35.
  • the plurality of contact regions 34 are formed in the surface portion of the body region 32.
  • the plurality of contact regions 34 have a p-type impurity concentration (peak value) higher than the p-type impurity concentration (peak value) of the plurality of body regions 32.
  • the p-type impurity concentration (peak value) of the plurality of contact regions 34 is higher than the p-type impurity concentration (peak value) of the plurality of second regions 15.
  • the plurality of contact regions 34 may have a p-type impurity concentration (peak value) of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the multiple contact regions 34 are interposed between the multiple source regions 33 adjacent to each other, and extend in a strip shape along the multiple gate structures 35.
  • the multiple contact regions 34 are formed at intervals from the bottom of the body region 32 toward the active surface 71, and face the multiple second regions 15 across a portion of the body region 32 in the stacking direction.
  • the multiple contact regions 34 may face the second drift region 17 across a portion of the body region 32 in the stacking direction.
  • the multiple contact regions 34 may be formed at intervals from the second drift region 17 toward the second region 15 so as not to face the second drift region 17 in the stacking direction.
  • Figure 51 is a perspective view showing the configuration of the outer peripheral region 11.
  • Figure 52A is a cross-sectional view in the first direction X showing a main part of the outer peripheral region 11.
  • Figure 52B is a cross-sectional view in the second direction Y showing a main part of the outer peripheral region 11.
  • the column region 12 is omitted from Figure 51.
  • the SiC semiconductor device 1B includes a p-type well region 78 formed in the surface layer portion of the outer peripheral surface 72.
  • the well region 78 is formed at a distance from the periphery (first to fourth side surfaces 5A to 5D) of the outer peripheral surface 72 toward the active surface 71 in a plan view, and extends in a band shape along the active surface 71.
  • the well region 78 is formed in a ring shape (specifically, a square ring shape) surrounding the active surface 71 in a plan view.
  • the well region 78 is pulled out from the surface layer portion of the outer peripheral surface 72 toward the first to fourth connection surfaces 73A to 73D, and extends along the surface layers of the first to fourth connection surfaces 73A to 73D.
  • the well region 78 is electrically connected to the body region 32 at the surface portion of the active surface 71, and is electrically connected to the second regions 15 at the first to fourth connection surfaces 73A to 73D.
  • the well region 78 is formed at a distance from the lower end of the second layer 9 toward the outer peripheral surface 72, and faces the first layer 8 with a portion of the second layer 9 in between.
  • the bottom of the well region 78 is located closer to the lower end of the second layer 9 than the bottom wall of the gate structure 35. It is preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the second lower ends 15a of the second regions 15. It is particularly preferable that the bottom of the well region 78 is located closer to the outer circumferential surface 72 than the intermediate portions of the thickness ranges of the second regions 15.
  • the well region 78 is composed of a random impurity region introduced into the surface layer of the second layer 9 by a random injection method into the second layer 9 (see also FIG. 14). Therefore, the well region 78 has a thickness in the direction along the second axial channel CH2 that is less than the second region thickness TR2 of the second region 15. The thickness of the well region 78 is less than the first region thickness TR1 of the first region 14.
  • Well region 78 differs from second region 15 etc. in that it does not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more, and has a concentration gradient in a range of 0.5 ⁇ m that includes a gradually increasing portion 20, a peak portion 21 and a gradually decreasing portion 23.
  • Well region 78 may have a peak value of a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the well region 78 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 34.
  • the p-type impurity concentration of the well region 78 is higher than the p-type impurity concentration of the body region 32.
  • the p-type impurity concentration of the well region 78 may be lower than the body region 32.
  • the well region 78 forms a pn junction with the second layer 9.
  • the p-type impurity concentration of the well region 78 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the well region 78 may be the same as the trivalent element of the second region 15, etc., or may be a different species from the trivalent element of the second region 15, etc.
  • the trivalent element of the well region 78 may be at least one of boron, aluminum, gallium, and indium.
  • the SiC semiconductor device 1B includes at least one (preferably 2 to 20) p-type field region 38 formed in the surface layer of the outer peripheral surface 72 in the outer peripheral region 11.
  • the multiple field regions 38 are formed in the surface layer of the outer peripheral surface 72 in a manner similar to that of the SiC semiconductor device 1A.
  • the multiple field regions 38 are arranged at intervals from the periphery of the active surface 71 (first to fourth connection surfaces 73A to 73D) and the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). Specifically, the multiple field regions 38 are arranged at intervals from the well region 78 to the periphery side of the outer circumferential surface 72.
  • the multiple field regions 38 extend in a band shape along the active surface 71 in a plan view, and are formed in a ring shape (specifically a square ring) surrounding the active surface 71.
  • the multiple field regions 38 overlap the column regions 12 in the stacking direction on the outer peripheral surface 72. That is, the multiple field regions 38 are formed in a region above multiple intersections of the multiple first regions 14 and the multiple second regions 15. The multiple field regions 38 intersect with the multiple second regions 15 in the portion extending in the first extension direction De1 in a plan view, and intersect with the multiple first regions 14 in the portion extending in the second extension direction De2.
  • the multiple field regions 38 are formed at intervals from the bottom of the second layer 9 toward the outer circumferential surface 72, and face the first layer 8 across a portion of the second layer 9.
  • the multiple field regions 38 are located closer to the lower end of the second layer 9 than the bottom of the gate structure 35.
  • the bottoms of the multiple field regions 38 are preferably located on the outer peripheral surface 72 side relative to the middle part of the thickness range of the second region 15.
  • the multiple field regions 38 may be connected to the multiple second regions 15 in the portion extending along the second extension direction De2.
  • the multiple field regions 38 may be formed horizontally spaced apart from the multiple second regions 15 in the portion extending along the second extension direction De2, and may not be connected to the multiple second regions 15.
  • the SiC semiconductor device 1B includes the aforementioned interlayer insulating film 40 that covers the first main surface 3.
  • the interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D.
  • the first insulating film 41 is connected to the insulating film 76 on the active surface 71, exposing the buried electrode 77.
  • the first insulating film 41 covers the well region 78 and the multiple field regions 38 on the outer peripheral surface 72.
  • the first insulating film 41 is continuous with the first to fourth side surfaces 5A to 5D. Therefore, the first insulating film 41 covers the multiple second marks Mk2 (multiple second regions 15) on the periphery of the outer peripheral surface 72.
  • the first insulating film 41 may be formed at a distance inward from the periphery of the outer peripheral surface 72, exposing the second layer 9 from the periphery of the outer peripheral surface 72. In this case, the first insulating film 41 exposes multiple second marks Mk2 (multiple second regions 15) from the periphery of the outer peripheral surface 72.
  • the first insulating film 41 covers the well region 78 on the first to fourth connection surfaces 73A to 73D.
  • the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 covers the multiple gate structures 35 in the active region 10.
  • the second insulating film 42 covers the multiple field regions 38 and well regions 78 in the outer peripheral region 11, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 is continuous with the first to fourth side surfaces 5A to 5D.
  • the second insulating film 42 may cover the second marks Mk2 (the second regions 15) on the periphery of the outer surface 72, sandwiching the first insulating film 41 between them.
  • the second insulating film 42 may be formed spaced inward from the periphery of the outer surface 72, and may expose the second marks Mk2 (the second regions 15) from the periphery of the outer surface 72 together with the first insulating film 41.
  • the SiC semiconductor device 1A includes a plurality of contact openings 43 formed in the interlayer insulating film 40.
  • the plurality of contact openings 43 include a plurality of contact openings 43 (not shown) that expose a plurality of gate structures 35 (buried electrodes 77), and a plurality of contact openings 43 that expose a plurality of source regions 33.
  • the plurality of contact openings 43 for the source regions 33 are formed in the regions between the plurality of adjacent gate structures 35, and expose the plurality of source regions 33 and the plurality of contact regions 34.
  • the SiC semiconductor device 1B includes a sidewall structure 79 disposed in the interlayer insulating film 40 so as to cover at least one of the first to fourth connection surfaces 73A to 73D.
  • the sidewall structure 79 is disposed on the first insulating film 41 and is covered by the second insulating film 42.
  • the sidewall structure 79 reduces the step formed between the active surface 71 and the outer peripheral surface 72.
  • the sidewall structure 79 is formed in a band shape extending along at least one of the first to fourth connection surfaces 73A to 73D.
  • the sidewall structure 79 is formed in a ring shape (specifically, a square ring shape) extending along the first to fourth connection surfaces 73A to 73D so as to surround the active surface 71 in a plan view.
  • the sidewall structure 79 may have a portion that extends in a film-like manner along the outer peripheral surface 72, and a portion that extends in a film-like manner along the first to fourth connection surfaces 73A to 73D.
  • the sidewall structure 79 is formed at a distance from the innermost field region 38 toward the active surface 71, and faces the multiple second regions 15 and well regions 78 in the horizontal and stacking directions, sandwiching the first insulating film 41 between them.
  • the sidewall structure 79 may face the body region 32, sandwiching the first insulating film 41 between them.
  • the SiC semiconductor device 1B includes a gate pad 45, a plurality of gate wirings 46, a source pad 47, and a drain pad 48.
  • the drain pad 48 is formed in the same manner as in the first embodiment.
  • the gate pad 45 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view.
  • the gate pad 45 is disposed in a region close to the center of one side of the active surface 71 (the second connection surface 73B in this embodiment) in a plan view.
  • the gate pad 45 may also be disposed at a corner of the active surface 71 or in the center of the active surface 71 in a plan view.
  • the multiple gate wirings 46 are arranged on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view.
  • the multiple gate wirings 46 include a first gate wiring 46A and a second gate wiring 46B.
  • the first gate wiring 46A is pulled out from the gate pad 45 toward the second connection surface 73B and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, perpendicular to) a portion (specifically, one end) of the multiple gate structures 35.
  • the first gate wiring 46A penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to one end of the multiple gate structures 35 (buried electrodes 77).
  • the second gate wiring 46B is pulled out from the gate pad 45 toward the fourth connection surface 73D and extends in a line along the periphery of the active surface 71 so as to intersect (specifically, perpendicular to) a portion (specifically, the other end) of the multiple gate structures 35.
  • the second gate wiring 46B penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the other end of the multiple gate structures 35 (buried electrodes 77).
  • the source pad 47 is disposed on the active surface 71 at a distance from the outer peripheral surface 72 in a plan view.
  • the source pad 47 penetrates the interlayer insulating film 40 via a plurality of contact openings 43, and is electrically connected to the body region 32, the plurality of source regions 33, and the plurality of contact regions 34. In other words, the source pad 47 is electrically connected to the column region 12 via the body region 32.
  • FIG. 53 is a cross-sectional perspective view showing a gate structure 35 according to the second embodiment.
  • the multiple gate structures 35 according to the first embodiment described above were arranged shifted from the column region 12 (multiple second regions 15) toward the multiple second drift regions 17.
  • the multiple gate structures 35 according to the second embodiment are arranged so as to overlap the multiple second regions 15 in the stacking direction.
  • the multiple gate structures 35 overlap the multiple second regions 15 in a one-to-one correspondence in the stacking direction.
  • the multiple gate structures 35 each have a bottom wall connected to a corresponding second region 15. Specifically, the multiple gate structures 35 are formed wider than the corresponding second region 15, and each have a bottom wall connected to the corresponding second region 15 and a side wall connected to the corresponding second drift region 17.
  • the buried electrodes 77 face the corresponding second regions 15 across the insulating film 76 in the stacking direction, and face the corresponding second drift regions 17 across the insulating film 76 in the horizontal direction.
  • the aforementioned multiple source regions 33 and multiple contact regions 34 each face the corresponding second drift regions 17 across a portion of the body region 32 in the stacking direction.
  • FIG. 54 is a cross-sectional perspective view showing a gate structure 35 according to a third embodiment.
  • the multiple gate structures 35 according to the third embodiment each have a layout that does not require consideration of misalignment with respect to the multiple second regions 15.
  • the multiple gate structures 35 extend in a direction other than the second extension direction De2 so as to intersect with the multiple second regions 15.
  • the multiple gate structures 35 are arranged at intervals in the first array direction Da1 of the first region 14 and extend in the first extension direction De1 of the first region 14.
  • the first array direction Da1 is the a-axis direction (first direction X)
  • the first extension direction De1 is the m-axis direction (second direction Y).
  • the multiple gate structures 35 may face the multiple first regions 14 in a one-to-one correspondence in the stacking direction. Of course, each gate structure 35 may face the multiple first regions 14 in the stacking direction. The multiple gate structures 35 may face the multiple first drift regions 16 in a one-to-one correspondence in the stacking direction.
  • each gate structure 35 may face multiple first drift regions 16 in the stacking direction.
  • the multiple gate structures 35 may be arranged offset from the multiple first regions 14 in the first array direction Da1 and face either one or both of the first regions 14 and the first drift regions 16 in the stacking direction.
  • the arrangement direction and extension direction of the multiple gate structures 35 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the m-axis direction, and the first extension direction De1 may be the a-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the arrangement direction of the multiple gate structures 35 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2.
  • the extension direction of the multiple gate structures 35 may be a direction other than the first extension direction De1 and the second extension direction De2.
  • the multiple gate structures 35 may intersect both the multiple first regions 14 and the multiple second regions 15 in a planar view.
  • the angle (absolute value) between the extension direction of the gate structure 35 and the second extension direction De2 may be greater than 0° and less than 90°.
  • the angle (absolute value) of the gate structure 35 may have a value belonging to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the angle (absolute value) of the gate structure 35 may be set to a value belonging to any one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • the buried electrode 77 faces the second regions 15 and the second drift regions 17 across the insulating film 76 in the stacking direction and horizontal direction.
  • the source regions 33 and contact regions 34 described above face the second regions 15 and the second drift regions 17 across a portion of the body region 32 in the stacking direction.
  • FIG. 55 is a cross-sectional perspective view showing a gate structure 35 according to the fourth embodiment.
  • the multiple gate structures 35 according to the fourth embodiment each have a configuration that contributes to narrowing the pitch.
  • the multiple gate structures 35 according to the fourth embodiment are particularly effective in realizing a narrower pitch in the column region 12 (multiple second regions 15).
  • FIG. 55 shows an example in which the gate structure 35 according to the first embodiment described above is replaced with the gate structure 35 according to the fourth embodiment, but the configuration of the gate structure 35 according to the fourth embodiment is also applicable to the configurations of the gate structures 35 according to the second and third embodiments.
  • the multiple gate structures 35 each include a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80.
  • the trench 75 has a form similar to that of the first embodiment.
  • the insulating film 76 is formed at a distance from the first main surface 3 (active surface 71) to the bottom wall side of the trench 75, exposing a surface portion of the first main surface 3 (active surface 71) at the opening end of the trench 75. It is preferable that the upper end of the insulating film 76 is located on the first main surface 3 side relative to the intermediate depth range of the trench 75.
  • the buried electrode 77 is buried in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, and defines an open recess that is recessed toward the bottom wall of the trench 75 at the opening end of the trench 75.
  • the buried electrode 77 exposes the surface portion of the first main surface 3 (active surface 71) and the upper end of the insulating film 76 at the opening end of the trench 75. It is preferable that the upper end of the buried electrode 77 is located on the first main surface 3 side relative to the middle part of the depth range of the trench 75.
  • the buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first principal surface 3 (active surface 71), and covers the insulating film 76 and buried electrode 77 within the trench 75.
  • the buried insulator 80 is buried in the trench 75 at a distance from the first principal surface 3 (active surface 71) toward the buried electrode 77, and exposes the surface portion of the first principal surface 3 (active surface 71) at the open end of the trench 75.
  • the upper end of the buried insulator 80 is preferably located on the first main surface 3 side relative to the intermediate portion of the depth range of the trench 75.
  • the buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the buried insulator 80 preferably includes a silicon oxide film.
  • the aforementioned multiple source regions 33 are each formed in a region between multiple adjacent gate structures 35 in the surface layer portion of the first main surface 3 (active surface 71).
  • the multiple source regions 33 are arranged at intervals along the multiple gate structures 35 so as to be connected to the multiple gate structures 35 located on both sides.
  • the multiple source regions 33 arranged along one sidewall of the gate structure 35 face the multiple source regions 33 arranged along the other sidewall of the gate structure 35 in a one-to-one correspondence.
  • the multiple source regions 33 are arranged in a matrix in a planar view.
  • the multiple source regions 33 on one side may face the regions between the multiple source regions 33 on the other side in a one-to-one correspondence.
  • the multiple source regions 33 may be arranged in a staggered pattern in a planar view.
  • the multiple source regions 33 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 between them.
  • the aforementioned contact regions 34 are formed in the regions between adjacent gate structures 35 on the surface layer of the first main surface 3 (active surface 71).
  • the contact regions 34 are arranged at intervals along the gate structures 35 so as to be connected to the gate structures 35 located on both sides.
  • the multiple contact regions 34 are arranged alternately with the multiple source regions 33 along the multiple gate structures 35. More specifically, the multiple contact regions 34 arranged along one sidewall of the gate structure 35 face the multiple contact regions 34 arranged along the other sidewall of the gate structure 35 in a one-to-one correspondence.
  • the multiple source regions 33 are also arranged in a matrix in a planar view.
  • the multiple contact regions 34 on one side may face the regions between the multiple source regions 33 on the other side (i.e., the multiple source regions 33) in a one-to-one correspondence.
  • the multiple contact regions 34 may be arranged in a staggered pattern in a planar view.
  • the multiple contact regions 34 have portions exposed from the sidewall of the trench 75 at the opening end of the trench 75, and face the buried electrode 77 and the buried insulator 80 with the insulating film 76 between them.
  • the aforementioned interlayer insulating film 40 has a layered structure including a first insulating film 41 and a second insulating film 42.
  • the first insulating film 41 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D.
  • the first insulating film 41 covers the peripheral portion of the active surface 71 and exposes the multiple gate structures 35 collectively in the inner portion of the active surface 71. Specifically, the first insulating film 41 is connected to the insulating film 76 at both ends of the multiple gate structures 35, exposing the buried electrodes 77. The first insulating film 41 also covers the outer peripheral surface 72 and the first to fourth connection surfaces 73A to 73D in the same manner as in the first embodiment.
  • the second insulating film 42 selectively covers the active surface 71, the outer peripheral surface 72, and the first to fourth connection surfaces 73A to 73D across the first insulating film 41.
  • the second insulating film 42 covers the peripheral portion of the active surface 71, exposing the multiple gate structures 35 collectively at the inner portion of the active surface 71.
  • the second insulating film 42 penetrates into the trench 75 from above the first main surface 3 (active surface 71) at both ends of the multiple gate structures 35, and is connected to the buried insulator 80 within the trench 75.
  • the interlayer insulating film 40 includes a plurality of contact openings 43 (not shown) that expose both ends (buried electrodes 77) of the plurality of gate structures 35, and a single contact opening 43 that collectively exposes the inner portions (buried insulator 80) of the plurality of gate structures 35, the plurality of source regions 33, and the plurality of contact regions 34.
  • the aforementioned gate pad 45, the aforementioned multiple gate wirings 46, and the aforementioned drain pad 48 have the same configuration as in the first embodiment.
  • the aforementioned source pad 47 penetrates into the single contact opening 43 from above the interlayer insulating film 40, and collectively covers the inner parts (buried insulator 80) of the multiple gate structures 35, the multiple source regions 33, and the multiple contact regions 34 within the single contact opening 43.
  • the source pad 47 is electrically insulated from the multiple gate structures 35 (buried electrodes 77) by the buried insulator 80, and is electrically connected to the multiple source regions 33 and multiple contact regions 34 at the first main surface 3 (active surface 71).
  • the source pad 47 has a buried portion buried in the trench 75. The buried portion of the source pad 47 faces the buried electrode 77 within the trench 75 with the buried insulator 80 in between, and is electrically connected to the multiple source regions 33 and multiple contact regions 34 at the opening end of the trench 75.
  • FIG. 56 is a cross-sectional perspective view showing a gate structure 35 according to the fifth embodiment.
  • the gate structures 35 according to the fifth embodiment each have a configuration that is a modification of the gate structures 35 according to the fourth embodiment.
  • the configuration of the gate structure 35 according to the fifth embodiment is also applicable to the configurations of the gate structures 35 according to the first to third embodiments.
  • the multiple gate structures 35 each include a trench 75, an insulating film 76, a buried electrode 77, and a buried insulator 80.
  • the trench 75 has a similar configuration to that of the first embodiment.
  • the insulating film 76 includes an upper insulating film 81 and a lower insulating film 82.
  • the upper insulating film 81 is formed as an insulating film for channel control, and covers the wall surface on the opening side of the trench 75 relative to the bottom of the body region 32.
  • the upper insulating film 81 has a portion that crosses the boundary between the second drift region 17 and the body region 32 and covers the second drift region 17. In this case, it is preferable that the coverage area of the upper insulating film 81 relative to the body region 32 is larger than the coverage area of the upper insulating film 81 relative to the second drift region 17.
  • the upper insulating film 81 may include a silicon oxide film. It is preferable that the upper insulating film 81 includes a silicon oxide film made of an oxide of the chip 2.
  • the upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value that belongs to any one of the following ranges: 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the lower insulating film 82 covers the wall surface on the bottom wall side of the trench 75 relative to the bottom of the body region 32.
  • the lower insulating film 82 covers the second drift region 17.
  • the coverage area of the lower insulating film 82 relative to the second drift region 17 is larger than the coverage area of the upper insulating film 81 relative to the body region 32.
  • the lower insulating film 82 may include a silicon oxide film.
  • the lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.
  • the lower insulating film 82 has a thickness greater than that of the upper insulating film 81.
  • the thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.
  • the lower insulating film 82 may have a thickness of 100 nm or more and 500 nm or less.
  • the thickness of the lower insulating film 82 may have a value that belongs to any one of the following ranges: 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less, and 450 nm or more and 500 nm or less.
  • the buried electrode 77 has a multi-electrode structure (double electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85.
  • the upper electrode 83 is buried in the opening side of the trench 75 with an insulating film 76 in between.
  • the upper electrode 83 is buried in the opening side of the trench 75 with an upper insulating film 81 in between, and faces the body region 32 with the upper insulating film 81 in between.
  • the facing area of the upper electrode 83 relative to the body region 32 is larger than the facing area of the upper electrode 83 relative to the second drift region 17.
  • the upper electrode 83 is embedded in the trench 75 at a distance from the first main surface 3 (active surface 71) toward the bottom wall of the trench 75, and defines an opening recess that is recessed toward the bottom wall of the trench 75 at the opening end of the trench 75.
  • the upper electrode 83 exposes the surface portion of the first main surface 3 (active surface 71) and the upper end of the upper insulating film 81 at the opening end of the trench 75.
  • a gate potential is applied to the upper electrode 83 as a control potential.
  • the upper electrode 83 controls the inversion and non-inversion of the channel (current path) in the body region 32 in response to the gate potential.
  • the upper electrode 83 may include p-type or n-type conductive polysilicon.
  • the lower electrode 84 is embedded in the bottom wall side of the trench 75 with the insulating film 76 in between. Specifically, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with the lower insulating film 82 in between, and faces the second drift region 17 with the lower insulating film 82 in between. In other words, the lower electrode 84 is embedded in the bottom wall side of the trench 75 with respect to the bottom of the body region 32. Although specific illustration is omitted, the lower electrode 84 is drawn out to the opening side of the trench 75 in part of the trench 75 (both ends in this embodiment).
  • the facing area of the lower electrode 84 with respect to the second drift region 17 is larger than the facing area of the upper electrode 83 with respect to the body region 32.
  • the lower electrode 84 extends in a wall shape along the depth direction of the trench 75.
  • the lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83, and is engaged with the lower end of the upper electrode 83.
  • the upper end of the lower electrode 84 faces the upper insulating film 81 (body region 32) horizontally, sandwiching the lower end of the upper electrode 83 therebetween.
  • the lower electrode 84 may be applied with a gate potential or a source potential.
  • a gate potential When a gate potential is applied to the lower electrode 84, the lower electrode 84 has the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration on the gate structure 35.
  • the lower electrode 84 when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 84 (field electrode) and the second layer 9 (drift region 13) is reduced. This suppresses the decrease in switching speed caused by the parasitic capacitance.
  • the lower electrode 84 may include p-type or n-type conductive polysilicon.
  • the intermediate insulating film 85 is interposed between the upper electrode 83 and the lower electrode 84, and electrically insulates the upper electrode 83 and the lower electrode 84 within the trench 75.
  • the intermediate insulating film 85 is continuous with the upper insulating film 81 and the lower insulating film 82.
  • the intermediate insulating film 85 has a thickness smaller than that of the lower insulating film 82.
  • the thickness of the intermediate insulating film 85 is preferably greater than that of the upper insulating film 81.
  • the intermediate insulating film 85 may include a silicon oxide film.
  • the intermediate insulating film 85 preferably includes a silicon oxide film made of an oxide of the lower electrode 84.
  • the buried insulator 80 is buried in the trench 75 (open recess) so as to expose the first principal surface 3 (active surface 71), and covers the upper insulating film 81 and the upper electrode 83 within the recess.
  • the buried insulator 80 is buried in the trench 75 at a distance from the first principal surface 3 (active surface 71) toward the upper electrode 83, and exposes the surface portion of the first principal surface 3 (active surface 71) at the open end of the trench 75.
  • the aforementioned multiple source regions 33 have portions exposed from the sidewall of trench 75 at the opening end of trench 75, and face upper electrode 83 and buried insulator 80 across upper insulating film 81.
  • the aforementioned multiple contact regions 34 have portions exposed from the sidewall of trench 75 at the opening end of trench 75, and face upper electrode 83 and buried insulator 80 across upper insulating film 81.
  • the aforementioned field regions 38, interlayer insulating film 40, gate pad 45, aforementioned gate wirings 46, aforementioned source pad 47, and aforementioned drain pad 48 have the same configuration as in the second embodiment.
  • the multiple gate wirings 46 penetrate the interlayer insulating film 40 via the multiple contact openings 43 and are electrically connected to the multiple upper electrodes 83.
  • the multiple gate wirings 46 penetrate the interlayer insulating film 40 via the multiple contact openings 43 and are electrically connected to the multiple upper electrodes 83 and the multiple lower electrodes 84.
  • the SiC semiconductor device 1B may include a source wiring drawn from the source pad 47 onto the interlayer insulating film 40.
  • the source wiring is formed in a line shape extending along the periphery of the active surface 71 so as to intersect (specifically, perpendicularly) with a portion (one end or both ends) of the multiple gate structures 35 in a region outside the multiple gate wirings 46.
  • the source wiring penetrates the interlayer insulating film 40 via the multiple contact openings 43 and is electrically connected to the multiple lower electrodes 84.
  • Figure 57 is a plan view showing a SiC semiconductor device 1C relating to the third embodiment.
  • Figure 58A is a cross-sectional view taken along line LVIIIA-LVIIIA shown in Figure 57.
  • Figure 58B is a cross-sectional view taken along line LVIIIB-LVIIIB shown in Figure 57.
  • Figure 59A is a plan view showing an example layout of chip 2 (first layer 8).
  • Figure 59B is a plan view showing an example layout of chip 2 (second layer 9).
  • Figure 60 is a perspective view showing an example layout of chip 2.
  • Figure 61 is a perspective view showing the configuration of the outer periphery region 11. In Figure 61, the column region 12 is omitted from illustration.
  • the SiC semiconductor device 1C includes a chip 2, a base layer 6, a stacked portion 7 (first layer 8 and second layer 9), an active region 10, a peripheral region 11, a column region 12, a plurality of field regions 38, and a decorative pattern PT, similar to the SiC semiconductor device 1A.
  • the decorative pattern PT may have at least one of the multiple features shown in the first to fifth embodiment examples.
  • the column region 12 may have at least one of the multiple features shown in the first to twelfth embodiment examples described above.
  • the column region 12 may have a feature that combines multiple (two or more) features shown in the first to twelfth embodiment examples described above.
  • the SiC semiconductor device 1C includes an interlayer insulating film 90 that selectively covers the first main surface 3.
  • the interlayer insulating film 90 may have a single layer structure or a multilayer structure that includes at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the interlayer insulating film 90 has a single layer structure that includes a silicon oxide film.
  • the interlayer insulating film 90 covers the multiple field regions 38 in the peripheral region 11.
  • the interlayer insulating film 90 is continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).
  • the interlayer insulating film 90 may be formed at a distance inward from the periphery of the first main surface 3, exposing the second layer 9 from the periphery of the first main surface 3.
  • the interlayer insulating film 90 has a contact opening 91 that exposes the active region 10.
  • the contact opening 91 has an opening wall surface positioned above the innermost field region 38, exposing the entire active region 10 and the inner edge of the innermost field region 38.
  • the SiC semiconductor device 1C includes a first pad electrode 92 that covers the first main surface 3 in the active region 10.
  • the first pad electrode 92 is formed as an anode pad.
  • the first pad electrode 92 is disposed at a distance inward from the periphery of the chip 2.
  • the first pad electrode 92 is formed in a polygonal shape (a square shape in this embodiment) that follows the periphery of the chip 2 in a plan view.
  • the first pad electrode 92 penetrates the contact opening 91 from above the interlayer insulating film 90, and is electrically connected to the first main surface 3 and the innermost field region 38 within the contact opening 91.
  • the first pad electrode 92 forms a Schottky junction with the first main surface 3 (second layer 9).
  • an SBD structure 93 Schottky Barrier Diode structure serving as a diode structure (device structure) is formed in the active region 10.
  • the SiC semiconductor device 1C includes a second pad electrode 94 covering the second main surface 4.
  • the second pad electrode 94 is formed as a cathode pad.
  • the second pad electrode 94 forms an ohmic contact with the base layer 6 exposed from the second main surface 4.
  • the second pad electrode 94 is electrically connected to the first layer 8 (the multiple first drift regions 16) and the second layer 9 (the multiple second drift regions 17) via the base layer 6.
  • the second pad electrode 94 may cover the entire second main surface 4 so as to be continuous with the periphery (first to fourth side surfaces 5A to 5D) of the chip 2.
  • the second pad electrode 94 may cover the second main surface 4 at a distance inward from the periphery of the chip 2 so as to expose the periphery of the chip 2.
  • the breakdown voltage that can be applied between the first pad electrode 92 and the second pad electrode 94 (between the first main surface 3 and the second main surface 4) may be 500V to 3000V or less.
  • the breakdown voltage may have a value that falls within any one of the following ranges: 500V to 1000V, 1000V to 1500V, 1500V to 2000V, 2000V to 2500V, and 2500V to 3000V.
  • the breakdown voltage be set to a value belonging to any one of the ranges of 500V to 1000V, 1000V to 1500V, and 1500V to 2000V.
  • the breakdown voltage be set to a value belonging to any one of the ranges of 1000V to 1500V, 1500V to 2000V, 2000V to 2500V, and 2500V to 3000V.
  • Fig. 62 is a cross-sectional perspective view showing the SBD structure 93 according to the first embodiment example.
  • the first pad electrode 92 forms a Schottky junction with the portion of the second layer 9 interposed between the first main surface 3 and the second upper ends 15b.
  • Figure 63 is a cross-sectional perspective view showing an SBD structure 93 according to a second embodiment.
  • the first pad electrode 92 is mechanically and electrically connected to the second regions 15 and the second drift regions 17 at the first main surface 3.
  • the first pad electrode 92 forms a JBS structure (Junction Barrier Controlled Schottky structure) with the second regions 15, and forms a Schottky junction with the second drift regions 17.
  • JBS structure Joint Barrier Controlled Schottky structure
  • Figure 64 is a cross-sectional perspective view showing an SBD structure 93 according to a third embodiment.
  • the first pad electrode 92 forms a Schottky junction with the top layer 30 (first main surface 3).
  • the top layer 30 may be omitted.
  • Figure 65 is a cross-sectional perspective view showing an SBD structure 93 according to a fourth embodiment.
  • the SiC semiconductor device 1C may include a plurality of p-type surface regions 95 (impurity regions) formed in the surface portion of the first main surface 3 within the top layer 30 of the active region 10.
  • the multiple surface regions 95 are arranged at intervals in the second array direction Da2 and are each formed in a strip shape extending in the second extension direction De2. In other words, in this embodiment, the multiple surface regions 95 are arranged in stripes extending along the second extension direction De2 of the multiple second regions 15.
  • the second arrangement direction Da2 is the m-axis direction
  • the second extension direction De2 is the a-axis direction
  • the arrangement direction and extension direction of the multiple surface layer regions 95 are changed according to the second arrangement direction Da2 and second extension direction De2 of the multiple second regions 15. Therefore, the second arrangement direction Da2 may be the a-axis direction, and the second extension direction De2 may be the m-axis direction.
  • the second arrangement direction Da2 may be a direction other than the a-axis direction and the m-axis direction
  • the second extension direction De2 may be a direction other than the a-axis direction and the m-axis direction.
  • the multiple surface regions 95 each have a width different from the width of the multiple first regions 14, and are arranged at a pitch different from the pitch of the multiple first regions 14.
  • the width of the surface region 95 may be less than the width of the multiple first regions 14, and the pitch of the surface region 95 may be less than the pitch of the multiple first regions 14.
  • the width of the surface region 95 may be less than the width of the multiple first regions 14, and the pitch of the surface region 95 may be greater than the pitch of the multiple first regions 14.
  • the width of the surface region 95 may be greater than the width of the multiple first regions 14, and the pitch of the surface region 95 may be less than the pitch of the multiple first regions 14.
  • the width of the surface region 95 may be greater than the width of the multiple first regions 14, and the pitch of the surface region 95 may be greater than the pitch of the multiple first regions 14.
  • the width of the multiple surface regions 95 may be approximately equal to the width of the multiple first regions 14.
  • the pitch of the multiple surface regions 95 may be approximately equal to the pitch of the multiple first regions 14.
  • the multiple surface regions 95 each have a width different from the width of the multiple second regions 15, and are arranged at a pitch different from the pitch of the multiple second regions 15.
  • the width of the surface region 95 may be less than the width of the multiple second regions 15, and the pitch of the surface region 95 may be less than the pitch of the multiple second regions 15.
  • the width of the surface region 95 may be less than the width of the multiple second regions 15, and the pitch of the surface region 95 may be greater than the pitch of the multiple second regions 15.
  • the width of the surface region 95 may be greater than the width of the second regions 15, and the pitch of the surface region 95 may be less than the pitch of the second regions 15.
  • the width of the surface region 95 may be greater than the width of the second regions 15, and the pitch of the surface region 95 may be greater than the pitch of the second regions 15.
  • the width of the surface regions 95 may be approximately equal to the width of the second regions 15.
  • the pitch of the surface regions 95 may be approximately equal to the pitch of the second regions 15.
  • the multiple surface layer regions 95 are formed at intervals from the multiple second regions 15 toward the first main surface 3.
  • the multiple surface layer regions 95 are preferably formed at intervals from the lower end (second layer 9) of the top layer 30 toward the first main surface 3, and face the multiple second layers 9 with at least a portion of the top layer 30 in between.
  • the multiple surface layer regions 95 may face either one or both of the second regions 15 and the second drift region 17 in the stacking direction.
  • the multiple surface regions 95 are made of random impurity regions introduced into the surface portion of the second layer 9 by a random injection method into the second layer 9 (see also FIG. 14). Therefore, the multiple surface regions 95 have a thickness in the direction along the top axis channel CHT that is less than the second region thickness TR2 of the second region 15. The thickness of the multiple surface regions 95 is less than the first region thickness TR1 of the first region 14.
  • the surface regions 95 unlike the second region 15 etc., do not have a gradual portion 22 having a thickness of 0.5 ⁇ m or more, and have a concentration gradient including a gradually increasing portion 20, a peak portion 21 and a gradually decreasing portion 23 within a range of 0.5 ⁇ m.
  • the surface regions 95 may have a peak value of a p-type impurity concentration of 1 ⁇ 10 cm ⁇ 3 or more and 1 ⁇ 10 cm ⁇ 3 or less.
  • the p-type impurity concentration of the multiple surface regions 95 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the surface region 95 may be the same as the trivalent element of the second region 15, etc., or may be a different species from the trivalent element of the second region 15, etc.
  • the trivalent element of the surface region 95 may be at least one of boron, aluminum, gallium, and indium.
  • the first pad electrode 92 is mechanically and electrically connected to the top layer 30 on the first main surface 3.
  • the first pad electrode 92 forms a JBS structure with the multiple surface layer regions 95 on the first main surface 3, and forms a Schottky junction with the region between the multiple surface layer regions 95 on the first main surface 3.
  • the layout restrictions and electrical characteristic restrictions of the JBS structure resulting from the layout of the superjunction structure SJ are alleviated.
  • the top layer 30 may be omitted.
  • FIG. 66 is a cross-sectional perspective view showing an SBD structure 93 according to the fifth embodiment.
  • the SBD structure 93 according to the fifth embodiment has a layout that is a modification of the layout of the multiple surface regions 95 according to the fourth embodiment. Specifically, the multiple surface regions 95 are arranged in stripes in the active region 10 that extend in a direction intersecting the second extension direction De2 of the multiple second regions 15.
  • the multiple surface regions 95 are arranged at intervals in the first arrangement direction Da1 of the first region 14 and extend in the first extension direction De1 of the first region 14.
  • the first arrangement direction Da1 is the m-axis direction
  • the first extension direction De1 is the a-axis direction.
  • the arrangement direction and extension direction of the multiple surface regions 95 are changed according to the first arrangement direction Da1 and first extension direction De1 of the multiple first regions 14. Therefore, the first arrangement direction Da1 may be the a-axis direction, and the first extension direction De1 may be the m-axis direction. Also, the first arrangement direction Da1 may be a direction other than the a-axis direction and the m-axis direction, and the first extension direction De1 may be a direction other than the a-axis direction and the m-axis direction.
  • the arrangement direction of the multiple surface regions 95 may be a direction other than the first arrangement direction Da1 and the second arrangement direction D2.
  • the extension direction of the multiple surface regions 95 may be a direction other than the first extension direction De1 and the second extension direction De2.
  • the multiple surface regions 95 may intersect both the multiple first regions 14 and the multiple second regions 15 in a planar view.
  • the angle (absolute value) between the extension direction of the surface region 95 and the second extension direction De2 may be greater than 0° and less than 90°.
  • the angle (absolute value) of the surface region 95 may have a value that belongs to any one of the ranges of greater than 0° and less than 18°, 18° or more and less than 36°, 36° or more and less than 54°, 54° or more and less than 72°, and 72° or more and less than 90°.
  • the angle (absolute value) of the surface region 95 may be set to a value that belongs to any one of the ranges of 30° ⁇ 5°, 45° ⁇ 5°, and 60° ⁇ 5°.
  • modified examples of the decorative pattern PT are shown. Below, an example is shown in which the modified decorative pattern PT is adopted in the SiC semiconductor device 1 according to the first embodiment, but the modified decorative pattern PT can also be applied to the SiC semiconductor device 1B according to the second embodiment and the SiC semiconductor device 1C according to the third embodiment.
  • Figure 67 is a perspective view showing a chip 2 together with a decorative pattern PT according to a first modified example.
  • the multiple first marks Mk1 were formed on a different side than the multiple second marks Mk2.
  • the multiple first marks Mk1 may be formed on the same side as the multiple second marks Mk2.
  • Figure 67 shows an example in which the multiple first marks Mk1 are formed on both the first side 5A and the second side 5B.
  • the multiple first marks Mk1 may have a width (first width W1) different from the width (second width W2) of the multiple second marks Mk2 on the second side 5B.
  • the multiple first marks Mk1 may have a pitch (first pitch P1) different from the pitch (second pitch P2) of the multiple second marks Mk2 on the second side 5B.
  • the multiple first marks Mk1 may overlap either one or both of the multiple second marks Mk2 and the multiple second spaces Sp2 in the thickness direction on the second side 5B.
  • the decorative pattern PT of the first modified example is realized by forming a plurality of first regions 14 extending in a direction intersecting both the first side 5A and the second side 5B.
  • the first extension direction De1 of the plurality of first regions 14 is a direction intersecting both the a-axis direction and the m-axis direction.
  • the second difference mark Md2 is not formed on the second side 5B.
  • Figure 68 is a perspective view showing a chip 2 together with a decorative pattern PT according to a second modified example.
  • the multiple second marks Mk2 were formed on a different side than the multiple first marks Mk1.
  • the multiple second marks Mk2 may be formed on the same side as the multiple first marks Mk1.
  • Figure 68 shows an example in which the multiple second marks Mk2 are formed on both the first side 5A and the second side 5B.
  • the second marks Mk2 may have a width (second width W2) different from the width (first width W1) of the first marks Mk1 on the first side 5A.
  • the second marks Mk2 may have a pitch (second pitch P2) different from the pitch (first pitch P1) of the first marks Mk1 on the first side 5A.
  • the second marks Mk2 may overlap either one or both of the first marks Mk1 and the first spaces Sp1 in the thickness direction on the first side 5A.
  • the decorative pattern PT of the second modified example is realized by forming a plurality of second regions 15 extending in a direction intersecting both the first side 5A and the second side 5B.
  • the second extension direction De2 of the plurality of second regions 15 is a direction intersecting both the a-axis direction and the m-axis direction.
  • Figure 69 is an oblique view showing a chip 2 together with a decorative pattern PT according to a third modified example.
  • the decorative pattern PT according to the third modified example has a form that combines the decorative pattern PT according to the first modified example and the decorative pattern PT according to the second modified example.
  • the multiple first marks Mk1 are exposed from both the first side 5A and the second side 5B
  • the multiple second marks Mk2 are exposed from both the first side 5A and the second side 5B.
  • a plurality of first regions 14 are formed extending in a direction intersecting the first side surface 5A and the second side surface 5B, and a plurality of second regions 15 are formed extending in a direction intersecting the first side surface 5A and the second side surface 5B.
  • the plurality of second regions 15 intersect or are perpendicular to the plurality of first regions 14.
  • Figure 70 is a perspective view showing a chip 2 together with a decorative pattern PT relating to the fourth modified example.
  • Figure 71 is a cross-sectional perspective view showing a column region 12 relating to the modified example.
  • Figure 72 is a cross-sectional view showing a main part of the outer periphery region 11 together with a column region 12 relating to the modified example.
  • Figure 71 shows a modified example of the column region 12 relating to the first basic form.
  • the column region 12 according to the modified example may have at least one of the multiple features shown in the first to twelfth embodiment examples.
  • the column region 12 according to the modified example may have a feature that combines multiple (two or more) features shown in the first to twelfth embodiment examples.
  • the multiple first marks Mk1 and the multiple second marks Mk2 may be formed on only one of the first side 5A (third side 5C) extending in the first direction X and the second side 5B (fourth side 5D) extending in the second direction Y.
  • FIG. 70 shows an example in which both the multiple first marks Mk1 and the multiple second marks Mk2 are formed on the second side 5B (fourth side 5D).
  • the multiple first marks Mk1 are formed in the lower area of the laminate 7 on the second side 5B in the same manner as in the above-mentioned embodiment.
  • the multiple second marks Mk2 are formed in the upper range of the laminated portion 7 on the second side surface 5B.
  • the multiple second marks Mk2 are arranged at intervals in the first direction X in the upper range so as to overlap the multiple first marks Mk1 in the stacking direction, and define multiple second spaces Sp2 each consisting of a part of the laminated portion 7 (second layer 9).
  • the multiple second marks Mk2 overlap with the multiple first marks Mk1 in a one-to-one correspondence in the stacking direction
  • the multiple second spaces Sp2 overlap with the multiple first spaces Sp1 in a one-to-one correspondence in the stacking direction.
  • the lower end of the second mark Mk2 may be formed at a distance from the lower end to the upper end of the second layer 9, facing the first mark Mk1 across a part (lower end) of the second layer 9.
  • the lower end of the second mark Mk2 may have an extension that crosses the boundary between the first layer 8 and the second layer 9 and is located within the first layer 8.
  • the extensions of the multiple second marks Mk2 are connected to the multiple first marks Mk1 in a one-to-one correspondence.
  • the multiple second marks Mk2 form a stripe pattern integrated with the multiple first marks Mk1.
  • the decorative pattern PT according to the fourth modified example is realized by matching both the second arrangement direction Da2 and the second extension direction De2 of the multiple second regions 15 with both the first arrangement direction Da1 and the first extension direction De1 of the multiple first regions 14.
  • the multiple second regions 15 are formed in the second layer 9 so as to overlap the multiple first regions 14 in a one-to-one correspondence in the stacking direction in both the active region 10 and the peripheral region 11.
  • the multiple first regions 14 extend in stripes in the first extension direction De1 (second extension direction De2) within the first layer 8.
  • the multiple first regions 14 define multiple first drift regions 16 that extend in stripes in the first extension direction De1 (second extension direction De2) within the first layer 8.
  • the multiple second regions 15 extend in stripes in the first extension direction De1 (second extension direction De2) within the second layer 9.
  • the multiple second regions 15 define multiple second drift regions 17 that extend in stripes in the first extension direction De1 (second extension direction De2) within the second layer 9.
  • the second regions 15, together with the first regions 14, form column regions 12 that extend in stripes in the first extension direction De1 (second extension direction De2) within the stack 7.
  • the column regions 12 define drift regions 13 that extend in stripes in the first extension direction De1 (second extension direction De2) within the stack 7.
  • first arrangement direction Da1 and the second arrangement direction Da2 are the a-axis direction
  • first extension direction De1 and the second extension direction De2 are the m-axis direction
  • first arrangement direction Da1 and the second arrangement direction Da2 may be the m-axis direction
  • first extension direction De1 and the second extension direction De2 may be the a-axis direction.
  • first extension direction De1 and the second extension direction De2 may be directions other than the a-axis direction and the m-axis direction.
  • a decorative pattern PT similar to the decorative pattern PT of the third modified example is formed by a plurality of column regions 12 extending in a stripe shape.
  • the field regions 38 are formed in a region on the first main surface 3 side of the striped column regions 12.
  • the field regions 38 extend along the first regions 14 and the second regions 15 in the portion extending in the first extension direction De1 (second extension direction De2).
  • the multiple field regions 38 intersect with the multiple first regions 14 and the multiple second regions 15 at the same locations in the portion extending in a direction intersecting the first extension direction De1 (second extension direction De2).
  • the multiple field regions 38 may be connected to the multiple second regions 15, or may be formed at a distance from the multiple second regions 15.
  • the decorative pattern PT is formed on the first to fourth side faces 5A to 5D.
  • a structure without the decorative pattern PT may be adopted.
  • the multiple first regions 14 and the multiple second regions 15 are formed in the laminated portion 7 at intervals inward from the first to fourth side faces 5A to 5D.
  • the multiple first regions 14 and the multiple second regions 15 may be formed in the active region 10 at intervals inward from the peripheral region 11.
  • one of the multiple first regions 14 and the multiple second regions 15 may be exposed from the first to fourth side surfaces 5A to 5D, and the other of the multiple first regions 14 and the multiple second regions 15 may be formed at intervals inward from the first to fourth side surfaces 5A to 5D.
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 each contain a SiC single crystal.
  • at least one or all of the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • a wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon.
  • Examples of single crystals of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga 2 O 3 ).
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26, and the top layer 30 may be made of the same type of single crystal or different types of single crystals.
  • the aforementioned channeling injection process (the process of injecting impurities into regions with sparse atomic rows) can also be applied to single crystals that form a cubic crystal.
  • the single crystal of the wide band gap semiconductor may be a cubic crystal or a hexagonal crystal.
  • these axial channels are formed by regions surrounded by atomic rows that are aligned along the low-index crystal axes of the cubic crystal axes.
  • the low-index crystal axis of a cubic crystal is a crystal axis in which the absolute values of "h", "k” and “l” in the Miller indices (h, k, l) are all 2 or less (preferably 1 or less).
  • the base layer 6, the first layer 8, the second layer 9, the buffer layer 26 and the top layer 30 may contain single crystal silicon.
  • the MIS structure 31 and the SBD structure 93 are formed individually on different chips 2.
  • the MIS structure 31 and the SBD structure 93 may be formed on one chip 2.
  • the SBD structure 93 may be electrically interposed between the source pad 47 (anode pad) and the drain pad 48 (cathode pad) as a freewheeling diode for the MIS structure 31.
  • an n-type base layer 6 is shown.
  • a p-type base layer 6 may be adopted.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.
  • a semiconductor device (1A, 1B, 1C) including a first layer (8) of a first conductivity type (n type) including a semiconductor single crystal and having a first axial channel (CH1) along the stacking direction, a second layer (9) of a first conductivity type (n type) including a semiconductor single crystal and having a second axial channel (CH2) along the stacking direction and stacked on the first layer (8), a first region (14) of a second conductivity type (p type) extending along the first axial channel (CH1) in the first layer (8) in a cross-sectional view and extending in a first extension direction (De1) in a planar view, and a second region (15) of a second conductivity type (p type) extending along the second axial channel (CH2) in the second layer (9) in a cross-sectional view and extending in a second extension direction (De2) intersecting the first extension direction (De1) so as to intersect the first region (14) in a planar view.
  • p-type second conductivity type
  • n-type semiconductor layer (7) having a main surface (3), an active region (10) set in the inner part of the main surface (3), an outer peripheral region (11) set in the peripheral part of the main surface (3), and a second conductivity type (p-type) column region (12) including a plurality of impurity regions (14, 15) formed in the semiconductor layer (7) at intervals in the horizontal direction along the main surface (3) and located in both the active region (10) and the outer peripheral region (11).
  • the semiconductor device (1A, 1B, 1C) according to any one of B2 to B6, wherein the first region (14) includes a first peak value (PA, 21A) at the upper end of the first layer (8) and a first gradual portion (22A) in which the impurity concentration gradually decreases at a gradual rate in a region of the first layer (8) lower than the first peak value (PA, 21A), and the second region (15) includes a second peak value (PB, 21B) at the upper end of the second layer (9) and a second gradual portion (22B) in which the impurity concentration gradually decreases at a gradual rate in a region of the second layer (9) lower than the second peak value (PB, 21B).
  • the first region (14) includes a first peak value (PA, 21A) at the upper end of the first layer (8) and a first gradual portion (22A) in which the impurity concentration gradually decreases at a gradual rate in a region of the first layer (8) lower than the first peak value (PA, 21A)
  • the side surfaces (5A to 5D) include a first side surface (5A, 5C) extending in a first direction (X) in a plan view, and a second side surface (5B, 5D) extending in a second direction (Y) intersecting the first direction (X) in a plan view
  • the decorative pattern (PT) includes at least one of the marks (Mk1, Mk2) formed on either or both of the first side surface (5A, 5C) and
  • [C5] The semiconductor device (1A, 1B, 1C) described in C4, in which the semiconductor layer (7) is made of a hexagonal crystal, the first direction (X) is one of the m-axis direction and the a-axis direction of the crystal orientations of the semiconductor layer (7), and the second direction (Y) is the other of the m-axis direction and the a-axis direction of the crystal orientations.
  • [C12] A semiconductor device (1A, 1B, 1C) according to C10 or C11, in which the first mark (Mk1) is formed at an interval from the upper end to the lower end of the first layer (8).
  • the first layer (8) has a first axial channel (CH1) along the stacking direction
  • the second layer (9) has a second axial channel (CH2) along the stacking direction
  • the first mark (Mk1) extends along the first axial channel (CH1) on the surface portion of the first side surface (5A, 5C)
  • the second mark (Mk2) extends along the second axial channel (CH2) on the surface portion of the second side surface (5B, 5D).
  • a semiconductor device (1A, 1B, 1C) according to any one of C10 to C12.
  • the semiconductor device (1A, 1B, 1C) according to any one of C10 to C14, wherein the first mark (Mk1) includes a first peak value (PA, 21A) on the upper end side of the first layer (8) and a first gradual portion (22A) in which the impurity concentration gradually decreases at a gradual rate in a region on the lower end side of the first layer (8) from the first peak value (PA, 21A), and the second mark (Mk2) includes a second peak value (PB, 21B) on the upper end side of the second layer (9) and a second gradual portion (22B) in which the impurity concentration gradually decreases at a gradual rate in a region on the lower end side of the second layer (9) from the second peak value (PB, 21B).
  • the first mark (Mk1) includes a first peak value (PA, 21A) on the upper end side of the first layer (8) and a first gradual portion (22A) in which the impurity concentration gradually decreases at a gradual rate in a region on the lower end side
  • Md1 a first different mark
  • p-type second conductivity type
  • Md2 a second different mark
  • p-type a second conductivity type
  • the impurity region (15) includes a peak value (PB, 21B) on the upper end side of the semiconductor layer (9) and a gradual portion (22B) in which the impurity concentration gradually decreases at a gradual rate of decrease in the region on the lower end side of the semiconductor layer (9) from the peak value (PB, 21B).
  • a lower semiconductor layer (8) having a lower axial channel (CH1) along the thickness direction (Z), and a lower impurity region (14) of a second conductivity type (p-type) extending along the lower axial channel (CH1) in the lower semiconductor layer (8), the semiconductor layer (9) being stacked on the lower semiconductor layer (8), and the impurity region (15) being formed in the semiconductor layer (9) so as to overlap the lower impurity region (14) in the stack
  • n-type first conductivity type
  • a contact region (34) of a second conductivity type (p-type) formed in a region different from the source region (33) along the gate structure (35) in the surface layer portion of the body region (32), and the source pad (47) is electrically connected to the contact region (34) on the main surface (3).

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
PCT/JP2023/046701 2022-12-28 2023-12-26 ＳｉＣ半導体装置 Ceased WO2024143380A1 (ja)

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DE112023004902.5T DE112023004902T5 (de) 2022-12-28 2023-12-26 Sic-halbleiterbauelement
CN202380089479.8A CN120457786A (zh) 2022-12-28 2023-12-26 SiC半导体装置
US19/251,831 US20250338546A1 (en) 2022-12-28 2025-06-27 Sic semiconductor device

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119611A (ja) * 2002-09-25 2004-04-15 Toshiba Corp 電力用半導体素子
US20150028351A1 (en) 2013-07-26 2015-01-29 Cree, Inc. Methods of Forming Buried Junction Devices in Silicon Carbide Using Ion Implant Channeling and Silicon Carbide Devices Including Buried Junctions
JP2021027138A (ja) * 2019-08-02 2021-02-22 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2021089916A (ja) * 2019-12-02 2021-06-10 富士電機株式会社 炭化珪素半導体装置の製造方法、炭化珪素基板の製造方法および炭化珪素基板
JP2022080586A (ja) * 2020-11-18 2022-05-30 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119611A (ja) * 2002-09-25 2004-04-15 Toshiba Corp 電力用半導体素子
US20150028351A1 (en) 2013-07-26 2015-01-29 Cree, Inc. Methods of Forming Buried Junction Devices in Silicon Carbide Using Ion Implant Channeling and Silicon Carbide Devices Including Buried Junctions
JP2021027138A (ja) * 2019-08-02 2021-02-22 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2021089916A (ja) * 2019-12-02 2021-06-10 富士電機株式会社 炭化珪素半導体装置の製造方法、炭化珪素基板の製造方法および炭化珪素基板
JP2022080586A (ja) * 2020-11-18 2022-05-30 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4645392A1

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JPWO2024143380A1 (https=) 2024-07-04

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