WO2024143379A1 - ＳｉＣ半導体装置 - Google Patents

ＳｉＣ半導体装置 Download PDF

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Publication number
WO2024143379A1
WO2024143379A1 PCT/JP2023/046700 JP2023046700W WO2024143379A1 WO 2024143379 A1 WO2024143379 A1 WO 2024143379A1 JP 2023046700 W JP2023046700 W JP 2023046700W WO 2024143379 A1 WO2024143379 A1 WO 2024143379A1
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region
trench
semiconductor layer
semiconductor device
column
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French (fr)
Japanese (ja)
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誠悟 森
佑紀 中野
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to DE112023004897.5T priority Critical patent/DE112023004897T5/de
Priority to JP2024567870A priority patent/JPWO2024143379A1/ja
Priority to CN202380089503.8A priority patent/CN120457787A/zh
Publication of WO2024143379A1 publication Critical patent/WO2024143379A1/ja
Priority to US19/252,254 priority patent/US20250324681A1/en
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Definitions

  • Patent document 1 discloses an electronic device having an impurity region introduced into a silicon carbide layer by channeling implantation.
  • the present disclosure provides a novel SiC semiconductor device.
  • the present disclosure provides a SiC semiconductor device including a first conductivity type SiC layer including a main surface and having an axial channel in the stacking direction, a trench formed in the main surface and defining a lower region between the main surface and a bottom of the SiC layer, and a column region of a second conductivity type formed in the lower region within the SiC layer and extending along the axial channel.
  • FIG. 9 is an enlarged cross-sectional view showing a trench structure according to the first embodiment.
  • FIG. 10 is a graph showing an example of the n-type concentration gradient in the high concentration region.
  • FIG. 11 is a graph showing a comparative example of the n-type concentration gradient in the high concentration region.
  • FIG. 12 is a graph showing an example of the p-type concentration gradient in the column region.
  • FIG. 13 is a perspective view showing the configuration of the outer circumferential area.
  • FIG. 14 is a cross-sectional view showing a main part of the outer circumferential region.
  • FIG. 15 is a cross-sectional view showing a main part of the outer circumferential region.
  • FIG. 16 is a schematic diagram showing a wafer used in the manufacture of a SiC semiconductor device.
  • FIG. 16 is a schematic diagram showing a wafer used in the manufacture of a SiC semiconductor device.
  • FIG. 18O is a cross-sectional perspective view showing a step subsequent to FIG. 18N.
  • FIG. 19A is a schematic diagram for explaining the crystal orientation measurement process.
  • FIG. 19B is a schematic diagram for explaining the crystal orientation measurement process.
  • FIG. 20A is a schematic diagram for explaining the ion implantation step.
  • FIG. 20B is a schematic diagram for explaining the ion implantation step.
  • FIG. 21 is a cross-sectional perspective view showing a trench structure according to the second embodiment.
  • FIG. 22 is a cross-sectional perspective view showing a trench structure according to the third embodiment.
  • FIG. 23 is a cross-sectional perspective view showing a trench structure according to the fourth embodiment.
  • FIG. 24 is a cross-sectional perspective view showing a SiC semiconductor device according to a first modification.
  • FIG. 25 is a cross-sectional perspective view showing a SiC semiconductor device according to a second modification.
  • SiC semiconductor device 1 includes chip 2 including SiC single crystal.
  • Chip 2 may be referred to as a "SiC chip” or a “semiconductor chip".
  • chip 2 is made of hexagonal SiC single crystal and is formed in a rectangular parallelepiped shape.
  • the hexagonal SiC single crystal has multiple polytypes including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, 6H-SiC single crystal, etc.
  • chip 2 is made of 4H-SiC single crystal, but chip 2 may be made of other polytypes.
  • the second axis channel C2 is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a planar view. It is preferable that the second axis channel C2 is a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • the outer peripheral surface 11 has an outer peripheral depth DO.
  • the outer peripheral depth DO may be 0.1 ⁇ m or more and 2 ⁇ m or less.
  • the outer peripheral depth DO may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the outer peripheral depth DO is preferably 0.1 ⁇ m or more and 1.5 ⁇ m or less.
  • the high concentration region 15 extends from the outer periphery region 9 towards the first to fourth side faces 5A to 5D and is exposed from the first to fourth side faces 5A to 5D.
  • the high concentration region 15 may be formed in the semiconductor layer 7 with a space inward from the first to fourth side faces 5A to 5D.
  • the peripheral portion of the high concentration region 15 may be located in the active region 8 or in the outer periphery region 9.
  • the high concentration region 15 has an upper end located on the upper end side of the semiconductor layer 7, and a lower end located on the lower end side of the semiconductor layer 7.
  • the upper end of the high concentration region 15 is located in a region on the upper end side of the semiconductor layer 7 relative to the intermediate part of the thickness range of the semiconductor layer 7, and the lower end of the high concentration region 15 is located in a region on the lower end side of the semiconductor layer 7 relative to the intermediate part of the thickness range of the semiconductor layer 7.
  • the distance between the lower end of the semiconductor layer 7 and the lower end of the high concentration region 15 may have a value that belongs to any one of the following ranges: more than 0 ⁇ m and not more than 1 ⁇ m, 1 ⁇ m or more and not more than 2 ⁇ m, 2 ⁇ m or more and not more than 3 ⁇ m, 3 ⁇ m or more and not more than 4 ⁇ m, and 4 ⁇ m or more and not more than 5 ⁇ m.
  • the high concentration region 15 is made of a p-type channeling region that extends along the second axis channel C2 in the semiconductor layer 7 in a cross-sectional view.
  • the high concentration region 15 is made of an impurity region that is introduced parallel or nearly parallel to the region (second axis channel C2) surrounded by the atomic rows along the low-index crystal axis in the semiconductor layer 7, and extends at an angle with respect to the first main surface 3.
  • the high concentration region 15 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the n-type impurity concentration of the high concentration region 15 is preferably adjusted with at least one pentavalent element.
  • the n-type impurity concentration of the high concentration region 15 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • the high concentration region 15 preferably contains a pentavalent element other than nitrogen and phosphorus.
  • the n-type impurity concentration of the high concentration region 15 is preferably adjusted with at least one of arsenic, antimony, and bismuth. In view of availability, the n-type impurity concentration of the high concentration region 15 is preferably adjusted with arsenic or antimony.
  • Figure 10 is a graph (simulation) showing an example of the n-type concentration gradient of the high concentration region 15.
  • Figure 11 is a graph (simulation) showing a comparative example of the n-type concentration gradient of the high concentration region 15.
  • the vertical axis indicates the n-type impurity concentration of the high concentration region 15, and the horizontal axis indicates the depth along the second axis channel C2 with the first main surface 3 as the reference (zero point).
  • high concentration region 15 a region having an n-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more is defined as high concentration region 15 and is shown as a graph.
  • the values of impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of high concentration region 15 based on the concentration gradient, and are not shown with the intention of uniquely limiting the configuration of high concentration region 15.
  • the impurity concentration, thickness, etc. are adjusted to various values depending on the implantation conditions of the pentavalent element (dose amount, implantation temperature, implantation energy, etc.), etc.
  • the dose of the pentavalent element is 1 ⁇ 10 13 cm ⁇ 2 .
  • the thickness of the semiconductor layer 7 is about 5 ⁇ m.
  • the concentration gradient when the high concentration region 15 is formed by implantation energy of 1500 KeV or more and 2500 KeV or less is shown by a dashed line.
  • the random direction is a direction (e.g., vertical direction Z) that is not parallel (almost parallel) to the second axial channel C2.
  • the dose amount of the pentavalent element is 1 ⁇ 10 13 cm ⁇ 2 .
  • the thickness of the semiconductor layer 7 is about 5 ⁇ m.
  • the concentration gradient when the high concentration region 15 is formed by implantation energy of 1500 KeV or more and 2500 KeV or less is indicated by a dashed line.
  • the first gradual section 18 is formed in a region closer to the lower end than the first peak section 17, and is a section where the impurity concentration gradually decreases at a relatively gradual rate of decrease.
  • the first gradual section 18 is a section that maintains a constant n-type impurity concentration in a certain depth range, and forms the main body of the high concentration region 15.
  • the n-type impurity concentration of the first gradual section 18 gradually decreases in a concentration range that is less than the n-type impurity concentration of the first peak section 17.
  • the first gradual portion 18 is defined by a portion having a concentration drop rate of 50% or less in a thickness range of at least 0.5 ⁇ m.
  • the first gradual portion 18 has a thickness of 0.8 ⁇ m or more and 1.1 ⁇ m or less, and has a concentration drop rate of 50% or less in that thickness range.
  • the thickness (depth) of the high concentration region 15 increases with increasing injection energy.
  • the depth position of the upper end of the high concentration region 15 relative to the first main surface 3 increases with increasing injection energy.
  • the thicknesses of the first gradually increasing portion 16, the first peak portion 17, the first gradual portion 18, and the first gradually decreasing portion 19 increase with increasing injection energy.
  • the first peak value P1 of the high concentration region 15 decreases with increasing injection energy. This is because the pentavalent element is introduced into deep regions with increasing injection energy, increasing the n-type impurity concentration in those deep regions.
  • the body region 20 is composed of a random region introduced into the surface layer of the semiconductor layer 7 by a random injection method into the semiconductor layer 7. Therefore, unlike the high concentration region 15, the body region 20 does not have a slow portion such as the first slow portion 18.
  • the body region 20 has a thickness less than the thickness of the high concentration region 15 in the direction along the second axial channel C2.
  • Each trench structure 25 has a trench width WT in the arrangement direction and a trench depth DT in the vertical direction Z.
  • the trench width WT is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the trench width WT is preferably less than the thickness of the high concentration region 15.
  • the trench width WT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench depth DT is preferably greater than the trench width WT.
  • each of the multiple trench structures 25 has an aspect ratio DT/WT that extends in a vertically elongated columnar shape.
  • the aspect ratio DT/WT is the ratio of the trench width WT to the trench depth DT.
  • the trench depth DT may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the trench pitch PT may have a value in any one of the ranges of 0.1 ⁇ m to 0.25 ⁇ m, 0.25 ⁇ m to 0.5 ⁇ m, 0.5 ⁇ m to 0.75 ⁇ m, 0.75 ⁇ m to 1 ⁇ m, 1 ⁇ m to 1.5 ⁇ m, 1.5 ⁇ m to 2 ⁇ m, 2 ⁇ m to 2.5 ⁇ m, 2.5 ⁇ m to 3 ⁇ m, 3 ⁇ m to 3.5 ⁇ m, 3.5 ⁇ m to 4 ⁇ m, 4 ⁇ m to 4.5 ⁇ m, and 4.5 ⁇ m to 5 ⁇ m.
  • the trench pitch PT is preferably 0.5 ⁇ m to 1.5 ⁇ m.
  • the insulating film 27 covers the wall surface of the trench 26.
  • the insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the insulating film 27 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the insulating film 27 includes a silicon oxide film made of an oxide of the chip 2.
  • the buried electrode 28 is buried in the trench 26 and faces the channel across the insulating film 27.
  • the buried electrode 28 faces the high concentration region 15 and the body region 20 across the insulating film 27.
  • the buried electrode 28 may include p-type or n-type conductive polysilicon.
  • both ends of the multiple column regions 30 may be located on the inner side of the active region 8 relative to both ends of the multiple trench structures 25. With respect to the second direction Y, both ends of the multiple column regions 30 may be located on the peripheral side of the active region 8 relative to both ends of the multiple trench structures 25.
  • the multiple column regions 30 have upper ends located on the bottom wall side of the trench structure 25 and lower ends located on the lower end side of the semiconductor layer 7.
  • the upper ends of the multiple column regions 30 are located in a region on the bottom wall side of the trench structure 25 relative to the intermediate part of the thickness range of the lower region 7a
  • the lower ends of the multiple column regions 30 are located in a region on the lower end side of the semiconductor layer 7 relative to the intermediate part of the thickness range of the lower region 7a.
  • the upper ends of the multiple column regions 30 are formed at intervals on the lower end side of the semiconductor layer 7 relative to the depth position of the outer circumferential surface 11.
  • the upper ends of the multiple column regions 30 are formed at intervals on the lower end side of the semiconductor layer 7 from the bottom walls of the multiple trench structures 25, and face the multiple trench structures 25 with a portion of the semiconductor layer 7 in between.
  • the upper ends of the multiple column regions 30 face the multiple trench structures 25 with a portion of the high concentration region 15 in between.
  • the upper ends of the multiple column regions 30 are electrically connected to the relatively high concentration region 15.
  • the upper ends of the multiple column regions 30 may also be connected to the bottom walls of the multiple trench structures 25.
  • the intermediate distance between the bottom walls of the trench structures 25 and the upper ends of the column regions 30 may be 0 ⁇ m or more and 1 ⁇ m or less.
  • the intermediate distance may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less.
  • the lower ends of the multiple column regions 30 are pulled out into the semiconductor layer 7 across the bottom of the high concentration region 15.
  • the multiple column regions 30 include a portion located in the region between the bottom of the high concentration region 15 and the bottom walls of the multiple trench structures 25, and a portion located in the region between the lower end of the semiconductor layer 7 and the bottom of the high concentration region 15.
  • the lower ends of the multiple column regions 30 are electrically connected to the relatively low concentration semiconductor layer 7.
  • the lower ends of the multiple column regions 30 are formed at intervals from the lower end of the semiconductor layer 7 toward the bottom side of the high concentration region 15, and face the base layer 6 across a part of the semiconductor layer 7.
  • the lower ends of the multiple column regions 30 may cross the boundary between the semiconductor layer 7 and the base layer 6 and be located within the base layer 6.
  • the lower ends of the multiple column regions 30 may cross the bottom of the high concentration region 15 within the base layer 6.
  • the bottom distance between the bottom end of the semiconductor layer 7 and the bottom ends of the plurality of column regions 30 may be 0 ⁇ m or more and 2 ⁇ m or less.
  • the bottom distance may have a value that falls within any one of the ranges of 0 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, and 1.5 ⁇ m or more and 2 ⁇ m or less.
  • the lower ends of the multiple column regions 30 may be formed at intervals from the bottom of the high-concentration region 15 toward the bottom wall of the trench structure 25.
  • the multiple column regions 30 may be electrically connected to the high-concentration region 15 at both their upper and lower ends.
  • the multiple column regions 30 are made up of channeling regions that extend along the second axis channel C2 in a cross-sectional view.
  • the column regions 30 are impurity regions that are introduced parallel or nearly parallel to the region (second axis channel C2) surrounded by atomic rows along the low-index crystal axis in the semiconductor layer 7, and extend at an angle with respect to the first main surface 3.
  • the plurality of column regions 30 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration (peak value) of the column region 30 may be higher than the p-type impurity concentration (peak value) of the body region 20.
  • the p-type impurity concentration (peak value) of the column region 30 may be lower than the p-type impurity concentration (peak value) of the body region 20.
  • the multiple column regions 30 each have a column width WC in the arrangement direction.
  • the column width WC may be approximately equal to the trench width WT.
  • the column width WC may be greater than the trench width WT.
  • the column width WC may be less than the trench width WT.
  • the column width WC may be less than the trench depth DT.
  • the column width WC may be greater than the trench depth DT.
  • the column width WC is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the column width WC is preferably less than the thickness of the high concentration region 15.
  • the column width WC may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • the column width WC may have a value that falls within any one of the following ranges: 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the multiple column regions 30 each have a column thickness TC (region depth).
  • the column thickness TC is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the column thickness TC is preferably less than the thickness of the high concentration region 15. It is particularly preferable that the column thickness TC is equal to or greater than the trench depth DT. It is preferable that the column thickness TC is greater than the trench width WT. It is particularly preferable that the column thickness TC is greater than the trench depth DT. Of course, the column thickness TC may be less than the trench depth DT.
  • the column thickness TC may be 1 to 5 times the trench depth DT.
  • the ratio TC/DT of the column thickness TC to the trench depth DT may be in any one of the following ranges: 1 to 1.5, 1.5 to 2, 2 to 2.5, 2.5 to 3, 3 to 3.5, 3.5 to 4, 4 to 4.5, and 4.5 to 5.
  • the column thickness TC is preferably greater than the column width WC.
  • each of the multiple column regions 30 has an aspect ratio TC/WC that extends in a vertically elongated columnar shape along the second axial channel C2.
  • the aspect ratio TC/WC is the ratio of the column thickness TC to the column width WC. It is preferable that the column thickness TC is 1 ⁇ m or more and 5 ⁇ m or less.
  • the column thickness TC may have a value falling within any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the column pitch PC is preferably less than the column thickness TC.
  • the column pitch PC is preferably less than the trench depth DT.
  • the column pitch PC is preferably less than the second thickness T2 of the semiconductor layer 7.
  • the column pitch PC is preferably less than the thickness of the high concentration region 15.
  • the column pitch PC may be 0.1 ⁇ m or more and 5 ⁇ m or less.
  • FIG. 12 is a graph showing an example of the p-type concentration gradient in the column region 30.
  • the vertical axis indicates the p-type impurity concentration in the column region 30, and the horizontal axis indicates the depth along the second axis channel C2 with the bottom wall of the trench structure 25 as the reference (zero point).
  • a region having a p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more is defined as the column region 30 and is shown as a graph.
  • the values of the impurity concentration, thickness, etc. shown below are examples for explaining the basic configuration of the column region 30 based on the concentration gradient, and are not shown with the intention of uniquely limiting the configuration of the column region 30.
  • the impurity concentration, thickness, etc. are adjusted to various values depending on the implantation conditions of the trivalent element (dose amount, implantation temperature, implantation energy, etc.), etc.
  • the column region 30 has a thickness of 2.5 ⁇ m or more and 2.8 ⁇ m or less, and has an upper end spaced from the bottom wall of the trench structure 25 toward the lower end of the semiconductor layer 7, and a lower end spaced from the lower end of the semiconductor layer 7 toward the upper end.
  • the second peak portion 32 is a portion having a second peak value P2 (maximum value) of the p-type impurity concentration.
  • the second peak portion 32 is also a convex main concentration transition portion including a series of concentration changes (inflection points) where the p-type impurity concentration changes from an increase (increasing trend) to a decrease (decreasing trend).
  • the second peak portion 32 is electrically connected to the high concentration region 15.
  • the second peak value P2 is located closer to the lower end of the semiconductor layer 7 than the first peak value P1 of the high concentration region 15.
  • the depth position of the upper end of the column region 30 relative to the bottom wall of the trench structure 25 decreases as the implantation energy decreases.
  • the thicknesses of the second increasing portion 31, the second peak portion 32, the second gradual portion 33, and the second decreasing portion 34 decrease as the implantation energy decreases.
  • the second peak value P2 of the column region 30 increases as the implantation energy decreases. This is because the introduction of trivalent elements is inhibited in shallow regions as the implantation energy decreases.
  • the SiC semiconductor device 1 includes a plurality of p-type intermediate regions 36 that are respectively interposed in the semiconductor layer 7 in the regions between the bottom walls of the plurality of trench structures 25 and the plurality of column regions 30.
  • the plurality of intermediate regions 36 are interposed in the region between the bottom wall of one trench structure 25 and the upper end of one column region 30.
  • the intermediate regions 36 reduce the electric field with respect to the trench structure 25.
  • the intermediate regions 36 do not necessarily need to form a charge balance with the drift regions 35.
  • the intermediate regions 36 may form a plurality of pn junctions having a charge balance with the drift regions 35.
  • the intermediate regions 36 are random regions introduced into the surface layers of the drift regions 35 by a random injection method into the semiconductor layer 7.
  • the intermediate regions 36 have a thickness less than the thickness of the column regions 30 in the direction along the second axial channel C2.
  • the intermediate regions 36 do not have a second slow portion 33 having a thickness of 0.5 ⁇ m or more in either direction along the second axial channel C2.
  • the p-type impurity concentration (peak value) of the intermediate region 36 may be higher than the p-type impurity concentration (peak value) of the column region 30.
  • the p-type impurity concentration (peak value) of the intermediate region 36 may be lower than the p-type impurity concentration (peak value) of the column region 30.
  • the p-type impurity concentration of the intermediate region 36 is preferably adjusted by at least one trivalent element.
  • the trivalent element of the intermediate region 36 may be the same as the trivalent element of the column region 30, or may be a different species from the trivalent element of the column region 30.
  • the trivalent element of the intermediate region 36 may be at least one of boron, aluminum, gallium, and indium.
  • the SiC semiconductor device 1 includes a plurality of source regions 37 formed on both sides of a plurality of trench structures 25 in a surface layer portion of the first main surface 3 (active surface 10).
  • the plurality of source regions 37 are formed in a surface layer portion of the body region 20.
  • the plurality of source regions 37 have a higher n-type impurity concentration (peak value) than that of the semiconductor layer 7.
  • the n-type impurity concentration of the plurality of source regions 37 is higher than that of the high concentration region 15.
  • the plurality of source regions 37 may have an n-type impurity concentration of 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less as a peak value.
  • the SiC semiconductor device 1 includes a plurality of contact regions 38 formed in the surface portion of the first main surface 3 (active surface 10) in the region between the plurality of trench structures 25.
  • the plurality of contact regions 38 are formed in the surface portion of the body region 20.
  • the multiple contact regions 38 are interposed between the multiple source regions 37 adjacent to each other, and extend in a band shape in the extension direction of the multiple trench structures 25.
  • the multiple contact regions 38 are formed at intervals from the bottom of the body region 20 toward the active surface 10, and face the drift region 35 (semiconductor layer 7/high concentration region 15) directly below, sandwiching a part of the body region 20 in the stacking direction.
  • the multiple contact regions 38 may face multiple intermediate regions 36 in the horizontal direction.
  • the well region 39 is pulled out from the surface portion of the outer peripheral surface 11 toward the first to fourth connection surfaces 12A to 12D and extends along the surface portions of the first to fourth connection surfaces 12A to 12D.
  • the well region 39 is electrically connected to the body region 20 at the surface portion of the active surface 10.
  • the well region 39 is formed at a distance from the lower end of the semiconductor layer 7 toward the outer circumferential surface 11, and faces the base layer 6 across a portion of the semiconductor layer 7. Specifically, the well region 39 is formed at a distance from the bottom of the high concentration region 15 toward the outer circumferential surface 11, and is located closer to the bottom of the high concentration region 15 than the bottom wall of the trench structure 25. The well region 39 forms a pn junction with the semiconductor layer 7 (high concentration region 15).
  • the well region 39 is composed of a random region introduced into the surface layer of the semiconductor layer 7 by a random injection method into the semiconductor layer 7.
  • the well region 39 has a thickness less than the thickness of the high concentration region 15 in the direction along the second axial channel C2.
  • the thickness of the well region 39 is also less than the thickness of the column region 30.
  • the well region 39 does not have a gentle portion having a thickness of 0.5 ⁇ m or more.
  • the well region 39 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the well region 39 has a p-type impurity concentration lower than the p-type impurity concentration of the contact region 38.
  • the p-type impurity concentration of the well region 39 may be higher than the p-type impurity concentration of the body region 20. Of course, the p-type impurity concentration of the well region 39 may be lower than the body region 20. The p-type impurity concentration of the well region 39 may be approximately equal to the p-type impurity concentration of the intermediate region 36. Of course, the p-type impurity concentration of the well region 39 may be higher than the p-type impurity concentration of the intermediate region 36, or may be lower than the p-type impurity concentration of the intermediate region 36.
  • the p-type impurity concentration of the well region 39 is preferably adjusted by at least one type of trivalent element.
  • the trivalent element of the well region 39 may be the same type as the trivalent element of the column region 30, or may be a different type from the trivalent element of the column region 30.
  • the trivalent element of the well region 39 may be at least one type of boron, aluminum, gallium, and indium.
  • the multiple field regions 40 are arranged at intervals from the periphery of the active surface 10 (first to fourth connection surfaces 12A to 12D) and the periphery of the chip 2 (first to fourth side surfaces 5A to 5D). Specifically, the multiple field regions 40 are arranged at intervals from the well region 39 to the periphery side of the outer circumferential surface 11.
  • the multiple field regions 40 are formed in the semiconductor layer 7 at intervals from the lower end of the semiconductor layer 7 toward the outer circumferential surface 11, and form a pn junction with the semiconductor layer 7. It is preferable that the multiple field regions 40 have a bottom located on the outer circumferential surface 11 side relative to the intermediate part of the thickness range of the semiconductor layer 7. It is preferable that the multiple field regions 40 are formed at intervals from the bottom of the high concentration region 15 toward the outer circumferential surface 11, and form a pn junction with the high concentration region 15.
  • the field regions 40 are formed at intervals from the column regions 30 toward the periphery of the chip 2. Therefore, the field regions 40 do not face the column regions 30 in the stacking direction.
  • the field regions 40 are located closer to the bottom of the semiconductor layer 7 (high concentration region 15) than the bottom wall of the trench structure 25.
  • the multiple field regions 40 are random regions introduced into the surface layer of the semiconductor layer 7 by a random injection method into the semiconductor layer 7.
  • the multiple field regions 40 have a thickness less than the thickness of the high concentration region 15 in the direction along the second axial channel C2.
  • the thickness of the multiple field regions 40 is less than the thickness of the column region 30.
  • the field regions 40 do not have a gentle portion having a thickness of 0.5 ⁇ m or more.
  • the field regions 40 may have a peak p-type impurity concentration of 1 ⁇ 10 15 cm ⁇ 3 or more and 1 ⁇ 10 18 cm ⁇ 3 or less.
  • the p-type impurity concentration of the field region 40 may be approximately equal to the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the field regions 40 may be higher than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the field regions 40 may be lower than the p-type impurity concentration of the body region 20.
  • the p-type impurity concentration of the multiple field regions 40 is preferably adjusted by at least one type of trivalent element.
  • the trivalent element of the field region 40 may be the same type as the trivalent element of the column region 30, or may be a different type from the trivalent element of the column region 30.
  • the trivalent element of the field region 40 may be at least one type of boron, aluminum, gallium, and indium.
  • the field regions 40 preferably have a width different from the column width WC of the column region 30.
  • the electric field relaxation effect of the field regions 40 is preferably adjusted separately from the column regions 30. It is particularly preferable that the width of the field regions 40 is greater than the column width WC.
  • the width of the field regions 40 may be smaller than the column width WC.
  • the width of the column region 30 may be approximately equal to the column width WC.
  • the SiC semiconductor device 1 includes an interlayer insulating film 41 that covers the first main surface 3.
  • the interlayer insulating film 41 may be referred to as an "insulating film,” an "interlayer film,” an “intermediate insulating film,” or the like.
  • the interlayer insulating film 41 has a layered structure that includes a first insulating film 42 and a second insulating film 43.
  • the first insulating film 42 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 42 includes a silicon oxide film made of an oxide of the chip 2 (semiconductor layer 7).
  • the first insulating film 42 selectively covers the first main surface 3 in the active region 8 and the peripheral region 9. Specifically, the first insulating film 42 selectively covers the active surface 10, the peripheral surface 11, and the first to fourth connection surfaces 12A to 12D. The first insulating film 42 is connected to the insulating film 27 in the active surface 10, exposing the buried electrode 28.
  • the sidewall structure 45 may have a portion that extends in a film shape along the outer peripheral surface 11, and a portion that extends in a film shape along the first to fourth connection surfaces 12A to 12D.
  • the sidewall structure 45 is formed at a distance from the innermost field region 40 toward the active surface 10, and faces the well region 39 in the horizontal direction and stacking direction, sandwiching the first insulating film 42 between them.
  • the sidewall structure 45 may face the body region 20, sandwiching the first insulating film 42 between them.
  • the injection angle of the pentavalent element into the semiconductor layer 7 is controlled, and the pentavalent element is introduced into the semiconductor layer 7 along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) with a predetermined injection energy (also refer to FIG. 10).
  • a predetermined injection energy also refer to FIG. 10
  • either or both of the injection angle of the pentavalent element into the semiconductor layer 7 and the inclination angle of the semiconductor layer 7 with respect to the injection angle of the pentavalent element are adjusted.
  • the implantation energy of the pentavalent element may be 100 KeV or more and 2000 KeV or less.
  • the implantation energy may have a value that belongs to any one of the following ranges: 100 KeV or more and 250 KeV or less, 250 KeV or more and 500 KeV or less, 500 KeV or more and 750 KeV or less, 750 KeV or more and 1000 KeV or less, 1000 KeV or more and 1250 KeV or less, 1250 KeV or more and 1500 KeV or less, 1500 KeV or more and 1750 KeV or less, and 1750 KeV or more and 2000 KeV or less.
  • the second mask 72 is preferably an organic mask (resist mask).
  • the second mask 72 is disposed on the upper end of the semiconductor layer 7, and has a plurality of second openings 72a that expose the plurality of trenches 26 in a one-to-one correspondence.
  • the second openings 72a are formed at intervals in the first direction X, and are each partitioned into bands extending in the second direction Y. In other words, the second openings 72a have an extension direction that extends along the off-direction Do in a planar view.
  • the injection temperature for the column region 30 may be approximately equal to the injection temperature for the high concentration region 15, or may be different from the injection temperature for the high concentration region 15.
  • the injection temperature for the column region 30 may be equal to or higher than the injection temperature for the high concentration region 15.
  • the injection temperature for the column region 30 may be lower than the injection temperature for the high concentration region 15.
  • the injection angle of the trivalent element is preferably set within a range of ⁇ 2° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°). It is particularly preferable that the injection angle of the trivalent element is set within a range of ⁇ 1° with respect to the axis along the second axial channel C2 (in this embodiment, the c-axis of the SiC single crystal) as the reference (0°).
  • the process for forming the plurality of intermediate regions 36 includes a process for introducing a trivalent element into the semiconductor layer 7 with a predetermined injection energy in a direction intersecting the second axial channel C2 (off angle ⁇ o) by a random injection method through a third mask 73.
  • the trivalent element is introduced into the semiconductor layer 7 (high concentration region 15) through the wall surfaces (side walls and bottom walls) of the plurality of trenches 26 from the plurality of third openings 73a.
  • the trivalent element may be introduced into the semiconductor layer 7 once or multiple times.
  • the trivalent element When the trivalent element is introduced multiple times, the trivalent element may be introduced in multiple stages at different depth positions in the semiconductor layer 7 with multiple implantation energies.
  • the trivalent element may be introduced into the semiconductor layer 7 (high concentration region 15) through the wall surfaces (side walls and bottom walls) of the multiple trenches 26 by oblique ion implantation. Referring to FIG. 18J, after the process of forming the multiple intermediate regions 36, the third mask 73 is removed.
  • a process for forming a buried electrode 28 is performed (step S15 in FIG. 17).
  • This process includes a process for forming a base electrode film 74 on the insulating film 27.
  • the base electrode film 74 includes conductive polysilicon.
  • the base electrode film 74 backfills the multiple trenches 26 and covers the upper end of the semiconductor layer 7.
  • the base electrode film 74 may be formed by a CVD method.
  • unnecessary portions of the buried electrode 28 are removed by an etching method.
  • the unnecessary portions of the buried electrode 28 are removed until the insulating film 27 is exposed.
  • the etching method may be either or both of a wet etching method and a dry etching method. As a result, a plurality of buried electrodes 28 are buried in the plurality of trenches 26, respectively, and a plurality of trench structures 25 are formed.
  • gate pad 50, gate wiring 51, and source pad 52 are formed by depositing a metal film on interlayer insulating film 41 by sputtering, and then shaping the metal film into a predetermined layout by etching through a mask (not shown) having a predetermined layout.
  • a process for forming the drain pad 53 is carried out (step S18 in FIG. 17).
  • the drain pad 53 is formed by depositing a metal film on the second wafer main surface 62 by a sputtering method.
  • the wafer 60 is then cut along a number of planned cutting lines 66 (step S19 in FIG. 17).
  • a number of SiC semiconductor devices 1 are manufactured from a single wafer 60.
  • the multiple trench structures 25 each include a trench 26, an insulating film 27, a buried electrode 28, and a buried insulator 80.
  • the trench 26 has a form similar to that of the first embodiment.
  • the insulating film 27 is formed at a distance from the first main surface 3 (active surface 10) to the bottom wall side of the trench 26, exposing the surface portion of the first main surface 3 (active surface 10) at the opening end of the trench 26. It is preferable that the upper end of the insulating film 27 is located on the first main surface 3 side relative to the middle part of the depth range of the trench 26.
  • the buried electrode 28 is buried in the trench 26 at a distance from the first main surface 3 (active surface 10) toward the bottom wall of the trench 26, and defines an open recess that is recessed toward the bottom wall of the trench 26 at the opening end of the trench 26.
  • the buried electrode 28 exposes the surface portion of the first main surface 3 (active surface 10) and the upper end of the insulating film 27 at the opening end of the trench 26. It is preferable that the upper end of the buried electrode 28 is located on the first main surface 3 side relative to the middle part of the depth range of the trench 26.
  • the upper end of the buried insulator 80 is preferably located on the first main surface 3 side relative to the intermediate portion of the depth range of the trench 26.
  • the buried insulator 80 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.
  • the buried insulator 80 preferably includes a silicon oxide film.
  • the aforementioned multiple source regions 37 are each formed in a region between multiple adjacent trench structures 25 in the surface layer portion of the first main surface 3 (active surface 10).
  • the multiple source regions 37 are arranged at intervals along the multiple trench structures 25 so as to be connected to the multiple trench structures 25 located on both sides.
  • the multiple source regions 37 arranged along one sidewall of the trench structure 25 face the multiple source regions 37 arranged along the other sidewall of the trench structure 25 in a one-to-one correspondence.
  • the multiple source regions 37 are arranged in a matrix in a planar view.
  • the multiple source regions 37 on one side may face the regions between the multiple source regions 37 on the other side in a one-to-one correspondence.
  • the multiple source regions 37 may be arranged in a staggered pattern in a planar view.
  • the multiple source regions 37 have portions exposed from the sidewall of the trench 26 at the opening end of the trench 26, and face the buried electrode 28 and the buried insulator 80 with the insulating film 27 between them.
  • the aforementioned contact regions 38 are formed in the regions between adjacent trench structures 25 in the surface layer of the first main surface 3 (active surface 10).
  • the contact regions 38 are arranged at intervals along the trench structures 25 so as to be connected to the trench structures 25 located on both sides.
  • the multiple contact regions 38 are arranged alternately with the multiple source regions 37 along the multiple trench structures 25. More specifically, the multiple contact regions 38 arranged along one sidewall of the trench structure 25 face the multiple contact regions 38 arranged along the other sidewall of the trench structure 25 in a one-to-one correspondence. In addition, the multiple source regions 37 are arranged in a matrix in a planar view.
  • the multiple contact regions 38 on one side may face the regions between the multiple source regions 37 on the other side (i.e., the multiple source regions 37) in a one-to-one correspondence.
  • the multiple contact regions 38 may be arranged in a staggered pattern in a planar view.
  • the multiple contact regions 38 have portions exposed from the sidewall of the trench 26 at the opening end of the trench 26, and face the buried electrode 28 and the buried insulator 80 with the insulating film 27 between them.
  • the aforementioned interlayer insulating film 41 has a layered structure including a first insulating film 42 and a second insulating film 43.
  • the first insulating film 42 selectively covers the active surface 10, the outer peripheral surface 11, and the first to fourth connecting surfaces 12A to 12D.
  • the first insulating film 42 covers the peripheral portion of the active surface 10 and exposes the multiple trench structures 25 collectively in the inner portion of the active surface 10. Specifically, the first insulating film 42 is connected to the insulating film 27 at both ends of the multiple trench structures 25, exposing the buried electrodes 28. The first insulating film 42 also covers the outer peripheral surface 11 and the first to fourth connection surfaces 12A to 12D in the same manner as in the first embodiment.
  • the second insulating film 43 selectively covers the active surface 10, the outer peripheral surface 11, and the first to fourth connection surfaces 12A to 12D with the first insulating film 42 in between.
  • the second insulating film 43 covers the peripheral portion of the active surface 10 and exposes the multiple trench structures 25 collectively in the inner portion of the active surface 10.
  • the second insulating film 43 penetrates into the trenches 26 from above the first main surface 3 (active surface 10) at both ends of the multiple trench structures 25, and is connected to the buried insulator 80 within the trenches 26.
  • the interlayer insulating film 41 includes a plurality of contact openings 44 (not shown) that expose both ends (buried electrodes 28) of the plurality of trench structures 25, and a single contact opening 44 that collectively exposes the inner portions (buried insulator 80) of the plurality of trench structures 25, the plurality of source regions 37, and the plurality of contact regions 38.
  • the aforementioned gate pad 50, the aforementioned multiple gate wirings 51, and the aforementioned drain pad 53 have the same configuration as in the first embodiment.
  • the aforementioned source pad 52 penetrates into the single contact opening 44 from above the interlayer insulating film 41, and collectively covers the inner parts (buried insulator 80) of the multiple trench structures 25, the multiple source regions 37, and the multiple contact regions 38 within the single contact opening 44.
  • the source pad 52 is electrically insulated from the multiple trench structures 25 (buried electrodes 28) by the buried insulator 80, and is electrically connected to the multiple source regions 37 and multiple contact regions 38 at the first major surface 3 (active surface 10). In this embodiment, the source pad 52 is also electrically connected to exposed portions of the multiple intermediate regions 36 at the first major surface 3.
  • the source pad 52 has a buried portion buried in the trench 26.
  • the buried portion of the source pad 52 faces the buried electrode 28 within the trench 26 with the buried insulator 80 therebetween, and is electrically connected to the multiple source regions 37 and the multiple contact regions 38 at the opening end of the trench 26.
  • FIG. 22 is a cross-sectional perspective view showing a trench structure 25 according to the third embodiment.
  • the trench structures 25 according to the third embodiment each have a configuration that is a modification of the trench structures 25 according to the second embodiment.
  • the multiple trench structures 25 each include a trench 26, an insulating film 27, a buried electrode 28, and a buried insulator 80.
  • the trench 26 has a similar configuration to that of the first embodiment.
  • the insulating film 27 includes an upper insulating film 81 and a lower insulating film 82.
  • the upper insulating film 81 is formed as an insulating film 27 for channel control, and covers the wall surface of the opening side of the trench 26 relative to the bottom of the body region 20.
  • the upper insulating film 81 has a portion that crosses the boundary between the semiconductor layer 7 (high concentration region 15) and the body region 20 and covers the semiconductor layer 7 (high concentration region 15). In this case, it is preferable that the coverage area of the upper insulating film 81 relative to the body region 20 is larger than the coverage area of the upper insulating film 81 relative to the drift region 35.
  • the upper insulating film 81 may include a silicon oxide film. It is preferable that the upper insulating film 81 includes a silicon oxide film made of an oxide of the chip 2.
  • the upper insulating film 81 may have a thickness of 1 nm or more and 100 nm or less. The thickness of the upper insulating film 81 may have a value that belongs to any one of the following ranges: 1 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less.
  • the lower insulating film 82 covers the wall surface on the bottom wall side of the trench 26 relative to the bottom of the body region 20.
  • the lower insulating film 82 covers the semiconductor layer 7 (high concentration region 15).
  • the coverage area of the lower insulating film 82 relative to the drift region 35 is larger than the coverage area of the upper insulating film 81 relative to the body region 20.
  • the lower insulating film 82 may include a silicon oxide film.
  • the lower insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film formed by a CVD method.
  • the lower insulating film 82 has a thickness greater than that of the upper insulating film 81.
  • the thickness of the lower insulating film 82 is preferably 10 to 50 times the thickness of the upper insulating film 81.
  • the lower insulating film 82 may have a thickness of 100 nm or more and 500 nm or less.
  • the thickness of the lower insulating film 82 may have a value that belongs to any one of the following ranges: 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less, and 450 nm or more and 500 nm or less.
  • the buried electrode 28 has a multi-electrode structure (double electrode structure) including an upper electrode 83, a lower electrode 84, and an intermediate insulating film 85.
  • the upper electrode 83 is buried in the opening side of the trench 26 with an insulating film 27 in between.
  • the upper electrode 83 is buried in the opening side of the trench 26 with an upper insulating film 81 in between, and faces the body region 20 with the upper insulating film 81 in between.
  • the facing area of the upper electrode 83 relative to the body region 20 is larger than the facing area of the upper electrode 83 relative to the drift region 35.
  • the upper electrode 83 is embedded in the trench 26 at a distance from the first main surface 3 (active surface 10) toward the bottom wall of the trench 26, and defines an opening recess that is recessed toward the bottom wall of the trench 26 at the opening end of the trench 26.
  • the upper electrode 83 exposes the surface portion of the first main surface 3 (active surface 10) and the upper end of the upper insulating film 81 at the opening end of the trench 26.
  • the upper electrode 83 is applied with a gate potential as a control potential.
  • the upper electrode 83 controls the inversion and non-inversion of the channel (current path) in the body region 20 in response to the gate potential.
  • the upper electrode 83 may include p-type or n-type conductive polysilicon.
  • the lower electrode 84 is embedded in the bottom wall side of the trench 26 with the insulating film 27 in between. Specifically, the lower electrode 84 is embedded in the bottom wall side of the trench 26 with the lower insulating film 82 in between, and faces the drift region 35 with the lower insulating film 82 in between. In other words, the lower electrode 84 is embedded in the bottom wall side of the trench 26 with respect to the bottom of the body region 20. Although specific illustration is omitted, the lower electrode 84 is drawn out to the opening side of the trench 26 in part of the trench 26 (both ends in this embodiment).
  • the facing area of the lower electrode 84 with respect to the drift region 35 is larger than the facing area of the upper electrode 83 with respect to the body region 20.
  • the lower electrode 84 extends in a wall shape along the depth direction of the trench 26.
  • the lower electrode 84 has an upper end that protrudes from the lower insulating film 82 toward the upper electrode 83, and is engaged with the lower end of the upper electrode 83.
  • the upper end of the lower electrode 84 faces the upper insulating film 81 (body region 20) horizontally, sandwiching the lower end of the upper electrode 83 therebetween.
  • the lower electrode 84 may be applied with a gate potential or a source potential.
  • a gate potential When a gate potential is applied to the lower electrode 84, the lower electrode 84 has the same potential as the upper electrode 83. Therefore, the voltage drop between the upper electrode 83 and the lower electrode 84 is suppressed. This suppresses electric field concentration in the trench structure 25.
  • the lower electrode 84 when a source potential is applied to the lower electrode 84, the lower electrode 84 can function as a field electrode. Therefore, the parasitic capacitance between the lower electrode 84 (field electrode) and the drift region 35 is reduced. This suppresses the decrease in switching speed caused by the parasitic capacitance.
  • the lower electrode 84 may include p-type or n-type conductive polysilicon.
  • the intermediate insulating film 85 is interposed between the upper electrode 83 and the lower electrode 84, and electrically insulates the upper electrode 83 and the lower electrode 84 within the trench 26.
  • the intermediate insulating film 85 is continuous with the upper insulating film 81 and the lower insulating film 82.
  • the intermediate insulating film 85 has a thickness smaller than that of the lower insulating film 82.
  • the thickness of the intermediate insulating film 85 is preferably greater than that of the upper insulating film 81.
  • the intermediate insulating film 85 may include a silicon oxide film.
  • the intermediate insulating film 85 preferably includes a silicon oxide film made of an oxide of the lower electrode 84.
  • the buried insulator 80 is buried in the trench 26 (open recess) so as to expose the first principal surface 3 (active surface 10), and covers the upper insulating film 81 and the upper electrode 83 within the recess.
  • the buried insulator 80 is buried in the trench 26 at a distance from the first principal surface 3 (active surface 10) toward the upper electrode 83, and exposes the surface portion of the first principal surface 3 (active surface 10) at the open end of the trench 26.
  • the aforementioned multiple source regions 37 have portions exposed from the sidewall of trench 26 at the opening end of trench 26, and face upper electrode 83 and buried insulator 80 across upper insulating film 81.
  • the aforementioned multiple contact regions 38 have portions exposed from the sidewall of trench 26 at the opening end of trench 26, and face upper electrode 83 and buried insulator 80 across upper insulating film 81.
  • the aforementioned gate wirings 51 penetrate the interlayer insulating film 41 via the contact openings 44 and are electrically connected to the upper electrodes 83.
  • the gate wirings 51 penetrate the interlayer insulating film 41 via the contact openings 44 and are electrically connected to the upper electrodes 83 and the lower electrodes 84.
  • the SiC semiconductor device 1 may include a source wiring drawn from the source pad 52 onto the interlayer insulating film 41.
  • the source wiring is formed in a line shape extending along the periphery of the active surface 10 so as to intersect (specifically, perpendicularly) with a portion (one end or both ends) of the multiple trench structures 25 in a region outside the multiple gate wirings 51.
  • the source wiring penetrates the interlayer insulating film 41 via the multiple contact openings 44 and is electrically connected to the multiple lower electrodes 84.
  • FIG. 23 is a cross-sectional perspective view showing a trench structure 25 according to the fourth embodiment.
  • the multiple trench structures 25 according to the first embodiment are arranged at intervals in the first direction X (m-axis direction) and are each formed in a band shape extending in the second direction Y (a-axis direction).
  • the multiple trench structures 25 may also be each formed in a band shape extending in the first direction X (m-axis direction) and arranged at intervals in the second direction Y (a-axis direction).
  • the multiple column regions 30 are formed in strips extending in the first direction X (m-axis direction) according to the layout of the multiple trench structures 25, and are arranged at intervals in the second direction Y (a-axis direction).
  • the extension direction of the multiple column regions 30 intersects (specifically, is perpendicular to) the off-direction Do of the SiC single crystal, so the multiple column regions 30 are inclined by approximately the off angle ⁇ o from the vertical axis toward the off-direction Do in a cross-sectional view seen from the m-plane of the SiC single crystal. Therefore, in consideration of the accuracy of the charge balance, it is preferable that the multiple column regions 30 extend in the off-direction Do.
  • FIG. 24 is a cross-sectional perspective view showing the SiC semiconductor device 1 according to the first modified example.
  • the SiC semiconductor device 1 has a high concentration region 15.
  • the SiC semiconductor device 1 according to the modified example does not have a high concentration region 15.
  • a plurality of trench structures 25, a plurality of column regions 30, a plurality of drift regions 35, etc. are each formed in the semiconductor layer 7.
  • FIG. 25 is a cross-sectional perspective view showing a SiC semiconductor device 1 according to a second modified example.
  • the SiC semiconductor device 1 according to the second modified example further includes an n-type buffer layer 86 made of single crystal SiC stacked on the base layer 6.
  • the buffer layer 86 is also a component of the chip 2.
  • the buffer layer 86 may also be referred to as a "buffer SiC layer", a "buffer region”, etc.
  • the buffer layer 86 extends horizontally in a layered manner and forms the middle part of the chip 2 and part of the first to fourth side surfaces 5A to 5D.
  • the buffer layer 86 is made of an epitaxial layer (i.e., a SiC epitaxial layer) that is crystal-grown starting from the base layer 6.
  • the buffer layer 86 has a lower end and an upper end.
  • the lower end of the buffer layer 86 is the starting point of crystal growth, and the upper end of the buffer layer 86 is the end point of crystal growth. Since the buffer layer 86 is grown continuously from the base layer 6, the lower end of the buffer layer 86 coincides with the upper end of the base layer 6.
  • the boundary between the base layer 6 and the buffer layer 86 is not necessarily visible, and can be indirectly evaluated and/or determined from other configurations or elements.
  • the buffer layer 86 has an off-direction Do and an off-angle ⁇ o that are approximately the same as the off-direction Do and off-angle ⁇ o of the base layer 6.
  • the buffer layer 86 has a third axis channel C3 along the stacking direction.
  • the third axis channel C3 is a region (channel) in which the interatomic distance (atomic spacing) is relatively wide with respect to the SiC single crystal that constitutes the buffer layer 86, and is surrounded by atomic rows along a crystal axis that extends in the stacking direction (crystal growth direction).
  • the third axis channel C3 is a region in which the atomic rows extend in the stacking direction and the atomic rows (atomic distance/atomic density) in the horizontal direction are sparse in a planar view. It is preferable that the third axis channel C3 is a region surrounded by atomic rows along a low-index crystal axis among the crystal axes.
  • the third axis channel C3 consists of a region surrounded by atomic rows along the c-axis of the SiC single crystal. That is, the third axis channel C3 extends along the c-axis and has an off-direction Do and an off-angle ⁇ o. In other words, the third axis channel C3 is inclined from the vertical axis toward the off-direction Do by the off-angle ⁇ o.
  • the n-type impurity concentration of the buffer layer 86 is preferably lower than the n-type impurity concentration of the base layer 6.
  • the buffer layer 86 may have a peak n-type impurity concentration of 1 ⁇ 10 15 cm -3 or more and 1 ⁇ 10 18 cm -3 or less.
  • the n-type impurity concentration of the buffer layer 86 may be approximately constant in the thickness direction.
  • the n-type impurity concentration of the buffer layer 86 may have a concentration gradient that gradually increases and/or gradually decreases in the stacking direction (crystal growth direction).
  • the buffer layer 86 has an n-type impurity concentration adjusted with at least one pentavalent element.
  • the n-type impurity concentration of the buffer layer 86 may be adjusted with at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth. It is preferable that the buffer layer 86 contains a pentavalent element other than phosphorus.
  • the n-type impurity concentration of the buffer layer 86 is preferably adjusted with at least nitrogen.
  • the buffer layer 86 preferably contains nitrogen and a pentavalent element other than nitrogen.
  • the buffer layer 86 preferably contains either arsenic or antimony, or both, as the pentavalent element other than phosphorus and nitrogen.
  • the buffer layer 86 has a third thickness T3.
  • the third thickness T3 is preferably less than the first thickness T1 of the base layer 6.
  • the third thickness T3 is preferably 1 ⁇ m or more.
  • the third thickness T3 is preferably 5 ⁇ m or less.
  • the third thickness T3 may have a value that belongs to any one of the following ranges: 1 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the semiconductor layer 7 is stacked on the buffer layer 86.
  • the semiconductor layer 7 is made of an epitaxial layer (i.e., a SiC epitaxial layer) crystal-grown starting from the buffer layer 86. Therefore, the semiconductor layer 7 has an off-direction Do and an off-angle ⁇ o that are approximately the same as the off-direction Do and the off-angle ⁇ o of the buffer layer 86.
  • the second axis channel C2 is approximately the same as the third axis channel C3.
  • the second thickness T2 of the semiconductor layer 7 is preferably greater than the third thickness T3.
  • the second thickness T2 may be less than the third thickness T3.
  • the second thickness T2 may be approximately equal to the third thickness T3.
  • the above-mentioned embodiment can be implemented in other forms.
  • the above-mentioned embodiment employs the base layer 6, semiconductor layer 7, and buffer layer 86, each of which contains a SiC single crystal.
  • the base layer 6, semiconductor layer 7, and buffer layer 86 may contain a single crystal of a wide band gap semiconductor other than a SiC single crystal.
  • a wide band gap semiconductor is a semiconductor having a band gap larger than that of silicon.
  • Examples of single crystals of wide band gap semiconductors include silicon carbide (SiC), gallium nitride (GaN), diamond (C), and gallium oxide (Ga 2 O 3 ).
  • the base layer 6, the semiconductor layer 7, and the buffer layer 86 may be made of the same type of single crystal, or may be made of different types of single crystal.
  • the low-index crystal axis of a cubic crystal is a crystal axis in which the absolute values of "h", "k” and “l” in the Miller indices (h, k, l) are all 2 or less (preferably 1 or less).
  • the base layer 6, the semiconductor layer 7 and the buffer layer 86 may contain single crystal silicon.
  • an n-type base layer 6 is shown.
  • a p-type base layer 6 may be adopted.
  • an IGBT (Insulated Gate Bipolar Transistor) structure is formed instead of the MISFET structure.
  • the "source” of the MISFET structure is replaced with the "emitter” of the IGBT structure, and the "drain” of the MISFET structure is replaced with the "collector” of the IGBT structure.
  • the p-type base layer 6 may be a p-type region containing a trivalent element introduced into the surface layer of the second main surface 4 of the chip 2 by ion implantation.

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  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119611A (ja) * 2002-09-25 2004-04-15 Toshiba Corp 電力用半導体素子
JP2021027138A (ja) * 2019-08-02 2021-02-22 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2021089916A (ja) * 2019-12-02 2021-06-10 富士電機株式会社 炭化珪素半導体装置の製造方法、炭化珪素基板の製造方法および炭化珪素基板
JP2022080586A (ja) * 2020-11-18 2022-05-30 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004119611A (ja) * 2002-09-25 2004-04-15 Toshiba Corp 電力用半導体素子
JP2021027138A (ja) * 2019-08-02 2021-02-22 株式会社東芝 半導体装置、インバータ回路、駆動装置、車両、及び、昇降機
JP2021089916A (ja) * 2019-12-02 2021-06-10 富士電機株式会社 炭化珪素半導体装置の製造方法、炭化珪素基板の製造方法および炭化珪素基板
JP2022080586A (ja) * 2020-11-18 2022-05-30 国立研究開発法人産業技術総合研究所 炭化珪素半導体装置
WO2022163081A1 (ja) * 2021-02-01 2022-08-04 ローム株式会社 ＳｉＣ半導体装置

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