WO2024135067A1 - 積層セラミックコンデンサ - Google Patents

積層セラミックコンデンサ Download PDF

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Publication number
WO2024135067A1
WO2024135067A1 PCT/JP2023/037366 JP2023037366W WO2024135067A1 WO 2024135067 A1 WO2024135067 A1 WO 2024135067A1 JP 2023037366 W JP2023037366 W JP 2023037366W WO 2024135067 A1 WO2024135067 A1 WO 2024135067A1
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Prior art keywords
exposed
dielectric layer
internal electrode
main surface
region
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Ceased
Application number
PCT/JP2023/037366
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English (en)
French (fr)
Japanese (ja)
Inventor
和博 西林
悠子 河崎
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Murata Manufacturing Co Ltd
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Murata Manufacturing Co Ltd
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Priority to KR1020257010627A priority Critical patent/KR20250054115A/ko
Priority to CN202380069539.XA priority patent/CN119948584A/zh
Priority to JP2024565623A priority patent/JPWO2024135067A1/ja
Publication of WO2024135067A1 publication Critical patent/WO2024135067A1/ja
Priority to US18/905,342 priority patent/US20250029789A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/30—Stacked capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/008—Selection of materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/005—Electrodes
    • H01G4/012—Form of non-self-supporting electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/018—Dielectrics
    • H01G4/06—Solid dielectrics
    • H01G4/08—Inorganic dielectrics
    • H01G4/12—Ceramic dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/35—Feed-through capacitors or anti-noise capacitors

Definitions

  • the present invention relates to a multilayer ceramic capacitor.
  • the present invention aims to provide a multilayer ceramic capacitor that can reduce the possibility of moisture intrusion from the external electrode side.
  • a laminate including: an inner layer portion in which a plurality of dielectric layers, each having an internal electrode disposed thereon, are laminated; two main surfaces having a first main surface provided on one side of a lamination direction and a second main surface provided on the other side; two side surfaces provided on both sides in a width direction intersecting the lamination direction; and two end faces provided on both sides in a length direction intersecting the lamination direction and the width direction; external electrodes disposed on the end faces and the side faces of the laminate;
  • the dielectric layer includes a first dielectric layer and a second dielectric layer alternately laminated with the first dielectric layer, the first dielectric layer is provided with an end surface exposed internal electrode exposed at least to the end surface as the internal electrode, the second dielectric layer is provided with a side surface exposed internal electrode exposed at least to the side surface as the internal electrode, and the end surface exposed internal electrode and the side surface exposed internal electrode each have an opposing portion opposing each other and an extraction portion extracted from the opposing portion.
  • a multilayer ceramic capacitor the inner layer portion has a first main surface side region, a second main surface side region, and a central region between the first main surface side region and the second main surface side region,
  • Lc the average thickness of the dielectric layer located between the internal electrodes adjacent to each other in the stacking direction and exposed to the same surface in the central region at the contact portion with the external electrode
  • Ls a thickness Ls of the dielectric layer located between the internal electrodes adjacent to each other in the stacking direction and exposed on the same surface in at least one of the first main surface side region and the second main surface side region at a contact portion with the external electrode
  • the present invention provides a multilayer ceramic capacitor that can reduce the possibility of moisture intrusion from the external electrode side.
  • FIG. 1 is a schematic perspective view of a multilayer ceramic capacitor 1.
  • FIG. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the II-II direction in FIG. 1.
  • 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the line III-III in FIG. 1.
  • FIG. 2 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 1.
  • 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to a second embodiment taken along the line II-II in FIG. 1.
  • 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to a second embodiment taken along the line III-III in FIG. 1.
  • FIG. 1 is a schematic perspective view of the multilayer ceramic capacitor 1.
  • Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the II-II direction in Fig. 1.
  • Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the first embodiment taken along the III-III direction in Fig. 1.
  • the multilayer ceramic capacitor 1 is a multilayer ceramic capacitor with a three-terminal structure, including end surface external electrodes 3 provided on both end surfaces C in the length direction L of the laminate 2, and side surface external electrodes 4 provided on both side surfaces B in the width direction W of the laminate 2.
  • the laminate 2 includes an inner layer portion 11 in which a dielectric layer 14 and an internal electrode 15 are laminated, and an outer layer portion 12.
  • the terminology used to indicate the orientation of the multilayer ceramic capacitor 1 refers to the direction in which the dielectric layers 14 and internal electrodes 15 are stacked in the multilayer ceramic capacitor 1 as the stacking direction T.
  • the direction that intersects with the stacking direction T and in which the pair of end face external electrodes 3 are provided is referred to as the length direction L.
  • the direction that intersects with both the length direction L and the stacking direction T is referred to as the width direction W.
  • the stacking direction T, the length direction L, and the width direction W are mutually orthogonal.
  • a pair of outer surfaces on both sides of the stacking direction T are referred to as principal surfaces A
  • a pair of outer surfaces extending in the stacking direction T and on both sides of the width direction W are referred to as side surfaces B
  • a pair of outer surfaces extending in the stacking direction T and on both sides of the length direction L are referred to as end surfaces C.
  • the principal surfaces A have a first principal surface A1 and a second principal surface A2.
  • the laminate 2 includes an inner layer portion 11 and outer layer portions 12 disposed on both sides of the inner layer portion 11 in the stacking direction T. It is preferable that the corners and ridges of the laminate 2 are rounded. The corners are portions where three surfaces of the laminate intersect, and the ridges are portions where two surfaces of the laminate intersect.
  • the outer layer portion 12 is a dielectric layer of a constant thickness disposed on the main surface A side of the inner layer portion 11.
  • the outer layer portion 12 is made of the same material as the dielectric layer 14 of the inner layer portion 11.
  • the inner layer portion 11 includes a plurality of dielectric layers 14 and internal electrodes 15 laminated in a lamination direction T.
  • the internal electrodes 15 are preferably made of a metal material such as Ni, Cu, Ag, Pd, an Ag-Pd alloy, or Au.
  • the internal electrode 15 has a plurality of end-exposed internal electrodes 15A and a plurality of side-exposed internal electrodes 15B arranged alternately. When there is no need to distinguish between the end-exposed internal electrodes 15A and the side-exposed internal electrodes 15B, they will be collectively referred to as the internal electrodes 15.
  • End surface exposed internal electrode 15A extends between both end faces C in the length direction L of the laminate 2 and is spaced a fixed distance from both side faces B in the width direction W.
  • the end surface exposed internal electrode 15A has an end surface facing portion 15Aa located in the center between both end faces C and an end surface drawn portion 15Ab extending from the end surface facing portion 15Aa to both end faces C.
  • the end surface drawn portions 15Ab extend to both end faces C, respectively, are exposed at the end faces C of the laminate 2, and are connected to the end surface external electrodes 3 provided on both end faces C in the length direction L of the laminate 2.
  • the side surface exposed internal electrode 15B is slightly smaller than the laminate 2 and is spaced a fixed distance from both end faces C in the longitudinal direction L.
  • the side surface exposed internal electrode 15B has a side surface facing portion 15Ba located in the center between both side surfaces B, and a side surface drawn portion 15Bb extending from the side surface facing portion 15Ba to both side surfaces B.
  • the side surface drawn portions 15Bb extend to both side surfaces B, are exposed at the side surfaces B of the laminate 2, and are connected to the side surface external electrodes 4 provided on both side surfaces B in the width direction W of the laminate 2.
  • the end face facing portion 15Aa and the side face facing portion 15Ba face each other and form a capacitor portion.
  • the facing portion 15a unless it is necessary to distinguish between the end face facing portion 15Aa and the side face facing portion 15Ba, they will be collectively referred to as the facing portion 15a.
  • the end face drawn-out portion 15Ab and the side face drawn-out portion 15Bb they will be collectively referred to as the drawn-out portion 15b.
  • the region in the laminate 2 where the facing portion 15a is arranged will be referred to as the facing region, and the region in which the end face drawn-out portion 15Ab or the side face drawn-out portion 15Bb is arranged will be referred to as the drawn-out region.
  • the dielectric layer 14 is made of a ceramic material.
  • a dielectric ceramic containing BaTiO3 as a main component is used as the ceramic material.
  • the ceramic material may be one containing at least one of the subcomponents such as a Mn compound, an Fe compound, a Cr compound, a Co compound, and a Ni compound in addition to the main component.
  • the dielectric layer 14 includes a first dielectric layer 14A and a second dielectric layer 14B that is alternately stacked with the first dielectric layer 14A.
  • FIG. 4 is an exploded perspective view of the laminate 2.
  • the first dielectric layer 14A has an end-surface-exposed internal electrode 15A that is exposed on the end surface as the internal electrode 15, and the second dielectric layer 14B has a side-surface-exposed internal electrode 15B that is exposed on the side surface as the internal electrode 15.
  • the inner layer portion 11 has a first main surface side region 11s1 close to the first main surface A1, a second main surface side region 11s2 close to the second main surface A2, and a central region 11c between the first main surface side region 11s1 and the second main surface side region 11s2.
  • the thickness of each of the first dielectric layer 14As and the second dielectric layer 14Bs in the first main surface side region 11s1 and the second main surface side region 11s2 is thinner than the thickness of each of the first dielectric layer 14Ac and the second dielectric layer 14Bc in the central region 11c, and is 0.75 times or less.
  • the thickness of the dielectric layer 14ABs between the internal electrodes 15 adjacent in the stacking direction T and exposed to the same surface in the first main surface side region 11s1 and the second main surface side region 11s2 in the lead-out region is denoted by Ls.
  • the thickness Ls of the dielectric layer 14ABs located between the internal electrodes 15 is equal to the total thickness of the two overlapping dielectric layers 14As and 14Bs.
  • the thickness Ls of the dielectric layer 14ABs located between the internal electrodes 15 in both the first main surface side region 11s1 and the second main surface side region 11s2 is thinner than the thickness Lc of the dielectric layer 14ABc located between the internal electrodes 15 in the central region 11c.
  • Ls ⁇ 0.75Lc. It is as follows.
  • one of the first main surface region 11s1 and the second main surface region 11s2 is Ls ⁇ 0.75Lc may be also.
  • the first main surface side region 11s1 and the second main surface side region 11s2 each include two or more dielectric layers 14ABs having a thickness Ls of Ls ⁇ 0.75Lc, starting from the layer closest to the main surface A, which are arranged in succession.
  • the total number of the internal electrodes 15 is K
  • the number m of the internal electrodes 15 in each of the first main surface side region 11s1 and the second main surface side region 11s2 is m ⁇ K/3 It is.
  • End surface external electrode 3 end surface external electrodes 3 are disposed on both end surfaces C of the laminate 2. End surface drawn portions 15Ab of end surface exposed internal electrodes 15A are connected to the end surface external electrodes 3.
  • the end surface external electrodes 3 cover not only the end surfaces C but also parts of the main surfaces A and side surfaces B on the end surface C side.
  • side surface external electrodes 4 are disposed on both side surfaces B of the laminate 2. Side surface drawn portions 15Bb of side surface exposed internal electrodes 15B are connected to the side surface external electrodes 4. The side surface external electrodes 4 cover not only the side surface B but also a portion of the main surface A on the side surface B side.
  • the end face external electrode 3 and the side face external electrode 4 include an underlying electrode layer 31 and a plating layer 32 disposed on the underlying electrode layer 31.
  • the underlying electrode layer 31 contains Cu as a main component.
  • the plating layer 32 includes a Ni (nickel) plating layer 321 disposed on the underlying electrode layer 31 and a Sn (tin) plating layer 322 disposed on the Ni plating layer 321.
  • the end face external electrode 3 and the side face external electrode 4 include a plurality of voids H.
  • the end face external electrode 3 and the side face external electrode 4 are thinner on the main surface A side in the stacking direction T than in the central portion in the stacking direction T. Therefore, even in the inner layer portion 11, the thicknesses of the end face external electrodes 3 and the side face external electrodes 4 in the first main surface side region 11s1 and the second main surface side region 11s2 are thinner than the thicknesses of the end face external electrodes 3 and the side face external electrodes 4 in the central region 11c.
  • the end face external electrodes 3 and the side face external electrodes 4 are 10 ⁇ m or less in the first main surface side region 11s1 and the second main surface side region 11s2, and are thicker than 10 ⁇ m and approximately 60 ⁇ m or less in the central region 11c.
  • an interdiffusion layer 17 is formed at the joint between the internal electrode 15 and the end face external electrode 3 and the side face external electrode 4.
  • the interdiffusion layer 17 is formed with a substantially constant dimension in the stacking direction T, sandwiching the internal electrode 15 therebetween.
  • the thickness Lc of the dielectric layer 14ABc located between the internal electrodes 15 is thick and is wider than the dimension of the interdiffusion layer 17, so that the interdiffusion layer 17 is discontinuous.
  • the thickness Ls of the dielectric layer 14ABs located between the internal electrodes 15 is thinner than Lc, i.e., Ls ⁇ 0.75Lc. Since Ls is narrower than the dimension of the interdiffusion layer 17, the interdiffusion layer 17 is continuous.
  • An end surface exposed internal electrode 15A is formed from a conductive paste on the ceramic green sheet that will become the first dielectric layer 14A.
  • a side surface exposed internal electrode 15B is formed from a conductive paste on the ceramic green sheet that will become the second dielectric layer 14B.
  • Ceramic green sheets are strip-shaped sheets made by forming a ceramic slurry containing ceramic powder, binder, and solvent onto a carrier film using a die coater, gravure coater, microgravure coater, etc.
  • the thickness of the ceramic green sheets arranged in the first main surface side region 11s1 and the second main surface side region 11s2 is thinner than the ceramic green sheets arranged in the central region 11c, and is 0.75 times or less thicker.
  • the end-exposed internal electrodes 15A and side-exposed internal electrodes 15B are formed by printing, such as screen printing, gravure printing, letterpress printing, etc.
  • Ceramic sheets that will become the first dielectric layer 14A on which the end surface exposed internal electrodes 15A are arranged and ceramic sheets that will become the second dielectric layer 14B on which the side surface exposed internal electrodes 15B are arranged are alternately laminated.
  • a stack of thick ceramic green sheets to be arranged in the central region 11c is placed above and below a stack of thin ceramic green sheets to be arranged in the first main surface region 11s1 and the second main surface region 11s2.
  • ceramic green sheets for the outer layer portions are further placed above and below and thermocompression bonded to form a mother block.
  • end surface external electrodes 3 are formed on both end surfaces C of the laminate 2, and side surface external electrodes 4 are formed on both side surfaces B.
  • An end surface lead portion 15Ab of an end surface exposed internal electrode 15A is connected to the end surface external electrode 3.
  • the end surface external electrode 3 is formed so as to cover not only the end surface C, but also parts of the end surface C side of the main surface A and the side surface B.
  • a side surface lead portion 15Bb of a side surface exposed internal electrode 15B is connected to the side surface external electrode 4.
  • the side surface external electrode 4 is formed so as to cover not only the side surface B, but also parts of the side surface B side of the main surface A.
  • the end face external electrode 3 and the side face external electrode 4 are formed by applying an external electrode paste that is composed of metal particles containing Cu as a main component, an inorganic binder such as glass particles, additives (plasticizers, dispersants, etc.), organic solvents, etc.
  • an external electrode paste that is composed of metal particles containing Cu as a main component, an inorganic binder such as glass particles, additives (plasticizers, dispersants, etc.), organic solvents, etc.
  • Step S5 Heating is performed for a predetermined time in a nitrogen atmosphere at the set firing temperature. As a result, the end surface external electrodes 3 and the side surface external electrodes 4 are baked onto the laminate 2. At this time, the metal particles produce some voids, the glass particles melt and fill the voids, and the portions where the glass particles were present become voids H.
  • the thicknesses of the end surface external electrodes 3 and side surface external electrodes 4 in the first main surface region 11s1 and the second main surface region 11s2 in the inner layer portion 11 are thinner than the thicknesses of the end surface external electrodes 3 and side surface external electrodes 4 in the central region 11c.
  • an interdiffusion layer 17 is formed at the junctions between the internal electrode 15 and the end face external electrode 3 and the side face external electrode 4.
  • the thickness Lc of the dielectric layer 14ABc located between the internal electrodes 15 is large. Therefore, the interdiffusion layer 17 between the internal electrode 15 and the end face external electrode 3 and the side face external electrode 4 is discontinuous.
  • the thickness Ls of the dielectric layer 14ABc located between the internal electrodes 15 is thinner than Lc, i.e., Ls ⁇ 0.75Lc. Therefore, the interdiffusion layers 17 of the internal electrodes 15 and the end surface external electrodes 3 and side surface external electrodes 4 are continuous.
  • end face external electrodes 3 and side face external electrodes 4 are thin, moisture may penetrate through the voids H, causing a deterioration in the insulation resistance of the multilayer ceramic capacitor 1. This phenomenon is particularly noticeable on the main surface A side, where the end face external electrodes 3 and side face external electrodes 4 are the thinnest.
  • the interdiffusion layer 17 formed between the internal electrode 15 and the end face external electrode 3 and the side face external electrode 4 is continuous.
  • This interdiffusion layer 17 prevents moisture from entering through the voids H, reducing the possibility of the insulation resistance of the multilayer ceramic capacitor 1 deteriorating. This makes it possible to provide a multilayer ceramic capacitor that can reduce the possibility of moisture entering from the external electrode side.
  • the distance between the internal electrodes 15 is short in the first main surface side region 11s1 and the second main surface side region 11s2, so the DC resistance value can be reduced.
  • the internal electrodes 15 arranged in the first main surface side region 11s1 and the second main surface side region 11s2 all had the same thickness, but this is not limited to this, and for example, the internal electrodes 15 arranged in the first main surface side region 11s1 and the second main surface side region 11s2 may be thicker than the internal electrodes 15 arranged in the central region 11c. In this case, it is preferable that the thickness of the internal electrodes 15 arranged in the first main surface side region 11s1 and the second main surface side region 11s2 is about 1.1 times that of the internal electrodes 15 arranged in the central region 11c. Increasing the thickness of the internal electrode 15 allows the interdiffusion layer 17 to be more continuous.
  • the multilayer ceramic capacitor 1 in the embodiment is a three-terminal multilayer ceramic capacitor 1, but is not limited to this and may be a two-terminal multilayer ceramic capacitor.
  • FIG. 1 is common to the first embodiment
  • Fig. 6 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the second embodiment taken along the II-II direction in Fig. 1.
  • Fig. 7 is a cross-sectional view of the multilayer ceramic capacitor 1 according to the second embodiment taken along the III-III direction in Fig. 1.
  • the same reference numerals are used for the parts common to the multilayer ceramic capacitor 1 of the first embodiment, and a common description will be omitted.
  • the thickness of each of the first dielectric layer 14As and the second dielectric layer 14Bs in the first main surface side region 11s1 and the second main surface side region 11s2 is equal to the thickness of each of the first dielectric layer 14Ac and the second dielectric layer 14Bc in the central region 11c.
  • a side surface-exposed auxiliary internal electrode 16A as an auxiliary internal electrode 16 is arranged on the side surface B of the first dielectric layer 14A on which the end surface-exposed internal electrode 15A is arranged.
  • the side surface-exposed auxiliary internal electrode 16A is disposed at a distance from the end surface-exposed internal electrode 15A.
  • the side surface-exposed auxiliary internal electrode 16A is exposed to the side surface B, and faces the side surface drawn portion 15Bb of the side surface-exposed internal electrode 15B adjacent in the stacking direction T to the end surface-exposed internal electrode 15A.
  • an end face exposed auxiliary internal electrode 16B as the auxiliary internal electrode 16 is arranged on the end face C side of the second dielectric layer 14B on which the side face exposed internal electrode 15B is arranged.
  • the end surface exposed auxiliary internal electrode 16B is disposed at a distance from the side surface exposed internal electrode 15 B.
  • the end surface exposed auxiliary internal electrode 16B is exposed at the end surface C, and faces the end surface drawn portion 15Ab of the end surface exposed internal electrode 15A adjacent in the stacking direction T to the side surface exposed internal electrode 15B.
  • the thickness Ls of the dielectric layer 14 between the internal electrodes 15 that are adjacent in the stacking direction T and exposed to the same end face C is equal to the thickness of one dielectric layer of the dielectric layer 14B between the end face drawn portion 15Ab and the end face exposed auxiliary internal electrode 16B.
  • the thickness Ls of the dielectric layer 14 between the internal electrodes 15 that are adjacent in the stacking direction T and exposed to the same side surface B is the thickness of the dielectric layer 14A between the side surface extended portion 15Bb and the side surface exposed auxiliary internal electrode 16A, which is the thickness of one dielectric layer.
  • the thickness Lc of the dielectric layer 14 between the internal electrodes 15 adjacent in the stacking direction T and exposed to the same end face C is the thickness of the dielectric layer 14c between the end face lead-out portions 15Ab, which is equivalent to two dielectric layers.
  • an interdiffusion layer 17 is formed at the joint between the internal electrode 15 and the end surface external electrode 3 and the side surface external electrode 4 .
  • the thickness Lc of the dielectric layer 14s located between the internal electrodes 15 is large, so that the interdiffusion layers 17 between the internal electrodes 15 and the end surface external electrodes 3 and side surface external electrodes 4 are discontinuous.
  • the thickness Ls of the dielectric layer 14c located between the internal electrodes 15 is thinner than Lc, so that the interdiffusion layers 17 between the internal electrodes 15 and the end surface external electrodes 3 and side surface external electrodes 4 are continuous.
  • the possibility of moisture penetrating through the voids H and deteriorating the insulation resistance of the multilayer ceramic capacitor 1 is reduced, making it possible to provide a multilayer ceramic capacitor that can reduce the possibility of moisture penetrating from the external electrode side.
  • the dielectric layer includes a first dielectric layer and a second dielectric layer alternately laminated with the first dielectric layer, the first dielectric layer is provided with an end surface exposed internal electrode exposed at least to the end surface as the internal electrode, the second dielectric layer is provided with a side surface exposed internal electrode exposed at least to the side surface as the internal electrode, and the end surface exposed internal electrode and the side surface exposed internal electrode each have an opposing portion opposing each other and an extraction portion extracted from the opposing portion.
  • a multilayer ceramic capacitor the inner layer portion has a first main surface side region, a second main surface side region, and a central region between the first main surface side region and the second main surface side region,
  • Lc the average thickness of the dielectric layer located between the internal electrodes adjacent to each other in the stacking direction and exposed to the same surface in the central region at the contact portion with the external electrode
  • Ls a thickness Ls of the dielectric layer located between the internal electrodes adjacent to each other in the stacking direction and exposed on the same surface in at least one of the first main surface side region and the second main surface side region at a contact portion with the external electrode
  • ⁇ 2> The multilayer ceramic capacitor described in ⁇ 1>, in which the dielectric layer having a thickness Ls at the contact portion with the external electrode is arranged in two or more consecutive layers.
  • ⁇ 3> The multilayer ceramic capacitor according to ⁇ 1> or ⁇ 2>, in which the number m of the internal electrodes in each of the first main surface side region and the second main surface side region is m ⁇ K/3, where K is the total number of the internal electrodes.
  • the internal electrodes arranged in the first main surface region and the second main surface region are The multilayer ceramic capacitor according to any one of ⁇ 1> to ⁇ 3>, wherein the inner electrode is thicker than the inner electrode arranged in the central region.
  • the internal electrode is, in the first main surface side region and the second main surface side region, a side surface-exposed auxiliary internal electrode is disposed on the first dielectric layer, the side surface-exposed auxiliary internal electrode is disposed at a distance from the end surface-exposed internal electrode disposed on the first dielectric layer, the side surface-exposed auxiliary internal electrode is exposed at the side surface, and the side surface-exposed auxiliary internal electrode faces the lead portion of the side surface-exposed internal electrode disposed on the second dielectric layer adjacent in the stacking direction; or, the second dielectric layer is disposed at a distance from the side surface-exposed internal electrode disposed on the second dielectric layer, the side surface-exposed auxiliary internal electrode is exposed at the end surface, and the side surface-exposed auxiliary internal electrode faces the lead portion of the end surface-exposed internal electrode disposed on the first dielectric layer adjacent in the stacking direction;
  • the average thickness Ls is an average thickness of the dielectric layer between the side surface exposed auxiliary internal electrode disposed on the first dielectric layer,

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
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  • Inorganic Chemistry (AREA)
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PCT/JP2023/037366 2022-12-19 2023-10-16 積層セラミックコンデンサ Ceased WO2024135067A1 (ja)

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Application Number Priority Date Filing Date Title
KR1020257010627A KR20250054115A (ko) 2022-12-19 2023-10-16 적층 세라믹 콘덴서
CN202380069539.XA CN119948584A (zh) 2022-12-19 2023-10-16 层叠陶瓷电容器
JP2024565623A JPWO2024135067A1 (https=) 2022-12-19 2023-10-16
US18/905,342 US20250029789A1 (en) 2022-12-19 2024-10-03 Multilayer ceramic capacitor

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JP2022-202430 2022-12-19
JP2022202430 2022-12-19

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JP2013115422A (ja) * 2011-11-25 2013-06-10 Samsung Electro-Mechanics Co Ltd 積層セラミック電子部品
JP2016086118A (ja) * 2014-10-28 2016-05-19 京セラ株式会社 積層型コンデンサ
CN115483031A (zh) * 2021-06-16 2022-12-16 株式会社村田制作所 层叠陶瓷电容器

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JP2019201106A (ja) * 2018-05-16 2019-11-21 株式会社村田製作所 積層セラミックコンデンサ
JP7231340B2 (ja) * 2018-06-05 2023-03-01 太陽誘電株式会社 セラミック電子部品およびその製造方法

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JP2013115422A (ja) * 2011-11-25 2013-06-10 Samsung Electro-Mechanics Co Ltd 積層セラミック電子部品
JP2016086118A (ja) * 2014-10-28 2016-05-19 京セラ株式会社 積層型コンデンサ
CN115483031A (zh) * 2021-06-16 2022-12-16 株式会社村田制作所 层叠陶瓷电容器

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