WO2024130557A1 - 一种移位寄存器、驱动方法、栅极驱动电路及显示装置 - Google Patents

一种移位寄存器、驱动方法、栅极驱动电路及显示装置 Download PDF

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WO2024130557A1
WO2024130557A1 PCT/CN2022/140471 CN2022140471W WO2024130557A1 WO 2024130557 A1 WO2024130557 A1 WO 2024130557A1 CN 2022140471 W CN2022140471 W CN 2022140471W WO 2024130557 A1 WO2024130557 A1 WO 2024130557A1
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Prior art keywords
switch transistor
coupled
terminal
signal
electrode
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PCT/CN2022/140471
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English (en)
French (fr)
Inventor
陈文波
于子阳
王梦奇
张跳梅
赵二瑾
谷泉泳
承天一
吴建鹏
蒋志亮
胡明
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京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Priority to PCT/CN2022/140471 priority Critical patent/WO2024130557A1/zh
Publication of WO2024130557A1 publication Critical patent/WO2024130557A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a shift register, a driving method, a gate driving circuit and a display device.
  • GOA Gate Driver on Array
  • TFT Thin Film Transistor
  • a shift module coupled to the input signal terminal and the cascade signal output terminal respectively; the shift module is configured to respond to the signal of the input signal terminal so that the cascade signal output terminal outputs the cascade signal;
  • a reverse output module coupled to the cascade signal output terminal, the first power supply terminal, the second power supply terminal and the reverse signal output terminal respectively;
  • the reverse output module is configured to respond to the signal of the cascade signal output terminal so that the reverse signal output terminal outputs a signal opposite to that of the cascade signal output terminal;
  • a latch module is coupled to the masking signal terminal, the cascade signal output terminal, and the reverse signal output terminal of the previous stage respectively; the latch module is configured to respond to the signals of the cascade signal output terminal and the reverse signal output terminal of the previous stage, so that the output terminal of the latch module outputs the control signal of the masking signal terminal;
  • the selection output module is coupled to the first power supply terminal, the second power supply terminal, the output terminal of the latch module and the drive signal output terminal respectively; the selection output module is configured to respond to the signal of the output terminal of the latch module and provide the signal of the first power supply terminal or the second power supply terminal to the drive signal output terminal.
  • the reverse output module includes: a first switch transistor and a second switch transistor; the first switch transistor and the second switch transistor are of different types; wherein,
  • the gate of the first switch transistor is coupled to the cascade signal output terminal, the first electrode of the first switch transistor is coupled to the first power supply terminal, and the second electrode of the first switch transistor is coupled to the reverse signal output terminal;
  • a gate of the second switch transistor is coupled to the cascade signal output terminal, a first electrode of the second switch transistor is coupled to the second power supply terminal, and a second electrode of the second switch transistor is coupled to the reverse signal output terminal.
  • the latch module includes: a third switch transistor and a fourth switch transistor; wherein,
  • the gate of the third switch transistor is coupled to the cascade signal output terminal, the first electrode of the third switch transistor is coupled to the mask signal terminal, and the second electrode of the third switch transistor is coupled to the first electrode of the fourth switch transistor;
  • the gate of the fourth switch transistor is coupled to the reverse signal output terminal of the previous stage, and the second electrode of the fourth switch transistor is the output terminal of the latch module.
  • the selection output module includes: a fifth switch transistor, a sixth switch transistor and a first capacitor; the fifth switch transistor and the sixth switch transistor are of different types; wherein,
  • the gate of the fifth switch transistor is coupled to the second electrode of the fourth switch transistor, and the first electrode of the fifth switch transistor is coupled to the drive signal output terminal;
  • the gate of the sixth switch transistor is coupled to the second electrode of the fourth switch transistor, the first electrode of the sixth switch transistor is coupled to the second power supply terminal, and the second electrode of the sixth switch transistor is coupled to the drive signal output terminal;
  • a first terminal of the first capacitor is coupled to the first power supply terminal, and a second terminal of the first capacitor is coupled to a second electrode of the fourth switch transistor.
  • the second electrode of the fifth switch transistor is coupled to the cascade signal output terminal.
  • the selection output module also includes: a seventh switching transistor; the type of the seventh switching transistor is the same as the type of the fifth switching transistor; the gate of the seventh switching transistor is coupled to the shift module, the first pole of the seventh switching transistor is coupled to the first power supply terminal, and the second pole of the seventh switching transistor is coupled to the second pole of the fifth switching transistor.
  • an eighth switching transistor is also included, the gate of the eighth switching transistor is coupled to the shift module, the first electrode of the eighth switching transistor is coupled to the second power supply terminal, and the second electrode of the eighth switching transistor is coupled to the drive signal output terminal.
  • the first switch transistor, the third switch transistor, the fourth switch transistor, the fifth switch transistor and the eighth switch transistor are all P-type transistors, and the second switch transistor and the sixth switch transistor are all N-type transistors.
  • the shift module includes:
  • an input circuit coupled to the input signal terminal, the first clock signal terminal, the second power supply terminal, the first node, and the second node, respectively; the input circuit is configured to provide the signal of the input signal terminal to the first node and the second node in response to the signal of the first clock signal terminal;
  • a node control circuit coupled to the first node, the second node, the third node, the fourth node, the fifth node, the first power supply terminal, the second power supply terminal, the first clock signal terminal, and the second clock signal terminal, respectively;
  • the node control circuit is configured to adjust the signals of the first node, the second node, the third node, the fourth node, and the fifth node, so that the cascade signal output terminal outputs the signal of the first power supply terminal or the signal of the second power supply terminal;
  • a reset circuit coupled to the first power supply terminal, the reset signal terminal, the first node, the fourth node and the fifth node respectively; the reset circuit is configured to reset the cascade signal output by the cascade signal output terminal in response to a signal at the reset signal terminal;
  • a first cascade output circuit coupled to the fourth node, the first power supply terminal and the cascade signal output terminal respectively;
  • the first cascade output circuit is configured to provide the signal of the first power supply terminal to the cascade signal output terminal in response to the signal of the fourth node;
  • the gate of the seventh switch transistor is coupled to the fourth node;
  • the second cascade output circuit is coupled to the fifth node, the second power supply terminal and the cascade signal output terminal respectively; the second cascade output circuit is configured to provide the signal of the second power supply terminal to the cascade signal output terminal in response to the signal of the fifth node; the gate of the eighth switching transistor is coupled to the fifth node.
  • the input circuit includes: a ninth switch transistor, a tenth switch transistor and an eleventh switch transistor;
  • the gate of the ninth switch transistor is coupled to the first clock signal terminal, the first electrode of the ninth switch transistor is coupled to the input signal terminal, and the second electrode of the ninth switch transistor is coupled to the first node;
  • the gate of the tenth switch transistor is coupled to the first clock signal terminal, the first electrode of the tenth switch transistor is coupled to the input signal terminal, and the second electrode of the tenth switch transistor is coupled to the first electrode of the eleventh switch transistor;
  • a gate of the eleventh switch transistor is coupled to the second power supply terminal, and a second electrode of the eleventh switch transistor is coupled to the second node.
  • the node control circuit includes: a twelfth switch transistor, a thirteenth switch transistor, a fourteenth switch transistor, a fifteenth switch transistor, a sixteenth switch transistor, a seventeenth switch transistor, an eighteenth switch transistor, a nineteenth switch transistor, a second capacitor and a third capacitor; wherein,
  • the gate of the twelfth switch transistor is coupled to the first clock signal terminal, the first electrode of the twelfth switch transistor is coupled to the second power supply terminal, and the second electrode of the twelfth switch transistor is coupled to the third node;
  • the gate of the thirteenth switch transistor is coupled to the first node, the first electrode of the thirteenth switch transistor is coupled to the first clock signal terminal, and the second electrode of the thirteenth switch transistor is coupled to the third node;
  • the gate and the first electrode of the fourteenth switch transistor are coupled to the second node, and the second electrode of the fourteenth switch transistor is coupled to the fifth node;
  • the gate of the fifteenth switch transistor is coupled to the second node, the first electrode of the fifteenth switch transistor is coupled to the second clock signal terminal, and the second electrode of the fifteenth switch transistor is coupled to the first electrode of the sixteenth switch transistor;
  • the gate of the sixteenth switch transistor is coupled to the third node, and the second electrode of the sixteenth switch transistor is coupled to the first power supply terminal;
  • a first terminal of the second capacitor is coupled to the second node, and a second terminal of the second capacitor is coupled to a first electrode of the sixteenth switch transistor;
  • the gate of the seventeenth switch transistor is coupled to the second power supply terminal, the first electrode of the seventeenth switch transistor is coupled to the third node, and the second electrode of the seventeenth switch transistor is coupled to the gate of the eighteenth switch transistor;
  • a first electrode of the eighteenth switch transistor is coupled to the second clock signal terminal, and a second electrode of the eighteenth switch transistor is coupled to a first electrode of the nineteenth switch transistor;
  • the gate of the nineteenth switch transistor is coupled to the second clock signal terminal, and the second electrode of the nineteenth switch transistor is coupled to the fourth node;
  • a first terminal of the third capacitor is coupled to the gate of the eighteenth switch transistor, and a second terminal of the third capacitor is coupled to the second electrode of the eighteenth switch transistor.
  • the reset circuit includes: a twentieth switch transistor, a twenty-first switch transistor and a twenty-second switch transistor; wherein,
  • a gate of the 20th switch transistor is coupled to the reset signal terminal, a first electrode of the 20th switch transistor is coupled to the first power supply terminal, and a second electrode of the 20th switch transistor is coupled to the first node and a gate of the 21st switch transistor;
  • a first electrode of the twenty-first switch transistor is coupled to the first power supply terminal, and a second electrode of the twenty-first switch transistor is coupled to the fourth node;
  • a gate of the twenty-second switch transistor is coupled to the second power supply terminal, a first electrode of the twenty-second switch transistor is coupled to the first node, and a second electrode of the twenty-second switch transistor is coupled to the fifth node.
  • the first cascade output circuit includes: a twenty-third switch transistor and a fourth capacitor; wherein,
  • a gate of the twenty-third switch transistor is coupled to the fourth node, a first electrode of the twenty-third switch transistor is coupled to the first power supply terminal, and a second electrode of the twenty-third switch transistor is coupled to the cascade signal output terminal;
  • a first terminal of the fourth capacitor is coupled to the fourth node, and a second terminal of the fourth capacitor is coupled to the first power supply terminal.
  • the second cascade output circuit includes a twenty-fourth switching transistor, a gate of the twenty-fourth switching transistor is coupled to the fifth node, a first electrode of the twenty-fourth switching transistor is coupled to the second power supply terminal, and a second electrode of the twenty-fourth switching transistor is coupled to the cascade signal output terminal.
  • the gate driving circuit provided by the embodiment of the present disclosure comprises a plurality of cascaded shift registers as described above;
  • the input signal terminal of the first stage shift register is configured to be coupled to the frame trigger signal terminal;
  • the input signal terminal of the subsequent shift register is configured to be coupled to the cascade signal output terminal of the previous shift register.
  • the display device provided by the embodiment of the present disclosure includes the above-mentioned gate driving circuit.
  • the latch module provides the control signal of the masking signal terminal to the selection output module according to the signal of the cascade signal output terminal and the reverse signal output terminal of the previous stage; the selection output module provides the signal of the first power supply terminal to the driving signal output terminal in response to the control signal of the masking signal terminal;
  • the latch module provides the control signal of the mask signal end to the selection output module according to the signal of the cascade signal output end and the reverse signal output end of the previous stage; the selection output module responds to the control signal of the mask signal end and provides the signal of the second power supply end to the drive signal output end.
  • FIG1 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure.
  • FIG2 is a schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure.
  • FIG3 is a schematic diagram of the structure of another shift register provided by an embodiment of the present disclosure.
  • FIG4 is a schematic diagram of the structure of a pixel circuit provided by an embodiment of the present disclosure.
  • FIG5 is a signal timing diagram corresponding to the operation of the pixel circuit shown in FIG4 ;
  • FIG6 is a signal timing diagram of the shift register operation provided by an embodiment of the present disclosure.
  • FIG7 is a simulation diagram corresponding to the driving signal output terminal of the shift register shown in FIG6 ;
  • FIG8 is a flow chart of a driving method provided by an embodiment of the present disclosure.
  • FIG9 is a schematic diagram of the structure of a gate driving circuit provided in an embodiment of the present disclosure.
  • FIG. 10 is a schematic diagram of the structure of a display device provided in an embodiment of the present disclosure.
  • the present disclosure provides a shift register, as shown in FIG. 1 and FIG. 2 , which may include:
  • the shift module 1 is coupled to the input signal terminal IP and the cascade signal output terminal GP(n) respectively; the shift module 1 is configured to respond to the signal of the input signal terminal IP so that the cascade signal output terminal GP(n) outputs the cascade signal;
  • the reverse output module 2 is coupled to the cascade signal output terminal GP(n), the first power supply terminal VGH, the second power supply terminal VGL and the reverse signal output terminal Anti-GP(n) respectively; the reverse output module 2 is configured to respond to the signal of the cascade signal output terminal GP(n) so that the reverse signal output terminal Anti-GP(n) outputs a signal opposite to that of the cascade signal output terminal GP(n);
  • the latch module 3 is respectively coupled to the masking signal terminal Vms, the cascade signal output terminal GP(n), and the previous stage reverse signal output terminal Anti-GP(n-1); the latch module 3 is configured to respond to the signals of the cascade signal output terminal GP(n) and the previous stage reverse signal output terminal Anti-GP(n-1), so that the output terminal of the latch module 3 outputs the signal of the masking signal terminal Vms;
  • the output selection module 4 is coupled to the first power supply terminal VGH, the second power supply terminal VGL, the output terminal of the latch module 3 and the drive signal output terminal OP(n), respectively; the output selection module 4 is configured to respond to the signal of the output terminal of the latch module 3 and provide the signal of the first power supply terminal VGH or the second power supply terminal VGL to the drive signal output terminal OP(n).
  • the shift register provided in the embodiment of the present disclosure is provided with a reverse output module, a latch module and a selection output module coupled to the shift module.
  • the control signal of the corresponding mask signal end is latched in the selection output module, so as to realize the control of the signal outputted by the drive signal output end, and realize different refresh rates in different areas of the display panel, that is, high and low refresh rates can coexist in the same frame, and the embodiment of the present disclosure is not limited to realizing different refresh rates in a fixed area of the display panel, and can realize dynamic refresh of any area, so as to reduce the power consumption of the display panel;
  • the latch module can use the phase difference of the cascade signal outputted by the front and rear stages of the shift module to store the control signal of the mask signal end into each stage of the shift register, so as to realize the continuous correct output of the shift register of this stage; and only one control line electrically connected to the mask signal end is needed to control the adaptive refresh rate of the
  • the shift module 1 may include:
  • the input circuit 11 is coupled to the input signal terminal IP, the first clock signal terminal CK, the second power supply terminal VGL, the first node P1 and the second node P2 respectively; the input circuit 11 is configured to provide the signal of the input signal terminal IP to the first node P1 and the second node P2 in response to the signal of the first clock signal terminal CK; for example, the input circuit 11 may include: a ninth switch transistor T9, a tenth switch transistor T10 and an eleventh switch transistor T11; the gate of the ninth switch transistor T9 is coupled to the first clock signal terminal CK, the first electrode of the ninth switch transistor T9 is coupled to the input signal terminal IP, and the second electrode of the ninth switch transistor T9 is coupled to the first node P1; the gate of the tenth switch transistor T10 is coupled to the first clock signal terminal CK, the first electrode of the tenth switch transistor T10 is coupled to the input signal terminal IP, and the second electrode of the tenth switch transistor T10 is coupled to the first electrode of the eleventh switch transistor T11
  • the node control circuit 12 is coupled to the first node P1, the second node P2, the third node P3, the fourth node P4, the fifth node P5, the first power supply terminal VGH, the second power supply terminal VGL, the first clock signal terminal CK and the second clock signal terminal CB respectively; the node control circuit 12 is configured to adjust the signals of the first node P1, the second node P2, the third node P3, the fourth node P4 and the fifth node P5, so that the cascade signal output terminal GP(n) outputs the signal of the first power supply terminal VGH or the signal of the second power supply terminal VGL; for example, the node control circuit 12 may include: a twelfth switch transistor T12, a thirteenth switch transistor T13, a fourteenth switch transistor T14, a fifteenth switch transistor T15, a sixteenth switch transistor T16, a seventeenth switch transistor T17, an eighteenth switch transistor T18, a nineteenth switch transistor T19, a second capacitor C2 and a third capacitor C3;
  • a gate of the twelfth switch transistor T12 is coupled to the first clock signal terminal CK, a first electrode of the twelfth switch transistor T12 is coupled to the second power supply terminal VGL, and a second electrode of the twelfth switch transistor T12 is coupled to the third node P3;
  • a gate of the thirteenth switch transistor T13 is coupled to the first node P1, a first electrode of the thirteenth switch transistor T13 is coupled to the first clock signal terminal CK, and a second electrode of the thirteenth switch transistor T13 is coupled to the third node P3;
  • the gate and the first electrode of the fourteenth switch transistor T14 are coupled to the second node P2, and the second electrode of the fourteenth switch transistor T14 is coupled to the fifth node P5;
  • a gate of the fifteenth switch transistor T15 is coupled to the second node P2, a first electrode of the fifteenth switch transistor T15 is coupled to the second clock signal terminal CB, and a second electrode of the fifteenth switch transistor T15 is coupled to a first electrode of the sixteenth switch transistor T16;
  • a gate of the sixteenth switch transistor T16 is coupled to the third node P3, and a second electrode of the sixteenth switch transistor T16 is coupled to the first power supply terminal VGH;
  • a first terminal of the second capacitor C2 is coupled to the second node P2, and a second terminal of the second capacitor C2 is coupled to a first electrode of the sixteenth switch transistor T16;
  • a gate of the seventeenth switch transistor T17 is coupled to the second power supply terminal VGL, a first electrode of the seventeenth switch transistor T17 is coupled to the third node P3, and a second electrode of the seventeenth switch transistor T17 is coupled to a gate of the eighteenth switch transistor T18;
  • a first electrode of the eighteenth switch transistor T18 is coupled to the second clock signal terminal CB, and a second electrode of the eighteenth switch transistor T18 is coupled to a first electrode of the nineteenth switch transistor T19;
  • a gate of the nineteenth switch transistor T19 is coupled to the second clock signal terminal CB, and a second electrode of the nineteenth switch transistor T19 is coupled to the fourth node P4;
  • a first terminal of the third capacitor C3 is coupled to the gate of the eighteenth switch transistor T18, and a second terminal of the third capacitor C3 is coupled to the second electrode of the eighteenth switch transistor T18;
  • the reset circuit 13 is coupled to the first power supply terminal VGH, the reset signal terminal VEL, the first node P1, the fourth node P4 and the fifth node P5 respectively; the reset circuit 13 is configured to reset the cascade signal output by the cascade signal output terminal GP(n) in response to the signal of the reset signal terminal VEL; specifically, the reset circuit 13 is configured to reset the voltages of the fourth node P4 and the fifth node P5 in response to the signal of the reset signal terminal VEL, and then reset the cascade signal output by the cascade signal output terminal GP(n); for example, the reset circuit 13 may include: a twentieth switch transistor T20, a twenty-first switch transistor T21 and a twenty-second switch transistor T22; wherein,
  • a gate of the twentieth switch transistor T20 is coupled to the reset signal terminal VEL, a first electrode of the twentieth switch transistor T20 is coupled to the first power supply terminal VGH, and a second electrode of the twentieth switch transistor T20 is coupled to the first node P1 and a gate of the twenty-first switch transistor T21;
  • a first electrode of the twenty-first switch transistor T21 is coupled to the first power supply terminal VGH, and a second electrode of the twenty-first switch transistor T21 is coupled to the fourth node P4;
  • a gate of the twenty-second switch transistor T22 is coupled to the second power supply terminal VGL, a first electrode of the twenty-second switch transistor T22 is coupled to the first node P1, and a second electrode of the twenty-second switch transistor T22 is coupled to the fifth node P5;
  • the first cascade output circuit 14 is coupled to the fourth node P4, the first power supply terminal VGH and the cascade signal output terminal GP(n) respectively; the first cascade output circuit 14 is configured to respond to the signal of the fourth node P4 and provide the signal of the first power supply terminal VGH to the cascade signal output terminal GP(n); for example, the first cascade output circuit 14 may include: a twenty-third switch transistor T23 and a fourth capacitor C4; wherein,
  • a gate of the twenty-third switch transistor T23 is coupled to the fourth node P4, a first electrode of the twenty-third switch transistor T23 is coupled to the first power supply terminal VGH, and a second electrode of the twenty-third switch transistor T23 is coupled to the cascade signal output terminal GP(n);
  • a first terminal of the fourth capacitor C4 is coupled to the fourth node P4 , and a second terminal of the fourth capacitor C4 is coupled to the first power supply terminal VGH.
  • the second cascade output circuit 15 is coupled to the fifth node P5, the second power supply terminal VGL and the cascade signal output terminal GP(n), respectively; the second cascade output circuit 15 is configured to provide the signal of the second power supply terminal VGL to the cascade signal output terminal GP(n) in response to the signal of the fifth node P5; for example, the second cascade output circuit 15 may include a twenty-fourth switching transistor T24, the gate of the twenty-fourth switching transistor T24 is coupled to the fifth node P5, the first electrode of the twenty-fourth switching transistor T24 is coupled to the second power supply terminal VGL, and the second electrode of the twenty-fourth switching transistor T24 is coupled to the cascade signal output terminal GP(n).
  • all the switch transistors of the shift module 1 can be P-type transistors.
  • the main function of the shift module 1 provided in the embodiment of the present disclosure is to realize the function of shifting from top to bottom in timing.
  • the embodiment of the present disclosure selects a 16T3C shift module 1 that transmits signals more stably.
  • the shift module 1 is not limited to the 16T3C structure provided in the embodiment of the present disclosure, and can be a variety of other shift registers that can realize the shift function, such as 10T3C, 12T3C, 13T3C, etc. commonly used in OLED display panels.
  • FIG3 is a schematic diagram of the structure of another shift module 1 provided in the embodiment of the present disclosure.
  • the shift module 1 has the same function as the shift module 1 in FIG1 and FIG2 , and will not be described in detail here.
  • the reverse output module 2 may include: a first switch transistor T1 and a second switch transistor T2; the first switch transistor T1 and the second switch transistor T2 are of different types, for example, the first switch transistor T1 is a P-type transistor, and the second switch transistor T2 is an N-type transistor; wherein,
  • the gate of the first switch transistor T1 is coupled to the cascade signal output terminal GP(n), the first electrode of the first switch transistor T1 is coupled to the first power supply terminal VGH, and the second electrode of the first switch transistor T1 is coupled to the reverse signal output terminal Anti-GP(n);
  • the gate of the second switch transistor T2 is coupled to the cascade signal output terminal GP(n), the first electrode of the second switch transistor T2 is coupled to the second power supply terminal VGL, and the second electrode of the second switch transistor T2 is coupled to the reverse signal output terminal Anti-GP(n).
  • the reverse output module 2 uses the circuit structure of N-type transistors and P-type transistors to construct the reverse signal of GP(n-1), so that the latch module uses the phase difference of the cascade signals output by the front and rear stages of the shift module to write the required control signal of the masked signal terminal in advance, so that one control signal can control the output of multiple valid level signals (high level).
  • the latch module 3 may include: a third switch transistor T3 and a fourth switch transistor T4; wherein,
  • the gate of the third switch transistor T3 is coupled to the cascade signal output terminal GP(n), the first electrode of the third switch transistor T3 is coupled to the mask signal terminal Vms, and the second electrode of the third switch transistor T3 is coupled to the first electrode of the fourth switch transistor T4;
  • a gate of the fourth switch transistor T4 is coupled to the previous stage reverse signal output terminal Anti-GP(n ⁇ 1), and a second electrode of the fourth switch transistor T4 is an output terminal of the latch module 3 .
  • the latch module 3 may include: a third switch transistor T3 and a fourth switch transistor T4; wherein,
  • a gate of the fourth switch transistor T4 is coupled to the cascade signal output terminal GP(n), a first electrode of the fourth switch transistor T4 is coupled to the mask signal terminal Vms, and a second electrode of the fourth switch transistor T4 is coupled to a first electrode of the third switch transistor T3;
  • the gate of the third switch transistor T3 is coupled to the previous stage reverse signal output terminal Anti-GP(n ⁇ 1), and the second electrode of the third switch transistor T3 is the output terminal of the latch module 3 .
  • the latch module 3 utilizes the phase difference between the signal of the reverse signal output terminal Anti-GP(n-1) of the previous stage and the signal of the cascade signal output terminal GP(n) to realize that the control signal of the masking signal terminal Vms is written in advance and stored in the selection output module 4, so that the signal of the first power supply terminal VGH can be consistent with the GP(n) signal, and a plurality of valid level signals (high level) can be output for a long time.
  • the selection output module 4 may include: a fifth switch transistor T5, a sixth switch transistor T6 and a first capacitor C1; the fifth switch transistor T5 and the sixth switch transistor T6 are of different types, for example, the fifth switch transistor T5 is a P-type transistor, and the sixth switch transistor T6 is an N-type transistor; wherein,
  • a gate of the fifth switch transistor T5 is coupled to the second electrode of the fourth switch transistor T4, and a first electrode of the fifth switch transistor T5 is coupled to the drive signal output terminal OP(n);
  • a gate of the sixth switch transistor T6 is coupled to the second electrode of the fourth switch transistor T4, a first electrode of the sixth switch transistor T6 is coupled to the second power supply terminal VGL, and a second electrode of the sixth switch transistor T6 is coupled to the drive signal output terminal OP(n);
  • a first terminal of the first capacitor C1 is coupled to the first power supply terminal VGH, and a second terminal of the first capacitor C1 is coupled to the second electrode of the fourth switch transistor T4.
  • the output module 4 selects the high-level signal or low-level signal written by the masking signal terminal Vms to convert the high-level signal output by the driving signal output terminal OP(n) into a low-level signal, or maintains the high-level signal output normally, so as to meet the requirements of different refresh rates in the display area.
  • the selection output module 4 may also include: a seventh switch transistor T7; the type of the seventh switch transistor T7 is the same as the type of the fifth switch transistor T5, for example, the seventh switch transistor T7 is a P-type transistor; the gate of the seventh switch transistor T7 is coupled to the shift module 1 (the fourth node P4), the first electrode of the seventh switch transistor T7 is coupled to the first power supply terminal VGH, and the second electrode of the seventh switch transistor T7 is coupled to the second electrode of the fifth switch transistor T5.
  • the control signal of the masking signal terminal Vms can be controlled to be a high level or a low level according to the demand of the display refresh rate, so that the driving signal output terminal OP(n) outputs a low level or a high level, thereby achieving different refresh rates in different areas of the display panel.
  • the second electrode of the fifth switch transistor T5 can be directly coupled to the cascade signal output terminal GP(n).
  • the structure of the selection output module 4 shown in FIG2 is reduced by a seventh switch transistor T7 which is co-gate with the twenty-third switch transistor T23 compared with the structure of the selection output module 4 shown in FIG1 , because the fifth switch transistor T5 can lock the voltage of the cascade signal output terminal GP(n), and can directly output the high-level signal output by the cascade signal output terminal GP(n) to the drive signal output terminal OP(n), which can reduce a seventh switch transistor T7 (Buffer tube) and save LayOP wiring space.
  • the shift register in the above-mentioned shift register provided in the embodiment of the present disclosure, as shown in Figures 1-3, it also includes an eighth switch transistor T8, the gate of the eighth switch transistor T8 is coupled to the shift module (the fifth node P5), the first electrode of the eighth switch transistor T8 is coupled to the second power supply terminal VGL, and the second electrode of the eighth switch transistor T8 is coupled to the drive signal output terminal OP(n).
  • the main function of the eighth switching transistor T8 is to distinguish the signal of the second power supply terminal VGL output to the drive signal output terminal OP(n) from the normal cascade signal of the transmitted cascade signal output terminal GP(n), so as to avoid signal disorder caused by the difference between the signal of the drive signal output terminal OP(n) and the signal of the cascade signal output terminal GP(n) when the control signal is written to the masking signal terminal Vms, thereby realizing the normal shifting function of the shift register.
  • the first switch transistor T1, the third switch transistor T3, the fourth switch transistor T4, the fifth switch transistor T5 and the eighth switch transistor T8 are all P-type transistors, and the second switch transistor T2 and the sixth switch transistor T6 are all N-type transistors.
  • the P-type transistor is turned off under the action of a high-level signal and turned on under the action of a low-level signal
  • the N-type transistor is turned on under the action of a high-level signal and turned off under the action of a low-level signal.
  • control signal of the masking signal terminal Vms when the control signal of the masking signal terminal Vms is a low-level signal, it can be -20V to -5V, and when it is a high-level signal, it can be 5V to 20V.
  • the signal of the first power supply terminal VGH is a high level signal, for example, 5V to 10V; the signal of the second power supply terminal VGL is a low level signal, for example, -10V to -5V.
  • the signal at the first clock signal terminal CK and the signal at the second clock signal terminal CB are AC signals with the same period and opposite potentials.
  • the first electrode of each switching transistor can be used as its source, and the second electrode can be used as its drain; or, the first electrode can be used as its drain, and the second electrode can be used as its source, without making a specific distinction here.
  • the switching transistor mentioned in the above embodiments of the present disclosure can be a TFT or a Metal Oxide Semiconductor Field Effect Transistor (MOS), which is not limited here.
  • MOS Metal Oxide Semiconductor Field Effect Transistor
  • the shift register provided in the embodiment of the present disclosure can be used to provide a driving signal to an organic light emitting display panel, wherein the display area of the organic light emitting display panel includes a plurality of sub-pixels, each of which is generally provided with a plurality of organic light emitting diodes and a pixel circuit connected to each organic light emitting diode.
  • the pixel circuit can be a 6T1C, 7T1C or other structure, as shown in FIG4 , FIG4 is a 7T1C pixel circuit structure provided in the embodiment of the present disclosure
  • the driving signal output terminal OP(n) of the shift register shown in FIG1 to FIG3 outputs a driving signal mainly used to control an oxide switch transistor in a row of pixel circuits in the display panel (used to provide a scanning signal to the gate of the first scanning transistor M2 in FIG4 ), when a frame needs to be refreshed, the driving signal output terminal OP(n) outputs a high level for a period of time, and outputs a low level for the remaining time period in a frame time, controls the first scanning transistor M2 to be turned on, and realizes the refreshing of the data voltage; when in a non-refreshing frame, the driving signal output terminal OP(n) always outputs a low level, and the first scanning transistor M2 cannot be turned on, thereby realizing the non-refreshing of the data voltage.
  • the pixel circuit provided by the embodiment of the present disclosure is not limited to the structure shown in FIG. 4 . Any pixel circuit that requires the initialization transistor M1 and the scan transistor M2 to be turned on at the same time to provide an initialization signal to the N1 node belongs to the pixel circuit structure protected by the embodiment of the present disclosure.
  • the working process of the pixel circuit shown in FIG4 is first described in conjunction with the signal timing diagram shown in FIG5. Specifically, four stages of the first initialization stage T1', the data writing stage T2', the second initialization stage T3' and the light emitting stage T4' in one frame time period are selected in the signal timing diagram shown in FIG5.
  • the first control terminal PSR1 inputs a low level signal
  • the first initialization transistor M1 is turned on
  • the first initialization signal terminal Vint1 provides an initialization signal to the N3 node to initialize the N3 node.
  • the first scan control terminal P_Scan inputs a low level signal
  • the second scan control terminal N_Scan inputs a high level signal
  • the first scan transistor M2 and the second scan transistor M4 are both turned on
  • the driving transistor M3 maintains the on state of the previous frame light-emitting stage, so the data voltage of the data signal terminal D is written to the N1 node.
  • the second control terminal PSR2 inputs a low level signal
  • the second initialization transistor M7 is turned on
  • the second initialization signal terminal Vint2 provides an initialization signal to the anode of the OLED to initialize the anode.
  • the light-emitting control terminal EM inputs a low-level signal
  • the first light-emitting control transistors M5 and M6 are both turned on
  • the signal of the first power supply terminal VDD generates a current through the driving transistor M3 to drive the OLED to emit light.
  • the working sequence of the above pixel circuit is the first frame. If the refresh rate of the first frame needs to be maintained in the second frame (i.e., the second frame does not need to be refreshed), the first scanning transistor M2 needs to be controlled to be turned off in the data writing phase T2', so that the drive signal output terminal OP(n) of the shift register provided by the embodiment of the present disclosure needs to input a low-level signal, that is, the second scanning control terminal N_Scan in FIG5 originally inputs a high-level signal (dashed line A) and needs to be changed to a low-level signal, so as to achieve the second frame as the refresh rate maintenance frame of the first frame.
  • the shift register shown in FIG1-FIG3 provided by the embodiment of the present disclosure can achieve different refresh rates in different areas of the display panel.
  • the following takes the shift register shown in FIG. 1 as an example and describes the working principle of the shift register provided in the embodiment of the present disclosure to control the display panel to achieve different refresh rates in different areas in combination with the signal timing diagram shown in FIG. 6 .
  • the signal timing diagram shown in FIG6 only takes the input (IP) and output (OP(1), OP(2), OP(3), OP(4)) of the first four-stage shift register as an example.
  • IP input
  • OP(1), OP(2), OP(3), OP(4) input
  • the signal at the cascade signal output terminal GP(1) of the first-stage shift register and the signal at the reverse signal output terminal Anti-GP(0) of the previous stage are both low-level signals (at time t1)
  • the third switch transistor T3 and the fourth switch transistor T4 are both turned on, that is, at time t1, the low-level signal of the masking signal terminal Vms is latched in the first capacitor C1 of the selection output module 4, and when the first-stage cascade signal output terminal GP(1) outputs a high level (at time T1”), the fourth node
  • the signal at P4 is a low level signal and the signal at the fifth
  • the fifth switch transistor T5 is turned on and the sixth switch transistor T6 is turned off. Then, at the time T1", the drive signal output terminal OP(1) of the first-stage shift register outputs a high level signal of the first power supply terminal VGH, thereby realizing a high refresh rate of the first row of pixels in the display area.
  • the maintenance time of the high level signal of the first power supply terminal VGH output by the drive signal output terminal OP(1) of the first-stage shift register can be set as required.
  • the maintenance time of the high level signal of the first power supply terminal VGH output by the drive signal output terminal OP(1) of the first-stage shift register overlaps with the high level signal of the first power supply terminal VGH output by the drive signal output terminal OP(4) of the fourth-stage shift register, so the pixel circuit corresponding to the drive signal output terminal OP(4) of the fourth-stage shift register can be pre-charged.
  • the holding time of the output level signal of the driving signal output terminal OP(n) of the other stages of shift registers is similar and will not be described in detail.
  • the third switch transistor T3 and the fourth switch transistor T4 are both turned on, that is, at time t2, the high-level signal of the masking signal terminal Vms is latched in the first capacitor C1 of the selection output module 4;
  • the second-stage cascade signal output terminal GP(2) outputs a high level (at time T2”)
  • the signal of the fourth node P4 is a low-level signal
  • the signal of the fifth node P5 is a high-level signal
  • the seventh switch transistor T7 is turned on, and since the first capacitor C1 maintains the high-level signal of the masking signal terminal Vms at time t1, the fifth switch transistor T5 is turned off, and the sixth switch transistor T6 is turned on, then at time T2”, the drive signal output terminal OP(2) of the second-stage shift register outputs a low-
  • the third switch transistor T3 and the fourth switch transistor T4 are both turned on, that is, at time T3, the high-level signal of the masking signal terminal Vms is locked in the first capacitor C1 of the selection output module 4;
  • the third-stage cascade signal output terminal GP(3) outputs a high level (at time T3”)
  • the signal of the fourth node P4 is a low-level signal
  • the signal of the fifth node P5 is a high-level signal
  • the seventh switch transistor T7 is turned on, and since the first capacitor C1 maintains the high-level signal of the masking signal terminal Vms at time t1, the fifth switch transistor T5 is turned off, and the sixth switch transistor T6 is turned on, then at time T3”,
  • the drive signal output terminal OP(3) of the third-stage shift register outputs a low-level signal of
  • the third switch transistor T3 and the fourth switch transistor T4 are both turned on, that is, at time t4, the low-level signal of the masking signal terminal Vms is latched in the first capacitor C1 of the selection output module 4.
  • the fourth-stage cascade signal output terminal GP(4) outputs a high-level signal (at time T4”), the signal at the fourth node P4 is a low-level signal, and the signal at the fifth node P5 is a high-level signal. Then, the seventh switch transistor T7 is turned on.
  • the drive signal output terminal OP(4) of the fourth-stage shift register outputs a high-level signal of the first power supply terminal VGH, thereby realizing a high refresh rate of the fourth row of pixels in the display area.
  • the oxide switching transistor (M2 in Figure 3) of the corresponding pixel circuit in the display panel is cut off, and the data voltage in the display panel is not charged, and the state of the previous frame is maintained, thereby achieving a low refresh rate in this area.
  • the oxide switching transistors of the pixel circuits in different rows of the same frame can be selectively turned on or off based on the duration of the high-level signal input to the masking signal terminal Vms (for example, the working time of 2-3 rows of pixel circuits) and the signal combined with the cascade signal output terminal and the reverse signal output terminal of the previous stage, thereby achieving the refresh rate of different rows of the display panel.
  • the signal output from the drive signal output terminal OP(n) of the shift register shown in FIG1 is simulated, and the simulation diagram is shown in FIG7 .
  • the horizontal axis represents time
  • the vertical axis represents voltage.
  • the embodiment of the present disclosure only takes the area corresponding to the second row of pixels and the third row of pixels in the display panel as the low refresh rate area to illustrate the working process of the shift register.
  • the low refresh rate can be achieved for any area in the display panel.
  • the embodiment of the present disclosure further provides a driving method of the above shift register, which, as shown in FIG8 , may include:
  • the latch module in the first refresh rate stage, provides the control signal of the masking signal terminal to the selection output module according to the signal of the cascade signal output terminal and the reverse signal output terminal of the previous stage; the selection output module provides the signal of the first power supply terminal to the driving signal output terminal in response to the control signal of the masking signal terminal; for example, in the first refresh rate stage, the latch module provides the low-level control signal of the masking signal terminal to the selection output module according to the signal of the cascade signal output terminal of this stage and the reverse signal output terminal of the previous stage; the selection output module provides the high-level signal of the first power supply terminal to the driving signal output terminal in response to the low-level control signal of the masking signal terminal.
  • the latch module in the second refresh rate stage, provides the control signal of the masking signal terminal to the selection output module according to the signal of the cascade signal output terminal and the reverse signal output terminal of the previous stage; the selection output module responds to the control signal of the masking signal terminal and provides the signal of the second power supply terminal to the driving signal output terminal.
  • the latch module provides the high-level control signal of the masking signal end to the selection output module according to the signal of the cascade signal output end of this stage and the reverse signal output end of the previous stage; the selection output module responds to the high-level control signal of the masking signal end and provides the low-level signal of the first power supply end to the driving signal output end.
  • the first refresh rate stage corresponds to a high refresh rate stage in the aforementioned shift register
  • the second refresh rate stage corresponds to a low refresh rate stage in the aforementioned shift register.
  • the driving principle and specific implementation of the driving method are the same as those of the shift register in the above embodiment. Therefore, the driving method can be implemented with reference to the specific implementation of the shift register in the above embodiment, which will not be described in detail here.
  • the embodiment of the present disclosure further provides a gate driving circuit, as shown in FIG9 , comprising a plurality of cascaded shift registers SR(1), SR(2)...SR(n-1), SR(n)...SR(N-1), SR(N) provided in the embodiment of the present disclosure (a total of N shift registers, 1 ⁇ n ⁇ N, n is an integer); wherein the input signal terminal IP of the first-stage shift register SR(1) is configured to be coupled to the frame trigger signal terminal STV;
  • the input signal terminal IP of the subsequent shift register SR(n) is configured to be coupled to the cascade signal output terminal GP(n) of the previous shift register SR(n-1).
  • each shift register in the above-mentioned gate drive circuit is the same as the above-mentioned shift register in the present disclosure in terms of function and structure, and the repeated parts are not repeated.
  • the gate drive circuit can be configured in a liquid crystal display panel or in an electroluminescent display panel, which is not limited here.
  • the embodiment of the present disclosure also provides a display device, including the above-mentioned gate driving circuit provided by the embodiment of the present disclosure.
  • the principle of solving the problem by the display device is similar to that of the above-mentioned shift register, so the implementation of the display device can refer to the implementation of the above-mentioned shift register, and the repeated parts will not be repeated here.
  • the display device provided in the embodiment of the present disclosure may be a mobile phone as shown in FIG10.
  • the display device provided in the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc.
  • a display function such as a tablet computer, a television, a display, a laptop computer, a digital photo frame, a navigator, etc.
  • Other essential components of the display device should be understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used as a limitation to the present disclosure.
  • the display device provided in the embodiment of the present disclosure may be a liquid crystal display device or an organic light emitting display device.

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Abstract

一种移位寄存器、驱动方法、栅极驱动电路及显示装置，其中，移位寄存器，包括: 移位模块（1），移位模块（1）被配置为响应于输入信号端（IP）的信号，使级联信号输出端（GP(n)）输出级联信号；反向输出模块（2），反向输出模块（2）被配置为响应于级联信号输出端（GP(n)）的信号，使反向信号输出端（Anti-GP(n)）输出与级联信号输出端（GP(n)）相反的信号；锁存模块（3），锁存模块（3）被配置为响应于级联信号输出端（GP(n)）以及前一级反向信号输出端（Anti-GP(n-1)）的信号，使锁存模块（3）的输出端输出掩蔽信号端（Vms）的控制信号；选择输出模块（4），选择输出模块（4）被配置为响应于锁存模块（3）的输出端的信号，将第一电源端（VGH）或第二电源端（VGL）的信号提供给驱动信号输出端（OP(n)）。

Description

一种移位寄存器、驱动方法、栅极驱动电路及显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种移位寄存器、驱动方法、栅极驱动电路及显示装置。
背景技术
随着显示技术的飞速发展，显示装置越来越向着高集成度和低成本的方向发展。其中，GOA(Gate Driver on Array，阵列基板行驱动)技术将TFT(Thin Film Transistor，薄膜晶体管)栅极驱动电路集成在显示装置的阵列基板上以形成对显示装置的扫描驱动。其中，栅极驱动电路通常由多个级联的移位寄存器构成。然而，现有的移位寄存器的驱动模式无法在同一个显示区域实现不同的刷新率。
发明内容
本公开实施例提供的一种移位寄存器，包括：
移位模块，分别与输入信号端和级联信号输出端耦接；所述移位模块被配置为响应于所述输入信号端的信号，使所述级联信号输出端输出级联信号；
反向输出模块，分别与所述级联信号输出端、第一电源端、第二电源端以及反向信号输出端耦接；所述反向输出模块被配置为响应于所述级联信号输出端的信号，使所述反向信号输出端输出与所述级联信号输出端相反的信号；
锁存模块，分别与掩蔽信号端、所述级联信号输出端、前一级所述反向信号输出端耦接；所述锁存模块被配置为响应于所述级联信号输出端以及前一级所述反向信号输出端的信号，使所述锁存模块的输出端输出所述掩蔽信号端的控制信号；
选择输出模块，分别与所述第一电源端、所述第二电源端、所述锁存模 块的输出端以及驱动信号输出端耦接；所述选择输出模块被配置为响应于所述锁存模块的输出端的信号，将所述第一电源端或所述第二电源端的信号提供给所述驱动信号输出端。
可选地，在本公开实施例中，所述反向输出模块包括：第一开关晶体管和第二开关晶体管；所述第一开关晶体管和所述第二开关晶体管的类型不同；其中，
所述第一开关晶体管的栅极与所述级联信号输出端耦接，所述第一开关晶体管的第一极与所述第一电源端耦接，所述第一开关晶体管的第二极与所述反向信号输出端耦接；
所述第二开关晶体管的栅极与所述级联信号输出端耦接，所述第二开关晶体管的第一极与所述第二电源端耦接，所述第二开关晶体管的第二极与所述反向信号输出端耦接。
可选地，在本公开实施例中，所述锁存模块包括：第三开关晶体管和第四开关晶体管；其中，
所述第三开关晶体管的栅极与所述级联信号输出端耦接，所述第三开关晶体管的第一极与所述掩蔽信号端耦接，所述第三开关晶体管的第二极与所述第四开关晶体管的第一极耦接；
所述第四开关晶体管的栅极与前一级所述反向信号输出端耦接，所述第四开关晶体管的第二极为所述锁存模块的输出端。
可选地，在本公开实施例中，所述选择输出模块包括：第五开关晶体管、第六开关晶体管和第一电容；所述第五开关晶体管和所述第六开关晶体管的类型不同；其中，
所述第五开关晶体管的栅极与所述第四开关晶体管的第二极耦接，所述第五开关晶体管的第一极与所述驱动信号输出端耦接；
所述第六开关晶体管的栅极与所述第四开关晶体管的第二极耦接，所述第六开关晶体管的第一极与所述第二电源端耦接，所述第六开关晶体管的第二极与所述驱动信号输出端耦接；
所述第一电容的第一端与所述第一电源端耦接，所述第一电容的第二端与所述第四开关晶体管的第二极耦接。
可选地，在本公开实施例中，所述第五开关晶体管的第二极与所述级联信号输出端耦接。
可选地，在本公开实施例中，所述选择输出模块还包括：第七开关晶体管；所述第七开关晶体管的类型与所述第五开关晶体管的类型相同；所述第七开关晶体管的栅极与所述移位模块耦接，所述第七开关晶体管的第一极与所述第一电源端耦接，所述第七开关晶体管的第二极与所述第五开关晶体管的第二极耦接。
可选地，在本公开实施例中，还包括第八开关晶体管，所述第八开关晶体管的栅极与所述移位模块耦接，所述第八开关晶体管的第一极与所述第二电源端耦接，所述第八开关晶体管的第二极与所述驱动信号输出端耦接。
可选地，在本公开实施例中，所述第一开关晶体管、所述第三开关晶体管、所述第四开关晶体管、所述第五开关晶体管和所述第八开关晶体管均为P型晶体管，所述第二开关晶体管和所述第六开关晶体管均为N型晶体管。
可选地，在本公开实施例中，所述移位模块包括：
输入电路，分别与所述输入信号端、第一时钟信号端、所述第二电源端、第一节点和第二节点耦接；所述输入电路被配置为响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一节点和所述第二节点；
节点控制电路，分别与所述第一节点、所述第二节点、第三节点、第四节点、第五节点、所述第一电源端、所述第二电源端、所述第一时钟信号端和第二时钟信号端耦接；所述节点控制电路被配置为调节所述第一节点、所述第二节点、所述第三节点、所述第四节点和所述第五节点的信号，使所述级联信号输出端输出所述第一电源端的信号或所述第二电源端的信号；
复位电路，分别与所述第一电源端、复位信号端、所述第一节点、所述第四节点和所述第五节点耦接；所述复位电路被配置为响应于所述复位信号端的信号，对所述级联信号输出端输出的级联信号进行复位；
第一级联输出电路，分别与所述第四节点、所述第一电源端以及级联信号输出端耦接；所述第一级联输出电路被配置为响应于所述第四节点的信号，将所述第一电源端的信号提供给所述级联信号输出端；所述第七开关晶体管的栅极与所述第四节点耦接；
第二级联输出电路，分别与所述第五节点、所述第二电源端以及所述级联信号输出端耦接；所述第二级联输出电路被配置为响应于所述第五节点的信号，将所述第二电源端的信号提供给所述级联信号输出端；所述第八开关晶体管的栅极与所述第五节点耦接。
可选地，在本公开实施例中，所述输入电路包括：第九开关晶体管，第十开关晶体管和第十一开关晶体管；
所述第九开关晶体管的栅极与所述第一时钟信号端耦接，所述第九开关晶体管的第一极与所述输入信号端耦接，所述第九开关晶体管的第二极与所述第一节点耦接；
所述第十开关晶体管的栅极与所述第一时钟信号端耦接，所述第十开关晶体管的第一极与所述输入信号端耦接，所述第十开关晶体管的第二极与所述第十一开关晶体管的第一极耦接；
所述第十一开关晶体管的栅极与所述第二电源端耦接，所述第十一开关晶体管的第二极与所述第二节点耦接。
可选地，在本公开实施例中，所述节点控制电路包括：第十二开关晶体管，第十三开关晶体管，第十四开关晶体管，第十五开关晶体管，第十六开关晶体管，第十七开关晶体管，第十八开关晶体管，第十九开关晶体管，第二电容和第三电容；其中，
所述第十二开关晶体管的栅极与所述第一时钟信号端耦接，所述第十二开关晶体管的第一极与所述第二电源端耦接，所述第十二开关晶体管的第二极与所述第三节点耦接；
所述第十三开关晶体管的栅极与所述第一节点耦接，所述第十三开关晶体管的第一极与所述第一时钟信号端耦接，所述第十三开关晶体管的第二极 与所述第三节点耦接；
所述第十四开关晶体管的栅极和第一极均与所述第二节点耦接，所述第十四开关晶体管的第二极与所述第五节点耦接；
所述第十五开关晶体管的栅极与所述第二节点耦接，所述第十五开关晶体管的第一极与所述第二时钟信号端耦接，所述第十五开关晶体管的第二极与所述第十六开关晶体管的第一极耦接；
所述第十六开关晶体管的栅极与所述第三节点耦接，所述第十六开关晶体管的第二极与所述第一电源端耦接；
所述第二电容的第一端与所述第二节点耦接，所述第二电容的第二端与所述第十六开关晶体管的第一极耦接；
所述第十七开关晶体管的栅极与所述第二电源端耦接，所述第十七开关晶体管的第一极与所述第三节点耦接，所述第十七开关晶体管的第二极与所述第十八开关晶体管的栅极耦接；
所述第十八开关晶体管的第一极与所述第二时钟信号端耦接，所述第十八开关晶体管的第二极与所述第十九开关晶体管的第一极耦接；
所述第十九开关晶体管的栅极与所述第二时钟信号端耦接，所述第十九开关晶体管的第二极与所述第四节点耦接；
所述第三电容的第一端与所述第十八开关晶体管的栅极耦接，所述第三电容的第二端与所述第十八开关晶体管的第二极耦接。
可选地，在本公开实施例中，所述复位电路包括：第二十开关晶体管，第二十一开关晶体管和第二十二开关晶体管；其中，
所述第二十开关晶体管的栅极与所述复位信号端耦接，所述第二十开关晶体管的第一极与所述第一电源端耦接，所述第二十开关晶体管的第二极与所述第一节点以及所述第二十一开关晶体管的栅极耦接；
所述第二十一开关晶体管的第一极与所述第一电源端耦接，所述第二十一开关晶体管的第二极与所述第四节点耦接；
所述第二十二开关晶体管的栅极与所述第二电源端耦接，所述第二十二 开关晶体管的第一极与所述第一节点耦接，所述第二十二开关晶体管的第二极与所述第五节点耦接。
可选地，在本公开实施例中，所述第一级联输出电路包括：第二十三开关晶体管和第四电容；其中，
所述第二十三开关晶体管的栅极与所述第四节点耦接，所述第二十三开关晶体管的第一极与所述第一电源端耦接，所述第二十三开关晶体管的第二极与所述级联信号输出端耦接；
所述第四电容的第一端与所述第四节点耦接，所述第四电容的第二端与所述第一电源端耦接。
可选地，在本公开实施例中，所述第二级联输出电路包括第二十四开关晶体管，所述第二十四开关晶体管的栅极与所述第五节点耦接，所述第二十四开关晶体管的第一极与所述第二电源端耦接，所述第二十四开关晶体管的第二极与所述级联信号输出端耦接。
本公开实施例提供的栅极驱动电路，包括多个级联的上述移位寄存器；
第一级移位寄存器的输入信号端被配置为与帧触发信号端耦接；
每相邻两个所述移位寄存器中，后一级移位寄存器的输入信号端被配置为与前一级移位寄存器的级联信号输出端耦接。
本公开实施例提供的显示装置，包括上述栅极驱动电路。
本公开实施例提供的上述移位寄存器的驱动方法，包括：
第一刷新率阶段，所述锁存模块根据所述级联信号输出端与前一级所述反向信号输出端的信号，将所述掩蔽信号端的控制信号提供至所述选择输出模块；所述选择输出模块响应于所述掩蔽信号端的控制信号，将所述第一电源端的信号提供给所述驱动信号输出端；
第二刷新率阶段，所述锁存模块根据所述级联信号输出端与前一级所述反向信号输出端的信号，将所述掩蔽信号端的控制信号提供至所述选择输出模块；所述选择输出模块响应于所述掩蔽信号端的控制信号，将所述第二电源端的信号提供给所述驱动信号输出端。
附图说明
图1为本公开实施例提供的一种移位寄存器的结构示意图；
图2为本公开实施例提供的又一种移位寄存器的结构示意图；
图3为本公开实施例提供的又一种移位寄存器的结构示意图；
图4为本公开实施例提供的一种像素电路的结构示意图；
图5为对应图4所示的像素电路工作的信号时序图；
图6为本公开实施例提供的移位寄存器工作的信号时序图；
图7为对应图6所示的移位寄存器的驱动信号输出端的仿真模拟图；
图8为本公开实施例提供的驱动方法的流程图；
图9为本公开实施例提供的栅极驱动电路的结构示意图；
图10为本公开实施例提供的显示装置的结构示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是 示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
本公开实施例提供了一种移位寄存器，如图1和图2所示，可以包括：
移位模块1，分别与输入信号端IP和级联信号输出端GP(n)耦接；移位模块1被配置为响应于输入信号端IP的信号，使级联信号输出端GP(n)输出级联信号；
反向输出模块2，分别与级联信号输出端GP(n)、第一电源端VGH、第二电源端VGL以及反向信号输出端Anti-GP(n)耦接；反向输出模块2被配置为响应于级联信号输出端GP(n)的信号，使反向信号输出端Anti-GP(n)输出与级联信号输出端GP(n)相反的信号；
锁存模块3，分别与掩蔽信号端Vms、级联信号输出端GP(n)、前一级反向信号输出端Anti-GP(n-1)耦接；锁存模块3被配置为响应于级联信号输出端GP(n)以及前一级反向信号输出端Anti-GP(n-1)的信号，使锁存模块3的输出端输出掩蔽信号端Vms的信号；
选择输出模块4，分别与第一电源端VGH、第二电源端VGL、锁存模块3的输出端以及驱动信号输出端OP(n)耦接；选择输出模块4被配置为响应于锁存模块3的输出端的信号，将第一电源端VGH或第二电源端VGL的信号提供给驱动信号输出端OP(n)。
本公开实施例提供的上述移位寄存器，通过增设与移位模块耦接的反向输出模块、锁存模块和选择输出模块，通过这几个模块的相互配合，根据显示区域刷新率的要求，将相应的掩蔽信号端的控制信号锁存在选择输出模块内，可以实现对驱动信号输出端输出的信号的控制，实现在显示面板的不同区域可以实现不同的刷新率，即在同一帧画面内可实现高低刷新率共存，且本公开实施例不局限于在显示面板的固定区域实现不同刷新率，可以实现任意区域的动态刷新，从而可以降低显示面板功耗；同时，锁存模块可以利用移位模块前后级输出的级联信号的相位差，将掩蔽信号端的控制信号的存入每一级移位寄存器，从而实现该级移位寄存器持续正确输出；并且，只需一 根与掩蔽信号端电连接的控制线就可控制整屏自适应刷新率，不仅降低LayOP布线难度，减少边框的宽度，还可以进一步降低为实现多频驱动采用的多条控制线导致需要额外增加驱动芯片的控制功耗。
下面对本公开实施例提供的移位模块1的具体结构进行说明：
在一种可能的实现方式中，在本公开实施例提供的上述移位寄存器中，如图1和图2所示，移位模块1可以包括：
输入电路11，分别与输入信号端IP、第一时钟信号端CK、第二电源端VGL、第一节点P1和第二节点P2耦接；输入电路11被配置为响应于第一时钟信号端CK的信号，将输入信号端IP的信号提供给第一节点P1和第二节点P2；例如，输入电路11可以包括：第九开关晶体管T9，第十开关晶体管T10和第十一开关晶体管T11；第九开关晶体管T9的栅极与第一时钟信号端CK耦接，第九开关晶体管T9的第一极与输入信号端IP耦接，第九开关晶体管T9的第二极与第一节点P1耦接；第十开关晶体管T10的栅极与第一时钟信号端CK耦接，第十开关晶体管T10的第一极与输入信号端IP耦接，第十开关晶体管T10的第二极与第十一开关晶体管T11的第一极耦接；第十一开关晶体管T11的栅极与第二电源端VGL耦接，第十一开关晶体管T11的第二极与第二节点P2耦接；
节点控制电路12，分别与第一节点P1、第二节点P2、第三节点P3、第四节点P4、第五节点P5、第一电源端VGH、第二电源端VGL、第一时钟信号端CK和第二时钟信号端CB耦接；节点控制电路12被配置为调节第一节点P1、第二节点P2、第三节点P3、第四节点P4和第五节点P5的信号，使级联信号输出端GP(n)输出第一电源端VGH的信号或第二电源端VGL的信号；例如，节点控制电路12可以包括：第十二开关晶体管T12，第十三开关晶体管T13，第十四开关晶体管T14，第十五开关晶体管T15，第十六开关晶体管T16，第十七开关晶体管T17，第十八开关晶体管T18，第十九开关晶体管T19，第二电容C2和第三电容C3；其中，
第十二开关晶体管T12的栅极与第一时钟信号端CK耦接，第十二开关 晶体管T12的第一极与第二电源端VGL耦接，第十二开关晶体管T12的第二极与第三节点P3耦接；
第十三开关晶体管T13的栅极与第一节点P1耦接，第十三开关晶体管T13的第一极与第一时钟信号端CK耦接，第十三开关晶体管T13的第二极与第三节点P3耦接；
第十四开关晶体管T14的栅极和第一极均与第二节点P2耦接，第十四开关晶体管T14的第二极与第五节点P5耦接；
第十五开关晶体管T15的栅极与第二节点P2耦接，第十五开关晶体管T15的第一极与第二时钟信号端CB耦接，第十五开关晶体管T15的第二极与第十六开关晶体管T16的第一极耦接；
第十六开关晶体管T16的栅极与第三节点P3耦接，第十六开关晶体管T16的第二极与第一电源端VGH耦接；
第二电容C2的第一端与第二节点P2耦接，第二电容C2的第二端与第十六开关晶体管T16的第一极耦接；
第十七开关晶体管T17的栅极与第二电源端VGL耦接，第十七开关晶体管T17的第一极与第三节点P3耦接，第十七开关晶体管T17的第二极与第十八开关晶体管T18的栅极耦接；
第十八开关晶体管T18的第一极与第二时钟信号端CB耦接，第十八开关晶体管T18的第二极与第十九开关晶体管T19的第一极耦接；
第十九开关晶体管T19的栅极与第二时钟信号端CB耦接，第十九开关晶体管T19的第二极与第四节点P4耦接；
第三电容C3的第一端与第十八开关晶体管T18的栅极耦接，第三电容C3的第二端与第十八开关晶体管T18的第二极耦接；
复位电路13，分别与第一电源端VGH、复位信号端VEL、第一节点P1、第四节点P4和第五节点P5耦接；复位电路13被配置为响应于复位信号端VEL的信号，对级联信号输出端GP(n)输出的级联信号进行复位；具体地，复位电路13被配置为响应于复位信号端VEL的信号，对第四节点P4和第五节 点P5的电压进行复位，进而可以对级联信号输出端GP(n)输出的级联信号进行复位；例如，复位电路13可以包括：第二十开关晶体管T20，第二十一开关晶体管T21和第二十二开关晶体管T22；其中，
第二十开关晶体管T20的栅极与复位信号端VEL耦接，第二十开关晶体管T20的第一极与第一电源端VGH耦接，第二十开关晶体管T20的第二极与第一节点P1以及第二十一开关晶体管T21的栅极耦接；
第二十一开关晶体管T21的第一极与第一电源端VGH耦接，第二十一开关晶体管T21的第二极与第四节点P4耦接；
第二十二开关晶体管T22的栅极与第二电源端VGL耦接，第二十二开关晶体管T22的第一极与第一节点P1耦接，第二十二开关晶体管T22的第二极与第五节点P5耦接；
第一级联输出电路14，分别与第四节点P4、第一电源端VGH以及级联信号输出端GP(n)耦接；第一级联输出电路14被配置为响应于第四节点P4的信号，将第一电源端VGH的信号提供给级联信号输出端GP(n)；例如，第一级联输出电路14可以包括：第二十三开关晶体管T23和第四电容C4；其中，
第二十三开关晶体管T23的栅极与第四节点P4耦接，第二十三开关晶体管T23的第一极与第一电源端VGH耦接，第二十三开关晶体管T23的第二极与级联信号输出端GP(n)耦接；
第四电容C4的第一端与第四节点P4耦接，第四电容C4的第二端与第一电源端VGH耦接。
第二级联输出电路15，分别与第五节点P5、第二电源端VGL以及级联信号输出端GP(n)耦接；第二级联输出电路15被配置为响应于第五节点P5的信号，将第二电源端VGL的信号提供给级联信号输出端GP(n)；例如，第二级联输出电路15可以包括第二十四开关晶体管T24，第二十四开关晶体管T24的栅极与第五节点P5耦接，第二十四开关晶体管T24的第一极与第二电源端VGL耦接，第二十四开关晶体管T24的第二极与级联信号输出端GP(n)耦接。
为了简化制备工艺，在具体实施时，在本公开实施例中，如图1和图2 所示，可以使移位模块1的所有开关晶体管均为P型晶体管。
以上仅是举例说明本公开实施例提供的移位寄存器中移位模块的具体结构，在具体实施时，上述各电路的具体结构不限于本公开实施例提供的上述结构，还可以是本领域技术人员可知的其他结构，在此不作限定。
需要说明的是，本公开实施例提供的上述图1和图2所示的移位模块1的工作原理与相关技术中相同，主要通过级联信号输出端GP(n)产生级联信号以实现信号的移位功能，在此不做详述。
需要说明的是，本公开实施例提供的移位模块1的主要作用是时序从上到下移位功能的实现，本公开实施例选择采用更稳定传递信号的16T3C的移位模块1，当然移位模块1可以不仅限于本公开实施例提供的16T3C结构，可以是其它可以实现移位功能的多种移位寄存器，例如OLED显示面板中常用的10T3C、12T3C、13T3C等等。可选地，如图3所示，图3为本公开实施例提供的另一种移位模块1的结构示意图，该移位模块1与图1和图2中的移位模块1的功能相同，在此不做详述。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图1-图3所示，反向输出模块2可以包括：第一开关晶体管T1和第二开关晶体管T2；第一开关晶体管T1和第二开关晶体管T2的类型不同，例如第一开关晶体管T1为P型晶体管，第二开关晶体管T2为N型晶体管；其中，
第一开关晶体管T1的栅极与级联信号输出端GP(n)耦接，第一开关晶体管T1的第一极与第一电源端VGH耦接，第一开关晶体管T1的第二极与反向信号输出端Anti-GP(n)耦接；
第二开关晶体管T2的栅极与级联信号输出端GP(n)耦接，第二开关晶体管T2的第一极与第二电源端VGL耦接，第二开关晶体管T2的第二极与反向信号输出端Anti-GP(n)耦接。
具体地，如图1-图3所示，反向输出模块2利用N型晶体管和P型晶体管的电路结构，构建GP(n-1)的反向信号，从而实现锁存模块利用移位模块前后级输出的级联信号的相位差，提前写入需要的掩蔽信号端的控制信号，达 到一个控制信号可以控制多个有效电平信号(高电平)的输出。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图1-图3所示，锁存模块3可以包括：第三开关晶体管T3和第四开关晶体管T4；其中，
第三开关晶体管T3的栅极与级联信号输出端GP(n)耦接，第三开关晶体管T3的第一极与掩蔽信号端Vms耦接，第三开关晶体管T3的第二极与第四开关晶体管T4的第一极耦接；
第四开关晶体管T4的栅极与前一级反向信号输出端Anti-GP(n-1)耦接，第四开关晶体管T4的第二极为锁存模块3的输出端。
可选地，锁存模块3可以包括：第三开关晶体管T3和第四开关晶体管T4；其中，
第四开关晶体管T4的栅极与级联信号输出端GP(n)耦接，第四开关晶体管T4的第一极与掩蔽信号端Vms耦接，第四开关晶体管T4的第二极与第三开关晶体管T3的第一极耦接；
第三开关晶体管T3的栅极与前一级反向信号输出端Anti-GP(n-1)耦接，第三开关晶体管T3的第二极为锁存模块3的输出端。
具体地，如图1-图3所示，锁存模块3利用前一级反向信号输出端Anti-GP(n-1)的信号和级联信号输出端GP(n)的信号的相位差，实现掩蔽信号端Vms的控制信号提前写入并存储在选择输出模块4内，从而实现第一电源端VGH的信号可以与GP(n)信号保持一致，实现多个有效电平信号(高电平)的长时间输出。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图1-图3所示，选择输出模块4可以包括：第五开关晶体管T5、第六开关晶体管T6和第一电容C1；第五开关晶体管T5和第六开关晶体管T6的类型不同，例如第五开关晶体管T5为P型晶体管，第六开关晶体管T6为N型晶体管；其中，
第五开关晶体管T5的栅极与第四开关晶体管T4的第二极耦接，第五开关晶体管T5的第一极与驱动信号输出端OP(n)耦接；
第六开关晶体管T6的栅极与第四开关晶体管T4的第二极耦接，第六开关晶体管T6的第一极与第二电源端VGL耦接，第六开关晶体管T6的第二极与驱动信号输出端OP(n)耦接；
第一电容C1的第一端与第一电源端VGH耦接，第一电容C1的第二端与第四开关晶体管T4的第二极耦接。
具体地，选择输出模块4通过存储掩蔽信号端Vms写入的高电平信号或低电平信号，实现将驱动信号输出端OP(n)输出的高电平信号变成低电平信号，或者维持正常输出的高电平信号，以实现显示区域内不同刷新率的需求。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图1和图3所示，选择输出模块4还可以包括：第七开关晶体管T7；第七开关晶体管T7的类型与第五开关晶体管T5的类型相同，例如第七开关晶体管T7为P型晶体管；第七开关晶体管T7的栅极与移位模块1(第四节点P4)耦接，第七开关晶体管T7的第一极与第一电源端VGH耦接，第七开关晶体管T7的第二极与第五开关晶体管T5的第二极耦接。
具体地，如图1和图3所示，在第四节点P4的信号为低电平信号时，可以根据显示刷新率的需求，控制掩蔽信号端Vms的控制信号为高电平或低电平，使得驱动信号输出端OP(n)输出低电平或高电平，实现在显示面板的不同区域可以实现不同的刷新率。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图2所示，第五开关晶体管T5的第二极可以直接与级联信号输出端GP(n)耦接。具体地，图2所示的选择输出模块4的结构较图1所示的选择输出模块4的结构减少了一个与第二十三开关晶体管T23共栅的第七开关晶体管T7，因为第五开关晶体管T5可以锁死级联信号输出端GP(n)的电压，可以将级联信号输出端GP(n)输出的高电平信号直接输出至驱动信号输出端OP(n)，可以减少一个第七开关晶体管T7(Buffer管)，节省LayOP布线空间。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图1-图3所示，还包括第八开关晶体管T8，第八开关晶体管T8的栅极与移位模块(第 五节点P5)耦接，第八开关晶体管T8的第一极与第二电源端VGL耦接，第八开关晶体管T8的第二极与驱动信号输出端OP(n)耦接。
具体地，第八开关晶体管T8的主要作用是将输出至驱动信号输出端OP(n)的第二电源端VGL的信号和递传的级联信号输出端GP(n)正常的级联信号区分开来，避免因掩蔽信号端Vms写入控制信号时，驱动信号输出端OP(n)的信号和级联信号输出端GP(n)的信号差异而造成的信号紊乱，实现移位寄存器的正常移位功能。
在具体实施时，在本公开实施例提供的上述移位寄存器中，如图1-图3所示，第一开关晶体管T1、第三开关晶体管T3、第四开关晶体管T4、第五开关晶体管T5和第八开关晶体管T8均为P型晶体管，第二开关晶体管T2和第六开关晶体管T6均为N型晶体管。
进一步的，在具体实施时，P型晶体管在高电平信号作用下截止，在低电平信号作用下导通。N型晶体管在高电平信号作用下导通，在低电平信号作用下截止。
在具体实施时，如图1-图3所示，掩蔽信号端Vms的控制信号为低电平信号时，可以为-20V～-5V，为高电平信号时，可以为5V～20V。
在具体实施时，如图1-图3所示，第一电源端VGH的信号为高电平信号，例如可以为5V～10V；第二电源端VGL的信号为低电平信号，例如可以为-10V～-5V。
在具体实施时，如图1-图3所示，第一时钟信号端CK的信号和第二时钟信号端CB的信号为周期相同、电位相反的交流信号。
在具体实施时，根据信号的流通方向，上述各开关晶体管的第一极可以作为其源极，第二极可以作为其漏极；或者，第一极作为其漏极，第二极作为其源极，在此不作具体区分。
需要说明的是，本公开上述实施例中提到的开关晶体管可以是TFT，也可以是金属氧化物半导体场效应管(Metal Oxide Semiconductor，MOS)，在此不作限定。
可选地，本公开实施例提供的上述移位寄存器可以用于向有机发光显示面板提供驱动信号，有机发光显示面板的显示区域包括多个子像素，每个子像素一般设置有多个有机发光二极管以及与各有机发光二极管连接的像素电路。像素电路可以为6T1C、7T1C等结构，如图4所示，图4为本公开实施例提供的一种7T1C的像素电路结构，图1-图3所示的移位寄存器的驱动信号输出端OP(n)输出的驱动信号主要用于控制显示面板中一行像素电路中的氧化物开关晶体管(用于向图4中的第一扫描晶体管M2的栅极提供扫描信号)，当需要刷新的一帧中，驱动信号输出端OP(n)在一段时间内输出高电平，一帧时间内的其余时间段输出低电平，控制第一扫描晶体管M2导通，实现数据电压的刷新；当在不刷新帧中，驱动信号输出端OP(n)则一直输出低电平，第一扫描晶体管M2无法导通，从而实现数据电压的不刷新。
本公开实施例提供的像素电路不限于图4所示的结构，只要需要初始化晶体管M1和扫描晶体管M2同时导通给N1节点提供初始化信号的像素电路均属于本公开实施例保护的像素电路结构。
先结合图5所示的信号时序图对图4所示的像素电路的工作过程进行说明。具体地，选取如图5所示的信号时序图中一帧时间段的第一初始化阶段T1’、数据写入阶段T2’、第二初始化阶段T3’以及发光阶段T4’四个阶段。
在第一初始化阶段T1’：第一控制端PSR1输入低电平信号，第一初始化晶体管M1导通，第一初始化信号端Vint1向N3节点提供初始化信号，对N3节点进行初始化。
在数据写入阶段T2’，第一扫描控制端P_Scan输入低电平信号，第二扫描控制端N_Scan输入高电平信号，第一扫描晶体管M2和第二扫描晶体管M4均导通，驱动晶体管M3维持上一帧发光阶段的导通状态，因此数据信号端D的数据电压写入N1节点。
在第二初始化阶段T3’，第二控制端PSR2输入低电平信号，第二初始化晶体管M7导通，第二初始化信号端Vint2向OLED的阳极提供初始化信号，对阳极进行初始化。
在发光阶段T4’，发光控制端EM输入低电平信号，第一发光控制晶体管M5和M6均导通，第一电源端VDD的信号经过驱动晶体管M3产生电流，驱动OLED发光。
例如上述像素电路的工作时序为第一帧，若在第二帧需要维持第一帧的刷新率(即第二帧无需刷新)，则在数据写入阶段T2’需要控制第一扫描晶体管M2截止，这样就需要本公开实施例提供的移位寄存器的驱动信号输出端OP(n)输入低电平信号，即图5中的第二扫描控制端N_Scan原本输入高电平信号(虚线A)需要变为低电平信号，从而实现第二帧为第一帧的刷新率保持帧。然而本公开实施例提供得图1-图3所示的移位寄存器能够实现在显示面板的不同区域实现不同的刷新率。
下面以图1所示的移位寄存器为例，结合图6所示的信号时序图对本公开实施例提供的上述移位寄存器能够实现控制显示面板在不同区域实现不同刷新率的工作原理作以描述。
具体地，图6所示的信号时序图仅以前四级移位寄存器的输入(IP)、输出(OP(1)、OP(2)、OP(3)、OP(4))为例。例如在显示面板内的第二行像素和第三行像素对应的区域为低刷新率区域，第一行像素和第四行像素为高刷新率区域时，在第一级移位寄存器的级联信号输出端GP(1)的信号和前一级反向信号输出端Anti-GP(0)的信号均为低电平信号时(t1时刻)，第三开关晶体管T3和第四开关晶体管T4均导通，即在t1时刻将掩蔽信号端Vms的低电平信号锁存在选择输出模块4的第一电容C1内，在第一级级联信号输出端GP(1)输出高电平时(T1”时刻)，则第四节点P4的信号为低电平信号，第五节点P5的信号为高电平信号，则第七开关晶体管T7导通，由于第一电容C1维持t1时刻的掩蔽信号端Vms的低电平信号，则第五开关晶体管T5导通，第六开关晶体管T6截止，则在T1”时刻，第一级移位寄存器的驱动信号输出端OP(1)输出第一电源端VGH的高电平信号，实现显示区域内第一行像素的高刷新率；当然，第一级移位寄存器的驱动信号输出端OP(1)输出第一电源端VGH的高电平信号的维持时间可以根据需要进行设定。例如：第一级移位寄 存器的驱动信号输出端OP(1)输出第一电源端VGH的高电平信号的维持时间与第四级移位寄存器的驱动信号输出端OP(4)输出第一电源端VGH的高电平信号存在交叠，可以对第四级移位寄存器的驱动信号输出端OP(4)对应的像素电路进行预充。类似的，其他级移位寄存器的驱动信号输出端OP(n)输出电平信号的维持时间类似，不再赘述。
在第二级移位寄存器的级联信号输出端GP(2)的信号和前一级反向信号输出端Anti-GP(1)的信号均为低电平信号时(t2时刻)，第三开关晶体管T3和第四开关晶体管T4均导通，即在t2时刻将掩蔽信号端Vms的高电平信号锁存在选择输出模块4的第一电容C1内；在第二级级联信号输出端GP(2)输出高电平时(T2”时刻)，则第四节点P4的信号为低电平信号，第五节点P5的信号为高电平信号，则第七开关晶体管T7导通，由于第一电容C1维持t1时刻的掩蔽信号端Vms的高电平信号，则第五开关晶体管T5截止，第六开关晶体管T6导通，则在T2”时刻，第二级移位寄存器的驱动信号输出端OP(2)输出第二电源端VGL的低电平信号，实现显示区域内第二行像素的低刷新率；
在第三级移位寄存器的级联信号输出端GP(3)的信号和前一级反向信号输出端Anti-GP(2)的信号均为低电平信号时(t3时刻)，第三开关晶体管T3和第四开关晶体管T4均导通，即在T3时刻将掩蔽信号端Vms的高电平信号锁存在选择输出模块4的第一电容C1内；在第三级级联信号输出端GP(3)输出高电平时(T3”时刻)，则第四节点P4的信号为低电平信号，第五节点P5的信号为高电平信号，则第七开关晶体管T7导通，由于第一电容C1维持t1时刻的掩蔽信号端Vms的高电平信号，则第五开关晶体管T5截止，第六开关晶体管T6导通，则在T3”时刻，第三级移位寄存器的驱动信号输出端OP(3)输出第二电源端VGL的低电平信号，实现显示区域内第三行像素的低刷新率；
在第四级移位寄存器的级联信号输出端GP(4)的信号和前一级反向信号输出端Anti-GP(3)的信号均为低电平信号时(t4时刻)，第三开关晶体管T3和第四开关晶体管T4均导通，即在t4时刻将掩蔽信号端Vms的低电平信号锁存在选择输出模块4的第一电容C1内，在第四级级联信号输出端GP(4)输 出高电平时(T4”时刻)，则第四节点P4的信号为低电平信号，第五节点P5的信号为高电平信号，则第七开关晶体管T7导通，由于第一电容C1维持t1时刻的掩蔽信号端Vms的低电平信号，则第五开关晶体管T5导通，第六开关晶体管T6截止，则在T4”时刻，第四级移位寄存器的驱动信号输出端OP(4)输出第一电源端VGH的高电平信号，实现显示区域内第四行像素的高刷新率。
因此，在显示面板的某一区域需要低刷新率时，通过掩蔽信号端Vms给入高电平信号，驱动信号输出端一直输出低电平，对应显示面板内像素电路的氧化物开关晶体管(图3中的M2)截止，则显示面板内的数据电压不进行充电，则维持上一帧的状态，从而实现该区域的低刷新率。
可选地，可以根据掩蔽信号端Vms给入高电平信号的时长(例如2-3行像素电路的工作时间)，以及结合级联信号输出端与前一级反向信号输出端的信号，实现同一帧不同行的像素电路的氧化物开关晶体管选择开启或截止，进而实现显示面板不同行的刷新率。
并且，还根据图6所示的信号时序图，对图1所示的移位寄存器的驱动信号输出端OP(n)输出的信号进行仿真模拟，仿真模拟图如图7所示。其中，横坐标代表时间，纵坐标代表电压。可以看出，本公开实施例可以实现对驱动信号输出端OP(n)输出的信号的控制，实现在显示面板的不同区域可以实现不同的刷新率，即在同一帧画面内可实现高低刷新率共存，且本公开实施例不局限于在显示面板的固定区域实现不同刷新率，可以实现任意区域的动态刷新，从而可以降低显示面板功耗。
需要说明的是，本公开实施例仅是以显示面板内第二行像素和第三行像素对应的区域为低刷新率区域为例进行说明移位寄存器的工作过程，当然，可以对显示面板内的任意区域实现低刷新率。
需要说明的是，在实际应用中，上述各信号的具体电压值可以根据实际应用环境来设计确定，在此不作限定。
基于同一发明构思，本公开实施例还提供了上述移位寄存器的驱动方法，其中，如图8所示，可以包括：
S801、第一刷新率阶段，锁存模块根据级联信号输出端与前一级反向信号输出端的信号，将掩蔽信号端的控制信号提供至选择输出模块；选择输出模块响应于掩蔽信号端的控制信号，将第一电源端的信号提供给驱动信号输出端；例如，第一刷新率阶段，锁存模块根据本级的级联信号输出端与前一级反向信号输出端的信号，将掩蔽信号端的低电平控制信号提供至选择输出模块；选择输出模块响应于掩蔽信号端的低电平控制信号，将第一电源端的高电平信号提供给驱动信号输出端。
S802、第二刷新率阶段，锁存模块根据级联信号输出端与前一级反向信号输出端的信号，将掩蔽信号端的控制信号提供至选择输出模块；选择输出模块响应于掩蔽信号端的控制信号，将第二电源端的信号提供给驱动信号输出端。
例如，第二刷新率阶段，锁存模块根据本级的级联信号输出端与前一级反向信号输出端的信号，将掩蔽信号端的高电平控制信号提供至选择输出模块；选择输出模块响应于掩蔽信号端的高电平控制信号，将第一电源端的低电平信号提供给驱动信号输出端。
具体地，第一刷新率阶段对应前述一种移位寄存器中的高刷新率阶段，第二刷新率阶段对应前述一种移位寄存器中的低刷新率阶段。
其中，该驱动方法的驱动原理和具体实施方式与上述实施例移位寄存器的原理和实施方式相同，因此，该驱动方法可参见上述实施例中移位寄存器的具体实施方式进行实施，在此不再赘述。
基于同一发明构思，本公开实施例还提供了一种栅极驱动电路，如图9所示，包括级联的多个本公开实施例提供的上述移位寄存器SR(1)、SR(2)…SR(n-1)、SR(n)…SR(N-1)、SR(N)(共N个移位寄存器，1≤n≤N，n为整数)；其中，第一级移位寄存器SR(1)的输入信号端IP被配置为与帧触发信号端STV耦接；
每相邻两个移位寄存器中，后一级移位寄存器SR(n)的输入信号端IP被配置为与前一级移位寄存器SR(n-1)的级联信号输出端GP(n)耦接。
具体地，上述栅极驱动电路中的每个移位寄存器的具体结构与本公开上述移位寄存器在功能和结构上均相同，重复之处不再赘述。该栅极驱动电路可以应被配置为液晶显示面板中，也可以应被配置为电致发光显示面板中，在此不作限定。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述栅极驱动电路。该显示装置解决问题的原理与前述移位寄存器相似，因此该显示装置的实施可以参见前述移位寄存器的实施，重复之处在此不再赘述。
在具体实施时，本公开实施例提供的上述显示装置可以为如图10所示的手机。当然，本公开实施例提供的上述显示装置也可以为平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。对于该显示装置的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的，在此不做赘述，也不应作为对本公开的限制。
在具体实施时，本公开实施例提供的上述显示装置可以为液晶显示装置或有机发光显示装置。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (17)

  1. 一种移位寄存器，其中，包括：
    移位模块，分别与输入信号端和级联信号输出端耦接；所述移位模块被配置为响应于所述输入信号端的信号，使所述级联信号输出端输出级联信号；
    反向输出模块，分别与所述级联信号输出端、第一电源端、第二电源端以及反向信号输出端耦接；所述反向输出模块被配置为响应于所述级联信号输出端的信号，使所述反向信号输出端输出与所述级联信号输出端相反的信号；
    锁存模块，分别与掩蔽信号端、所述级联信号输出端、前一级所述反向信号输出端耦接；所述锁存模块被配置为响应于所述级联信号输出端以及前一级所述反向信号输出端的信号，使所述锁存模块的输出端输出所述掩蔽信号端的控制信号；
    选择输出模块，分别与所述第一电源端、所述第二电源端、所述锁存模块的输出端以及驱动信号输出端耦接；所述选择输出模块被配置为响应于所述锁存模块的输出端的信号，将所述第一电源端或所述第二电源端的信号提供给所述驱动信号输出端。
  2. 根据权利要求1所述的移位寄存器，其中，所述反向输出模块包括：第一开关晶体管和第二开关晶体管；所述第一开关晶体管和所述第二开关晶体管的类型不同；其中，
    所述第一开关晶体管的栅极与所述级联信号输出端耦接，所述第一开关晶体管的第一极与所述第一电源端耦接，所述第一开关晶体管的第二极与所述反向信号输出端耦接；
    所述第二开关晶体管的栅极与所述级联信号输出端耦接，所述第二开关晶体管的第一极与所述第二电源端耦接，所述第二开关晶体管的第二极与所述反向信号输出端耦接。
  3. 根据权利要求2所述的移位寄存器，其中，所述锁存模块包括：第三 开关晶体管和第四开关晶体管；其中，
    所述第三开关晶体管的栅极与所述级联信号输出端耦接，所述第三开关晶体管的第一极与所述掩蔽信号端耦接，所述第三开关晶体管的第二极与所述第四开关晶体管的第一极耦接；
    所述第四开关晶体管的栅极与前一级所述反向信号输出端耦接，所述第四开关晶体管的第二极为所述锁存模块的输出端。
  4. 根据权利要求3所述的移位寄存器，其中，所述选择输出模块包括：第五开关晶体管、第六开关晶体管和第一电容；所述第五开关晶体管和所述第六开关晶体管的类型不同；其中，
    所述第五开关晶体管的栅极与所述第四开关晶体管的第二极耦接，所述第五开关晶体管的第一极与所述驱动信号输出端耦接；
    所述第六开关晶体管的栅极与所述第四开关晶体管的第二极耦接，所述第六开关晶体管的第一极与所述第二电源端耦接，所述第六开关晶体管的第二极与所述驱动信号输出端耦接；
    所述第一电容的第一端与所述第一电源端耦接，所述第一电容的第二端与所述第四开关晶体管的第二极耦接。
  5. 根据权利要求4所述的移位寄存器，其中，所述第五开关晶体管的第二极与所述级联信号输出端耦接。
  6. 根据权利要求4所述的移位寄存器，其中，所述选择输出模块还包括：第七开关晶体管；所述第七开关晶体管的类型与所述第五开关晶体管的类型相同；所述第七开关晶体管的栅极与所述移位模块耦接，所述第七开关晶体管的第一极与所述第一电源端耦接，所述第七开关晶体管的第二极与所述第五开关晶体管的第二极耦接。
  7. 根据权利要求5或6所述的移位寄存器，其中，还包括第八开关晶体管，所述第八开关晶体管的栅极与所述移位模块耦接，所述第八开关晶体管的第一极与所述第二电源端耦接，所述第八开关晶体管的第二极与所述驱动信号输出端耦接。
  8. 根据权利要求7所述的移位寄存器，其中，所述第一开关晶体管、所述第三开关晶体管、所述第四开关晶体管、所述第五开关晶体管和所述第八开关晶体管均为P型晶体管，所述第二开关晶体管和所述第六开关晶体管均为N型晶体管。
  9. 根据权利要求7所述的移位寄存器，其中，所述移位模块包括：
    输入电路，分别与所述输入信号端、第一时钟信号端、所述第二电源端、第一节点和第二节点耦接；所述输入电路被配置为响应于所述第一时钟信号端的信号，将所述输入信号端的信号提供给所述第一节点和所述第二节点；
    节点控制电路，分别与所述第一节点、所述第二节点、第三节点、第四节点、第五节点、所述第一电源端、所述第二电源端、所述第一时钟信号端和第二时钟信号端耦接；所述节点控制电路被配置为调节所述第一节点、所述第二节点、所述第三节点、所述第四节点和所述第五节点的信号，使所述级联信号输出端输出所述第一电源端的信号或所述第二电源端的信号；
    复位电路，分别与所述第一电源端、复位信号端、所述第一节点、所述第四节点和所述第五节点耦接；所述复位电路被配置为响应于所述复位信号端的信号，对所述级联信号输出端输出的级联信号进行复位；
    第一级联输出电路，分别与所述第四节点、所述第一电源端以及级联信号输出端耦接；所述第一级联输出电路被配置为响应于所述第四节点的信号，将所述第一电源端的信号提供给所述级联信号输出端；所述第七开关晶体管的栅极与所述第四节点耦接；
    第二级联输出电路，分别与所述第五节点、所述第二电源端以及所述级联信号输出端耦接；所述第二级联输出电路被配置为响应于所述第五节点的信号，将所述第二电源端的信号提供给所述级联信号输出端；所述第八开关晶体管的栅极与所述第五节点耦接。
  10. 根据权利要求9所述的移位寄存器，其中，所述输入电路包括：第九开关晶体管，第十开关晶体管和第十一开关晶体管；
    所述第九开关晶体管的栅极与所述第一时钟信号端耦接，所述第九开关 晶体管的第一极与所述输入信号端耦接，所述第九开关晶体管的第二极与所述第一节点耦接；
    所述第十开关晶体管的栅极与所述第一时钟信号端耦接，所述第十开关晶体管的第一极与所述输入信号端耦接，所述第十开关晶体管的第二极与所述第十一开关晶体管的第一极耦接；
    所述第十一开关晶体管的栅极与所述第二电源端耦接，所述第十一开关晶体管的第二极与所述第二节点耦接。
  11. 根据权利要求9所述的移位寄存器，其中，所述节点控制电路包括：第十二开关晶体管，第十三开关晶体管，第十四开关晶体管，第十五开关晶体管，第十六开关晶体管，第十七开关晶体管，第十八开关晶体管，第十九开关晶体管，第二电容和第三电容；其中，
    所述第十二开关晶体管的栅极与所述第一时钟信号端耦接，所述第十二开关晶体管的第一极与所述第二电源端耦接，所述第十二开关晶体管的第二极与所述第三节点耦接；
    所述第十三开关晶体管的栅极与所述第一节点耦接，所述第十三开关晶体管的第一极与所述第一时钟信号端耦接，所述第十三开关晶体管的第二极与所述第三节点耦接；
    所述第十四开关晶体管的栅极和第一极均与所述第二节点耦接，所述第十四开关晶体管的第二极与所述第五节点耦接；
    所述第十五开关晶体管的栅极与所述第二节点耦接，所述第十五开关晶体管的第一极与所述第二时钟信号端耦接，所述第十五开关晶体管的第二极与所述第十六开关晶体管的第一极耦接；
    所述第十六开关晶体管的栅极与所述第三节点耦接，所述第十六开关晶体管的第二极与所述第一电源端耦接；
    所述第二电容的第一端与所述第二节点耦接，所述第二电容的第二端与所述第十六开关晶体管的第一极耦接；
    所述第十七开关晶体管的栅极与所述第二电源端耦接，所述第十七开关 晶体管的第一极与所述第三节点耦接，所述第十七开关晶体管的第二极与所述第十八开关晶体管的栅极耦接；
    所述第十八开关晶体管的第一极与所述第二时钟信号端耦接，所述第十八开关晶体管的第二极与所述第十九开关晶体管的第一极耦接；
    所述第十九开关晶体管的栅极与所述第二时钟信号端耦接，所述第十九开关晶体管的第二极与所述第四节点耦接；
    所述第三电容的第一端与所述第十八开关晶体管的栅极耦接，所述第三电容的第二端与所述第十八开关晶体管的第二极耦接。
  12. 根据权利要求9所述的移位寄存器，其中，所述复位电路包括：第二十开关晶体管，第二十一开关晶体管和第二十二开关晶体管；其中，
    所述第二十开关晶体管的栅极与所述复位信号端耦接，所述第二十开关晶体管的第一极与所述第一电源端耦接，所述第二十开关晶体管的第二极与所述第一节点以及所述第二十一开关晶体管的栅极耦接；
    所述第二十一开关晶体管的第一极与所述第一电源端耦接，所述第二十一开关晶体管的第二极与所述第四节点耦接；
    所述第二十二开关晶体管的栅极与所述第二电源端耦接，所述第二十二开关晶体管的第一极与所述第一节点耦接，所述第二十二开关晶体管的第二极与所述第五节点耦接。
  13. 根据权利要求9所述的移位寄存器，其中，所述第一级联输出电路包括：第二十三开关晶体管和第四电容；其中，
    所述第二十三开关晶体管的栅极与所述第四节点耦接，所述第二十三开关晶体管的第一极与所述第一电源端耦接，所述第二十三开关晶体管的第二极与所述级联信号输出端耦接；
    所述第四电容的第一端与所述第四节点耦接，所述第四电容的第二端与所述第一电源端耦接。
  14. 根据权利要求9所述的移位寄存器，其中，所述第二级联输出电路包括第二十四开关晶体管，所述第二十四开关晶体管的栅极与所述第五节点 耦接，所述第二十四开关晶体管的第一极与所述第二电源端耦接，所述第二十四开关晶体管的第二极与所述级联信号输出端耦接。
  15. 一种栅极驱动电路，其中，包括多个级联的如权利要求1-14任一项所述的移位寄存器；
    第一级移位寄存器的输入信号端被配置为与帧触发信号端耦接；
    每相邻两个所述移位寄存器中，后一级移位寄存器的输入信号端被配置为与前一级移位寄存器的级联信号输出端耦接。
  16. 一种显示装置，其中，包括如权利要求15所述的栅极驱动电路。
  17. 一种如权利要求1-14任一项所述的移位寄存器的驱动方法，其中，包括：
    第一刷新率阶段，所述锁存模块根据所述级联信号输出端与前一级所述反向信号输出端的信号，将所述掩蔽信号端的控制信号提供至所述选择输出模块；所述选择输出模块响应于所述掩蔽信号端的控制信号，将所述第一电源端的信号提供给所述驱动信号输出端；
    第二刷新率阶段，所述锁存模块根据所述级联信号输出端与前一级所述反向信号输出端的信号，将所述掩蔽信号端的控制信号提供至所述选择输出模块；所述选择输出模块响应于所述掩蔽信号端的控制信号，将所述第二电源端的信号提供给所述驱动信号输出端。
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CN111276177A (zh) * 2020-02-21 2020-06-12 京东方科技集团股份有限公司 移位寄存器及其驱动方法、栅极驱动电路、显示装置
WO2021227766A1 (zh) * 2020-05-09 2021-11-18 京东方科技集团股份有限公司 移位寄存器单元及其控制方法、栅极驱动电路和显示装置
CN114974171A (zh) * 2022-03-09 2022-08-30 康佳集团股份有限公司 基于显示装置的刷新率控制方法、装置、显示终端及介质

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