WO2024119711A1 - 一种半导体基板的缺陷区域的评价方法及系统 - Google Patents
一种半导体基板的缺陷区域的评价方法及系统 Download PDFInfo
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Definitions
- the present invention belongs to the technical field of evaluating defective regions of semiconductor substrates, and in particular, relates to a method and system for evaluating defective regions of semiconductor substrates.
- Semiconductors refer to materials with electrical conductivity between conductors and insulators at room temperature. Semiconductors are used in integrated circuits, consumer electronics, communication systems, photovoltaic power generation, lighting, high-power power conversion and other fields. For example, diodes are devices made of semiconductors. Whether from the perspective of science and technology or economic development, the importance of semiconductors is enormous. Most electronic products, such as computers, mobile phones or core units of digital recorders, are closely related to semiconductors. Common semiconductor materials include silicon, germanium, gallium arsenide, etc. Silicon is the most influential one in various semiconductor material applications; however, the existing semiconductor substrate defect area evaluation system collects unclear images of semiconductor substrates, which affects the evaluation of defects; at the same time, the defect position of the semiconductor substrate cannot be accurately located.
- a system for evaluating a defective region of a semiconductor substrate comprises:
- Substrate image acquisition module main control module, substrate image enhancement module, image segmentation module, defect location module, defect evaluation module, display module;
- the main control module control method :
- the collected semiconductor substrate image is acquired by the central processing unit, and the collected semiconductor substrate image is sent to the substrate image enhancement module for enhancement processing; after processing, the image is fed back to the central processing unit;
- the central processing unit sends the enhanced image to the image segmentation module to segment the image features, and then feeds back to the central processing unit after segmentation;
- a substrate image enhancement module is connected to the main control module and is used to enhance the semiconductor substrate image
- evaluating the confidence that two or more spatially adjacent semiconductor substrate image blocks are clustered into the same cluster based on the semiconductor substrate image features of each semiconductor substrate image block includes: performing edge extraction on the input semiconductor substrate image to obtain an edge map;
- a defect locating module connected to the main control module, for locating defects on the semiconductor substrate;
- a defect evaluation module connected to the main control module, for evaluating defects of semiconductor substrates
- the display module is connected to the main control module and is used to display the semiconductor substrate image, positioning information, and defect evaluation results.
- a method for evaluating a defective region of a semiconductor substrate comprises the following steps:
- Step 1 collecting a semiconductor substrate image by a substrate image collection module
- Step 2 The main control module performs enhancement processing on the semiconductor substrate image through the substrate image enhancement module;
- Step three segmenting the semiconductor substrate image through an image segmentation module; locating the semiconductor substrate defects through a defect location module;
- Step 4 Evaluate the defects of the semiconductor substrate through the defect evaluation module; and display the semiconductor substrate image, positioning information, and defect evaluation results through the display module.
- substrate image enhancement module enhancement method is as follows:
- the semiconductor substrate image enhancement network includes at least two levels of sub-networks, the original semiconductor substrate image is used as the input of the first-level sub-network of the semiconductor substrate image enhancement network, the first-level sub-network outputs the first-level node semiconductor substrate image, the node semiconductor substrate image output by each level of sub-network is used as the input of the next level of sub-network, the last-level sub-network of the semiconductor substrate image enhancement network outputs the last-level node semiconductor substrate image, and the last-level node semiconductor substrate image is used as the enhanced semiconductor substrate image;
- the semiconductor substrate image enhancement network is obtained in advance by the following steps:
- the original semiconductor substrate image samples, the enhanced semiconductor substrate image samples and the multi-level node semiconductor substrate image samples are used as training samples to train the semiconductor substrate image enhancement network to obtain the trained semiconductor substrate image enhancement network; wherein the original semiconductor substrate image samples are used as the training input of the first-level sub-network, the enhanced sample semiconductor substrate image is used as the training output of the last-level sub-network, the node semiconductor substrate image samples of each level are used as the training input of the sub-network of the next level, and the node semiconductor substrate image samples of each level are used as the training output of the sub-network of the corresponding level.
- the semiconductor substrate image enhancement network is a fully convolutional network, and in a multi-level sub-network, sub-networks of different levels have different network parameters.
- the original semiconductor substrate image sample and the enhanced semiconductor substrate image sample generate a multi-level node semiconductor substrate image sample, specifically including:
- Corresponding multi-level node semiconductor substrate image samples are acquired according to the multi-level node semiconductor substrate image matrix.
- a multi-level node semiconductor substrate image matrix is inserted between the semiconductor substrate image matrix of the original semiconductor substrate image sample and the semiconductor substrate image matrix of the enhanced semiconductor substrate image sample, specifically:
- the semiconductor substrate image matrix of the original semiconductor substrate image sample and the enhanced semiconductor A multi-level node semiconductor substrate image matrix is inserted between the semiconductor substrate image matrices of the substrate image samples according to a preset gradient change.
- the step of obtaining the semiconductor substrate image enhancement network in advance also includes:
- the trained semiconductor substrate image enhancement network is optimized according to the target loss function to obtain an optimized semiconductor substrate image enhancement network.
- defect location module positioning method is as follows:
- the step of using a probe in a defect locator to carve a marking point at a position close to the defect point specifically includes:
- the step of using the probe to carve a marking point at the position specifically includes:
- the step of using the probe to carve a marking point at the position specifically includes:
- the determining of the positional relationship between the identification point and the defect point specifically includes:
- the determining of the positional relationship between the identification point and the defect point specifically includes:
- the positional relationship between the defect point and all the corresponding identification points is determined respectively.
- the method further includes:
- the step of using a probe in a defect locator to carve a marking point at a position close to the defect points specifically includes:
- the present invention uses a semiconductor substrate image enhancement network pre-obtained by a substrate image enhancement module to gradually enhance the original semiconductor substrate image, and the first-level sub-network of the semiconductor substrate image enhancement network performs first-level semiconductor substrate image enhancement on the original semiconductor substrate image to obtain a first-level node semiconductor substrate image, and the subsequent sub-networks of each level perform first-level semiconductor substrate image enhancement on the node semiconductor substrate image obtained by the previous sub-network in turn.
- the substrate image is subjected to semiconductor substrate image enhancement, and a final node semiconductor substrate image is obtained from the output of the final sub-network, and the final node semiconductor substrate image is used as an enhanced semiconductor substrate image corresponding to the original semiconductor substrate image; at the same time, the position of the defect point of the semiconductor substrate can be accurately located through the defect location module.
- the present invention uses a semiconductor substrate image enhancement network pre-obtained by a substrate image enhancement module to enhance the original semiconductor substrate image step by step, and the first-level subnetwork of the semiconductor substrate image enhancement network performs first-level semiconductor substrate image enhancement on the original semiconductor substrate image to obtain a first-level node semiconductor substrate image, and subsequent subnetworks of each level sequentially perform semiconductor substrate image enhancement on the node semiconductor substrate image obtained by the previous subnetwork, and the final node semiconductor substrate image is obtained from the output of the final subnetwork, and the final node semiconductor substrate image is used as the enhanced semiconductor substrate image corresponding to the original semiconductor substrate image; at the same time, the defect point position of the semiconductor substrate can be accurately located through the defect positioning module.
- FIG. 1 is a flow chart of a method for evaluating a defective region of a semiconductor substrate provided by an embodiment of the present invention.
- FIG. 2 is a structural block diagram of a defect region evaluation system for a semiconductor substrate provided by an embodiment of the present invention.
- FIG. 3 is a flow chart of a substrate image enhancement module enhancement method provided by an embodiment of the present invention.
- FIG. 4 is a flow chart of a defect location module positioning method provided by an embodiment of the present invention.
- the method for evaluating a defective region of a semiconductor substrate comprises the following steps:
- the main control module performs enhancement processing on the semiconductor substrate image through the substrate image enhancement module
- the defect area evaluation system for a semiconductor substrate includes: a substrate image acquisition module 1, a main control module 2, a substrate image enhancement module 3, an image segmentation module 4, a defect location module 5, a defect evaluation module 6, and a display module 7.
- the substrate image acquisition module 1 is connected to the main control module 2 and is used to acquire the semiconductor substrate image;
- the main control module 2 is connected with the substrate image acquisition module 1, the substrate image enhancement module 3, the image segmentation module 4, the defect location module 5, the defect evaluation module 6, and the display module 7, and is used to control the normal operation of each module;
- the main control module control method :
- the collected semiconductor substrate image is acquired by the central processing unit, and the collected semiconductor substrate image is sent to the substrate image enhancement module for enhancement processing; after processing, the image is fed back to the central processing unit;
- the central processing unit sends the enhanced image to the image segmentation module to segment the image features, and then feeds back to the central processing unit after segmentation;
- the central processor will send the acquired feature images to the defect location module and defect evaluation module for processing
- the substrate image enhancement module 3 is connected to the main control module 2 and is used to enhance the semiconductor substrate image. deal with;
- An image segmentation module 4 connected to the main control module 2, for segmenting the semiconductor substrate image
- the image segmentation module segmentation method :
- each semiconductor substrate image block including one or more pixels
- Each cluster of the semiconductor substrate image blocks forms a segmented region of the input semiconductor substrate image
- evaluating the confidence that two or more spatially adjacent semiconductor substrate image blocks are clustered into the same cluster based on the semiconductor substrate image features of each semiconductor substrate image block includes: performing edge extraction on the input semiconductor substrate image to obtain an edge map;
- a defect locating module 5 connected to the main control module 2, for locating defects on the semiconductor substrate;
- the display module 7 is connected to the main control module 2 and is used to display the semiconductor substrate image, positioning information, and defect evaluation results.
- the substrate image enhancement module enhancement method provided by the present invention is as follows:
- the semiconductor substrate image enhancement network includes at least two levels of sub-networks, the original semiconductor substrate image is used as the input of the first-level sub-network of the semiconductor substrate image enhancement network, the first-level sub-network outputs the first-level node semiconductor substrate image, the node semiconductor substrate image output by each level of sub-network is used as the input of the next level of sub-network, the last-level sub-network of the semiconductor substrate image enhancement network outputs the last-level node semiconductor substrate image, and the last-level node semiconductor substrate image is used as the enhanced semiconductor substrate image;
- the semiconductor substrate image enhancement network is obtained in advance by the following steps:
- the original semiconductor substrate image samples, the enhanced semiconductor substrate image samples and the multi-level node semiconductor substrate image samples are used as training samples to train the semiconductor substrate image enhancement network to obtain the trained semiconductor substrate image enhancement network; wherein the original semiconductor substrate image samples are used as the training input of the first-level sub-network, the enhanced sample semiconductor substrate image is used as the training output of the last-level sub-network, the node semiconductor substrate image samples of each level are used as the training input of the sub-network of the next level, and the node semiconductor substrate image samples of each level are used as the training output of the sub-network of the corresponding level.
- the semiconductor substrate image enhancement network provided by the present invention is a fully convolutional network, and in a multi-level sub-network, sub-networks of different levels have different network parameters.
- the original semiconductor substrate image sample and the enhanced semiconductor substrate image sample provided by the present invention generate a multi-level node semiconductor substrate image sample, specifically including:
- the semiconductor substrate image matrix of the original semiconductor substrate image sample and the enhanced semiconductor A multi-level node semiconductor substrate image matrix is inserted between the semiconductor substrate image matrices of the substrate image samples; wherein the number of levels of the multi-level node semiconductor substrate image matrix is one less than the number of levels of the sub-network;
- Corresponding multi-level node semiconductor substrate image samples are acquired according to the multi-level node semiconductor substrate image matrix.
- a multi-level node semiconductor substrate image matrix is inserted between the semiconductor substrate image matrix of the original semiconductor substrate image sample and the semiconductor substrate image matrix of the enhanced semiconductor substrate image sample provided by the present invention, specifically:
- a multi-level node semiconductor substrate image matrix is inserted between the semiconductor substrate image matrix of the original semiconductor substrate image sample and the semiconductor substrate image matrix of the enhanced semiconductor substrate image sample according to a preset gradient change.
- the step of obtaining the semiconductor substrate image enhancement network in advance provided by the present invention also includes:
- the trained semiconductor substrate image enhancement network is optimized according to the target loss function to obtain an optimized semiconductor substrate image enhancement network.
- the defect location module location method As shown in FIG4 , the defect location module location method provided by the present invention is as follows:
- S301 configuring parameters of a defect locator, electrically connecting a probe in the defect locator to a failed sample device of a semiconductor substrate; applying an excitation to the failed sample device of the semiconductor substrate to make a defect point appear;
- the step of using the probe in the defect locator to carve a marking point at a position close to the defect point specifically includes:
- the step of using the probe to carve a marking point at the position specifically includes:
- the step of using the probe to carve a marking point at the position specifically includes:
- the determining of the positional relationship between the identification point and the defect point specifically includes:
- the determining of the positional relationship between the identification point and the defect point specifically includes:
- the method further includes:
- the step of using a probe in a defect locator to carve a marking point at a position close to the defect point specifically includes:
- the present invention uses a semiconductor substrate image enhancement network pre-obtained by a substrate image enhancement module to enhance the original semiconductor substrate image step by step, and the first-level subnetwork of the semiconductor substrate image enhancement network performs first-level semiconductor substrate image enhancement on the original semiconductor substrate image to obtain a first-level node semiconductor substrate image, and subsequent subnetworks of each level sequentially perform semiconductor substrate image enhancement on the node semiconductor substrate image obtained by the previous subnetwork, and the final node semiconductor substrate image is obtained from the output of the final subnetwork, and the final node semiconductor substrate image is used as the enhanced semiconductor substrate image corresponding to the original semiconductor substrate image; at the same time, the defect point position of the semiconductor substrate can be accurately located through the defect positioning module.
- the embodiments of the present invention can be implemented by hardware, software, or a combination of software and hardware.
- the hardware part can be implemented using dedicated logic; the software part can be stored in a memory and executed by an appropriate instruction execution system, such as a microprocessor or dedicated design hardware.
- an appropriate instruction execution system such as a microprocessor or dedicated design hardware.
- a person of ordinary skill in the art will appreciate that the above-mentioned devices and methods can be implemented using computer executable instructions and/or contained in a processor control code, such as a carrier medium such as a disk, CD or DVD-ROM, a programmable memory such as a read-only memory (firmware), or a data carrier such as an optical or electronic signal carrier. Such code is provided on the carrier medium.
- the device and its modules of the present invention can be implemented by hardware circuits such as very large-scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, etc., or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., can also be implemented by software executed by various types of processors, and can also be implemented by a combination of the above-mentioned hardware circuits and software, such as firmware.
- the present invention uses a semiconductor substrate image enhancement network pre-obtained by a substrate image enhancement module to gradually enhance the original semiconductor substrate image.
- the first-level subnetwork of the semiconductor substrate image enhancement network performs first-level semiconductor substrate image enhancement on the original semiconductor substrate image to obtain a first-level node semiconductor substrate image, and the subsequent subnetworks of each level sequentially perform semiconductor substrate image enhancement on the node semiconductor substrate image obtained by the previous subnetwork, and obtain the last-level node semiconductor substrate image from the output of the last-level subnetwork.
- Conductor substrate image, using the final node semiconductor substrate image as the enhanced semiconductor substrate image corresponding to the original semiconductor substrate image; at the same time, the defect point position of the semiconductor substrate can be accurately located through the defect location module.
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Abstract
本发明属于半导体基板的缺陷区域的评价技术领域，公开了一种半导体基板的缺陷区域的评价方法及系统，所述半导体基板的缺陷区域的评价系统包括：基板图像采集模块、主控模块、基板图像增强模块、图像分割模块、缺陷定位模块、缺陷评价模块、显示模块。本发明通过基板图像增强模块获得首级节点半导体基板图像，并由后续的各级子网络依次对上一级子网络获得的节点半导体基板图像进行半导体基板图像增强，从所述末级子网络的输出获得末级节点半导体基板图像，以所述末级节点半导体基板图像作为所述原始半导体基板图像对应的增强半导体基板图像；同时，通过缺陷定位模块可以准确定位半导体基板缺陷点位置。
Description
本发明属于半导体基板的缺陷区域的评价技术领域，尤其涉及一种半导体基板的缺陷区域的评价方法及系统。
半导体指常温下导电性能介于导体与绝缘体之间的材料。半导体在集成电路、消费电子、通信系统、光伏发电、照明、大功率电源转换等领域都有应用，如二极管就是采用半导体制作的器件。无论从科技或是经济发展的角度来看，半导体的重要性都是非常巨大的。大部分的电子产品，如计算机、移动电话或是数字录音机当中的核心单元都和半导体有着极为密切的关联。常见的半导体材料有硅、锗、砷化镓等，硅是各种半导体材料应用中最具有影响力的一种；然而，现有半导体基板的缺陷区域的评价系统采集的半导体基板图像不清晰，影响对缺陷的评价；同时，不能准确定位半导体基板缺陷位置。
通过上述分析，现有技术存在的问题及缺陷为：
(1)现有半导体基板的缺陷区域的评价系统采集的半导体基板图像不清晰，影响对缺陷的评价。
(2)不能准确定位半导体基板缺陷位置。
发明内容
针对现有技术存在的问题，本发明提供了一种半导体基板的缺陷区域的评价方法及系统。
本发明是这样实现的，一种半导体基板的缺陷区域的评价系统包括：
基板图像采集模块、主控模块、基板图像增强模块、图像分割模块、缺陷定位模块、缺陷评价模块、显示模块；
基板图像采集模块，与主控模块连接，用于采集半导体基板图像；
主控模块，与基板图像采集模块、基板图像增强模块、图像分割模块、缺陷定位模块、缺陷评价模块、显示模块连接，用于控制各个模块正常工作；
所述主控模块控制方法：
通过中央处理器获取采集的采集半导体基板图像，并将采集半导体基板图像发送到基板图像增强模块进行增强处理；处理后反馈给中央处理器；
中央处理器将增强的图像发送到图像分割模块对图像特征进行分割，分割后反馈给中央处理器；
最后，中央处理器将获取特征图像分别发送缺陷定位模块、缺陷评价模块进行处理；
基板图像增强模块，与主控模块连接，用于对半导体基板图像进行增强处理；
图像分割模块，与主控模块连接，用于对半导体基板图像进行分割处理；
所述图像分割模块分割方法：
提取输入半导体基板图像中的各个半导体基板图像块的半导体基板图像特征，每个半导体基板图像块包括一个或更多个像素；
基于各半导体基板图像块的半导体基板图像特征来评估在空间上相邻的两个或更多个相邻半导体基板图像块被聚类到同一聚类中的置信度；
以及对所述半导体基板图像块进行基于样例的聚类，其中在聚类过程中考虑了所述评估的结果；
所述半导体基板图像块的每一聚类形成所述输入半导体基板图像的一个分割区域；
其中，基于各半导体基板图像块的半导体基板图像特征来评估在空间上相邻的两个或更多个相邻半导体基板图像块被聚类到同一聚类中的置信度包括：对所述输入半导体基板图像进行边缘提取，得到边缘图；
计算所述边缘图中与所述相邻半导体基板图像块对应的相邻边缘图块之间
的边缘损失；
以及基于所述边缘损失来评估所述相邻半导体基板图像块被聚类到同一聚类中的置信度；
缺陷定位模块，与主控模块连接，用于对半导体基板缺陷进行定位；
缺陷评价模块，与主控模块连接，用于对半导体基板缺陷进行评价；
显示模块，与主控模块连接，用于显示半导体基板图像、定位信息、缺陷评价结果。
一种半导体基板的缺陷区域的评价方法包括以下步骤：
步骤一，通过基板图像采集模块采集半导体基板图像；
步骤二，主控模块通过基板图像增强模块对半导体基板图像进行增强处理；
步骤三，通过图像分割模块对半导体基板图像进行分割处理；通过缺陷定位模块对半导体基板缺陷进行定位；
步骤四，通过缺陷评价模块对半导体基板缺陷进行评价；通过显示模块显示半导体基板图像、定位信息、缺陷评价结果。
进一步，所述基板图像增强模块增强方法如下：
(1)获取原始半导体基板图像；对原始半导体基板图像去噪处理；将所述原始半导体基板图像输入预先得到的半导体基板图像增强网络，对所述原始半导体基板图像进行逐级增强，得到所述原始半导体基板图像对应的增强半导体基板图像；
其中，所述半导体基板图像增强网络包括至少两级子网络，所述原始半导体基板图像作为所述半导体基板图像增强网络的首级子网络的输入，所述首级子网络输出首级节点半导体基板图像，每一级子网络输出的节点半导体基板图像作为下一级子网络的输入，所述半导体基板图像增强网络的末级子网络输出末级节点半导体基板图像，所述末级节点半导体基板图像作为所述增强半导体基板图像；
通过如下步骤预先得到所述半导体基板图像增强网络：
获取原始半导体基板图像样本和对应的增强半导体基板图像样本；
根据所述原始半导体基板图像样本和所述增强半导体基板图像样本，生成多级节点半导体基板图像样本；其中所述多级节点半导体基板图像样本的级数比所述子网络的级数少一；
将所述原始半导体基板图像样本、所述增强半导体基板图像样本和所述多级节点半导体基板图像样本作为训练样本，对所述半导体基板图像增强网络进行训练，得到完成训练的所述半导体基板图像增强网络；其中，所述原始半导体基板图像样本作为首级子网络的训练输入，所述增强样本半导体基板图像作为末级子网络的训练输出，每一级的节点半导体基板图像样本作为下一级次的所述子网络的训练输入，且每一级的节点半导体基板图像样本作为对应级次的所述子网络的训练输出。
进一步，所述半导体基板图像增强网络为全卷积网络，并且在多级子网络中，不同级次的子网络具有不完全相同的网络参数。
进一步，所述原始半导体基板图像样本和所述增强半导体基板图像样本，生成多级节点半导体基板图像样本，具体包括：
获取所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵；
在所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵之间插入多级节点半导体基板图像矩阵；其中，所述多级节点半导体基板图像矩阵的级数比所述子网络的级数少一；
根据所述多级节点半导体基板图像矩阵获取相应的多级节点半导体基板图像样本。
进一步，所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵之间插入多级节点半导体基板图像矩阵，具体为：
在所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体
基板图像样本的半导体基板图像矩阵之间，根据预设的梯度变化插入多级节点半导体基板图像矩阵。
进一步，所述预先得到所述半导体基板图像增强网络的步骤还包括：
生成每一级节点半导体基板图像样本对应的节点特征图；
将所述原始半导体基板图像样本输入完成训练的所述半导体基板图像增强网络，得到测试的增强半导体基板图像样本；
以所述节点特征图和所述测试的增强半导体基板图像样本作为函数参数，构建所述半导体基板图像增强网络的目标损失函数；
根据所述目标损失函数对所述完成训练的所述半导体基板图像增强网络进行优化，得到优化的所述半导体基板图像增强网络。
进一步，所述缺陷定位模块定位方法如下：
1)配置缺陷定位仪参数，将缺陷定位仪中的探针与半导体基板的失效样品器件进行电性连接；对所述半导体基板的失效样品器件施加激励，使缺陷点显现；
2)使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点；确定标识点和缺陷点的位置关系；根据标识点的位置和所述位置关系，定位所述缺陷点。
进一步，所述对所述半导体基板的器件施加激励使缺陷点显现的步骤中，当显现出一个缺陷点时，所述使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点的步骤，具体包括：
移动缺陷定位仪中的探针至靠近所述缺陷点的位置；
使用所述探针在该位置刻出标识点；
所述使用所述探针在该位置刻出标识点，具体包括：
使用所述探针在该位置刻出一个标识点；
所述使用所述探针在该位置刻出标识点，具体包括：
使用所述探针在该位置刻出至少两个标识点；
所述确定标识点和缺陷点的位置关系，具体包括：
选择与所述缺陷点距离最近的标识点作为目标标识点；
确定所述目标标识点和所述缺陷点的位置关系；
所述确定标识点和缺陷点的位置关系，具体包括：
分别确定所述缺陷点和其对应的所有标识点的位置关系。
进一步，所述确定标识点和缺陷点的位置关系之前，还包括：
移动所述探针返回初始位置；
再次对所述半导体基板的器件施加激励，使缺陷点再次显现；
对所述半导体基板的器件施加激励使缺陷点显现的步骤中，当显现出至少两个缺陷点时，所述使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点的步骤，具体包括：
移动缺陷定位仪中的探针至靠近其中一个缺陷点的位置；
使用所述探针在该位置刻出标识点；
移动所述探针返回初始位置；
再次对所述半导体基板的器件施加激励，使缺陷点再次显现；
重复上述步骤直至为所有的缺陷点都刻出对应的标识点。
结合上述的技术方案和解决的技术问题，请从以下几方面分析本发明所要保护的技术方案所具备的优点及积极效果为：
第一、针对上述现有技术存在的技术问题以及解决该问题的难度，紧密结合本发明的所要保护的技术方案以及研发过程中结果和数据等，详细、深刻地分析本发明技术方案如何解决的技术问题，解决问题之后带来的一些具备创造性的技术效果。具体描述如下：
本发明通过基板图像增强模块预先得到的半导体基板图像增强网络对原始半导体基板图像进行逐级增强，由所述半导体基板图像增强网络的首级子网络对所述原始半导体基板图像进行首级半导体基板图像增强，以获得首级节点半导体基板图像，并由后续的各级子网络依次对上一级子网络获得的节点半导体
基板图像进行半导体基板图像增强，从所述末级子网络的输出获得末级节点半导体基板图像，以所述末级节点半导体基板图像作为所述原始半导体基板图像对应的增强半导体基板图像；同时，通过缺陷定位模块可以准确定位半导体基板缺陷点位置。
第二，把技术方案视为一个整体或者从产品的角度，本发明所要保护的技术方案具备的技术效果和优点，具体描述如下：
本发明通过基板图像增强模块预先得到的半导体基板图像增强网络对原始半导体基板图像进行逐级增强，由所述半导体基板图像增强网络的首级子网络对所述原始半导体基板图像进行首级半导体基板图像增强，以获得首级节点半导体基板图像，并由后续的各级子网络依次对上一级子网络获得的节点半导体基板图像进行半导体基板图像增强，从所述末级子网络的输出获得末级节点半导体基板图像，以所述末级节点半导体基板图像作为所述原始半导体基板图像对应的增强半导体基板图像；同时，通过缺陷定位模块可以准确定位半导体基板缺陷点位置。
图1是本发明实施例提供的半导体基板的缺陷区域的评价方法流程图。
图2是本发明实施例提供的半导体基板的缺陷区域的评价系统结构框图。
图3是本发明实施例提供的基板图像增强模块增强方法流程图。
图4是本发明实施例提供的缺陷定位模块定位方法流程图。
图2中：1、基板图像采集模块；2、主控模块；3、基板图像增强模块；4、图像分割模块；5、缺陷定位模块；6、缺陷评价模块；7、显示模块。
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以
解释本发明，并不用于限定本发明。
一、解释说明实施例。为了使本领域技术人员充分了解本发明如何具体实现，该部分是对权利要求技术方案进行展开说明的解释说明实施例。
如图1所示，本发明提供的半导体基板的缺陷区域的评价方法包括以下步骤：
S101，通过基板图像采集模块采集半导体基板图像；
S102，主控模块通过基板图像增强模块对半导体基板图像进行增强处理；
S103，通过图像分割模块对半导体基板图像进行分割处理；通过缺陷定位模块对半导体基板缺陷进行定位；
S104，通过缺陷评价模块对半导体基板缺陷进行评价；通过显示模块显示半导体基板图像、定位信息、缺陷评价结果。
如图2所示，本发明实施例提供的半导体基板的缺陷区域的评价系统包括：基板图像采集模块1、主控模块2、基板图像增强模块3、图像分割模块4、缺陷定位模块5、缺陷评价模块6、显示模块7。
基板图像采集模块1，与主控模块2连接，用于采集半导体基板图像；
主控模块2，与基板图像采集模块1、基板图像增强模块3、图像分割模块4、缺陷定位模块5、缺陷评价模块6、显示模块7连接，用于控制各个模块正常工作；
所述主控模块控制方法：
通过中央处理器获取采集的采集半导体基板图像，并将采集半导体基板图像发送到基板图像增强模块进行增强处理；处理后反馈给中央处理器；
中央处理器将增强的图像发送到图像分割模块对图像特征进行分割，分割后反馈给中央处理器；
最后，中央处理器将获取特征图像分别发送缺陷定位模块、缺陷评价模块进行处理；
基板图像增强模块3，与主控模块2连接，用于对半导体基板图像进行增强
处理；
图像分割模块4，与主控模块2连接，用于对半导体基板图像进行分割处理；
所述图像分割模块分割方法：
提取输入半导体基板图像中的各个半导体基板图像块的半导体基板图像特征，每个半导体基板图像块包括一个或更多个像素；
基于各半导体基板图像块的半导体基板图像特征来评估在空间上相邻的两个或更多个相邻半导体基板图像块被聚类到同一聚类中的置信度；
以及对所述半导体基板图像块进行基于样例的聚类，其中在聚类过程中考虑了所述评估的结果；
所述半导体基板图像块的每一聚类形成所述输入半导体基板图像的一个分割区域；
其中，基于各半导体基板图像块的半导体基板图像特征来评估在空间上相邻的两个或更多个相邻半导体基板图像块被聚类到同一聚类中的置信度包括：对所述输入半导体基板图像进行边缘提取，得到边缘图；
计算所述边缘图中与所述相邻半导体基板图像块对应的相邻边缘图块之间的边缘损失；
以及基于所述边缘损失来评估所述相邻半导体基板图像块被聚类到同一聚类中的置信度；
缺陷定位模块5，与主控模块2连接，用于对半导体基板缺陷进行定位；
缺陷评价模块6，与主控模块2连接，用于对半导体基板缺陷进行评价；
显示模块7，与主控模块2连接，用于显示半导体基板图像、定位信息、缺陷评价结果。
如图3所示，本发明提供的基板图像增强模块增强方法如下：
S201，获取原始半导体基板图像；对原始半导体基板图像去噪处理；将所述原始半导体基板图像输入预先得到的半导体基板图像增强网络，对所述原始半导体基板图像进行逐级增强，得到所述原始半导体基板图像对应的增强半导
体基板图像；
其中，所述半导体基板图像增强网络包括至少两级子网络，所述原始半导体基板图像作为所述半导体基板图像增强网络的首级子网络的输入，所述首级子网络输出首级节点半导体基板图像，每一级子网络输出的节点半导体基板图像作为下一级子网络的输入，所述半导体基板图像增强网络的末级子网络输出末级节点半导体基板图像，所述末级节点半导体基板图像作为所述增强半导体基板图像；
通过如下步骤预先得到所述半导体基板图像增强网络：
获取原始半导体基板图像样本和对应的增强半导体基板图像样本；
根据所述原始半导体基板图像样本和所述增强半导体基板图像样本，生成多级节点半导体基板图像样本；其中所述多级节点半导体基板图像样本的级数比所述子网络的级数少一；
将所述原始半导体基板图像样本、所述增强半导体基板图像样本和所述多级节点半导体基板图像样本作为训练样本，对所述半导体基板图像增强网络进行训练，得到完成训练的所述半导体基板图像增强网络；其中，所述原始半导体基板图像样本作为首级子网络的训练输入，所述增强样本半导体基板图像作为末级子网络的训练输出，每一级的节点半导体基板图像样本作为下一级次的所述子网络的训练输入，且每一级的节点半导体基板图像样本作为对应级次的所述子网络的训练输出。
本发明提供的半导体基板图像增强网络为全卷积网络，并且在多级子网络中，不同级次的子网络具有不完全相同的网络参数。
本发明提供的原始半导体基板图像样本和所述增强半导体基板图像样本，生成多级节点半导体基板图像样本，具体包括：
获取所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵；
在所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体
基板图像样本的半导体基板图像矩阵之间插入多级节点半导体基板图像矩阵；其中，所述多级节点半导体基板图像矩阵的级数比所述子网络的级数少一；
根据所述多级节点半导体基板图像矩阵获取相应的多级节点半导体基板图像样本。
本发明提供的原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵之间插入多级节点半导体基板图像矩阵，具体为：
在所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵之间，根据预设的梯度变化插入多级节点半导体基板图像矩阵。
本发明提供的预先得到所述半导体基板图像增强网络的步骤还包括：
生成每一级节点半导体基板图像样本对应的节点特征图；
将所述原始半导体基板图像样本输入完成训练的所述半导体基板图像增强网络，得到测试的增强半导体基板图像样本；
以所述节点特征图和所述测试的增强半导体基板图像样本作为函数参数，构建所述半导体基板图像增强网络的目标损失函数；
根据所述目标损失函数对所述完成训练的所述半导体基板图像增强网络进行优化，得到优化的所述半导体基板图像增强网络。
如图4所示，本发明提供的缺陷定位模块定位方法如下：
S301，配置缺陷定位仪参数，将缺陷定位仪中的探针与半导体基板的失效样品器件进行电性连接；对所述半导体基板的失效样品器件施加激励，使缺陷点显现；
S302，使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点；确定标识点和缺陷点的位置关系；根据标识点的位置和所述位置关系，定位所述缺陷点。
本发明提供的对所述半导体基板的器件施加激励使缺陷点显现的步骤中，
当显现出一个缺陷点时，所述使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点的步骤，具体包括：
移动缺陷定位仪中的探针至靠近所述缺陷点的位置；
使用所述探针在该位置刻出标识点；
所述使用所述探针在该位置刻出标识点，具体包括：
使用所述探针在该位置刻出一个标识点；
所述使用所述探针在该位置刻出标识点，具体包括：
使用所述探针在该位置刻出至少两个标识点；
所述确定标识点和缺陷点的位置关系，具体包括：
选择与所述缺陷点距离最近的标识点作为目标标识点；
确定所述目标标识点和所述缺陷点的位置关系；
所述确定标识点和缺陷点的位置关系，具体包括：
分别确定所述缺陷点和其对应的所有标识点的位置关系；
所述确定标识点和缺陷点的位置关系之前，还包括：
移动所述探针返回初始位置；
再次对所述半导体基板的器件施加激励，使缺陷点再次显现；
对所述半导体基板的器件施加激励使缺陷点显现的步骤中，当显现出至少两个缺陷点时，所述使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点的步骤，具体包括：
移动缺陷定位仪中的探针至靠近其中一个缺陷点的位置；
使用所述探针在该位置刻出标识点；
移动所述探针返回初始位置；
再次对所述半导体基板的器件施加激励，使缺陷点再次显现；
重复上述步骤直至为所有的缺陷点都刻出对应的标识点。
二、应用实施例。为了证明本发明的技术方案的创造性和技术价值，该部分是对权利要求技术方案进行具体产品上或相关技术上的应用实施例。
本发明通过基板图像增强模块预先得到的半导体基板图像增强网络对原始半导体基板图像进行逐级增强，由所述半导体基板图像增强网络的首级子网络对所述原始半导体基板图像进行首级半导体基板图像增强，以获得首级节点半导体基板图像，并由后续的各级子网络依次对上一级子网络获得的节点半导体基板图像进行半导体基板图像增强，从所述末级子网络的输出获得末级节点半导体基板图像，以所述末级节点半导体基板图像作为所述原始半导体基板图像对应的增强半导体基板图像；同时，通过缺陷定位模块可以准确定位半导体基板缺陷点位置。
应当注意，本发明的实施方式可以通过硬件、软件或者软件和硬件的结合来实现。硬件部分可以利用专用逻辑来实现；软件部分可以存储在存储器中，由适当的指令执行系统，例如微处理器或者专用设计硬件来执行。本领域的普通技术人员可以理解上述的设备和方法可以使用计算机可执行指令和/或包含在处理器控制代码中来实现，例如在诸如磁盘、CD或DVD-ROM的载体介质、诸如只读存储器(固件)的可编程的存储器或者诸如光学或电子信号载体的数据载体上提供了这样的代码。本发明的设备及其模块可以由诸如超大规模集成电路或门阵列、诸如逻辑芯片、晶体管等的半导体、或者诸如现场可编程门阵列、可编程逻辑设备等的可编程硬件设备的硬件电路实现，也可以用由各种类型的处理器执行的软件实现，也可以由上述硬件电路和软件的结合例如固件来实现。
三、实施例相关效果的证据。本发明实施例在研发或者使用过程中取得了一些积极效果，和现有技术相比的确具备很大的优势，下面内容结合试验过程的数据、图表等进行描述。
本发明通过基板图像增强模块预先得到的半导体基板图像增强网络对原始半导体基板图像进行逐级增强，由所述半导体基板图像增强网络的首级子网络对所述原始半导体基板图像进行首级半导体基板图像增强，以获得首级节点半导体基板图像，并由后续的各级子网络依次对上一级子网络获得的节点半导体基板图像进行半导体基板图像增强，从所述末级子网络的输出获得末级节点半
导体基板图像，以所述末级节点半导体基板图像作为所述原始半导体基板图像对应的增强半导体基板图像；同时，通过缺陷定位模块可以准确定位半导体基板缺陷点位置。
以上所述，仅为本发明的具体实施方式，但本发明的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本发明揭露的技术范围内，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，都应涵盖在本发明的保护范围之内。
Claims (10)
- 一种半导体基板的缺陷区域的评价系统，其特征在于，所述半导体基板的缺陷区域的评价系统包括：基板图像采集模块、主控模块、基板图像增强模块、图像分割模块、缺陷定位模块、缺陷评价模块、显示模块；基板图像采集模块，与主控模块连接，用于采集半导体基板图像；主控模块，与基板图像采集模块、基板图像增强模块、图像分割模块、缺陷定位模块、缺陷评价模块、显示模块连接，用于控制各个模块正常工作；所述主控模块控制方法：通过中央处理器获取采集的采集半导体基板图像，并将采集半导体基板图像发送到基板图像增强模块进行增强处理；处理后反馈给中央处理器；中央处理器将增强的图像发送到图像分割模块对图像特征进行分割，分割后反馈给中央处理器；最后，中央处理器将获取特征图像分别发送缺陷定位模块、缺陷评价模块进行处理；基板图像增强模块，与主控模块连接，用于对半导体基板图像进行增强处理；图像分割模块，与主控模块连接，用于对半导体基板图像进行分割处理；所述图像分割模块分割方法：提取输入半导体基板图像中的各个半导体基板图像块的半导体基板图像特征，每个半导体基板图像块包括一个或更多个像素；基于各半导体基板图像块的半导体基板图像特征来评估在空间上相邻的两个或更多个相邻半导体基板图像块被聚类到同一聚类中的置信度；以及对所述半导体基板图像块进行基于样例的聚类，其中在聚类过程中考虑了所述评估的结果；所述半导体基板图像块的每一聚类形成所述输入半导体基板图像的一个分割区域；其中，基于各半导体基板图像块的半导体基板图像特征来评估在空间上相邻的两个或更多个相邻半导体基板图像块被聚类到同一聚类中的置信度包括：对所述输入半导体基板图像进行边缘提取，得到边缘图；计算所述边缘图中与所述相邻半导体基板图像块对应的相邻边缘图块之间的边缘损失；以及基于所述边缘损失来评估所述相邻半导体基板图像块被聚类到同一聚类中的置信度；缺陷定位模块，与主控模块连接，用于对半导体基板缺陷进行定位；缺陷评价模块，与主控模块连接，用于对半导体基板缺陷进行评价；显示模块，与主控模块连接，用于显示半导体基板图像、定位信息、缺陷评价结果。
- 一种如权利要求1所述的半导体基板的缺陷区域的评价方法，其特征在于，所述半导体基板的缺陷区域的评价方法包括以下步骤：步骤一，通过基板图像采集模块采集半导体基板图像；步骤二，主控模块通过基板图像增强模块对半导体基板图像进行增强处理；步骤三，通过图像分割模块对半导体基板图像进行分割处理；通过缺陷定位模块对半导体基板缺陷进行定位；步骤四，通过缺陷评价模块对半导体基板缺陷进行评价；通过显示模块显示半导体基板图像、定位信息、缺陷评价结果。
- 如权利要求1所述半导体基板的缺陷区域的评价系统，其特征在于，所述基板图像增强模块增强方法如下：(1)获取原始半导体基板图像；对原始半导体基板图像去噪处理；将所述原始半导体基板图像输入预先得到的半导体基板图像增强网络，对所述原始半导体基板图像进行逐级增强，得到所述原始半导体基板图像对应的增强半导体基板图像；其中，所述半导体基板图像增强网络包括至少两级子网络，所述原始半导 体基板图像作为所述半导体基板图像增强网络的首级子网络的输入，所述首级子网络输出首级节点半导体基板图像，每一级子网络输出的节点半导体基板图像作为下一级子网络的输入，所述半导体基板图像增强网络的末级子网络输出末级节点半导体基板图像，所述末级节点半导体基板图像作为所述增强半导体基板图像；通过如下步骤预先得到所述半导体基板图像增强网络：获取原始半导体基板图像样本和对应的增强半导体基板图像样本；根据所述原始半导体基板图像样本和所述增强半导体基板图像样本，生成多级节点半导体基板图像样本；其中所述多级节点半导体基板图像样本的级数比所述子网络的级数少一；将所述原始半导体基板图像样本、所述增强半导体基板图像样本和所述多级节点半导体基板图像样本作为训练样本，对所述半导体基板图像增强网络进行训练，得到完成训练的所述半导体基板图像增强网络；其中，所述原始半导体基板图像样本作为首级子网络的训练输入，所述增强样本半导体基板图像作为末级子网络的训练输出，每一级的节点半导体基板图像样本作为下一级次的所述子网络的训练输入，且每一级的节点半导体基板图像样本作为对应级次的所述子网络的训练输出。
- 如权利要求3所述半导体基板的缺陷区域的评价系统，其特征在于，所述半导体基板图像增强网络为全卷积网络，并且在多级子网络中，不同级次的子网络具有不完全相同的网络参数。
- 如权利要求3所述半导体基板的缺陷区域的评价系统，其特征在于，所述原始半导体基板图像样本和所述增强半导体基板图像样本，生成多级节点半导体基板图像样本，具体包括：获取所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵；在所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体 基板图像样本的半导体基板图像矩阵之间插入多级节点半导体基板图像矩阵；其中，所述多级节点半导体基板图像矩阵的级数比所述子网络的级数少一；根据所述多级节点半导体基板图像矩阵获取相应的多级节点半导体基板图像样本。
- 如权利要求3所述半导体基板的缺陷区域的评价系统，其特征在于，所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵之间插入多级节点半导体基板图像矩阵，具体为：在所述原始半导体基板图像样本的半导体基板图像矩阵和所述增强半导体基板图像样本的半导体基板图像矩阵之间，根据预设的梯度变化插入多级节点半导体基板图像矩阵。
- 如权利要求3所述半导体基板的缺陷区域的评价系统，其特征在于，所述预先得到所述半导体基板图像增强网络的步骤还包括：生成每一级节点半导体基板图像样本对应的节点特征图；将所述原始半导体基板图像样本输入完成训练的所述半导体基板图像增强网络，得到测试的增强半导体基板图像样本；以所述节点特征图和所述测试的增强半导体基板图像样本作为函数参数，构建所述半导体基板图像增强网络的目标损失函数；根据所述目标损失函数对所述完成训练的所述半导体基板图像增强网络进行优化，得到优化的所述半导体基板图像增强网络。
- 如权利要求1所述半导体基板的缺陷区域的评价系统，其特征在于，所述缺陷定位模块定位方法如下：1)配置缺陷定位仪参数，将缺陷定位仪中的探针与半导体基板的失效样品器件进行电性连接；对所述半导体基板的失效样品器件施加激励，使缺陷点显现；2)使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点；确定标识点和缺陷点的位置关系；根据标识点的位置和所述位置关系，定位所述缺陷 点。
- 如权利要求8所述半导体基板的缺陷区域的评价系统，其特征在于，所述对所述半导体基板的器件施加激励使缺陷点显现的步骤中，当显现出一个缺陷点时，所述使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点的步骤，具体包括：移动缺陷定位仪中的探针至靠近所述缺陷点的位置；使用所述探针在该位置刻出标识点；所述使用所述探针在该位置刻出标识点，具体包括：使用所述探针在该位置刻出一个标识点；所述使用所述探针在该位置刻出标识点，具体包括：使用所述探针在该位置刻出至少两个标识点；所述确定标识点和缺陷点的位置关系，具体包括：选择与所述缺陷点距离最近的标识点作为目标标识点；确定所述目标标识点和所述缺陷点的位置关系；所述确定标识点和缺陷点的位置关系，具体包括：分别确定所述缺陷点和其对应的所有标识点的位置关系。
- 如权利要求8所述半导体基板的缺陷区域的评价系统，其特征在于，所述确定标识点和缺陷点的位置关系之前，还包括：移动所述探针返回初始位置；再次对所述半导体基板的器件施加激励，使缺陷点再次显现；对所述半导体基板的器件施加激励使缺陷点显现的步骤中，当显现出至少两个缺陷点时，所述使用缺陷定位仪中的探针在靠近所述缺陷点的位置刻出标识点的步骤，具体包括：移动缺陷定位仪中的探针至靠近其中一个缺陷点的位置；使用所述探针在该位置刻出标识点；移动所述探针返回初始位置；再次对所述半导体基板的器件施加激励，使缺陷点再次显现；重复上述步骤直至为所有的缺陷点都刻出对应的标识点。
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109102468A (zh) * | 2018-06-27 | 2018-12-28 | 广州视源电子科技股份有限公司 | 图像增强方法、装置、终端设备及存储介质 |
| CN111862067A (zh) * | 2020-07-28 | 2020-10-30 | 中山佳维电子有限公司 | 一种焊接缺陷检测方法、装置、电子设备以及存储介质 |
| US20210073972A1 (en) * | 2019-09-06 | 2021-03-11 | Accenture Global Solutions Limited | Intelligent defect detection from image data |
| CN115205279A (zh) * | 2020-05-04 | 2022-10-18 | 应用材料以色列公司 | 检验半导体样本的系统和方法 |
| CN115731228A (zh) * | 2022-11-30 | 2023-03-03 | 杭州数途信息科技有限公司 | 一种镀金芯片缺陷检测系统和方法 |
| CN115830594A (zh) * | 2022-12-02 | 2023-03-21 | 内蒙古农业大学 | 一种基于机器学习算法的牛乳体细胞图像识别方法 |
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- 2023-04-13 CN CN202310392900.4A patent/CN116739975A/zh not_active Withdrawn
- 2023-05-09 WO PCT/CN2023/092877 patent/WO2024119711A1/zh unknown
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109102468A (zh) * | 2018-06-27 | 2018-12-28 | 广州视源电子科技股份有限公司 | 图像增强方法、装置、终端设备及存储介质 |
| US20210073972A1 (en) * | 2019-09-06 | 2021-03-11 | Accenture Global Solutions Limited | Intelligent defect detection from image data |
| CN115205279A (zh) * | 2020-05-04 | 2022-10-18 | 应用材料以色列公司 | 检验半导体样本的系统和方法 |
| CN111862067A (zh) * | 2020-07-28 | 2020-10-30 | 中山佳维电子有限公司 | 一种焊接缺陷检测方法、装置、电子设备以及存储介质 |
| CN115731228A (zh) * | 2022-11-30 | 2023-03-03 | 杭州数途信息科技有限公司 | 一种镀金芯片缺陷检测系统和方法 |
| CN115830594A (zh) * | 2022-12-02 | 2023-03-21 | 内蒙古农业大学 | 一种基于机器学习算法的牛乳体细胞图像识别方法 |
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