WO2024119697A1 - 一种dcdc降压装置的驱动级供电电路 - Google Patents

一种dcdc降压装置的驱动级供电电路 Download PDF

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Publication number
WO2024119697A1
WO2024119697A1 PCT/CN2023/090215 CN2023090215W WO2024119697A1 WO 2024119697 A1 WO2024119697 A1 WO 2024119697A1 CN 2023090215 W CN2023090215 W CN 2023090215W WO 2024119697 A1 WO2024119697 A1 WO 2024119697A1
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Prior art keywords
transistor
driving
power supply
pin
signal
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PCT/CN2023/090215
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English (en)
French (fr)
Inventor
李博
杨义凯
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上海裕芯电子科技有限公司
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Publication of WO2024119697A1 publication Critical patent/WO2024119697A1/zh

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Classifications

    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/36—Means for starting or stopping converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Definitions

  • the invention belongs to the field of integrated circuit DCDC step-down devices and relates to a driving-level power supply circuit of a DCDC step-down device.
  • DCDC refers to converting a fixed DC voltage into a variable DC voltage.
  • adding a driver-level acceleration control circuit can meet the power supply requirements of the driver-level circuit without the need for additional power pins.
  • the driver-level power supply circuit of the DCDC step-down device is becoming more and more widely used.
  • FIG1 is a schematic diagram of a driving stage power supply circuit of a DCDC step-down device in the prior art.
  • the circuit includes a Q1 driving module, a Q2 driving module and a Q3 driving module; the circuit is connected to one or more driving units (DR1 and DR2, etc.) in the Q2 driving module through an external pin VDD to provide power for it, and the output of the driving unit is connected to the gate of the transistor Q2 to control the on and off of the transistor Q2; VDD is connected to the drain of the transistor Q3 in the Q3 driving module to charge the external capacitor CBST, and at the same time, the gate of the transistor Q1 in the Q1 driving module is controlled to be on or off by the output of one or more driving units such as DR5 and DR6, and the power supply of the Q3 driving module is provided by the external capacitor CBST of the external pin BST (the peripheral pin that provides CBST energy); the external pin BST is connected to one or more driving units (DR3 and DR4, etc.
  • transistors Q1 and Q2 are high-power transistors integrated on the chip, the cost of high-gate-voltage-driven transistors is not accepted by the market.
  • the high-power transistors controlled by the gate voltage of the mainstream process can only be driven by a low-voltage power supply, and therefore cannot be directly driven by the power supply of the external high-voltage power supply VIN. Therefore, an additional low-voltage power supply VDD is required for the on-chip driver stage.
  • VDD provides power to the transistor Q2 driver module and is controlled by the CLKLG signal to drive transistor Q2 to work.
  • VDD can continue to charge the external CBST capacitor through the pin BST by default through the body diode path of transistor Q3.
  • transistor Q3 can also be controlled by CLKBT (internal Q 3 drive module and the drive signal) signal control, turn on the transistor Q3 when the external capacitor CBST needs to be charged, so that it has a small on-resistance, enhance its conduction ability and quickly fill the external capacitor CBST with energy; the energy of CBST provides power to the Q1 drive module through the pin BST, and is controlled by the CLKUG signal to drive the transistor Q1 to work. Due to the existence of the external capacitor CBST, the voltage across the capacitor cannot change suddenly.
  • CLKBT internal Q 3 drive module and the drive signal
  • the transistor Q1 After the CLKUG signal turns on the transistor Q1, the transistor Q1 will not be turned off due to the increase of the voltage of the switch drive output signal pin SW, but will maintain a fixed voltage difference with the pin BST as the switch drive output signal pin SW rises, so that the transistor Q1 can work normally.
  • the pre-stage drive unit (DR1 and DR2, etc.) needs to provide a strong current to charge the gate capacitance of the transistor Q2 to turn it on. Therefore, a larger pre-stage drive unit is required, and a large pre-stage drive unit requires a strong power supply. Therefore, it is usually necessary to add additional pins of an external low-voltage power supply for on-chip use, which increases the restrictions on the power supply in the application scenario, and the additional pins are contrary to the current trend of high integration.
  • FIG 2 is a schematic diagram of a driving stage power supply circuit of another DCDC buck device in the prior art.
  • the circuit includes a Q1 driving module, a Q2 driving module, a Q3 driving module and an LDO module.
  • the positive end of the operational amplifier OP of the LDO module receives the VREF reference voltage signal generated internally, and the negative end receives the feedback signal FB between the resistor R1 and the resistor R2.
  • the output end of the operational amplifier OP is connected to the gate of the transistor Q4, and the voltage output of OP is adjusted according to the feedback signal FB.
  • the drain of the transistor Q4 is connected to the high-voltage power supply VIN, the source end is connected to R1, and a low-voltage power supply VDD with strong load capacity is output.
  • VDD is connected to an external capacitor CVDD via an external pin;
  • VDD is connected to one or more drive units (DR1 and DR2, etc.) in the transistor Q2 drive module to provide power for it, and the output of the drive unit is connected to the gate of the transistor Q2 to control the on and off of the transistor Q2;
  • VDD is connected to the drain of the transistor Q3 to charge the external capacitor CBST, and at the same time, the gate of the transistor Q1 is controlled to be on or off by the output of one or more drive units (DR5 and DR6, etc.), and the power supply of the Q3 drive module is provided by the capacitor CBST connected to the external BST;
  • the external pin BST is connected to one or more drive units (DR3 and DR4, etc.) in the Q1 drive module to provide power for it, and the output of the drive unit is connected to the gate of the transistor Q1 to control the on and off of the transistor Q1.
  • Transistor Q1 and transistor Q2 are high-power transistors integrated on the chip. Because the cost of transistors driven by high gate voltage is not accepted by the market, the high-power transistors controlled gate voltage of the mainstream process can only be driven by a low-voltage power supply, and therefore cannot be directly driven by the power supply of the external high-voltage power supply VIN. Therefore, an internal LDO module is required to provide a low-voltage power supply VDD for the on-chip driver stage.
  • VDD provides power to the Q2 driver module and is controlled by the CLKLG signal to drive transistor Q2 to work; when the voltage of the external capacitor CBST is low, VDD can continue to charge the external CBST capacitor through the pin BST by default through the body diode path of transistor Q3.
  • transistor Q3 can also be controlled by the CLKBT signal.
  • transistor Q3 When the external capacitor CBST needs to be charged, transistor Q3 is turned on to make it have a small on-resistance, enhance its conduction ability and quickly fill CBST with energy; the energy of the external capacitor CBST provides power to the Q1 drive module through the pin BST, and is controlled by the CLKUG signal to drive transistor Q1 to work. Due to the existence of the external capacitor CBST, the voltage across the capacitor cannot change suddenly. After the CLKUG signal turns on transistor Q1, transistor Q1 will not be turned off due to the increase of SW voltage, but will maintain a fixed voltage difference with the increase of SW so that transistor Q1 can work normally.
  • the transistor Q2 of the step-down device usually has a large current driving capability and a huge gate parasitic capacitance
  • the pre-stage driving unit for example, DR1 and DR2, etc.
  • the LDO module usually still needs to increase the off-chip large capacitor CVDD to provide instantaneous energy to the driving unit, thereby additionally increasing the cost of external application components and the chip power pins, which is contrary to the current trend of high integration.
  • the present invention proposes a driving stage power supply circuit of a DCDC step-down device, which can meet the power demand of the front-stage driving unit at the moment when the transistor Q2 is turned on without the need for additional external power supply and external power supply capacitor, thereby ensuring its normal operation.
  • a driving stage power supply circuit of a DCDC step-down device comprising a pin BST for providing energy to an external capacitor CBST, a pin VIN for providing a high voltage power supply, a switch drive output signal pin SW and a ground terminal GND, wherein the external capacitor CBST is connected between the pin BST and the pin SW; and
  • a Q1 driving module comprising one or more first driving units and a transistor Q1, wherein the drain of the transistor Q1 is connected to the pin VIN, the signal CLKUG is a driving signal of the Q1 driving module, and the first driving unit receives energy from the pin BST;
  • a Q2 driving module includes one or more second driving units and a transistor Q2, wherein the drain of the transistor Q2 and the source of the transistor Q1 are connected to the pin SW, and the signal CLKLG is a driving signal of the Q2 driving module;
  • a Q3 driving module includes one or more third driving units and a transistor Q3, wherein the source of the transistor Q3 is connected to the pin BST, and the third driving unit receives energy from the pin BST; a signal CLKBT is a driving signal of the Q3 driving module;
  • a Q2 driving acceleration module is used to receive a CLKLG signal to enhance the driving capability of the Q2 driving module to accelerate the opening of the Q2 transistor; it includes one or more fourth driving units and a transistor Q6, the fourth driving unit is used to drive the opening of the transistor Q6; the transistor Q6 is used to obtain energy from the external high-voltage power supply VIN to accelerate the opening of the transistor Q2;
  • the LDO module includes an operational amplifier OP, a transistor Q4, a resistor R1, a resistor R2 and a capacitor C1; the positive end of the operational amplifier OP receives an internally generated VREF reference voltage signal, and the negative end receives a feedback signal FB between the resistor R1 and the resistor R2; the output end of the operational amplifier OP is connected to the gate of the transistor Q4, and the voltage output by the operational amplifier OP is adjusted according to the feedback signal FB; the drain of the transistor Q4 is connected to the high-voltage power supply VIN; the source end of the transistor Q4, one end of the resistor R1 and one end of the capacitor C1 form a connection end, and a low-voltage power supply VDD1 is output at the connection end; the low-voltage power supply VD D1 is connected to the drain end of the transistor Q3, and the fourth driving unit receives energy from the low-voltage power supply VDD1; the low-voltage power supply VDD1 is connected to one or more second driving units in the Q2 driving
  • the transistor Q3 When the external capacitor CBST needs to be charged, the transistor Q3 is turned on to charge the external capacitor CBST with energy.
  • the energy of the external capacitor CBST provides power to the Q1 driving module through the pin BST.
  • the CLKUG signal turns on the transistor Q1, and the voltage of the pin SW rises to maintain a fixed voltage difference with the pin BST to make the transistor Q1 work.
  • the low-voltage power supply VDD1 provides power to the Q2 driving module and is controlled by the CLKLG signal to drive the transistor Q2 to work.
  • the number of the first driving unit, the second driving unit, the third driving unit and the fourth driving unit is two each connected in series.
  • the driving-stage power supply circuit of the DCDC step-down device is manufactured in the form of a chip, and the capacitor C1 is an on-chip capacitor.
  • a driving stage power supply circuit of a DCDC step-down device comprising a pin BST for providing energy to an external capacitor CBST, a pin VIN for providing a high voltage power supply, a switch drive output signal pin SW and a ground terminal GND, wherein the external capacitor CBST is connected between the pin BST and the pin SW; and
  • a Q1 driving module comprising one or more first driving units and a transistor Q1, wherein the drain of the transistor Q1 is connected to the pin VIN, the signal CLKUG is a driving signal of the Q1 driving module, and the first driving unit receives energy from the pin BST;
  • a Q2 driving module includes one or more second driving units and a transistor Q2, wherein the drain of the transistor Q2 and the source of the transistor Q1 are connected to the pin SW, and the signal CLKLG is a driving signal of the Q2 driving module;
  • a Q3 driving module includes one or more third driving units and a transistor Q3, wherein the source of the transistor Q3 is connected to the pin BST, and the third driving unit receives energy from the pin BST; a signal CLKBT is a driving signal of the Q3 driving module;
  • a Q2 driving acceleration module is used to receive a CLKLG signal to enhance the driving capability of the Q2 driving module to accelerate the opening of the Q2 transistor; it includes one or more fourth driving units and a transistor Q6, the fourth driving unit is used to drive the opening of the transistor Q6; the transistor Q6 is used to obtain energy from the external high-voltage power supply VIN to accelerate the opening of the transistor Q2;
  • the LDO module includes an operational amplifier OP, a transistor Q4, a resistor R1, a resistor R2, a capacitor C1 and a capacitor C2; the positive end of the operational amplifier OP receives an internally generated VREF reference voltage signal, and the negative end receives a feedback signal FB between the resistor R1 and the resistor R2; the output end of the operational amplifier OP is connected to the gates of the transistor Q4 and the transistor Q5, and the voltage output by the operational amplifier OP is adjusted according to the feedback signal FB; the drain of the transistor Q4 is connected to the high-voltage power supply VIN; the source end of the transistor Q4, one end of the resistor R1 and one end of the capacitor C1 form a connection end, and a low-voltage power supply VDD1 is output at the connection end; the The drain is connected to the high voltage power supply VIN, the capacitor C2 is connected in series between the source terminal of the transistor Q5 and the ground terminal GND, and a low voltage power supply VDD2 is output at the connection terminal; the
  • the transistor Q3 can also be controlled by the CLKBT signal to turn on the Q3 transistor when the external capacitor CBST is charged to fill the external capacitor CBST with energy;
  • the energy of the external capacitor CBST provides power to the Q1 driver module through the BST pin, which is controlled by the CLKUG signal to drive the transistor Q1 to work, and the voltage of the pin SW rises to maintain a fixed voltage difference with the pin BST to make the transistor Q1 work;
  • the low voltage power supply VDD1 provides power to the Q2 driver module, which is controlled by the CLKLG signal to drive the transistor Q2 to work.
  • the driving stage power supply circuit of the DCDC step-down device in the present invention enhances the driving capability of the Q2 driving module by reasonably allocating the path of the LDO output power supply VDD and adding a Q2 driving acceleration module, thereby reducing the size of the front-stage driving unit, reducing the demand for instantaneous power supply energy, and accelerating the turning on of the transistor Q2; that is, the normal driving operation of the Q2 transistor can be ensured without the need for an external large capacitor off-chip and without the need for an on-chip integrated ultra-large capacitor or an external power supply.
  • FIG. 1 is a schematic diagram of a driving stage power supply circuit of a DCDC step-down device in the prior art.
  • FIG. 2 is a schematic diagram of a driving stage power supply circuit of another DCDC step-down device in the prior art.
  • FIG. 3 is a schematic diagram showing a preferred embodiment of a driving stage power supply circuit of a DCDC step-down device of the present invention.
  • FIG. 4 is a schematic diagram showing another preferred embodiment of a driving stage power supply circuit of a DCDC step-down device of the present invention.
  • FIG. 5 is a schematic diagram showing waveforms of the low voltage power supply VDD1 in Embodiment 1 of the present invention and the low voltage power supplies VDD1 and VDD2 in Embodiment 2.
  • the biggest difference between the present invention and the prior art is that in the driving-stage power supply circuit of the DCDC step-down device of the present invention, by reasonably allocating the path of the LDO module output power supply VDD and adding a Q2 driving acceleration module, the normal driving transistor Q2 operation can be ensured without the need for an external large capacitor and without the need for an on-chip integrated ultra-large capacitor or an external power supply.
  • the driving stage power supply circuit of the DCDC step-down device of the present invention is described in detail below through two specific embodiments.
  • the driving-stage power supply circuit of the DCDC step-down device includes a pin BST for providing energy to an external capacitor CBST, a pin VIN for providing a high-voltage power supply, a switch drive output signal pin SW and a ground terminal GND, wherein the external capacitor CBST is connected between the pin BST and the pin SW; and an LDO module, a Q1 driving module, a Q2 driving module, a Q3 driving module, a Q2 driving acceleration module and a capacitor C1.
  • the Q1 driving module may include one or more first driving units (for example, two first driving units DR3 and DR4 connected in series) and a transistor Q1, the drain of the transistor Q1 is connected to the pin VIN, the signal CLKUG is the driving signal of the Q1 driving module, and the first driving unit receives energy from the pin BST.
  • first driving units for example, two first driving units DR3 and DR4 connected in series
  • the drain of the transistor Q1 is connected to the pin VIN
  • the signal CLKUG is the driving signal of the Q1 driving module
  • the first driving unit receives energy from the pin BST.
  • the Q2 driving module may include one or more second driving units and a transistor Q2 (for example, two second driving units DR1 and DR2 connected in series in sequence), the drain of the transistor Q2 and the source of the transistor Q1 are connected to the pin SW, and the signal CLKLG is the driving signal of the Q2 driving module;
  • the Q3 driving module includes one or more third driving units and a transistor Q3, the source of the transistor Q3 is connected to the pin BST, and the third driving unit receives energy from the pin BST;
  • the signal CLKBT is the driving signal of the Q3 driving module.
  • the newly added Q2 driving acceleration module is a module for receiving a CLKLG signal to enhance the driving capability of the Q2 driving module, that is, it can accelerate the turning on of the transistor Q2.
  • the Q2 drive acceleration module is used to receive a CLKLG signal to enhance the driving capability of the Q2 drive module to accelerate the turning on of the Q2 transistor; it may include one or more fourth drive units and a transistor Q6, wherein the fourth drive unit is used to drive the turning on of the transistor Q6; the transistor Q6 is used to obtain energy from the external high-voltage power supply VIN to accelerate the turning on of the transistor Q2.
  • the Q2 drive acceleration module may include one or more fourth drive units (for example, two second drive units DR7 and DR8 connected in series in sequence) and a transistor Q6; one or more fourth drive units are used to drive the transistor Q6 to turn on; the transistor Q6 is used to obtain energy from an external high-voltage power supply VIN to accelerate the turning on of the transistor Q2.
  • fourth drive units for example, two second drive units DR7 and DR8 connected in series in sequence
  • the transistor Q6 is used to obtain energy from an external high-voltage power supply VIN to accelerate the turning on of the transistor Q2.
  • the LDO module pair unit may include an operational amplifier OP, a transistor Q4, a resistor R1, a resistor R2 and a capacitor C1; the positive end of the operational amplifier OP receives an internally generated VREF reference voltage signal, and the negative end receives a feedback signal FB between the resistor R1 and the resistor R2; the output end of the operational amplifier OP is connected to the gate of the transistor Q4, and the voltage output by the operational amplifier OP is adjusted according to the feedback signal FB; the drain of the transistor Q4 is connected to the high voltage power supply VIN; the source end of the transistor Q4, one end of the resistor R1 and one end of the capacitor C1 form a connection end, and a low voltage power supply VDD1 is output at the connection end; the low voltage power supply VDD1 is connected to the drain end of the transistor Q3, and the fourth driving unit receives energy from the low voltage power supply VDD1; the low voltage power supply VDD1 is connected to one or more second driving units in the Q2
  • the source of the transistor Q2, the other end of the resistor R2 and the other end of the capacitor are connected to the ground GND.
  • the output of the fourth driving unit is connected to the base of the transistor Q6 to control the on and off of the transistor Q6.
  • the collector of the transistor Q6 is connected to the high-voltage power supply VIN, and the emitter is connected to the gate of the transistor Q2.
  • the low-voltage power supply VDD1 is connected to the drain of the transistor Q3 to charge the external capacitor CBST.
  • the gate of the transistor Q1 is controlled to be on or off by the output of one or more first driving units.
  • the power supply of the Q3 driving module is provided by the external capacitor CBST.
  • the external pin BST is connected to the output of one or more first driving units in the Q1 driving module to provide power for it.
  • the output of the one or more first driving units is connected to the gate of the transistor Q1 to control the on and off of the transistor Q1.
  • the LDO module provides a low-voltage power supply VDD1 for use by each driving stage in the chip (circuit); when the voltage of the external capacitor CBST is low, the low-voltage power supply VDD1 can continue to charge the external capacitor CBST through the pin BST by default through the body diode path of the transistor Q3 until the external capacitor CBST is fully charged; at the same time, the transistor Q3 can also be controlled by the CLKBT signal, and the transistor Q3 is turned on when the CBST needs to be charged, so that it has a small on-resistance, thereby enhancing its conduction ability and quickly filling the external capacitor CBST with energy; the energy of the external capacitor CBST provides power to the Q1 driver module through the pin BST, which is controlled by the CLKUG signal and can be used to drive the transistor Q1 to work.
  • the transistor Q1 Due to the existence of the external capacitor CBST and the characteristic that the voltage across the external capacitor CBST cannot change suddenly, after the CLKUG signal turns on the transistor Q1, the transistor Q1 will not be turned off due to the increase of the voltage of the switch drive output signal pin SW, but the fixed voltage difference with the pin BST will be maintained as the switch drive output signal pin SW rises, so that the transistor Q1 can work normally; the low-voltage power supply VDD1 provides power to the Q2 drive module, is controlled by the CLKLG signal, and can be used to drive the transistor Q2 to work.
  • the LDO module integrated in the circuit cannot use a huge capacitor to provide instantaneous energy to the pre-stage driver unit; that is, the VDD1 provided by the LDO module output alone cannot instantly meet the power supply requirements of the large-sized pre-stage driver unit (for example, two second driver units DR1 and DR2 connected in series) that turns on the transistor Q2. If the large-sized pre-stage driver unit is still used, the entire low-voltage power supply VDD1 will drop suddenly, thereby affecting the voltage of other circuits for normal operation.
  • the present invention reduces the size of the front-stage driving unit to reduce the demand for instantaneous power energy.
  • a transistor Q2 acceleration module is added.
  • the transistor Q2 needs to be turned on, it can be controlled by the CLKLG signal to enable the fourth driving unit to turn on the transistor Q6.
  • the transistor Q6 can obtain energy from the external high-voltage power supply VIN to accelerate the rise of the gate voltage of the transistor Q2, which plays a role in accelerating the turning on of the transistor Q2.
  • it also solves the defect that the LDO module cannot turn on the transistor Q2 normally due to the insufficient power demand capacity of the front-stage driving unit at the moment when the transistor Q2 is turned on.
  • Figure 4 is a schematic diagram of another preferred embodiment of the driving stage power supply circuit of the DCDC buck device of the present invention.
  • the driving stage power supply circuit of the DCDC buck device includes an LDO module, a Q1 driving module, a Q2 driving module, a Q3 driving module and a Q2 driving acceleration module, a capacitor C1 and a capacitor C2.
  • the LDO module uses VREF as a reference and enables Q4 to generate a stable internal low-voltage power supply VDD according to the FB feedback point voltage; the Q1 drive module receives the CLKUG signal to drive the transistor Q1 to turn on or off; the Q2 drive module receives the CLKLG signal to drive the transistor Q2 to turn on or off; the Q3 drive module receives the CLKBT signal to drive the transistor Q3 to turn on or off.
  • the Q1 driving module may include one or more first driving units (for example, two first driving units DR3 and DR4 connected in series) and a transistor Q1, the drain of the transistor Q1 is connected to the pin VIN, the signal CLKUG is the driving signal of the Q1 driving module, and the first driving unit receives energy from the pin BST.
  • first driving units for example, two first driving units DR3 and DR4 connected in series
  • the drain of the transistor Q1 is connected to the pin VIN
  • the signal CLKUG is the driving signal of the Q1 driving module
  • the first driving unit receives energy from the pin BST.
  • the Q2 driving module may include one or more second driving units and a transistor Q2 (for example, two second driving units DR1 and DR2 connected in series in sequence), the drain of the transistor Q2 and the source of the transistor Q1 are connected to the pin SW, and the signal CLKLG is the driving signal of the Q2 driving module;
  • the Q3 driving module includes one or more third driving units and a transistor Q3, the source of the transistor Q3 is connected to the pin BST, and the third driving unit receives energy from the pin BST;
  • the signal CLKBT is the driving signal of the Q3 driving module.
  • the newly added Q2 driving acceleration module is a module for receiving a CLKLG signal to enhance the driving capability of the Q2 driving module, that is, it can accelerate the turning on of the transistor Q2.
  • the Q2 drive acceleration module may include one or more fourth drive units (for example, two fourth drive units DR7 and DR8 connected in series in sequence) and a transistor Q6; one or more drive units are used to drive the transistor Q6 to turn on; the transistor Q6 is used to obtain energy from an external high-voltage power supply VIN to accelerate the turning on of the transistor Q2.
  • fourth drive units for example, two fourth drive units DR7 and DR8 connected in series in sequence
  • the transistor Q6 is used to obtain energy from an external high-voltage power supply VIN to accelerate the turning on of the transistor Q2.
  • the Q2 driving acceleration module is used to receive the CLKLG signal to enhance the driving capability of the Q2 driving module to accelerate the turning on of the Q2 transistor; it may include one or more fourth driving units and a transistor Q6, the fourth driving unit is used to drive the turning on of the transistor Q6; the transistor Q6 is used to obtain energy from the external high-voltage power supply VIN to accelerate the turning on of the transistor Q2.
  • the Q2 drive acceleration module may include one or more fourth drive units (for example, two fourth drive units DR7 and DR8 connected in series in sequence) and a transistor Q6; one or more fourth drive units are used to drive the transistor Q6 to turn on; the transistor Q6 is used to obtain energy from an external high-voltage power supply VIN to accelerate the turning on of the transistor Q2.
  • fourth drive units for example, two fourth drive units DR7 and DR8 connected in series in sequence
  • the transistor Q6 is used to obtain energy from an external high-voltage power supply VIN to accelerate the turning on of the transistor Q2.
  • the LDO module may include an operational amplifier OP, a transistor Q4, a resistor R1, a resistor R2, a capacitor C1 and a capacitor C2; the positive end of the operational amplifier OP receives an internally generated VREF reference voltage signal, and the negative end receives a feedback signal FB between the resistor R1 and the resistor R2; the output end of the operational amplifier OP is connected to the gates of the transistor Q4 and the transistor Q5, and the voltage output by the operational amplifier OP is adjusted according to the feedback signal FB; the drain of the transistor Q4 is connected to the high voltage power supply VIN, the source end of the transistor Q4, one end of the resistor R1 and one end of the capacitor C1 form a connection end, and a low voltage power supply VDD1 is output at the connection end; the drain of the transistor Q5 is connected to the high voltage power supply VIN, the capacitor C2 is connected in series between the source end of the transistor Q5 and the ground end GND, and a low voltage power supply
  • FIG. 5 shows a waveform diagram of the low-voltage power supply VDD1 in Example 1 of the present invention and the low-voltage power supplies VDD1 and VDD2 in Example 2.
  • the LDO module outputs the low-voltage power supply VDD1 and provides energy to the second drive unit and the external CBST capacitor at the same time.
  • the second drive unit drives the transistor Q2 to turn on
  • the voltage value of the low-voltage power supply VDD1 will drop and then recover to rise.
  • the transistor Q3 is turned on and needs to charge the external capacitor CBST, the voltage value of the low-voltage power supply VDD1 will drop and then recover to rise. Therefore, this frequent power ripple noise on the low-voltage power supply VDD1 is very unfavorable to the stable operation of other circuit modules.
  • the output of the LDO module in Example 2 of the present invention can provide a low-voltage power supply VDD1 and a low-voltage power supply VDD2 for use by the driving unit in the circuit (chip), separate the power supply of the driving unit from the charging power supply for the external capacitor CBST, and stagger the moment when the transistor Q2 and the transistor Q3 are turned on respectively, causing the power drop, thereby reducing the mutual influence between the two.
  • the output of the LDO module provides low-voltage power supplies VDD1 and VDD2 for use by each driving stage in the chip (circuit), separates the power supply of the driving unit from the power supply for charging the peripheral capacitor CBST, and staggers the moment when the power supply drops when the transistor Q2 and the transistor Q3 are turned on, thereby reducing the mutual influence between the two.
  • the low-voltage power supply VDD2 can charge the external capacitor CBST through the pin BST by default through the body diode path of the transistor Q3 until the capacitor CBST is fully charged.
  • the transistor Q3 can also be controlled by the CLKBT signal to turn on the transistor Q3 when the external capacitor CBST needs to be charged, so that it has a small on-resistance, enhance its conduction ability and quickly fill the external capacitor CBST with energy; the energy of the external capacitor CBST provides power to the transistor Q1 drive module through the BST pin, which is controlled by the CLKUG signal and can be used to drive the transistor Q1 to work. Due to the existence of the external capacitor CBST, the voltage across the capacitor cannot change suddenly.
  • VDD1 provides power to the transistor Q2 drive module, which is controlled by the CLKLG signal and can be used to drive the transistor Q2 transistor to work.
  • the LDO integrated in the chip cannot use a huge capacitor to provide instantaneous energy to the pre-stage driver unit.
  • the VDD1 provided by the LDO output alone cannot instantly meet the power supply demand of the large-size pre-stage driver unit that turns on the transistor Q2. If the large-size pre-stage driver unit is still used, the entire VDD1 will drop suddenly instantly, thereby affecting the voltage of other circuits for normal operation.
  • the size of the front-stage driving unit is reduced to reduce the demand for instantaneous power energy.
  • a transistor Q2 acceleration module is added.
  • the transistor Q2 needs to be turned on, it can be controlled by the CLKLG signal so that the driving unit turns on the transistor Q6.
  • the transistor Q6 can obtain energy from the external high voltage VIN to accelerate the rise of the gate voltage of the transistor Q2, which plays a role in accelerating the turning on of the transistor Q2, and also solves the defect that the LDO module cannot turn on the transistor Q2 normally due to the insufficient power demand capacity of the front-stage driving unit at the moment when the transistor Q2 is turned on.

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Abstract

一种DCDC降压装置的驱动级供电电路，包括用于给外部电容CBST提供能量的引脚BST、提供高压电源的引脚VIN、开关驱动输出信号引脚SW和接地端GND，所述外部电容CBST连接在所述引脚BST和所述引脚SW之间，以及Q1驱动模块、Q2驱动模块、Q3驱动模块、Q2驱动加速模块和LDO模块。因此，本发明通过合理分配LDO输出电源VDD的路径以及增加Q2驱动加速模块，用以增强Q2驱动模块驱动能力，减小了前级驱动单元的尺寸，降低了对瞬间电源能量的需求，还可以加速晶体管Q2的开启，即在无需外挂片外大电容且无需片内集成超大电容或者外部电源的情况下亦可保证正常驱动Q2晶体管工作。

Description

一种DCDC降压装置的驱动级供电电路 技术领域
本发明属于集成电路DCDC降压装置领域，涉及一种DCDC降压装置的驱动级供电电路。
 背景技术
DCDC是指将一个固定的直流电压变换为可变的直流电压。将单一的高压输入电源转换成低电压电源的应用场景，相对于传统的降压装置，增加驱动级加速控制电路，可无需额外电源引脚的情况下满足驱动级电路的供电需求。DCDC降压装置的驱动级供电电路应用越来越广泛。
请参阅图1，图1所示为现有技术中DCDC降压装置的驱动级供电电路的示意图。如图1所示，该电路包括包含Q1驱动模块、Q2驱动模块和Q3驱动模块；该电路内部通过外部引脚VDD连接Q2驱动模块中的一个或多个驱动单元（DR1和DR2等）为其提供电源，驱动单元输出连接晶体管Q2栅极，控制晶体管Q2的开启关闭；VDD连接Q3驱动模块中的晶体管Q3的漏极给外部电容CBST充电，同时Q1驱动模块中的晶体管Q1的栅极受一个或多个的DR5和DR6等驱动单元输出控制其开启或关闭，Q3驱动模块的电源由外部引脚BST（提供CBST能量的外围引脚）的外部电容CBST提供；外部引脚BST连接Q1驱动模块中的一个或多个驱动单元（DR3和DR4等）为其提供电源，驱动单元输出连接晶体管Q1栅极，控制晶体管Q1的开启关闭。
由于晶体管Q1和晶体管Q2为片内集成大功率晶体管，因高栅压驱动的晶体管成本使用方面不被市场所接收，主流工艺的片内大功率晶体管受控栅压只能使用低压电源进行驱动，因而无法直接使用外部高压电源VIN的电源进行驱动，因此需要外部额外提供一个低压电源VDD供片内驱动级使用，VDD给晶体管Q2驱动模块提供电源，受CLKLG信号控制，可用以驱动晶体管Q2工作；当外部电容CBST的电压较低时，VDD可通过晶体管Q3的体二极管通路默认会持续给经引脚BST给外部CBST电容进行充电，同时晶体管Q3亦可受CLKBT（内部Q3驱动模块的而驱动信号）信号控制，在需要给外部电容CBST充电的时刻打开晶体管Q3，使其有一个小导通阻抗，增强其导通能力进而快速的给外部电容CBST充满能量；CBST的能量经过引脚BST给Q1驱动模块提供电源，受CLKUG信号控制，可用以驱动晶体管Q1工作，由于外部电容CBST的存在，电容两端电压无法突变的特性，CLKUG信号将晶体管Q1打开后不会因为开关驱动输出信号引脚SW电压的上升使得晶体管Q1关闭，而会随着开关驱动输出信号引脚SW的上升保持着与所述引脚BST固定的电压差使得晶体管Q1能够正常工作。
然而，由于降压装置的晶体管Q2通常有着较大的电流驱动能力，栅极寄生电容是巨大的，当晶体管Q2开启瞬间，需要前级驱动单元（DR1和DR2等）的瞬间能提供强劲电流给晶体管Q2栅极电容充电使其开启，因此就需要较大尺寸的前级驱动单元，而大尺寸的前级驱动单元就需要强劲的电源供给，所以通常需要额外增加外部低压电源的引脚供片内使用，增加了应用场景对电源的限制，并且额外增加的引脚跟当下高集成化的趋势是相违背的。
请参阅图2，图2为现有技术中另一DCDC降压装置的驱动级供电电路的示意图。如图2所示，该电路包含Q1驱动模块、Q2驱动模块、Q3驱动模块和LDO模块。
LDO模块的运算放大器OP正端接收内部产生的VREF参考电压信号，负端接收电阻R1和电阻R2之间的反馈信号FB，运算放大器OP的输出端连接晶体管Q4的栅极，根据反馈信号FB调节OP输出的电压大小，晶体管Q4漏极连接高压电源VIN，源端连接R1，并输出一带负载能力强劲的低压电源VDD，VDD经由外部引脚连接一外部电容CVDD；VDD连接晶体管Q2驱动模块中的一个或多个驱动单元（DR1和DR2等）为其提供电源，驱动单元输出连接晶体管Q2栅极，控制晶体管Q2的开启关闭；VDD连接晶体管Q3漏极给外部电容CBST充电，同时晶体管Q1的栅极受一个或多个驱动单元（DR5和DR6等）输出控制其开启或关闭，Q3驱动模块电源由外部连接BST的电容CBST提供；外部引脚BST连接Q1驱动模块中的一个或多个驱动单元（DR3和DR4等）为其提供电源，驱动单元输出连接晶体管Q1栅极，控制晶体管Q1的开启关闭。
晶体管Q1和晶体管Q2为片内集成大功率晶体管，因高栅压驱动的晶体管成本使用方面不被市场所接收，主流工艺的片内大功率晶体管受控栅压只能使用低压电源进行驱动，因而无法直接使用外部高压电源VIN的电源进行驱动，因此需要内部LDO模块提供一个低压电源VDD供片内驱动级使用，VDD给Q2驱动模块提供电源，受CLKLG信号控制，可用以驱动晶体管Q2工作；当外部电容CBST电压较低时，VDD可通过晶体管Q3的体二极管通路默认会持续给经引脚BST给外部CBST电容进行充电，同时晶体管Q3亦可受CLKBT信号控制，在需要给外部电容CBST充电的时刻打开晶体管Q3，使其有一个小导通阻抗，增强其导通能力进而快速的给CBST充满能量；外部电容CBST的能量经过引脚BST给Q1驱动模块提供电源，受CLKUG信号控制，可用以驱动晶体管Q1工作，由于外部电容CBST的存在，电容两端电压无法突变的特性，CLKUG信号将晶体管Q1打开后不会因为SW电压的上升使得晶体管Q1关闭，而会随着SW的上升保持着固定的电压差使得晶体管Q1能够正常工作。
然而，由于降压装置的晶体管Q2通常有着较大的电流驱动能力，栅极寄生电容是巨大的，当晶体管Q2开启瞬间，需要前级驱动单元（例如，DR1和DR2等）瞬间能提供强劲电流给晶体管Q2栅极电容充电使其开启，因此就需要较大尺寸的前级驱动单元，而大尺寸的前级驱动单元就需要强劲的电源供给，虽然解决了额外的外部低压电源的应用限制，但是通常LDO模块仍需要增加片外大电容CVDD给驱动单元提供瞬间的能量，因此额外增加了外部应用元器件的成本以及芯片电源引脚，跟当下高集成化的趋势是相违背的。
 发明内容
为解决的上述技术问题，本发明提出一种DCDC降压装置的驱动级供电电路，其在无需额外增加外部电源以及外挂电源电容的情况下，亦可满足晶体管Q2开启瞬间前级驱动单元对电源的需求，保证其正常工作。
为实现上述目的，本发明的技术方案如下：
一种DCDC降压装置的驱动级供电电路，其包括用于给外部电容CBST提供能量的引脚BST、提供高压电源的引脚VIN、开关驱动输出信号引脚SW和接地端GND，所述外部电容CBST连接在所述引脚BST和所述引脚SW之间；以及
Q1驱动模块，包括一个或多个第一驱动单元和晶体管Q1，所述晶体管Q1的漏极接所述引脚VIN，信号CLKUG为所述Q1驱动模块的驱动信号，所述第一驱动单元从所述引脚BST接收能量；
Q2驱动模块，包括一个或多个第二驱动单元和晶体管Q2，所述晶体管Q2漏极和晶体管Q1的源极连接所述引脚SW，信号CLKLG为所述Q2驱动模块的驱动信号；
Q3驱动模块，包括一个或多个第三驱动单元和晶体管Q3，所述晶体管Q3的源极接所述引脚BST，所述第三驱动单元从所述引脚BST接收能量；信号CLKBT为所述Q3驱动模块的驱动信号；
Q2驱动加速模块，用于接收CLKLG信号用以增强Q2驱动模块的驱动能力，以加速Q2晶体管的开启；其包括一个或多个第四驱动单元和三极管Q6，所述第四驱动单元用以驱动所述三极管Q6的开启；所述三极管Q6用以从所述外部高压电源VIN获取能量加速晶体管Q2的开启；
LDO模块，包括运算放大器OP、晶体管Q4、电阻R1、电阻R2和电容C1；所述运算放大器OP正端接收内部产生的VREF参考电压信号，负端接收电阻R1和电阻R2之间的反馈信号FB，所述运算放大器OP的输出端连接晶体管Q4的栅极，根据反馈信号FB调节运算放大器OP输出的电压大小，所述晶体管Q4的漏极连接所述高压电源VIN，所述晶体管Q4的源端、所述电阻R1的一端和电容C1的一端形成连接端，并在所述连接端输出一低压电源VDD1；所述低压电源VDD1连接所述晶体管Q3的漏端，所述第四驱动单元从所述低压电源VDD1接收能量；所述低压电源VDD1连接Q2驱动模块中的一个或多个第二驱动单元为其提供电源，所述第二驱动单元输出连接晶体管Q2的栅极，控制所述晶体管Q2的开启关闭，晶体管Q2的源极、电阻R2的另一端和电容的另一端连接地端GND；所述第四驱动单元输出连接所述三极管Q6的基极，控制所述三级管Q6的开启关闭，所述三极管Q6的集电极连接所述高压电源VIN，发射极连接晶体管Q2的栅极；所述低压电源VDD1连接晶体管Q3漏极给所述外部电容CBST充电；所述Q3驱动模块的电源由所述外部电容CBST提供；所述外部引脚BST连接Q1驱动模块中的一个或多个第一驱动单元输出为其提供电源，所述一个或多个第一驱动单元的输出连接晶体管Q1的栅极，控制所述晶体管Q1的开启关闭；当所述外部电容CBST的电压较低时，所述低压电源VDD1可通过晶体管Q3持续给经所述引脚BST给外部所述外部电容CBST进行充电，直至所述外部电容CBST充满，同时所述晶体管Q3亦受所述CLKBT信号控制，在需要给所述外部电容CBST充电的时刻打开所述晶体管Q3，给所述外部电容CBST充满能量；所述外部电容CBST的能量经过所述引脚BST给Q1驱动模块提供电源，受所述CLKUG信号控制，所述CLKUG信号将所述晶体管Q1打开，所述引脚SW的电压上升保持着与所述引脚BST固定的电压差使所述晶体管Q1工作；所述低压电源VDD1给所述Q2驱动模块提供电源，受所述CLKLG信号控制，以驱动所述晶体管Q2工作。
进一步地，所第一驱动单元、第二驱动单元、第三驱动单元和第四驱动单元的数量均为依次串接的两个。
进一步地，所述的DCDC降压装置的驱动级供电电路以芯片为成品，所述电容C1为片内电容。
为实现上述目的，本发明又一技术方案如下：
一种DCDC降压装置的驱动级供电电路，其包括用于给外部电容CBST提供能量的引脚BST、提供高压电源的引脚VIN、开关驱动输出信号引脚SW和接地端GND，所述外部电容CBST连接在所述引脚BST和所述引脚SW之间；以及
Q1驱动模块，包括一个或多个第一驱动单元和晶体管Q1，所述晶体管Q1的漏极接所述引脚VIN，信号CLKUG为所述Q1驱动模块的驱动信号，所述第一驱动单元从所述引脚BST接收能量；
Q2驱动模块，包括一个或多个第二驱动单元和晶体管Q2，所述晶体管Q2漏极和晶体管Q1的源极连接所述引脚SW，信号CLKLG为所述Q2驱动模块的驱动信号；
Q3驱动模块，包括一个或多个第三驱动单元和晶体管Q3，所述晶体管Q3的源极接所述引脚BST，所述第三驱动单元从所述引脚BST接收能量；信号CLKBT为所述Q3驱动模块的驱动信号；
Q2驱动加速模块，用于接收CLKLG信号用以增强Q2驱动模块的驱动能力，以加速Q2晶体管的开启；其包括一个或多个第四驱动单元和三极管Q6，所述第四驱动单元用以驱动所述三极管Q6的开启；所述三极管Q6用以从所述外部高压电源VIN获取能量加速晶体管Q2的开启；
LDO模块，包括运算放大器OP、晶体管Q4、电阻R1、电阻R2、电容C1和电容C2；所述运算放大器OP正端接收内部产生的VREF参考电压信号，负端接收电阻R1和电阻R2之间的反馈信号FB，所述运算放大器OP的输出端连接晶体管Q4和晶体管Q5的栅极，根据反馈信号FB调节运算放大器OP输出的电压大小，所述晶体管Q4的漏极连接所述高压电源VIN，所述晶体管Q4的源端、所述电阻R1的一端和电容C1的一端形成连接端，并在所述连接端输出一低压电源VDD1；所述晶体管Q5的漏极连接所述高压电源VIN，所述电容C2串接在所述晶体管Q5的源端和接地端GND之间，并在所述连接端输出一低压电源VDD2；所述低压电源VDD1连接Q2驱动模块中的一个或多个第二驱动单元为其提供电源，所述第二驱动单元的输出连接所述晶体管Q2栅极，控制所述晶体管Q2的开启关闭；所述低压电源VDD1连接Q2驱动加速模块中的一个或多个第二驱动单元为其提供电源，所述第四驱动单元输出连接所述三极管Q6的基极，控制所述三级管Q6的开启关闭，所述三极管Q6的集电极连接所述高压电源VIN，所述三极管Q6的发射极连接晶体管Q2的栅极；所述低压电源VDD2连接晶体管Q3漏极给所述外部电容CBST充电；所述Q3驱动模块的电源由所述外部电容CBST提供；所述外部引脚BST连接所述Q1驱动模块中的一个或多个第一驱动单元输出为其提供电源，所述一个或多个第一驱动单元的输出连接晶体管Q1的栅极，控制所述晶体管Q1的开启关闭；当所述外部电容CBST的电压较低时，所述低压电源VDD1可通过晶体管Q3持续给经所述引脚BST给所述外部电容CBST进行充电，直至所述外部电容CBST充满，同时所述晶体管Q3亦可受所述CLKBT信号控制，给所述外部电容CBST充电的时刻打开所述Q3晶体管，给所述外部电容CBST充满能量；所述外部电容CBST的能量经过所述BST引脚给所述Q1驱动模块提供电源，受所述CLKUG信号控制，以驱动所述晶体管Q1工作，所述引脚SW的电压上升保持着与所述引脚BST固定的电压差使所述晶体管Q1工作；所述低压电源VDD1给所述Q2驱动模块提供电源，受所述CLKLG信号控制，以驱动所述晶体管Q2工作。
从上述技术方案可以看出，本发明中的DCDC降压装置的驱动级供电电路，其通过合理分配LDO输出电源VDD的路径以及增加Q2驱动加速模块，用以增强Q2驱动模块驱动能力，减小了前级驱动单元的尺寸，降低了对瞬间电源能量的需求，还可以加速晶体管Q2的开启；即在无需外挂片外大电容且无需片内集成超大电容或者外部电源的情况下亦可保证正常驱动Q2晶体管工作。
 附图说明
图1所示为现有技术中DCDC降压装置的驱动级供电电路示意图
图2为现有技术中另一DCDC降压装置的驱动级供电电路的示意图。
图3所示为本发明DCDC降压装置的驱动级供电电路一较佳实施例的示意图
图4所示为本发明DCDC降压装置的驱动级供电电路另一较佳实施例的示意图
图5所示为本发明的实施例1低压电源VDD1和实施例2中低压电源VDD1与VDD2的波形示意图
 实施方式
下面结合附图3-4，对本发明的具体实施方式作进一步的详细说明。
需要说明的是，本发明与现有技术最大不同点为：在本发明的DCDC降压装置的驱动级供电电路中，通过合理分配LDO模块输出电源VDD的路径以及增加Q2驱动加速模块，在无需外挂片外大电容且无需片内集成超大电容或者外部电源的情况下亦可保证正常驱动晶体管Q2工作。
下面通过两个具体的实施例，对本发明的DCDC降压装置的驱动级供电电路进行详细说明。
实施例一
请参阅图3，图3所示为本发明DCDC降压装置的驱动级供电电路一较佳实施例的示意图。如图3所示，该DCDC降压装置的驱动级供电电路，包括用于给外部电容CBST提供能量的引脚BST、提供高压电源的引脚VIN、开关驱动输出信号引脚SW和接地端GND，所述外部电容CBST连接在所述引脚BST和所述引脚SW之间；以及LDO模块、Q1驱动模块、Q2驱动模块、Q3驱动模块、Q2驱动加速模块和电容C1。
与现有技术相同，Q1驱动模块可以包括一个或多个第一驱动单元（例如两个依次串接的第一驱动单元DR3和DR4）和晶体管Q1，所述晶体管Q1的漏极接所述引脚VIN，信号CLKUG为所述Q1驱动模块的驱动信号，所述第一驱动单元从所述引脚BST接收能量。
Q2驱动模块可以包括一个或多个第二驱动单元和晶体管Q2（例如两个依次串接的第二驱动单元DR1和DR2），所述晶体管Q2漏极和晶体管Q1的源极连接所述引脚SW，信号CLKLG为所述Q2驱动模块的驱动信号；Q3驱动模块包括一个或多个第三驱动单元和晶体管Q3，所述晶体管Q3的源极接所述引脚BST，所述第三驱动单元从所述引脚BST接收能量；信号CLKBT为所述Q3驱动模块的驱动信号。
与现有技术不同是，新增加的Q2驱动加速模块是一种用于接收CLKLG信号用以增强Q2驱动模块驱动能力，即其可以加速晶体管Q2的开启。
在本发明的实施例中，Q2驱动加速模块用于接收CLKLG信号用以增强Q2驱动模块的驱动能力，以加速Q2晶体管的开启；其可以包括一个或多个第四驱动单元和三极管Q6，所述第四驱动单元用以驱动所述三极管Q6的开启；所述三极管Q6用以从所述外部高压电源VIN获取能量加速晶体管Q2的开启。
具体地，Q2驱动加速模块可以包括一个或者多个的第四驱动单元（例如两个依次串接的第二驱动单元DR7和DR8）和三极管Q6；一个或者多个的第四驱动单元，用以驱动三极管Q6的开启；三极管Q6用以从外部高压电源VIN获取能量加速晶体管Q2的开启。
并且，在本发明的实施例中，LDO模块对单元可以包括运算放大器OP、晶体管Q4、电阻R1、电阻R2和电容C1；所述运算放大器OP正端接收内部产生的VREF参考电压信号，负端接收电阻R1和电阻R2之间的反馈信号FB，所述运算放大器OP的输出端连接晶体管Q4的栅极，根据反馈信号FB调节运算放大器OP输出的电压大小，所述晶体管Q4的漏极连接所述高压电源VIN，所述晶体管Q4的源端、所述电阻R1的一端和电容C1的一端形成连接端，并在所述连接端输出一低压电源VDD1；所述低压电源VDD1连接所述晶体管Q3的漏端，所述第四驱动单元从所述低压电源VDD1接收能量；所述低压电源VDD1连接Q2驱动模块中的一个或多个第二驱动单元为其提供电源，所述第二驱动单元输出连接晶体管Q2的栅极，控制所述晶体管Q2的开启关闭，晶体管Q2的源极、电阻R2的另一端和电容的另一端连接地端GND；所述第四驱动单元输出连接所述三极管Q6的基极，控制所述三级管Q6的开启关闭，所述三极管Q6的集电极连接所述高压电源VIN，发射极连接晶体管Q2的栅极；所述低压电源VDD1连接晶体管Q3漏极给所述外部电容CBST充电，同时所述晶体管Q1的栅极受一个或多个第一驱动单元输出控制其开启或关闭；所述Q3驱动模块的电源由所述外部电容CBST提供；所述外部引脚BST连接Q1驱动模块中的一个或多个第一驱动单元输出为其提供电源，所述一个或多个第一驱动单元的输出连接晶体管Q1的栅极，控制所述晶体管Q1的开启关闭。
也就是说，LDO模块提供低压电源VDD1供芯片（电路）内各驱动级使用；当所述外部电容CBST的电压较低时，低压电源VDD1可通过晶体管Q3的体二极管通路默认会持续给经引脚BST给所述外部电容CBST的进行充电，直至所述外部电容CBST充满；同时晶体管Q3亦可受CLKBT信号控制，在需要给CBST充电的时刻打开晶体管Q3，使其有一个小导通阻抗，增强其导通能力进而快速的给所述外部电容CBST充满能量；所述外部电容CBST的能量经过引脚BST给Q1驱动模块提供电源，受CLKUG信号控制，可用以驱动晶体管Q1工作。
由于所述外部电容CBST的存在，所述外部电容CBST两端电压无法突变的特性，CLKUG信号将晶体管Q1打开后不会因为开关驱动输出信号引脚SW电压的上升使得晶体管Q1关闭，而会随着开关驱动输出信号引脚SW的上升保持着与所述引脚BST固定的电压差使得晶体管Q1能够正常工作；低压电源VDD1给Q2驱动模块提供电源，受CLKLG信号控制，可用以驱动晶体管Q2工作。
本领域技术人员清楚，电路（芯片）内集成的LDO模块无法使用巨大的电容来给前级驱动单元提供瞬间能量；也就是说，单由LDO模块输出提供的VDD1瞬间是无法满足使晶体管Q2开启的大尺寸前级驱动单元（例如两个依次串接的第二驱动单元DR1和DR2）电源需求，仍使用大尺寸前级驱动单元会导致整个低压电源VDD1的瞬间骤降，进而影响其他电路正常工作的电压。
因此，本发明通过减小前级驱动单元的尺寸，以降低对瞬间电源能量的需求，同时为保证晶体管Q2能够正常驱动开启，增加晶体管Q2加速模块，在晶体管Q2需要开启时，可以受CLKLG信号的控制，使第四驱动单元将三极管Q6打开，三极管Q6可以从外部高压电源VIN获取能量，加速晶体管Q2栅极电压的上升，即起到了加速晶体管Q2开启的作用，同时也解决了LDO模块在晶体管Q2开启瞬间前级驱动单元电源需求能力不足而导致晶体管Q2无法正常开启的缺陷。
实施例二
如图4所示，图4所示为本发明DCDC降压装置的驱动级供电电路另一较佳实施例的示意图。如图4所示，该DCDC降压装置的驱动级供电电路，包括LDO模块、Q1驱动模块、Q2驱动模块、Q3驱动模块和Q2驱动加速模块、电容C1和电容C2。
与现有技术相同，LDO模块以VREF作为参考，根据FB反馈点电压使Q4产生稳定的内部低压电源VDD；Q1驱动模块接收CLKUG信号用以驱动晶体管Q1的开启或者关闭；Q2驱动模块接收CLKLG信号用以驱动晶体管Q2的开启或者关闭；Q3驱动模块接收CLKBT信号用以驱动晶体管Q3的开启或者关闭。
与现有技术相同，Q1驱动模块可以包括一个或多个第一驱动单元（例如两个依次串接的第一驱动单元DR3和DR4）和晶体管Q1，所述晶体管Q1的漏极接所述引脚VIN，信号CLKUG为所述Q1驱动模块的驱动信号，所述第一驱动单元从所述引脚BST接收能量。
Q2驱动模块可以包括一个或多个第二驱动单元和晶体管Q2（例如两个依次串接的第二驱动单元DR1和DR2），所述晶体管Q2漏极和晶体管Q1的源极连接所述引脚SW，信号CLKLG为所述Q2驱动模块的驱动信号；Q3驱动模块包括一个或多个第三驱动单元和晶体管Q3，所述晶体管Q3的源极接所述引脚BST，所述第三驱动单元从所述引脚BST接收能量；信号CLKBT为所述Q3驱动模块的驱动信号。
与现有技术不同是，新增加的Q2驱动加速模块是一种用于接收CLKLG信号用以增强Q2驱动模块驱动能力，即其可以加速晶体管Q2的开启。
在本发明的实施例中，Q2驱动加速模块可以包括一个或者多个的第四驱动单元（例如两个依次串接的第四驱动单元DR7和DR8）和三极管Q6；一个或者多个的驱动单元用以驱动三极管Q6的开启；三极管Q6用以从外部高压电源VIN获取能量加速晶体管Q2的开启。
Q2驱动加速模块用于接收CLKLG信号用以增强Q2驱动模块的驱动能力，以加速Q2晶体管的开启；其可以包括一个或多个第四驱动单元和三极管Q6，所述第四驱动单元用以驱动所述三极管Q6的开启；所述三极管Q6用以从所述外部高压电源VIN获取能量加速晶体管Q2的开启。
具体地，Q2驱动加速模块可以包括一个或者多个的第四驱动单元（例如两个依次串接的第四驱动单元DR7和DR8）和三极管Q6；一个或者多个的第四驱动单元，用以驱动三极管Q6的开启；三极管Q6用以从外部高压电源VIN获取能量加速晶体管Q2的开启。
并且，在本发明的实施例中，LDO模块可以包括运算放大器OP、晶体管Q4、电阻R1、电阻R2、电容C1和电容C2；所述运算放大器OP正端接收内部产生的VREF参考电压信号，负端接收电阻R1和电阻R2之间的反馈信号FB，所述运算放大器OP的输出端连接晶体管Q4和晶体管Q5的栅极，根据反馈信号FB调节运算放大器OP输出的电压大小，所述晶体管Q4的漏极连接所述高压电源VIN，所述晶体管Q4的源端、所述电阻R1的一端和电容C1的一端形成连接端，并在所述连接端输出一低压电源VDD1；所述晶体管Q5的漏极连接所述高压电源VIN，所述电容C2串接在所述晶体管Q5的源端和接地端GND之间，并在所述连接端输出一低压电源VDD2；所述低压电源VDD1连接Q2驱动模块中的一个或多个第二驱动单元为其提供电源，所述第二驱动单元的输出连接所述晶体管Q2栅极，控制所述晶体管Q2的开启关闭；所述低压电源VDD1连接Q2驱动加速模块中的一个或多个第二驱动单元（例如两个依次串接的第二驱动单元DR1和DR2）为其提供电源，所述第四驱动单元输出连接所述三极管Q6的基极，控制所述三级管Q6的开启关闭，所述三极管Q6的集电极连接所述高压电源VIN，所述三极管Q6的发射极连接晶体管Q2的栅极；所述低压电源VDD2连接晶体管Q3漏极给所述外部电容CBST充电，同时所述晶体管Q1的栅极受一个或多个第一驱动单元（例如两个依次串接的第一驱动单元DR3和DR4）输出控制其开启或关闭；所述Q3驱动模块的电源由所述外部电容CBST提供；所述外部引脚BST连接所述Q1驱动模块中的一个或多个第一驱动单元输出为其提供电源，所述一个或多个第一驱动单元的输出连接晶体管Q1的栅极，控制所述晶体管Q1的开启关闭。
请查阅图5，图5所示为本发明的实施例1低压电源VDD1和实施例2中低压电源VDD1与VDD2的波形示意图。如图5所示，在本发明的实施例1中，LDO模块输出低压电源VDD1同时给第二驱动单元和外部CBST电容提供能量，当第二驱动单元驱动晶体管Q2开启瞬间，低压电源VDD1电压值会有一个跌落而后恢复上升，当晶体管Q3导通需要给外部电容CBST充电时，低压电源VDD1电压值会有一个跌落而后恢复上升，因此这种频繁的低压电源VDD1上的电源纹波噪声，非常不利于其他电路模块的稳定工作。
与实施例1相比，在本发明的实施例2中的LDO模块的输出，可以分别提供低压电源VDD1和低压电源VDD2供电路（芯片）内的驱动单元使用，将驱动单元的电源和给外部电容CBST的充电电源分开，错开了在晶体管Q2和晶体管Q3各自打开瞬间造成电源跌落的时刻，进而减少了造成对两者互相影响。
也就是说，在本发明的实施例2中，LDO模块的输出，分别提供低压电源VDD1和VDD2供芯片（电路）内各驱动级使用，将驱动单元的电源和给外围电容CBST充电电源分开，错开了在晶体管Q2和晶体管Q3各自打开瞬间造成电源跌落的时刻，进而减少了造成对两者互相影响。
当外部CBST电压较低时，低压电源VDD2可通过晶体管Q3的体二极管通路默认会持续给经引脚BST给外部电容CBST进行充电，直至部电容CBST充满，同时晶体管Q3亦可受CLKBT信号控制，在需要给外部电容CBST充电的时刻打开晶体管Q3，使其有一个小导通阻抗，增强其导通能力进而快速的给外部电容CBST充满能量；外部电容CBST的能量经过BST引脚给晶体管Q1驱动模块提供电源，受CLKUG信号控制，可用以驱动晶体管Q1工作，由于外部电容CBST的存在，电容两端电压无法突变的特性，CLKUG信号将晶体管Q1打开后不会因为SW电压的上升使得晶体管Q1关闭，而会随着SW的上升保持着与所述引脚BST固定的电压差使得晶体管Q1能够正常工作；VDD1给晶体管Q2驱动模块提供电源，受CLKLG信号控制，可用以驱动晶体管Q2晶体管工作。
本领域技术人员清楚，片内集成的LDO无法使用巨大的电容来给前级驱动单元提供瞬间能量，也就是说，单由LDO输出提供的VDD1瞬间是无法满足使晶体管Q2开启的大尺寸前级驱动单元电源需求的，仍使用大尺寸前级驱动单元会导致整个VDD1的瞬间骤降，进而影响其他电路正常工作的电压。
因此，在本发明的实施例中，通过减小前级驱动单元的尺寸，以降低对瞬间电源能量的需求，同时为保证晶体管Q2能够正常驱动开启，增加晶体管Q2加速模块，在晶体管Q2需要开启时，可以受CLKLG信号的控制，使驱动单元将三极管Q6打开，三极管Q6可以从外部高压VIN获取能量，加速晶体管Q2栅极电压的上升，即起到了加速晶体管Q2开启的作用，亦解决了LDO模块在晶体管Q2开启瞬间前级驱动单元电源需求能力不足而导致晶体管Q2无法正常开启的缺陷。
以上所述的仅为本发明的优选实施例，所述实施例并非用以限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明的保护范围内。 

Claims (6)

  1. 一种DCDC降压装置的驱动级供电电路，其特征在于，包括用于给外部电容CBST提供能量的引脚BST、提供高压电源的引脚VIN、开关驱动输出信号引脚SW和接地端GND，所述外部电容CBST连接在所述引脚BST和所述引脚SW之间；以及
    Q1驱动模块，包括一个或多个第一驱动单元和晶体管Q1，所述晶体管Q1的漏极接所述引脚VIN，信号CLKUG为所述Q1驱动模块的驱动信号，所述第一驱动单元从所述引脚BST接收能量；
    Q2驱动模块，包括一个或多个第二驱动单元和晶体管Q2，所述晶体管Q2漏极和晶体管Q1的源极连接所述引脚SW，信号CLKLG为所述Q2驱动模块的驱动信号；
    Q3驱动模块，包括一个或多个第三驱动单元和晶体管Q3，所述晶体管Q3的源极接所述引脚BST，所述第三驱动单元从所述引脚BST接收能量；信号CLKBT为所述Q3驱动模块的驱动信号；
    Q2驱动加速模块，用于接收CLKLG信号用以增强Q2驱动模块的驱动能力，以加速Q2晶体管的开启；其包括一个或多个第四驱动单元和三极管Q6，所述第四驱动单元用以驱动所述三极管Q6的开启；所述三极管Q6用以从所述外部高压电源VIN获取能量加速晶体管Q2的开启；
    LDO模块，包括运算放大器OP、晶体管Q4、电阻R1、电阻R2和电容C1；所述运算放大器OP正端接收内部产生的VREF参考电压信号，负端接收电阻R1和电阻R2之间的反馈信号FB，所述运算放大器OP的输出端连接晶体管Q4的栅极，根据反馈信号FB调节运算放大器OP输出的电压大小，所述晶体管Q4的漏极连接所述高压电源VIN，所述晶体管Q4的源端、所述电阻R1的一端和电容C1的一端形成连接端，并在所述连接端输出一低压电源VDD1；所述低压电源VDD1连接所述晶体管Q3的漏端，所述第四驱动单元从所述低压电源VDD1接收能量；所述低压电源VDD1连接Q2驱动模块中的一个或多个第二驱动单元为其提供电源，所述第二驱动单元输出连接晶体管Q2的栅极，控制所述晶体管Q2的开启关闭，晶体管Q2的源极、电阻R2的另一端和电容的另一端连接地端GND；所述第四驱动单元输出连接所述三极管Q6的基极，控制所述三级管Q6的开启关闭，所述三极管Q6的集电极连接所述高压电源VIN，发射极连接晶体管Q2的栅极；所述低压电源VDD1连接晶体管Q3漏极给所述外部电容CBST充电，所述Q3驱动模块的电源由所述外部电容CBST提供；所述外部引脚BST连接Q1驱动模块中的一个或多个第一驱动单元输出为其提供电源，所述一个或多个第一驱动单元的输出连接晶体管Q1的栅极，控制所述晶体管Q1的开启关闭；
    当所述外部电容CBST的电压较低时，所述低压电源VDD1可通过晶体管Q3持续给经所述引脚BST给外部所述外部电容CBST进行充电，直至所述外部电容CBST充满，同时所述晶体管Q3亦受所述CLKBT信号控制，在需要给所述外部电容CBST充电的时刻打开所述晶体管Q3，给所述外部电容CBST充满能量；所述外部电容CBST的能量经过所述引脚BST给Q1驱动模块提供电源，受所述CLKUG信号控制，所述CLKUG信号将所述晶体管Q1打开，所述引脚SW的电压上升保持着与所述引脚BST固定的电压差使所述晶体管Q1工作；所述低压电源VDD1给所述Q2驱动模块提供电源，受所述CLKLG信号控制，以驱动所述晶体管Q2工作。
  2. 根据权利要求1所述的DCDC降压装置的驱动级供电电路，其特征在于，所第一驱动单元、第二驱动单元、第三驱动单元和第四驱动单元的数量均为依次串接的两个。
  3. 根据权利要求1所述的DCDC降压装置的驱动级供电电路，其特征在于，所述的DCDC降压装置的驱动级供电电路以芯片为成品，所述电容C1为片内电容。
  4. 一种DCDC降压装置的驱动级供电电路，其特征在于，包括用于给外部电容CBST提供能量的引脚BST、提供高压电源的引脚VIN、开关驱动输出信号引脚SW和接地端GND，所述外部电容CBST连接在所述引脚BST和所述引脚SW之间；以及
    Q1驱动模块，包括一个或多个第一驱动单元和晶体管Q1，所述晶体管Q1的漏极接所述引脚VIN，信号CLKUG为所述Q1驱动模块的驱动信号，所述第一驱动单元从所述引脚BST接收能量；
    Q2驱动模块，包括一个或多个第二驱动单元和晶体管Q2，所述晶体管Q2漏极和晶体管Q1的源极连接所述引脚SW，信号CLKLG为所述Q2驱动模块的驱动信号；
    Q3驱动模块，包括一个或多个第三驱动单元和晶体管Q3，所述晶体管Q3的源极接所述引脚BST，所述第三驱动单元从所述引脚BST接收能量；信号CLKBT为所述Q3驱动模块的驱动信号；
    Q2驱动加速模块，用于接收CLKLG信号用以增强Q2驱动模块的驱动能力，以加速Q2晶体管的开启；其包括一个或多个第四驱动单元和三极管Q6，所述第四驱动单元用以驱动所述三极管Q6的开启；所述三极管Q6用以从所述外部高压电源VIN获取能量加速晶体管Q2的开启；
    LDO模块，包括运算放大器OP、晶体管Q4、电阻R1、电阻R2、电容C1和电容C2；所述运算放大器OP正端接收内部产生的VREF参考电压信号，负端接收电阻R1和电阻R2之间的反馈信号FB，所述运算放大器OP的输出端连接晶体管Q4和晶体管Q5的栅极，根据反馈信号FB调节运算放大器OP输出的电压大小，所述晶体管Q4的漏极连接所述高压电源VIN，所述晶体管Q4的源端、所述电阻R1的一端和电容C1的一端形成连接端，并在所述连接端输出一低压电源VDD1；所述晶体管Q5的漏极连接所述高压电源VIN，所述电容C2串接在所述晶体管Q5的源端和接地端GND之间，并在所述连接端输出一低压电源VDD2；所述低压电源VDD1连接Q2驱动模块中的一个或多个第二驱动单元为其提供电源，所述第二驱动单元的输出连接所述晶体管Q2栅极，控制所述晶体管Q2的开启关闭；所述低压电源VDD1连接Q2驱动加速模块中的一个或多个第二驱动单元为其提供电源，所述第四驱动单元输出连接所述三极管Q6的基极，控制所述三级管Q6的开启关闭，所述三极管Q6的集电极连接所述高压电源VIN，所述三极管Q6的发射极连接晶体管Q2的栅极；所述低压电源VDD2连接晶体管Q3漏极给所述外部电容CBST充电；所述Q3驱动模块的电源由所述外部电容CBST提供；所述外部引脚BST连接所述Q1驱动模块中的一个或多个第一驱动单元输出为其提供电源，所述一个或多个第一驱动单元的输出连接晶体管Q1的栅极，控制所述晶体管Q1的开启关闭；
    当所述外部电容CBST的电压较低时，所述低压电源VDD2可通过晶体管Q3持续给经所述BST引脚给所述外部电容CBST进行充电，直至所述外部电容CBST充满，同时所述晶体管Q3亦可受所述CLKBT信号控制，给所述外部电容CBST充电的时刻打开所述Q3晶体管，给所述外部电容CBST充满能量；所述外部电容CBST的能量经过所述BST引脚给所述Q1驱动模块提供电源，受所述CLKUG信号控制，以驱动所述晶体管Q1工作，所述引脚SW的电压上升保持着与所述引脚BST固定的电压差使所述晶体管Q1工作；所述低压电源VDD1给所述Q2驱动模块提供电源，受所述CLKLG信号控制，以驱动所述晶体管Q2工作。
  5. 根据权利要求1所述的DCDC降压装置的驱动级供电电路，其特征在于，所第一驱动单元、第二驱动单元、第三驱动单元和第四驱动单元的数量均为依次串接的两个。
  6. 根据权利要求1所述的DCDC降压装置的驱动级供电电路；其特征在于，所述的DCDC降压装置的驱动级供电电路以芯片为成品，所述电容C1和所述电容C2为片内电容。
PCT/CN2023/090215 2022-12-05 2023-04-24 一种dcdc降压装置的驱动级供电电路 WO2024119697A1 (zh)

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