WO2024119503A1 - 像素电路及其驱动方法、阵列基板、显示装置 - Google Patents

像素电路及其驱动方法、阵列基板、显示装置 Download PDF

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Publication number
WO2024119503A1
WO2024119503A1 PCT/CN2022/138079 CN2022138079W WO2024119503A1 WO 2024119503 A1 WO2024119503 A1 WO 2024119503A1 CN 2022138079 W CN2022138079 W CN 2022138079W WO 2024119503 A1 WO2024119503 A1 WO 2024119503A1
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Prior art keywords
electrode
signal terminal
transistor
driving transistor
reset
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Ceased
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PCT/CN2022/138079
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English (en)
French (fr)
Inventor
王铸
尚延阳
闫政龙
石领
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BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
Original Assignee
BOE Technology Group Co Ltd
Chengdu BOE Optoelectronics Technology Co Ltd
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Application filed by BOE Technology Group Co Ltd, Chengdu BOE Optoelectronics Technology Co Ltd filed Critical BOE Technology Group Co Ltd
Priority to CN202280004998.5A priority Critical patent/CN118475972A/zh
Priority to PCT/CN2022/138079 priority patent/WO2024119503A1/zh
Priority to US18/558,257 priority patent/US12431085B2/en
Publication of WO2024119503A1 publication Critical patent/WO2024119503A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
    • H10K59/1216—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/04—Changes in size, position or resolution of an image
    • G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
    • G09G2340/0435—Change or adaptation of the frame rate of the video stream

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a pixel circuit and a driving method thereof, an array substrate, and a display device.
  • OLED display panels have the advantages of active luminescence, wide viewing angle, high contrast, fast response speed and low power consumption. They are widely used in display products such as mobile phones, tablet computers, digital cameras, and therefore receive widespread attention.
  • a pixel circuit in one aspect, includes a driving transistor, a reset subcircuit, an anti-leakage electronic circuit and a data writing subcircuit.
  • the driving transistor includes a control electrode, a first electrode and a second electrode.
  • the reset subcircuit is electrically connected to a first scanning signal terminal, a reference voltage signal terminal and a first electrode of the driving transistor, and is configured to transmit a reference voltage signal from the reference voltage signal terminal to the first electrode of the driving transistor under the control of a first scanning signal from the first scanning signal terminal.
  • the anti-leakage electronic circuit is electrically connected to a second scanning signal terminal, a first electrode of the driving transistor and a control electrode of the driving transistor, and is configured to connect the first electrode of the driving transistor to the control electrode under the control of a second scanning signal from the second scanning signal terminal.
  • the data writing subcircuit is electrically connected to a third scanning signal terminal, a data signal terminal and a second electrode of the driving transistor, and is configured to transmit a data signal from the data signal terminal to the second electrode of the driving transistor under the control of a third scanning signal from the third scanning signal terminal.
  • the reset subcircuit includes a first transistor
  • the anti-leakage electronic circuit includes a second transistor
  • the data writing subcircuit includes a third transistor.
  • the control electrode of the first transistor is electrically connected to the first scan signal terminal, the first electrode is electrically connected to the reference voltage signal terminal, and the second electrode is electrically connected to the first electrode of the driving transistor.
  • the control electrode of the second transistor is electrically connected to the second scan signal terminal, the first electrode is electrically connected to the first electrode of the driving transistor, and the second electrode is electrically connected to the control electrode of the driving transistor.
  • the control electrode of the third transistor is electrically connected to the third scan signal terminal, the first electrode is electrically connected to the data signal terminal, and the second electrode is electrically connected to the second electrode of the driving transistor.
  • the second transistor is a metal oxide thin film transistor.
  • the first transistor, the third transistor and the driving transistor are low temperature polysilicon thin film transistors.
  • the reset subcircuit is turned on once or twice when the leakage protection electronic circuit is turned off.
  • the leakage prevention electronic circuit when the leakage prevention electronic circuit is turned off, the data writing subcircuit is turned on at least once, and the data signal terminal outputs a first reset voltage signal.
  • the pixel circuit further includes a first control subcircuit, a second control subcircuit, a reset subcircuit and an energy storage subcircuit.
  • the first control subcircuit is electrically connected to the light emitting control signal terminal, the first voltage signal terminal and the first electrode of the driving transistor, and is configured to transmit the first voltage signal from the first voltage signal terminal to the first electrode of the driving transistor under the control of the light emitting control signal from the light emitting control signal terminal.
  • the second control subcircuit is electrically connected to the light emitting control signal terminal, the second electrode of the driving transistor and the light emitting device, and is configured to transmit the driving current from the driving transistor to the light emitting device under the control of the light emitting control signal.
  • the reset subcircuit is electrically connected to the first scanning signal terminal, the initialization signal terminal and the light emitting device, and is configured to transmit the initialization signal from the initialization signal terminal to the light emitting device under the control of the first scanning signal.
  • the energy storage subcircuit is electrically connected to the control electrode of the driving transistor and the first voltage signal terminal, and is configured to maintain the voltage of the control electrode of the driving transistor.
  • the first control subcircuit includes a fourth transistor
  • the second control subcircuit includes a fifth transistor
  • the reset subcircuit includes a sixth transistor
  • the energy storage subcircuit includes a storage capacitor.
  • the control electrode of the fourth transistor is electrically connected to the light-emitting control signal terminal
  • the first electrode is electrically connected to the first voltage signal terminal
  • the second electrode is electrically connected to the first electrode of the driving transistor.
  • the control electrode of the fifth transistor is electrically connected to the light-emitting control signal terminal
  • the first electrode is electrically connected to the second electrode of the driving transistor
  • the second electrode is electrically connected to the light-emitting device.
  • the control electrode of the sixth transistor is electrically connected to the first scan signal terminal, the first electrode is electrically connected to the initialization signal terminal, and the second electrode is electrically connected to the light-emitting device.
  • the first plate of the storage capacitor is electrically connected to the control electrode of the driving transistor, and the second plate is electrically connected to the first voltage signal terminal.
  • a display frame includes a reset phase, a data writing phase and a first reset phase.
  • the driving method includes: in the reset phase, the first scanning signal terminal and the second scanning signal terminal output a working level, and the third scanning signal terminal outputs a non-working level; the reference voltage signal from the reference voltage signal terminal is transmitted to the control electrode of the driving transistor via the reset subcircuit and the anti-leakage electronic circuit.
  • the data writing phase the first scanning signal terminal outputs a non-working level
  • the second scanning signal terminal and the third scanning signal terminal output a working level
  • the data signal terminal outputs a data signal.
  • the data signal is transmitted to the second electrode of the driving transistor via the data writing subcircuit, and the control electrode of the driving transistor writes the data signal and the threshold voltage.
  • the first scanning signal terminal outputs a working level at least once, and the second scanning signal terminal outputs a non-working level.
  • the reference voltage signal is transmitted to the first electrode of the driving transistor via the reset subcircuit.
  • the pixel circuit includes a first refresh frequency and a second refresh frequency, and the first refresh frequency is less than the second refresh frequency.
  • the pixel circuit also includes a light-emitting stage and a second reset stage after the first reset stage in one display frame.
  • the driving method also includes: in the light-emitting stage, the first scan signal terminal, the second scan signal terminal and the third scan signal terminal output a non-working level, and the light-emitting control signal terminal outputs a working level; the driving current from the driving transistor is transmitted to the light-emitting device.
  • the first scan signal terminal outputs a working level
  • the second scan signal terminal, the third scan signal terminal and the light-emitting control signal terminal output a non-working level
  • the reference voltage signal from the reference voltage signal terminal is transmitted to the first electrode of the driving transistor via the reset subcircuit.
  • the voltage value of the reference voltage signal from the reference voltage signal terminal in the first reset phase is a first reference voltage signal value
  • the voltage value in the second reset phase is a second reference voltage signal value.
  • the first reference voltage signal value is equal to the second reference voltage signal value
  • the first reference voltage signal value and the second reference voltage signal value are negative values.
  • the first reference voltage signal value is less than the second reference voltage signal value
  • the first reference voltage signal value is a negative value
  • the second reference voltage signal value is greater than the voltage value of the first voltage signal from the first voltage signal terminal.
  • an array substrate comprises a substrate and a plurality of pixel circuits disposed on the substrate and arranged in an array.
  • the pixel circuit is the pixel circuit described in any of the above embodiments.
  • the pixel circuit includes a driving transistor, a first transistor, a third transistor and a storage capacitor.
  • the array substrate also includes a first semiconductor layer, a first gate conductive layer and a second gate conductive layer disposed on a substrate.
  • the first semiconductor layer includes a first semiconductor pattern of the first transistor, a third semiconductor pattern of the third transistor and a seventh semiconductor pattern of the driving transistor, wherein the third semiconductor pattern is connected to the seventh semiconductor pattern and is spaced apart from the first semiconductor pattern.
  • the first gate conductive layer is located on a side of the first semiconductor layer away from the substrate, and includes a first scan signal line, a third scan signal line and a first plate of the storage capacitor.
  • the second gate conductive layer is located on a side of the first gate conductive layer away from the substrate, and includes a second plate of the storage capacitor.
  • the pixel circuit further includes a second transistor.
  • the array substrate further includes a second semiconductor layer, a third gate conductive layer, a first source-drain conductive layer, and a second source-drain conductive layer.
  • the second semiconductor layer is located on a side of the second gate conductive layer away from the substrate, and includes a second semiconductor pattern of the second transistor.
  • the third gate conductive layer is located on a side of the second semiconductor layer away from the substrate, and includes a second scanning signal line and a reference voltage signal line.
  • the first source-drain conductive layer is located on a side of the third gate conductive layer away from the substrate, and includes a first connection pattern, a second connection pattern, and a third connection pattern.
  • the first connection pattern is connected to the reference voltage signal line and the first electrode of the first semiconductor pattern.
  • the second connection pattern is connected to the second electrode of the first semiconductor pattern, the first electrode of the second semiconductor pattern, and the first electrode of the seventh semiconductor pattern.
  • the third connection pattern is connected to the second electrode of the second semiconductor pattern and the first electrode plate of the storage capacitor.
  • the second source-drain conductive layer is located on a side of the first source-drain conductive layer away from the substrate, and includes a data line.
  • the data line is connected to the first electrode of the third semiconductor pattern.
  • the second electrode of the third semiconductor pattern is connected to the second electrode of the seventh semiconductor pattern.
  • the second semiconductor pattern in an orthographic projection onto the substrate, partially overlaps the third scan signal line.
  • the second semiconductor pattern includes a first portion and a second portion.
  • the first portion is located on a side of the second scan signal line close to the storage capacitor and overlaps the third scan signal line.
  • the second portion is connected to the first portion and extends along a second direction.
  • the second portion intersects the second scan signal line.
  • the size of the first portion is larger than the size of the third scan signal line, and in an orthographic projection onto the substrate, two ends of the first portion are respectively located on both sides of the third scan signal line. The second direction intersects the first direction.
  • the second connection pattern extends along the second direction, and in an orthographic projection onto the substrate, the second portion overlaps the second connection pattern.
  • the second semiconductor pattern extends along a second direction, and in an orthographic projection onto the substrate, the second semiconductor pattern and the second connection pattern are separated from each other.
  • the third connection pattern in an orthographic projection onto the substrate, partially overlaps with the third scan signal line.
  • the third connection pattern in an orthographic projection onto the substrate, is located on a side of the third scan signal line close to the storage capacitor.
  • the third connection pattern partially overlaps with the second semiconductor pattern, and the overlapping portion is located on a side of the third scan signal line close to the storage capacitor.
  • a portion of the third scan signal line is bent toward a side away from the storage capacitor to form a concave portion, and a portion where the third connection pattern and the second semiconductor pattern overlap on the substrate is located in the concave portion.
  • the third semiconductor pattern is an L-shaped structure.
  • the third semiconductor pattern includes a first extension segment and a second extension segment.
  • the first extension segment extends along a first direction.
  • the second extension segment extends along a second direction and is connected to the first extension segment.
  • the first direction is a row direction in which the plurality of sub-pixels are arranged, and the second direction intersects with the first direction.
  • the third scanning signal line includes a main body and a protruding portion.
  • the main body extends along the first direction, and the orthographic projection of the main body on the substrate overlaps with a portion of the second extension segment.
  • the protruding portion extends along the second direction, and the orthographic projection of the protruding portion on the substrate overlaps with a portion of the first extension segment.
  • the second gate conductive layer further includes an auxiliary second scan signal line configured to transmit a second scan signal, and in an orthographic projection onto the substrate, the auxiliary second scan signal line overlaps with an orthographic projection of the second scan signal line on the substrate.
  • a display device comprises a light emitting device and an array substrate as described in any one of the above embodiments.
  • the light emitting device is disposed on the array substrate, the light emitting device is electrically connected to a pixel circuit of the array substrate, and is configured to emit light under the control of the pixel circuit.
  • FIG1 is a structural diagram of a display panel according to some embodiments.
  • FIG2 is another structural diagram of a display panel according to some embodiments.
  • FIG3 is a cross-sectional structural diagram of a display panel according to some embodiments.
  • FIG4 is a structural block diagram of a pixel circuit according to some embodiments.
  • FIG5 is a structural diagram of a pixel circuit according to some embodiments.
  • FIG6 is another structural block diagram of a pixel circuit according to some embodiments.
  • FIG. 7A is another structural diagram of a pixel circuit according to some embodiments.
  • FIG7B is another structural diagram of a pixel circuit according to some embodiments.
  • FIG8 is a diagram showing a connection relationship between a gate driving circuit and a pixel circuit according to some embodiments.
  • FIG9 is a driving timing diagram of a pixel circuit according to some embodiments.
  • FIG10 is another driving timing diagram of a pixel circuit according to some embodiments.
  • FIG11 is another driving timing diagram of a pixel circuit according to some embodiments.
  • FIG12 is another driving timing diagram of a pixel circuit according to some embodiments.
  • FIG. 13A is another driving timing diagram of a pixel circuit according to some embodiments.
  • FIG. 13B is another driving timing diagram of a pixel circuit according to some embodiments.
  • first and second are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.
  • a feature defined as “first” or “second” may explicitly or implicitly include one or more of the features.
  • plural means two or more.
  • the expressions “coupled” and “connected” and their derivatives may be used.
  • the term “connected” may be used to indicate that two or more components are in direct physical or electrical contact with each other.
  • the term “coupled” may be used to indicate that two or more components are in direct physical or electrical contact.
  • the term “coupled” or “communicatively coupled” may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
  • At least one of A, B, and C has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.
  • a and/or B includes the following three combinations: A only, B only, and a combination of A and B.
  • parallel includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°;
  • perpendicular includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°.
  • equal includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, the difference between the two equalities is less than or equal to 5% of either one.
  • Exemplary embodiments are described herein with reference to cross-sectional views and/or plan views that are idealized exemplary drawings.
  • the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and/or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.
  • the control electrode of the transistor is the gate of the transistor
  • the first electrode is one of the source and drain of the transistor
  • the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be indistinguishable in structure, that is, the first electrode and the second electrode of the transistor in the embodiment of the present disclosure can be indistinguishable in structure.
  • the first electrode (or the second electrode) of the driving transistor can be the source or the drain at different stages of a display frame, that is, the source and the drain of the driving transistor can be interchanged (the source and the drain of the driving transistor are reversed) at different stages of a display frame.
  • the first electrode of other transistors is the source
  • the second electrode is the drain.
  • the display device 1000 may be any device that displays either moving (e.g., video) or fixed (e.g., still image), and whether textual or image.
  • the display device 1000 may be a television, a laptop computer, a tablet computer, a mobile phone, an electronic photo, an electronic billboard or signboard, a personal digital assistant (full name in English: Personal Digital Assistant; PDA for short), a navigator, a wearable device, an augmented reality (full name in English: Augmented Reality; AR for short) device, a virtual reality (full name in English: Virtual Reality; VR for short) device, or any other product or component with a display function.
  • PDA Personal Digital Assistant
  • the display device 1000 may be an electroluminescent display device or a photoluminescent display device.
  • the electroluminescent display device may be an organic light-emitting diode (OLED) display device or a quantum dot light-emitting diode (QLED) display device.
  • OLED organic light-emitting diode
  • QLED quantum dot light-emitting diode
  • the display device 1000 includes a display panel 1100 and a driving circuit board (English full name: Source Printed Circuit Board; abbreviated as: SPCB) 1200.
  • SPCB Source Printed Circuit Board
  • the display panel 1100 may include a display area AA and a peripheral area BB (also called a non-display area).
  • the peripheral area BB is at least located on one side of the display area AA.
  • the peripheral area BB is described as surrounding the display area AA.
  • the display area AA may include a plurality of sub-pixels (full name in English: Sub Pixel) P, a plurality of data lines DL, and a plurality of scan signal lines (a first scan signal line RL, a second scan signal line GNL, a third scan signal line GPL, and a fourth scan signal line EML).
  • the sub-pixel P includes a pixel circuit 120 and a light-emitting device EL.
  • the plurality of sub-pixels P are arranged in a plurality of rows and a plurality of columns, each row including a plurality of sub-pixels P arranged along a first direction X, that is, the first direction X is the arrangement direction of a row of sub-pixels P, and a plurality of rows of sub-pixels P are arranged along a second direction Y.
  • Each column includes a plurality of sub-pixels P arranged along a second direction Y, that is, the second direction Y is the arrangement direction of a column of sub-pixels P; a plurality of columns of sub-pixels P are arranged along the first direction X.
  • the first direction X and the second direction Y intersect, for example, the first direction X is perpendicular to the second direction Y.
  • the display panel 1100 may include an array substrate 100 , a light emitting device EL disposed on the array substrate 100 , and an encapsulation layer 200 disposed on the light emitting device EL.
  • the array substrate 100 includes a substrate 110 and a plurality of pixel circuits 120 disposed on the substrate 110.
  • the pixel circuit 120 may include a plurality of thin film transistors (full name: Thin Film Transistor; abbreviated as TFT) and a storage capacitor Cst, wherein only two thin film transistors (a fifth transistor T5 and a second transistor T2) are exemplarily shown in FIG. 3 .
  • the arrangement of the plurality of pixel circuits may be similar to the arrangement of the plurality of sub-pixels P, that is, the plurality of pixel circuits are arranged in a plurality of rows and a plurality of columns.
  • the row direction of the arrangement of the plurality of pixel circuits is parallel to the row direction of the arrangement of the plurality of sub-pixels P, that is, the first direction X may also be considered as the row direction of the arrangement of the plurality of pixel circuits.
  • the peripheral area BB may include at least a gate driver circuit 130 and a source driver 140.
  • the gate driver circuit 130 may include a plurality of shift registers (full name in English: Gate Driver On Array; abbreviated as GOA), each of which is electrically connected to at least one row of pixel circuits 120 via a gate line (see below).
  • the source driver 140 may be, for example, a source driver chip (full name in English: Source Driver IC).
  • the driving circuit board 1200 may include a timing controller (full name in English: Timing Controller; abbreviated as: TCON), a power management chip DC/DC and an adjustable resistor voltage divider circuit (for generating Vcom) and other driving circuits.
  • the driving circuit board 1200 is electrically connected to the source driver 140 to control the source driver 140 to output a data signal.
  • the driving circuit board 1200 is electrically connected to the gate driving circuit 130 to transmit the control signal to the shift register so that the corresponding shift register scans the multiple rows of pixel circuits 120 line by line.
  • the display panel 1100 realizes image display under the joint action of electronic components and circuits such as the driving circuit board 1200, the source driver 140, the gate driving circuit 130, the pixel circuit 120 and the light-emitting device EL.
  • the pixel circuit 120 includes a driving transistor DT, and the channel of the driving transistor itself exhibits an obvious hysteresis effect due to the large number of defect states.
  • the hysteresis effect of the driving transistor refers to an uncertainty in the electrical characteristics of the driving transistor under a certain bias voltage, that is, the magnitude of the current of the driving transistor is not only related to the current bias voltage, but also to the bias state of the previous period. For example, the image of the previous moment (previous frame period) is often retained in the image display of the next moment, resulting in the above-mentioned display problem of flickering screen.
  • a reset transistor is usually added to the pixel circuit.
  • the reset transistor can be used to reset the voltage of the source of the driving transistor (also called voltage reset or voltage initialization), thereby adjusting the bias state of the driving transistor and improving the hysteresis effect of the driving transistor.
  • the pixel circuit provided in the related art will increase the number of transistors included in the pixel circuit, thereby increasing the space occupied by the pixel circuit, which is not conducive to improving the pixel density of the display panel (full name in English: Pixels Per Inch; abbreviated as: PPI).
  • the pixel circuit 120 includes a driving transistor DT, a reset subcircuit 121, an anti-leakage electronic circuit 122 and a data writing subcircuit 123.
  • the driving transistor DT includes a control electrode N1, a first electrode N2 and a second electrode N3.
  • the reset subcircuit 121 is electrically connected to the first scan signal terminal Reset, the reference voltage signal terminal Vref and the first electrode N2 of the driving transistor DT.
  • the reset subcircuit 121 is configured to transmit the reference voltage signal from the reference voltage signal terminal Vref to the first electrode N2 of the driving transistor DT under the control of the first scan signal from the first scan signal terminal Reset.
  • the leakage prevention electronic circuit 122 is electrically connected to the second scan signal terminal Gate-N, the first electrode N2 of the driving transistor DT and the control electrode N1 of the driving transistor DT.
  • the leakage prevention electronic circuit 122 is configured to connect the first electrode N2 of the driving transistor DT to the control electrode N1 under the control of the second scan signal from the second scan signal terminal Gate-N.
  • the data writing sub-circuit 123 is electrically connected to the third scanning signal terminal Gate-P, the data signal terminal Data and the second electrode N3 of the driving transistor DT.
  • the data writing sub-circuit 123 is configured to transmit the data signal from the data signal terminal Data to the second electrode N3 of the driving transistor DT under the control of the third scanning signal from the third scanning signal terminal Gate-P.
  • the leakage prevention electronic circuit 122 When the leakage prevention electronic circuit 122 is turned on, the reset sub-circuit 121 and the data writing sub-circuit 123 are turned on in sequence.
  • the leakage prevention electronic circuit 122 is turned on, which means that the leakage prevention electronic circuit 122 connects the first electrode N2 of the driving transistor DT to the control electrode N1 under the control of the second scanning signal.
  • the reset subcircuit 121 is turned on, which means that the reset subcircuit 121 transmits the reference voltage signal from the reference voltage signal terminal Vref to the first electrode N2 of the driving transistor DT under the control of the first scanning signal.
  • the data writing subcircuit 123 is turned on, which means that the data writing subcircuit 123 transmits the data signal to the second electrode N3 of the driving transistor DT under the control of the third scanning signal from the third scanning signal terminal Gate-P.
  • one display frame may include a refresh frame T10 and a hold frame T20 located after the refresh frame T10 , and the refresh frame T10 may include a reset phase T11 , a data writing phase T12 , and a first reset phase T13 which are sequentially arranged.
  • the leakage prevention electronic circuit 122 is turned on in the reset phase T11 and the data writing phase T12, and the reset sub-circuit 121 is turned on in the reset phase T11, and the data writing sub-circuit 123 is turned on in the data writing phase T12.
  • the anti-leakage electronic circuit 122 connects the first electrode N2 of the driving transistor DT to the control electrode N1 under the control of the second scanning signal.
  • the reset subcircuit 121 transmits the reference voltage signal to the first electrode N2 of the driving transistor DT under the control of the first scanning signal, and further, the reference voltage signal is transmitted from the first electrode N2 of the driving transistor DT to the control electrode N1 of the driving transistor DT.
  • the reference voltage signal from the reference voltage signal terminal Vref can be transmitted to the control electrode N1 of the driving transistor DT, so as to achieve the voltage reset (also called: voltage initialization or voltage reset) of the control electrode N1 of the driving transistor DT.
  • the anti-leakage electronic circuit 122 connects the first electrode N2 of the driving transistor DT to the control electrode N1 under the control of the second scanning signal.
  • the data signal is transmitted to the second electrode N3 of the driving transistor DT, and is transmitted to the first electrode N2 of the driving transistor DT after compensation by the second electrode N3 of the driving transistor DT, and then transmitted to the control electrode N1 of the driving transistor DT through the anti-leakage electronic circuit 122, so as to realize the threshold voltage compensation of the driving transistor DT and the writing of the data signal.
  • the reset sub-circuit 121 is turned on at least once.
  • the anti-leakage electronic circuit 122 is turned off, which means that the second scanning signal terminal does not output the second scanning signal (outputs a non-working level), and the reset sub-circuit 121 cannot conduct the first electrode N2 of the driving transistor DT and the control electrode N1, that is, the first electrode N2 of the driving transistor DT and the control electrode N1 cannot transmit an electrical signal through the anti-leakage electronic circuit 122.
  • the anti-leakage electronic circuit 122 is turned off, and the reset subcircuit 121 transmits the reference voltage signal to the first electrode N2 of the driving transistor DT under the control of the first scanning signal, and the reference voltage signal is not further transmitted to other nodes of the circuit.
  • the reset subcircuit 121 can achieve the voltage reset of the first electrode N2 of the driving transistor DT, and then adjust the bias state of the driving transistor DT (adjust the voltage difference Vgs between the gate and the source of the driving transistor DT), and improve the hysteresis effect of the driving transistor.
  • the reset subcircuit 121 can be used to reset the voltage of the control electrode N1 of the driving transistor DT, and can also be used to reset the voltage of the first electrode N2 of the driving transistor DT.
  • the reset subcircuit 121 can realize two functions (resetting the voltage of the control electrode N1 and the first electrode N2 of the driving transistor DT respectively), so that one reset transistor (for resetting the voltage of the control electrode N1 of the driving transistor DT) can be reduced, thereby reducing the number of transistors included in the pixel circuit 120, which is conducive to reducing the space occupied by the pixel circuit 120 and improving the pixel density of the display panel 1100.
  • the reset subcircuit and the data writing subcircuit are usually electrically connected to the first pole (source) of the driving transistor, so that the data signal and the reference voltage signal are written to the same node (the first pole of the driving transistor) in different time periods (data writing stage and first reset stage).
  • the reset subcircuit 121 is electrically connected to the first pole N2 of the driving transistor DT
  • the data writing subcircuit 123 is electrically connected to the second pole N3 of the driving transistor DT.
  • the data writing subcircuit 123 transmits the data signal to the second pole N3 of the driving transistor DT, at which time the second pole N3 of the driving transistor DT serves as the source, and the data signal is transmitted from the second pole N3 of the driving transistor DT to the first pole N2.
  • the reset subcircuit 121 transmits the reference voltage signal to the first pole N2 of the driving transistor DT, at which time the first pole N2 of the driving transistor DT serves as the source.
  • the source and drain of the driving transistor DT are reversed, and the bias state of the driving transistor DT is different, which is conducive to improving the hysteresis effect of the driving transistor DT and reducing the risk of screen flickering in the display panel 1100.
  • the reset sub-circuit 121 includes a first transistor T1
  • the leakage prevention electronic circuit 122 includes a second transistor T2
  • the data writing sub-circuit 123 includes a third transistor T3 .
  • the control electrode of the first transistor T1 is electrically connected to the first scan signal terminal Reset, the first electrode is electrically connected to the reference voltage signal terminal Vref, and the second electrode is electrically connected to the first electrode N2 of the driving transistor DT.
  • the control electrode of the second transistor T2 is electrically connected to the second scan signal terminal Gate-N, the first electrode is electrically connected to the first electrode N2 of the driving transistor DT, and the second electrode is electrically connected to the control electrode N1 of the driving transistor DT.
  • the control electrode of the third transistor T3 is electrically connected to the third scan signal terminal Gate-P, the first electrode is electrically connected to the data signal terminal Data, and the second electrode is electrically connected to the second electrode N3 of the driving transistor DT.
  • the first transistor T1 and the third transistor T3 are both P-type transistors, which are turned on when the voltage of the control electrode is a low voltage, and turned off when the voltage of the control electrode is a high voltage.
  • the reset subcircuit 121 when the reset subcircuit 121 is turned on, the first scan signal terminal Reset can output a low-voltage first scan signal to the control electrode of the first transistor T1, and the first transistor T1 is turned on under the control of the low-voltage first scan signal. Conversely, when the reset subcircuit 121 is turned off, the first transistor T1 is turned off under the control of the high voltage.
  • the second transistor T2 may be an N-type transistor, which is turned on when the voltage of the control electrode is a high voltage, and is turned off when the voltage of the control electrode is a low voltage. Based on this, when the anti-leakage electronic circuit 122 is turned on, the second scanning signal terminal Gate-P outputs a high-voltage second scanning signal to the control electrode of the second transistor T2, and the second transistor T2 is turned on under the control of the high-voltage second scanning signal. Conversely, when the anti-leakage electronic circuit 122 is turned off, the second transistor T2 is turned off under the control of the low voltage.
  • the second transistor T2 may be a metal oxide thin film transistor (full name in English: Thin Film Transistor; abbreviated as TFT), and the metal oxide may be, for example, indium gallium zinc oxide (full name in English: Indium Gallium Zinc Oxide; abbreviated as IGZO).
  • TFT Thin Film Transistor
  • IGZO Indium Gallium Zinc Oxide
  • the metal oxide thin film transistor has the advantage of small current, which is conducive to reducing the leakage current of the second transistor T2, thereby improving the voltage holding capability of the control electrode N1 of the driving transistor DT.
  • the first transistor T1, the third transistor T3 and the driving transistor DT are low temperature polysilicon (LTPS) thin film transistors.
  • LTPS low temperature polysilicon
  • Low temperature polysilicon thin film transistors have high electron mobility, which is beneficial to reducing the load of each transistor and reducing the energy consumption of the pixel circuit 120.
  • the reset subcircuit 121 when the leakage prevention electronic circuit 122 is turned off, can be turned on once or twice. That is, in the first reset stage T13, the first scan signal terminal Reset outputs the first scan signal (working level) once or twice, and the reset subcircuit 121 transmits the reference voltage signal to the first electrode N2 of the driving transistor DT once or twice under the control of the first scan signal.
  • the first scan signal terminal Reset outputs a working level once, and the reset subcircuit 121 is turned on once.
  • the first scan signal terminal Reset outputs a working level once, and the reset subcircuit 121 is turned on once.
  • the first scan signal terminal Reset outputs a working level twice, and the reset subcircuit 121 is turned on twice.
  • the reference voltage signal it is beneficial for the reference voltage signal to be more fully transmitted to the first pole N2 of the driving transistor DT, and the voltage reset of the first pole N2 of the driving transistor DT is more fully.
  • the first scan signal terminal Reset can also output the first scan signal more than twice, for example, the first scan signal terminal Reset can output the first scan signal three times, four times or five times, and the embodiments of the present disclosure will not be listed one by one.
  • the data writing subcircuit 123 when the leakage prevention electronic circuit 122 is turned off, the data writing subcircuit 123 is turned on at least once, and the data signal terminal Data outputs a first reset voltage signal.
  • the data writing subcircuit 123 transmits the data signal to the second pole N3 of the driving transistor DT, and a bias occurs between the second pole N3 of the driving transistor DT and the first pole N2, and after the data writing phase T12 ends, there may be a residual voltage in the second pole N3 of the driving transistor DT.
  • the leakage prevention electronic circuit 122 when the leakage prevention electronic circuit 122 is turned off, the data writing subcircuit 123 is turned on at least once, and after the data writing phase T12, the first reset voltage signal can be transmitted to the second pole N3 of the driving transistor DT through the data writing subcircuit 123, and the voltage of the second pole N3 of the driving transistor DT is reset. Reduce the influence of the data signal on the voltage of the second pole N3 of the driving transistor DT, thereby reducing the risk of display brightness difference of the display panel 1100 due to the change of the data signal, and reduce the risk of flickering of the display panel 1100.
  • the data writing subcircuit 123 is turned on row by row (data signals are written row by row), and the first reset stage is entered row by row.
  • the target row pixel circuit any row pixel circuit
  • the data writing subcircuit 123 is turned on
  • the data writing subcircuit of a certain row pixel circuit after the target row pixel circuit (hereinafter referred to as the subsequent row pixel circuit) is turned on to write the data signal.
  • the data signal of the subsequent row pixel circuit is written into the second pole N3 of the driving transistor DT of the target row pixel circuit through the data writing subcircuit of the target row pixel circuit, and the voltage of the second pole N3 of the driving transistor DT of the target row pixel circuit is reset. That is to say, in the first reset stage, the first reset voltage signal (of the target row pixel circuit) is the data signal of the subsequent row pixel circuit.
  • the data signal is usually a positive voltage, which can increase the voltage of the second electrode N3 of the driving transistor DT of the target row pixel circuit, and pre-charge the second electrode N3 of the driving transistor DT before the light-emitting stage, which is beneficial to reduce the flickering phenomenon of the display panel 1100 when switching between low refresh frequency and high refresh frequency or when switching screen display.
  • the data writing sub-circuit 123 is turned on under the control of the third scanning signal, thereby transmitting the first reset voltage signal from the data signal terminal Data to the second electrode N3 of the driving transistor DT.
  • the third scanning signal terminal Gate-P outputs a working level (low voltage level signal)
  • the third transistor T3 is turned on, and the first reset voltage signal of the data signal terminal Data is transmitted to the second electrode N3 of the driving transistor DT through the third transistor T3.
  • the reset subcircuit 121 and the data writing subcircuit 123 are turned on the same number of times.
  • the reset subcircuit 121 and the data writing subcircuit 123 are both turned on once, refer to FIG11, and the first scanning signal terminal Reset and the third scanning signal terminal Gate-P both output sequential working levels.
  • the reset subcircuit 121 and the data writing subcircuit 123 are both turned on twice, refer to FIG12, and the first scanning signal terminal Reset and the third scanning signal terminal Gate-P both output sequential working levels.
  • the first scanning signal and the third scanning signal are both pulse signals, and the pulse widths of the first scanning signal and the third scanning signal are the same.
  • the reset subcircuit 121 and the data writing subcircuit 123 can be turned on and off at the same time, that is, the first scanning signal terminal Reset and the third scanning signal terminal Gate-P output the first scanning signal and the third scanning signal in the same time period, respectively.
  • the pixel circuit 120 further includes a first control subcircuit 124 , a second control subcircuit 125 , a reset subcircuit 126 , and an energy storage subcircuit 127 .
  • the first control subcircuit 124 is electrically connected to the light emitting control signal terminal EM (also referred to as the enable signal terminal), the first voltage signal terminal VDD, and the first electrode N2 of the driving transistor DT.
  • the first control subcircuit 124 is configured to transmit the first voltage signal from the first voltage signal terminal VDD to the first electrode N2 of the driving transistor DT under the control of the light emitting control signal from the light emitting control signal terminal EM.
  • the second control subcircuit 125 is electrically connected to the emission control signal terminal EM, the second electrode N3 of the driving transistor DT and the light emitting device EL.
  • the second control subcircuit 125 is configured to transmit the driving current from the driving transistor DT to the light emitting device EL under the control of the emission control signal.
  • the reset subcircuit 126 is electrically connected to the first scan signal terminal Reset, the initialization signal terminal Vinit, and the light emitting device EL (specifically, the anode of the light emitting device EL).
  • the reset subcircuit 126 is configured to transmit the initialization signal from the initialization signal terminal Vinit to the light emitting device EL under the control of the first scan signal (from the first scan signal terminal Reset).
  • the energy storage sub-circuit 127 is electrically connected to the control electrode N1 of the driving transistor DT and the first voltage signal terminal VDD.
  • the energy storage sub-circuit 127 is configured to maintain the voltage of the control electrode N1 of the driving transistor DT.
  • the holding frame T20 includes a light-emitting phase T21.
  • the first control subcircuit 124 is turned on under the control of the light-emitting control signal, and the first voltage signal from the first voltage signal terminal VDD is transmitted to the first electrode N2 of the driving transistor DT through the first control subcircuit 124.
  • the driving transistor DT generates a driving current under the control of the voltage difference between the control electrode N1 and the first electrode N2.
  • the second control subcircuit 125 is also turned on under the control of the light-emitting control signal, and the driving current generated by the driving transistor DT is transmitted to the light-emitting device EL through the second control subcircuit 125, and the light-emitting device EL starts to emit light (is lit) under the action of the driving current.
  • the reset sub-circuit 126 and the reset sub-circuit 121 are both electrically connected to the first scan signal terminal Reset, and are both turned on under the control of the scan signal from the first scan signal terminal Reset. Based on this, when the reset sub-circuit 121 in any of the above embodiments is turned on, the reset sub-circuit 126 is turned on synchronously with the reset sub-circuit 121, and the voltage of the light-emitting device EL (the anode of the light-emitting device EL) is reset once.
  • the energy storage subcircuit 127 can maintain the voltage of the control electrode N1 node of the driving transistor DT and reduce the leakage current of the control electrode N1 of the driving transistor DT in the data writing stage T12 after the compensated data signal is transmitted to the control electrode N1 of the driving transistor DT, so that the driving transistor DT can generate a stable driving current in the light-emitting stage T21, drive the light-emitting device EL to emit light, and make the light-emitting device EL display a preset gray scale.
  • the first control subcircuit 124 includes a fourth transistor T4
  • the second control subcircuit 125 includes a fifth transistor T5
  • the reset subcircuit 126 includes a sixth transistor T6
  • the energy storage subcircuit 127 includes a storage capacitor Cst.
  • the control electrode of the fourth transistor T4 is electrically connected to the light emitting control signal terminal EM, the first electrode is electrically connected to the first voltage signal terminal VDD, and the second electrode is electrically connected to the first electrode N2 of the driving transistor DT.
  • the control electrode of the fifth transistor T5 is electrically connected to the light emitting control signal terminal EM, the first electrode is electrically connected to the second electrode N3 of the driving transistor DT, and the second electrode is electrically connected to the light emitting device EL.
  • the control electrode of the sixth transistor T6 is electrically connected to the first scanning signal terminal Reset, the first electrode is electrically connected to the initialization signal terminal Vinit, and the second electrode is electrically connected to the light emitting device EL.
  • the first electrode plate of the storage capacitor Cst is electrically connected to the control electrode of the driving transistor DT, and the second electrode plate is electrically connected to the first voltage signal terminal VDD.
  • the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are low temperature polysilicon thin film transistors.
  • the storage capacitor Cst may be a capacitor device manufactured separately by a process.
  • the capacitor device may be implemented by manufacturing a dedicated capacitor plate (a first plate and a second plate of the storage capacitor Cst).
  • each capacitor plate of the storage capacitor may be implemented by a metal layer.
  • the third transistor T3 may be a dual-gate transistor, so that the leakage current of the third transistor T3 may be reduced.
  • the array substrate 100 provided by the embodiment of the present disclosure further includes a first shift register Reset-GOA, a second shift register GN-GOA, a third shift register GP-GOA and a fourth shift register EM-GOA.
  • the first shift register Reset-GOA is connected to at least one row of pixel circuits 120 correspondingly, and is configured to transmit a first scan signal to at least one row of pixel circuits 120.
  • the first shift register Reset-GOA is electrically connected to two rows of pixel circuits 120 through a first scan signal line RL.
  • the first scan signal line RL serves as a first scan signal terminal Reset, and the control electrode of the first transistor T1 and the control electrode of the sixth transistor T6 are both electrically connected to the first scan signal line RL (first scan signal terminal Reset).
  • the first shift register Reset-GOA is arranged on opposite sides of the display area AA along the first direction X, that is, the first shift register Reset-GOA adopts bilateral drive.
  • the second shift register GN-GOA is connected to at least one row of pixel circuits 120, and is configured to transmit a first scan signal to at least one row of pixel circuits 120.
  • the second shift register GN-GOA is electrically connected to two rows of pixel circuits 120 via a second scan signal line GNL.
  • the second scan signal line GNL serves as a second scan signal terminal GN
  • the control electrode of the second transistor T2 is electrically connected to the second scan signal line GNL (second scan signal terminal GN).
  • the second shift register GN-GOA is disposed on one side of the display area AA along the first direction X, that is, the second shift register GN-GOA adopts unilateral drive.
  • the third shift register GP-GOA is connected to a row of pixel circuits 120 correspondingly, and is configured to transmit a third scan signal to a row of pixel circuits 120.
  • the third shift register GP-GOA is electrically connected to two rows of pixel circuits 120 through a third scan signal line GPL.
  • the third scan signal line GPL serves as a third scan signal terminal GP, and the control electrode of the third transistor T3 is electrically connected to the third scan signal line GPL (third scan signal terminal GP).
  • the third shift register GP-GOA is arranged on two opposite sides of the display area AA along the first direction X, that is, the third shift register GP-GOA adopts bilateral drive.
  • the fourth shift register EM-GOA is connected to at least one row of pixel circuits 120, and is configured to transmit a fourth scan signal to at least one row of pixel circuits 120.
  • the fourth shift register EM-GOA is electrically connected to two rows of pixel circuits 120 via a fourth scan signal line EML.
  • the fourth scan signal line EML serves as a light emitting control signal terminal EM, and the control electrode of the fourth transistor T4 and the control electrode of the fifth transistor T5 are both electrically connected to the fourth scan signal line EML (fourth scan signal terminal EM).
  • the fourth shift register EM-GOA is disposed on the opposite side of the display area AA along the first direction X, that is, the fourth shift register EM-GOA adopts unilateral drive.
  • the first transistor T1 included in the reset subcircuit 121 and the sixth transistor T6 included in the reset subcircuit 126 share the first shift register Reset-GOA. Based on this, one shift register can be reduced, which is beneficial to reducing the width of the peripheral area BB and realizing a narrow frame of the display panel 1100.
  • Some other embodiments of the present disclosure further provide a driving method for a pixel circuit 120, and the driving method is used to drive the pixel circuit 120 described in any of the above embodiments.
  • the driving method includes:
  • the first scan signal terminal Reset and the second scan signal terminal Gate-N output a working level
  • the third scan signal terminal Gate-P outputs a non-working level.
  • the reference voltage signal from the reference voltage signal terminal Vref is transmitted to the control electrode N1 of the driving transistor DT via the reset subcircuit 121 and the anti-leakage electronic circuit 122.
  • the working level refers to a level signal that can turn on the transistor electrically connected to the corresponding scanning signal terminal, that is, under the drive of the working level, the first electrode and the second electrode of the corresponding transistor are connected.
  • the non-working level refers to a level signal that turns off (closes) the transistor electrically connected to the corresponding scanning signal terminal, that is, under the drive of the non-working level, the first electrode and the second electrode of the corresponding transistor are cut off.
  • the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are all P-type transistors (P-type transistors are turned on when the control electrode is at a low voltage and turned off when the control electrode is at a high voltage), the first scanning signal terminal Reset, the third scanning signal terminal Gate-P and the light-emitting control signal terminal EM connected to the control electrodes of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6, the output working level refers to the voltage signal with a low output voltage value of the corresponding signal terminal, and the output non-working level refers to the voltage signal with a high output voltage value.
  • the third scanning signal terminal Gate-P electrically connected to the third transistor T3 outputs the working level, which means that the third scanning signal terminal Gate-P outputs the voltage signal with a low output voltage value, and the third scanning signal terminal Gate-P outputs the non-working level, which means that the third scanning signal terminal Gate-P outputs the voltage signal with a high output voltage value.
  • the second scanning signal terminal Gate-N When the second transistor T2 is an N-type transistor (the N-type transistor is turned on when the control voltage is extremely high and is turned off when the control voltage is extremely low), the second scanning signal terminal Gate-N outputs a working level, which means a voltage signal with a high output voltage value, and the second scanning signal terminal Gate-N outputs a non-working level, which means a voltage signal with a low output voltage value.
  • the embodiments of the present disclosure do not limit the specific voltage values of the working level and the non-working level, wherein the voltage value of the working level can fully turn on the corresponding transistor.
  • the first scan signal terminal Reset outputs a working level
  • the reset sub-circuit 121 electrically connected to the first scan signal terminal Reset is turned on.
  • the reset sub-circuit 121 includes a first transistor T1
  • the first transistor T1 is turned on.
  • the first transistor T1 transmits the reference voltage signal from the reference voltage signal terminal Vref to the first electrode N2 of the driving transistor DT.
  • the reset subcircuit 126 includes a sixth transistor T6, in the reset phase T11, the sixth transistor T6 and the first transistor T1 are synchronously turned on, and the sixth transistor T6 transmits the initialization signal from the initialization signal terminal Vinit to the anode of the light emitting device EL, and resets the voltage of the anode of the light emitting device EL.
  • the first transistor T1 and the second transistor T2 together reset the voltage of the control electrode N1 of the driving transistor DT (see above, no further description is given here).
  • the second scanning signal terminal Gate-N outputs a working level, and the leakage prevention electronic circuit 122 electrically connected to the second scanning signal terminal Gate-N is turned on.
  • the leakage prevention electronic circuit 122 includes a second transistor T2, and the second transistor T2 is an N-type transistor
  • the second scanning signal terminal Gate-N outputs a high voltage working level to the control electrode of the second transistor T2, and the second transistor T2 is turned on.
  • the second transistor T2 transmits the reference voltage signal transmitted to the first electrode N2 of the driving transistor DT via the first transistor T1 to the control electrode N1 of the driving transistor DT, thereby resetting the voltage of the control electrode N1 of the driving transistor DT.
  • the first scanning signal terminal Reset outputs a non-working level
  • the second scanning signal terminal Gate-N and the third scanning signal terminal Gate-P output working levels
  • the data signal terminal Data outputs a data signal.
  • the data signal is transmitted to the second electrode N3 of the driving transistor DT via the data writing sub-circuit 123, and the control electrode N1 of the driving transistor DT writes the data signal and the threshold voltage.
  • the first scan signal terminal Reset outputs a non-operating level, and the reset sub-circuit 121 and the reset sub-circuit 126 electrically connected to the first scan signal terminal Reset are turned off, that is, the first transistor T1 and the sixth transistor T6 are turned off.
  • the second scanning signal terminal Gate-N outputs a working level, and the leakage prevention electronic circuit 122 electrically connected to the second scanning signal terminal Gate-N remains turned on, that is, the second transistor T2 remains in a conducting state.
  • the third scanning signal terminal Gate-P outputs a working level, and the data writing sub-circuit 123 electrically connected to the third scanning signal terminal Gate-P is turned on.
  • the data writing sub-circuit 123 includes a third transistor T3, the third transistor T3 is turned on, and the third transistor T3 transmits the data signal from the data signal terminal Data to the second electrode N3 of the driving transistor DT.
  • the data signal is transmitted from the second electrode N3 of the driving transistor DT to the first electrode N2 of the driving transistor DT after compensation by the driving transistor DT, and then the data signal and the threshold voltage are transmitted from the first electrode N2 of the driving transistor DT to the control electrode N1 of the driving transistor DT via the second transistor T2.
  • the first scan signal terminal Reset outputs at least one working level
  • the second scan signal terminal Gate-N outputs a non-working level
  • the reference voltage signal is transmitted to the first electrode N2 of the driving transistor DT via the reset sub-circuit 121 to achieve voltage reset of the first electrode N2 of the driving transistor DT.
  • the first scanning signal terminal Reset outputs a working level
  • the reset subcircuit 121 electrically connected to the first scanning signal terminal Reset is turned on, that is, the first transistor T1 is turned on.
  • the first transistor T1 transmits the reference voltage signal from the reference voltage signal terminal Vref to the first electrode N2 of the driving transistor DT.
  • the second scanning signal terminal Gate-N outputs a non-working level, and the anti-leakage electronic circuit 122 electrically connected to the second scanning signal terminal Gate-N is turned off, that is, the second transistor T2 is turned off, and the reference voltage signal cannot be written into the control of the driving transistor DT through the anti-leakage electronic circuit 122, and then only the voltage of the first electrode N2 of the driving transistor DT is reset.
  • the driving method of the pixel circuit 120 provided in the embodiment of the present disclosure can reset the voltage of the control electrode N1 of the driving transistor DT through the reset subcircuit 121 (first transistor T1) and the anti-leakage electronic circuit 122 (second transistor T2) in the reset stage T11, and reset the voltage of the first electrode N2 of the driving transistor DT through the reset subcircuit 121 in the first reset stage T13.
  • the pixel circuit 120 can reduce one reset transistor, which is beneficial to reduce the space occupied by the pixel circuit 120 and improve the pixel density of the display panel 1100.
  • the first scan signal terminal Reset in the first reset stage T13, can output a working level.
  • the reset subcircuit 121 performs a voltage reset on the first electrode N2 of the driving transistor DT, which is beneficial to shorten the duration of the first reset stage T13, thereby increasing the refresh frequency of the display panel 1100.
  • the first scan signal terminal Reset in the first reset stage T13, can output the working level twice.
  • the reset subcircuit 121 performs two voltage resets on the first electrode N2 of the driving transistor DT, which is conducive to more fully transmitting the reference voltage signal to the first electrode N2 of the driving transistor DT.
  • the first scan signal terminal Reset may output the working level more times; for example, three times, four times or more, which is not specifically limited in the embodiments of the present disclosure.
  • the driving method of the pixel circuit further includes: in the first reset stage T13, the third scanning signal terminal Gate-P outputs a non-working level signal. That is, in the first reset stage T13, the data writing sub-circuit is turned off, which is conducive to simplifying the driving method of the pixel circuit.
  • the driving method of the pixel circuit further includes: in the first reset stage T13 , the third scanning signal terminal Gate-P outputs a working level signal at least once, and the data signal terminal outputs a first reset voltage signal.
  • the data writing sub-circuit 123 is turned on, and the data signal terminal Data outputs a first reset voltage signal.
  • the first reset voltage signal can be transmitted to the second electrode N3 of the driving transistor DT, and the voltage of the second electrode N3 of the driving transistor DT is reset.
  • the influence of the data signal on the voltage of the second electrode N3 of the driving transistor DT is reduced, thereby reducing the risk of display brightness difference of the display panel 1100 due to the change of the data signal, and reducing the risk of flickering of the display panel 1100.
  • the third scan signal terminal Gate-P outputs a working level once, which is beneficial to shorten the duration of the first reset stage T13 , thereby increasing the refresh frequency of the display panel 1100 .
  • the third scanning signal terminal Gate-P outputs the working level twice.
  • the data writing subcircuit 123 performs two voltage resets on the second electrode N3 of the driving transistor DT, which is conducive to more fully transmitting the first reset voltage signal to the second electrode N3 of the driving transistor DT.
  • the pixel circuit 120 may include a first refresh frequency and a second refresh frequency, the first refresh frequency being less than the second refresh frequency, that is, the display panel adopts a variable refresh rate (English full name: (Variable Refresh Rate; abbreviated: VRR) display technology, the display panel can select a suitable refresh frequency according to changes in usage scenarios, and the specific value of the refresh frequency of the display panel is not specifically limited in the embodiments of the present disclosure.
  • the first refresh frequency may be, for example, 1 Hz or 30 Hz; the second refresh frequency may be, for example, 60 Hz or 120 Hz.
  • the pixel circuit 120 in one display frame further includes a light emitting phase T21 and a second reset phase T22 after the first reset phase T13.
  • the driving method of the pixel circuit 120 further includes:
  • the first scanning signal terminal Reset, the second scanning signal terminal Gate-N and the third scanning signal terminal Gate-P output non-working levels
  • the light-emitting control signal terminal EM outputs a working level
  • the driving current from the driving transistor DT is transmitted to the light-emitting device EL.
  • the first scan signal terminal Reset outputs a non-working level
  • the first transistor T1 and the sixth transistor T6 electrically connected to the first scan signal terminal Reset are turned off.
  • the second scan signal terminal Gate-N outputs a non-working level
  • the second transistor T2 electrically connected to the second scan signal terminal Gate-N is turned off.
  • the third scan signal terminal Gate-P outputs a non-working level
  • the third transistor T3 electrically connected to the third scan signal terminal Gate-P is turned off.
  • the light-emitting control signal terminal EM outputs a working level
  • the fourth transistor T4 and the fifth transistor T5 electrically connected to the light-emitting control signal terminal EM are turned on.
  • the driving transistor DT is turned on under the control of the voltage (data signal and threshold voltage) of the control electrode N1.
  • the fourth transistor T4 transmits the first voltage signal from the first voltage signal terminal VDD to the first electrode N2 of the driving transistor DT, and the driving transistor DT generates a driving current under the control of the voltage difference between the control electrode N1 and the first electrode N2.
  • the driving current is transmitted to the light emitting device EL through the fifth transistor T5, and the light emitting device EL emits light under the driving of the driving current.
  • the first scan signal terminal Reset outputs a working level
  • the second scan signal terminal Gate-N and the light-emitting control signal terminal EM output a non-working level
  • the reference voltage signal from the reference voltage signal terminal Vref is transmitted to the first electrode N2 of the driving transistor DT via the reset sub-circuit 121.
  • the first scan signal terminal Reset outputs a working level
  • the first transistor T1 and the sixth transistor T6 connected to the first scan signal terminal Reset are turned on
  • the first transistor T1 transmits the reference voltage signal from the reference voltage signal terminal Vref to the first electrode N2 of the driving transistor DT
  • resets the voltage of the first electrode N2 of the driving transistor DT so that the bias state of the driving transistor DT can be adjusted and the hysteresis effect of the driving transistor DT can be reduced.
  • the sixth transistor T6 transmits the initialization signal from the initialization signal terminal Vinit to the anode of the light emitting device EL, and resets the voltage of the anode of the light emitting device EL.
  • the holding frame T20 may include a plurality of light-emitting stages T21 and second reset stages T22 that are alternately arranged.
  • the holding frame T20 may include a plurality of light-emitting stages T21 and second reset stages T22 that are alternately arranged.
  • FIGS. 13A and 13B only one light-emitting stage T21 and one second reset stage T22 are exemplarily shown.
  • the voltage value of the reference voltage signal output by the reference voltage signal terminal Vref in the first reset stage T13 may be the same as or different from the voltage value of the reference voltage signal output in the second reset stage T22.
  • the voltage value of the reference voltage signal from the reference voltage signal terminal Vref in the first reset stage T13 is the first reference voltage signal value V1
  • the voltage value in the second reset stage T22 is the second reference voltage signal value V2.
  • the first reference voltage signal value V1 is equal to the second reference voltage signal value V2, and the first reference voltage signal value V1 and the second reference voltage signal value V2 are negative values.
  • the reference voltage signal terminal Vref outputs reference voltage signals of the same magnitude in the first reset stage T13 and the second reset stage T22, which is conducive to simplifying the driving method of the reference voltage signal terminal, and further simplifying the driving method of the pixel circuit.
  • the first reference voltage signal value is less than the second reference voltage signal value.
  • the first reference voltage signal value V1 is a negative value, so that in the first reset stage T13, the reference voltage signal with the value of the first reference voltage signal value V1 can be used to reset the voltage of the first pole N2 of the driving transistor DT.
  • the second reference voltage signal value V2 is greater than the voltage value of the first voltage signal from the first voltage signal terminal VDD, so that in the second reset stage T22, the second pole N3 of the driving transistor DT serves as the source of the driving transistor DT, and the first pole N2 of the driving transistor DT serves as the drain of the driving transistor DT.
  • the first pole N2 of the driving transistor DT serves as the source of the driving transistor DT
  • the second pole N3 of the driving transistor DT serves as the drain of the driving transistor DT. That is to say, in the light-emitting stage T21 and the second reset stage T22, the source and drain of the driving transistor DT are reversed, so that the driving transistor DT is in two opposite bias states, which is conducive to improving the hysteresis phenomenon of the driving transistor DT and reducing the risk of screen flickering in the display panel 1100.
  • the third scan signal terminal Gate-P outputs a non-operating level, and the data writing subcircuit 123 is turned off.
  • the voltage of the first electrode N2 of the driving transistor DT and the anode of the light emitting device EL is reset.
  • the third scanning signal terminal Gate-P outputs a working level, and the data signal terminal outputs a second reset voltage signal.
  • the data writing subcircuit 123 is turned on, and the second reset voltage signal is transmitted to the second electrode N3 of the driving transistor DT, thereby resetting the voltage of the second electrode N3 of the driving transistor DT.
  • the second reset voltage signal may be a high voltage signal with a positive voltage value, and at the same time, the quasi-voltage signal value V2 output by the reference voltage signal terminal Vref may be a negative number, so that in the second reset stage, the second electrode N3 of the driving transistor DT serves as the source of the driving transistor DT, and the first electrode N2 serves as the drain of the driving transistor DT.
  • the source and drain of the driving transistor DT are reversed, which is beneficial to reducing the hysteresis phenomenon of the driving transistor DT.
  • the second reset voltage signal can also be adjusted according to the data signal in the data writing stage T12. For example, when the refresh frequency of the pixel circuit is 1 Hz, in the second reset stage, the second reset voltage signal can dynamically adjust the size of the second reset voltage signal according to the different grayscales displayed by the light-emitting device EL.
  • the array substrate 100 further includes a first semiconductor layer 11, a first gate conductive layer 12, a second gate conductive layer 13, a second semiconductor layer 14, a third gate conductive layer 15, a first source-drain conductive layer 16, and a second source-drain conductive layer 17, which are sequentially arranged in a direction perpendicular to the substrate 110 and away from the substrate 110.
  • the array substrate 100 further includes at least one insulating layer arranged between any two adjacent conductive layers. The embodiments of the present disclosure will not be described one by one in detail for the insulating layers included in the array substrate 100.
  • two adjacent pixel circuits 120 are symmetrically arranged along the first direction X. Based on this, the structures of two pixel circuits are shown in FIG. 14 to FIG. 22.
  • FIG. 14 is a structural diagram of the first semiconductor layer 11 according to some embodiments.
  • the first semiconductor layer 11 is disposed on a substrate (not shown in the figure), and includes a first semiconductor pattern 111 of a first transistor T1, a third semiconductor pattern 113 of a third transistor T3, and a seventh semiconductor pattern 117 of a driving transistor DT.
  • the third semiconductor pattern 113 and the seventh semiconductor pattern 117 are connected, for example, the region on the third semiconductor pattern 113 used to form the second electrode of the third transistor T3 may be connected to the region on the seventh semiconductor pattern 117 used to form the second electrode of the driving transistor DT, so that the second electrode of the third transistor T3 is connected to the second electrode of the driving transistor DT.
  • the first semiconductor layer 11 also includes a fourth semiconductor pattern 114 of the fourth transistor T4, a fifth semiconductor pattern 115 of the fifth transistor T5 and a sixth semiconductor pattern 116 of the sixth transistor T6.
  • the third semiconductor pattern 113, the fourth semiconductor pattern 114, the fifth semiconductor pattern 115, the sixth semiconductor pattern 116 and the seventh semiconductor pattern 117 are connected to each other as a whole.
  • the third semiconductor pattern 113, the fourth semiconductor pattern 114, the fifth semiconductor pattern 115, the sixth semiconductor pattern 116 and the seventh semiconductor pattern 117 are part of a continuous pattern.
  • FIG15A is a structural diagram of the first gate conductive layer 12 and the first semiconductor layer 11.
  • the first gate conductive layer 12 is located on a side of the first semiconductor layer 11 away from the substrate 110, and the first gate conductive layer 12 includes a first scan signal line RL, a third scan signal line GPL and a first plate C1 of a storage capacitor Cst.
  • the first gate conductive layer 12 may further include a fourth scan signal line EML.
  • the first scan signal line RL partially overlaps with the first semiconductor pattern 111 and the sixth semiconductor pattern 116, and is used to form the control electrodes of the first transistor T1 and the sixth transistor T6.
  • the first semiconductor pattern 111 includes a semiconductor layer of the first transistor T1 overlapping with the first scan signal line RL, and a first electrode of the first transistor T1 (located on the upper side of the first scan signal line RL) and a second electrode of the first transistor T1 (located on the lower side of the first scan signal line RL) located on opposite sides of the first scan signal line RL.
  • the sixth semiconductor pattern 116 includes a semiconductor layer of the sixth transistor T6 overlapping with the first scan signal line RL, a first electrode of the sixth transistor T6 located on the lower side of the first scan signal line RL, and a second electrode of the sixth transistor T6 located on the upper side of the first scan signal line RL.
  • the third scan signal line GPL partially overlaps with the third semiconductor pattern 113 to form a control electrode of the third transistor T3.
  • the third semiconductor pattern 113 includes a semiconductor region of the third transistor T3 overlapping with the third scan signal line GPL, a first electrode of the third transistor T3 located on the upper side of the third scan signal line GPL, and a second electrode of the third transistor T3 located on the upper side of the third scan signal line GPL.
  • the fourth scan signal line EML partially overlaps with the fourth semiconductor pattern 114 and the fifth semiconductor pattern 115, and is used to form a control electrode of the fourth transistor T4 and a control electrode of the fifth transistor T5.
  • the fourth semiconductor pattern 114 includes a semiconductor layer of the fourth transistor T4 overlapping with the fourth scan signal line EML, a first electrode of the fourth transistor T4 located below the fourth scan signal line EML, and a second electrode of the fourth transistor T4 located above the fourth scan signal line EML.
  • the fifth semiconductor pattern 115 includes a semiconductor layer of the fifth transistor T5 overlapping with the fourth scan signal line EML, a first electrode of the fifth transistor T5 located above the fourth scan signal line EML, and a second electrode of the fifth transistor T5 located below the fourth scan signal line EML.
  • the second electrode of the third semiconductor pattern 113, the first electrode of the fifth semiconductor pattern 115 and the second electrode of the seventh semiconductor pattern 117 are connected to form the second electrode N3 of the driving transistor DT.
  • the second electrode of the fourth transistor T4 is connected to the first electrode N2 of the driving transistor DT.
  • FIG. 15B is a structural diagram of the semiconductor layer 11 and the first gate conductive layer 12 when the third transistor T3 is a dual-gate transistor.
  • the third semiconductor pattern 113 is an L-shaped structure, and the third semiconductor pattern 113 includes a first extension segment 1131 and a second extension segment 1132.
  • the first extension segment 1131 extends along a first direction
  • the second extension segment 1132 extends along a second direction and is connected to the first extension segment 1131.
  • the third scan signal line GPL includes a main portion GPL1 extending along the first direction X and a protruding portion GPL2 extending along the second direction Y.
  • the main portion GPL1 partially overlaps the second extension section 1132
  • the protruding portion GPL2 partially overlaps the first extension section 1131 .
  • the data signal terminal Data is electrically connected to a side of the protruding portion GPL2 of the first extending section 1131 away from the second extending section 1132 .
  • FIG. 16A is a structural diagram when the second gate conductive layer 13 does not include the auxiliary second scanning signal line GNL'.
  • the second gate conductive layer 13 is located on the side of the first gate conductive layer 12 away from the substrate 110.
  • the second gate conductive layer 13 includes a second electrode plate C2 of the storage capacitor Cst. In the orthographic projection onto the substrate 110, the second electrode plate C2 partially overlaps with the first electrode plate C1. Exemplarily, a avoidance hole C21 is provided in the middle of the second electrode plate C2.
  • FIG. 16B is a structural diagram when the second gate conductive layer 13 includes the auxiliary second scan signal line GNL′.
  • the second gate conductive layer 13 includes the second electrode plate C2 of the storage capacitor Cst and the auxiliary second scan signal line GNL′.
  • the auxiliary second scan signal line GNL′ is configured to transmit the second scan signal together with the second scan signal line GNL.
  • the second semiconductor layer 14 is located on the side of the second gate conductive layer 13 away from the substrate.
  • Fig. 17 is a structural diagram of the array substrate from the semiconductor layer 11 to the second semiconductor layer 14.
  • the second semiconductor layer 14 includes a second semiconductor pattern 141 of the second transistor T2.
  • the third gate conductive layer 15 is located on the side of the second semiconductor layer 14 away from the substrate 110.
  • Fig. 18A is a structural diagram of the array substrate from the first semiconductor layer to the third gate conductive layer.
  • the third gate conductive layer 15 includes a second scanning signal line GNL and a reference voltage signal line VL.
  • the second scan signal line GNL partially overlaps with the second semiconductor pattern 141, and the second semiconductor pattern 141 includes a semiconductor layer of a second transistor T2 overlapping with the second scan signal line GNL, a first electrode of the second transistor T2 located above the second scan signal line GNL, and a second electrode of the second transistor T2 below the second scan signal line GNL.
  • the reference voltage signal line VL is used to transmit a reference voltage signal and form a reference voltage signal terminal Vref.
  • the second scan signal line GNL at least partially overlaps with the orthographic projection of the auxiliary second scan signal line GNL' on the substrate.
  • FIG19A is a structural diagram of the array substrate from the first semiconductor layer to the first source-drain conductive layer.
  • the first source-drain conductive layer 16 includes a first connection pattern 161, a second connection pattern 162, and a third connection pattern 163.
  • the first connection pattern 161 is connected to the reference voltage signal line VL and the first electrode of the first semiconductor pattern 111 , so that the first electrode of the first transistor T1 is electrically connected to the reference voltage signal terminal Vref.
  • the second connection pattern 162 is connected to the second electrode of the first semiconductor pattern 111, the first electrode of the second semiconductor pattern 141, and the first electrode of the seventh semiconductor pattern 117.
  • the second electrode of the first transistor T1 is electrically connected to the first electrode of the second transistor T2 and the first electrode of the driving transistor DT.
  • the second connection pattern 162 is also electrically connected to the second electrode of the fourth semiconductor pattern 114.
  • the third connection pattern 163 is connected to the second electrode of the second semiconductor pattern 141 and the first electrode plate C1 of the storage capacitor Cst. In the orthographic projection onto the substrate 110, the third connection pattern 163 partially overlaps the avoidance hole C21 of the second electrode plate C2 of the storage capacitor Cst, and the third connection pattern 163 passes through the avoidance hole C21 to connect to the first electrode plate C1.
  • the first source-drain conductive layer 16 further includes a fourth connection pattern 164 , and the fourth connection pattern 164 is electrically connected to the first electrode of the fourth semiconductor pattern 114 .
  • the first source-drain conductive layer 16 further includes a fifth connection pattern 165 , which is used to connect the pixel circuit and the anode of the light emitting device.
  • the second source-drain conductive layer 17 is located on a side of the first source-drain conductive layer 16 away from the substrate 110.
  • the second source-drain conductive layer 17 includes a data line DL, which is connected to a first electrode of the third semiconductor pattern (not shown in the figure).
  • the second electrode of the third semiconductor pattern 113 is connected to a second electrode of the seventh semiconductor pattern 117 (as shown in FIG15A ).
  • FIG20 is a structural diagram of the array substrate.
  • the second source-drain conductive layer 17 may further include a first voltage signal line VDDL.
  • the first voltage signal line VDDL is used to form a first voltage signal terminal VDD.
  • the first voltage signal line VDDL is electrically connected to the fourth connection pattern 164 .
  • the second source-drain conductive layer 17 may further include a transfer block 171 , which is connected to the fifth connection pattern 165 and is used to connect the pixel circuit 120 to the light emitting device EL.
  • the second semiconductor pattern 141 in the orthographic projection onto the substrate 110, partially overlaps with the third scan signal line GPL.
  • the second electrode of the second semiconductor pattern 141 overlaps with the third scan signal line GPL, and a parasitic capacitor is formed in the overlapping region, and the second electrode of the second semiconductor pattern 141 is connected to the first electrode plate C1 of the storage capacitor Cst (as shown in FIG. 19A ). Based on this, the coupling effect between the third scan signal line GPL and the first electrode plate C1 can be improved.
  • the third scan signal line GPL outputs the third scan signal
  • the voltage of the second electrode of the second semiconductor pattern 141 increases under the bootstrap effect of the capacitor, and the voltage of the first electrode plate C1 increases, which is conducive to improving the efficiency of data signal transmission to the first electrode plate C1.
  • FIG. 18B is a partial enlarged view of A1 in FIG. 18A .
  • the second semiconductor pattern 141 includes a first portion 1411 and a second portion 1412 .
  • the first portion 1411 is located on a side (lower side) of the second scan signal line GNL close to the storage capacitor Cst in an orthographic projection onto the substrate, and the first portion 1411 overlaps the third scan signal line GPL.
  • the second portion 1412 is connected to the first portion 1411 and extends along a second direction Y, which is perpendicular to the first direction X. In an orthographic projection onto the substrate 110, the second portion 1412 intersects the second scanning signal line GNL.
  • the portion of the second portion 1412 overlapping the second scanning signal line GNL forms a semiconductor layer of the second transistor T2, and the portion of the second scanning signal line GNL away from the storage capacitor Cst (upper side) forms a first electrode of the second transistor T2.
  • the size of the first portion 1411 is larger than the size of the third scanning signal line GPL, and in the orthographic projection to the substrate 110, the two ends of the first portion 1411 are respectively located on both sides of the third scanning signal line GPL.
  • the edges of the first portion 1411 on both sides along the first direction Y are located outside the third scanning signal line GPL, which is beneficial to increase the facing area between the second semiconductor pattern 141 and the third scanning signal line GPL, and enhance the coupling effect between the second electrode of the second semiconductor pattern 141 and the third scanning signal line GPL.
  • the second connection pattern 162 extends along the second direction Y, and in the orthographic projection to the substrate 110, the second portion 1412 overlaps the second connection pattern 162. In this way, the second connection pattern 162 can shield or reduce the interference of the signal located on the side of the first source-drain conductive layer away from the substrate 110 to the second semiconductor pattern 141.
  • FIG. 19B is a partial enlarged view of A2 in FIG. 19A .
  • FIG. 21 is a structural diagram when the second semiconductor pattern 141 is separated from the second connection pattern.
  • the second semiconductor pattern 141 extends along the second direction Y, and in the orthographic projection onto the substrate, the second semiconductor pattern 141 and the second connection pattern 162 are separated from each other.
  • the second semiconductor pattern 141 forms a long strip structure, which is conducive to simplifying the structure of the second semiconductor pattern 141, thereby reducing the difficulty of manufacturing the second semiconductor pattern 141 and reducing the difficulty of manufacturing the display panel 1100.
  • the third connection pattern 163 partially overlaps the third scan signal line GPL in an orthographic projection onto the substrate 110 .
  • FIG22 is a structural diagram when the third connection pattern is located below the third scan signal line GPL.
  • the third connection pattern 163 is located on the side (lower side) of the third scan signal line GPL close to the storage capacitor Cst; the third connection pattern 163 partially overlaps with the second semiconductor pattern 141, and the overlapping portion of the third connection pattern 163 and the second semiconductor pattern 141 is located on the side of the third scan signal line GPL close to the storage capacitor Cst.
  • a portion of the third scan signal line GPL is bent toward a side (upper side) away from the storage capacitor Cst to form a concave portion 128 , and a portion where the third connection pattern 163 and the second semiconductor pattern 141 overlap on the substrate is located in the concave portion 128 .
  • the light emitting device EL includes an anode 18, a light emitting functional layer 19 and a cathode layer 21 arranged in sequence in a direction perpendicular to the substrate 110 and away from the substrate 110.
  • the pixel circuit 120 is electrically connected to the anode 18 of the light emitting device EL through the adapter block 171.
  • the encapsulation layer 200 may include a first inorganic material layer 201, an organic material layer 202, and a second inorganic material layer 203 arranged in sequence in a direction perpendicular to the substrate 110 and away from the substrate 110.
  • the first inorganic material layer 201 and the second inorganic material layer 203 can isolate water and oxygen, reduce the external water and oxygen from corroding the film structure below the encapsulation layer 200 (close to the side of the substrate 11), especially reduce the risk of water and oxygen corroding the light-emitting functional layer 19, and improve the service life of the display panel 1100.
  • the organic material layer 202 can be used to flatten the light-emitting surface of the display panel 1100, and can be used to absorb and release the stress of the display panel 1100.

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Abstract

一种像素电路，包括驱动晶体管、重置子电路、防漏电子电路和数据写入子电路。重置子电路与第一扫描信号端、基准电压信号端和驱动晶体管的第一极电连接，被配置为在第一扫描信号的控制下，将基准电压信号传输至驱动晶体管的第一极。防漏电子电路与第二扫描信号端、驱动晶体管的第一极和控制极电连接，被配置为在第二扫描信号的控制下，将驱动晶体管的第一极与控制极连通。数据写入子电路与第三扫描信号端、数据信号端和驱动晶体管的第二极电连接，被配置为在第三扫描信号的控制下，将数据信号传输至驱动晶体管的第二极。其中，在防漏电子电路开启时，重置子电路和数据写入子电路依次开启。在防漏电子电路关闭时，重置子电路开启至少一次。

Description

像素电路及其驱动方法、阵列基板、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种像素电路及其驱动方法、阵列基板、显示装置。
背景技术
有机发光二极管(英文全称：Organic Light-Emitting Diode；简称：OLED)显示面板具有主动发光、广视角、对比度高、响应速度快、耗电低等优点，广泛应用于手机、平板电脑、数码相机等显示产品，因此受到广泛关注。
发明内容
一方面，提供一种像素电路。所述像素电路包括驱动晶体管、重置子电路、防漏电子电路和数据写入子电路。所述驱动晶体管包括控制极、第一极和第二极。所述重置子电路与第一扫描信号端、基准电压信号端和所述驱动晶体管的第一极电连接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将来自所述基准电压信号端的基准电压信号传输至所述驱动晶体管的第一极。所述防漏电子电路与第二扫描信号端、所述驱动晶体管的第一极和所述驱动晶体管的控制极电连接，被配置为在来自所述第二扫描信号端的第二扫描信号的控制下，将所述驱动晶体管的第一极与控制极连通。所述数据写入子电路与第三扫描信号端、数据信号端和所述驱动晶体管的第二极电连接，被配置为在来自所述第三扫描信号端的第三扫描信号的控制下，将来自所述数据信号端的数据信号传输至所述驱动晶体管的第二极。其中，在所述防漏电子电路开启时，所述重置子电路和所述数据写入子电路依次开启。在所述防漏电子电路关闭时，所述重置子电路开启至少一次。
在一些实施例中，所述重置子电路包括第一晶体管，所述防漏电子电路包括第二晶体管，所述数据写入子电路包括第三晶体管。所述第一晶体管的控制极与所述第一扫描信号端电连接，第一极与所述基准电压信号端电连接，第二极与所述驱动晶体管的第一极电连接。所述第二晶体管的控制极与所述第二扫描信号端电连接，第一极与所述驱动晶体管的第一极电连接，第二极与所述驱动晶体管的控制极电连接。所述第三晶体管的控制极与所述第三扫描信号端电连接，第一极与所述数据信号端电连接，第二极与所述驱动晶体管的第二极电连接。
在一些实施例中，所述第二晶体管为金属氧化物薄膜晶体管。所述第一晶体管、所述第三晶体管和所述驱动晶体管为低温多晶硅薄膜晶体管。
在一些实施例中，在所述防漏电子电路关闭时，所述重置子电路开启一次或两次。
在一些实施例中，在所述防漏电子电路关闭时，所述数据写入子电路开启至少一次，且所述数据信号端输出第一复位电压信号。
在一些实施例中，所述像素电路还包括第一控制子电路、第二控制子电路、复位子电路和储能子电路。所述第一控制子电路与发光控制信号端、第一电压信号端和所述驱动晶体管的第一极电连接，被配置为在来自所述发光控制信号端的发光控制信号的控制下，将来自所述第一电压信号端的第一电压信号传输至所述驱动晶体管的第一极。所述第二控制子电路与所述发光控制信号端、所述驱动晶体管的第二极和发光器件电连接，被配置为在所述发光控制信号的控制下，将来自所述驱动晶体管的驱动电流传输至所述发光器件。所述复位子电路与所述第一扫描信号端、初始化信号端和所述发光器件电连接，被配置为在所述第一扫描信号的控制下，将来自所述初始化信号端的初始化信号传输至所述发光器件。所述储能子电路与所述驱动晶体管的控制极和所述第一电压信号端电连接，被配置为维持所述驱动晶体管的控制极的电压。
在一些实施例中，所述第一控制子电路包括第四晶体管，所述第二控制子电路包括第五晶体管，所述复位子电路包括第六晶体管，所述储能子电路包括存储电容器。所述第四晶体管的控制极与所述发光控制信号端电连接，第一极与所述第一电压信号端电连接，第二极与所述驱动晶体管的第一极电连接。所述第五晶体管的控制极与所述发光控制信号端电连接，第一极与所述驱动晶体管的第二极电连接，第二极与所述发光器件电连接。所述第六晶体管的控制极与所述第一扫描信号端电连接，第一极与所述初始化信号端电连接，第二极与所述发光器件电连接。所述存储电容器的第一极板与所述驱动晶体管的控制极电连接，第二极板与所述第一电压信号端电连接。
另一方面，还提供一种像素电路的驱动方法，所述驱动方法用于驱动上述任一实施例中所述的像素电路。一个显示帧包括复位阶段、数据写入阶段和第一重置阶段。所述驱动方法包括：在所述复位阶段，第一扫描信号端和第二扫描信号端输出工作电平，第三扫描信号端输出非工作电平；来自基准电压信号端的基准电压信号经重置子电路和防漏电子电路传输至驱动晶体管的控制极。在所述数据写入阶段，所述第一扫描信号端输出非工作电平，所述第二扫描信号端和所述第三扫描信号端输出工作电平，所述数据信号端输出数据信号。所述数据信号经数据写入子电路传输至所述驱动晶体管的第二 极，且所述驱动晶体管的控制极写入所述数据信号和阈值电压。在所述第一重置阶段，所述第一扫描信号端输出至少一次工作电平，所述第二扫描信号端输出非工作电平。所述基准电压信号经所述重置子电路传输至所述驱动晶体管的第一极。
在一些实施例中，所述像素电路包括第一刷新频率和第二刷新频率，所述第一刷新频率小于所述第二刷新频率。在所述第一刷新频率下，所述像素电路在一个显示帧还包括在所述第一重置阶段之后的发光阶段和第二重置阶段。所述驱动方法还包括：在所述发光阶段，所述第一扫描信号端、所述第二扫描信号端和所述第三扫描信号端输出非工作电平，发光控制信号端输出工作电平；来自所述驱动晶体管的驱动电流传输至发光器件。在所述第二重置阶段，所述第一扫描信号端输出工作电平，所述第二扫描信号端、所述第三扫描信号端和所述发光控制信号端输出非工作电平；来自基准电压信号端的基准电压信号经所述重置子电路传输至所述驱动晶体管的第一极。
在一些实施例中，来自基准电压信号端的基准电压信号在所述第一重置阶段的电压值为第一基准电压信号值，在所述第二重置阶段的电压值为第二基准电压信号值。所述第一基准电压信号值等于所述第二基准电压信号值，且所述第一基准电压信号值和所述第二基准电压信号值为负值。或者，所述第一基准电压信号值小于所述第二基准电压信号值，所述第一基准电压信号值为负值，所述第二基准电压信号值大于来自第一电压信号端的第一电压信号的电压值。
又一方面，还提供了一种阵列基板。所述阵列基板包括衬底和设置于衬底上且阵列式布置的多个像素电路。像素电路为上述任一实施例中所述的像素电路。
在一些实施例中，像素电路包括驱动晶体管、第一晶体管、第三晶体管和存储电容器。所述阵列基板还包括设置于衬底上的第一半导体层、第一栅导电层和第二栅导电层。所述第一半导体层包括所述第一晶体管的第一半导体图案、所述第三晶体管的第三半导体图案和所述驱动晶体管的第七半导体图案，其中，第三半导体图案和所述第七半导体图案相连，且与所述第一半导体图案具有间隔。所述第一栅导电层位于所述第一半导体层远离所述衬底的一侧，包括第一扫描信号线、第三扫描信号线和所述存储电容器的第一极板。所述第二栅导电层位于所述第一栅导电层远离所述衬底的一侧，包括所述存储电容器的第二极板。
在一些实施例中，所述像素电路还包括第二晶体管。所述阵列基板还包 括第二半导体层、第三栅导电层、第一源漏导电层和第二源漏导电层。所述第二半导体层位于所述第二栅导电层远离所述衬底的一侧，包括所述第二晶体管的第二半导体图案。所述第三栅导电层位于所述第二半导体层远离所述衬底的一侧，包括第二扫描信号线和基准电压信号线。所述第一源漏导电层位于所述第三栅导电层远离所述衬底的一侧，包括第一连接图案、第二连接图案和第三连接图案。所述第一连接图案与所述基准电压信号线和所述第一半导体图案的第一极连接。所述第二连接图案与所述第一半导体图案的第二极、所述第二半导体图案的第一极和所述第七半导体图案的第一极连接。所述第三连接图案与所述第二半导体图案的第二极和所述存储电容器的第一极板连接。所述第二源漏导电层位于所述第一源漏导电层远离所述衬底的一侧，包括数据线。所述数据线与所述第三半导体图案的第一极连接。所述第三半导体图案的第二极与所述第七半导体图案的第二极连接。
在一些实施例中，在向所述衬底的正投影中，所述第二半导体图案与所述第三扫描信号线部分交叠。
在一些实施例中，所述第二半导体图案包括第一部分和第二部分。在向所述衬底的正投影中，所述第一部分位于所述第二扫描信号线靠近所述存储电容器的一侧，且与所述第三扫描信号线交叠。所述第二部分与所述第一部分相连，且沿第二方向延伸。在向所述衬底的正投影中，所述第二部分与所述第二扫描信号线交叉。其中，沿所述第二方向，所述第一部分的尺寸大于所述第三扫描信号线的尺寸，且在向所述衬底的正投影中，所述第一部分的两端分别位于第三扫描信号线的两侧。所述第二方向与第一方向交叉。
在一些实施例中，所述第二连接图案沿所述第二方向延伸，在向所述衬底的正投影中，所述第二部分与所述第二连接图案交叠。
在一些实施例中，所述第二半导体图案沿第二方向延伸，在向所述衬底上的正投影中，所述第二半导体图案与所述第二连接图案相互分离。
在一些实施例中，在向所述衬底的正投影中，所述第三连接图案与所述第三扫描信号线部分交叠。
在一些实施例中，在向所述衬底上的正投影中，所述第三连接图案位于所述第三扫描信号线靠近所述存储电容器的一侧。所述第三连接图案与所述第二半导体图案部分交叠，且交叠部分位于所述第三扫描信号线靠近所述存储电容器的一侧。
在一些实施例中，所述第三扫描信号线的部分向远离所述存储电容器的一侧弯折形成凹部。所述第三连接图案与所述第二半导体图案在所述衬底上 相互交叠的部分位于所述凹部内。
在一些实施例中，所述第三半导体图案为L型结构。所述第三半导体图案包括第一延伸段和第二延伸段。所述第一延伸段沿第一方向延伸。所述第二延伸段沿第二方向延伸，且与所述第一延伸段相连。所述第一方向为所述多个子像素排列的行方向，所述第二方向与所述第一方向交叉。所述第三扫描信号线包括主体部和凸出部。所述主体部沿所述第一方向延伸，且所述主体部在所述衬底上的正投影，与所述第二延伸段部分交叠。所述凸出部沿所述第二方向延伸，且所述凸出部在所述衬底上的正投影，与所述第一延伸段部分交叠。
在一些实施例中，所述第二栅导电层还包括辅助第二扫描信号线。所述辅助第二扫描信号线被配置为传输第二扫描信号，在向所述衬底上的正投影中，所述辅助第二扫描信号线与所述第二扫描信号线在所述衬底上的正投影交叠。
再一方面，提供一种显示装置。所述显示装置包括发光器件和上述任一实施例中所述的阵列基板。所述发光器件设置于所述阵列基板上，所述发光器件与所述阵列基板的像素电路电连接，被配置为在所述像素电路的控制下发光。
附图说明
为了更清楚地说明本公开中的技术方案，下面将对本公开一些实施例中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例的附图，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图。此外，以下描述中的附图可以视作示意图，并非对本公开实施例所涉及的产品的实际尺寸、方法的实际流程、信号的实际时序等的限制。
图1为根据一些实施例的显示面板的一种结构图；
图2为根据一些实施例的显示面板的另一种结构图；
图3为根据一些实施例的显示面板的截面结构图；
图4为根据一些实施例的像素电路的一种结构框图；
图5为根据一些实施例的像素电路的一种结构图；
图6为根据一些实施例的像素电路的另一种结构框图；
图7A为根据一些实施例的像素电路的另一种结构图；
图7B为根据一些实施例的像素电路的又一种结构图；
图8为根据一些实施例的栅极驱动电路与像素电路的连接关系图；
图9为根据一些实施例的像素电路的一种驱动时序图；
图10为根据一些实施例的像素电路的另一种驱动时序图；
图11为根据一些实施例的像素电路的又一种驱动时序图；
图12为根据一些实施例的像素电路的又一种驱动时序图；
图13A为根据一些实施例的像素电路的又一种驱动时序图；
图13B为根据一些实施例的像素电路的又一种驱动时序图；
图14～图22为根据一些实施例的阵列基板的结构图。
具体实施方式
下面将结合附图，对本公开一些实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。基于本公开所提供的实施例，本领域普通技术人员所获得的所有其他实施例，都属于本公开保护的范围。
除非上下文另有要求，否则，在整个说明书和权利要求书中，术语“包括(comprise)”及其其他形式例如第三人称单数形式“包括(comprises)”和现在分词形式“包括(comprising)”被解释为开放、包含的意思，即为“包含，但不限于”。在说明书的描述中，术语“一个实施例(one embodiment)”、“一些实施例(some embodiments)”、“示例性实施例(exemplary embodiments)”、“示例(example)”、“特定示例(specific example)”或“一些示例(some examples)”等旨在表明与该实施例或示例相关的特定特征、结构、材料或特性包括在本公开的至少一个实施例或示例中。上述术语的示意性表示不一定是指同一实施例或示例。此外，所述的特定特征、结构、材料或特点可以以任何适当方式包括在任何一个或多个实施例或示例中。
以下，术语“第一”、“第二”仅用于描述目的，而不能理解为指示或暗示相对重要性或者隐含指明所指示的技术特征的数量。由此，限定有“第一”、“第二”的特征可以明示或者隐含地包括一个或者更多个该特征。在本公开实施例的描述中，除非另有说明，“多个”的含义是两个或两个以上。
在描述一些实施例时，可能使用了“耦接”和“连接”及其衍伸的表达。例如，描述一些实施例时可能使用了术语“连接”以表明两个或两个以上部件彼此间有直接物理接触或电接触。又如，描述一些实施例时可能使用了术语“耦接”以表明两个或两个以上部件有直接物理接触或电接触。然而，术语“耦接”或“通信耦合(communicatively coupled)”也可能指两个或两个以上部件彼此间并无直接接触，但仍彼此协作或相互作用。这里所公开的实施例并不必然限制于本文内容。
“A、B和C中的至少一个”与“A、B或C中的至少一个”具有相同含义，均包括以下A、B和C的组合：仅A，仅B，仅C，A和B的组合，A和C的组合，B和C的组合，及A、B和C的组合。
“A和/或B”，包括以下三种组合：仅A，仅B，及A和B的组合。
本文中“适用于”或“被配置为”的使用意味着开放和包容性的语言，其不排除适用于或被配置为执行额外任务或步骤的设备。
另外，“基于”的使用意味着开放和包容性，因为“基于”一个或多个所述条件或值的过程、步骤、计算或其他动作在实践中可以基于额外条件或超出所述的值。
如本文所使用的那样，“约”、“大致”或“近似”包括所阐述的值以及处于特定值的可接受偏差范围内的平均值，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。
如本文所使用的那样，“平行”、“垂直”、“相等”包括所阐述的情况以及与所阐述的情况相近似的情况，该相近似的情况的范围处于可接受偏差范围内，其中所述可接受偏差范围如由本领域普通技术人员考虑到正在讨论的测量以及与特定量的测量相关的误差(即，测量系统的局限性)所确定。例如，“平行”包括绝对平行和近似平行，其中近似平行的可接受偏差范围例如可以是5°以内偏差；“垂直”包括绝对垂直和近似垂直，其中近似垂直的可接受偏差范围例如也可以是5°以内偏差。“相等”包括绝对相等和近似相等，其中近似相等的可接受偏差范围内例如可以是相等的两者之间的差值小于或等于其中任一者的5％。
应当理解的是，当层或元件被称为在另一层或基板上时，可以是该层或元件直接在另一层或基板上，或者也可以是该层或元件与另一层或基板之间存在中间层。
本文参照作为理想化示例性附图的剖视图和/或平面图描述了示例性实施方式。在附图中，为了清楚，放大了层和区域的厚度。因此，可设想到由于例如制造技术和/或公差引起的相对于附图的形状的变动。因此，示例性实施方式不应解释为局限于本文示出的区域的形状，而是包括因例如制造而引起的形状偏差。例如，示为矩形的蚀刻区域通常将具有弯曲的特征。因此，附图中所示的区域本质上是示意性的，且它们的形状并非旨在示出设备的区域的实际形状，并且并非旨在限制示例性实施方式的范围。
本公开的实施例中，晶体管的控制极为晶体管的栅极，第一极为晶体管 的源极和漏极中一者，第二极为晶体管的源极和漏极中另一者。由于晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的，也就是说，本公开的实施例中的晶体管的第一极和第二极在结构上可以是没有区别的。示例性的，在本公开的实施例中，驱动晶体管的第一极(或第二极)在一个显示帧的不同阶段可以为源极或者漏极，也就是说，在一个显示帧的不同阶段，驱动晶体管的源极和漏极可以互换(驱动晶体管的源极和漏极反转)。其他的晶体管(除驱动晶体管之外的所有晶体管)的第一极为源极，第二极为漏极。
本公开的实施例提供了一种显示装置1000，参阅图1，显示装置1000可以是显示不论运动(例如，视频)还是固定(例如，静止图像)的，且不论是文字的还是图像的任何装置。示例性地，该显示装置1000可以为电视机、笔记本电脑、平板电脑、手机、电子相片、电子广告牌或指示牌、个人数字助理(英文全称：Personal Digital Assistant；简称：PDA)、导航仪、可穿戴设备、增强现实(英文全称：Augmented Reality；简称：AR)设备、虚拟现实(英文全称：Virtual Reality；简称：VR)设备等任何具有显示功能的产品或者部件。
上述显示装置1000可以为电致发光显示装置或光致发光显示装置。在该显示装置1000为电致发光显示装置的情况下，电致发光显示装置可以是有机电致发光二极管(英文全称：Organic Light-Emitting Diode；简称：OLED)显示装置或者量子点电致发光二极管(英文全称：Quantum Dot Light Emitting Diodes；简称：QLED)显示装置。
在一些实施例中，参阅图2，显示装置1000包括显示面板1100和驱动电路板(英文全称：Source Printed Circuit Board；简称：SPCB)1200。
如图2所示，显示面板1100可以包括显示区AA和周边区BB(也可以叫非显示区)。周边区BB至少位于显示区AA一侧，本公开的实施例中，如图2所示，以周边区BB围绕显示区AA为例进行描述。
显示区AA可以包括多个子像素(英文全称：Sub Pixel)P、多条数据线DL和多条扫描信号线(第一扫描信号线RL、第二扫描信号线GNL、第三扫描信号线GPL和第四扫描信号线EML)。其中，子像素P包括像素电路120和发光器件EL。多个子像素P排列成多行和多列，每行包括沿第一方向X排列的多个子像素P，即第一方向X为一行子像素P的排列方向，多行子像素P沿第二方向Y排列。每列包括沿第二方向Y排列的多个子像素P，即第二方向Y为一列子像素P的排列方向；多列子像素P沿第一方向X排列。其中，第一方向X和第二方向Y交叉，比如，第一方向X与第二方向Y垂直。
参阅图3，显示面板1100可以包括阵列基板100、设置于阵列基板100上的发光器件EL和设置于发光器件EL上的封装层200。
阵列基板100包括衬底110和设置于衬底110上的多个像素电路120。像素电路120可以包括多个薄膜晶体管(英文全称：Thin Film Transistor；简称：TFT)和一个存储电容器Cst，其中图3中仅示例性地展示了两个薄膜晶体管(第五晶体管T5和第二晶体管T2)。
如图2所示，多个像素电路的排列方式可以与多个子像素P排列方式相似的，即多个像素电路排列成多行和多列。多个像素电路排列的行方向，与多个子像素P排列的行方向平行，也就是说，第一方向X也可以认为是多个像素电路排列的行方向。
如图2所示，周边区BB可以至少包括栅极驱动电路130和源极驱动器140。栅极驱动电路130可以包括多个移位寄存器(英文全称：Gate Driver On Array；简称：GOA)，每个移位寄存器通过一条栅线与至少一行像素电路120电连接(参阅下文)。源极驱动器140比如可以是源极驱动芯片(英文全称：Source Driver IC)。
驱动电路板1200可以包括时序控制器(英文全称：Timing Controller；简称：TCON)，电源管理芯片DC/DC和可调电阻分压电路(用于生成Vcom)等驱动电路。驱动电路板1200与源极驱动器140电连接，以控制源极驱动器140输出数据信号。以及，驱动电路板1200与栅极驱动电路130电连接，以将控制信号传输至移位寄存器中，使得相应的移位寄存器对多行像素电路120进行逐行扫描。显示面板1100在驱动电路板1200、源极驱动器140、栅极驱动电路130、像素电路120以及发光器件EL等电子元件和电路的共同作用下实现图像显示。
像素电路120包括驱动晶体管DT，驱动晶体管的沟道本身因为缺陷态多而显现出明显的磁滞效应。驱动晶体管的磁滞效应指的是在一定的偏压下，驱动晶体管的电特性所表现出来的一种不确定性，即驱动晶体管的电流的大小不仅与当前的偏压有关，还与前一时段的偏压状态相关。比如上一时刻(前一个帧周期)的图像往往会保留在下一时刻的图像显示中，从而导致上述画面闪烁的显示问题。
相关技术中，为了改善上述驱动晶体管的磁滞效应，通常在像素电路中增加一个重置晶体管，重置晶体管比如可以用于对驱动晶体管的源极进行电压重置(也可以称为电压复位或电压初始化)，进而调节驱动晶体管的偏置状态，改善驱动晶体管的磁滞效应。但是，相关技术中提供的像素电路，会 增加像素电路所包含的晶体管的数量，进而增加像素电路所占用的空间，不利于提升显示面板的像素密度(英文全称：Pixels Per Inch；简称：PPI)。
为了解决上述技术问题，本公开的一些实施例还提供了一种像素电路120。参阅图4，像素电路120包括驱动晶体管DT，重置子电路121、防漏电子电路122和数据写入子电路123。驱动晶体管DT包括控制极N1、第一极N2和第二极N3。
重置子电路121与第一扫描信号端Reset、基准电压信号端Vref和驱动晶体管DT的第一极N2电连接。重置子电路121被配置为在来自第一扫描信号端Reset的第一扫描信号的控制下，将来自基准电压信号端Vref的基准电压信号传输至驱动晶体管DT的第一极N2。
防漏电子电路122与第二扫描信号端Gate-N、驱动晶体管DT的第一极N2和驱动晶体管DT的控制极N1电连接。防漏电子电路122被配置为在来自第二扫描信号端Gate-N的第二扫描信号的控制下，将驱动晶体管DT的第一极N2与控制极N1连通。
数据写入子电路123与第三扫描信号端Gate-P、数据信号端Data和驱动晶体管DT的第二极N3电连接。数据写入子电路123被配置为在来自第三扫描信号端Gate-P的第三扫描信号的控制下，将来自数据信号端Data的数据信号传输至驱动晶体管DT的第二极N3。
在防漏电子电路122开启时，重置子电路121和数据写入子电路123依次开启。
防漏电子电路122开启是指：防漏电子电路122在第二扫描信号的控制下，将驱动晶体管DT的第一极N2与控制极N1连通。重置子电路121开启是指：重置子电路121在第一扫描信号的控制下，将来自基准电压信号端Vref的基准电压信号传输至驱动晶体管DT的第一极N2。数据写入子电路123开启是指：数据写入子电路123在来自第三扫描信号端Gate-P的第三扫描信号的控制下，将数据信号传输至驱动晶体管DT的第二极N3。
如图9所示，一个显示帧可以包括刷新帧T10和位于刷新帧T10之后的保持帧T20，且刷新帧T10可以包括依次设置的复位阶段T11、数据写入阶段T12和第一重置阶段T13。
示例性地，防漏电子电路122在复位阶段T11和数据写入阶段T12开启，且重置子电路121在复位阶段T11开启，数据写入子电路123在数据写入阶段T12开启。
基于上述示例，在复位阶段T11，防漏电子电路122在第二扫描信号的控 制下，将驱动晶体管DT的第一极N2与控制极N1连通。重置子电路121在第一扫描信号的控制下，将基准电压信号传输至驱动晶体管DT的第一极N2，进一步的，基准电压信号从驱动晶体管DT的第一极N2传输至驱动晶体管DT的控制极N1。基于此，在防漏电子电路122和重置子电路121同时开启的时候，来自基准电压信号端Vref的基准电压信号可以传输至驱动晶体管DT的控制极N1，实现对驱动晶体管DT的控制极N1的电压重置(也可以称为：电压初始化或者电压复位)。
在数据写入阶段T12，防漏电子电路122在第二扫描信号的控制下，将驱动晶体管DT的第一极N2与控制极N1连通。数据写入阶段T12在第三扫描信号的控制下，将数据信号传输至驱动晶体管DT的第二极N3，并由驱动晶体管DT的第二极N3经补偿后传输至驱动晶体管DT的第一极N2，然后经防漏电子电路122传输至驱动晶体管DT的控制极N1，实现对驱动晶体管DT的阈值电压补偿和数据信号的写入。
在防漏电子电路122关闭时，重置子电路121开启至少一次。防漏电子电路122关闭是指，第二扫描信号端不输出第二扫描信号(输出非工作电平)，重置子电路121不能将驱动晶体管DT的第一极N2与控制极N1导通，也就是说，驱动晶体管DT的第一极N2与控制极N1之间不能通过防漏电子电路122传输电信号。
示例性地，在第一重置阶段T13，防漏电子电路122关闭，重置子电路121在第一扫描信号的控制下，将基准电压信号传输至驱动晶体管DT的第一极N2，且基准电压信号没有进一步传输至电路的其他节点处。这样，重置子电路121可以实现对驱动晶体管DT的第一极N2的电压重置，进而调节驱动晶体管DT的偏置状态(调节驱动晶体管DT的栅极与源极之间的电压差Vgs)，改善驱动晶体管的磁滞效应。
本公开的实施例中，重置子电路121既可以用于对驱动晶体管DT的控制极N1的电压重置，还可以用于对驱动晶体管DT的第一极N2的电压重置。也就是说，重置子电路121能够实现两种功能(分别对驱动晶体管DT的控制极N1和第一极N2进行电压重置)，这样，可以减少设置一个(用于对驱动晶体管DT的控制极N1进行电压重置)复位晶体管，进而减少像素电路120包含的晶体管的数量，有利于降低像素电路120占用的空间，提升显示面板1100的像素密度。
而且，相较于相关技术中提供的像素电路，重置子电路和数据写入子电路通常均与驱动晶体管的第一极(源极)电连接，这样，数据信号和基准电 压信号在不同时段(数据写入阶段和第一重置阶段)写入同一节点(驱动晶体管的第一极)。本公开的实施例提供的像素电路120，重置子电路121与驱动晶体管DT的第一极N2，数据写入子电路123与驱动晶体管DT的第二极N3电连接。基于此，在数据写入阶段T12，数据写入子电路123的将数据信号传输至驱动晶体管DT的第二极N3，此时驱动晶体管DT的第二极N3作为源极，数据信号由驱动晶体管DT的第二极N3向第一极N2传输。在第一重置阶段T13，重置子电路121将基准电压信号传输至驱动晶体管DT的第一极N2，此时驱动晶体管DT的第一极N2作为源极。也就是说，在数据写入阶段T12和第一重置阶段T13，驱动晶体管DT的源极和漏极发生反转，驱动晶体管DT的偏置状态不同，这样有利于改善驱动晶体管DT的磁滞效应，降低显示面板1100发生画面闪烁的风险。
在一些实施例中，参阅图5，重置子电路121包括第一晶体管T1，防漏电子电路122包括第二晶体管T2，数据写入子电路123包括第三晶体管T3。
第一晶体管T1的控制极与第一扫描信号端Reset电连接，第一极与基准电压信号端Vref电连接，第二极与驱动晶体管DT的第一极N2电连接。第二晶体管T2的控制极与第二扫描信号端Gate-N电连接，第一极与驱动晶体管DT的第一极N2电连接，第二极与驱动晶体管DT的控制极N1电连接。第三晶体管T3的控制极与第三扫描信号端Gate-P电连接，第一极与数据信号端Data电连接，第二极与驱动晶体管DT的第二极N3电连接。
示例性地，第一晶体管T1和第三晶体管T3均为P型晶体管，P型晶体管在控制极的电压为低电压的时候导通，在控制极的电压为高电压的情况下截止。以重置子电路121为例，在重置子电路121开启时，第一扫描信号端Reset可以向第一晶体管T1的控制极输出低电压的第一扫描信号，第一晶体管T1在低电压的第一扫描信号的控制下打开，反之，在重置子电路121关闭时，第一晶体管T1在高电压的控制下截止。
第二晶体管T2可以为N型晶体管，N型晶体管在控制极的电压为高电压的时候导通，在控制极的电压为低电压的情况下截止。基于此，防漏电子电路122开启时，第二扫描信号端Gate-P向第二晶体管T2的控制极输出高电压的第二扫描信号，第二晶体管T2在高电压的第二扫描信号的控制下导通，反之，在防漏电子电路122关闭时，第二晶体管T2在低电压的控制下截止。
在一些实施例中，第二晶体管T2可以为金属氧化物薄膜晶体管(英文全称：Thin Film Transistor；简称：TFT)，金属氧化物比如可以是铟镓锌氧化物(英文全称：Indium Gallium Zinc Oxide；简称：IGZO)。金属氧化物薄膜晶体 管具有电流小的优势，有利于降低第二晶体管T2的漏电流，进而提升驱动晶体管DT的控制极N1的电压保持能力。
第一晶体管T1、第三晶体管T3和驱动晶体管DT为低温多晶硅(英文全称：Low Temperature Poly Silicon；简称：LTPS)薄膜晶体管。低温多晶硅薄膜晶体管具有较高的电子迁移率，有利于降低各个晶体管的负载，降低像素电路120的能耗。
在一些实施例中，在防漏电子电路122关闭时，重置子电路121可以开启一次或两次。也就是说，在第一重置阶段T13，第一扫描信号端Reset输出一次或者两次第一扫描信号(工作电平)，重置子电路121在第一扫描信号的控制下，将基准电压信号传输至驱动晶体管DT的第一极N2一次或两次。
示例性地，如图9所示，在第一重置阶段T13，第一扫描信号端Reset输出一次工作电平，重置子电路121开启一次。这样，在实现对驱动晶体管DT的第一极N2的电压重置的前提下，有利于减少第一重置阶段T13的时长，有利于显示面板1100实现高的刷新频率(比如120Hz)。或者，示例性地，如图10所示，在第一重置阶段T13，第一扫描信号端Reset输出两次工作电平，重置子电路121开启两次。这样，有利于基准电压信号更充分的传输至驱动晶体管DT的第一极N2，对驱动晶体管DT的第一极N2的电压重置更充分。
可以理解的是，在第一重置阶段T13，第一扫描信号端Reset还可以输出超过两次第一扫描信号，比如，第一扫描信号端Rese可以输出三次、四次或者五次第一扫描信号，本公开的实施例不再一一列举。
在一些实施例中，如图11和图12所示，在防漏电子电路122关闭时，数据写入子电路123开启至少一次，且数据信号端Data输出第一复位电压信号。在数据写入阶段T12，数据写入子电路123会将数据信号传输至驱动晶体管DT的第二极N3，驱动晶体管DT的第二极N3与第一极N2之间发生偏置，且数据写入阶段T12结束后，驱动晶体管DT的第二极N3可能存在残余电压。基于此，在防漏电子电路122关闭时，数据写入子电路123开启至少一次，可以在数据写入阶段T12之后，通过数据写入子电路123向驱动晶体管DT的第二极N3传输第一复位电压信号，对驱动晶体管DT的第二极N3进行电压重置。降低数据信号对驱动晶体管DT的第二极N3的电压的影响，进而降低因为数据信号变化导致显示面板1100产生显示亮度差异的风险，并降低显示面板1100发生闪烁的风险。
可以理解的是，在刷新帧T10，显示面板1100所包括的多行像素电路120中，数据写入子电路123逐行开启(逐行写入数据信号)，且逐行进入第一 重置阶段。这样，在目标行像素电路(任一行像素电路)处于第一重置阶段T13，且数据写入子电路123开启时，目标行像素电路之后的某一行像素电路(下文称为后续行像素电路)的数据写入子电路开启，进行数据信号写入。基于此，后续行像素电路的数据信号经目标行像素电路的数据写入子电路写入目标行像素电路的驱动晶体管DT的第二极N3，对目标行像素电路的驱动晶体管DT的第二极N3进行电压重置。也就是说，在第一重置阶段，(目标行像素电路的)第一复位电压信号是后续行像素电路的数据信号。数据信号通常为正电压，能够提升目标行像素电路的驱动晶体管DT的第二极N3的电压，起到在发光阶段之前，对驱动晶体管DT的第二极N3进行预充电的作用，有利于降低显示面板1100在低刷新频率和高刷新频率切换时或者切屏显示时的闪烁现象。
示例性地，参阅图11，在第一重置阶段T13，在防漏电子电路122关闭时，数据写入子电路123在第三扫描信号的控制下开启，进而将来自数据信号端Data的第一复位电压信号传输至驱动晶体管DT的第二极N3。示例性地，第三扫描信号端Gate-P输出工作电平(低压电平信号)，第三晶体管T3开启，数据信号端Data的第一复位电压信号通过第三晶体管T3传输至驱动晶体管DT的第二极N3。
示例性地，在防漏电子电路122关闭时，重置子电路121和数据写入子电路123的开启次数相同。比如，在第一重置阶段T13，重置子电路121和数据写入子电路123均开启一次，参阅图11，第一扫描信号端Reset和第三扫描信号端Gate-P均输出依次工作电平。或者，在第一重置阶段T13，重置子电路121和数据写入子电路123均开启两次，参阅图12，第一扫描信号端Reset和第三扫描信号端Gate-P均输出依次工作电平。
示例性地，第一扫描信号和第三扫描信号均为脉冲信号，且第一扫描信号和第三扫描信号的脉冲宽度相同。如图11和图12所示，比如，重置子电路121和数据写入子电路123可以同时开启和同时关闭，也就是说，第一扫描信号端Reset和第三扫描信号端Gate-P分别在相同时间段输出第一扫描信号和第三扫描信号。
在一些实施例中，参阅图6，像素电路120还包括第一控制子电路124、第二控制子电路125、复位子电路126和储能子电路127。
第一控制子电路124与发光控制信号端EM(也可以称为使能信号端)、第一电压信号端VDD和驱动晶体管DT的第一极N2电连接。第一控制子电路124被配置为在来自发光控制信号端EM的发光控制信号的控制下，将来 自第一电压信号端VDD的第一电压信号传输至驱动晶体管DT的第一极N2。
第二控制子电路125与发光控制信号端EM、驱动晶体管DT的第二极N3和发光器件EL电连接。第二控制子电路125被配置为在发光控制信号的控制下，将来自驱动晶体管DT的驱动电流传输至发光器件EL。
复位子电路126与第一扫描信号端Reset、初始化信号端Vinit和发光器件EL(具体为发光器件EL的阳极)电连接。复位子电路126被配置为在(来自第一扫描信号端Reset的)第一扫描信号的控制下，将来自初始化信号端Vinit的初始化信号传输至发光器件EL。
储能子电路127与驱动晶体管DT的控制极N1和第一电压信号端VDD电连接。储能子电路127被配置为维持驱动晶体管DT的控制极N1的电压。
示例性地，如图13A所示，保持帧T20包括发光阶段T21。在发光阶段T21，第一控制子电路124在发光控制信号的控制下开启，来自第一电压信号端VDD的第一电压信号经过第一控制子电路124传输至驱动晶体管DT的第一极N2。驱动晶体管DT在控制极N1与第一极N2之间的电压差的控制下，产生驱动电流。第二控制子电路125也在发光控制信号的控制下开启，驱动晶体管DT产生的驱动电流经第二控制子电路125传输至发光器件EL，发光器件EL在驱动电流的作用下开始发光(被点亮)。
复位子电路126和重置子电路121均与第一扫描信号端Reset电连接，且均在来自第一扫描信号端Reset的扫描信号的控制下开启，基于此，在上述任一实施例中的重置子电路121开启的时候，复位子电路126与重置子电路121同步开启，并对发光器件EL(发光器件EL的阳极)进行一次电压重置。
储能子电路127例如可以在数据写入阶段T12，补偿后的数据信号传输至驱动晶体管DT的控制极N1之后，维持驱动晶体管DT的控制极N1节点的电压，降低驱动晶体管DT的控制极N1的漏电流，使驱动晶体管DT可以在发光阶段T21可以产生稳定的驱动电流，驱动发光器件EL发光，并使发光器件EL显示预设灰阶。
在一些实施例中，参阅图7A，第一控制子电路124包括第四晶体管T4，第二控制子电路125包括第五晶体管T5，复位子电路126包括第六晶体管T6，储能子电路127包括存储电容器Cst。
如图7A所示，第四晶体管T4的控制极与发光控制信号端EM电连接，第一极与第一电压信号端VDD电连接，第二极与驱动晶体管DT的第一极N2电连接。第五晶体管T5的控制极与发光控制信号端EM电连接，第一极与驱动晶体管DT的第二极N3电连接，第二极与发光器件EL电连接。第六 晶体管T6的控制极与第一扫描信号端Reset电连接，第一极与初始化信号端Vinit电连接，第二极与发光器件EL电连接。存储电容器Cst的第一极板与驱动晶体管DT的控制极电连接，第二极板与第一电压信号端VDD电连接。
在一些实施例中，第四晶体管T4、第五晶体管T5、第六晶体管T6为低温多晶硅薄膜晶体管。存储电容器Cst可以是通过工艺制程单独制作的电容器件，示例性地，可以通过制作专门的电容极板(存储电容器Cst的第一极板和第二极板)来实现电容器件，比如该存储电容器的各个电容极板可以通过金属层实现。
在一些实施例中，如图7B所示，第三晶体管T3可以为双栅晶体管，这样，可以降低第三晶体管T3的漏电流。
在一些实施例中，如图8所示，本公开的实施例提供的阵列基板100，还包括第一移位寄存器Reset-GOA、第二移位寄存器GN-GOA、第三移位寄存器GP-GOA和第四移位寄存器EM-GOA。
第一移位寄存器Reset-GOA与至少一行像素电路120对应连接，被配置为向至少一行像素电路120传输第一扫描信号。示例性地，第一移位寄存器Reset-GOA通过第一扫描信号线RL与两行像素电路120电连接。第一扫描信号线RL作为第一扫描信号端Reset，第一晶体管T1的控制极和第六晶体管T6的控制均与第一扫描信号线RL(第一扫描信号端Reset)电连接。第一移位寄存器Reset-GOA设置于显示区AA沿第一方向X相对的两侧，也就是说，第一移位寄存器Reset-GOA采用双边驱动。
第二移位寄存器GN-GOA与至少一行像素电路120对应连接，被配置为向至少一行像素电路120传输第一扫描信号。示例性地，第二移位寄存器GN-GOA通过第二扫描信号线GNL与两行像素电路120电连接。第二扫描信号线GNL作为第二扫描信号端GN，第二晶体管T2的控制极与第二扫描信号线GNL(第二扫描信号端GN)电连接。第二移位寄存器GN-GOA设置于显示区AA沿第一方向X的其中一侧，也就是说，第二移位寄存器GN-GOA采用单边驱动。
第三移位寄存器GP-GOA与一行像素电路120对应连接，被配置为向一行像素电路120传输第三扫描信号。示例性地，第三移位寄存器GP-GOA通过第三扫描信号线GPL与两行像素电路120电连接。第三扫描信号线GPL作为第三扫描信号端GP，第三晶体管T3的控制极与第三扫描信号线GPL(第三扫描信号端GP)电连接。第三移位寄存器GP-GOA设置于显示区AA沿第一方向X相对的两侧，也就是说，第三移位寄存器GP-GOA采用双边驱动。
第四移位寄存器EM-GOA与至少一行像素电路120对应连接，被配置为向至少一行像素电路120传输第四扫描信号。示例性地，第四移位寄存器EM-GOA通过第四扫描信号线EML与两行像素电路120电连接。第四扫描信号线EML作为发光控制信号端EM，第四晶体管T4的控制极和第五晶体管T5的控制极均与第四扫描信号线EML(第四扫描信号端EM)电连接。第四移位寄存器EM-GOA设置于显示区AA沿第一方向X相对的一侧，也就是说，第四移位寄存器EM-GOA采用单边驱动。
本公开实施例提供的显示面板1100，重置子电路121所包含的第一晶体管T1和复位子电路126所包含的第六晶体管T6共用第一移位寄存器Reset-GOA，基于此，可以减少一个移位寄存器，有利于降低周边区BB的宽度，实现显示面板1100的窄边框。
本公开的另一些实施例，还提供了一种像素电路120的驱动方法，驱动方法用于驱动上述任一实施例中所述的像素电路120。如图9所示，驱动方法包括：
在复位阶段T11，第一扫描信号端Reset和第二扫描信号端Gate-N输出工作电平，第三扫描信号端Gate-P输出非工作电平。来自基准电压信号端Vref的基准电压信号经重置子电路121和防漏电子电路122传输至驱动晶体管DT的控制极N1。
其中，本公开的实施例中，工作电平是指能够将与对应扫描信号端电连接的晶体管打开的电平信号，也就是说，在工作电平的驱动下，对应晶体管的第一极和第二极之间导通。非工作电平是指将与对应扫描信号端电连接的晶体管截止(关闭)的电平信号，也就是说，在非工作电平的驱动下，对应晶体管的第一极与第二极之间截止。
示例性地，以如图7A所示的像素电路120为例，在第一晶体管T1、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6均为P型晶体管(P型晶体管在控制极为低电压的时候导通，在控制极为高电压的时候截止)的情况下，与上述第一晶体管T1、第三晶体管T3、第四晶体管T4、第五晶体管T5和第六晶体管T6的控制极相连的第一扫描信号端Reset、第三扫描信号端Gate-P和发光控制信号端EM，输出的工作电平是指对应信号端输出电压值为低的电压信号，输出的非工作电平是指输出电压值为高的电压信号。比如，与第三晶体管T3电连接的第三扫描信号端Gate-P输出工作电平，是指第三扫描信号端Gate-P输出电压值为低的电压信号，第三扫描信号端Gate-P输出非工作电平，是指第三扫描信号端Gate-P输出电压值为高的电压 信号。
在第二晶体管T2为N型晶体管(N型晶体管在控制极为高电压的时候导通，在控制极为低电压的时候截止)的情况下，第二扫描信号端Gate-N输出工作电平是指输出电压值为高的电压信号，第二扫描信号端Gate-N输出非工作电平是指输出电压值为低的电压信号。本公开的实施例对工作电平和非工作电平的具体电压值不做限定，其中，工作电平的电压值能够完全打开对应的晶体管即可。
在复位阶段T11，第一扫描信号端Reset输出工作电平，与第一扫描信号端Reset电连接的重置子电路121开启，在重置子电路121包括第一晶体管T1的情况下，第一晶体管T1导通。第一晶体管T1将来自基准电压信号端Vref的基准电压信号传输至驱动晶体管DT的第一极N2。
在像素电路120包括复位子电路126，且复位子电路126包括第六晶体管T6的情况下，在复位阶段T11，第六晶体管T6和第一晶体管T1同步导通，第六晶体管T6将来自初始化信号端Vinit的初始化信号传输至发光器件EL的阳极，对发光器件EL的阳极进行电压重置。第一晶体管T1与第二晶体管T2一起对驱动晶体管DT的控制极N1进行电压重置(参阅上文，此处不再赘述)。
第二扫描信号端Gate-N输出工作电平，与第二扫描信号端Gate-N电连接的防漏电子电路122开启，在防漏电子电路122包括第二晶体管T2，且第二晶体管T2为N型晶体管的情况下，第二扫描信号端Gate-N向第二晶体管T2的控制极输出高电压的工作电平，第二晶体管T2导通，第二晶体管T2将经第一晶体管T1传输至驱动晶体管DT的第一极N2的基准电压信号，传输至驱动晶体管DT的控制极N1，实现对驱动晶体管DT的控制极N1的电压重置。
在数据写入阶段T12，第一扫描信号端Reset输出非工作电平，第二扫描信号端Gate-N和第三扫描信号端Gate-P输出工作电平，数据信号端Data输出数据信号。数据信号经数据写入子电路123传输至驱动晶体管DT的第二极N3，且驱动晶体管DT的控制极N1写入数据信号和阈值电压。
第一扫描信号端Reset输出非工作电平，与第一扫描信号端Reset电连接的重置子电路121和复位子电路126关闭，即第一晶体管T1和第六晶体管T6截止。
第二扫描信号端Gate-N输出工作电平，与第二扫描信号端Gate-N电连接的防漏电子电路122保持开启。即第二晶体管T2保持导通状态。
第三扫描信号端Gate-P输出工作电平，与第三扫描信号端Gate-P电连接 的数据写入子电路123开启，在数据写入子电路123包括第三晶体管T3的情况下，第三晶体管T3打开，第三晶体管T3将来自数据信号端Data的数据信号传输至驱动晶体管DT的第二极N3。数据信号由驱动晶体管DT的第二极N3经驱动晶体管DT补偿后传输至驱动晶体管DT的第一极N2，然后数据信号和阈值电压由驱动晶体管DT的第一极N2经第二晶体管T2传输至驱动晶体管DT的控制极N1。
在第一重置阶段T13，第一扫描信号端Reset输出至少一次工作电平，第二扫描信号端Gate-N输出非工作电平，基准电压信号经重置子电路121传输至驱动晶体管DT的第一极N2。实现对驱动晶体管DT的第一极N2的电压重置。
第一扫描信号端Reset输出工作电平，与第一扫描信号端Reset电连接的重置子电路121开启，即第一晶体管T1打开。第一晶体管T1将来自基准电压信号端Vref的基准电压信号传输至驱动晶体管DT的第一极N2。第二扫描信号端Gate-N输出非工作电平，与第二扫描信号端Gate-N电连接的防漏电子电路122关闭，即第二晶体管T2截止，基准电压信号不能经防漏电子电路122写入驱动晶体管DT的控制下，进而只对驱动晶体管DT的第一极N2进行电压重置。
本公开实施例提供的像素电路120的驱动方法，如上文所述，能够在复位阶段T11通过重置子电路121(第一晶体管T1)和防漏电子电路122(第二晶体管T2)对驱动晶体管DT的控制极N1进行电压重置，并在第一重置阶段T13，通过重置子电路121对驱动晶体管DT的第一极N2进行电压重置。基于此，与上述任一实施例中的像素电路类似的，通过本申请提供的像素电路的驱动方法，可以使像素电路120减少一个复位晶体管，有利于降低像素电路120占用的空间，提升显示面板1100的像素密度。
在一些实施例中，如图9所示，在第一重置阶段T13，第一扫描信号端Reset可以输出一次工作电平。这样，重置子电路121对驱动晶体管DT的第一极N2进行一次电压重置，有利于缩短第一重置阶段T13的时长，进而提升显示面板1100的刷新频率。
或者，在另一些实施例中，如图10所示，在第一重置阶段T13，第一扫描信号端Reset可以输出两次工作电平。这样，重置子电路121对驱动晶体管DT的第一极N2进行两次电压重置，有利于基准电压信号更充分的传输至驱动晶体管DT的第一极N2。
当然，在其他一些实施例中，在第一重置阶段T13，第一扫描信号端Reset 可以输出更多次数的工作电平；比如三次、四次或者更多，本公开的实施例对此不做具体限定。
在一些实施例中，如图9和图10所示，像素电路的驱动方法还包括：在第一重置阶段T13，第三扫描信号端Gate-P输出非工作电平信号。也就是说，在第一重置阶段T13，数据写入子电路关闭，这样，有利于简化像素电路的驱动方法。
在另一些实施例中，如图11和图12所示，像素电路的驱动方法还包括：在第一重置阶段T13，第三扫描信号端Gate-P输出至少一次工作电平信号，且所述数据信号端输出第一复位电压信号。
也就是说，在第一重置阶段T13，数据写入子电路123开启，且数据信号端Data输出第一复位电压信号。基于此，可以将第一复位电压信号传输至驱动晶体管DT的第二极N3，对驱动晶体管DT的第二极N3进行电压重置。降低数据信号对驱动晶体管DT的第二极N3的电压的影响，进而降低因为数据信号变化导致显示面板1100产生显示亮度差异的风险，以及降低显示面板1100发生闪烁的风险。
示例性地，参阅图11，在第一重置阶段T13，第三扫描信号端Gate-P输出一次工作电平，这样，有利于缩短第一重置阶段T13的时长，进而提升显示面板1100的刷新频率。
或者，如图12所示，在第一重置阶段T13，第三扫描信号端Gate-P输出两次工作电平。这样，数据写入子电路123对驱动晶体管DT的第二极N3进行两次电压重置，有利于第一复位电压信号更充分的传输至驱动晶体管DT的第二极N3。
在一些实施例中，像素电路120可以包括第一刷新频率和第二刷新频率，第一刷新频率小于第二刷新频率，也就是说，显示面板采用了可变刷新频率(英文全称：(Variable Refresh Rate；简称：VRR)显示技术，显示面板可以根据使用场景的变化，选择合适的刷新频率，显示面板的刷新频率的具体数值本公开的实施例不做具体限定。示例性地，第一刷新频率比如可以是1Hz或者30Hz；第二刷新频率比如可以是60Hz或者120Hz。
在第一刷新频率下，像素电路120在一个显示帧还包括在第一重置阶段T13之后的发光阶段T21和第二重置阶段T22。如图13A和图13B所示，像素电路120的驱动方法还包括：
在发光阶段T21，第一扫描信号端Reset、第二扫描信号端Gate-N和第三扫描信号端Gate-P输出非工作电平，发光控制信号端EM输出工作电平，来 自驱动晶体管DT的驱动电流传输至发光器件EL。
第一扫描信号端Reset输出非工作电平，与第一扫描信号端Reset电连接的第一晶体管T1和第六晶体管T6截止。第二扫描信号端Gate-N输出非工作电平，与第二扫描信号端Gate-N电连接的第二晶体管T2截止。第三扫描信号端Gate-P输出非工作电平，与第三扫描信号端Gate-P电连接的第三晶体管T3截止。发光控制信号端EM输出工作电平，与发光控制信号端EM电连接的第四晶体管T4和第五晶体管T5导通。驱动晶体管DT在控制极N1的电压(数据信号和阈值电压)控制下导通。
第四晶体管T4将来自第一电压信号端VDD的第一电压信号传输至驱动晶体管DT的第一极N2，驱动晶体管DT在控制极N1和第一极N2的电压差的控制下产生驱动电流。驱动电流经第五晶体管T5传输至发光器件EL，发光器件EL在驱动电流的驱动下发光。
在第二重置阶段T22，第一扫描信号端Reset输出工作电平，第二扫描信号端Gate-N和发光控制信号端EM输出非工作电平，来自基准电压信号端Vref的基准电压信号经重置子电路121传输至驱动晶体管DT的第一极N2。
第一扫描信号端Reset输出工作电平，与第一扫描信号端Reset连接的第一晶体管T1和第六晶体管T6导通，第一晶体管T1将来自基准电压信号端Vref的基准电压信号传输至驱动晶体管DT的第一极N2，对驱动晶体管DT的第一极N2进行电压重置，这样，能够调节驱动晶体管DT的偏置状态，降低驱动晶体管DT的磁滞效应。第六晶体管T6将来自初始化信号端Vinit的初始化信号传输至发光器件EL的阳极，对发光器件EL的阳极进行电压重置。
示例性地，根据显示面板1100的刷新频率，保持帧T20可以包括交替设置的多个发光阶段T21和第二重置阶段T22，本公开的实施例中，如图13A和图13B所示，仅示例性地展示了一个发光阶段T21和一个第二重置阶段T22。
在一些实施例中，基准电压信号端Vref在第一重置阶段T13输出的基准电压信号的电压值，与在第二重置阶段T22输出的基准电压信号的电压值可以相同或者不相同。示例性地，来自基准电压信号端Vref的基准电压信号在第一重置阶段T13的电压值为第一基准电压信号值V1，在第二重置阶段T22的电压值为第二基准电压信号值V2。
示例性地，第一基准电压信号值V1等于第二基准电压信号值V2，且第一基准电压信号值V1和第二基准电压信号值V2为负值，这样，基准电压信号端Vref在第一重置阶段T13和第二重置阶段T22输出大小相同的基准电压 信号，有利于简化基准电压信号端的驱动方法，进而简化像素电路的驱动方法。
或者，第一基准电压信号值小于第二基准电压信号值。其中，第一基准电压信号值V1为负值，这样在第一重置阶段T13，数值为第一基准电压信号值V1的基准电压信号能够用于对驱动晶体管DT的第一极N2的电压重置。第二基准电压信号值V2大于来自第一电压信号端VDD的第一电压信号的电压值，这样，在第二重置阶段T22，驱动晶体管DT的第二极N3作为驱动晶体管DT的源极，驱动晶体管DT的第一极N2作为驱动晶体管DT的漏极。在发光阶段T21，驱动晶体管DT的第一极N2作为驱动晶体管DT的源极，驱动晶体管DT的第二极N3作为驱动晶体管DT的漏极。也就是说，在发光阶段T21和第二重置阶段T22，驱动晶体管DT的源极和漏极发生反转，这样，驱动晶体管DT处于两种相反的偏置状态，有利于改善驱动晶体管DT的磁滞现象，降低显示面板1100发生画面闪烁的风险。
在一些实施例中，如图13A所示，在第二重置阶段T22，第三扫描信号端Gate-P输出非工作电平，此时数据写入子电路123关闭。在第二重置阶段TT对驱动晶体管DT的第一极N2和发光器件EL的阳极进行电压重置。
在另一些实施例中，如图13B所示，在第二重置阶段T22，第三扫描信号端Gate-P输出工作电平，且数据信号端输出第二复位电压信号。此时，数据写入子电路123开启，第二复位电压信号传输至驱动晶体管DT的第二极N3，实现对驱动晶体管DT的第二极N3的电压重置。
示例性地，第二复位电压信号可以为电压值为正的高电压信号，于此同时，基准电压信号端Vref输出的准电压信号值V2可以为负数，这样，在第二重置阶段，驱动晶体管DT的第二极N3作为驱动晶体管DT的源极，第一极N2作为驱动晶体管DT的漏极。相较于发光阶段T21，驱动晶体管DT的源极和漏极反转，有利于降低驱动晶体管DT的磁滞现象。
可以理解的是，第二复位电压信号也可以根据在数据写入阶段T12的数据信号进行调整，比如，在像素电路的刷新频率为1Hz的情况下，在第二重置阶段，第二复位电压信号可以根据发光器件EL显示的灰阶不同，动态调节第二复位电压信号的大小。
在一些实施例中，参阅图3和图14～图22，阵列基板100还包括沿垂直于衬底110且远离衬底110方向依次设置的第一半导体层11、第一栅导电层12、第二栅导电层13、第二半导体层14、第三栅导电层15、第一源漏导电层16和第二源漏导电层17。阵列基板100还包括设置于任意相邻两个导电层之 间的至少一个绝缘层，本公开的实施例对阵列基板100包括的绝缘层不再一一赘述。其中，在一些实施例中，沿第一方向X相邻两个像素电路120对称设置，基于此，图14～图22中均示出了两个像素电路的结构。
参阅图3和图14，图14为根据一些实施例的第一半导体层11的结构图。第一半导体层11设置于衬底(图中未示出)上，包括第一晶体管T1的第一半导体图案111、第三晶体管T3的第三半导体图案113和驱动晶体管DT的第七半导体图案117。其中，第三半导体图案113和第七半导体图案117相连，比如，可以是第三半导体图案113上用于形成第三晶体管T3的第二极的区域，和第七半导体图案117上用于形成驱动晶体管DT的第二极的区域连接，这样，有利于第三晶体管T3的第二极和驱动晶体管DT的第二极连接。
当然，在像素电路120还包括第四晶体管T4、第五晶体管T5和第六晶体管T6的情况下，如图14所示，第一半导体层11还包括第四晶体管T4的第四半导体图案114、第五晶体管T5的第五半导体图案115和第六晶体管T6的第六半导体图案116。
其中，第三半导体图案113、第四半导体图案114、五半导体图案115、第六半导体图案116和第七半导体图案117相互连接为一个整体。也就是说，第三半导体图案113、第四半导体图案114、五半导体图案115、第六半导体图案116和第七半导体图案117是一个连续图案中的一部分。
参阅图3和图15A，图15A为第一栅导电层12和第一半导体层11的结构图。第一栅导电层12位于第一半导体层11远离衬底110的一侧，第一栅导电层12包括第一扫描信号线RL、第三扫描信号线GPL和存储电容器Cst的第一极板C1。
在像素电路120还包括第四晶体管T4和第五晶体管T5的情况下，第一栅导电层12还可以包括第四扫描信号线EML。
如图15A所示，其中，在向衬底110上的正投影中，第一扫描信号线RL与第一半导体图案111和第六半导体图案116部分交叠，用于形成第一晶体管T1和第六晶体管T6的控制极。第一半导体图案111包括与第一扫描信号线RL重叠的第一晶体管T1的半导体层，以及位于第一扫描信号线RL的相对两侧的第一晶体管T1的第一极(位于第一扫描信号线RL的上侧)和第一晶体管T1的第二极(位于第一扫描信号线RL的下侧)。第六半导体图案116包括与第一扫描信号线RL重叠的第六晶体管T6的半导体层，位于第一扫描信号线RL下侧的第六晶体管T6的第一极，以及位于第一扫描信号线RL上侧的第六晶体管T6的第二极。
在向衬底110上的正投影中，第三扫描信号线GPL与第三半导体图案113部分交叠，用于形成第三晶体管T3的控制极。第三半导体图案113包括与第三扫描信号线GPL重叠的第三晶体管T3的半导体区域，位于第三扫描信号线GPL上侧的第三晶体管T3的第一极，位于第三扫描信号线GPL上侧的第三晶体管T3的第二极。
在向衬底110上的正投影中，第四扫描信号线EML与第四半导体图案114和第五半导体图案115部分交叠，用于形成第四晶体管T4的控制极和第五晶体管T5的控制极。第四半导体图案114包括与第四扫描信号线EML交叠的第四晶体管T4的半导体层，位于第四扫描信号线EML下侧的第四晶体管T4的第一极，位于第四扫描信号线EML上侧的第四晶体管T4的第二极。第五半导体图案115包括与第四扫描信号线EML交叠的第五晶体管T5的半导体层，位于第四扫描信号线EML上侧的第五晶体管T5的第一极，位于第四扫描信号线EML下侧的第五晶体管T5的第二极。
其中，第三半导体图案113的第二极、第五半导体图案115的第一极和第七半导体图案117的第二极相连，共同形成驱动晶体管DT的第二极N3。第四晶体管T4的第二极与驱动晶体管DT的第一极N2相连。
在一些实施例中，参阅图15B，图15B为第三晶体管T3为双栅晶体管时，半导体层11和第一栅导电层12的结构图。在第三晶体管T3为双栅晶体管的情况下，第三半导体图案113为L型结构，第三半导体图案113包括第一延伸段1131和第二延伸段1132。第一延伸段1131沿第一方向延伸，第二延伸段1132沿第二方向延伸，且与第一延伸段1131连接。
第三扫描信号线GPL包括主体部GPL1和凸出部GPL2，主体部GPL1沿第一方向X延伸，凸出部GPL2沿第二方向Y延伸。在向衬底110上的正投影中，主体部GPL1与第二延伸段1132部分交叠，凸出部GPL2与第一延伸段1131部分交叠。
其中，数据信号端Data与第一延伸段1131中位于凸出部GPL2远离第二延伸段1132的一侧电连接。
在一些实施例中，参阅图3和图16A，图16A为第二栅导电层13不包括辅助第二扫描信号线GNL＇时的结构图。第二栅导电层13位于第一栅导电层12远离衬底110的一侧。第二栅导电层13包括存储电容器Cst的第二极板C2。在向衬底110上的正投影中，第二极板C2与第一极板C1部分交叠。示例性地，第二极板C2的中部设有避让孔C21。
在另一些实施例中，如图16B所示，图16B为第二栅导电层13包括辅助 第二扫描信号线GNL＇时的结构图。第二栅导电层13包括存储电容器Cst的第二极板C2，以及辅助第二扫描信号线GNL＇。辅助第二扫描信号线GNL＇被配置为与第二扫描信号线GNL一起传输第二扫描信号。
如图3所示，第二半导体层14位于第二栅导电层13远离衬底的一侧。参阅图17，图17为阵列基板从半导体层11至第二半导体层14的结构图。第二半导体层14包括第二晶体管T2的第二半导体图案141。
如图3所示，第三栅导电层15位于第二半导体层14远离衬底110的一侧。参阅图18A，图18A为阵列基板从第一半导体层至第三栅导电层的结构图。第三栅导电层15包括第二扫描信号线GNL和基准电压信号线VL。
其中，在向衬底110上的正投影中，第二扫描信号线GNL与第二半导体图案141部分交叠，且第二半导体图案141包括与第二扫描信号线GNL重叠的第二晶体管T2的半导体层，位于第二扫描信号线GNL上方的第二晶体管T2的第一极，以及第二扫描信号线GNL下方的第二晶体管T2的第二极。基准电压信号线VL用于传输基准电压信号，并形成基准电压信号端Vref。示例性地，第二扫描信号线GNL与辅助第二扫描信号线GNL＇在衬底上的正投影至少部分交叠。
如图3所示，第一源漏导电层16位于第三栅导电层15远离衬底110的一侧。参阅图19A，图19A为阵列基板从第一半导体层至第一源漏导电层的结构图。第一源漏导电层16包括第一连接图案161、第二连接图案162和第三连接图案163。
第一连接图案161与基准电压信号线VL和第一半导体图案111的第一极连接，使第一晶体管T1的第一极与基准电压信号端Vref电连接。
第二连接图案162与第一半导体图案111的第二极、第二半导体图案141的第一极和第七半导体图案117的第一极连接。使第一晶体管T1的第二极与第二晶体管T2的第一极以及驱动晶体管DT的第一极电连接。且在第一半导体层11包括第四半导体图案114的情况下，第二连接图案162还与第四半导体图案114的第二极电连接。
第三连接图案163与第二半导体图案141的第二极和存储电容器Cst的第一极板C1连接。在向衬底110上的正投影中，第三连接图案163与存储电容器Cst的第二极板C2的避让孔C21部分交叠，且第三连接图案163穿过避让孔C21与第一极板C1连接。
在一些实施例中，如图19A所示，在像素电路120包括第四晶体管T4的情况下，第一源漏导电层16还包括第四连接图案164，第四连接图案164 与第四半导体图案114的第一极电连接。
第一源漏导电层16还包括第五连接图案165，第五连接图案165用于连接像素电路和发光器件的阳极。
如图3所示，第二源漏导电层17位于第一源漏导电层16远离衬底110的一侧。参阅图20，第二源漏导电层17包括数据线DL，数据线DL与第三半导体图案的第一极(图中未示出)连接。第三半导体图案113的第二极与第七半导体图案117的第二极连接(如图15A所示)。其中，图20为阵列基板的结构图。
继续参阅图20，第二源漏导电层17还可以包括第一电压信号线VDDL，第一电压信号线VDDL用于形成第一电压信号端VDD，第一电压信号线VDDL与第四连接图案164电连接。
第二源漏导电层17还可以包括转接块171，转接块171与第五连接图案165连接，用于将像素电路120与发光器件EL连接。
在一些实施例中，参阅图17，在向衬底110的正投影中，第二半导体图案141与第三扫描信号线GPL部分交叠。示例性地，第二半导体图案141的第二极与第三扫描信号线GPL交叠，且交叠区域形成寄生电容，第二半导体图案141的第二极与存储电容器Cst的第一极板C1连接(如图19A所示)。基于此，可以提升第三扫描信号线GPL与第一极板C1之间的耦合作用，在第三扫描线信号线GPL输出第三扫描信号时，第二半导体图案141的第二极的电压在电容的自举作用下升高，第一极板C1的电压升高，有利于提升数据信号向第一极板C1传输的效率。
在一些实施例中，如图18A和图18B所示，图18B为图18A中A1的局部当大图。第二半导体图案141包括第一部分1411和第二部分1412。
在向衬底的正投影中，第一部分1411位于第二扫描信号线GNL靠近存储电容器Cst的一侧(下侧)，且第一部分1411与第三扫描信号线GPL交叠。
第二部分1412与第一部分1411相连，且沿第二方向Y延伸，第二方向Y与第一方向X垂直。在向衬底110上的正投影中，第二部分1412与第二扫描信号线GNL交叉。其中，第二部分1412中与第二扫描信号线GNL重叠的部分形成第二晶体管T2的半导体层，位于第二扫描信号线GNL远离存储电容器Cst(上侧)的部分形成第二晶体管T2的第一极。
如图18B所示，沿第二方向Y，第一部分1411的尺寸大于第三扫描信号线GPL的尺寸，且在向衬底110的正投影中，第一部分1411的两端分别位于第三扫描信号线GPL的两侧。第一部分1411沿第一方向Y的两侧的边缘， 位于第三扫描信号线GPL之外，这样，有利于提升第二半导体图案141与第三扫描信号线GPL之间的正对面积，提升第二半导体图案141的第二极与第三扫描信号线GPL的耦合作用。
在一些实施例中，如图19A和图19B所示，第二连接图案162沿第二方向Y延伸，在向衬底110的正投影中，第二部分1412与第二连接图案162交叠。这样，第二连接图案162能够屏蔽或者降低，位于第一源漏导电层远离衬底110一侧的信号对第二半导体图案141的干扰。其中，图19B为图19A中A2的局部放大图。
在一些实施例中，如图21所示，图21为第二半导体图案141与第二连接图案分离时的结构图。第二半导体图案141沿第二方向Y延伸，在向衬底上的正投影中，第二半导体图案141与第二连接图案162相互分离。这样，第二半导体图案141形成长条形结构，有利于简化第二半导体图案141的结构，进而降低第二半导体图案141的制备难度，降低显示面板1100的制备难度。
在一些实施例中，如图19A和图19B所示，在向衬底110的正投影中，第三连接图案163与第三扫描信号线GPL部分交叠。
在另一些实施例中，参阅图22，图22为第三连接图案位于第三扫描信号线GPL下方时的结构图。在向衬底上的正投影中，第三连接图案163位于第三扫描信号线GPL靠近存储电容器Cst的一侧(下侧)；第三连接图案163与第二半导体图案141部分交叠，且第三连接图案163与第二半导体图案141交叠部分位于第三扫描信号线GPL靠近存储电容器Cst的一侧。
参阅图22，第三扫描信号线GPL的部分向远离存储电容器Cst的一侧(上侧)弯折，形成凹部128，第三连接图案163与第二半导体图案141在衬底上相互交叠的部分位于凹部128内。
在一些实施例中，如图3所示，发光器件EL包括沿垂直于衬底110且远离衬底110的方向依次设置的阳极18、发光功能层19和阴极层21。其中，像素电路120通过转接块171与发光器件EL的阳极18电连接。
如图3所示，封装层200可以包括沿垂直于衬底110且远离衬底110的方向依次设置第一无机材料层201、有机材料层202和第二无机材料层203。其中，其中，第一无机材料层201和第二无机材料层203能够隔绝水氧，降低外界水氧侵蚀封装层200以下(靠近衬底11一侧)的各膜层结构，尤其是降低水氧侵蚀发光功能层19的风险，提升显示面板1100的使用寿命。有机材料层202可以用于平坦化显示面板1100的出光面，并可用于吸收和释放显 示面板1100的应力。
以上所述，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (23)

  1. 一种像素电路，包括：
    驱动晶体管，包括控制极、第一极和第二极；
    重置子电路，与第一扫描信号端、基准电压信号端和所述驱动晶体管的第一极电连接，被配置为在来自所述第一扫描信号端的第一扫描信号的控制下，将来自所述基准电压信号端的基准电压信号传输至所述驱动晶体管的第一极；
    防漏电子电路，与第二扫描信号端、所述驱动晶体管的第一极和所述驱动晶体管的控制极电连接，被配置为在来自所述第二扫描信号端的第二扫描信号的控制下，将所述驱动晶体管的第一极与控制极连通；
    数据写入子电路，与第三扫描信号端、数据信号端和所述驱动晶体管的第二极电连接，被配置为在来自所述第三扫描信号端的第三扫描信号的控制下，将来自所述数据信号端的数据信号传输至所述驱动晶体管的第二极；
    在所述防漏电子电路开启时，所述重置子电路和所述数据写入子电路依次开启；
    在所述防漏电子电路关闭时，所述重置子电路开启至少一次。
  2. 根据权利要求1所述的像素电路，其中，
    所述重置子电路包括第一晶体管，所述第一晶体管的控制极与所述第一扫描信号端电连接，第一极与所述基准电压信号端电连接，第二极与所述驱动晶体管的第一极电连接；
    所述防漏电子电路包括第二晶体管，所述第二晶体管的控制极与所述第二扫描信号端电连接，第一极与所述驱动晶体管的第一极电连接，第二极与所述驱动晶体管的控制极电连接；
    所述数据写入子电路包括第三晶体管，所述第三晶体管的控制极与所述第三扫描信号端电连接，第一极与所述数据信号端电连接，第二极与所述驱动晶体管的第二极电连接。
  3. 根据权利要求2所述的像素电路，其中，所述第二晶体管为金属氧化物薄膜晶体管；
    所述第一晶体管、所述第三晶体管和所述驱动晶体管为低温多晶硅薄膜晶体管。
  4. 根据权利要求1～3中任一项所述的像素电路，其中，在所述防漏电子电路关闭时，所述重置子电路开启一次或两次。
  5. 根据权利要求1～4中任一项所述的像素电路，其中，在所述防漏电子电路关闭时，所述数据写入子电路开启至少一次，且所述数据信号端输出第 一复位电压信号。
  6. 根据权利要求1～5中任一项所述的像素电路，还包括：
    第一控制子电路，与发光控制信号端、第一电压信号端和所述驱动晶体管的第一极电连接，被配置为在来自所述发光控制信号端的发光控制信号的控制下，将来自所述第一电压信号端的第一电压信号传输至所述驱动晶体管的第一极；
    第二控制子电路，与所述发光控制信号端、所述驱动晶体管的第二极和发光器件电连接，被配置为在所述发光控制信号的控制下，将来自所述驱动晶体管的驱动电流传输至所述发光器件；
    复位子电路，与所述第一扫描信号端、初始化信号端和所述发光器件电连接，被配置为在所述第一扫描信号的控制下，将来自所述初始化信号端的初始化信号传输至所述发光器件；
    储能子电路，与所述驱动晶体管的控制极和所述第一电压信号端电连接，被配置为维持所述驱动晶体管的控制极的电压。
  7. 根据权利要求6所述的像素电路，其中，
    所述第一控制子电路包括第四晶体管，所述第四晶体管的控制极与所述发光控制信号端电连接，第一极与所述第一电压信号端电连接，第二极与所述驱动晶体管的第一极电连接；
    所述第二控制子电路包括第五晶体管，所述第五晶体管的控制极与所述发光控制信号端电连接，第一极与所述驱动晶体管的第二极电连接，第二极与所述发光器件电连接；
    所述复位子电路包括第六晶体管，所述第六晶体管的控制极与所述第一扫描信号端电连接，第一极与所述初始化信号端电连接，第二极与所述发光器件电连接；
    所述储能子电路包括存储电容器，所述存储电容器的第一极板与所述驱动晶体管的控制极电连接，第二极板与所述第一电压信号端电连接。
  8. 一种像素电路的驱动方法，用于驱动如权利要求1～7中任一项所述的像素电路，一个显示帧包括复位阶段、数据写入阶段和第一重置阶段；
    所述驱动方法包括：
    在所述复位阶段，第一扫描信号端和第二扫描信号端输出工作电平，第三扫描信号端输出非工作电平，来自基准电压信号端的基准电压信号经重置子电路和防漏电子电路传输至驱动晶体管的控制极；
    在所述数据写入阶段，所述第一扫描信号端输出非工作电平，所述第二 扫描信号端和所述第三扫描信号端输出工作电平，数据信号端输出数据信号，所述数据信号经数据写入子电路传输至所述驱动晶体管的第二极，且所述驱动晶体管的控制极写入所述数据信号和阈值电压；
    在所述第一重置阶段，所述第一扫描信号端输出至少一次工作电平，所述第二扫描信号端输出非工作电平，所述基准电压信号经所述重置子电路传输至所述驱动晶体管的第一极。
  9. 根据权利要求8所述的驱动方法，其中，所述像素电路包括第一刷新频率和第二刷新频率，所述第一刷新频率小于所述第二刷新频率；在所述第一刷新频率下，所述像素电路在一个显示帧还包括在所述第一重置阶段之后的发光阶段和第二重置阶段；
    所述驱动方法还包括：
    在所述发光阶段，所述第一扫描信号端、所述第二扫描信号端和所述第三扫描信号端输出非工作电平，发光控制信号端输出工作电平，来自所述驱动晶体管的驱动电流传输至发光器件；
    在所述第二重置阶段，所述第一扫描信号端输出工作电平，所述第二扫描信号端、所述第三扫描信号端和所述发光控制信号端输出非工作电平，来自基准电压信号端的基准电压信号经所述重置子电路传输至所述驱动晶体管的第一极。
  10. 根据权利要求9所述的驱动方法，其中，来自基准电压信号端的基准电压信号在所述第一重置阶段的电压值为第一基准电压信号值，在所述第二重置阶段的电压值为第二基准电压信号值；
    其中，所述第一基准电压信号值等于所述第二基准电压信号值，且所述第一基准电压信号值和所述第二基准电压信号值为负值；或者，所述第一基准电压信号值小于所述第二基准电压信号值，所述第一基准电压信号值为负值，所述第二基准电压信号值大于来自第一电压信号端的第一电压信号的电压值。
  11. 一种阵列基板，包括衬底，及设置于所述衬底上且阵列式布置的多个像素电路，所述像素电路为如权利要求1～7中所述的像素电路。
  12. 根据权利要求11所述的阵列基板，其中，所述像素电路包括驱动晶体管、第一晶体管、第三晶体管和存储电容器；
    所述阵列基板还包括：
    设置于衬底上的第一半导体层，所述第一半导体层包括所述第一晶体管的第一半导体图案、所述第三晶体管的第三半导体图案和所述驱动晶体管的 第七半导体图案；其中，第三半导体图案和所述第七半导体图案相连，且与所述第一半导体图案具有间隔；
    第一栅导电层，位于所述第一半导体层远离所述衬底的一侧，包括第一扫描信号线、第三扫描信号线和所述存储电容器的第一极板；
    第二栅导电层，位于所述第一栅导电层远离所述衬底的一侧，包括所述存储电容器的第二极板。
  13. 根据权利要求12所述的阵列基板，其中，所述像素电路还包括第二晶体管；
    所述阵列基板还包括：
    第二半导体层，位于所述第二栅导电层远离所述衬底的一侧，包括所述第二晶体管的第二半导体图案；
    第三栅导电层，位于所述第二半导体层远离所述衬底的一侧，包括第二扫描信号线和基准电压信号线；
    第一源漏导电层，位于所述第三栅导电层远离所述衬底的一侧，包括第一连接图案、第二连接图案和第三连接图案；所述第一连接图案与所述基准电压信号线和所述第一半导体图案的第一极连接，所述第二连接图案与所述第一半导体图案的第二极、所述第二半导体图案的第一极和所述第七半导体图案的第一极连接，所述第三连接图案与所述第二半导体图案的第二极和所述存储电容器的第一极板连接；
    第二源漏导电层，位于所述第一源漏导电层远离所述衬底的一侧，包括数据线，所述数据线与所述第三半导体图案的第一极连接；所述第三半导体图案的第二极与所述第七半导体图案的第二极连接。
  14. 根据权利要求13所述的阵列基板，其中，
    在向所述衬底的正投影中，所述第二半导体图案与所述第三扫描信号线部分交叠。
  15. 根据权利要求14所述的阵列基板，其中，所述第二半导体图案包括：
    第一部分，在向所述衬底的正投影中，所述第一部分位于所述第二扫描信号线靠近所述存储电容器的一侧，且与所述第三扫描信号线交叠；
    第二部分，与所述第一部分相连，且沿第二方向延伸，在向所述衬底的正投影中，所述第二部分与所述第二扫描信号线交叉；所述第二方向与第一方向交叉；
    其中，沿所述第二方向，所述第一部分的尺寸大于所述第三扫描信号线的尺寸，且在向所述衬底的正投影中，所述第一部分的两端分别位于第三扫 描信号线的两侧。
  16. 根据权利要求15所述的阵列基板，其中，在向所述衬底的正投影中，所述第二部分与所述第二连接图案交叠。
  17. 根据权利要求12～14中任一项所述的阵列基板，其中，所述第二半导体图案沿第二方向延伸，在向所述衬底上的正投影中，所述第二半导体图案与所述第二连接图案相互分离。
  18. 根据权利要求12～17中任一项所述的阵列基板，其中，
    在向所述衬底的正投影中，所述第三连接图案与所述第三扫描信号线部分交叠。
  19. 根据权利要求12～17中任一项所述的阵列基板，其中，在向所述衬底上的正投影中，所述第三连接图案位于所述第三扫描信号线靠近所述存储电容器的一侧；所述第三连接图案与所述第二半导体图案部分交叠，且交叠部分位于所述第三扫描信号线靠近所述存储电容器的一侧。
  20. 根据权利要求19所述的阵列基板，其中，
    所述第三扫描信号线的部分向远离所述存储电容器的一侧弯折，形成凹部，所述第三连接图案与所述第二半导体图案在所述衬底上相互交叠的部分位于所述凹部内。
  21. 根据权利要求12～20中任一项所述的阵列基板，其中，
    所述第三半导体图案为L型结构，所述第三半导体图案包括：
    第一延伸段，沿第一方向延伸，所述第一方向为所述多个子像素排列的行方向；
    第二延伸段，沿第二方向延伸，且与所述第一延伸段相连，所述第二方向与所述第一方向交叉；
    所述第三扫描信号线包括：
    主体部，沿所述第一方向延伸，且所述主体部在所述衬底上的正投影，与所述第二延伸段部分交叠；
    凸出部，沿所述第二方向延伸，且所述凸出部在所述衬底上的正投影，与所述第一延伸段部分交叠。
  22. 根据权利要求17～21中任一项所述的阵列基板，其中，所述第二栅导电层还包括：
    辅助第二扫描信号线，被配置为传输第二扫描信号，且所述辅助第二扫描信号线在所述衬底上的正投影，与所述第一扫描信号线在所述衬底上的正投影交叠。
  23. 一种显示装置，其特征在于，包括：
    如权利要求12～22中任一项所述的阵列基板；
    发光器件，设置于所述阵列基板上，所述发光器件与所述阵列基板的像素电路电连接，被配置为在所述像素电路的控制下发光。
PCT/CN2022/138079 2022-12-09 2022-12-09 像素电路及其驱动方法、阵列基板、显示装置 Ceased WO2024119503A1 (zh)

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WO2023184402A1 (zh) * 2022-03-31 2023-10-05 京东方科技集团股份有限公司 显示基板及其制作方法、显示面板
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109087610A (zh) * 2018-08-20 2018-12-25 武汉华星光电半导体显示技术有限公司 Amoled像素驱动电路、驱动方法及显示面板
CN111508426A (zh) * 2020-05-29 2020-08-07 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN112634830A (zh) * 2019-09-24 2021-04-09 三星显示有限公司 像素电路及包括像素电路的显示装置
CN114530464A (zh) * 2022-02-22 2022-05-24 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN115394252A (zh) * 2022-09-20 2022-11-25 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示面板

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112509517B (zh) * 2020-11-26 2022-07-12 合肥维信诺科技有限公司 像素电路的驱动方法、显示面板
CN115148153B (zh) * 2021-05-17 2024-07-26 上海天马微电子有限公司 显示面板和显示装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN109087610A (zh) * 2018-08-20 2018-12-25 武汉华星光电半导体显示技术有限公司 Amoled像素驱动电路、驱动方法及显示面板
CN112634830A (zh) * 2019-09-24 2021-04-09 三星显示有限公司 像素电路及包括像素电路的显示装置
CN111508426A (zh) * 2020-05-29 2020-08-07 京东方科技集团股份有限公司 像素电路及其驱动方法、显示面板
CN114530464A (zh) * 2022-02-22 2022-05-24 京东方科技集团股份有限公司 阵列基板、显示面板和显示装置
CN115394252A (zh) * 2022-09-20 2022-11-25 京东方科技集团股份有限公司 一种像素驱动电路及其驱动方法、显示面板

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