WO2024117131A1 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
WO2024117131A1
WO2024117131A1 PCT/JP2023/042566 JP2023042566W WO2024117131A1 WO 2024117131 A1 WO2024117131 A1 WO 2024117131A1 JP 2023042566 W JP2023042566 W JP 2023042566W WO 2024117131 A1 WO2024117131 A1 WO 2024117131A1
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WIPO (PCT)
Prior art keywords
trench
insulating film
edge
electrode
region
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Ceased
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PCT/JP2023/042566
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English (en)
French (fr)
Japanese (ja)
Inventor
圭司 山本
肇 奥田
泰詔 福田
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Rohm Co Ltd
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Rohm Co Ltd
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Priority to JP2024561511A priority Critical patent/JPWO2024117131A1/ja
Publication of WO2024117131A1 publication Critical patent/WO2024117131A1/ja
Priority to US19/221,293 priority patent/US20250294804A1/en
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
    • H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
    • H10D30/66—Vertical DMOS [VDMOS] FETs
    • H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
    • H10D62/126—Top-view geometrical layouts of the regions or the junctions
    • H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/393—Body regions of DMOS transistors or IGBTs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H10D62/832—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge being Group IV materials comprising two or more elements, e.g. SiGe
    • H10D62/8325—Silicon carbide
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/111—Field plates
    • H10D64/117—Recessed field plates, e.g. trench field plates or buried field plates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/152—Source regions of DMOS transistors
    • H10D62/155—Shapes 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 

Definitions

  • FIG. 12 of Patent Document 1 discloses a semiconductor device including a substrate, a trench, polycrystalline silicon, and a side spacer.
  • the substrate has a surface.
  • a trench is formed in the surface of the substrate.
  • Polycrystalline silicon is embedded in the trench.
  • the side spacer is made of an insulator such as a nitride film and is formed on the sidewall of the trench on the polycrystalline silicon.
  • the present disclosure provides a semiconductor device having a novel layout for a trench structure.
  • the present disclosure provides a semiconductor device including a chip having a main surface, a trench formed in the main surface and having a sidewall and a bottom wall, a buried electrode embedded in the trench, the buried electrode having an electrode surface located closer to the bottom wall than the main surface, and a recess edge portion recessed toward the bottom wall at an edge portion of the electrode surface along the sidewall, and an edge insulator embedded in the recess edge portion.
  • FIG. 1 is a plan view showing a semiconductor device according to a specific embodiment.
  • FIG. 2 is a cross-sectional view taken along the line II-II shown in FIG.
  • FIG. 3 is a schematic circuit diagram showing an electrical configuration of the semiconductor device shown in FIG.
  • FIG. 4 is a schematic circuit diagram showing a configuration of an output transistor.
  • FIG. 5 is a plan view showing the output area.
  • FIG. 6 is an enlarged plan view showing a main part of the output area of FIG.
  • FIG. 7 is an enlarged plan view showing a further essential part of the output region of FIG.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG.
  • FIG. 9 is a cross-sectional view taken along line IX-IX in FIG.
  • FIG. 10 is a cross-sectional view taken along line X-X of FIG.
  • FIG. 11 is a cross-sectional view taken along line XI-XI in FIG.
  • FIG. 12 is a cross-sectional view taken along line XII-XII in FIG.
  • FIG. 13 is an enlarged cross-sectional view of one trench structure extracted from FIG.
  • FIG. 14 is an enlarged cross-sectional view of one trench structure extracted from FIG.
  • FIG. 15 is an enlarged cross-sectional view of one trench structure extracted from FIG.
  • FIG. 16 is an enlarged cross-sectional view showing a main part of the trench structure.
  • FIG. 17 is a schematic diagram showing a wafer used in the manufacture of semiconductor devices.
  • FIG. 17 is a schematic diagram showing a wafer used in the manufacture of semiconductor devices.
  • FIG. 18A is a cross-sectional view for explaining a manufacturing method of a semiconductor device.
  • FIG. 18B is a cross-sectional view showing a step subsequent to that of FIG. 18A.
  • FIG. 18C is a cross-sectional view showing a step subsequent to FIG. 18B.
  • FIG. 18D is a cross-sectional view showing a step subsequent to FIG. 18C.
  • FIG. 18E is a cross-sectional view showing a step subsequent to FIG. 18D.
  • FIG. 18F is a cross-sectional view showing a step subsequent to FIG. 18E.
  • FIG. 18G is a cross-sectional view showing a step subsequent to FIG. 18F.
  • FIG. 18H is a cross-sectional view showing a step subsequent to FIG. 18G.
  • FIG. 18I is a cross-sectional view showing a step subsequent to FIG. 18H.
  • FIG. 18J is a cross-sectional view showing a step subsequent to FIG. 18I.
  • FIG. 18K is a cross-sectional view showing a step subsequent to FIG. 18J.
  • FIG. 18L is a cross-sectional view showing a step subsequent to FIG. 18K.
  • FIG. 18M is a cross-sectional view showing a step subsequent to FIG. 18L.
  • FIG. 18N is a cross-sectional view showing a step subsequent to FIG. 18M.
  • FIG. 18O is a cross-sectional view showing a step subsequent to FIG. 18N.
  • FIG. 18P is a cross-sectional view showing a step subsequent to that shown in FIG. 18O.
  • FIG. 18P is a cross-sectional view showing a step subsequent to that shown in FIG. 18O.
  • FIG. 18P is a cross-sectional view showing a step subsequent to that shown in FIG.
  • FIG. 18Q is a cross-sectional view showing a step subsequent to FIG. 18P.
  • FIG. 18R is a cross-sectional view showing a step subsequent to FIG. 18Q.
  • FIG. 18S is a cross-sectional view showing a step subsequent to FIG. 18R.
  • FIG. 18T is a cross-sectional view showing a step subsequent to FIG. 18S.
  • FIG. 18U is a cross-sectional view showing a step subsequent to FIG. 18T.
  • FIG. 18V is a cross-sectional view showing a step subsequent to FIG. 18U.
  • FIG. 18W is a cross-sectional view showing a step subsequent to FIG. 18V.
  • FIG. 18X is a cross-sectional view showing a step subsequent to FIG. 18W.
  • FIG. 19 is a cross-sectional view comparing a trench structure on the first device region side and a trench structure on the second device region side.
  • FIG. 20 is a graph showing the relationship between channel length and recess depth.
  • FIG. 21 is a cross-sectional view showing another example of the gate structure.
  • FIG. 22 is a cross-sectional view showing another example of the gate structure.
  • FIG. 23 is a cross-sectional view showing another example of the gate structure.
  • FIG. 24 is a cross-sectional view showing another example of the gate structure.
  • FIG. 25 is a cross-sectional view showing another example of the gate structure.
  • this wording includes a numerical value (shape) that is equal to the numerical value (shape) of the comparison target, as well as a numerical error (shape error) within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • shape a numerical value that is equal to the numerical value (shape) of the comparison target
  • error a numerical error within a range of ⁇ 10% based on the numerical value (shape) of the comparison target.
  • the conductivity type of a semiconductor region is indicated using “p-type” or “n-type”, but “p-type” may also be referred to as the “first conductivity type” and “n-type” as the “second conductivity type”. Of course, “n-type” may also be referred to as the "first conductivity type” and “p-type” as the “second conductivity type”.
  • P-type is a conductivity type resulting from a trivalent element
  • n-type is a conductivity type resulting from a pentavalent element.
  • the trivalent element is at least one of boron, aluminum, gallium, and indium.
  • the pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.
  • FIG. 1 is a plan view showing a semiconductor device 1 according to a specific embodiment.
  • FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1.
  • the semiconductor device 1 includes a chip 2 formed in a rectangular parallelepiped shape.
  • the chip 2 is a Si chip including a Si single crystal.
  • chip 2 may be made of a wide bandgap semiconductor chip that includes a single crystal of a wide bandgap semiconductor.
  • a wide bandgap semiconductor is a semiconductor that has a bandgap larger than the bandgap of Si. Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond).
  • chip 2 may be a SiC chip that includes a single crystal of SiC.
  • the chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4.
  • the first main surface 3 and the second main surface 4 are formed in a quadrangular shape when viewed in a plan view from their normal direction Z (hereinafter simply referred to as "plan view").
  • the normal direction Z is also the thickness direction of the chip 2.
  • the first main surface 3 is a circuit surface on which various circuit structures that constitute an electronic circuit are formed.
  • the second main surface 4 is a non-circuit surface that does not have any circuit structures.
  • the first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face (face away from) a second direction Y that intersects (specifically, is perpendicular to) the first direction X.
  • the third side surface 5C and the fourth side surface 5D extend in the second direction Y and face (face away from) the first direction X.
  • the semiconductor device 1 includes an output region 6 provided on the first main surface 3.
  • the output region 6 is a region having an electronic circuit (circuit device) configured to generate an output signal to be output to the outside.
  • the output region 6 is partitioned into an area on the first side surface 5A side of the first main surface 3.
  • the output region 6 is partitioned into a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.
  • the position, size, planar shape, etc. of the output area 6 are arbitrary and are not limited to a specific layout.
  • the output area 6 may have a planar area of 25% to 80% of the planar area of the first main surface 3.
  • the planar area of the output area 6 may be 30% or more of the planar area of the first main surface 3.
  • the planar area of the output area 6 may be 40% or more of the planar area of the first main surface 3.
  • the planar area of the output area 6 may be 50% or more of the planar area of the first main surface 3.
  • the planar area of the output area 6 may be 75% or less of the planar area of the first main surface 3.
  • the semiconductor device 1 includes a control region 7 provided in a region on the first main surface 3 different from the output region 6.
  • the control region 7 is a region having multiple types of electronic circuits (circuit devices) configured to generate control signals that control the output region 6.
  • the control region 7 is defined in a region on the second side surface 5B side of the output region 6, and faces the output region 6 in the second direction Y.
  • the control region 7 is defined in a polygonal shape (a square shape in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.
  • the position, size, planar shape, etc. of the control area 7 are arbitrary and are not limited to a specific layout.
  • the control area 7 may have a planar area of 25% or more and 80% or less of the planar area of the first main surface 3.
  • the planar area of the control area 7 may be 30% or more of the planar area of the first main surface 3.
  • the planar area of the control area 7 may be 40% or more of the planar area of the first main surface 3.
  • the planar area of the control area 7 may be 50% or more of the planar area of the first main surface 3.
  • the planar area of the control area 7 may be 75% or less of the planar area of the first main surface 3.
  • the planar area of the control area 7 may be approximately equal to the planar area of the output area 6.
  • the planar area of the control area 7 may be greater than the planar area of the output area 6.
  • the planar area of the control area 7 may be smaller than the planar area of the output area 6.
  • the ratio of the planar area of the control area 7 to the planar area of the output area 6 may be 0.1 or more and 4 or less.
  • the semiconductor device 1 includes an n-type (first conductivity type) drain region 8 formed in a surface layer portion of the second main surface 4.
  • the n-type impurity concentration of the drain region 8 may be 1 ⁇ 10 18 cm -3 or more and 1 ⁇ 10 21 cm -3 or less.
  • the drain region 8 is formed in a layer shape extending along the second main surface 4 throughout the entire surface layer portion of the second main surface 4, and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D.
  • the drain region 8 may have a thickness of 50 ⁇ m or more and 200 ⁇ m or less.
  • the thickness of the drain region 8 is preferably 150 ⁇ m or less.
  • the drain region 8 is formed from an n-type semiconductor substrate (Si substrate).
  • the semiconductor device 1 includes an n-type drift region 9 formed in a surface layer portion of the first main surface 3.
  • the drift region 9 has a lower n-type impurity concentration than the drain region 8.
  • the n-type impurity concentration of the drift region 9 may be not less than 1 ⁇ 10 15 cm ⁇ 3 and not more than 1 ⁇ 10 18 cm ⁇ 3 .
  • the drift region 9 is formed in the output region 6 and the control region 7 in a layer shape extending along the first main surface 3.
  • the drift region 9 is formed in a layer extending along the first main surface 3 over the entire surface portion of the first main surface 3, and is exposed from the first main surface 3 and the first to fourth side surfaces 5A to 5D.
  • the drift region 9 is electrically connected to the drain region 8 within the chip 2.
  • the drift region 9 has a thickness less than the thickness of the drain region 8.
  • the thickness of the drift region 9 may be 1 ⁇ m or more and 20 ⁇ m or less.
  • the thickness of the drift region 9 is preferably 5 ⁇ m or more and 15 ⁇ m or less. It is particularly preferable that the thickness of the drift region 9 is 10 ⁇ m or less.
  • the drift region 9 is formed by an n-type epitaxial layer (Si epitaxial layer).
  • the semiconductor device 1 includes an interlayer film 10 that covers the first main surface 3.
  • the interlayer film 10 collectively covers the output region 6 and the control region 7.
  • the interlayer film 10 may cover the entire first main surface 3 so as to be continuous with the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D).
  • the interlayer film 10 may be formed at a distance inward from the periphery of the first main surface 3 so as to expose the periphery of the first main surface 3.
  • the interlayer film 10 has a multilayer wiring structure having a laminated structure in which multiple insulating layers and multiple wiring layers are alternately stacked.
  • Each insulating layer may include at least one of a silicon oxide film and a silicon nitride film.
  • Each wiring layer may include at least one of a pure Al layer (Al layer with a purity of 99% or more), a Cu layer (Cu layer with a purity of 99% or more), an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.
  • the semiconductor device 1 includes a plurality of terminals 11-13 arranged on either or both of the first main surface 3 and the second main surface 4 (both in this embodiment).
  • the plurality of terminals 11-13 includes a source terminal 11, a plurality of control terminals 12, and a drain terminal 13.
  • the source terminal 11 is provided as an output terminal electrically connected to a load, and is disposed on a portion of the interlayer film 10 that covers the output region 6.
  • the source terminal 11 may cover the entire output region 6 in a plan view.
  • the source terminal 11 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.
  • the multiple control terminals 12 are terminals electrically connected to various electronic circuits in the control region 7, and are arranged on the portion of the interlayer film 10 that covers the control region 7.
  • the multiple ground terminals include various terminals such as a ground terminal, an input terminal, a cathode terminal, an anode terminal, and a test terminal, depending on the circuit configuration in the control region 7.
  • the multiple control terminals 12 each have a planar area less than the planar area of the source terminal 11, and are arranged at intervals along the periphery of the control region 7 (the periphery of the first main surface 3).
  • the planar area of each control terminal 12 is set to a range that allows a bonding wire to be connected.
  • the planar area of each control terminal 12 may be 1/10 or less of the planar area of the source terminal 11.
  • the multiple control terminals 12 may include at least one of a pure Al layer, a Cu layer, an AlCu alloy layer, an AlSiCu alloy layer, and an AlSi alloy layer.
  • the drain terminal 13 is provided as a power supply terminal and directly covers the second main surface 4 of the chip 2. That is, in this embodiment, the semiconductor device 1 is a high-side switching device that is electrically interposed between a power supply and a load. The drain terminal 13 is electrically connected to the drain region 8 on the second main surface 4. The drain terminal 13 covers the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (the first to fourth side surfaces 5A to 5D).
  • FIG. 3 is a schematic circuit diagram showing the electrical configuration of the semiconductor device 1 shown in FIG. 1.
  • FIG. 4 is a schematic circuit diagram showing the configuration of the output transistor 15.
  • FIG. 3 shows an example in which an inductive load L, as an example of a load, is electrically connected to the source terminal 11 to show an example of the operation of the semiconductor device 1.
  • the inductive load L is not a component of the semiconductor device 1. Therefore, a configuration including the semiconductor device 1 and the inductive load L may be referred to as an "inductive load driving device” or an “inductive load control device.” Examples of the inductive load L include relays, solenoids, lamps, motors, etc.
  • the inductive load L may be an inductive load L for use in a vehicle.
  • the semiconductor device 1 may be an inductive load 1 for use in a vehicle.
  • the semiconductor device 1 includes an output transistor 15 formed in the output region 6.
  • the output transistor 15 is a gate split transistor including one main drain, one main source, and multiple main gates.
  • the main drain is electrically connected to the drain terminal 13.
  • the main source is electrically connected to the source terminal 11.
  • the multiple main gates are configured so that multiple electrically independent gate signals (gate potentials) are input individually.
  • the output transistor 15 generates a single output current Io (output signal) in response to the multiple gate signals.
  • the output transistor 15 is a multi-input single-output type switching device.
  • the output current Io is a drain-source current that flows between the main drain and the main source.
  • the output current Io is output outside the chip 2 (to the inductive load L) via the source terminal 11.
  • the output transistor 15 includes a plurality (two or more) of system transistors 16 that are electrically and independently controlled.
  • the plurality of system transistors 16 includes a first system transistor 16A and a second system transistor 16B.
  • the plurality of system transistors 16 are formed in a concentrated manner in the output region 6.
  • the plurality of system transistors 16 are connected in parallel so that a plurality of gate signals are inputted individually, and are configured so that the system transistors 16 in the on state and the system transistors 16 in the off state coexist.
  • the multiple system transistors 16 each include a system drain, a system source, and a system gate.
  • the multiple system drains are electrically connected to the main drain (drain terminal 13).
  • the multiple system sources are electrically connected to the main source (source terminal 11).
  • Each system gate is electrically connected to each main gate. In other words, each system gate constitutes each main gate.
  • the multiple system transistors 16 each generate a system current Is in response to a corresponding gate signal.
  • Each system current Is is a drain-source current flowing between the system drain and system source of each system transistor 16.
  • the multiple system currents Is may have different values or may have approximately equal values.
  • the multiple system currents Is are added between the main drain and main source. This generates a single output current Io consisting of the sum of the multiple system currents Is.
  • the multiple system transistors 16 each include a single or multiple unit transistors 17 that are organized (grouped) as individual control targets. Specifically, the multiple system transistors 16 are configured with a single unit transistor 17 or a parallel circuit including multiple unit transistors 17. In this embodiment, each of the multiple unit transistors 17 is of a trench gate vertical type. The multiple system transistors 16 may be configured with the same number of unit transistors 17, or may be configured with different numbers of unit transistors 17.
  • Each unit transistor 17 includes a unit drain, a unit source, and a unit gate.
  • the unit drain of each unit transistor 17 is electrically connected to the system drain of the corresponding system transistor 16.
  • the unit source of each unit transistor 17 is electrically connected to the system source of the corresponding system transistor 16.
  • the unit gate of each unit transistor 17 is electrically connected to the system gate of the corresponding system transistor 16.
  • the multiple unit transistors 17 each generate a unit current Iu in response to a corresponding gate signal.
  • Each unit current Iu is a drain-source current that flows between the unit drain and unit source of each unit transistor 17.
  • the multiple unit currents Iu may have different values or may have approximately equal values.
  • the multiple unit currents Iu are added between the corresponding system drains and system sources. This generates a system current Is consisting of the sum of the multiple unit currents Iu.
  • the output transistor 15 is configured so that the first system transistor 16A and the second system transistor 16B are controlled to be turned on and off while being electrically independent of each other. That is, the output transistor 15 is configured so that both the first system transistor 16A and the second system transistor 16B are simultaneously in the on state. Also, the output transistor 15 is configured so that either the first system transistor 16A or the second system transistor 16B is in the on state and the other is in the off state.
  • the output transistor 15 is made of an on-resistance variable switching device.
  • the semiconductor device 1 includes a control circuit 18 formed in the control region 7 so as to be electrically connected to the output transistor 15.
  • the control circuit 18 may be referred to as a "control IC.”
  • the control circuit 18 has various functional circuits, and together with the output transistor 15, constitutes an IPD (Intelligent Power Device).
  • the IPD may be referred to as an "IPM (Intelligent Power Module),” an “IPS (Intelligent Power Switch),” a “smart power driver,” a “smart MISFET (smart MOSFET),” or a "protected MISFET (protected MOSFET).”
  • control circuit 18 includes a gate control circuit 19, a current monitor circuit 20, an overcurrent protection circuit 21, an overheat protection circuit 22, a low voltage malfunction avoidance circuit 23, an open load detection circuit 24, an active clamp circuit 25, a power supply reverse connection protection circuit 26, and a logic circuit 27.
  • the control circuit 18 does not necessarily need to include all of these functional circuits at the same time, and it is sufficient if it includes at least one of these functional circuits.
  • the current monitor circuit 20 may be referred to as a CS circuit (Current Sense circuit).
  • the overcurrent protection circuit 21 may be referred to as an OCP circuit (Over Current Protection circuit).
  • the overheat protection circuit 22 may be referred to as a TSD circuit (Thermal shutdown circuit).
  • the low voltage malfunction avoidance circuit 23 may be referred to as a UVLO circuit (Under Voltage Lock Out circuit).
  • the open load detection circuit 24 may be referred to as an OLD circuit (Open Load Detection circuit).
  • the power supply reverse connection protection circuit 26 may be referred to as an RBP circuit (Reverse Battery Protection circuit).
  • the gate control circuit 19 is configured to generate a gate signal that controls the on/off state of the output transistor 15. Specifically, the gate control circuit 19 generates a plurality of gate signals that individually control the on/off state of the plurality of system transistors 16. That is, in this embodiment, the gate control circuit 19 generates a first gate signal that individually controls the on/off state of the first system transistor 16A, and a second gate signal that individually controls the on/off state of the second system transistor 16B electrically independent of the first system transistor 16A.
  • the current monitor circuit 20 generates a monitor current that monitors the output current Io of the output transistor 15 and outputs it to another circuit.
  • the current monitor circuit 20 may be configured to include a transistor having a similar configuration to the output transistor 15, and to generate a monitor current linked to the output current Io by being controlled to be turned on and off simultaneously with the output transistor 15.
  • the current monitor circuit 20 may also be configured to generate a monitor current linked to one or more system currents Is.
  • the overcurrent protection circuit 21 generates an electrical signal that controls the gate control circuit 19 based on the monitor current from the current monitor circuit 20, and cooperates with the gate control circuit 19 to control the on/off state of the output transistor 15.
  • the overcurrent protection circuit 21 may be configured to determine that the output transistor 15 is in an overcurrent state when the monitor current is equal to or greater than a predetermined threshold, and to cooperate with the gate control circuit 19 to control some or all of the output transistor 15 (multiple system transistors 16) to an off state.
  • the overcurrent protection circuit 21 may also be configured to cooperate with the gate control circuit 19 to transition the output transistor 15 to normal operation when the monitor current is less than a predetermined threshold.
  • the overheat protection circuit 22 includes a first temperature sensing device (e.g., a temperature sensing diode) that detects the temperature of the output region 6, and a second temperature sensing device (e.g., a temperature sensing diode) that detects the temperature of the control region 7.
  • the overheat protection circuit 22 generates an electrical signal that controls the gate control circuit 19 based on a first temperature detection signal from the first temperature sensing device and a second temperature detection signal from the second temperature sensing device, and cooperates with the gate control circuit 19 to control the on/off of the output transistor 15.
  • the overheat protection circuit 22 may be configured to determine that the output region 6 is in an overheated state when the difference value between the first temperature detection signal and the second temperature detection signal is equal to or greater than a predetermined threshold, and to cooperate with the gate control circuit 19 to control some or all of the output transistors 15 (multiple system transistors 16) to an off state.
  • the overheat protection circuit 22 may also be configured to cooperate with the gate control circuit 19 to transition the output transistors 15 to normal operation when the difference value is less than a predetermined threshold.
  • the low voltage malfunction avoidance circuit 23 is configured to prevent various functional circuits in the control circuit 18 from malfunctioning when the startup voltage for starting the control circuit 18 is less than a predetermined value.
  • the low voltage malfunction avoidance circuit 23 may be configured to start the control circuit 18 when the startup voltage is equal to or greater than a predetermined threshold voltage, and to stop the control circuit 18 when the startup voltage is less than the threshold voltage.
  • the threshold voltage may have a hysteresis characteristic.
  • the open load detection circuit 24 determines the electrical connection state of the inductive load L.
  • the open load detection circuit 24 may be configured to monitor the terminal voltage of the output transistor 15 and determine that the inductive load L is in an open state when the terminal voltage is equal to or greater than a predetermined threshold.
  • the open load detection circuit 24 may be configured to determine that the inductive load L is in an open state when the monitor current is equal to or less than a predetermined threshold.
  • the active clamp circuit 25 is electrically connected to the main drain and at least one main gate (for example, the system gate of the first system transistor 16A) of the output transistor 15.
  • the active clamp circuit 25 includes a Zener diode and a pn junction diode connected in series with the Zener diode in a reverse bias state.
  • the pn junction diode is a backflow prevention diode that prevents backflow from the output transistor 15.
  • the active clamp circuit 25 is configured to cooperate with the gate control circuit 19 to control a part or all of the output transistor 15 to the on state when a back electromotive force caused by the inductive load L is applied to the output transistor 15. Specifically, the output transistor 15 is controlled in a number of operating modes including a normal operation, a first off operation, an active clamp operation, and a second off operation.
  • both the first system transistor 16A and the second system transistor 16B are simultaneously controlled to the on state. This increases the channel utilization rate of the output transistor 15 and reduces the on resistance.
  • both the first system transistor 16A and the second system transistor 16B are simultaneously controlled from the on state to the off state. This causes the back electromotive force caused by the inductive load L to be applied to both the first system transistor 16A and the second system transistor 16B.
  • Active clamp operation is an operation in which the energy stored in the inductive load L is absorbed (consumed) by the output transistor 15, and is executed when the back electromotive force caused by the inductive load L exceeds a predetermined threshold voltage.
  • the first system transistor 16A is controlled from an off state to an on state, and at the same time, the second system transistor 16B is controlled (maintained) in an off state.
  • the channel utilization rate of the output transistor 15 during active clamp operation is less than the channel utilization rate of the output transistor 15 during normal operation.
  • the on-resistance of the output transistor 15 during active clamp operation is greater than the on-resistance of the output transistor 15 during normal operation. This suppresses a sudden increase in temperature of the output transistor 15 during active clamp operation, improving the active clamp tolerance.
  • the second off operation is executed when the back electromotive force voltage falls below a predetermined threshold voltage.
  • the first system transistor 16A is controlled from the on state to the off state, and at the same time, the second system transistor 16B is controlled (maintained) in the off state.
  • the back electromotive force (energy) of the inductive load L is absorbed by a part of the output transistor 15 (here, the first system transistor 16A).
  • the first system transistor 16A may be controlled (maintained) in the off state, and the second system transistor 16B may be controlled to the on state.
  • the power supply reverse connection protection circuit 26 is configured to detect the reverse voltage that occurs when the power supply is connected in reverse, and to protect the control circuit 18 and the output transistor 15 from the reverse voltage (reverse current).
  • the logic circuit 27 is configured to generate an electrical signal that is supplied to various circuits within the control circuit 18.
  • Fig. 5 is a plan view showing the output area 6.
  • Fig. 6 is an enlarged plan view showing a main part of the output area 6 in Fig. 5.
  • Fig. 7 is an enlarged plan view showing further main parts of the output area 6 in Fig. 5.
  • FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 6.
  • FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 6.
  • FIG. 10 is a cross-sectional view taken along line X-X in FIG. 6.
  • FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 6.
  • FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 6.
  • FIG. 13 is an enlarged cross-sectional view of one gate structure 40 (trench structure) extracted from FIG. 8 together with a source region 71.
  • FIG. 14 is an enlarged cross-sectional view of one gate structure 40 (trench structure) extracted from FIG. 8 together with a contact region 72.
  • FIG. 15 is an enlarged cross-sectional view of one gate structure 40 (trench structure) extracted from FIG. 9.
  • FIG. 16 is an enlarged cross-sectional view showing a main portion of a gate structure 40 (trench structure).
  • the semiconductor device 1 includes one or more (one in this embodiment) trench electrode type (trench insulation type) isolation structures 30 formed on the first main surface 3 so as to partition the output region 6.
  • the isolation structure 30 may be referred to as a "trench isolation structure", a "region isolation structure”, etc.
  • the isolation structure 30 electrically isolates the output region 6 from the control region 7 within the chip 2.
  • a source potential may be applied to the isolation structure 30.
  • the isolation structure 30 is formed in a ring shape surrounding the output region 6 in a plan view.
  • the isolation structure 30 is formed in a polygonal ring shape (a square ring in this embodiment) having four sides parallel to the periphery of the first main surface 3 in a plan view.
  • the isolation structure 30 is formed at a distance from the bottom of the drift region 9 toward the first main surface 3, and faces the drain region 8 across a portion of the drift region 9.
  • the isolation structure 30 has an isolation width WI and an isolation depth DI.
  • the isolation width WI is the width in a direction perpendicular to the extension direction of the isolation structure 30.
  • the isolation width WI may be 0.4 ⁇ m or more and 2.5 ⁇ m or less.
  • the isolation width WI may have a value belonging to any one of the following ranges: 0.4 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the isolation width WI is preferably 1.25 ⁇ m or more and 1.75 ⁇ m or less.
  • the separation depth DI may be 1 ⁇ m or more and 10 ⁇ m or less.
  • the separation depth DI may have a value that belongs to any one of the following ranges: 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 6 ⁇ m or less, 6 ⁇ m or more and 8 ⁇ m or less, and 8 ⁇ m or more and 10 ⁇ m or less. It is preferable that the separation depth DI is 3 ⁇ m or more and 5 ⁇ m or less.
  • the isolation structure 30 includes an isolation trench 31, an isolation insulating film 32, and an isolation electrode 33.
  • the isolation structure 30 has a single electrode structure including a single electrode (isolation electrode 33) embedded in the isolation trench 31 with an insulator (isolation insulating film 32) sandwiched therebetween.
  • the isolation trench 31 is formed on the first main surface 3 and defines the wall surface of the isolation structure 30.
  • the isolation trench 31 may be formed in a tapered shape in which the opening width gradually narrows from the opening side toward the bottom wall side in a cross-sectional view.
  • the isolation insulating film 32 covers the wall surface of the isolation trench 31.
  • the isolation insulating film 32 may include a silicon oxide film.
  • the isolation insulating film 32 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film (oxide separate from the chip 2) formed by a CVD method.
  • the isolation insulating film 32 may have a thickness of 100 nm or more and 500 nm or less.
  • the isolation electrode 33 is embedded in the isolation trench 31 with an isolation insulating film 32 sandwiched therebetween.
  • the isolation electrode 33 may include n-type or p-type conductive polysilicon.
  • the multiple isolation structures 30 are formed in an annular shape surrounding the output region 6 with spaces between them, and isolate one output region 6 from the control region 7. In this case, it is preferable that the multiple isolation structures 30 are formed with a fixed space between them.
  • the semiconductor device 1 includes an output transistor 15 formed on the first main surface 3 in the output region 6.
  • the following configurations are described as components of the semiconductor device 1, but are also components of the output transistor 15.
  • the semiconductor device 1 includes an n-type high-concentration drift region 35 formed in a surface layer portion of the drift region 9 in the output region 6.
  • the high-concentration drift region 35 has a higher n-type impurity concentration than the drift region 9.
  • the n-type impurity concentration of the high-concentration drift region 35 may be lower than the n-type impurity concentration of the drain region 8.
  • the n-type impurity concentration of the high-concentration drift region 35 may be 1 ⁇ 10 16 cm ⁇ 3 or more and 1 ⁇ 10 19 cm ⁇ 3 or less.
  • the high-concentration drift region 35 may be regarded as a part (high concentration portion) of the drift region 9.
  • the high-concentration drift region 35 forms a concentration gradient within the drift region 9 in which the n-type impurity concentration increases from the bottom side of the drift region 9 toward the first main surface 3.
  • the drift region 9 in the output region 6 has a concentration gradient formed by the high-concentration drift region 35 such that the n-type impurity concentration increases from the bottom side toward the first main surface 3.
  • the high-concentration drift region 35 is formed in the inner part of the output region 6 at a distance from the isolation structure 30. Therefore, the high-concentration drift region 35 is surrounded by the drift region 9 in the output region 6 and is not in contact with the isolation structure 30. The high-concentration drift region 35 locally increases the n-type impurity concentration of the drift region 9 in the output region 6.
  • the high-concentration drift region 35 is formed at a distance from the bottom of the drift region 9 toward the first main surface 3, and faces the drain region 8 across a portion of the drift region 9.
  • the high-concentration drift region 35 has a bottom that is located closer to the bottom of the drift region 9 than the bottom wall of the isolation structure 30.
  • the bottom of the high-concentration drift region 35 meanders to one side and the other side in the thickness direction in a cross-sectional view.
  • the bottom of the high-concentration drift region 35 has multiple bulges 36 and multiple recesses 37 in a cross-sectional view.
  • the multiple bulges 36 are arc-shaped bulges toward the bottom of the drift region 9.
  • the multiple bulges 36 are formed continuously in the first direction X in a plan view, and are each formed in a band shape extending in the second direction Y. Each bulge 36 is formed wider than the separation structure 30 in the first direction X.
  • the multiple recesses 37 are each formed in a band shape extending in the second direction Y in the region between the multiple bulges 36.
  • the multiple recesses 37 are portions where the shallow parts of the multiple bulges 36 are connected to each other, and are located on the first main surface 3 side of the deepest parts of the multiple bulges 36.
  • the high-concentration drift region 35 may have a flat bottom that does not meander up and down in the thickness direction.
  • the high-concentration drift region 35 may be configured so that the entire drift region 9 in the output region 6 is highly concentrated. With this configuration, the on-resistance of the drift region 9 can be reduced by increasing the concentration of the drift region 9. However, in this case, attention should be paid to the possibility that the breakdown voltage may decrease as a result of electric field concentration being more likely to occur due to the increase in carrier density in the drift region 9. Therefore, in order to reduce the on-resistance while suppressing the decrease in the breakdown voltage, it is preferable to introduce the high-concentration drift region 35 into a part of the output region 6.
  • the semiconductor device 1 includes a plurality of trench electrode type gate structures 40 formed on the first main surface 3 in the output region 6.
  • the gate structures 40 may be referred to as “trench structures”, “trench gate structures”, etc.
  • the plurality of gate structures 40 are formed in the inner part of the output region 6 at a distance from the isolation structure 30.
  • the multiple gate structures 40 are arranged at intervals in the first direction X, and are each formed in a band shape extending in the second direction Y. In other words, the multiple gate structures 40 are arranged in a stripe shape extending in the second direction Y.
  • the multiple gate structures 40 have a first end on one side in the longitudinal direction (second direction Y) and a second end on the other side in the longitudinal direction (second direction Y).
  • the first end is located in a region between the isolation structure 30 and one end of the high concentration drift region 35 in a planar view.
  • the second end is located in a region between the isolation structure 30 and the other end of the high concentration drift region 35 in a planar view.
  • the multiple gate structures 40 cross one end and the other end of the high concentration drift region 35 in the longitudinal direction (second direction Y).
  • the multiple gate structures 40 are formed at intervals from the bottom of the drift region 9 toward the first main surface 3 in a cross-sectional view, and face the drain region 8 with a portion of the drift region 9 in between. Specifically, the multiple gate structures 40 are formed at intervals from the bottom of the high-concentration drift region 35 toward the first main surface 3, and face the drift region 9 with a portion of the high-concentration drift region 35 in between.
  • the multiple gate structures 40 are positioned within the high-concentration drift region 35 in a cross-sectional view.
  • the multiple gate structures 40 are formed offset in the first direction X with respect to the multiple recesses 37, and face the multiple bulges 36 in the thickness direction, respectively. It is preferable that the multiple gate structures 40 face the deepest parts of the multiple bulges 36.
  • the two gate structures 40 located on both sides in the first direction X are preferably formed in a region outside the high-concentration drift region 35.
  • the outermost gate structure 40 is preferably located within the drift region 9 at a position spaced from the high-concentration drift region 35 toward the isolation structure 30.
  • the outermost gate structure 40 is formed spaced from the bottom of the drift region 9 toward the first main surface 3, and faces the drain region 8 across a portion of the drift region 9.
  • the multiple gate structures 40 have a gate width WG (trench width) and a gate depth DG (trench depth).
  • the gate width WG is the width in a direction perpendicular to the extension direction of the gate structures 40 (i.e., the first direction X).
  • the gate width WG may be approximately equal to the isolation width WI. It is preferable that the gate width WG is equal to or smaller than the isolation width WI. It is particularly preferable that the gate width WG is less than the isolation width WI.
  • the gate width WG may be 0.4 ⁇ m or more and 2 ⁇ m or less.
  • the gate width WG may have a value that belongs to any one of the following ranges: 0.4 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the gate width WG is preferably 0.8 ⁇ m or more and 1.2 ⁇ m or less.
  • the gate depth DG may be approximately equal to the isolation depth DI. It is preferable that the gate depth DG is equal to or less than the isolation depth DI. It is particularly preferable that the gate depth DG is less than the isolation depth DI.
  • the gate depth DG may be 1 ⁇ m or more and 6 ⁇ m or less.
  • the gate depth DG may have a value that belongs to any one of the ranges of 1 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 5 ⁇ m or less, and 5 ⁇ m or more and 6 ⁇ m or less. It is preferable that the gate depth DG is 2.5 ⁇ m or more and 4.5 ⁇ m or less.
  • the multiple gate structures 40 are arranged in the first direction X at a predetermined trench pitch TP.
  • the trench pitch TP is also the mesa width of the mesa portion defined in the region between two adjacent gate structures 40.
  • the trench pitch TP is preferably equal to or smaller than the isolation width WI.
  • the trench pitch TP is preferably equal to or smaller than the gate width WG. It is particularly preferable that the trench pitch TP is less than the gate width WG.
  • the trench pitch TP may be 0.4 ⁇ m or more and 0.8 ⁇ m or less.
  • the trench pitch TP may have a value that falls within any one of the ranges of 0.4 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.6 ⁇ m or less, 0.6 ⁇ m or more and 0.7 ⁇ m or less, and 0.7 ⁇ m or more and 0.8 ⁇ m or less.
  • the trench pitch TP is preferably 0.5 ⁇ m or more and 0.7 ⁇ m or less.
  • the gate structure 40 includes a trench 41, an insulating film 42, and a buried electrode 43.
  • the trench 41 is formed in the first main surface 3 and defines the wall surface of the gate structure 40.
  • the trench 41 is formed in a tapering shape in which the opening width gradually narrows from the opening side toward the bottom wall side in a cross-sectional view.
  • the trench 41 has a first trench portion 44, a second trench portion 45, and a third trench portion 46 formed in this order from the opening side toward the bottom wall side in a cross-sectional view.
  • the first trench portion 44 is formed relatively wide on the surface layer of the first main surface 3, and defines the uppermost end (opening end) of the trench 41.
  • the first trench portion 44 has an upper end on the first main surface 3 side, and a lower end on the bottom wall side of the trench 41.
  • the upper end of the first trench portion 44 defines an opening end extending in an arc shape, and is connected to the first main surface 3.
  • the lower end of the first trench portion 44 defines a first inclined portion 44a that slopes diagonally downward into the trench 41.
  • the first trench portion 44 has a relatively wide first width W1 and a relatively shallow first depth D1.
  • the first width W1 forms the gate width WG.
  • the first depth D1 is the depth between the upper and lower ends of the first trench portion 44.
  • the first depth D1 may be 0.1 ⁇ m or more and 1 ⁇ m or less.
  • the first depth D1 may have a value that belongs to at least one of the ranges of 0.1 ⁇ m or more and 0.25 ⁇ m or less, 0.25 ⁇ m or more and 0.5 ⁇ m or less, 0.5 ⁇ m or more and 0.75 ⁇ m or less, and 0.75 ⁇ m or more and 1 ⁇ m or less. It is preferable that the first depth D1 is 0.1 ⁇ m or more and 0.5 ⁇ m or less.
  • the second trench portion 45 is formed narrower than the first trench portion 44 in the region below the first trench portion 44, and defines the middle portion of the trench 41.
  • the second trench portion 45 has an upper end on the first trench portion 44 side and a lower end on the bottom wall side of the trench 41.
  • the upper end of the second trench portion 45 is connected to the lower end (first inclined portion 44a) of the first trench portion 44.
  • the lower end of the second trench portion 45 defines a second inclined portion 45a that slopes diagonally downward toward the inside of the trench 41.
  • the second inclined portion 45a is located on the inner side of the trench 41 than the first inclined portion 44a.
  • the second trench portion 45 has a second width W2 that is less than the first width W1 and a second depth D2 that is greater than the first depth D1.
  • the first gap amount G1 between the wall surface of the first trench portion 44 and the wall surface of the second trench portion 45 may be 1 nm or more and 50 nm or less (see FIG. 16).
  • the first gap amount G1 is the horizontal distance from a first virtual line L1 that passes through the wall surface of the first trench portion 44 in the normal direction Z to the wall surface of the second trench portion 45 in a cross-sectional view.
  • the horizontal direction is the direction along the first main surface 3 (here, the first direction X).
  • the first gap amount G1 is also a value obtained by dividing the difference between the first width W1 and the second width W2 by half.
  • the first gap amount G1 may have a value that belongs to at least one of the following ranges: 1 nm or more and 5 nm or less, 5 nm or more and 10 nm or less, 10 nm or more and 20 nm or less, 20 nm or more and 30 nm or less, 30 nm or more and 40 nm or less, and 40 nm or more and 50 nm or less. It is preferable that the first gap amount G1 is 5 nm or more. It is preferable that the first gap amount G1 is 25 nm or less.
  • the second depth D2 is the depth between the upper end and the lower end of the second trench portion 45.
  • the second depth D2 may be 0.5 ⁇ m or more and 2 ⁇ m or less.
  • the second depth D2 may have a value that belongs to at least one of the following ranges: 0.5 ⁇ m or more and 0.75 ⁇ m or less, 0.75 ⁇ m or more and 1 ⁇ m or less, 1 ⁇ m or more and 1.25 ⁇ m or less, 1.25 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 1.75 ⁇ m or less, and 1.75 ⁇ m or more and 2 ⁇ m or less.
  • the second depth D2 is preferably 0.5 ⁇ m or more and 1.5 ⁇ m or less.
  • the third trench portion 46 is formed narrower than the second trench portion 45 in the region below the second trench portion 45, and defines the lower end of the trench 41.
  • the third trench portion 46 has an upper end on the second trench portion 45 side and a lower end on the second main surface 4 side.
  • the upper end of the third trench portion 46 is connected to the lower end (second inclined portion 45a) of the second trench portion 45.
  • the lower end of the third trench portion 46 defines the bottom wall of the trench 41.
  • the third trench portion 46 has a third width W3 that is less than the second width W2 and a third depth D3 that is greater than the second depth D2.
  • a second gap amount G2 between the wall surface of the second trench portion 45 and the wall surface of the third trench portion 46 may be 1 nm or more and 50 nm or less (see Figures 13 and 15).
  • the second gap amount G2 is the horizontal distance from the second virtual line L2, which passes through the wall surface of the second trench portion 45 in the normal direction Z, to the wall surface of the third trench portion 46 in a cross-sectional view.
  • the second gap amount G2 is also a value obtained by dividing the difference between the second width W2 and the third width W3 by half.
  • the second gap amount G2 may have a value that belongs to at least one of the following ranges: 1 nm or more and 5 nm or less, 5 nm or more and 10 nm or less, 10 nm or more and 20 nm or less, 20 nm or more and 30 nm or less, 30 nm or more and 40 nm or less, and 40 nm or more and 50 nm or less. It is preferable that the second gap amount G2 is 5 nm or more. It is preferable that the second gap amount G2 is 25 nm or less.
  • the third depth D3 is the depth between the upper and lower ends of the third trench portion 46.
  • the third depth D3 is the gate depth DG of the trench 41 minus the sum of the first depth D1 and the second depth D2. It is preferable that the third depth D3 is equal to or greater than the second depth D2. It is particularly preferable that the third depth D3 is equal to or greater than 1.5 times and equal to or less than 4 times the second depth D2.
  • the third depth D3 may be 0.5 ⁇ m or more and 5 ⁇ m or less.
  • the third depth D3 may have a value that belongs to at least one of the ranges of 0.5 ⁇ m or more and 1.5 ⁇ m or less, 1.5 ⁇ m or more and 2 ⁇ m or less, 2 ⁇ m or more and 2.5 ⁇ m or less, 2.5 ⁇ m or more and 3 ⁇ m or less, 3 ⁇ m or more and 3.5 ⁇ m or less, 3.5 ⁇ m or more and 4 ⁇ m or less, 4 ⁇ m or more and 4.5 ⁇ m or less, and 4.5 ⁇ m or more and 5 ⁇ m or less.
  • the third depth D3 may be 1.5 ⁇ m or more and 3 ⁇ m or less.
  • the insulating film 42 coats the wall surface of the trench 41 in the form of a film. Specifically, the insulating film 42 coats the wall surface of the first trench portion 44, the wall surface of the second trench portion 45, and the wall surface of the third trench portion 46 in the form of a film. More specifically, the insulating film 42 includes a first insulating film 47, a second insulating film 48, and a third insulating film 49.
  • the first insulating film 47 has a relatively small first thickness TF1 and covers the wall surface of the first trench portion 44. Specifically, the first insulating film 47 covers the region between the upper end and the lower end of the wall surface of the first trench portion 44 in the form of a film. The first insulating film 47 has a portion that covers the first inclined portion 44a of the first trench portion 44.
  • the first insulating film 47 may include a silicon oxide film. It is preferable that the first insulating film 47 includes a silicon oxide film made of an oxide of the chip 2.
  • the first film thickness TF1 has a value equal to or less than the first gap amount G1.
  • the first film thickness TF1 may be 1 nm or more and 50 nm or less (see FIG. 16).
  • the first film thickness TF1 may have a value belonging to at least one of the following ranges: 1 nm or more and 5 nm or less, 5 nm or more and 10 nm or less, 10 nm or more and 20 nm or less, 20 nm or more and 30 nm or less, 30 nm or more and 40 nm or less, and 40 nm or more and 50 nm or less.
  • the first film thickness TF1 is 5 nm or more.
  • the first film thickness TF1 is 25 nm or less.
  • the second insulating film 48 has a second thickness TF2 that is equal to or greater than the first thickness TF1, and covers the wall surface of the second trench portion 45 in a film-like manner. Specifically, the second insulating film 48 covers the region between the upper end and the lower end of the wall surface of the second trench portion 45 in a film-like manner.
  • the second insulating film 48 is connected to the first insulating film 47 at the upper end of the second trench portion 45, and has a portion that covers the second inclined portion 45a of the second trench portion 45.
  • the second insulating film 48 may include a silicon oxide film. It is preferable that the second insulating film 48 includes a silicon oxide film made of an oxide of the chip 2. It is preferable that the second film thickness TF2 is greater than the first film thickness TF1. It is particularly preferable that the second film thickness TF2 is greater than the first gap amount G1. Of course, the second film thickness TF2 may be less than the first film thickness TF1 (first gap amount G1).
  • the second film thickness TF2 may be 10 nm or more and 100 nm or less (see FIG. 16).
  • the second film thickness TF2 may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, and 75 nm or more and 100 nm or less. It is preferable that the second film thickness TF2 is 50 nm or less. It is preferable that the second film thickness TF2 is 25 nm or less.
  • the third insulating film 49 has a third film thickness TF3 that is equal to or greater than the second film thickness TF2, and covers the wall surface of the third trench portion 46 in a film-like manner. Specifically, the third insulating film 49 covers the region between the upper end and the lower end of the wall surface of the third trench portion 46 in a film-like manner, and is connected to the second insulating film 48 at the upper end of the third trench portion 46.
  • the third insulating film 49 defines a recess space that is U-shaped in cross section in the third trench portion 46 (the region on the bottom wall side of the trench 41).
  • the third insulating film 49 may include a silicon oxide film.
  • the third insulating film 49 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film (an oxide separate from the chip 2) formed by a CVD method.
  • the third film thickness TF3 is preferably greater than the second film thickness TF2. It is particularly preferable that the third film thickness TF3 is greater than the second gap amount G2.
  • the third film thickness TF3 may be 100 nm or more and 500 nm or less.
  • the third film thickness TF3 may have a value that belongs to at least one of the ranges of 100 nm or more and 200 nm or less, 200 nm or more and 300 nm or less, 300 nm or more and 400 nm or less, and 400 nm or more and 500 nm or less.
  • the third film thickness TF3 is preferably 200 nm or more.
  • the third film thickness TF3 may be approximately equal to the thickness of the insulating film 42 and the isolation insulating film 32.
  • the buried electrode 43 is buried in the trench 41 with an insulating film 42 sandwiched therebetween.
  • the buried electrode 43 may include n-type or p-type conductive polysilicon.
  • the buried electrode 43 has an electrode surface 50 exposed from the trench 41. In this embodiment, the electrode surface 50 is formed by a part of the conductive polysilicon.
  • the electrode surface 50 is located on the bottom wall side of the trench 41 with respect to the first main surface 3, and defines an opening recess 51 with the sidewall of the trench 41 at the opening side of the trench 41.
  • the opening recess 51 extends in a band shape along the trench 41.
  • the opening recess 51 may be formed over almost the entire area of the trench 41.
  • the opening recess 51 has a recess depth DR.
  • the recess depth DR is the maximum distance between the first main surface 3 and the electrode surface 50 based on the height position of the first main surface 3.
  • the recess depth DR may be 100 nm or more and 600 nm or less.
  • the recess depth DR may have a value that belongs to at least one of the following ranges: 100 nm or more and 150 nm or less, 150 nm or more and 200 nm or less, 200 nm or more and 250 nm or less, 250 nm or more and 300 nm or less, 300 nm or more and 350 nm or less, 350 nm or more and 400 nm or less, 400 nm or more and 450 nm or less, 450 nm or more and 500 nm or less, 500 nm or more and 550 nm or more and 600 nm or less.
  • the recess depth DR is preferably 200 nm or more and 400 nm or less.
  • the buried electrode 43 is buried in a region on the second trench portion 45 side with respect to the intermediate portion of the depth range of the first trench portion 44, and at least a portion of the first trench portion 44 is exposed.
  • the buried electrode 43 is buried in the trench 41 with the insulating film 42 (second insulating film 48) sandwiched therebetween so as to expose at least a portion of the first insulating film 47.
  • the buried electrode 43 is buried in the region on the second trench portion 45 side relative to the lower end of the first trench portion 44, exposing almost the entire area of the first trench portion 44.
  • the buried electrode 43 exposes at least a portion (in this embodiment, the entire portion) of the first insulating film 47 that covers the first inclined portion 44a of the first trench portion 44.
  • the buried electrode 43 has recessed edges 52 recessed toward the bottom wall of the trench 41 at the edges of the electrode surface 50 along the side walls of the trench 41.
  • multiple recessed edges 52 are formed on the edges of both sides of the electrode surface 50. Since the recessed edges 52 on both sides have the same form, the configuration of one of the recessed edges 52 will be described below. The description of the other recessed edge 52 will be based on the description of one of the recessed edges 52.
  • the recess edge 52 is defined in the region between the sidewall of the trench 41 (specifically, the wall surface of the first trench portion 44) and the upper end of the buried electrode 43 on the opening side of the trench 41.
  • the recess edge 52 extends along the sidewall of the trench 41 (the wall surface of the first trench portion 44) in a plan view, and is formed in a tapering shape (a windling shape) from the electrode surface 50 toward the bottom wall of the trench 41 in a cross-sectional view.
  • the opening end of the recess edge 52 is formed at a depth position (height position) that faces the wall surface of the first trench portion 44 in the horizontal direction.
  • the bottom wall of the recess edge 52 is formed at a depth position (height position) that faces the wall surface of the second trench portion 45 in the horizontal direction.
  • the opening end of the recess edge 52 faces the first insulating film 47 in the horizontal direction
  • the bottom wall of the recess edge 52 faces the second insulating film 48 in the horizontal direction.
  • the bottom wall of the recess edge 52 is located on the bottom wall side of the trench 41 with respect to the height position of the inner part of the electrode surface 50.
  • the recess edge 52 has a recess width WR in the horizontal direction.
  • the recess width WR may be 10 nm or more and 200 nm or less.
  • the recess width WR may have a value belonging to at least one of the following ranges: 10 nm or more and 25 nm or less, 25 nm or more and 50 nm or less, 50 nm or more and 75 nm or less, 75 nm or more and 100 nm or less, 100 nm or more and 125 nm or less, 125 nm or more and 150 nm or less, 150 nm or more and 175 nm or less, and 175 nm or more and 200 nm or less.
  • the recess width WR is preferably 50 nm or more and 150 nm or less.
  • the buried electrode 43 has a protruding edge 53 that protrudes from the edge of the electrode surface 50 toward the opening side of the trench 41.
  • a plurality of protruding edges 53 are formed on the edges of both sides of the electrode surface 50.
  • the protruding edges 53 are formed at a horizontal distance from the sidewall of the trench 41 (specifically, the wall surface of the first trench portion 44), and define a recess edge 52 between the sidewall of the trench 41 and the protruding edge 53.
  • the protruding edge 53 is formed in a tapered shape toward the opening side of the trench 41, and has a tip portion located on the first main surface 3 side relative to the inner part of the electrode surface 50.
  • the tip portion of the protruding edge 53 is formed on the bottom wall side of the trench 41 relative to the height position of the first main surface 3.
  • the protruding edge 53 forms an electrode surface 50 that is curved in an arc shape toward the bottom wall.
  • the buried electrode 43 has a multi-electrode structure including multiple electrodes spaced apart in the depth direction of the trench 41 with an insulator between them.
  • the uppermost electrode of the buried electrodes 43 (first electrode 54 described below) has the electrode surface 50, recess edge 52, and protruding edge 53 described above.
  • the buried electrode 43 has a double electrode structure including a first electrode 54, a second electrode 55, and an intermediate insulating film 56 arranged separately in the vertical direction.
  • the first electrode 54 may include n-type or p-type conductive polysilicon.
  • the first electrode 54 is embedded in the opening side of the trench 41 with the insulating film 42 in between.
  • the first electrode 54 is embedded in the second trench portion 45 with the second insulating film 48 in between.
  • the first electrode 54 is embedded in a region on the second trench portion 45 side with respect to the middle of the depth range of the first trench portion 44, exposing at least a part of the first trench portion 44.
  • the first electrode 54 is embedded in a region on the second trench portion 45 side relative to the lower end of the first trench portion 44.
  • the first electrode 54 covers the region between the upper and lower ends of the second insulating film 48, exposing almost the entire area of the first trench portion 44.
  • the first electrode 54 exposes a portion of the first insulating film 47 that covers the first inclined portion 44a of the first trench portion 44.
  • the first electrode 54 also has a portion that covers the second inclined portion 45a across the second insulating film 48.
  • the second electrode 55 may contain n-type or p-type conductive polysilicon.
  • the second electrode 55 is embedded in the bottom wall side of the trench 41 with the insulating film 42 in between.
  • the second electrode 55 is embedded in the third trench portion 46 with the third insulating film 49 in between.
  • the second electrode 55 is formed in the shape of a wall extending in the depth direction of the trench 41.
  • the second electrode 55 has an upper end that protrudes above the upper end of the third insulating film 49.
  • the upper end of the second electrode 55 bites into and engages with the lower end of the first electrode 54.
  • the upper end of the second electrode 55 faces the second insulating film 48, sandwiching the lower end of the first electrode 54 in the horizontal direction.
  • the intermediate insulating film 56 is interposed between the first electrode 54 and the second electrode 55, and electrically insulates the first electrode 54 and the second electrode 55 within the trench 41.
  • the intermediate insulating film 56 is continuous with the insulating film 42 (the second insulating film 48 and the third insulating film 49).
  • the intermediate insulating film 56 may include a silicon oxide film. It is preferable that the intermediate insulating film 56 includes a silicon oxide film made of an oxide of the second electrode 55. In other words, it is preferable that the intermediate insulating film 56 includes an oxide of polysilicon.
  • the intermediate insulating film 56 has a fourth thickness TF4.
  • the fourth thickness TF4 is greater than the first thickness TF1 and less than the third thickness TF3.
  • the fourth thickness TF4 is preferably greater than the second thickness TF2.
  • the fourth thickness TF4 may be less than the second thickness TF2.
  • a buried electrode 43 having a double electrode structure is shown.
  • the buried electrode 43 may have three or more electrodes arranged separately in the vertical direction.
  • an intermediate insulating film 56 is arranged in each region between two electrodes adjacent in the vertical direction.
  • the semiconductor device 1 includes a recess insulating film 57 that covers a portion of the electrode surface 50 that defines the recess edge portion 52.
  • the recess insulating film 57 may be considered as one component of the gate structure 40.
  • the recess insulating film 57 may include a silicon oxide film made of an oxide of the buried electrode 43.
  • the recess insulating film 57 may include an oxide of polysilicon.
  • the recess insulating film 57 may include a silicon oxide film formed by a CVD method.
  • the recess insulating film 57 may include an oxide that is separate from the buried electrode 43.
  • the recess insulating film 57 is formed in the shape of a film following the recess edge portion 52 along the wall surface of the recess edge portion 52, and has a film surface located below the first main surface 3 (on the electrode surface 50 side).
  • the recess insulating film 57 is connected to at least the first insulating film 47 of the insulating films 42. In this embodiment, the recess insulating film 57 is also connected to the second insulating film 48.
  • the recess insulating film 57 continuously covers the wall surface of the recess edge portion 52 and the wall surface of the protruding edge portion 53.
  • the recess insulating film 57 has a film thickness that gradually increases from the recess edge portion 52 toward the protruding edge portion 53.
  • the recess insulating film 57 may have a portion that extends from the protruding edge portion 53 toward the inner portion of the electrode surface 50. In this case, it is preferable that the film thickness of the recess insulating film 57 gradually decreases from the protruding edge portion 53 toward the inner portion of the electrode surface 50.
  • the thickness of the portion of the recess insulating film 57 that covers the protruding edge 53 is greater than the thickness of the portion of the recess insulating film 57 that covers the recess edge 52. Also, the thickness of the portion of the recess insulating film 57 that covers the protruding edge 53 is greater than the thickness of the portion of the recess insulating film 57 that covers the region on the inner side of the electrode surface 50.
  • the recess insulating film 57 does not necessarily need to be interrupted at the periphery of the electrode surface 50 in a cross-sectional view, and may cover the entire area of the electrode surface 50 in a cross-sectional view.
  • the recess insulating film 57 defines an insulating recess edge 58 that imitates the recess edge 52 between itself and the wall surface of the trench 41.
  • the recess insulating film 57 is formed at a horizontal distance from the insulating film 42, and defines the insulating recess edge 58 between itself and the insulating film 42.
  • the recess insulating film 57 is formed at a horizontal distance from the first insulating film 47, and defines the insulating recess edge 58 from the first insulating film 47.
  • the film thickness of the portion of the recess insulating film 57 that covers the protruding edge 53 is greater than the film thickness (first film thickness TF1) of the first insulating film 47.
  • insulating recess edge 58 extends along the sidewall of trench 41 (the wall surface of first trench portion 44) in a plan view, and is formed in a tapering shape (a dwindling shape) from electrode surface 50 toward the bottom wall of trench 41 in a cross-sectional view. Insulating recess edge 58 has an opening end located in a region closer to electrode surface 50 than first main surface 3.
  • the opening end of the insulating recess edge 58 is formed at a depth position (height position) that faces the wall surface of the first trench portion 44 in the horizontal direction.
  • the opening end of the insulating recess edge 58 is formed in a region on the electrode surface 50 side relative to the intermediate portion of the depth range of the first trench portion 44.
  • the opening end of the insulating recess edge 58 may also be formed in a region on the first main surface 3 side relative to the intermediate portion of the depth range of the first trench portion 44.
  • the insulating recess edge 58 has a bottom wall formed at the connection between the insulating film 42 (first insulating film 47) and the recess insulating film 57.
  • the bottom wall of the insulating recess edge 58 is formed at a depth position (height position) that faces the lower end of the first trench portion 44 in the horizontal direction. Specifically, the bottom wall of the insulating recess edge 58 faces the first inclined portion 44a of the first trench portion 44.
  • the semiconductor device 1 includes an edge insulator 60 embedded in the recess edge 52.
  • the edge insulator 60 is embedded in the recess edge 52 with a recess insulating film 57 in between. That is, the edge insulator 60 is embedded in the insulating recess edge 58.
  • the edge insulator 60 may be considered as one component of the gate structure 40.
  • the edge insulator 60 may be referred to as a "side spacer,” “sidewall,” “wall structure,” “step reduction portion,” etc.
  • edge insulators 60 are embedded in the recess edges 52 on both sides of the electrode surface 50 so as to expose the inner portion of the electrode surface 50. Since the edge insulators 60 on both sides have a similar shape, the configuration of one edge insulator 60 will be described below. The description of one edge insulator 60 applies to the description of the other edge insulator 60.
  • the edge insulator 60 may include one or more types of insulators.
  • the edge insulator 60 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. It is preferable that the edge insulator 60 includes an insulator different from the insulator that constitutes the insulating film 42 (specifically, the first insulating film 47). It is preferable that the edge insulator 60 includes an insulator different from the insulator that constitutes the recess insulating film 57 (insulating recess edge portion 58).
  • the edge insulator 60 includes an edge insulating film 61 that coats the sidewalls of the trench 41 and the wall surfaces of the recess edge 52 in a film-like manner.
  • the edge insulating film 61 faces the surface layer of the first main surface 3 across the first insulating film 47, and faces the buried electrode 43 (first electrode 54) across the recess insulating film 57 (recess insulating film 57).
  • the edge insulating film 61 includes an insulator different from the insulator that constitutes the insulating film 42 (specifically, the first insulating film 47).
  • the edge insulating film 61 also includes an insulator different from the insulator that constitutes the recess insulating film 57 (insulating recess edge portion 58).
  • the edge insulating film 61 includes either one or both of silicon nitride and silicon oxynitride.
  • the edge insulating film 61 includes a nitride film.
  • the edge insulating film 61 covers the wall surface of the recess edge portion 52 (insulating recess edge portion 58) in a U-shape or J-shape in cross-sectional view.
  • the edge insulating film 61 includes a first extension 61a and a second extension 61b.
  • the first extension 61a covers the sidewall of the trench 41 in a film-like manner.
  • the first extension 61a covers the first insulating film 47 in a film-like manner and faces the sidewall of the trench 41 across the first insulating film 47. It is preferable that the first extension 61a has a film thickness in the horizontal direction that is greater than the film thickness (first film thickness TF1) of the first insulating film 47.
  • the first extension 61a extends from a region outside the recess edge 52 to a region inside the recess edge 52 in the depth direction of the trench 41. That is, the first extension 61a has an upper end on the opening side of the trench 41 and a lower end inside the recess edge 52. The upper end of the first extension 61a is located on the bottom wall side of the recess edge 52 with respect to the first main surface 3, and is not formed in the region outside the trench 41.
  • the upper end of the first extension 61a is terminated within the trench 41, exposing the first main surface 3.
  • the upper end of the first extension 61a may be curved in an arc.
  • the lower end of the first extension 61a is located within the insulating recess edge 58 and faces the buried electrode 43 across the recess insulating film 57.
  • the second extension 61b has a film-forming direction that folds back from the lower end of the first extension 61a toward the first main surface 3, and coats the wall surface of the recess edge 52 in a film-like manner.
  • the second extension 61b has a film-forming direction that is inclined obliquely toward the opening side with respect to the film-forming direction of the first extension 61a.
  • the second extension 61b coats the recess insulating film 57 in a film-like manner, and coats the buried electrode 43 (first electrode 54) with the recess insulating film 57 in between.
  • the second extension portion 61b is formed in a film shape following the recess insulating film 57, and covers the protruding edge portion 53 of the buried electrode 43 with the recess insulating film 57 in between.
  • the second extension portion 61b has a thickness smaller than the thickness of the recess insulating film 57 in the depth direction (normal direction Z) of the trench 41. It is preferable that the second extension portion 61b has a thickness larger than the thickness of the first insulating film 47 (first thickness TF1).
  • the second extension 61b has an upper end on the opening side of the trench 41 and a lower end within the recess edge 52.
  • the upper end of the second extension 61b is located on the electrode surface 50 side relative to the first main surface 3.
  • the upper end of the second extension 61b is located on the protruding edge 53.
  • the upper end of the second extension 61b is located on the electrode surface 50 side (the bottom wall side of the trench 41) relative to the upper end of the first extension 61a, and faces the first extension 61a in the horizontal direction.
  • the upper end of the second extension 61b faces the middle of the depth range of the first extension 61a.
  • the upper end of the second extension 61b is discontinued within the trench 41, and the second extension 61b is not formed in an area outside the trench 41.
  • the second extension 61b also covers the recess edge 52 and the area near the recess edge 52, exposing the inner part of the electrode surface 50.
  • the upper end of the second extension 61b also faces the protruding edge 53 across the recess insulating film 57.
  • the lower end of the second extension 61b is connected to the lower end of the first extension 61a within the insulating recess edge 58. Therefore, the connection between the lower end of the second extension 61b and the lower end of the first extension 61a constitutes the common lower end of the first extension 61a and the second extension 61b.
  • the lower end of the second extension 61b faces the buried electrode 43 across the recess insulating film 57. In this way, the second extension 61b forms a U-shape or J-shape together with the first extension 61a in a cross-sectional view.
  • the edge insulator 60 has a groove portion 62 recessed toward the bottom of the recess edge 52 in the region above the recess edge 52.
  • the groove portion 62 is defined by the edge insulating film 61 in the region above the recess edge 52. More specifically, the groove portion 62 is defined by a first extension portion 61a and a second extension portion 61b of the edge insulating film 61 in the region above the insulating recess edge 58.
  • the groove portion 62 faces the wall surface of the first trench portion 44 across the first extension portion 61a, and faces the open recess 51 (the space inside the trench 41) across the second extension portion 61b.
  • the groove portion 62 has an open end located in a region below the first main surface 3 (region on the electrode surface 50 side) in the height range between the first main surface 3 and the electrode surface 50 of the buried electrode 43, and has a bottom wall located in a region above the electrode surface 50 (region on the first main surface 3 side).
  • the groove portion 62 has a width in the horizontal direction that is less than the width of the recess edge portion 52.
  • the groove portion 62 has a width in the horizontal direction that is less than the width of the insulating recess edge portion 58.
  • the edge insulating film 61 narrows the width of the recess edge portion 52 (insulating recess edge portion 58).
  • the groove portion 62 extends along the side wall of the trench 41 (the wall surface of the first trench portion 44) in a plan view, and is formed in a tapering shape (a dwindling shape) from the electrode surface 50 toward the bottom wall of the trench 41 in a cross-sectional view.
  • the edge insulator 60 includes an insulating filler 63 embedded in the groove 62.
  • the insulating filler 63 is shown by solid hatching. The insulating filler 63 reduces the step (protrusion/subsidence) caused by the groove 62.
  • the insulating filler 63 preferably includes an insulating material different from that of the edge insulator 60.
  • the insulating filler 63 includes an oxide.
  • the insulating filler 63 includes tetraethyl orthosilicate as an example of an oxide. Tetraethyl orthosilicate may also be referred to as "TEOS.”
  • TEOS Tetraethyl orthosilicate
  • the insulating filler 63 may be embedded only in the groove 62, exposing the entire area of the edge insulator 60 outside the groove 62.
  • the insulating filler 63 may be extended from inside the groove 62 to the area outside the groove 62, covering at least a part or all of the area of the edge insulator 60 outside the groove 62.
  • the insulating filler 63 has a main body 63a positioned in the groove 62, a first overlapping portion 63b covering the first extension 61a, and a second overlapping portion 63c covering the second extension 61b.
  • the insulating filler 63 does not need to include both the first overlapping portion 63b and the second overlapping portion 63c at the same time, and may include only one of the first overlapping portion 63b and the second overlapping portion 63c.
  • the first overlap portion 63b may cover a part or the entire area of the first extension portion 61a.
  • the second overlap portion 63c may cover a part or the entire area of the second extension portion 61b.
  • the first overlap portion 63b may be separated from the main body portion 63a.
  • the second overlap portion 63c covers a part of the second extension portion 61b, the second overlap portion 63c may be separated from the main body portion 63a.
  • the semiconductor device 1 includes a plurality of p-type (second conductivity type) body regions 65 formed in the surface layer of the first main surface 3 (drift region 9) in the output region 6.
  • the plurality of body regions 65 are formed in regions along the plurality of gate structures 40 in the surface layer of the first main surface 3 (drift region 9), and face corresponding buried electrodes 43 across corresponding insulating films 42.
  • the body regions 65 are formed shallower than the high concentration drift region 35, and face the drift region 9 across a portion of the high concentration drift region 35.
  • the configuration of one body region 65 for one gate structure 40 will be described below.
  • the body region 65 is located closer to the first main surface 3 than the intermediate portion of the depth range of the isolation structure 30.
  • the body region 65 is located closer to the first main surface 3 than the intermediate portion of the depth range of the gate structure 40.
  • the body region 65 is formed deeper than the lower end of the first trench portion 44, and has a portion that runs along the second trench portion 45.
  • the body region 65 therefore faces the first electrode 54 across the insulating film 42 (second insulating film 48).
  • the body region 65 may be formed deeper than the lower end of the second trench portion 45 and may have a portion that is aligned with the third trench portion 46.
  • the body region 65 may have a portion that faces the upper end of the second electrode 55 across the insulating film 42 (third insulating film 49).
  • the body region 65 includes a main body portion 65a and an extension portion 65b.
  • the main body portion 65a extends in a layered manner along the first main surface 3 so as to contact the sidewall of the trench 41. It is preferable that the main body portion 65a has a bottom portion located in a region on the second trench portion 45 side relative to the lower end of the first trench portion 44. It is preferable that the bottom portion of the main body portion 65a is located in a region between the upper end and the lower end of the second trench portion 45.
  • the main body 65a faces the edge insulator 60 across the first insulating film 47 in the portion along the first trench 44, and faces the buried electrode 43 (first electrode 54) across the second insulating film 48 in the portion along the second trench 45. In other words, the main body 65a faces a part of the edge insulating film 61 (first extension 61a) across the first insulating film 47. The main body 65a also faces the insulating buried object 63 in the horizontal direction.
  • the extension portion 65b is a portion of the main body portion 65a that extends from the portion along the trench 41 toward the bottom wall of the trench 41.
  • the extension portion 65b has a bottom that is located on the bottom wall side of the trench 41 relative to the bottom of the main body portion 65a.
  • the bottom of the extension portion 65b is curved in an arc shape toward the bottom wall side of the trench 41 in a cross-sectional view.
  • the bottom of the extension portion 65b is located at a distance from the lower end of the second trench portion 45 to the upper end side of the second trench portion 45.
  • the bottom of the extension 65b is located above the second inclined portion 45a of the second trench portion 45.
  • the extension 65b may be extended to a region along the upper end of the third trench portion 46 via the lower end (second inclined portion 45a) of the second trench portion 45.
  • the extension 65b (body region 65) may have a portion that faces the second electrode 55 across the third insulating film 49.
  • the multiple channel cells 70 are formed in a region along the inner portion of the gate structure 40 at a distance from both ends of the gate structure 40 in the longitudinal direction (second direction Y).
  • the multiple channel cells 70 expose the body region 65 from a region of the first main surface 3 that is sandwiched between both ends of the multiple gate structures 40.
  • the multiple channel cells 70 face the high-concentration drift region 35 across a portion of the body region 65 in the thickness direction. It is preferable that the multiple channel cells 70 are formed in the inner part of the high-concentration drift region 35 rather than the periphery of the high-concentration drift region 35 in a plan view.
  • the multiple source regions 71 are formed at intervals from the bottom of the corresponding body region 65 toward the first main surface 3, and are arranged at intervals along the corresponding gate structure 40.
  • the multiple source regions 71 face the edge insulator 60 across the insulating film 42 (first insulating film 47), and face the buried electrode 43 (first electrode 54) across the insulating film 42 (second insulating film 48).
  • the multiple source regions 71 form a channel of the output transistor 15 in the region between the drift region 9 (high concentration drift region 35).
  • the channel length LC of the channel is defined by the distance between the source region 71 and the drift region 9 (high concentration drift region 35).
  • the configuration of one source region 71 is described below.
  • the source region 71 includes a source body portion 71a and a source extension portion 71b.
  • the source body portion 71a extends in a layered manner along the first main surface 3 so as to contact the side wall of the trench 41.
  • the source body portion 71a has a bottom portion located in a region on the first main surface 3 side relative to the bottom portion of the body region 65, and faces the drift region 9 (high concentration drift region 35) across a portion of the body region 65.
  • the source body 71a faces the edge insulator 60 across the first insulating film 47 in the portion along the first trench 44. Specifically, the source body 71a faces a part of the edge insulating film 61 (first extension 61a) across the first insulating film 47. In other words, the source body 71a faces the insulating buried object 63 in the horizontal direction.
  • the source body 71a may be formed in a region on the first main surface 3 side relative to the lower end of the first trench 44.
  • the source body 71a may be formed in a region on the second trench 45 side relative to the lower end of the first trench 44.
  • the source body 71a may have a portion that follows the first inclined portion 44a of the first trench 44.
  • the source body 71a is preferably positioned on the upper end side of the second trench 45 relative to the intermediate portion of the depth range of the second trench 45.
  • the source body 71a may face the buried electrode 43 (first electrode 54) across the second trench 45.
  • the source extension 71b is a portion of the source body 71a that extends from the portion along the trench 41 toward the bottom wall of the trench 41.
  • the source extension 71b has a bottom that is located on the bottom wall side of the trench 41 relative to the bottom of the source body 71a.
  • the bottom of the source extension 71b is curved in an arc shape toward the bottom wall side of the trench 41 in a cross-sectional view.
  • the bottom of the source extension 71b is formed in a region on the first main surface 3 side relative to the bottom of the body region 65, and faces the drift region 9 (high concentration drift region 35) across a part of the body region 65.
  • the bottom of the source extension 71b is preferably located toward the upper end of the second trench portion 45 relative to the middle of the depth range of the second trench portion 45.
  • the source extension 71b faces the buried electrode 43 (first electrode 54) across the second trench portion 45.
  • the aforementioned channel length LC is the distance between the source extension 71b and the drift region 9 (high concentration drift region 35).
  • the source extension portion 71b When the source body portion 71a is located in a region on the first main surface 3 side relative to the lower end of the first trench portion 44, the source extension portion 71b is drawn out to a depth position that reaches the second trench portion 45 via the lower end of the first trench portion 44.
  • the source extension portion 71b may have a portion that follows the first inclined portion 44a of the first trench portion 44.
  • the portion of the source extension portion 71b that follows the first trench portion 44 faces the edge insulator 60 with the first insulating film 47 in between.
  • the source extension 71b faces a part of the edge insulating film 61 (first extension 61a) across the first insulating film 47.
  • the source extension 71b may be located in a region on the bottom wall side of the trench 41 with respect to the lower end of the insulating buried object 63.
  • the source extension 71b may be formed in a region below the lower end of the insulating buried object 63 so as not to face the insulating buried object 63 in the horizontal direction.
  • the source extension 71b may face the insulating buried object 63 in the horizontal direction.
  • the source extension 71b When the source body 71a is located in the region on the second trench 45 side relative to the lower end of the first trench 44, the source extension 71b is pulled out from the source body 71a toward the lower end of the second trench 45. In this case, the source extension 71b faces the buried electrode 43 (first electrode 54) in the horizontal direction, but does not face the insulating buried object 63 in the horizontal direction.
  • Each channel cell 70 includes a plurality of p-type contact regions 72.
  • the contact regions 72 may be referred to as "first back gate regions.”
  • Each contact region 72 has a higher p-type impurity concentration than the body region 65.
  • the p-type impurity concentration of each contact region 72 may be 1 ⁇ 10 18 cm ⁇ 3 or more and 1 ⁇ 10 21 cm ⁇ 3 or less.
  • the multiple contact regions 72 are formed at intervals from the bottom of the corresponding body region 65 toward the first main surface 3, and are arranged alternately with the multiple source regions 71 along the corresponding gate structure 40.
  • the multiple contact regions 72 face the edge insulator 60 across the insulating film 42 (first insulating film 47), and face the buried electrode 43 (first electrode 54) across the insulating film 42 (second insulating film 48).
  • the configuration of one contact region 72 is described below.
  • the contact region 72 includes a contact body portion 72a and a contact extension portion 72b.
  • the contact body portion 72a extends in a layered manner along the first main surface 3 so as to contact the sidewall of the trench 41.
  • the contact body portion 72a has a bottom portion formed in a region on the first main surface 3 side relative to the bottom portion of the body region 65, and faces the drift region 9 (high concentration drift region 35) across a portion of the body region 65.
  • the contact body 72a faces the edge insulator 60 across the first insulating film 47 in the portion along the first trench 44. Specifically, the contact body 72a faces a part of the edge insulating film 61 (first extension 61a) across the first insulating film 47. In other words, the contact body 72a faces the insulating buried object 63 in the horizontal direction.
  • the contact body 72a is preferably connected to the source body 71a of the source region 71 in the second direction Y.
  • the contact body 72a may be formed in a region on the first main surface 3 side relative to the lower end of the first trench 44.
  • the contact body 72a may be formed in a region on the second trench 45 side relative to the lower end of the first trench 44.
  • the contact body 72a may have a portion that follows the first inclined portion 44a of the first trench 44.
  • it is preferable that the contact body 72a is positioned on the upper end side of the second trench 45 relative to the intermediate portion of the depth range of the second trench 45.
  • the contact body 72a may face the buried electrode 43 (first electrode 54) across the second trench 45.
  • the contact extension 72b is a portion of the contact body 72a that extends from the portion along the trench 41 toward the bottom wall of the trench 41.
  • the contact extension 72b has a bottom that is located on the bottom wall side of the trench 41 relative to the bottom of the contact body 72a.
  • the bottom of the contact extension 72b is curved in an arc shape toward the bottom wall of the trench 41 in a cross-sectional view.
  • the bottom of the contact extension 72b is formed in a region on the first main surface 3 side of the bottom of the body region 65, and faces the drift region 9 (high-concentration drift region 35) with a part of the body region 65 in between.
  • the bottom of the contact extension 72b is preferably located toward the upper end of the second trench portion 45 relative to the intermediate portion of the depth range of the second trench portion 45.
  • the contact extension 72b faces the buried electrode 43 (first electrode 54) across the second trench portion 45.
  • the contact extension 72b is preferably connected to the source extension 71b of the source region 71 in the second direction Y.
  • the contact extension 72b When the contact body 72a is located in the region on the first main surface 3 side relative to the lower end of the first trench 44, the contact extension 72b is drawn out to a depth position that reaches the second trench 45 via the lower end of the first trench 44.
  • the contact extension 72b may have a portion that follows the first inclined portion 44a of the first trench 44.
  • the contact extension 72b faces the edge insulator 60 in the portion that follows the first trench 44, with the first insulating film 47 in between.
  • the contact extension 72b faces a part of the edge insulating film 61 (first extension 61a) across the first insulating film 47.
  • the contact extension 72b may be located in a region on the bottom wall side of the trench 41 with respect to the lower end of the insulating buried object 63.
  • the contact extension 72b may be formed in a region below the lower end of the insulating buried object 63 so as not to face the insulating buried object 63 in the horizontal direction.
  • the contact extension 72b may face the insulating buried object 63 in the horizontal direction.
  • the contact extension 72b is pulled out from the contact body 72a toward the lower end of the second trench 45.
  • the contact body 72a faces the buried electrode 43 (first electrode 54) in the horizontal direction, but does not face the insulating buried object 63 in the horizontal direction.
  • the multiple source regions 71 in one channel cell 70 face the multiple source regions 71 in the other channel cell 70 across the gate structure 40.
  • the source extension 71b on one side and the source extension 71b on the other side face each other across the gate structure 40.
  • the multiple contact regions 72 in one channel cell 70 face the multiple contact regions 72 in the other channel cell 70 across the gate structure 40.
  • the contact extension 72b on one side and the contact extension 72b on the other side face each other across the gate structure 40.
  • the multiple source regions 71 in one channel cell 70 may face the multiple contact regions 72 in the other channel cell 70 across the gate structure 40.
  • the multiple contact regions 72 in one channel cell 70 may face the multiple source regions 71 in the other channel cell 70 across the gate structure 40.
  • the multiple source regions 71 in one channel cell 70 are connected to the multiple contact regions 72 in the other channel cell 70 in the first direction X.
  • the source body portion 71a on one side is connected to the contact body portion 72a on the other side in the first direction X.
  • the multiple contact regions 72 in one channel cell 70 are connected to the multiple source regions 71 in the other channel cell 70 in the first direction X.
  • the contact body portion 72a on one side is connected to the source body portion 71a on the other side in the first direction X.
  • multiple source regions 71 in one channel cell 70 may be connected to multiple source regions 71 in the other channel cell 70 in the first direction X.
  • multiple contact regions 72 in one channel cell 70 may be connected to multiple contact regions 72 in the other channel cell 70 in the first direction X.
  • the channel cell 70 located on the inner side faces the drift region 9 across a portion of the body region 65 in the thickness direction.
  • the channel cell 70 located on the outer side does not include a source region 71, but only a contact region 72. This suppresses the formation of a current path in the region between the isolation structure 30 and the outermost gate structure 40.
  • the semiconductor device 1 includes a plurality of first silicide layers 75 formed on the surface layer portions of the plurality of source regions 71, respectively.
  • the plurality of first silicide layers 75 are formed by silicidizing the surface layer portions of the plurality of source regions 71 with a metal material.
  • the plurality of first silicide layers 75 may include n-type impurities of the source regions 71.
  • the plurality of first silicide layers 75 may include at least one of a TiSi layer, a TiSi 2 layer, a NiSi layer, a CoSi layer, a CoSi 2 layer, a MoSi 2 layer, and a WSi 2 layer.
  • the first silicide layer 75 includes a first silicide body portion 75a and a first silicide extension portion 75b.
  • the first silicide body portion 75a has a bottom portion located on the first main surface 3 side with respect to the bottom portion of the corresponding source region 71, and extends in a layer or film shape along the first main surface 3.
  • the first silicide body portion 75a faces a part of the body region 65 across a part of the source region 71.
  • the first silicide body portion 75a may be formed over almost the entire surface portion of the source region 71.
  • the first silicide body portion 75a is exposed from the first main surface 3.
  • the first silicide body 75a has a portion exposed from the sidewall of the trench 41.
  • the first silicide body 75a has a portion in contact with the insulating film 42, and faces the edge insulator 60 across the insulating film 42.
  • the first silicide body 75a5 faces the edge insulator 60 across the first insulating film 47 in a portion along the first trench portion 44.
  • the first silicide body 75a faces a part of the edge insulating film 61 (first extension 61a) across the first insulating film 47.
  • the first silicide body 75a faces the insulating embedded object 63 in the horizontal direction.
  • the edge insulator 60 in this embodiment, a laminated structure of the edge insulating film 61 and the insulating embedded object 63) functions as a structure for preventing a short circuit of the first silicide layer 75 with respect to the embedded electrode 43 (gate structure 40).
  • the first silicide extension 75b is a portion of the first silicide body 75a that extends from the portion along the trench 41 toward the bottom wall of the trench 41.
  • the first silicide extension 75b has a bottom that is located on the bottom wall side of the trench 41 relative to the bottom of the first silicide body 75a.
  • the bottom of the first silicide extension 75b is curved in an arc shape toward the bottom wall of the trench 41 in a cross-sectional view.
  • the bottom of the first silicide extension 75b is formed in a region on the first main surface 3 side with respect to the bottom of the source region 71, and faces the body region 65 with a part of the source region 71 in between.
  • the bottom of the first silicide extension 75b is preferably located on the upper end side of the first trench portion 44 with respect to the lower end (first inclined portion 44a) of the first trench portion 44.
  • the first silicide extension 75b faces the edge insulator 60 with the first trench portion 44 in between.
  • the first silicide extension 75b may face the insulating buried object 63 in the horizontal direction with the edge insulating film 61 (first extension 61a) in between.
  • the semiconductor device 1 includes a plurality of second silicide layers 76 formed in the surface layer portions of the plurality of contact regions 72, respectively.
  • the plurality of second silicide layers 76 are formed by silicidizing the surface layer portions of the plurality of contact regions 72 with a metal material.
  • the plurality of second silicide layers 76 may include n-type impurities of the contact regions 72.
  • the plurality of second silicide layers 76 may include at least one of a TiSi layer, a TiSi 2 layer, a NiSi layer, a CoSi layer, a CoSi 2 layer, a MoSi 2 layer, and a WSi 2 layer.
  • the second silicide layers 76 are made of the same material as the first silicide layers 75 and are connected to adjacent first silicide layers 75. In other words, the second silicide layers 76 form one silicide layer together with the first silicide layers 75 in one corresponding channel cell 70.
  • the second silicide layer 76 includes a second silicide body portion 76a and a second silicide extension portion 76b.
  • the second silicide body portion 76a has a bottom portion located on the first main surface 3 side with respect to the bottom portion of the corresponding contact region 72, and extends in a layer or film shape along the first main surface 3.
  • the second silicide body portion 76a faces a part of the body region 65 across a part of the contact region 72.
  • the second silicide body portion 76a may be formed over almost the entire surface portion of the contact region 72.
  • the second silicide body portion 76a is exposed from the first main surface 3.
  • the second silicide body 76a has a portion exposed from the sidewall of the trench 41.
  • the second silicide body 76a has a portion in contact with the insulating film 42, and faces the edge insulator 60 across the insulating film 42.
  • the second silicide body 76a5 faces the edge insulator 60 across the first insulating film 47 in a portion along the first trench portion 44.
  • the second silicide body 76a faces a part of the edge insulating film 61 (first extension 61a) across the first insulating film 47.
  • the second silicide body 76a faces the insulating embedded object 63 in the horizontal direction.
  • the edge insulator 60 in this embodiment, a laminated structure of the edge insulating film 61 and the insulating embedded object 63) functions as a structure for preventing shorting of the second silicide layer 76 to the embedded electrode 43 (gate structure 40).
  • the second silicide extension 76b is a portion of the second silicide body 76a that extends from the portion along the trench 41 toward the bottom wall of the trench 41.
  • the second silicide extension 76b has a bottom that is located on the bottom wall side of the trench 41 relative to the bottom of the second silicide body 76a.
  • the bottom of the second silicide extension 76b is curved in an arc shape toward the bottom wall of the trench 41 in a cross-sectional view.
  • the bottom of the second silicide extension 76b is formed in a region on the first main surface 3 side with respect to the bottom of the contact region 72, and faces the body region 65 with a part of the contact region 72 in between.
  • the bottom of the second silicide extension 76b is preferably located on the upper end side of the first trench portion 44 with respect to the lower end (first inclined portion 44a) of the first trench portion 44.
  • the second silicide extension 76b faces the edge insulator 60 with the first trench portion 44 in between.
  • the second silicide extension 76b may face the insulating filler 63 in the horizontal direction with the edge insulating film 61 (first extension 61a) in between.
  • the output transistor 15 includes a plurality of unit transistors 17.
  • Each of the plurality of unit transistors 17 includes a gate structure 40 and two channel cells 70 formed on both sides of the gate structure 40.
  • the gate structure 40 constitutes a unit gate
  • the source regions 71 two channel cells 70
  • the drain region 8 drift region 9 and high concentration drift region 35
  • the output transistors 15 include a first system of transistors 16A and a second system of transistors 16B.
  • the first system of transistors 16A includes a plurality of unit transistors 17 that are organized (grouped) as individual control targets from a plurality of unit transistors 17.
  • the second system of transistors 16B includes a plurality of unit transistors 17 that are organized (grouped) as individual control targets from a plurality of unit transistors 17 other than the first system of transistors 16A.
  • the output transistor 15 includes a plurality of group regions 77 provided in the output region 6.
  • the plurality of group regions 77 include a plurality of first group regions 77A and a plurality of second group regions 77B.
  • the plurality of first group regions 77A are regions in which one or more (multiple in this embodiment) unit transistors 17 for the first system transistors 16A are respectively arranged.
  • the plurality of second group regions 77B are regions in which one or more (multiple in this embodiment) unit transistors 17 for the second system transistors 16B are arranged.
  • the multiple first group regions 77A are arranged at intervals in the first direction X.
  • the number of unit transistors 17 in each first group region 77A is arbitrary. In this embodiment, two unit transistors 17 are arranged in each first group region 77A. As the number of unit transistors 17 in each first group region 77A increases, the amount of heat generated in each first group region 77A increases. Therefore, it is preferable that the number of unit transistors 17 in each first group region 77A be between two and five.
  • the second group regions 77B are arranged alternately with the first group regions 77A along the first direction X so as to sandwich one first group region 77A. This allows the heat generating locations caused by the first group regions 77A to be thinned out by the second group regions 77B, while at the same time allowing the heat generating locations caused by the second group regions 77B to be thinned out by the first group regions 77A.
  • the number of unit transistors 17 in each second group region 77B is arbitrary. In this embodiment, two unit transistors 17 are arranged in each second group region 77B. As the number of unit transistors 17 in each second group region 77B increases, the amount of heat generated in each second group region 77B increases.
  • the number of unit transistors 17 in each second group region 77B be between 2 and 5. In consideration of the in-plane temperature variation in the output region 6, it is preferable that the number of unit transistors 17 in the second group region 77B be the same as the number of unit transistors 17 in the first group region 77A.
  • the semiconductor device 1 includes a pair (multiple pairs in this embodiment) of trench electrode type connection structures 80 that connect both ends of multiple (two in this embodiment) gate structures 40 to be organized (grouped) in each group region 77. That is, the pair of connection structures 80 respectively connect both ends of multiple gate structures 40 to be organized as system transistors 16.
  • the connection structure 80 may be referred to as a "trench connection structure.”
  • connection structure 80 on one side connects the first ends of the corresponding multiple gate structures 40 (two in this embodiment) in a planar view in an arch shape.
  • the connection structure 80 on the other side connects the second ends of the corresponding multiple gate structures 40 (two in this embodiment) in a planar view in an arch shape.
  • connection structure 80 on one side has a first portion extending in a first direction X and multiple (two in this embodiment) second portions extending in a second direction Y.
  • the first portion faces the first ends of the multiple gate structures 40 in a plan view.
  • the multiple second portions extend from the first portion toward the multiple first ends so as to be connected to the multiple first ends.
  • connection structure 80 on the other side has a first portion extending in the first direction X and multiple (two in this embodiment) second portions extending in the second direction Y.
  • the first portion faces the second ends of the multiple gate structures 40 in a plan view.
  • the multiple second portions extend from the first portion toward the multiple second ends so as to be connected to the multiple second ends.
  • the multiple connection structures 80 form a ring-shaped or ladder-shaped trench structure with the multiple gate structures 40 in each group region 77.
  • the multiple connection structures 80 are formed in the region between the isolation structure 30 and the high concentration drift region 35 at intervals from the isolation structure 30 and the high concentration drift region 35.
  • the multiple connection structures 80 are formed at intervals from the bottom of the drift region 9 toward the first main surface 3, and face the drain region 8 with a portion of the drift region 9 in between.
  • connection structures 80 may be formed with approximately the same width and depth as the gate structures 40.
  • first and second portions of the connection structures 80 may have different widths.
  • the second portion of the connection structure 80 may be formed narrower than the first portion of the connection structure 80.
  • the first portion may have a width approximately equal to the width of the isolation structure 30, and the second portion may have a width approximately equal to the width of the gate structure 40. Furthermore, in this case, the first portion may have a depth approximately equal to the depth of the isolation structure 30, and the second portion may have a depth approximately equal to the depth of the gate structure 40.
  • the other side connection structure 80 has a structure similar to that of the one side connection structure 80, except that it is connected to the second end of the gate structure 40. Below, the configuration of the one side connection structure 80 is explained, and an explanation of the configuration of the other side connection structure 80 is omitted.
  • connection structure 80 includes a connection trench 81, a connection insulating film 82, and a connection electrode 83.
  • the connection trench 81 is formed on the first main surface 3 and defines the wall surface of the connection structure 80.
  • the connection trench 81 is connected to a plurality of trenches 41.
  • connection insulating film 82 covers the wall surface of the connection trench 81.
  • the connection insulating film 82 is connected to the insulating film 42 at the communicating portion between the connection trench 81 and the trench 41. Specifically, the connection insulating film 82 is connected to the first insulating film 47, the second insulating film 48, the third insulating film 49, and the intermediate insulating film 56.
  • connection insulating film 82 is thicker than the first insulating film 47.
  • the connection insulating film 82 is thicker than the second insulating film 48.
  • the thickness of the connection insulating film 82 may be approximately equal to the thickness of the third insulating film 49.
  • the connection insulating film 82 may include a silicon oxide film.
  • the connection insulating film 82 may include a silicon oxide film made of an oxide of the chip 2, or may include a silicon oxide film (an oxide separate from the chip 2) formed by a CVD method.
  • connection electrode 83 is embedded in the connection trench 81 with the connection insulating film 82 in between, and faces the drift region 9 with the connection insulating film 82 in between.
  • the connection electrode 83 is connected to the second electrode 55 at the communicating portion between the connection trench 81 and the trench 41, and is electrically insulated from the first electrode 54 by the intermediate insulating film 56.
  • the connection electrode 83 is composed of an extension portion where the second electrode 55 is extended from inside the trench 41 into the connection trench 81.
  • the connection electrode 83 may include n-type or p-type conductive polysilicon.
  • the semiconductor device 1 includes a field insulating film 85 that selectively covers the first main surface 3 inside and outside the output region 6.
  • the field insulating film 85 covers the first main surface 3 along the outer wall of the isolation structure 30 outside the output region 6 and is connected to the isolation insulating film 32.
  • the field insulating film 85 covers the first main surface 3 along the inner wall of the isolation structure 30 inside the output region 6 and is connected to the isolation insulating film 32 and the connection insulating film 82.
  • the field insulating film 85 is formed at a distance from the multiple gate structures 40 towards the isolation structure 30, and has a field opening 86 that exposes the multiple gate structures 40.
  • the field opening 86 is formed at a distance from the isolation structure 30 towards the inside of the output region 6 in a plan view, and has an opening wall surface that extends along the isolation structure 30. The field opening 86 exposes the multiple buried electrodes 43.
  • the field insulating film 85 is preferably thicker than the first insulating film 47. It is particularly preferable that the field insulating film 85 is thicker than the second insulating film 48. The thickness of the field insulating film 85 may be greater than or equal to the thickness of the third insulating film 49, or may be less than the thickness of the third insulating film 49.
  • the field insulating film 85 may include a silicon oxide film made of an oxide of the chip 2.
  • the field insulating film 85 may include a silicon oxide film formed by a CVD method. In other words, the field insulating film 85 may include an oxide separate from the chip 2.
  • the semiconductor device 1 further includes a contact insulating film 87 that covers the output region 6.
  • the contact insulating film 87 may include one or more types of insulators.
  • the contact insulating film 87 may include at least one insulator selected from the group consisting of silicon oxide, silicon nitride, and silicon oxynitride. It is preferable that the contact insulating film 87 includes an insulator different from the insulator that constitutes the insulating film 42.
  • the contact insulating film 87 preferably includes an insulator different from the insulator that constitutes the recess insulating film 57 (insulating recess edge portion 58).
  • the contact insulating film 87 preferably includes an insulator different from the insulator that constitutes the insulating filling 63.
  • the contact insulating film 87 includes either or both of silicon nitride and silicon oxynitride.
  • the edge insulating film 61 includes a nitride film.
  • the contact insulating film 87 has a portion that covers the field insulating film 85 in the output region 6, a portion that covers the first main surface 3, and a portion that covers the multiple gate structures 40. Specifically, the contact insulating film 87 extends from above the field insulating film 85 into the field opening 86, and covers the first main surface 3 and the multiple gate structures 40 within the field opening 86.
  • the contact insulating film 87 preferably directly covers the multiple first silicide layers 75 and the multiple second silicide layers 76 on the first main surface 3.
  • the contact insulating film 87 may indirectly cover the multiple first silicide layers 75 and the multiple second silicide layers 76.
  • the contact insulating film 87 may cover the multiple first silicide layers 75 and the multiple second silicide layers 76 with an oxide film sandwiched therebetween.
  • the contact insulating film 87 penetrates from above the first main surface 3 through the edge insulator 60 into the opening recess 51 (trench 41), and covers multiple buried electrodes 43 within the opening recess 51.
  • the contact insulating film 87 coats the electrode surface 50 and the edge insulator 60 in the opening recess 51 in the form of a film.
  • the portion of the contact insulating film 87 arranged in the opening recess 51 has a film surface formed on the electrode surface 50 side rather than the first main surface 3. In other words, the portion of the contact insulating film 87 arranged in the opening recess 51 does not protrude above the first main surface 3.
  • the contact insulating film 87 covers the first extension 61a and the second extension 61b of the edge insulating film 61, and has a portion that is in direct contact with the insulating filler 63 exposed from the region between the first extension 61a and the second extension 61b.
  • the contact insulating film 87 has a portion that is extended from above the edge insulating film 61 onto the recess insulating film 57.
  • the contact insulating film 87 has a portion that faces the buried electrode 43 across the recess insulating film 57.
  • the contact insulating film 87 may partially face the protruding edge portion 53 across the recess insulating film 57.
  • the contact insulating film 87 may have a portion that contacts the first insulating film 47 at the opening end of the trench 41.
  • the contact insulating film 87 preferably has a thickness greater than the first film thickness TF1. It is particularly preferable that the thickness of the contact insulating film 87 is greater than the second film thickness TF2. It is particularly preferable that the thickness of the contact insulating film 87 is smaller than the third film thickness TF3. It is particularly preferable that the thickness of the contact insulating film 87 is smaller than the thickness of the field insulating film 85.
  • the aforementioned interlayer film 10 covers the first main surface 3 inside and outside the output region 6.
  • the interlayer film 10 includes a bottom interlayer film 10a that covers the field insulating film 85 and the contact insulating film 87.
  • the bottom interlayer film 10a preferably includes an insulator having properties different from those of the edge insulator 60 (edge insulating film 61).
  • the bottom interlayer film 10a includes an oxide film (specifically, a silicon oxide film).
  • the bottom interlayer film 10a covers the isolation structure 30, the multiple gate structures 40, the multiple connection structures 80, and the field insulating film 85. Specifically, the bottom interlayer film 10a extends from the region above the first main surface 3 through the edge insulator 60 into the multiple trenches 41 (opening recesses 51) and includes anchor portions embedded in the multiple trenches 41 (opening recesses 51).
  • the anchor portion is sandwiched between edge insulators 60 on both sides within trench 41 (opening recess 51).
  • the anchor portion covers edge insulator 60 with contact insulating film 87 in between, and covers buried electrode 43 (electrode surface 50) with contact insulating film 87 in between.
  • the anchor portion covers first extension 61a and second extension 61b of edge insulating film 61 with contact insulating film 87 in between, and covers insulating buried object 63 with contact insulating film 87 in between.
  • the semiconductor device 1 includes a plurality of gate wirings 91 arranged in the interlayer film 10.
  • the plurality of gate wirings 91 are routed to the output region 6 and the control region 7, and are electrically connected to the output transistors 15 in the output region 6, and are electrically connected to the control circuit 18 (gate control circuit 19) in the control region 7.
  • the plurality of gate wirings 91 individually transmit a plurality of gate signals generated by the control circuit 18 (gate control circuit 19) to the output transistors 15.
  • the multiple gate wirings 91 include a first gate wiring 91A and a second gate wiring 91B.
  • the first gate wiring 91A individually transmits gate signals to the first system transistors 16A.
  • the first gate wiring 91A is electrically connected to multiple gate structures 40 for the first system transistors 16A via multiple gate contact electrodes 92 arranged in the interlayer film 10 (lowest interlayer film 10a).
  • the first gate wiring 91A is electrically connected to the corresponding multiple first electrodes 54 and multiple connection electrodes 83 via the multiple gate contact electrodes 92.
  • the first electrode 54 and the second electrode 55 for the first system transistor 16A are simultaneously controlled to be turned on and off by the same gate signal. This suppresses the voltage drop between the first electrode 54 and the second electrode 55, and suppresses undesirable electric field concentration. As a result, the decrease in breakdown voltage caused by the electric field concentration is suppressed.
  • the second gate wiring 91B transmits gate signals individually to the second system transistors 16B, electrically independent of the first gate wiring 91A.
  • the second gate wiring 91B is electrically connected to the multiple gate structures 40 for the second system transistors 16B via multiple gate contact electrodes 92 arranged in the interlayer film 10 (lowest interlayer film 10a).
  • the second gate wiring 91B is electrically connected to the corresponding multiple first electrodes 54 and multiple connection electrodes 83 via the multiple gate contact electrodes 92.
  • the first electrode 54 and the second electrode 55 for the second system transistor 16B are simultaneously controlled to be turned on and off by the same gate signal. This suppresses the voltage drop between the first electrode 54 and the second electrode 55, and suppresses undesirable electric field concentration. As a result, the decrease in breakdown voltage caused by the electric field concentration is suppressed.
  • the gate contact electrode 92 for the gate structure 40 has a width less than the gate width WG of each gate structure 40 in a cross-sectional view, and is mechanically and electrically connected to the inner part of the electrode surface 50 with a space therebetween from the edge insulators 60 on both sides.
  • the gate contact electrode 92 may have a width equal to or greater than 1/5 of the gate width WG. It is preferable that the gate contact electrode 92 have a width equal to or greater than 1/4 of the gate width WG. It is particularly preferable that the gate contact electrode 92 have a width equal to or greater than 1/3 of the trench pitch TP. The gate contact electrode 92 may have a width equal to or greater than 1/2 of the trench pitch TP.
  • the aforementioned edge insulator 60 functions as a structure for preventing short circuits of the gate contact electrode 92 with respect to the channel cell 70. Therefore, even if misalignment occurs in the gate contact electrode 92 in the direction approaching the channel cell 70, a short circuit of the gate contact electrode 92 with respect to the channel cell 70 is suppressed in the area where the gate contact electrode 92 contacts the edge insulator 60.
  • the multiple gate contact electrodes 92 are disposed in multiple contact openings 93 formed in the interlayer film 10 (lowest interlayer film 10a).
  • Each gate contact electrode 92 includes a first electrode film 94 and a second electrode film 95 laminated in this order from the wall side of the contact opening 93.
  • the first electrode film 94 is formed as a barrier electrode film, and covers the wall surface of the contact opening 93 in a film-like manner.
  • the first electrode film 94 is in contact with the interlayer film 10 (lowest interlayer film 10a) and the contact insulating film 87 within the contact opening 93.
  • the first electrode film 94 may have a thickness less than the thickness of the contact insulating film 87.
  • the first electrode film 94 may include a Ti-based metal film.
  • the first electrode film 94 may include either or both of a Ti film and a TiN film. When the first electrode film 94 has a layered structure, the order in which the Ti film and the TiN film are layered is arbitrary.
  • the second electrode film 95 is formed as an electrode body and is embedded in the contact opening 93 via the first electrode film 94.
  • the second electrode film 95 preferably includes at least one of a Cu film, a W film, and an Al film.
  • the second electrode film 95 has a thickness greater than the thickness of the first electrode film 94.
  • the volume of the second electrode film 95 in the contact opening 93 is greater than the volume of the first electrode film 94 in the contact opening 93.
  • the semiconductor device 1 includes a source wiring 96 disposed in the interlayer film 10.
  • the source wiring 96 is electrically connected to the source terminal 11, the isolation structure 30, and the plurality of channel cells 70.
  • the source wiring 96 is electrically connected to the isolation structure 30 and the plurality of channel cells 70 via a plurality of source contact electrodes 97 disposed in the interlayer film 10 (lowest interlayer film 10a).
  • the source contact electrode 97 for the channel cell 70 has a width less than the trench pitch TP and is arranged so as to straddle two adjacent channel cells 70 with a gap between them from the multiple gate structures 40.
  • the source contact electrode 97 is formed in a strip shape extending along the corresponding channel cell 70 in a planar view.
  • the source terminal 11 is electrically connected to the system sources of all the system transistors 16 (the unit sources of the unit transistors 17).
  • the source contact electrode 97 may have a width of 1/5 or more of the trench pitch TP. It is preferable that the source contact electrode 97 has a width of 1/4 or more of the trench pitch TP. It is particularly preferable that the source contact electrode 97 has a width of 1/3 or more of the trench pitch TP. The source contact electrode 97 may have a width of 1/2 or more of the trench pitch TP.
  • the aforementioned edge insulator 60 functions as a structure for preventing a short circuit of the source contact electrode 97 with respect to the gate structure 40. Therefore, even if the source contact electrode 97 is misaligned in a direction approaching the gate structure 40, a short circuit of the source contact electrode 97 with respect to the gate structure 40 is suppressed in the area where the source contact electrode 97 contacts the edge insulator 60.
  • each source contact electrode 97 is disposed in multiple contact openings 93 formed in the interlayer film 10 (lowest interlayer film 10a). Like the gate contact electrode 92, each source contact electrode 97 includes a first electrode film 94 and a second electrode film 95 laminated in this order from the wall side of the contact opening 93.
  • the semiconductor device 1 includes the chip 2, the trench 41, the buried electrode 43, and the edge insulator 60.
  • the chip 2 has a first main surface 3.
  • the trench 41 is formed on the first main surface 3 and has a sidewall and a bottom wall.
  • the buried electrode 43 is buried in the trench 41.
  • the buried electrode 43 has an electrode surface 50 located closer to the bottom wall of the trench 41 than the first main surface 3.
  • the buried electrode 43 has a recess edge 52 recessed toward the bottom wall at an edge of the electrode surface 50 along the sidewall of the trench 41.
  • the edge insulator 60 is buried in the recess edge 52.
  • This configuration makes it possible to provide a semiconductor device 1 having a novel layout for the trench structure.
  • this configuration makes it possible to suppress the deterioration of reliability caused by the recess edge 52 by the edge insulator 60.
  • factors that may cause a deterioration in reliability when the edge insulator 60 is not present include undesirable residues (particularly conductive residues) adhering to the recess edge 52, undesirable shape defects caused by the recess edge 52, reduced film formation caused by the recess edge 52, and fluctuations in electrical characteristics caused by the recess edge 52.
  • the edge insulator 60 preferably includes an edge insulating film 61 formed in a film shape along the sidewall of the trench 41 and the wall surface of the recess edge 52. With this configuration, the edge insulator 60 can be formed with the deposition precision of the edge insulating film 61, so that it is possible to prevent a portion of the edge insulator 60 from remaining in the area outside the recess edge 52. Such a configuration is particularly effective in forming the edge insulator 60 for the minute recess edge 52.
  • the buried electrode 43 may contain silicon (polysilicon).
  • the edge insulating film 61 preferably contains a nitride (nitride film).
  • the edge insulating film 61 may define a groove 62 recessed toward the bottom of the recess edge 52 in the region above the recess edge 52.
  • the edge insulator 60 preferably includes an insulating filler 63 (filler) embedded in the groove 62. With this configuration, unevenness formed in the edge insulator 60 can be mitigated by the insulating filler 63. This can improve the reliability of the edge insulator 60.
  • the insulating filler 63 preferably contains an insulating material different from that of the edge insulating film 61. This configuration makes it possible to prevent the edge insulating film 61 and the insulating filler 63 from being removed simultaneously during the manufacturing process. Therefore, the shape of the edge insulator 60 can be appropriately controlled.
  • the insulating filler 63 preferably contains an oxide. It is particularly preferable that the insulating filler 63 contains tetraethyl orthosilicate, which is one example of an oxide.
  • the buried electrode 43 may include a protruding edge 53 that protrudes toward the opening side of the trench 41 at the edge of the electrode surface 50.
  • the protruding edge 53 defines a recess edge 52 between itself and the side wall of the trench 41.
  • the trench 41 may have an opening end formed wider than the other portions.
  • the trench 41 includes a relatively wide first trench portion 44 and a second trench portion 45 narrower than the first trench portion 44, which are formed in this order from the first main surface 3 side.
  • the recess edge portion 52 is defined along the portion of the sidewall of the trench 41 that forms the opening end (i.e., the first trench portion 44).
  • the semiconductor device 1 preferably further includes an insulating film 42 that covers the sidewall of the trench 41.
  • the buried electrode 43 may be in contact with the insulating film 42 within the trench 41.
  • the edge insulator 60 may be in contact with the insulating film 42 within the recess edge 52.
  • the semiconductor device 1 may include a contact insulating film 87 that covers the electrode surface 50 and the edge insulator 60 in the trench 41 in a film-like manner. With this configuration, the electrode surface 50 and the edge insulator 60 can be protected by the contact insulating film 87. This suppresses morphological abnormalities of the electrode surface 50 and the edge insulator 60.
  • the semiconductor device 1 preferably includes a source region 71 formed in a region along the sidewall of the trench 41 in the surface layer of the first main surface 3 so as to face the buried electrode 43 and the edge insulator 60 in the horizontal direction along the first main surface 3.
  • the depth position of the source region 71 relative to the buried electrode 43 can be determined based on the depth position of the edge insulator 60.
  • the semiconductor device 1 preferably includes a source contact electrode 97 connected to the first main surface 3 on the side of the trench 41.
  • the edge insulator 60 functions as a structure to prevent shorting of the source contact electrode 97 to the buried electrode 43.
  • the semiconductor device 1 may include a source contact electrode 97 that is mechanically connected to the edge insulator 60.
  • the semiconductor device 1 preferably includes a gate contact electrode 92 that is connected to the electrode surface 50 of the buried electrode 43 and applies a potential to the buried electrode 43.
  • the edge insulator 60 functions as a short-circuit prevention structure for the gate contact electrode 92 with respect to the first main surface 3 (the area outside the trench 41).
  • the semiconductor device 1 may include a gate contact electrode 92 that is mechanically connected to the edge insulator 60.
  • the semiconductor device 1 preferably includes a first silicide layer 75 (second silicide layer 76) that faces the edge insulator 60 in the surface layer of the first main surface 3 in the horizontal direction along the first main surface 3.
  • the edge insulator 60 functions as a structure that prevents the first silicide layer 75 (second silicide layer 76) from shorting to the buried electrode 43. Therefore, shorting of the first silicide layer 75 (second silicide layer 76) to the buried electrode 43 is suppressed.
  • FIG. 17 is a schematic diagram showing a wafer W used in the manufacture of a semiconductor device 1.
  • the wafer W is formed in a flat disk shape.
  • the wafer W may also be formed in a flat rectangular parallelepiped shape.
  • the wafer W is made of single crystal silicon.
  • the wafer W has a first wafer main surface 103 on one side, a second wafer main surface 104 on the other side, and a wafer side surface 105 connecting the first wafer main surface 103 and the second wafer main surface 104.
  • the first wafer main surface 103 and the second wafer main surface 104 correspond to the first wafer main surface 3 and the second wafer main surface 4 of the chip 2, respectively.
  • the wafer W has a mark 106 on the wafer side surface 105 that indicates the crystal orientation of the Si single crystal.
  • the mark 106 may include either or both of an orientation flat and an orientation notch.
  • the orientation flat consists of a cutout that is cut in a straight line in a plan view.
  • the orientation notch consists of a cutout that is cut in a concave shape toward the center of the wafer W in a plan view.
  • the mark 106 may include a single or multiple orientation flats.
  • the orientation flats may extend in a first direction X or a second direction Y in a plan view. In FIG. 17, the orientation flat extends in the second direction Y in a plan view.
  • the mark 106 may include a first orientation flat extending in the first direction X and a second orientation flat extending in the second direction Y.
  • the mark 106 may include a single or multiple orientation notches.
  • the orientation notch may be formed in a tapered shape (tapered or triangular) toward the center of the wafer W in a plan view.
  • the orientation notch may be recessed in the first direction X or the second direction Y in a plan view.
  • the mark 106 may include a first orientation notch recessed in the first direction X and a second orientation notch recessed in the second direction Y.
  • a wafer W without the mark 106 may be used.
  • the wafer W includes an n-type drain region 8 formed in the surface layer of the second wafer main surface 104.
  • the drain region 8 is formed in a layer extending along the second wafer main surface 104 over the entire surface layer of the second wafer main surface 104, and is exposed from the second wafer main surface 104 and the wafer side surface 105.
  • the drain region 8 is formed from an n-type semiconductor substrate (Si substrate).
  • the wafer W includes an n-type drift region 9 formed in the surface layer of the first wafer main surface 103.
  • the drift region 9 is formed in a layer extending along the first wafer main surface 103 over the entire surface layer of the first wafer main surface 103, and is exposed from the first wafer main surface 103 and the wafer side surface 105.
  • the drift region 9 is electrically connected to the drain region 8 within the wafer W.
  • the drift region 9 is formed by an n-type epitaxial layer (Si epitaxial layer).
  • the wafer W includes a plurality of device regions 107 and a plurality of planned cutting lines 108 set on the first wafer main surface 103.
  • the plurality of device regions 107 and the plurality of planned cutting lines 108 are defined (set), for example, by alignment marks formed on the first wafer main surface 103.
  • Each device region 107 is an area corresponding to a semiconductor device 1.
  • the multiple device regions 107 are each set to have a rectangular shape in a planar view.
  • the multiple device regions 107 are arranged in a matrix along the first direction X and the second direction Y in a planar view.
  • the multiple device regions 107 are each arranged at intervals inward from the periphery of the first wafer main surface 103 in a planar view.
  • the multiple cutting lines 108 are set in a lattice shape extending along the first direction X and the second direction Y to partition the multiple device regions 107.
  • the multiple device regions 107 include multiple first device regions 107A and multiple second device regions 107B.
  • the first device region 107A is a device region 107 located in the inner portion of the first wafer main surface 103.
  • the second device region 107B is a device region 107 located in the peripheral portion of the first wafer main surface 103.
  • the inner part of the wafer W is defined by the part located inside the imaginary circle VC, which has a radius of 25% of the diameter of the wafer W, when the imaginary circle VC is drawn based on the center of the wafer W.
  • the diameter of the wafer W is defined by the length of the chord passing through the center of the wafer W outside the mark 106.
  • the peripheral part of the wafer W is defined by the part located outside the imaginary circle VC.
  • the device region 107 located on the imaginary circle VC is included in the first device region 107A.
  • the semiconductor device 1 formed in the first device region 107A may be referred to as the first semiconductor device, and the semiconductor device 1 formed in the second device region 107B may be referred to as the second semiconductor device.
  • a wafer W having a predetermined structure in the middle of the manufacturing process may be referred to as a "wafer structure", a "wafer intermediate”, etc.
  • FIGS. 18A to 18X are cross-sectional views for explaining the manufacturing method of the semiconductor device 1.
  • FIG. 19 is a cross-sectional view comparing the gate structure 40 on the first device region 107A side and the gate structure 40 on the second device region 107B side in a wafer W (wafer structure).
  • FIGS. 18A to 18X show the region in which one isolation structure 30 and one gate structure 40 are formed in one device region 107.
  • the aforementioned wafer W is prepared.
  • a first mask M1 having a predetermined pattern is formed on the first wafer main surface 103.
  • the first mask M1 may be made of a hard mask including an inorganic insulating film.
  • the first mask M1 has a layout that exposes the areas where the isolation trench 31, trench 41, and connection trench 81 are to be formed, and covers the other areas.
  • etching may be a wet etching method and/or a dry etching method. This results in the isolation trenches 31, the trenches 41 and the connection trenches 81 being formed in the first wafer main surface 103.
  • the first mask M1 is then removed.
  • a second mask M2 having a predetermined pattern is formed on the first wafer main surface 103.
  • the second mask M2 may be a resist mask (ion implantation mask) including an organic insulating film.
  • the second mask M2 has a layout that exposes the region where the high-concentration drift region 35 is to be formed and covers the other regions. Specifically, the second mask M2 exposes the region where the multiple trenches 41 are formed and covers the other regions.
  • n-type impurities are introduced into the surface layer of the first wafer main surface 103 by ion implantation through the second mask M2.
  • n-type impurities are introduced into the surface layer of the first wafer main surface 103 from the first wafer main surface 103 and the wall surface of the trench 41 by oblique ion implantation.
  • the relative implantation angle of the n-type impurity with respect to the first wafer main surface 103 is adjusted, and the n-type impurity is introduced obliquely into the surface layer of the first wafer main surface 103. That is, the wafer W may be supported in a horizontal position, or in a position obliquely inclined with respect to the horizontal direction. In either case, the implantation angle of the n-type impurity with respect to the wafer W is adjusted.
  • the implantation angle (absolute value) of the n-type impurity with respect to the first wafer main surface 103 may be greater than 0° and less than or equal to 15°.
  • the implantation angle may have a value belonging to at least one of the following ranges: greater than 0° and equal to or less than 3°, greater than or equal to 3° and equal to or less than 6°, greater than or equal to 6° and equal to or less than 9°, greater than or equal to 9° and equal to or less than 12°, and greater than or equal to 12° and equal to or less than 15°.
  • the implantation angle (absolute value) is preferably greater than or equal to 2° and equal to or less than 12°.
  • the second mask M2 is removed after the introduction of the n-type impurity. After that, a diffusion process of the n-type impurity is performed by a heat treatment method, and the high-concentration drift region 35 is formed.
  • the first base insulating film 110 serves as a base for the isolation insulating film 32, the third insulating film 49 of the insulating film 42, the connection insulating film 82, and the field insulating film 85.
  • the first base insulating film 110 coats the first wafer main surface 103, the wall surfaces of the isolation trench 31, the wall surfaces of the trench 41, and the wall surfaces of the connection trench 81 in the form of a film.
  • the first base insulating film 110 may be formed by a CVD method (Chemical Vapor Deposition method) and/or an oxidation treatment method.
  • the oxidation treatment method may be a wet oxidation treatment method and/or a thermal oxidation treatment method.
  • a first base electrode 111 is formed on the first wafer main surface 103.
  • the first base electrode 111 serves as a base for the separation electrode 33, the second electrode 55 of the buried electrode 43, and the connection electrode 83.
  • the first base electrode 111 covers the first wafer main surface 103 with the first base insulating film 110 in between, and is embedded in the separation trench 31, the trench 41, and the connection trench 81 with the first base insulating film 110 in between.
  • the first base electrode 111 includes conductive polysilicon and is formed by a CVD method.
  • unnecessary portions of the first base electrode 111 are removed by etching.
  • the etching may be wet etching and/or dry etching.
  • the first base electrode 111 is removed until the portion of the first base insulating film 110 that covers the first wafer main surface 103 is exposed. This forms the separation electrode 33 and the connection electrode 83.
  • a third mask M3 having a predetermined pattern is formed on the first base insulating film 110.
  • the third mask M3 may be a resist mask including an organic insulating film.
  • the third mask M3 has a layout that exposes the portion of the first base electrode 111 embedded in the trench 41 and covers the portion of the first base electrode 111 embedded in the isolation trench 31 (i.e., isolation electrode 33) and the portion embedded in the connection trench 81 (i.e., connection electrode 83).
  • the etching may be wet etching and/or dry etching. As a result, the portion of the first base electrode 111 buried in the trench 41 is further dug down, and the second electrode 55 of the buried electrode 43 is formed.
  • unnecessary portions of the first base insulating film 110 are removed by etching through the third mask M3.
  • the etching may be wet etching and/or dry etching.
  • the first base insulating film 110 is removed until the etching surface is located closer to the bottom wall of the trench 41 than the upper end of the second electrode 55 of the buried electrode 43. This forms the isolation insulating film 32, the third insulating film 49 of the insulating film 42, the connection insulating film 82, and the field insulating film 85.
  • the third mask M3 is then removed.
  • a second base insulating film 112 which is thinner than the first base insulating film 110, is formed on the first wafer main surface 103.
  • the second base insulating film 112 serves as a base for the second insulating film 48 and the intermediate insulating film 56 of the insulating film 42.
  • the second base insulating film 112 may be formed by a CVD method and/or an oxidation process method.
  • the oxidation process method may be a wet oxidation process method and/or a thermal oxidation process method.
  • the second base insulating film 112 is formed by an oxidation process (specifically, a thermal oxidation process).
  • the second base insulating film 112 covers, in a film form, the portion of the wall surface of the trench 41 exposed from the third insulating film 49 and the portion (upper end) of the second electrode 55 exposed from the third insulating film 49.
  • the second base insulating film 112 also covers, in a film form, the portion of the separation electrode 33 exposed from the separation insulating film 32, and covers, in a film form, the portion of the connection electrode 83 exposed from the connection insulating film 82.
  • Oxidation of the portion of the second base insulating film 112 that covers the wall surface of the trench 41 progresses from the wall surface of the trench 41 toward the inside of the wafer W.
  • a relatively wide second trench portion 45 is defined on the opening side of the trench 41
  • a narrower third trench portion 46 is defined on the bottom wall side of the trench 41.
  • a second base electrode 113 is formed on the second wafer main surface 104.
  • the second base electrode 113 serves as the base of the first electrode 54 of the buried electrode 43.
  • the second base electrode 113 covers the first wafer main surface 103, the separation electrode 33, and the connection electrode 83 with the second base insulating film 112 in between, and is embedded in the opening side of the trench 41 with the second base insulating film 112 in between.
  • the second base electrode 113 includes conductive polysilicon and is formed by a CVD method.
  • unnecessary portions of the second base electrode 113 are removed by etching.
  • the etching may be wet etching and/or dry etching.
  • the second base electrode 113 is removed until the etched surface is positioned closer to the bottom wall of the trench 41 than the first wafer main surface 103. This forms a buried electrode 43 including the first electrode 54 and the second electrode 55.
  • unnecessary portions of the second base insulating film 112 are removed by an etching method. Specifically, the portions of the second base insulating film 112 covering the first wafer main surface 103, the portions covering the separation electrode 33, the portions covering the connection electrode 83, and the portions exposed from the buried electrode 43 (first electrode 54) in the trench 41 are removed.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the unnecessary portions of the second base insulating film 112 may be removed simultaneously with the second base electrode 113 in the process of removing the second base electrode 113.
  • the buried electrode 43 has an electrode surface 50 located on the bottom wall side of the trench 41 relative to the first wafer main surface 103.
  • the electrode surface 50 defines an opening recess 51 together with the side wall of the trench 41 at the opening side of the trench 41. Referring to FIG. 19, the recess depth DR of the opening recess 51 on the second device region 107B side is different from the recess depth DR of the opening recess 51 on the first device region 107A side due to a process error (in-plane error) occurring within the surface of the first wafer main surface 103.
  • the recess depth DR on the second device region 107B side is greater than the recess depth DR on the first device region 107A side.
  • the recess depth DR on the first device region 107A side may be 50 nm or more and 300 nm or less.
  • the recess depth DR on the second device region 107B side may be 300 nm or more and 600 nm or less.
  • the buried electrode 43 has a recess edge 52 recessed toward the bottom wall of the trench 41 at the edge of the electrode surface 50 along the side wall of the trench 41.
  • the buried electrode 43 has a protruding edge 53 protruding toward the opening side of the trench 41 at the edge of the electrode surface 50.
  • the recess depth DR of the opening recess 51 on the second device region 107B side is greater than the recess depth DR of the opening recess 51 on the first device region 107A side.
  • the depth position of the recess edge 52 on the second device region 107B side is in a region lower than the depth position of the recess edge 52 on the first device region 107A side.
  • the depth position of the tip of the protruding edge 53 on the second device region 107B side is in a region lower than the depth position of the tip of the protruding edge 53 on the first device region 107A side.
  • a third base insulating film 114 which is thinner than the second base insulating film 112, is formed on the first wafer main surface 103.
  • the third base insulating film 114 serves as a base for the first insulating film 47 of the insulating film 42.
  • the third base insulating film 114 may be formed by a CVD method and/or an oxidation process method.
  • the oxidation process method may be a wet oxidation process method and/or a thermal oxidation process method.
  • the third base insulating film 114 is formed by an oxidation process (specifically, a thermal oxidation process).
  • the third base insulating film 114 coats, in a film form, the portion of the first wafer main surface 103 exposed from the field insulating film 85, the portion of the wall surface of the trench 41 exposed from the second insulating film 48, and the electrode surface 50 of the buried electrode 43 (first electrode 54).
  • the third base insulating film 114 also coats, in a film form, the portion of the isolation electrode 33 exposed from the isolation insulating film 32, and coats, in a film form, the portion of the connection electrode 83 exposed from the connection insulating film 82.
  • Oxidation of the portion of the third base insulating film 114 that covers the wall surface of the trench 41 progresses from the wall surface of the trench 41 toward the inside of the wafer W.
  • a relatively wide first trench portion 44 is defined on the opening side of the trench 41
  • a second trench portion 45 that is narrower than the first trench portion 44 is defined on the bottom wall side of the trench 41.
  • the third base insulating film 114 may be formed as part of the recess insulating film 57.
  • the third base insulating film 114 defines an insulating recess edge 58 that imitates the recess edge 52 between the wall surface of the trench 41 and the third base insulating film 114.
  • the description of the insulating recess edge 58 is omitted as it has been described above.
  • a fourth mask M4 having a predetermined pattern is formed on the first wafer main surface 103.
  • the fourth mask M4 may be a resist mask (ion implantation mask) including an organic insulating film.
  • the fourth mask M4 has a layout that exposes the regions where the multiple body regions 65 are to be formed and covers the other regions. Specifically, the fourth mask M4 exposes the regions where the multiple trenches 41 are formed and covers the other regions.
  • p-type impurities are introduced into the surface layer of the first wafer main surface 103 by ion implantation through the fourth mask M4.
  • p-type impurities are introduced into the surface layer of the first wafer main surface 103 from the first wafer main surface 103 and the sidewalls of the trenches 41 by oblique ion implantation.
  • the relative implantation angle of the p-type impurity with respect to the first wafer main surface 103 is adjusted, and the p-type impurity is introduced obliquely into the surface layer of the first wafer main surface 103. That is, the wafer W may be supported in a horizontal position, or in a position obliquely inclined with respect to the horizontal direction. In either case, the implantation angle of the p-type impurity with respect to the wafer W is adjusted.
  • the implantation angle (absolute value) of the p-type impurity with respect to the first wafer main surface 103 may be 1° or more and 10° or less.
  • the implantation angle may have a value belonging to at least one of the following ranges: 1° to 2.5°, 2.5° to 5°, 5° to 7.5°, and 7.5° to 10°.
  • the implantation angle (absolute value) is preferably 5° to 10°.
  • the fourth mask M4 is removed after the introduction of the p-type impurity. Then, the body region 65 is formed through a p-type impurity diffusion process using a heat treatment method.
  • a fourth base insulating film 115 is formed on the first wafer main surface 103.
  • the fourth base insulating film 115 serves as a base for the edge insulating film 61 of the edge insulator 60.
  • the fourth base insulating film 115 covers the third base insulating film 114 in a film-like manner. Specifically, the fourth base insulating film 115 covers the first wafer main surface 103, the separation electrode 33, the wall surface of the trench 41, the electrode surface 50 of the buried electrode 43, the connection electrode 83, and the field insulating film 85 with the third base insulating film 114 in between.
  • the fourth base insulating film 115 includes an insulator having properties different from those of the insulating film 42 (first insulating film 47). Specifically, the fourth base insulating film 115 includes an insulator having an etching rate different from that of the insulating film 42 (first insulating film 47). In this embodiment, the fourth base insulating film 115 includes a nitride film (specifically, a silicon nitride film) and is formed by a CVD method.
  • a nitride film specifically, a silicon nitride film
  • the fourth base insulating film 115 coats the sidewall of the trench 41 and the wall surface of the recess edge 52 in the form of a film within the trench 41.
  • the fourth base insulating film 115 also includes a first extension 61a, a second extension 61b, and a groove 62 in the portion that becomes the edge insulating film 61.
  • the description of the portion of the fourth base insulating film 115 that becomes the edge insulating film 61 is omitted as it has been described above.
  • the description of the first extension 61a, the second extension 61b, and the groove 62 of the fourth base insulating film 115 is also omitted as it has been described above.
  • a fifth base insulating film 116 is formed on the first wafer main surface 103.
  • the fifth base insulating film 116 becomes the base of the insulating filler 63 of the edge insulator 60.
  • the fifth base insulating film 116 fills the groove 62 and coats the fourth base insulating film 115 in a film-like manner.
  • the fifth base insulating film 116 coats the first wafer main surface 103, the separation electrode 33, the wall surface of the trench 41, the electrode surface 50 of the buried electrode 43, the connection electrode 83, and the field insulating film 85 in a film-like manner, sandwiching the third base insulating film 114 and the fourth base insulating film 115 therebetween.
  • the fifth base insulating film 116 includes an insulator having properties different from those of the fourth base insulating film 115. Specifically, the fifth base insulating film 116 includes an insulator having an etching rate different from that of the fourth base insulating film 115. In this embodiment, the fifth base insulating film 116 includes a tetraethyl orthosilicate film (TEOS film) and is formed by a CVD method.
  • TEOS film tetraethyl orthosilicate film
  • unnecessary portions of the fifth base insulating film 116 are removed by an etching method. Specifically, this process includes selectively removing the portions of the fifth base insulating film 116 located outside the grooves 62, so as to leave the portions of the fifth base insulating film 116 located within the grooves 62.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the etching method is preferably an anisotropic etching method.
  • the etching method is particularly preferably an RIE (Reactive Ion Etching method) method, which is an example of an anisotropic dry etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the etching method is preferably an anisotropic etching method. It is particularly preferable that the etching method is RIE, which is an example of an anisotropic dry etching method.
  • This process includes selectively removing the fourth base insulating film 115 except for the portion that covers the sidewall of the trench 41, so as to leave the portion of the fourth base insulating film 115 that covers the sidewall of the trench 41.
  • this process includes removing the fourth base insulating film 115 except for the portion that will become the edge insulating film 61.
  • the fifth base insulating film 116 (insulating filling material 63) has a different etching rate from the fourth base insulating film 115. Therefore, during the process of removing the fourth base insulating film 115, the fifth base insulating film 116 (insulating filling material 63) is maintained buried in the groove portion 62. This forms an edge insulator 60 having a layered structure including the edge insulating film 61 and the insulating filling material 63. The edge insulator 60 suppresses the intrusion of conductive residues and insulating residues into the recess edge portion 52 (insulating recess edge portion 58) in the subsequent process.
  • a first barrier insulating film 117 is formed on the first wafer main surface 103.
  • the first barrier insulating film 117 serves as a base for the insulating filler 63 of the edge insulator 60.
  • the first barrier insulating film 117 covers the isolation structure 30, the connection structure 80, and the field insulating film 85 on the first wafer main surface 103, and covers the electrode surface 50 and the edge insulator 60 in the trench 41.
  • the first barrier insulating film 117 covers the electrode surface 50 in the trench 41 with the third base insulating film 114 sandwiched therebetween.
  • the first barrier insulating film 117 includes an insulator having properties different from those of the edge insulating film 61 (fourth base insulating film 115). Specifically, the first barrier insulating film 117 includes an insulator having an etching rate different from that of the edge insulating film 61. In this embodiment, the first barrier insulating film 117 includes a tetraethyl orthosilicate film (TEOS film) and is formed by a CVD method.
  • TEOS film tetraethyl orthosilicate film
  • a fifth mask M5 having a predetermined pattern is formed on the first wafer main surface 103.
  • the fifth mask M5 may be a resist mask (ion implantation mask) including an organic insulating film.
  • the fifth mask M5 has a layout that exposes the regions where the multiple source regions 71 are to be formed and covers the other regions. Specifically, the fifth mask M5 exposes the regions where the multiple trenches 41 are formed and covers the other regions.
  • n-type impurities are introduced into the surface layer of the first wafer main surface 103 by ion implantation through the fifth mask M5.
  • n-type impurities are introduced into the surface layer of the first wafer main surface 103 from the first wafer main surface 103 and the wall surface of the trench 41 by oblique ion implantation.
  • the n-type impurities toward the sidewall of the trench 41 are implanted into the surface layer of the first wafer main surface 103 through the insulating film 42 (first insulating film 47), the edge insulator 60, and the first barrier insulating film 117.
  • the depth of the recess edge 52 (opening recess 51) on the second device region 107B side is greater than the depth of the recess edge 52 (opening recess 51) on the first device region 107A side. Therefore, if the edge insulator 60 does not exist, the introduction depth of the n-type impurity on the second device region 107B side is greater than the introduction depth of the n-type impurity on the first device region 107A side due to the relatively deep recess edge 52 (opening recess 51).
  • the depth of the source region 71 on the second device region 107B side becomes greater than the depth of the source region 71 on the first device region 107A side, and the channel length LC on the second device region 107B side becomes shorter than the channel length LC on the first device region 107A side.
  • an in-plane error occurs in the depth of the multiple source regions 71 between the first device region 107A and the second device region 107B, and an in-plane error occurs in the electrical characteristics of the multiple semiconductor devices 1 between the first device region 107A and the second device region 107B.
  • n-type impurities are introduced into the surface layer of the first wafer main surface 103 through the edge insulator 60, the introduction of the n-type impurities is partially blocked by the edge insulator 60, and the introduction depth of the n-type impurities is limited by the edge insulator 60. In other words, the n-type impurities are prevented from being introduced too deeply in both the first device region 107A and the second device region 107B.
  • the channel length LC on the second device region 107B side is prevented from becoming shorter than the channel length LC on the first device region 107A side.
  • the in-plane error of the multiple source regions 71 that may occur between the first device region 107A and the second device region 107B is suppressed, and therefore the in-plane error of the electrical characteristics of the semiconductor device 1 is suppressed.
  • the relative implantation angle of the n-type impurity with respect to the first wafer main surface 103 is adjusted, and the n-type impurity is introduced obliquely into the surface layer of the first wafer main surface 103. That is, the wafer W may be supported in a horizontal position, or in a position obliquely inclined with respect to the horizontal direction. In either case, the implantation angle of the n-type impurity with respect to the wafer W is adjusted.
  • the implantation angle (absolute value) of the n-type impurity with respect to the first wafer main surface 103 may be 5° or more and 35° or less.
  • the implantation angle may have a value belonging to at least one of the following ranges: 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, and 30° to 35°.
  • the implantation angle (absolute value) is preferably 10° to 25°.
  • the second mask M2 is removed after the introduction of the n-type impurity. Then, the source region 71 is formed through a diffusion process of the n-type impurity by a heat treatment method.
  • a sixth mask M6 having a predetermined pattern is formed on the first wafer main surface 103.
  • the sixth mask M6 may be a resist mask (ion implantation mask) including an organic insulating film.
  • the sixth mask M6 has a layout that exposes the regions where the multiple contact regions 72 are to be formed and covers the other regions. Specifically, the sixth mask M6 exposes the regions where the multiple trenches 41 are formed and covers the other regions.
  • p-type impurities are introduced into the surface layer of the first wafer main surface 103 by ion implantation through the sixth mask M6.
  • p-type impurities are introduced into the surface layer of the first wafer main surface 103 from the first wafer main surface 103 and the wall surfaces of the trench 41 by oblique ion implantation.
  • the p-type impurities directed toward the sidewall of the trench 41 are implanted into the surface layer of the first wafer main surface 103 through the insulating film 42 (first insulating film 47), edge insulator 60, and first barrier insulating film 117.
  • the depth of the recess edge 52 (opening recess 51) on the second device region 107B side is greater than the depth of the recess edge 52 (opening recess 51) on the first device region 107A side. Therefore, if the edge insulator 60 does not exist, the introduction depth of the p-type impurity on the second device region 107B side will be greater than the introduction depth of the p-type impurity on the first device region 107A side due to the relatively deep recess edge 52 (opening recess 51).
  • the depth of the contact region 72 on the second device region 107B side is greater than the depth of the contact region 72 on the first device region 107A side.
  • an in-plane error occurs in the depth of the multiple contact regions 72 between the first device region 107A and the second device region 107B, and therefore an in-plane error occurs in the electrical characteristics of the multiple semiconductor devices 1 between the first device region 107A and the second device region 107B.
  • the introduction of the p-type impurities is partially blocked by the edge insulator 60, and the introduction depth of the p-type impurities is limited by the edge insulator 60.
  • the p-type impurities are prevented from being introduced deeply into both the first device region 107A and the second device region 107B.
  • the in-plane error of the multiple contact regions 72 that may occur between the first device region 107A and the second device region 107B is suppressed, and the in-plane error of the electrical characteristics of the semiconductor device 1 is suppressed.
  • the relative implantation angle of the p-type impurity with respect to the first wafer main surface 103 is adjusted, and the p-type impurity is introduced into the surface layer of the first wafer main surface 103. That is, the wafer W may be supported in a horizontal position, or in a position obliquely inclined with respect to the horizontal direction. In either case, the implantation angle of the p-type impurity with respect to the wafer W is adjusted.
  • the implantation angle (absolute value) of the p-type impurity with respect to the first wafer main surface 103 may be 5° or more and 35° or less.
  • the injection angle may have a value that belongs to at least one of the following ranges: 5° to 10°, 10° to 15°, 15° to 20°, 20° to 25°, 25° to 30°, and 30° to 35°.
  • the injection angle (absolute value) is preferably 10° to 25°.
  • the sixth mask M6 is removed after the introduction of the p-type impurity. After that, a p-type impurity diffusion process is performed using a heat treatment method, and the contact region 72 is formed. The process of forming the multiple contact regions 72 may be performed prior to the process of forming the multiple source regions 71.
  • the first barrier insulating film 117 is removed.
  • This step may include a step of partially removing the third base insulating film 114 and a step of partially removing the field insulating film 85.
  • the step of forming the first barrier insulating film 117 does not necessarily have to be performed and may be omitted as necessary.
  • the source region 71 and the contact region 72 are introduced into the surface layer portion of the first wafer main surface 103 via the edge insulator 60.
  • a second barrier insulating film 118 is formed on the first wafer main surface 103.
  • the second barrier insulating film 118 covers the isolation structure 30, the connection structure 80, and the field insulating film 85 on the first wafer main surface 103, and covers the electrode surface 50 and the edge insulating film 60 in the trench 41.
  • the second barrier insulating film 118 includes an insulator having different properties than the edge insulating film 61.
  • the second barrier insulating film 118 includes an insulator having an etching rate different from the etching rate of the edge insulating film 61.
  • the second barrier insulating film 118 includes an oxide film and is formed by a CVD method.
  • the second barrier insulating film 118 may include a silicon oxide film with no added impurities.
  • the silicon oxide film with no added impurities may be referred to as a USG (Undoped Silicate Glass) film.
  • a seventh mask M7 having a predetermined pattern is formed on the second barrier insulating film 118.
  • the seventh mask M7 may be a resist mask (ion implantation mask) including an organic insulating film.
  • the seventh mask M7 has a layout that exposes the regions where the multiple first silicide layers 75 and the multiple second silicide layers 76 are to be formed, and covers the other regions.
  • the seventh mask M7 has a layout that exposes multiple mesa portions partitioned in the areas between the multiple trenches 41 and covers the other areas.
  • unnecessary portions of the second barrier insulating film 118 are removed by an etching method via the seventh mask M7.
  • the etching method may be a wet etching method and/or a dry etching method.
  • a metal film 119 is formed on the first wafer main surface 103.
  • the metal film 119 is a seed metal for the first silicide layer 75 and the second silicide layer 76.
  • the metal film 119 may include at least one of a Ti film, a Ni film, a Co film, an M film, and a W film.
  • the metal film 119 may be formed by a sputtering method.
  • the metal film 119 covers the second barrier insulating film 118 and a portion of the first wafer main surface 103 that is exposed from the second barrier insulating film 118.
  • the metal film 119 is reacted with the wafer W by a heat treatment method, and a plurality of first silicide layers 75 and a plurality of second silicide layers 76 are formed on the surface portion of the first wafer main surface 103.
  • the heat treatment method may be an RTA method (Rapid Thermal Annealing method). After the heat treatment process, the unreacted portions of the metal film 119 are removed.
  • the metal film 119 may be removed by an etching method (wet etching method and/or dry etching method). After the step of removing the metal film 119, the second barrier insulating film 118 is removed. The second barrier insulating film 118 may be removed by an etching method (wet etching method and/or dry etching method).
  • a contact insulating film 87 is formed on the first wafer main surface 103.
  • the contact insulating film 87 covers the isolation structure 30, the connection structure 80, and the field insulating film 85 on the first wafer main surface 103, and covers the electrode surface 50 and the edge insulator 60 in the trench 41.
  • the contact insulating film 87 includes an insulator different from the insulator that constitutes the recess insulating film 57 (insulating recess edge 58).
  • the contact insulating film 87 includes a nitride film (silicon nitride film) and is formed by a CVD method.
  • the bottom interlayer film 10a of the interlayer film 10 is formed on the first wafer main surface 103. Specifically, the bottom interlayer film 10a is formed on the contact insulating film 87.
  • the bottom interlayer film 10a includes an insulator having properties different from those of the edge insulator 60 (edge insulating film 61). Specifically, the bottom interlayer film 10a includes an insulator having an etching rate different from that of the edge insulator 60 (edge insulating film 61).
  • the bottom interlayer film 10a includes an oxide film (specifically, a silicon oxide film) and is formed by a CVD method.
  • an eighth mask M8 having a predetermined pattern is formed on the bottom interlayer film 10a.
  • the eighth mask M8 has a layout that exposes areas where a plurality of contact openings 93 for a plurality of gate contact electrodes 92 and a plurality of source contact electrodes 97 are to be formed, and covers the other areas.
  • etching method for example
  • the etching method may be a wet etching method and/or a dry etching method. This forms a plurality of contact openings 93 in the bottom interlayer film 10a.
  • the edge insulator 60 contains an insulating material different from that of the bottom interlayer film 10a, and functions as an etching stopper against the etching of the bottom interlayer film 10a.
  • a contact opening 93 may be formed directly above the edge insulator 60. This risk increases as the trench pitch TP becomes narrower.
  • a narrow pitch refers to a state in which the trench pitch TP is less than the gate width WG of the gate structure 40.
  • the etchant for the bottom interlayer film 10a contacts the edge insulator 60 through the contact opening 93.
  • the insulating material of the edge insulator 60 is the same as the insulating material of the bottom interlayer film 10a, part or all of the edge insulator 60 is removed by the etchant for the bottom interlayer film 10a.
  • edge insulator 60 contains an insulating material different from the insulating material of the bottom interlayer film 10a, undesired loss of the edge insulator 60 due to etching is suppressed. This prevents the etchant related to the bottom interlayer film 10a from penetrating into the recess edge 52. In other words, undesired loss of the insulating film 42 (such as the first insulating film 47 and the second insulating film 48) due to the etchant related to the bottom interlayer film 10a is also suppressed.
  • a base contact electrode 120 is formed on the bottom interlayer film 10a.
  • the base contact electrode 120 serves as a base for the multiple gate contact electrodes 92 and the multiple source contact electrodes 97.
  • the base contact electrode 120 is embedded in the multiple contact openings 93 and is formed so as to cover the bottom interlayer film 10a.
  • the base contact electrode 120 has a laminated structure including a first electrode film 94 and a second electrode film 95 laminated in this order from the bottom interlayer film 10a side.
  • the first electrode film 94 may be formed by sputtering
  • the second electrode film 95 may be formed by sputtering.
  • unnecessary portions of the base contact electrode 120 are removed by an etching method.
  • the etching method may be a wet etching method and/or a dry etching method.
  • the base contact electrode 120 is removed until the bottom interlayer film 10a is exposed. As a result, a plurality of gate contact electrodes 92 and a plurality of source contact electrodes 97 are formed.
  • the remaining manufacturing process is carried out on the wafer W, and the wafer W is cut along the multiple cutting lines 108. In this way, multiple semiconductor devices 1 are manufactured from one wafer W.
  • FIG. 20 is a graph showing the relationship between channel length LC and recess depth DR.
  • the vertical axis shows channel length LC
  • the horizontal axis shows recess depth DR of the open recess 51. The closer to the left side of the horizontal axis, the closer to the center of the wafer W, and the closer to the right side of the horizontal axis, the closer to the peripheral edge of the wafer W.
  • the graph shown in FIG. 20 includes a first characteristic S1 and a second characteristic S2.
  • the first characteristic S1 shows the characteristic of the channel length LC when there is no edge insulator 60, and is composed of five white circle plot points.
  • the second characteristic S2 shows the characteristic of the channel length LC when there is an edge insulator 60, and is composed of five black circle plot points.
  • the recess depth DR depth position of the recess edge 52
  • the depth position of the source region 71 relative to the bottom of the body region 65 increases and the channel length LC decreases.
  • the recess depth DR (depth position of the recess edge 52) of the second device region 107B was greater than the recess depth DR (depth position of the recess edge 52) of the first device region 107A.
  • the channel length LC of the second device region 107B was smaller than the channel length LC of the first device region 107A.
  • the channel length LC decreased from 730 ⁇ m to 580 ⁇ m.
  • the decrease in the channel length LC per unit of recess depth DR was 50 nm or more and 100 nm or less (specifically, about 75 nm).
  • the difference between the recess depth DR on the first device region 107A side and the recess depth DR on the second device region 107B side is greater than 0 nm and less than or equal to 100 nm
  • the difference between the channel length LC of the first device region 107A and the channel length LC of the second device region 107B falls within the range of 50 nm to 100 nm.
  • the difference value of the recess depth DR is 100 nm or more and 200 nm or less
  • the difference value of the channel length LC falls within the range of 100 nm or more and 200 nm or less.
  • the difference value of the recess depth DR is more than 0 nm and 200 nm or less
  • the difference value of the channel length LC falls within the range of 50 nm or more and 200 nm or less.
  • the recess depth DR depth position of the recess edge 52
  • the depth position of the source region 71 relative to the bottom of the body region 65 increases, and the channel length LC decreases.
  • the recess depth DR (depth position of the recess edge 52) of the second device region 107B was greater than the recess depth DR (depth position of the recess edge 52) of the first device region 107A.
  • the channel length LC of the second device region 107B was smaller than the channel length LC of the first device region 107A.
  • the decrease (decrease rate) of the channel length LC related to the second characteristic S2 was less than the decrease (decrease rate) of the channel length LC related to the first characteristic S1.
  • the channel length LC decreased from 775 ⁇ m to 765 ⁇ m.
  • the decrease in the channel length LC per unit recess depth DR was 5 nm or more and 25 nm or less (specifically, about 10 nm).
  • the difference between the recess depth DR on the first device region 107A side and the recess depth DR on the second device region 107B side is greater than 0 nm and is equal to or less than 100 nm
  • the difference between the channel length LC of the first device region 107A and the channel length LC of the second device region 107B falls within the range of 5 nm to 25 nm.
  • the difference value of the recess depth DR when the difference value of the recess depth DR is 100 nm or more and 200 nm or less, the difference value of the channel length LC falls within the range of 10 nm or more and 50 nm or less. In other words, when the difference value of the recess depth DR is more than 0 nm and 200 nm or less, the difference value of the channel length LC falls within the range of 5 nm or more and 50 nm or less.
  • the method for manufacturing the semiconductor device 1 provides the same effects as those described above for the semiconductor device 1. Furthermore, the method for manufacturing the semiconductor device 1 can suppress in-plane variations in the channel length LC in the wafer W. Furthermore, the method for manufacturing the semiconductor device 1 can manufacture and provide a wafer structure in which in-plane variations in the channel length LC in the wafer W are suppressed.
  • the in-plane variation of the gate threshold voltage can be suppressed.
  • the in-plane variation of the gate threshold voltage may be calculated by the difference (absolute value) between the gate threshold voltage on the first device region 107A side and the gate threshold voltage on the second device region 107B side.
  • the in-plane variation of the gate threshold voltage is 0.05 V or more and 0.1 V or less.
  • the in-plane variation of the gate threshold voltage is 0.001 V or more and 0.02 V or less.
  • the in-plane variation of the gate threshold voltage may have a value belonging to any one of the ranges of 0.001 V or more and 0.005 V or less, 0.005 V or more and 0.01 V or less, 0.01 V or more and 0.015 V or less, and 0.015 V or more and 0.02 V or less. It is preferable that the in-plane variation of the gate threshold voltage is adjusted to 0.015 V or less.
  • FIG. 21 to 25 several other examples of the gate structure 40 are shown with reference to Figures 21 to 25.
  • the several examples shown in Figures 21 to 25 may be applied independently to the above-mentioned embodiment.
  • an example in which at least two of the several examples shown in Figures 21 to 25 are combined may be applied to the above-mentioned embodiment.
  • the structures shown in Figures 21 to 25 can be obtained by appropriately adjusting the process conditions in the above-mentioned manufacturing process.
  • FIG. 21 is a cross-sectional view showing another example of the gate structure 40.
  • the buried electrode 43 in the above-mentioned embodiment has a protruding edge 53 that protrudes toward the opening at the edge of the electrode surface 50.
  • the buried electrode 43 does not necessarily have to have a protruding edge 53 at the electrode surface 50.
  • the buried electrode 43 may have an electrode surface 50 that is positioned closer to the opening side of the trench 41 (the first main surface 3 side) than the recess edge 52.
  • FIG. 22 is a cross-sectional view showing another example of the gate structure 40.
  • the gate structure 40 according to the above-mentioned embodiment includes a trench 41 having a first trench portion 44, a second trench portion 45, and a third trench portion 46.
  • the gate structure 40 may include a trench 41 that does not have a first trench portion 44, a second trench portion 45, and a third trench portion 46.
  • the trench 41 is formed in a tapered shape with an opening width that gradually narrows from the opening side of the trench 41 toward the bottom wall side in a cross-sectional view.
  • the trench 41 may be formed approximately perpendicular to the first main surface 3.
  • FIG. 23 is a cross-sectional view showing another example of the gate structure 40.
  • the insulating filling material 63 in the above-mentioned embodiment is buried in almost the entire area of the groove 62 in a cross-sectional view.
  • the contact insulating film 87 covers the area of the edge insulating film 61 outside the groove 62.
  • the insulating filling material 63 may be buried in the groove 62 with a gap from the opening end of the groove 62 toward the bottom wall of the groove 62 in a cross-sectional view. In other words, the insulating filling material 63 exposes the opening end of the groove 62 in a cross-sectional view.
  • the contact insulating film 87 has a portion that extends into the groove portion 62 from above the edge insulating film 61.
  • the portion of the contact insulating film 87 positioned within the groove portion 62 covers the insulating filling material 63 within the groove portion 62.
  • the contact insulating film 87 may be in direct contact with the edge insulating film 61 (first extension portion 61a and second extension portion 61b) within the groove portion 62.
  • the contact insulating film 87 may also be in direct contact with the insulating filling material 63 within the groove portion 62.
  • FIG. 24 is a cross-sectional view showing another example of the gate structure 40.
  • the edge insulator 60 in the above-described embodiment has a layered structure including an edge insulating film 61 and an insulating filler 63.
  • the edge insulator 60 may have a single-layer structure consisting of only the edge insulating film 61 without the insulating filler 63.
  • the contact insulating film 87 has a portion that extends from above the edge insulating film 61 into the groove portion 62.
  • the contact insulating film 87 may be in direct contact with the edge insulating film 61 (the first extension portion 61a and the second extension portion 61b) within the groove portion 62.
  • FIG. 25 is a cross-sectional view showing another example of the gate structure 40.
  • the buried electrode 43 in the above-mentioned embodiment has an electrode surface 50 on which the polysilicon (first electrode 54) is exposed.
  • the buried electrode 43 may have a silicide buried layer 130 formed on the surface layer of the electrode surface 50.
  • the silicide buried layer 130 is made of a region in which the surface layer of the electrode surface 50 (first electrode 54) is silicided with a metal material. That is, the silicide buried layer 130 is made of a polycide containing the impurity of the buried electrode 43 (first electrode 54).
  • the silicide buried layer 130 may include at least one of a TiSi layer, a TiSi2 layer, a NiSi layer, a CoSi layer, a CoSi2 layer, a MoSi2 layer, and a WSi2 layer.
  • the silicide buried layer 130 may be exposed from the entire electrode surface 50.
  • the silicide buried layer 130 may form at least a part or all of the recess edge 52.
  • the silicide buried layer 130 may form at least a part or all of the protruding edge 53.
  • the portion of the contact insulating film 87 that covers the electrode surface 50 may cover the silicide buried layer 130.
  • the silicide buried layer 130 may be formed simultaneously with the first silicide layer 75 and the second silicide layer 76.
  • the above-mentioned embodiment can be implemented in other forms.
  • an example was shown in which the output region 6 and the control region 7 are formed on one chip 2.
  • a semiconductor device 1 having an output region 6 but not a control region 7 may also be adopted.
  • a semiconductor device 1 having a control region 7 but not an output region 6 may also be adopted.
  • the semiconductor device 1 having the output region 6 and the semiconductor device 1 having the control region 7 may be incorporated into a semiconductor module, a semiconductor circuit, etc. to form an IPD as shown in FIG. 3.
  • multiple systems of output transistors 15 are shown. However, one system of output transistors 15 may be used.
  • the second system transistors 16B are formed as the first system transistors 16A, and all gate structures 40 for the output transistors 15 are simultaneously controlled to be turned on and off.
  • three or more systems of output transistors 15 may be used.
  • a plurality of group regions 77 for the system transistors 16 constituting the three or more systems are provided, and at the same time, three or more systems of gate wiring 91 corresponding to the group regions 77 are provided.
  • the current monitor circuit 20 may be formed using at least one unit transistor 17 out of the multiple unit transistors 17.
  • the first electrode 54 and the second electrode 55 are at the same potential.
  • a source potential may be applied to the second electrode 55.
  • the source wiring 96 is electrically connected to the connection electrode 83 via the source contact electrode 97.
  • the source terminal 11 is an output terminal and the drain terminal 13 is a power supply terminal.
  • a configuration in which the source terminal 11 is a ground terminal and the drain terminal 13 is an output terminal may also be adopted.
  • the semiconductor device 1 becomes a low-side switching device electrically interposed between a load (inductive load L) and ground.
  • the first conductivity type is n-type and the second conductivity type is p-type.
  • the first conductivity type may be p-type and the second conductivity type may be n-type.
  • a specific configuration in this case can be obtained by replacing the n-type region with a p-type region and at the same time replacing the p-type region with an n-type region in the above description and the attached drawings.
  • the first direction X and the second direction Y are defined by the extension directions of the first to fourth side faces 5A to 5D.
  • the first direction X and the second direction Y may be any directions as long as they maintain a mutually intersecting (specifically perpendicular) relationship.
  • the first direction X may be the extension direction of the third side face 5C (fourth side face 5D)
  • the second direction Y may be the extension direction of the first side face 5A (second side face 5B).
  • the first direction X may be a direction intersecting the first to fourth side faces 5A to 5D
  • the second direction Y may be a direction intersecting the first to fourth side faces 5A to 5D.
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a trench (41) formed in the main surface (3) and having a sidewall and a bottom wall; a buried electrode (43) buried in the trench (41), the buried electrode (43) having an electrode surface (50) located closer to the bottom wall than the main surface (3), and a recess edge portion (52) recessed toward the bottom wall at an edge portion of the electrode surface (50) along the sidewall; and an edge insulator (60) buried in the recess edge portion (52).
  • edge insulator (60) includes an edge insulating film (61) formed in a film shape along the sidewall of the trench (41) and the wall surface of the recess edge (52).
  • edge insulating film (61) includes a first extension (61a) that coats the sidewall of the trench (41) in a film-like manner, and a second extension (61b) that coats the wall surface of the recess edge (52) in a film-like manner so as to be inclined relative to the first extension (61a).
  • the semiconductor device (1) described in A21 or A22 further includes a mesa portion defined between the plurality of trenches (41) on the main surface (3), and a contact electrode (97) connected to the mesa portion at a distance from the plurality of trenches (41).
  • a semiconductor device (1) including: a chip (2) having a main surface (3); a trench (41) formed in the main surface (3) and having side walls and a bottom wall; a buried electrode (43) buried in the trench (41), the buried electrode (43) having an electrode surface (50) located closer to the bottom wall than the main surface (3) and a plurality of recess edges (52) recessed toward the bottom wall at the edges of both sides of the electrode surface (50) in a cross-sectional view; a plurality of edge insulators (60) buried in the plurality of recess edges (52) in a cross-sectional view; and a contact electrode (92) mechanically and electrically connected to the inner portion of the electrode surface (50) at a distance from the plurality of edge insulators (60).
  • a wafer (W) having a main surface (103), a first device region (107A) set in an inner portion of the main surface (103), a second device region (107B) set in a peripheral portion of the main surface (103), a plurality of trenches (41) each having a sidewall and a bottom wall formed in the main surface (103) in the first device region (107A) and the second device region (107B), and a plurality of trenches (41) each having a sidewall and a bottom wall.
  • a wafer structure including: a plurality of buried electrodes (43), each of which has an electrode surface (50) located closer to the bottom wall than the main surface (103), and a recess edge portion (52) recessed toward the bottom wall at an edge portion of the electrode surface (50) along the side wall; and a plurality of edge insulators (60) embedded in the recess edge portions (52) in the plurality of trenches (41).
  • edge insulators (60) each include an edge insulating film (61) formed in a film-like shape along the sidewall of the corresponding trench (41) and the wall surface of the corresponding recess edge (52).
  • edge insulators (60) each have a groove (62) defined by the edge insulating film (61) so as to recess toward the bottom of the recess edge (52).
  • each of the edge insulators (60) includes an embedded object (63) embedded in the groove portion (62).
  • [B5] A wafer structure according to any one of B1 to B4, in which the electrode surface (50) on the second device region (107B) side is positioned closer to the bottom wall of the plurality of trenches (41) than the electrode surface (50) on the first device region (107A) side.
  • a wafer structure according to any one of B1 to B10, further comprising: a drift region (9) of a first conductivity type (n-type) formed in a surface layer portion of the main surface (103) in the first device region (107A) and the second device region (107B); a plurality of body regions (65) of a second conductivity type (p-type) formed in a surface layer portion of the drift region (9) so as to be aligned with the plurality of trenches (41) in the first device region (107A) and the second device region (107B); and a plurality of source regions (71) of a first conductivity type (n-type) formed in a surface layer portion of the body region (65) so as to be aligned with the plurality of trenches (41) in the first device region (107A) and the second device region (107B).
  • a contact insulating film (87) that coats the electrode surface (50) and the edge insulator (60) in the trench (41) of the first device region (107A) in a film-like manner, and that coats the electrode surface (50) and the edge insulator (60) in the trench (41) of the second device region (107B) in a film-like manner.

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118412381A (zh) * 2024-07-02 2024-07-30 华羿微电子股份有限公司 一种高性能mosfet功率器件外延设计结构、制作方法及应用

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018129378A (ja) * 2017-02-07 2018-08-16 ローム株式会社 半導体装置および半導体装置の製造方法、ならびに、半導体ウエハ構造物
JP2019129300A (ja) * 2018-01-26 2019-08-01 トヨタ自動車株式会社 半導体装置とその製造方法
JP2019161199A (ja) * 2017-05-17 2019-09-19 ローム株式会社 半導体装置
JP2020027856A (ja) * 2018-08-10 2020-02-20 ローム株式会社 ＳｉＣ半導体装置
WO2020235629A1 (ja) * 2019-05-22 2020-11-26 ローム株式会社 ＳｉＣ半導体装置
JP2021150536A (ja) * 2020-03-19 2021-09-27 株式会社東芝 半導体装置
WO2022024812A1 (ja) * 2020-07-31 2022-02-03 ローム株式会社 ＳｉＣ半導体装置
WO2022024813A1 (ja) * 2020-07-31 2022-02-03 ローム株式会社 ＳｉＣ半導体装置

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018129378A (ja) * 2017-02-07 2018-08-16 ローム株式会社 半導体装置および半導体装置の製造方法、ならびに、半導体ウエハ構造物
JP2019161199A (ja) * 2017-05-17 2019-09-19 ローム株式会社 半導体装置
JP2019161200A (ja) * 2017-05-17 2019-09-19 ローム株式会社 半導体装置
JP2019129300A (ja) * 2018-01-26 2019-08-01 トヨタ自動車株式会社 半導体装置とその製造方法
JP2020027856A (ja) * 2018-08-10 2020-02-20 ローム株式会社 ＳｉＣ半導体装置
WO2020235629A1 (ja) * 2019-05-22 2020-11-26 ローム株式会社 ＳｉＣ半導体装置
JP2021150536A (ja) * 2020-03-19 2021-09-27 株式会社東芝 半導体装置
WO2022024812A1 (ja) * 2020-07-31 2022-02-03 ローム株式会社 ＳｉＣ半導体装置
WO2022024813A1 (ja) * 2020-07-31 2022-02-03 ローム株式会社 ＳｉＣ半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118412381A (zh) * 2024-07-02 2024-07-30 华羿微电子股份有限公司 一种高性能mosfet功率器件外延设计结构、制作方法及应用

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