WO2024110830A1 - 半導体装置、表示装置、及び電子機器 - Google Patents

半導体装置、表示装置、及び電子機器 Download PDF

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Publication number
WO2024110830A1
WO2024110830A1 PCT/IB2023/061666 IB2023061666W WO2024110830A1 WO 2024110830 A1 WO2024110830 A1 WO 2024110830A1 IB 2023061666 W IB2023061666 W IB 2023061666W WO 2024110830 A1 WO2024110830 A1 WO 2024110830A1
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Prior art keywords
transistor
terminal
conductor
circuit
electrically connected
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Ceased
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PCT/IB2023/061666
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English (en)
French (fr)
Japanese (ja)
Inventor
山崎舜平
木村肇
井上達則
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Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
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Priority to KR1020257017441A priority Critical patent/KR20250114024A/ko
Priority to CN202380077900.3A priority patent/CN120283276A/zh
Priority to JP2024559731A priority patent/JPWO2024110830A1/ja
Publication of WO2024110830A1 publication Critical patent/WO2024110830A1/ja
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266—Details of drivers for scan electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3275—Details of drivers for data electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H10D30/6736—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes characterised by the shape of gate insulators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K50/00—Organic light-emitting devices
    • H10K50/10—OLEDs or polymer light-emitting diodes [PLED]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0267—Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
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    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0289—Details of voltage level shifters arranged for use in a driving circuit

Definitions

  • One aspect of the present invention relates to a semiconductor device, a display device, and an electronic device.
  • one aspect of the present invention is not limited to the above technical field.
  • the technical field of the invention disclosed in this specification relates to an object, an operating method, or a manufacturing method.
  • one aspect of the present invention relates to a process, a machine, a manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one aspect of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, sensors, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, or inspection methods thereof.
  • display devices for electronic devices for XR Extended Reality or Cross Reality
  • XR Extended Reality or Cross Reality
  • VR Virtual Reality
  • AR Augmented Reality
  • mobile phones e.g., smartphones
  • tablet information terminals e.g., smartphones
  • notebook PCs personal computers
  • display devices are being developed that have higher screen resolution, improved color reproducibility (NTSC ratio), smaller drive circuits, and reduced power consumption.
  • Patent Document 1 describes an invention for a pixel circuit that has a circuit that corrects the threshold voltage of the drive transistor.
  • Another example is a technology that uses transistors with oxide semiconductors as semiconductor thin films as switching elements included in pixel circuits of display devices.
  • Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used in transistors.
  • oxide semiconductors have been attracting attention as materials other than silicon-based semiconductor materials.
  • oxide semiconductors not only oxides of single-component metals such as indium oxide and zinc oxide are known, but also oxides of multi-component metals.
  • IGZO In-Ga-Zn oxide
  • Patent Document 2 also discloses an invention in which a transistor containing IGZO in the active layer is used in the pixel circuit of a display device.
  • a display device is provided with a drive circuit, which is provided with various circuits.
  • a drive circuit that functions as a source driver is provided with a shift register circuit, a latch circuit, a source follower circuit, etc.
  • a transistor with a high driving frequency is provided in the shift register circuit.
  • a transistor with a high driving frequency can be manufactured by thinning the gate insulating film between the gate and the semiconductor layer including the channel formation region.
  • the transistor used in the source follower circuit is a transistor with high voltage resistance.
  • a transistor with high voltage resistance can be manufactured by thickening the gate insulating film.
  • the drive circuit When fabricating the drive circuit, it is preferable to fabricate the shift register circuit and the source follower circuit simultaneously from the standpoint of cost, number of processes, etc.
  • the optimal thicknesses of the gate insulating film of the transistors used in the shift register circuit and the source follower circuit are different, so when fabricating the shift register circuit and the source follower circuit simultaneously, it is necessary to consider a process for fabricating transistors with different gate insulating film thicknesses. Note that this fabrication of different transistors may apply not only to transistors in the drive circuit, but also to transistors included in the pixel circuit.
  • An object of one embodiment of the present invention is to provide a semiconductor device that operates stably.
  • An object of one embodiment of the present invention is to provide a semiconductor device with a high driving frequency.
  • an object of one embodiment of the present invention is to provide a highly reliable semiconductor device.
  • an object of one embodiment of the present invention is to provide a display device including the above-described semiconductor device.
  • an object of one embodiment of the present invention is to provide an electronic device including the above-described display device.
  • an object of one embodiment of the present invention is to provide a new semiconductor device, a new display device, or a new electronic device.
  • problems of one embodiment of the present invention are not limited to the problems listed above.
  • the problems listed above do not preclude the existence of other problems.
  • the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be appropriately extracted from these descriptions.
  • one embodiment of the present invention solves at least one of the problems listed above and other problems. Therefore, one embodiment of the present invention does not need to solve all of the problems listed above and other problems.
  • one aspect of the present invention is a semiconductor device having a transistor in which a gate electrode and a channel formation region are provided along the height direction.
  • the channel formation region is along the height direction, the source electrode and the drain electrode are located at different heights.
  • the thickness of the gate insulating film can be made different for each of the multiple transistors.
  • a first insulating film that becomes part of the gate insulating film and a second insulating film are stacked in each of the multiple transistors.
  • an etching process is performed so that the second insulating film is removed in the region that will become the gate insulating film.
  • the second insulating film remains in the region that will become the gate insulating film by the etching process. This makes it possible to create transistors with different gate insulating film thicknesses.
  • One aspect of the present invention is a semiconductor device including a shift register and a source follower circuit.
  • the shift register includes a first transistor
  • the source follower circuit includes a second transistor.
  • the first transistor and the second transistor include a first insulator.
  • the first transistor includes a first gate insulating film
  • the second transistor includes a second gate insulating film.
  • the first transistor includes a first channel formation region along a side surface of a first opening formed in the first insulator
  • the second transistor includes a second channel formation region along a side surface of a second opening formed in the first insulator.
  • the first gate insulating film is located above the first channel formation region in a plan view
  • the second gate insulating film is located above the second channel formation region in a plan view.
  • the second gate insulating film has a thickness greater than that of the first gate insulating film.
  • the first gate insulating film may have a second insulator
  • the second gate insulating film may have the second insulator and a third insulator. Note that it is preferable that the third insulator is located on the second insulator.
  • one aspect of the present invention may have a configuration in (2) above, further comprising a latch circuit.
  • the latch circuit comprises a third transistor, and it is preferable that the third transistor further comprises a third gate insulating film. It is also preferable that the third transistor comprises a third channel formation region along a side surface of the third opening formed in the first insulator. It is also preferable that the third gate insulating film is located above the third channel formation region in a plan view. It is also preferable that the third gate insulating film comprises the second insulator.
  • one aspect of the present invention may have a configuration in the above (3) that includes a level shifter circuit.
  • the level shifter circuit preferably includes a fourth transistor, and the fourth transistor preferably includes a fourth gate insulating film.
  • the fourth transistor preferably includes a fourth channel formation region along a side surface of the fourth opening formed in the first insulator.
  • the fourth gate insulating film is preferably located above the fourth channel formation region in a plan view.
  • the fourth gate insulating film preferably includes a second insulator and a third insulator.
  • each of the first to fourth channel formation regions may contain one or more elements selected from indium, zinc, and an element M.
  • the element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.
  • a taper angle of each of side surfaces of the first to fourth openings may be greater than or equal to 70° and less than or equal to 110°.
  • one aspect of the present invention is a display device including the semiconductor device according to (6) above and a pixel circuit.
  • the pixel circuit includes a driving transistor, and the driving transistor includes a fifth gate insulating film.
  • the driving transistor includes a fifth channel formation region above the first insulator.
  • the fifth gate insulating film is located above the fifth channel formation region in a plan view.
  • the fifth gate insulating film includes a second insulator and a third insulator.
  • the fifth channel formation region may include one or more elements selected from indium, zinc, and an element M.
  • the pixel circuit may include a light-emitting device including an organic EL material.
  • Another embodiment of the present invention is an electronic device including the display device described in (9) above and a housing.
  • Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, and a fourth transistor.
  • Each of the first to fourth transistors has a first conductor located below the first insulator and functioning as one of a source or a drain, a second conductor located above the first insulator and functioning as the other of a source or a drain, a semiconductor in contact with the side of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film.
  • the gate insulating films of the first and second transistors are thicker than the gate insulating films of the third and fourth transistors.
  • One of the first conductor or the second conductor of the first transistor is electrically connected to one of the first conductor or the second conductor of the second transistor. Also, one of the first conductor or the second conductor of the third transistor is electrically connected to one of the first conductor or the second conductor of the fourth transistor.
  • the gate insulating film of each of the first transistor and the second transistor may have the second insulator
  • the gate insulating film of each of the third transistor and the fourth transistor may have the second insulator and the third insulator.
  • the third insulator is located on the second insulator.
  • one aspect of the present invention may have a configuration according to (12) above, which includes a first circuit.
  • the first circuit preferably includes a first terminal, a second terminal, a third terminal, and a fourth terminal, and the first terminal is preferably electrically connected to the gate electrode of the first transistor, the second terminal is preferably electrically connected to the gate electrode of the second transistor, the third terminal is preferably electrically connected to the gate electrode of the third transistor, and the fourth terminal is preferably electrically connected to the gate electrode of the fourth transistor.
  • the first circuit preferably has a function of outputting one of a high-level potential or a low-level potential to each of the first terminal and the third terminal, and a function of outputting the other of the high-level potential or the low-level potential to each of the second terminal and the fourth terminal.
  • Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, and a second capacitor.
  • Each of the first to sixth transistors has a first conductor located below the first insulator and functioning as one of a source or a drain, a second conductor located above the first insulator and functioning as the other of a source or a drain, a semiconductor in contact with the side of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film.
  • the gate insulating films of the first, second, and fifth transistors are thicker than the gate insulating films of the third, fourth, and sixth transistors.
  • One of the first conductor or the second conductor of the first transistor is electrically connected to one of the first conductor or the second conductor of the second transistor and one of the pair of terminals of the first capacitance element, and the gate electrode of the first transistor is electrically connected to one of the first conductor or the second conductor of the fifth transistor and the other of the pair of terminals of the first capacitance element.
  • one of the first conductor or the second conductor of the third transistor is electrically connected to one of the first conductor or the second conductor of the fourth transistor and one of the pair of terminals of the second capacitance element
  • the gate electrode of the third transistor is electrically connected to one of the first conductor or the second conductor of the sixth transistor and the other of the pair of terminals of the second capacitance element.
  • the other of the first conductor or the second conductor of the fifth transistor is electrically connected to the other of the first conductor or the second conductor of the sixth transistor.
  • the gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor.
  • the gate insulating film of each of the first transistor, the second transistor, and the fifth transistor may have the second insulator
  • the gate insulating film of each of the third transistor, the fourth transistor, and the sixth transistor may have the second insulator and the third insulator.
  • the third insulator is located on the second insulator.
  • one aspect of the present invention may have a configuration according to (15) above, which includes a first circuit.
  • the first circuit preferably has a first terminal and a second terminal, and the first terminal is preferably electrically connected to the other of the first conductor or the second conductor of the fifth transistor and the other of the first conductor or the second conductor of the sixth transistor, and the second terminal is preferably electrically connected to a gate electrode of the second transistor and a gate electrode of the fourth transistor.
  • the first circuit preferably has a function of outputting one of a high-level potential or a low-level potential to the first terminal, and a function of outputting the other of the high-level potential or the low-level potential to the second terminal.
  • Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor.
  • Each of the first to eighth transistors has a first conductor located below the first insulator and functioning as one of a source or a drain, a second conductor located above the first insulator and functioning as the other of a source or a drain, a semiconductor in contact with the side of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film.
  • the gate insulating films of the first, second, fifth, and seventh transistors are thicker than the gate insulating films of the third, fourth, sixth, and eighth transistors.
  • One of the first conductor or the second conductor of the first transistor is electrically connected to one of the first conductor or the second conductor of the second transistor and one of the pair of terminals of the first capacitance element, and the gate electrode of the first transistor is electrically connected to one of the first conductor or the second conductor of the fifth transistor, the other of the pair of terminals of the first capacitance element, and one of the first conductor or the second conductor of the seventh transistor.
  • one of the first conductor or the second conductor of the third transistor is electrically connected to one of the first conductor or the second conductor of the fourth transistor and one of the pair of terminals of the second capacitance element
  • the gate electrode of the third transistor is electrically connected to one of the first conductor or the second conductor of the sixth transistor, the other of the pair of terminals of the second capacitance element, and one of the first conductor or the second conductor of the eighth transistor.
  • the other of the first conductor or the second conductor of the fifth transistor is electrically connected to the gate electrode of the fifth transistor, the other of the first conductor or the second conductor of the sixth transistor, and the gate electrode of the sixth transistor.
  • the gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor.
  • the gate insulating film of each of the first transistor, the second transistor, the fifth transistor, and the seventh transistor may have the second insulator
  • the gate insulating film of each of the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor may have the second insulator and the third insulator.
  • the third insulator is located on the second insulator.
  • one aspect of the present invention may have a configuration according to (18) above, which includes a first circuit.
  • the first circuit preferably has a first terminal and a second terminal, and the first terminal is preferably electrically connected to the other of the first conductor or the second conductor of the fifth transistor and the other of the first conductor or the second conductor of the sixth transistor, and the second terminal is preferably electrically connected to a gate electrode of the second transistor and a gate electrode of the fourth transistor.
  • the first circuit preferably has a function of outputting one of a high-level potential or a low-level potential to the first terminal, and a function of outputting the other of the high-level potential or the low-level potential to the second terminal.
  • Another embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a ninth transistor, a first capacitor, and a second capacitor.
  • Each of the first to sixth transistors and the ninth transistor has a first conductor located below the first insulator and functioning as one of a source or a drain, a second conductor located above the first insulator and functioning as the other of a source or a drain, a semiconductor in contact with the side of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film.
  • the gate insulating films of the first, second, fifth, and ninth transistors are thicker than the gate insulating films of the third, fourth, and sixth transistors.
  • One of the first conductor or the second conductor of the first transistor is electrically connected to one of the first conductor or the second conductor of the second transistor and one of the pair of terminals of the first capacitance element, and the gate electrode of the first transistor is electrically connected to one of the first conductor or the second conductor of the fifth transistor, the other of the pair of terminals of the first capacitance element, and the gate electrode of the ninth transistor.
  • one of the first conductor or the second conductor of the third transistor is electrically connected to one of the first conductor or the second conductor of the fourth transistor and one of the pair of terminals of the second capacitance element
  • the gate electrode of the third transistor is electrically connected to one of the first conductor or the second conductor of the sixth transistor and the other of the pair of terminals of the second capacitance element
  • the other of the first conductor or the second conductor of the fifth transistor is electrically connected to the other of the first conductor or the second conductor of the sixth transistor and one of the first conductor or the second conductor of the ninth transistor.
  • the gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor.
  • the gate insulating film of each of the first transistor, the second transistor, the fifth transistor, and the ninth transistor may have the second insulator
  • the gate insulating film of each of the third transistor, the fourth transistor, and the sixth transistor may have the second insulator and the third insulator.
  • the third insulator is located on the second insulator.
  • one aspect of the present invention may have a configuration according to (21) above, which includes a first circuit.
  • the first circuit preferably has a first terminal and a second terminal, and the first terminal is preferably electrically connected to the other of the first conductor or the second conductor of the fifth transistor and the other of the first conductor or the second conductor of the sixth transistor, and the second terminal is preferably electrically connected to a gate electrode of the second transistor and a gate electrode of the fourth transistor.
  • the first circuit preferably has a function of outputting one of a high-level potential or a low-level potential to the first terminal, and a function of outputting the other of the high-level potential or the low-level potential to the second terminal.
  • one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor, and having a configuration different from that of (7) above.
  • Each of the first to eighth transistors has a first conductor located below the first insulator and functioning as one of a source or a drain, a second conductor located above the first insulator and functioning as the other of a source or a drain, a semiconductor in contact with the side of an opening formed in the first insulator and in contact with the first conductor and the second conductor, a gate insulating film located on the semiconductor, and a gate electrode located on the gate insulating film.
  • the gate insulating films of the first, second, fifth, and seventh transistors are thicker than the gate insulating films of the third, fourth, sixth, and eighth transistors.
  • One of the first conductor or the second conductor of the first transistor is electrically connected to one of the first conductor or the second conductor of the second transistor and one of the pair of terminals of the first capacitance element, and the gate electrode of the first transistor is electrically connected to one of the first conductor or the second conductor of the fifth transistor, the other of the pair of terminals of the first capacitance element, and one of the first conductor or the second conductor of the seventh transistor.
  • one of the first conductor or the second conductor of the third transistor is electrically connected to one of the first conductor or the second conductor of the fourth transistor and one of the pair of terminals of the second capacitance element
  • the gate electrode of the third transistor is electrically connected to one of the first conductor or the second conductor of the sixth transistor, the other of the pair of terminals of the second capacitance element, and one of the first conductor or the second conductor of the eighth transistor.
  • the gate electrode of the fifth transistor is electrically connected to the gate electrode of the sixth transistor.
  • the gate electrode of the second transistor is electrically connected to the gate electrode of the fourth transistor.
  • the gate insulating film of each of the first transistor, the second transistor, the fifth transistor, and the seventh transistor may have the second insulator
  • the gate insulating film of each of the third transistor, the fourth transistor, the sixth transistor, and the eighth transistor may have the second insulator and the third insulator.
  • the third insulator is located on the second insulator.
  • one embodiment of the present invention may have a configuration according to (24) above, which includes a first circuit.
  • the first circuit preferably has a first terminal and a second terminal, and the first terminal is preferably electrically connected to the gate electrode of the fifth transistor and the gate electrode of the sixth transistor, and the second terminal is preferably electrically connected to the gate electrode of the second transistor and the gate electrode of the fourth transistor.
  • the first circuit preferably has a function of outputting one of a high-level potential or a low-level potential to the first terminal, and a function of outputting the other of the high-level potential or the low-level potential to the second terminal.
  • a taper angle of a side surface of each opening may be greater than or equal to 70° and less than or equal to 110°.
  • the channel formation region included in each semiconductor may contain one or more elements selected from indium, zinc, and an element M.
  • the element M is one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony.
  • Another embodiment of the present invention is a display device including a driver circuit including the semiconductor device described in (27) above and a display device.
  • the display portion may have a pixel circuit including any one of a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting diode.
  • Another embodiment of the present invention is an electronic device including the display device described in (29) above and a housing.
  • transistors with different gate insulating films can be provided in the same circuit or the same device. This makes it possible to provide a transistor with a high drive frequency and a transistor with high voltage resistance in the same circuit or the same device.
  • a semiconductor device that operates stably can be provided.
  • a semiconductor device with a high driving frequency can be provided.
  • a highly reliable semiconductor device can be provided.
  • a display device including the above-described semiconductor device can be provided.
  • an electronic device including the above-described display device can be provided.
  • a new semiconductor device, a new display device, or a new electronic device can be provided.
  • the effects of one embodiment of the present invention are not limited to the effects listed above.
  • the effects listed above do not preclude the existence of other effects.
  • the other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, etc., and can be extracted appropriately from these descriptions.
  • One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases.
  • FIG. 1 is a block diagram showing an example of a display device.
  • FIG. 2A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 2B to 2D are schematic cross-sectional views showing the example of the semiconductor device.
  • FIG. 3 is a block diagram showing an example of a semiconductor device.
  • FIG. 4 is a block diagram showing an example of a semiconductor device.
  • 5A and 5B are block diagrams illustrating an example of a semiconductor device.
  • 6A and 6B are circuit diagrams showing configuration examples of a semiconductor device.
  • FIG. 7 is a layout diagram showing a configuration example of a semiconductor device.
  • 8A and 8B are cross-sectional views showing configuration examples of a semiconductor device.
  • 9A and 9B are circuit diagrams showing configuration examples of a semiconductor device.
  • FIG. 1 is a block diagram showing an example of a display device.
  • FIG. 2A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 2B to 2D are
  • FIG. 10 is a circuit diagram showing a configuration example of a semiconductor device.
  • 11A and 11B are circuit diagrams showing configuration examples of a semiconductor device.
  • 12A and 12B are circuit diagrams showing configuration examples of a semiconductor device.
  • FIG. 13 is a circuit diagram showing a configuration example of a semiconductor device.
  • 14A and 14B are circuit diagrams showing configuration examples of a semiconductor device.
  • 15A and 15B are circuit diagrams showing configuration examples of a semiconductor device.
  • FIG. 16 is a circuit diagram showing a configuration example of a semiconductor device.
  • 17A and 17B are circuit diagrams showing configuration examples of a semiconductor device.
  • 18A and 18B are circuit diagrams showing configuration examples of a semiconductor device.
  • 19A and 19B are circuit diagrams showing configuration examples of a semiconductor device.
  • 20A and 20B are circuit diagrams showing configuration examples of a semiconductor device.
  • 21A and 21B are circuit diagrams showing configuration examples of a semiconductor device.
  • 22A and 22B are circuit diagrams showing configuration examples of a semiconductor device.
  • FIG. 23 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 24 is a circuit diagram showing a configuration example of a semiconductor device.
  • 25A to 25E are circuit diagrams showing configuration examples of a semiconductor device.
  • 26A to 26C are circuit diagrams showing configuration examples of a semiconductor device.
  • FIG. 27A is a circuit diagram showing a configuration example of a semiconductor device
  • FIG. 27B is a timing chart showing an operation example of the semiconductor device.
  • FIG. 28 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 28 is a circuit diagram showing a configuration example of a semiconductor device.
  • FIG. 29A is a circuit diagram showing a configuration example of a semiconductor device
  • FIG. 29B is a timing chart showing an operation example of the semiconductor device.
  • 30A to 30D are circuit diagrams showing configuration examples of pixel circuits.
  • 31A and 31B are circuit diagrams showing configuration examples of pixel circuits.
  • 32A and 32B are circuit diagrams showing configuration examples of pixel circuits.
  • FIG. 33 is a circuit diagram showing a configuration example of a pixel circuit.
  • FIG. 34 is a circuit diagram showing a configuration example of a pixel circuit.
  • FIG. 35A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 35B to 35D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 35A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 35B to 35D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 36A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 36B to 36D are schematic cross-sectional views illustrating the example of the method for manufacturing a semiconductor device.
  • FIG. 37A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 37B to 37D are schematic cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • FIG. 38A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 38B to 38D are schematic cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • FIG. 38A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 38B to 38D are schematic cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • FIG. 39A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 39B to 39D are schematic cross-sectional views illustrating the example of the method for manufacturing a semiconductor device.
  • FIG. 40A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 40B to 40D are schematic cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • FIG. 41A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 41B to 41D are schematic cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • FIG. 40A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 41B to 41D are schematic cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • FIG. 42A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 42B to 42D are schematic cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • FIG. 43A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 43B to 43D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 44A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 44B to 44D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 45A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS.
  • FIG. 45B to 45D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 46A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 46B to 46D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 47A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 47B to 47D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 48A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 48B and 48C are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 49A is a schematic plan view showing an example of a semiconductor device, and FIGS.
  • FIG. 49B to 49D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 50A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 50B to 50D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 51A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 51B to 51D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 52A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 52B to 52D are schematic cross-sectional views showing the example of a method for manufacturing a semiconductor device.
  • FIG. 53A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS.
  • FIG. 53B to 53D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 54A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 54B to 54D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 55A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 55B to 55D are schematic cross-sectional views showing the example of a method for manufacturing a semiconductor device.
  • FIG. 56A is a schematic plan view showing an example of a method for manufacturing a semiconductor device, and FIGS. 56B to 56D are schematic cross-sectional views showing the example of a method for manufacturing a semiconductor device.
  • FIG. 57A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 57B to 57D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 58A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 58B to 58D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 59A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 59B to 59D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 60A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 60B to 60D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 60A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 60B to 60D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 61A is a schematic plan view showing an example of a semiconductor device, and FIGS. 61B to 61D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 62A is a schematic plan view showing an example of a semiconductor device, and FIGS. 62B to 62D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 63A is a schematic plan view showing an example of a semiconductor device, and FIGS. 63B to 63D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 64A is a schematic plan view showing an example of a semiconductor device, and FIGS. 64B to 64D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 64A is a schematic plan view showing an example of a semiconductor device, and FIGS. 64B to 64D are schematic cross-sectional views showing an example of the semiconductor device.
  • FIG. 65A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 65B to 65D are schematic cross-sectional views showing an example of a method for manufacturing a semiconductor device.
  • FIG. 66A is a plan view schematic diagram showing an example of a method for manufacturing a semiconductor device
  • FIGS. 66B to 66D are cross-sectional views schematic diagrams showing an example of a method for manufacturing a semiconductor device.
  • FIG. 67A is a plan view schematic diagram showing an example of a method for manufacturing a semiconductor device
  • FIGS. 67B to 67D are cross-sectional views schematic diagrams showing an example of a method for manufacturing a semiconductor device.
  • FIG. 67A is a plan view schematic diagram showing an example of a method for manufacturing a semiconductor device
  • FIGS. 67B to 67D are cross-sectional views schematic diagrams showing an example of a method for manufacturing a semiconductor device.
  • FIG. 68A is a plan view schematic diagram showing an example of a method for manufacturing a semiconductor device
  • FIGS. 68B to 68D are cross-sectional views schematic diagrams showing an example of a method for manufacturing a semiconductor device.
  • FIG. 69A is a plan view schematic diagram showing an example of a method for manufacturing a semiconductor device
  • FIGS. 69B to 69D are cross-sectional views schematic diagrams showing an example of a method for manufacturing a semiconductor device.
  • FIG. 70A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 70B to 70D are schematic cross-sectional views showing the example of a method for manufacturing a semiconductor device.
  • FIG. 70A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 70B to 70D are schematic cross-sectional views showing the example of a method for manufacturing a semiconductor device.
  • FIG. 70A is a schematic plan view showing an example of a method for
  • FIG. 71A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 71B to 71D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 72A is a schematic plan view illustrating an example of a method for manufacturing a semiconductor device
  • FIGS. 72B to 72D are schematic cross-sectional views illustrating the example of a method for manufacturing a semiconductor device.
  • FIG. 73A is a schematic plan view showing an example of a method for manufacturing a semiconductor device
  • FIGS. 73B to 73D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 74A is a schematic plan view showing an example of a semiconductor device
  • FIGS. 71B to 71D are schematic cross-sectional views showing the example of the method for manufacturing a semiconductor device.
  • FIG. 74B to 74D are schematic cross-sectional views showing an example of the semiconductor device.
  • 75A and 75B are schematic perspective views showing a configuration example of a display device.
  • FIG. 76 is a block diagram showing an example of the configuration of a display device.
  • FIG. 77 is a schematic cross-sectional view showing a configuration example of a display device.
  • 78A to 78C are schematic cross-sectional views showing configuration examples of a display device.
  • FIG. 79 is a schematic cross-sectional view showing a configuration example of a display device.
  • FIG. 80 is a schematic cross-sectional view showing a configuration example of a display device.
  • FIG. 81 is a schematic cross-sectional view showing a configuration example of a display device.
  • FIG. 82 is a schematic cross-sectional view showing a configuration example of a display device.
  • FIG. 83 is a schematic cross-sectional view showing a configuration example of a display device.
  • FIG. 84 is a schematic cross-sectional view showing a configuration example of a display device.
  • FIG. 85 is a schematic cross-sectional view showing a configuration example of a display device.
  • FIG. 86 is a schematic cross-sectional view showing a configuration example of a display device.
  • FIG. 87 is a schematic cross-sectional view showing a configuration example of a display device.
  • 88A and 88B are diagrams showing a configuration example of a display module.
  • 89A to 89I are perspective views showing an example of an electronic device.
  • FIG. 90A is a schematic perspective view illustrating a configuration example of a memory device
  • FIG. 90B is a block diagram illustrating a configuration example of a semiconductor device
  • FIG. 91 is a block diagram illustrating an example of the configuration of a storage device
  • 92A and 92B are diagrams showing an example of an electronic component
  • 93A and 93B are diagrams showing an example of electronic equipment
  • FIGS. 93C to 93E are diagrams showing an example of a mainframe computer.
  • FIG. 94 is a diagram showing an example of space equipment.
  • FIG. 95 is a diagram illustrating an example of a storage system applicable to a data center.
  • a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (for example, a transistor, a diode, and a photodiode), or a device having such a circuit.
  • a semiconductor device also refers to any device that can function by utilizing semiconductor characteristics.
  • An example of a semiconductor device is an integrated circuit.
  • Another example of a semiconductor device is a chip equipped with an integrated circuit, and another example of a semiconductor device is an electronic component that houses a chip in a package.
  • a memory device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices, or may have a semiconductor device.
  • X and Y are connected, it is assumed that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a specific connection relationship, for example, a connection relationship shown in a figure or text, and it is assumed that a connection relationship other than that shown in a figure or text is also disclosed in the figure or text.
  • X and Y are assumed to be objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer).
  • one or more elements e.g., switches, transistors, capacitive elements, inductors, resistive elements, diodes, display devices, light-emitting devices, and loads
  • the switch has a function that allows it to be controlled to be turned on and off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.
  • a transistor if there is a connection between X and Y via the drain and source of the transistor, it is specified that X and Y are electrically connected.
  • a capacitive element is placed between X and Y, it may or may not be specified that X and Y are electrically connected.
  • a capacitive element is placed between X and Y, it may not be specified that X and Y are electrically connected.
  • an analog circuit if a capacitive element is placed between X and Y, it may be specified that X and Y are electrically connected.
  • one or more circuits that enable the functional connection between X and Y for example, logic circuits (for example, inverters, NAND circuits, and NOR circuits), signal conversion circuits (for example, digital-analog conversion circuits, analog-digital conversion circuits, and gamma correction circuits), potential level conversion circuits (for example, power supply circuits such as step-up circuits or step-down circuits, and level shifter circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (for example, circuits that can increase the signal amplitude or current amount, operational amplifiers, differential amplifier circuits, source follower circuits, and buffer circuits), signal generation circuits, memory circuits, and control circuits) can be connected between X and Y.
  • logic circuits for example, inverters, NAND circuits, and NOR circuits
  • signal conversion circuits for example, digital-analog conversion circuits, analog-digital conversion circuits, and gamma correction circuits
  • X, Y, the source (sometimes referred to as one of the first terminal or the second terminal) and the drain (sometimes referred to as the other of the first terminal or the second terminal) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y.”
  • X, Y, the source of the transistor, the drain of the transistor, and Y are electrically connected in this order.
  • X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are provided in this connection order.”
  • X and Y are assumed to be objects (for example, a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, or a layer).
  • one component may have the functions of multiple components.
  • one conductive film has both the functions of wiring and the function of an electrode. Therefore, in this specification, the term "electrically connected" also includes such cases where one conductive film has the functions of multiple components.
  • the term “resistance element” may be, for example, a circuit element having a resistance value higher than 0 ⁇ , or a wiring having a resistance value higher than 0 ⁇ . Therefore, in this specification, the term “resistance element” includes a wiring having a resistance value, a transistor in which a current flows between a source and a drain, a diode, or a coil. Therefore, the term “resistance element” may be rephrased as “resistance”, “load”, or “region having a resistance value”. Conversely, the term “resistance”, “load”, or “region having a resistance value” may be rephrased as “resistance element”.
  • the resistance value may be, for example, preferably 1 m ⁇ or more and 10 ⁇ or less, more preferably 5 m ⁇ or more and 5 ⁇ or less, and even more preferably 10 m ⁇ or more and 1 ⁇ or less. In addition, it may be, for example, 1 ⁇ or more and 1 ⁇ 10 9 ⁇ or less.
  • a “capacitive element” can be, for example, a circuit element having a capacitance value higher than 0F, a region of a wiring having a capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor.
  • the terms “capacitive element”, “parasitic capacitance”, and “gate capacitance” can sometimes be replaced with the term “capacitance”.
  • the term “capacitance” can sometimes be replaced with the term “capacitive element”, “parasitic capacitance”, or “gate capacitance”.
  • a “capacitive element” (including a “capacitive element” with three or more terminals) is configured to include an insulator and a pair of conductors sandwiching the insulator. Therefore, the term “pair of conductors" in a “capacitive element” can be replaced with “pair of electrodes", “pair of conductive regions", “pair of regions”, or “pair of terminals”. In addition, the terms “one of the pair of terminals” and “the other of the pair of terminals” may be referred to as a first terminal and a second terminal, respectively.
  • the value of the electrostatic capacitance can be, for example, 0.05 fF or more and 10 pF or less. In addition, it may be, for example, 1 pF or more and 10 ⁇ F or less.
  • a transistor has three terminals called a gate, a source, and a drain.
  • the gate is a control terminal that controls the conduction state of the transistor.
  • the two terminals that function as a source or a drain are input/output terminals of the transistor.
  • One of the two input/output terminals becomes a source and the other becomes a drain depending on the conductivity type of the transistor (e.g., n-channel type, p-channel type) and the level of the potential applied to the three terminals of the transistor.
  • the terms source and drain may be interchangeable.
  • the terms “one of the source or drain” (or the first electrode or the first terminal) and “the other of the source or drain” (or the second electrode or the second terminal) are used.
  • a backgate may be included in addition to the three terminals described above.
  • one of the gate or the backgate of the transistor may be referred to as the first gate
  • the other of the gate or the backgate of the transistor may be referred to as the second gate.
  • the terms “gate” and “backgate” may be interchangeable.
  • each gate may be referred to as a first gate, a second gate, a third gate, etc.
  • a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor.
  • the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-current and improve the withstand voltage of the transistor (improve reliability).
  • the multi-gate structure even if the voltage between the drain and source changes when operating in the saturation region, the current between the drain and source does not change much, and a voltage-current characteristic with a flat slope can be obtained. By using voltage-current characteristics with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.
  • the circuit element may have multiple circuit elements.
  • this includes the case where two or more resistors are electrically connected in series.
  • a single capacitance element is shown on a circuit diagram, this includes the case where two or more capacitance elements are electrically connected in parallel.
  • a single transistor is shown on a circuit diagram, this includes the case where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other.
  • a single switch is shown on a circuit diagram, this includes the case where the switch has two or more transistors, the two or more transistors are electrically connected in series or in parallel, and the gates of each transistor are electrically connected to each other.
  • a node can be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region depending on the circuit configuration and device structure. Also, a terminal, wiring, etc. can be referred to as a node.
  • Voltage refers to the potential difference from a reference potential, and if the reference potential is the ground potential, for example, then “voltage” can be used interchangeably as “potential.” Note that ground potential does not necessarily mean 0V. Potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to circuits, etc., and the potential output from circuits, etc. also change.
  • the terms “high-level potential” and “low-level potential” do not mean any specific potential. For example, if two wirings are both described as “functioning as wirings that supply a high-level potential,” the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, if two wirings are both described as “functioning as wirings that supply a low-level potential,” the low-level potentials provided by both wirings do not have to be equal to each other.
  • current refers to the phenomenon of charge transfer (electrical conduction), and for example, the statement “electrical conduction of a positively charged body is occurring” can be rephrased as “electrical conduction of a negatively charged body is occurring in the opposite direction.” Therefore, in this specification, unless otherwise specified, “current” refers to the phenomenon of charge transfer (electrical conduction) accompanying the movement of carriers. Examples of carriers here include electrons, holes, anions, cations, and complex ions, and the carriers differ depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, and vacuums). Furthermore, the "direction of current” in wiring, etc. is the direction in which positively charged carriers move, and is expressed as a positive current amount.
  • the direction in which negatively charged carriers move is the opposite direction to the current direction, and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive/negative (or current direction) of the current, the statement “current flows from element A to element B” can be rephrased as “current flows from element B to element A.” Additionally, the statement “current is input to element A” can be rephrased as "current is output from element A.”
  • ordinal numbers such as “first,” “second,” and “third” are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as “first” in one embodiment of this specification may be a component referred to as “second” in another embodiment or in the claims. Also, for example, a component referred to as “first” in one embodiment of this specification may be omitted in another embodiment or in the claims.
  • the words “above” and “below” indicating position may be used for convenience in explaining the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each configuration is depicted. Therefore, it is not limited to the words explained in the specification, but can be rephrased appropriately depending on the situation. For example, the expression “insulator located on the upper surface of a conductor” can be rephrased as “insulator located on the lower surface of a conductor” by rotating the orientation of the drawing shown by 180 degrees.
  • the terms “above” and “below” do not limit the positional relationship of components to being directly above or below and in direct contact.
  • the expression “electrode B on insulating layer A” does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.
  • the expression “electrode B above insulating layer A” does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.
  • the expression “electrode B below insulating layer A” does not require that electrode B be formed in direct contact below insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.
  • the terms “row” and “column” may be used to explain components arranged in a matrix and their relative positions. Furthermore, the relative positions of the components change as appropriate depending on the direction in which each configuration is depicted. Therefore, the terms are not limited to those described in the specification, and can be rephrased appropriately depending on the situation. For example, the expression “row direction” can sometimes be rephrased as “column direction” by rotating the orientation of the drawing shown by 90 degrees.
  • the terms “film” and “layer” can be interchanged depending on the situation.
  • the term “conductive layer” may be changed to the term “conductive film”.
  • the term “insulating film” may be changed to the term “insulating layer”.
  • the term “insulating layer” or “insulating film” may be changed to the term "insulator”.
  • electrode used in this specification and the like do not limit the functions of these components.
  • an “electrode” may be used as a part of a “wiring,” and vice versa.
  • the terms “electrode” and “wiring” include cases where multiple “electrodes” or “wirings” are formed integrally.
  • a “terminal” may be used as a part of a “wiring” or “electrode,” and vice versa.
  • terminal includes cases where one or more selected from “electrode,” “wiring,” and “terminal” are formed integrally.
  • an “electrode” can be a part of a “wiring” or “terminal,” and, for example, a “terminal” can be a part of a “wiring” or “electrode.”
  • the terms “electrode,” “wiring,” and “terminal” may be replaced with the term “region” depending on the circumstances.
  • the terms “wiring”, “signal line” and “power line” can be interchanged depending on the situation.
  • the term “wiring” can be changed to "signal line”.
  • the term “wiring” can be changed to "power line”.
  • the opposite is also true, and terms such as “signal line” or “power line” can be changed to "wiring”.
  • the term “power line” can be changed to "signal line”.
  • the opposite is also true, and terms such as “signal line” can be changed to "power line”.
  • the term “potential” applied to the wiring can be changed to "signal” depending on the situation. The opposite is also true, and the term “signal” can be changed to “potential”.
  • a timing chart may be used to explain the operation method of a semiconductor device.
  • the timing chart used in this specification shows an ideal operation example, and the period, the magnitude of a signal (e.g., potential or current), and the timing described in the timing chart are not limited unless otherwise specified.
  • the timing chart described in this specification may change the magnitude and timing of a signal (e.g., potential or current) input to each wiring (including a node) in the timing chart depending on the situation. For example, even if two periods are described at equal intervals in the timing chart, the lengths of the two periods may be different from each other. In addition, for example, even if one period is described as long and the other period is described as short, the lengths of both periods may be equal, or one period may be short and the other period may be long.
  • metal oxide is a metal oxide in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply OS), and the like. For example, when a metal oxide is included in the channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can constitute the channel formation region of a transistor having at least one of an amplification function, a rectification function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, when an OS transistor is described, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.
  • metal oxides containing nitrogen may also be collectively referred to as metal oxides.
  • Metal oxides containing nitrogen may also be referred to as metal oxynitrides.
  • impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor layer.
  • an element with a concentration of less than 0.1 atomic % is an impurity.
  • the inclusion of impurities may cause one or more of the following: an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity.
  • impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, and in particular, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.
  • a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows.
  • a switch refers to a device that has the function of selecting and switching the path through which a current flows. For this reason, a switch may have two or more terminals through which a current flows, in addition to a control terminal.
  • an electrical switch, a mechanical switch, etc. can be used.
  • the switch may be anything that can control a current, and is not limited to a specific type.
  • Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors), or logic circuits that combine these.
  • transistors e.g., bipolar transistors, MOS transistors, etc.
  • diodes e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, and diode-connected transistors
  • the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically shorted, or a state in which a current can flow between the source electrode and drain electrode.
  • the "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically cut off.
  • the polarity (conductivity type) of the transistor is not particularly limited.
  • a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology.
  • MEMS microelectromechanical systems
  • This switch has an electrode that can be moved mechanically, and the movement of the electrode controls whether the switch is conductive or non-conductive.
  • a device fabricated using a metal mask or an FMM may be referred to as a device with an MM (metal mask) structure.
  • a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.
  • a structure in which different light-emitting layers are made for each color light-emitting device (here, blue (B), green (G), and red (R)) or the light-emitting layers are painted differently may be referred to as an SBS (Side By Side) structure.
  • SBS Side By Side
  • a light-emitting device that can emit white light may be referred to as a white light-emitting device.
  • a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.
  • Light-emitting devices can be broadly divided into single-structure and tandem-structure devices.
  • a single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers.
  • light-emitting layers can be selected such that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration can be obtained in which the light-emitting device as a whole emits white light.
  • the light-emitting device as a whole can emit white light by combining the emission colors of the three or more light-emitting layers.
  • a device with a tandem structure has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers.
  • each light-emitting unit preferably includes one or more light-emitting layers.
  • light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light emission.
  • the structure for obtaining white light emission is the same as that of the single structure.
  • the light-emitting device with an SBS structure can reduce power consumption compared to the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device with an SBS structure.
  • the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device with an SBS structure, so it is preferable because the manufacturing cost can be reduced or the manufacturing yield can be increased.
  • parallel refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less.
  • substantially parallel or “roughly parallel” refers to a state in which two straight lines are arranged at an angle of -20° or more and 20° or less.
  • perpendicular refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less.
  • substantially perpendicular or “approximately perpendicular” refers to a state in which two straight lines are arranged at an angle of 70° or more and 110° or less.
  • the content described in one embodiment can be applied to, combined with, or substituted for at least one of the content described in another embodiment (or even a part of the content) and the content described in one or more other embodiments (or even a part of the content).
  • a figure (or a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or a part thereof) described in that embodiment, and/or one or more figures (or a part thereof) described in another embodiment or embodiments, thereby constituting even more figures.
  • an identification reference number such as “_1”, “[n]”, “[m,n]” may be added to the reference number.
  • an identification reference number such as “_1”, “[n]”, “[m,n]” is added to a reference number in a drawing, etc., when it is not necessary to distinguish between them in this specification, the identification reference number may not be added.
  • Example of the configuration of the display device> 1 is a schematic diagram showing an example of a display device DSP according to an embodiment of the present invention.
  • the display device DSP includes, as an example, a pixel array PXA, a driving circuit GD, a driving circuit SD, a protection circuit PRT, and a driving circuit TSD provided on a substrate BS.
  • the substrate BS functions as a support for providing the pixel array PXA, the drive circuit GD, the drive circuit SD, the protection circuit PRT, and the drive circuit TSD, as an example.
  • Some or all of the circuits listed above may be formed directly on the substrate BS, or may be mounted on the substrate BS using a COG (chip on glass) method or the like.
  • Some or all of the circuits listed above may be mounted on an FPC (flexible printed circuit) electrically connected to the substrate BS using a COF (chip on film) method or the like.
  • a semiconductor substrate for example, a single crystal substrate made of silicon or germanium
  • the substrate BS can be used as the substrate BS.
  • the substrate BS include SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, plastic substrates, sapphire glass substrates, metal substrates, stainless steel substrates, substrates with stainless steel foil, tungsten substrates, substrates with tungsten foil, flexible substrates, laminated films, paper containing fibrous materials, or base films.
  • SOI Silicon On Insulator
  • glass substrates include barium borosilicate glass, aluminoborosilicate glass, or soda lime glass.
  • Examples of flexible substrates, laminated films, and base films include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), or polytetrafluoroethylene (PTFE).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyethersulfone
  • PTFE polytetrafluoroethylene
  • Another example is synthetic resin such as acrylic resin.
  • polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be used.
  • polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, or paper can be used. If the manufacturing process of the display device DSP includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate BS.
  • the pixel array PXA has, as an example, a plurality of pixel circuits PX.
  • the plurality of pixel circuits PX are arranged in an array in the pixel array PXA.
  • the pixel array PXA has a plurality of pixel circuits PX arranged in any one of a matrix arrangement, a stripe arrangement, an S-stripe arrangement, a delta arrangement, a Bayer arrangement, a Pentile arrangement, etc.
  • the pixel circuit PX located in the i-th row and j-th column (i is an integer of 1 or more, and j is an integer of 1 or more) is represented as pixel circuit PX[i, j].
  • the pixel array PXA may have only one pixel circuit PX instead of multiple ones.
  • the multiple pixel circuits PX have the function of, for example, acquiring an image signal transmitted from a drive circuit SD described below, and emitting light of an intensity according to the image signal.
  • one pixel circuit PX may include two or more sub-pixel circuits.
  • the number of sub-pixel circuits included in one pixel circuit PX and the color of light emitted may be determined so that the light emitted by each of the multiple sub-pixel circuits is combined to produce white light.
  • the entire pixel circuit PX can be a circuit capable of emitting white light.
  • the screen resolution of the display device DSP is determined according to the number of pixel circuits PX included in the pixel array PXA. For example, if the screen resolution of the display device DSP is 8K4K, the number of pixel circuits PX included in the pixel array PXA is 7680 x 4320. Furthermore, if the pixel circuit PX includes three sub-pixel circuits, for example, red (R), green (G) and blue (B), the total number of the sub-pixel circuits included in the pixel array PXA is 7680 x 4320 x 3.
  • the screen resolution of the display device DSP may be SD (the number of pixel circuits PX is 720 x 480), HD (the number of pixel circuits PX is 1280 x 720), FHD (the number of pixel circuits PX is 1920 x 1080), or 4K2K (the number of pixel circuits PX is 3840 x 2160). Furthermore, the screen resolution of the display device DSP is not limited to the above and may be determined arbitrarily during the design stage of the display device DSP.
  • the diagonal size of the display area (pixel array PXA, as an example) of the display device DSP can be determined by the electronic device equipped with the display device DSP.
  • the diagonal size of the display area may be 20 inches or more, 30 inches or more, 60 inches or more, or 100 inches or more.
  • the diagonal size of the display area may be 3 inches or more and 13 inches or less.
  • the diagonal size may be, as an example, 10 inches or less, 5 inches or less, 1.5 inches or less, or 1 inch or less.
  • the resolution of the display area of the display device DSP (sometimes called pixel density) is determined by the screen resolution and diagonal size described above.
  • the resolution of the display area of the display device DSP is preferably 50 ppi or more, more preferably 100 ppi or more, and even more preferably 150 ppi or more.
  • the resolution of the display area of the display device DSP is preferably 200 ppi or more, more preferably 400 ppi or more, and even more preferably 800 ppi or more.
  • the resolution of the display area of the display device DSP is preferably 1000 ppi or more, more preferably 2000 ppi or more, and even more preferably 4000 ppi or more.
  • the screen ratio (aspect ratio) of the display area (pixel array PXA, as an example) of the display device DSP there is no particular limitation on the screen ratio (aspect ratio) of the display area (pixel array PXA, as an example) of the display device DSP.
  • the display area can accommodate various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, and 32:9.
  • the drive circuit GD functions, for example, as a gate driver circuit for selecting a pixel circuit PX included in the pixel array PXA to which an image signal is to be written.
  • the drive circuit SD functions as a source driver circuit for transmitting image signals to the pixel circuits PX included in the pixel array PXA.
  • the pixel circuit PX[i,j] is, for example, electrically connected to the drive circuit GD via the wiring GLS[i]. Also, the pixel circuit PX[i,j] is, for example, electrically connected to the drive circuit SD via the wiring SLS[j].
  • the wiring GLS[i] functions as a wiring for transmitting a selection signal for driving the pixel circuit PX[i,j] from the driving circuit GD to the pixel circuit PX[i,j].
  • the wiring SLS[j] functions as a wiring for transmitting an image signal from the drive circuit SD to the pixel circuit PX[i,j] to display an image in the pixel circuit PX[i,j].
  • the wiring GLS[i] may be a single wiring or a wiring group consisting of multiple wirings.
  • the wiring SLS[j] may be a single wiring or a wiring group consisting of multiple wirings.
  • the drive circuit TSD functions as a circuit for driving a touch sensor provided in an area overlapping the pixel array PXA in a planar view. Note that if a touch sensor is not provided in that area, the display device DSP does not need to be provided with a drive circuit TSD.
  • the protection circuit PRT is electrically connected to the wiring GLS[i] and another wiring.
  • the protection circuit PRT has a function of bringing the wiring GLS[i] and the other wiring into a conductive state, thereby keeping the potential of the wiring GLS[i] within a predetermined range.
  • the protection circuit PRT may be electrically connected to the wiring SLS[j] and another wiring.
  • the protection circuit PRT has a function of, for example, when a potential outside a predetermined range is applied to the wiring SLS[j], bringing the wiring SLS[j] and the other wiring into a conductive state, thereby keeping the potential of the wiring SLS[j] within a predetermined range.
  • the pixel array PXA, the drive circuit GD, the drive circuit SD, the protection circuit PRT, and the drive circuit TSD included in the display device DSP described above each have a transistor, as an example. Since the characteristics of a transistor are determined by the film thickness and material of the semiconductor including the channel formation region, the gate insulator, the source electrode or drain electrode, the gate electrode, etc., it is preferable to provide a transistor with an optimal configuration according to the arrangement location of the transistor. For example, since the level shifter included in the drive circuit SD or the drive circuit GD handles high voltages, it is preferable to use a transistor that is highly resistant to high voltages (high gate potential, high source potential, or high drain potential).
  • the frame rate of the display device DSP is high, it is preferable to use a transistor with a high drive frequency for the shift register included in the drive circuit SD or the drive circuit GD. Furthermore, when it is desired to hold data corresponding to an image signal in the pixel circuit PX for a long time, it is preferable to use a transistor with a low off-current characteristic for the write transistor included in the pixel circuit PX.
  • One embodiment of the present invention is a display device in view of the above, which has a transistor with high resistance to high voltage and a transistor with a high driving frequency.
  • one embodiment of the present invention is a display device in which a transistor with high resistance to high voltage and a transistor with a high driving frequency are formed without significantly increasing the number of manufacturing steps.
  • one embodiment of the present invention may be a display device having a transistor with low off-current characteristics. Note that the transistor with high resistance to high voltage and the transistor with a high driving frequency may have low off-current characteristics.
  • FIG. 2A to 2D show an example of a semiconductor device (for example, a pixel circuit or a driving circuit) including a transistor MTCK having high resistance to high voltage and a transistor MTHN having a high driving frequency.
  • FIG. 2A shows a schematic plan view of the transistor MTCK and the transistor MTHN.
  • FIG. 2B is a schematic cross-sectional view corresponding to the portion of the dashed line A1-A2 shown in FIG. 2A, and is also a schematic cross-sectional view of the transistor MTCK and the transistor MTHN.
  • FIG. 2C is a schematic cross-sectional view corresponding to the portion of the dashed line A3-A4 shown in FIG.
  • FIG. 2A is also a schematic cross-sectional view of the transistor MTCK.
  • FIG. 2D is a schematic cross-sectional view corresponding to the portion of the dashed line A5-A6 shown in FIG. 2A, and is also a schematic cross-sectional view of the transistor MTHN.
  • the direction of the dashed line A1-A2 is the X direction
  • the direction of the dashed line A3-A4 or dashed line A5-A6 is the Y direction.
  • the direction perpendicular to the X and Y directions is the Z direction.
  • the X and Y directions can be perpendicular to each other.
  • the definitions of the X, Y, and Z directions may be the same or different in the following drawings.
  • the right side may be called the X direction, the left side the -X direction, the upper side the Y direction, and the lower side the -Y direction.
  • the right side may be called the X direction, the left side the -X direction, the upper side the Z direction, and the lower side the -Z direction.
  • the right side may be called the -Y direction, the left side the +Y direction, the upper side the Z direction, and the lower side the -Z direction.
  • the transistors MTCK and MTHN in Figures 2A to 2D have insulators IS1 to IS3, insulators GI1 and GI2, conductors ME1 to ME3, and a semiconductor SC1.
  • the insulator IS1 functions as a base film for providing the source, drain, drain, and channel formation regions of the transistors MTCK and MTHN above it.
  • the conductor ME1 is a conductor (which may be referred to as a terminal, wiring, etc.) that functions as either the source or the drain in each of the transistors MTCK and MTHN.
  • the conductor ME2 is a conductor (which may be referred to as a terminal, wiring, etc.) that functions as the other of the source or the drain in each of the transistors MTCK and MTHN.
  • the conductor ME1 is provided as a wiring extending in the Y direction, as an example.
  • the conductor ME2 is provided as a wiring extending in the X direction, as an example.
  • the insulator IS2 functions as an interlayer film that separates the source and drain in the transistors MTCK and MTHN.
  • an opening KK1 is formed whose side is approximately perpendicular to the X-Y plane (taper angle is 70° or more and 110° or less).
  • the semiconductor SC1 including the channel formation region of the transistor MTCK is provided so as to contact the conductors ME1 and ME2 through the opening KK1.
  • an opening KK2 is formed whose side is approximately perpendicular to the X-Y plane.
  • the semiconductor SC1 including the channel formation region of the transistor MTHN is provided so as to contact the conductors ME1 and ME2 through the opening KK2.
  • an insulator GI1 is provided on the semiconductor SC1. Specifically, in a plan view, the insulator GI1 is positioned so as to overlap above the channel formation region included in the semiconductor SC1. Furthermore, in the transistor MTCK, an insulator GI2 is provided on the insulator GI1. Therefore, the insulators GI1 and GI2 function as gate insulating films in the transistor MTCK, and the insulator GI1 also functions as a gate insulating film in the transistor MTHN.
  • conductor ME3 is provided on insulator GI2 so as to fill opening KK1. Further, in transistor MTHN, conductor ME3 is provided on insulator GI1 so as to fill opening KK2.
  • Conductor ME3 is a conductor (which may be referred to as a terminal, wiring, etc.) that functions as a gate in each of transistors MTCK and MTHN.
  • the conductor ME3 is provided as wiring extending in the Y direction, as an example.
  • the conductor ME1 functioning as either the source or the drain is located below the insulator IS2, which serves as the interlayer film, and the conductor ME2 functioning as the other of the source or the drain is located above the insulator IS2. Therefore, the transistors MTCK and MTHN are configured such that their respective channel formation regions are provided along the opening of the first insulator.
  • transistor MTCK and transistor MTHN are located at different heights, and the current flowing through the semiconductor layer flows in the height direction.
  • transistor MTCK and transistor MTHN can also be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, vertical channel transistors, etc.
  • the formation area of the transistor can be made smaller than when the channel formation region of the transistor is provided along the X-Y plane.
  • the source electrode, semiconductor, and drain electrode of the transistor MTCK and the transistor MTHN can be provided in an overlapping manner, the occupation area can be significantly reduced compared to so-called planar transistors in which the semiconductor is arranged in a planar shape. Therefore, by forming a circuit using one or both of the transistor MTCK and the transistor MTHN, the area of the circuit can be made smaller. As a result, it is possible to reduce the size of a semiconductor device including the circuit or a display device including the circuit.
  • the channel length of transistor MTCK is the channel length LCK shown in Figures 2B and 2C
  • the channel length of transistor MTHN is the channel length LHN shown in Figures 2B and 2D.
  • Each of channel length LCK and channel length LHN can be said to be the shortest distance between the part of semiconductor SC1 that contacts conductor ME1 and the part that contacts conductor ME2 in a cross-sectional view.
  • the channel length can be the length between the source and drain of the channel formation region.
  • the channel length LCK of the transistor MTCK corresponds to the height of the opening KK1 of the insulator IS2 in a cross-sectional view.
  • the channel length LHN of the transistor MTHN corresponds to the height of the opening KK2 of the insulator IS2 in a cross-sectional view.
  • the channel length LCK and the channel length LHN are determined according to the thickness of the insulator IS2.
  • the channel length LCK is also determined by the angle between the opening KK1 and the surface to be formed (here, the upper surface of the conductor ME2)
  • the channel length LHN is also determined by the angle between the opening KK2 and the surface to be formed (here, the upper surface of the conductor ME2). Therefore, for example, the channel length LCK and the channel length LHN can be set to values smaller than the limit resolution of the exposure device, and a transistor of a fine size can be realized.
  • a transistor of an extremely small channel length that could not be realized with a conventional exposure device for mass production of flat panel displays (for example, a minimum line width of about 2 ⁇ m or 1.5 ⁇ m) can be realized. It is also possible to create transistors with channel lengths of less than 10 nm without using the extremely expensive exposure equipment used in cutting-edge LSI technology.
  • the channel length LCK and the channel length LHN can be, for example, 5 nm or more, 7 nm or more, or 10 nm or more, and less than 3 ⁇ m, 2.5 ⁇ m or less, 2 ⁇ m or less, 1.5 ⁇ m or less, 1.2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less.
  • the channel length LCK and the channel length LHN can be 100 nm or more and 1 ⁇ m or less.
  • the on-current of the transistors MTCK and MTHN can be increased. In other words, it is no longer necessary to increase the gate-source voltage in order to increase the on-current. For this reason, for example, by applying the transistors MTCK and MTHN to the drive circuit of a large display device or a drive circuit of a high-definition display device, the power consumption related to the gate-source voltage of these drive circuits can be reduced. Furthermore, when the transistors MTCK and MTHN are applied to a large display device or a high-definition display device, even if the number of wirings increases, the signal delay in each wiring can be reduced and display unevenness can be suppressed. Furthermore, since the area occupied by the circuit can be reduced, the frame of the display device can be narrowed.
  • the gate insulating film of transistor MTCK contains insulator GI2
  • the gate insulating film of transistor MTCK is thicker than the gate insulating film of transistor MTHN.
  • the gate insulating film of a transistor is made thicker, the voltage gradient between the gate of the transistor and the channel formation region of the semiconductor can be made gentler, and the tolerance of the transistor to the gate potential can be increased.
  • the gate insulating film of a transistor is made thin, the change in the electric field applied from the gate to the channel formation region of the semiconductor when the gate potential is changed becomes faster, and the driving frequency of the transistor can be increased.
  • the transistor MTCK functions as a transistor that is highly resistant to a high gate potential (in other words, sometimes referred to as a high gate-source voltage or a high gate-drain voltage), and the transistor MTHN functions as a transistor with a high drive frequency.
  • the transistor MTCK may also function as a transistor that is highly resistant to the source potential or drain potential.
  • transistor MTCK The difference between transistor MTCK and transistor MTHN is the thickness of the gate insulating film.
  • insulator GI1 After forming insulator GI1, insulator GI2 is formed on insulator GI1 in the region where transistor MTCK is to be formed, making it possible to easily create transistor MTCK with a thick gate insulating film and transistor MTHN with a thin gate insulating film.
  • the thickness of the insulator GI2 which is formed after the insulator GI1 is provided, can be determined at the stage of the film formation process of the insulator GI2. In other words, the thickness of the gate insulating film of the transistor MTCK may be adjusted even after the insulator GI1 is provided.
  • transistor MTCK has a configuration in which the gate insulating film includes two films, insulator GI1 and insulator GI2, but the gate insulating film of transistor MTCK may be an insulating film in which three or more insulators are stacked. Also, for example, three or more transistors each having a gate insulating film with a different thickness may be included in the same display device.
  • Fig. 3 shows an example of the configuration of a drive circuit SD that can be provided in the display device DSP of Fig. 1.
  • the drive circuit SD1 of Fig. 3 has, as an example, a shift register SR, a holding circuit LTC1, a holding circuit LTC2, an amplifier circuit SF, and a conversion circuit CVT.
  • the shift register SR has, as an example, a plurality of memory circuits RES (e.g., flip-flop circuits or register circuits) connected in a row. Specifically, in adjacent memory circuits RES, the first output terminal of the previous memory circuit RES is electrically connected to the first input terminal of the next memory circuit RES.
  • the first input terminal of the first memory circuit RES[1] (corresponding to the terminal IT of the memory circuit RESA shown in FIG. 6A, etc., described later) is electrically connected to the wiring SP.
  • the second input terminals of the plurality of memory circuits RES (corresponding to the terminals CLK1, CLK2, and PWC of the memory circuit RESA shown in FIG. 6A, etc., described later) are each electrically connected to the wiring CLS. Note that in FIG. 3, the memory circuits RES[1] to RES[5] are selectively shown as the memory circuits RES.
  • the wiring SP functions as a wiring that provides a variable potential (which may be referred to as a pulse potential, a pulse voltage, or a pulse signal) to the shift register SR.
  • the wiring SP may also function as a wiring that provides a fixed potential (for example, a high-level potential, a low-level potential, a ground potential, a negative potential, etc.).
  • the wiring SP may be a single wiring or multiple wirings.
  • the wiring SP functions as a wiring that provides a start pulse signal to the shift register SR.
  • the wiring CLS functions, for example, as a wiring that provides a clock signal to the shift register SR.
  • the wiring CLS may function as a wiring that provides a fixed potential (e.g., a high-level potential, a low-level potential, a ground potential, a negative potential, etc.) or a variable potential.
  • the wiring SP may be a single wiring or multiple wirings.
  • the shift register SR has the function of shifting the information held in the previous memory circuit RES to the subsequent memory circuit RES by receiving a clock signal.
  • the memory circuit RES also has the function of outputting a high-level potential to the second output terminal of the memory circuit RES when a clock signal is input from the wiring CLS to the second input terminal of the memory circuit RES, which stores information about the start pulse signal.
  • the holding circuit LTC1 has, as an example, a plurality of first latch circuits LA.
  • Each of the input terminals D of the plurality of first latch circuits LA is electrically connected to the wiring VIS.
  • each of the second output terminals (e.g., corresponding to the terminal GT of the memory circuit RESA in FIG. 6A described later) of the plurality of memory circuits RES included in the shift register SR is electrically connected in a one-to-one relationship to the enable input terminals E (clock input terminals) of the plurality of first latch circuits LA.
  • the first latch circuits LA[1] to LA[5] are selectively shown as the first latch circuits LA.
  • the wiring VIS functions, for example, as a wiring that provides an image signal (which may be referred to as a video signal or a display signal) as digital data to the holding circuit LTC1.
  • the wiring VIS may also function as a wiring that provides a fixed potential (e.g., a high-level potential, a low-level potential, a ground potential, a negative potential, etc.).
  • the wiring VIS in order to transmit an image signal, which is digital data, the wiring VIS is a multiple wiring.
  • the first latch circuit LA When a high-level potential is input from the second output terminal of the memory circuit RES to the enable input terminal E of the first latch circuit LA, the first latch circuit LA has a function of storing an image signal from the wiring VIS that is input to the input terminal of the first latch circuit LA. Furthermore, after storing the image signal, the first latch circuit has a function of outputting the image signal to the output terminal of the first latch circuit unless the image signal is rewritten.
  • a start pulse signal is input from the wiring SP to the shift register SR
  • a clock signal is input sequentially from the wiring CLS to the shift register SR, so that a high-level potential is input sequentially to each of the enable input terminals E of the multiple first latch circuits. Therefore, by changing the image signal on the wiring VIS in accordance with the clock signal from the wiring CLS to the shift register SR, each of the multiple first latch circuits can store an image signal corresponding to each column.
  • the holding circuit LTC2 has, as an example, a plurality of second latch circuits LB.
  • the input terminals D of the plurality of second latch circuits LB are electrically connected to the output terminals of the plurality of first latch circuits LA in a one-to-one relationship.
  • the enable input terminals E of the plurality of second latch circuits LB are electrically connected to the wiring DAT. Note that in FIG. 3, the second latch circuits LB[1] to LB[5] are selectively shown as the second latch circuits LB.
  • the wiring DAT functions as a wiring that provides a variable potential.
  • the wiring DAT may function as a wiring that provides a fixed potential (high-level potential, low-level potential, ground potential, negative potential, etc.). Note that, in this embodiment, the wiring DAT provides a high-level potential or a low-level potential to the holding circuit LTC2.
  • the wiring DAT applies a low-level potential to the enable input terminal E of the second latch circuit. Furthermore, when image signal information is stored in each of the multiple first latch circuits LA, the image signal output from the output terminal of the first latch circuit LA in that column is input to the input terminal of the second latch circuit LB. At this time, the second latch circuit LB stores the image signal information. In other words, when the storage of image signal information in each of the multiple first latch circuits LA is completed, the storage of image signal information in the multiple second latch circuits LB is also completed at the same time.
  • the stored image signals are output all at once from the output terminals of the second latch circuits LB.
  • the amplifier circuit SF has, as an example, a plurality of source follower circuits SAM.
  • the input terminals of the plurality of source follower circuits SAM are electrically connected in a one-to-one relationship to the output terminals of the plurality of second latch circuits LB. Note that in FIG. 3, the source follower circuits SAM[1] to SAM[5] are selectively shown as the source follower circuits SAM.
  • the conversion circuit CVT has, as an example, a plurality of digital-analog conversion circuits DAC.
  • the input terminals of the plurality of digital-analog conversion circuits DAC are electrically connected in a one-to-one relationship to the output terminals of the plurality of source follower circuits SAM.
  • the output terminals of the plurality of digital-analog conversion circuits DAC are electrically connected in a one-to-one relationship to the plurality of wirings SL.
  • digital-analog conversion circuits DAC[1] to digital-analog conversion circuits DAC[5] are selectively shown as the digital-analog conversion circuits DAC.
  • wirings SL[1] to SL[5] are selectively shown as the wirings SL.
  • the digital-to-analog conversion circuit DAC has a function of converting an image signal, which is digital data, input to an input terminal of the digital-to-analog conversion circuit DAC into analog data and outputting it to an output terminal of the digital-to-analog conversion circuit DAC.
  • the wiring SL can be a wiring equivalent to the wiring SLS shown in FIG. 1. Therefore, the wiring SL can be a wiring for transmitting an image signal, which is analog data, to the pixel circuit.
  • the shift register SR Since it is preferable for the shift register SR to operate at high speed, it is preferable for the memory circuit RES included in the shift register SR to use a transistor MTHN. Also, since the amplifier circuit SF is driven using a high voltage, it is preferable for the source follower circuit SAM included in the amplifier circuit SF to use a transistor MTCK.
  • first latch circuit LA included in the holding circuit LTC1 and the second latch circuit LB included in the holding circuit LTC2 may each use a transistor MTCK or a transistor MTHN. Furthermore, the first latch circuit LA or the second latch circuit LB may each use both a transistor MTCK and a transistor MTHN.
  • the power consumption in the shift register SR can be reduced.
  • the high-level potential output from the second output terminals of the multiple memory circuits RES is also lowered, so that the multiple first latch circuits LA included in the holding circuit LTC1 may not be able to properly capture the image signal transmitted from the wiring VIS to one or more of the multiple first latch circuits LA.
  • the drive circuit SD1 can be changed to the drive circuit SD2 shown in FIG. 4.
  • the drive circuit SD2 differs from the drive circuit SD1 in that it includes an amplifier circuit LVS.
  • the amplifier circuit LVS has a plurality of level shifter circuits LS.
  • the input terminals of the plurality of level shifter circuits LS are electrically connected in a one-to-one relationship to the second output terminals of the plurality of memory circuits RES.
  • the output terminals of the plurality of level shifter circuits LS are electrically connected in a one-to-one relationship to the input terminals of the plurality of first latch circuits LA.
  • the level shifter circuits LS[1] to LS[5] are selectively shown as the level shifter circuits LS.
  • the level shifter circuit LS has a function of amplifying the high-level potential output from the second output terminal of the memory circuit RES, level-shifting it to an even higher potential, and outputting it to the output terminal of the level shifter circuit LS.
  • a higher potential obtained by level-shifting the high-level potential output from the second output terminal of the memory circuit RES can be input to the enable input terminals E of the multiple first latch circuits LA, making it easier to capture the image signals transmitted from the wiring VIS to each of the multiple first latch circuits LA.
  • the driver circuit GD includes, for example, a shift register, which may have the same configuration as the shift register SR included in the driver circuit SD described above.
  • FIG. 5A shows a configuration example of a driver circuit GD according to one embodiment of the present invention that can be applied to the display device DSP in FIG. 1.
  • the driver circuit GD shown in FIG. 5A includes, as an example, memory circuits RES[1] to RES[m] that function as shift registers. Note that for the memory circuits RES[1] to RES[m], the description of the multiple memory circuits RES included in the shift register SR shown in FIG. 3 can be referred to.
  • Each of the memory circuits RES[1] to RES[m] has a first input terminal, a second input terminal, a first output terminal, and a second output terminal, similar to the multiple memory circuits RES included in the shift register SR of Figures 3 and 4, for example.
  • each of the memory circuits RES[1] to RES[m] for example, in adjacent memory circuits RES, the first output terminal of the previous memory circuit RES is electrically connected to the first input terminal of the subsequent memory circuit RES. Furthermore, the first input terminal of the first memory circuit RES[1] is electrically connected to the wiring SS. Furthermore, each of the second input terminals of the multiple memory circuits RES is electrically connected to the wiring CLS2.
  • wiring CLS2 for example, the description of wiring CLS shown in Figure 3 can be referred to.
  • the second output terminal of the memory circuit RES[i] is electrically connected to, for example, the wiring GL[i].
  • Each of the memory circuits RES[1] to RES[m] has, for example, a function of holding information input to a first input terminal and a function of outputting the held information to one or both of a first output terminal and a second output terminal. Note that for specific operations, the description of the shift register SR shown in FIG. 3 can be referred to.
  • the above-mentioned information can be, for example, a selection signal for selecting a pixel circuit PX to which image data is written in the pixel array PXA.
  • the selection signal is transmitted by the wiring SS, the selection signal is sequentially held in the memory circuits RES[1] to RES[m], and the selection signal is sequentially transmitted to the wirings GL[1] to GL[m].
  • the memory circuit RES[m] is illustrated as having a first output terminal, but since the memory circuits RES[1] to RES[m] are configured as shift registers, the memory circuit RES[m] may not have a first output terminal.
  • the configuration of the driver circuit GD that can be applied to the display device DSP in FIG. 1 is not limited to that in FIG. 5A.
  • the configuration of the driver circuit GD that can be applied to the display device DSP in FIG. 1 may be the driver circuit GD shown in FIG. 5B.
  • the driver circuit GD in FIG. 5B differs from the driver circuit GD in FIG. 5A in that it has circuits BF[1] to BF[m].
  • the input terminals of the circuits BF[1] to BF[m] are electrically connected to the second output terminals of the memory circuits RES[1] to RES[m] in a one-to-one relationship, and the output terminals of the circuits BF[1] to BF[m] are electrically connected to the wirings GL[1] to GL[m] in a one-to-one relationship.
  • Each of the circuits BF[1] to BF[m] can include an amplifier circuit, such as a buffer circuit, an inverter circuit, or a latch circuit.
  • each of the circuits BF[1] to BF[m] can have a function of referring to the potential of the second output terminal and outputting the amplified potential to the wiring GL.
  • the amplifier circuit may handle high voltages, it is preferable to use the transistor MTCK as a transistor having high resistance to voltage in the amplifier circuit.
  • the transistor MTHN as a transistor included in the amplifier circuit.
  • wirings other than the wirings CLS and SS may be extended to the driver circuit GD shown in FIG. 5A and FIG. 5B.
  • wirings that apply a fixed potential to drive each of the memory circuits RES[1] to RES[m] may be extended.
  • the driving circuit GD may also have a demultiplexer, as an example. If the potential corresponding to the signal transmitted by the demultiplexer is high, the transistor included in the demultiplexer is preferably a transistor having high resistance to voltage, such as a transistor MTCK. If it is desired to increase the operating speed of the demultiplexer, the transistor included in the demultiplexer is preferably a transistor having a high driving frequency, such as a transistor MTHN.
  • the driving circuit TSD may have a shift register. Therefore, the shift register of the driving circuit TSD may have the same configuration as the shift register SR included in the driving circuit SD described above.
  • the drive circuit TSD may also have, as an example, an amplifier circuit for amplifying a weak signal generated by the touch sensor.
  • the amplifier circuit may be supplied with a high power supply potential for amplifying the signal.
  • the amplifier circuit has a transistor MTCK as a transistor with high resistance to voltage.
  • the protection circuit PRT has a function of discharging electric charge from the wiring GLS[i] or the wiring SLS[j] to another wiring in order to reduce a potential outside a predetermined range applied to the wiring GLS[i] or the wiring SLS[j].
  • the protection circuit PRT handles a potential outside a predetermined range in the wiring GLS[i] or the wiring SLS[j].
  • the protection circuit PRT preferably includes the transistor MTCK as a transistor having high resistance to voltage.
  • the protection circuit PRT has a transistor MTHN, which is a transistor with a high driving frequency.
  • FIG. 6A illustrates an example of a circuit configuration of a memory circuit RESA that can be applied to the memory circuits RES[1] to RES[5] illustrated in FIG. 3 or FIG.
  • the memory circuit RESA includes, as an example, transistors MN1 to MN10 and capacitors C3 to C5. As shown in FIG. 6A, the memory circuit RESA is a unipolar circuit that does not include p-channel transistors and includes n-channel transistors. Therefore, the transistors MN1 to MN10 are n-channel transistors.
  • the memory circuit RESA also has terminals IT, CLK1, CLK2, PWC, GT, and OT, which function as input terminals or output terminals.
  • the memory circuit RESA can be functionally divided into a circuit LGC and a circuit OPC.
  • the circuit LGC has a function as a logic circuit that processes a signal input to a terminal IT
  • the circuit OPC has a function as a logic circuit that generates signals to be output to terminals OT and GT.
  • one or both of the circuit LGC and the circuit OPC may be an analog circuit instead of a logic circuit.
  • the circuit LGC includes, as an example, transistors MN1 to MN4 and a capacitance element C5
  • the circuit OPC includes, as an example, transistors MN5 to MN10, capacitance elements C3 and C4.
  • the division of transistors MN1 to MN10 and capacitance elements C3 to C5 into the circuit LGC and the circuit OPC shown in FIG. 6A is just an example, and the configurations of the circuit LGC and the circuit OPC are not particularly limited.
  • the capacitance element C5 included in the circuit LGC in FIG. 6A may be included in the circuit OPC.
  • the circuit LGC is assumed to have a terminal LI, a terminal LO1, and a terminal LO2.
  • the terminal LI functions as an input terminal in the circuit LGC
  • the terminal LO1 functions as a first output terminal in the circuit LGC
  • the terminal LO2 functions as a second output terminal in the circuit LGC.
  • the circuit OPC included in the memory circuit RESA in FIG. 6A has a function of holding a potential corresponding to a signal input to the terminal IT, using the capacitors C3 and C4. In other words, the circuit OPC has a function of holding a potential output from the terminal LO1 of the circuit LGC.
  • the circuit LGC included in the memory circuit RESA in FIG. 6A has a function of holding a potential of the terminal LO2, using the capacitor C5.
  • the gate of the transistor MN1 is electrically connected to the terminal IT via the terminal LI, and the first terminal of the transistor MN1 is electrically connected to the wiring VDE1.
  • the gate of the transistor MN3 is electrically connected to the terminal CLK2, and the first terminal of the transistor MN3 is electrically connected to the wiring VDE2.
  • the gate of the transistor MN2 is electrically connected to the second terminal of the transistor MN3, the first terminal of the transistor MN4, and the first terminal of the capacitance element C5, the first terminal of the transistor MN2 is electrically connected to the second terminal of the transistor MN1, and the second terminal of the transistor MN2 is electrically connected to the wiring VSE1.
  • the first terminal of the transistor MN2 is electrically connected to the first terminal of the transistor MN5 and the first terminal of the transistor MN8 via the terminal LO1.
  • the gate of the transistor MN2 is electrically connected to the gate of the transistor MN7 and the gate of the transistor MN10 via the terminal LO2.
  • the gate of transistor MN4 is electrically connected to terminal IT via terminal LI, and the second terminal of transistor MN4 is electrically connected to wiring VSE3.
  • the gate of transistor MN5 is electrically connected to wiring VDE3, and the second terminal of transistor MN5 is electrically connected to the gate of transistor MN6 and the first terminal of capacitance element C3.
  • the first terminal of transistor MN6 is electrically connected to terminal CLK1, and the second terminal of transistor MN6 is electrically connected to the first terminal of transistor MN7, the second terminal of capacitance element C3, and terminal OT.
  • the second terminal of transistor MN7 is electrically connected to wiring VSE4.
  • the gate of transistor MN8 is electrically connected to wiring VDE4, and the second terminal of transistor MN8 is electrically connected to the gate of transistor MN9 and the first terminal of capacitance element C4.
  • the first terminal of transistor MN9 is electrically connected to terminal PWC, and the second terminal of transistor MN9 is electrically connected to the first terminal of transistor MN10, the second terminal of capacitance element C4, and terminal GT.
  • the second terminal of transistor MN10 is electrically connected to wiring VSE5.
  • Terminal IT corresponds to the first input terminal of the memory circuit RES in FIG. 3 or FIG. 4.
  • terminals CLK1, CLK2, and PWC are terminals that correspond to the second input terminal of the memory circuit RES in FIG. 3 or FIG. 4. Therefore, the number of wirings CLS shown in FIG. 3 or FIG. 4 can be three or more.
  • the two wirings CLS electrically connected to terminals CLK1 and CLK2 and the one wiring CLS electrically connected to terminal PWC function as wirings that provide a pulse potential.
  • the pulse widths of the pulse potential provided by the one wiring CLS electrically connected to terminal CLK1 or terminal CLK2 and the one wiring CLS electrically connected to terminal PWC may be different from each other.
  • a clock signal with a constant pulse width is transmitted to the two wirings CLS electrically connected to terminals CLK1 and CLK2. It is also preferable that a clock signal with a pulse width that can be changed while the drive circuit SD is in operation is transmitted to one of the wirings CLS electrically connected to terminal PWC. In this case, while the drive circuit SD is in operation, the pulse width of the clock signal input to the memory circuit RES via terminal PWC can be determined arbitrarily.
  • Terminal OT corresponds to the first output terminal of memory circuit RES in FIG. 3 or FIG. 4.
  • Terminal GT corresponds to the second output terminal of memory circuit RES in FIG. 3 or FIG. 4.
  • Each of the wirings VDE1 to VDE4 functions as a wiring that applies a fixed potential, for example.
  • the fixed potential can be a high-level potential.
  • the wirings VDE1 to VDE4 may be applied with the same fixed potential or different fixed potentials. Two or more wirings selected from the wirings VDE1 to VDE4 may be applied with the same fixed potential, and the remaining wirings may be applied with a potential different from the fixed potential.
  • two or more wirings that apply the same fixed potential may be the same wiring. For example, if the wirings VDE1 and VDE2 apply the same fixed potential, the wirings VDE1 and VDE2 may be the same wiring.
  • one or more of the wirings VDE1 to VDE4 may be wirings that provide a variable potential instead of a fixed potential.
  • Each of the wirings VSE1 to VSE5 functions as a wiring that applies a fixed potential, for example.
  • the fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential.
  • the wirings VSE1 to VSE5 may be applied with the same fixed potential or different fixed potentials. Two or more wirings selected from the wirings VSE1 to VSE5 may be applied with the same fixed potential, and the remaining wirings may be applied with a potential different from the fixed potential.
  • two or more wirings that apply the same fixed potential may be the same wiring.
  • the wirings VSE1 and VSE2 may be the same wiring.
  • one or more of the wirings VSE1 to VSE4 may be wirings that provide a variable potential instead of a fixed potential.
  • the circuit LGC in FIG. 6A When, for example, a low-level potential is applied to terminal IT and a high-level potential is applied to terminal CLK2, the circuit LGC in FIG. 6A outputs from terminal LO1 the low-level potential provided by wiring VSE1, and outputs from terminal LO2 a potential obtained by subtracting the threshold voltage of transistor MN3 from the high-level potential provided by wiring VDE2. Note that since a potential obtained by subtracting the threshold voltage of transistor MN3 from the high-level potential provided by wiring VDE2 is input to the gate of transistor MN2, the potential output from terminal LO1 may be, strictly speaking, slightly higher than the low-level potential provided by wiring VSE1.
  • the circuit LGC outputs from terminal LO1 the low-level potential (or a potential slightly higher than the low-level potential) provided by wiring VSE1, which is the potential of node N1, and outputs from terminal LO2 the potential obtained by subtracting the threshold voltage of transistor MN3 from the high-level potential provided by wiring VDE2, which is the potential of node N2.
  • the circuit LGC outputs from terminal LO1 a potential obtained by subtracting the threshold voltage of transistor MN1 from the high-level potential applied by wiring VDE1, and outputs from terminal LO2 a low-level potential applied by wiring VSE3.
  • the circuit LGC outputs from terminal LO1 a potential obtained by subtracting the threshold voltage of transistor MN1 from the high-level potential provided by wiring VDE1, which is the potential of node N1, and outputs from terminal LO2 a potential obtained by subtracting the low-level potential provided by wiring VSE3, which is the potential of node N2.
  • the circuit LGC when a low level potential is input to terminal CLK2 and a high level potential is input to terminal IT, the circuit LGC ideally outputs a high level potential from terminal LO1 and a low level potential from terminal LO2. Also, when a high level potential is input to terminal CLK2 and a low level potential is input to terminal IT, the circuit LGC ideally outputs a low level potential from terminal LO1 and a high level potential from terminal LO2.
  • the circuit LGC when a low level potential is input to terminal CLK2 and a low level potential is input to terminal IT, the circuit LGC outputs the potential of node N1 from terminal LO1 (which may be rephrased as maintaining the potential output from terminal LO1) and outputs the potential of node N2 from terminal LO2 (which may be rephrased as maintaining the potential output from terminal LO2).
  • a memory circuit RESA with high resistance to high voltages can be configured.
  • the operating speed of the memory circuit RESA can be increased, and as a result, the frame frequency of the display device DSP can be increased.
  • FIG. 7 is a layout diagram (plan view) of the memory circuit RESA in FIG. 6A.
  • transistors MN1 to MN10 are illustrated as the transistors MTCK and MTHN described in embodiment 1.
  • the memory circuit RESA has a conductor GEM, a conductor SDD, a conductor SDU, a semiconductor SMC, and a conductor PLG. Note that insulators included in the memory circuit RESA are not illustrated in FIG. 7.
  • the conductor SDD is located below the conductor SDU.
  • the conductor SDU has an opening KK in the area where it overlaps with the conductor SDD. Note that the opening KK is indicated by a dashed line in FIG. 7.
  • the semiconductor SMC is located on the conductor SDU outside the area of the opening KK, and on the conductor SDD in the area of the opening KK.
  • the conductor GEM is located above the semiconductor SMC so as to fill the opening KK.
  • the conductor SDD corresponds to the conductor ME1 in Figures 2A to 2D
  • the conductor SDU corresponds to the conductor ME2 in Figures 2A to 2D
  • the semiconductor SMC corresponds to the semiconductor SC1 in Figures 2A to 2D
  • the conductor GEM corresponds to the conductor ME3 in Figures 2A to 2D.
  • the opening KK corresponds to the opening KK1 or opening KK2 in Figures 2A to 2D.
  • the semiconductor SMC, conductor GEM, conductor SDD, and conductor SDU can each be formed using, for example, a lithography method.
  • the conductive material that will become the conductor GEM can be formed using one or more methods selected from the sputtering method, the CVD (Chemical Vapor Deposition) method, the PLD (Pulsed Laser Deposition) method, and the ALD (Atomic Layer Deposition) method, and then the desired pattern can be formed using a lithography method.
  • the semiconductor SMC, conductor SDD, and conductor SDU can also be formed using the same method as above.
  • Insulators may be provided between the semiconductor SMC and the conductor GEM, between the conductor SDU and the conductor GEM, and between the conductor SDU and the conductor SDD.
  • the insulator provided between the semiconductor SMC and the conductor GEM may function as a gate insulating film.
  • a conductor PLG that functions as a wiring or plug is provided between the conductor SDD and the conductor SDU, and between the conductor SDU and the conductor GEM.
  • the conductor PLG is formed, for example, by forming an opening in the insulator and filling the opening with a conductive material that will become the conductor PLG. After the conductor PLG is formed, it may be planarized by a planarization process using a chemical mechanical polishing method or the like in order to align the film surface heights of the conductor PLG and the surrounding insulator.
  • an opening may be provided in the insulator between the conductor SDU and the conductor GEM, and the conductor SDU and the conductor GEM may be brought into direct contact with each other to electrically connect the conductor SDU and the conductor GEM.
  • the capacitance element C4 in FIG. 7 a part of the conductor GEM is used as the first terminal of the capacitance element C4, and a part of the conductor SDD is used as the second terminal of the capacitance element C4.
  • the insulator between the conductor GEM and the conductor SDD may be thinned in the region of the capacitance element C4 in FIG. 7.
  • an insulator with a high relative dielectric constant may be provided between the conductor GEM and the conductor SDD. Note that the description of the capacitance element C4 can also be referred to for the capacitance element C5.
  • the conductor SDU is used as the first terminal of the capacitance element C3, and a part of the conductor SDD is used as the second terminal of the capacitance element C3. Therefore, in the region of the capacitance element C3 of FIG. 7, the conductor GEM and the conductor SDU are electrically connected, but the conductor SDU and the conductor SDD are not electrically connected. Note that, in order to increase the electrostatic capacitance of the capacitance element C3, the insulator between the conductor SDD and the conductor SDU may be thinned in the region of the capacitance element C3 of FIG. 7. Also, an insulator with a high relative dielectric constant may be provided between the conductor SDD and the conductor SDU.
  • the memory circuit RESA in FIG. 6A may be configured such that some of the transistors MN1 to MN10 are the transistors MTCK or MTHN described in embodiment 1, and the remaining transistors are transistors of a different configuration.
  • the transistors included in the circuit LGC may be transistors that contain silicon in their channel formation region (hereinafter, these may be referred to as Si transistors), and the transistors included in the circuit OPC may be the transistors MTCK or MTHN described in embodiment 1.
  • the silicon may be, for example, amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon (such as low-temperature polysilicon (LTPS)), or single crystal silicon.
  • amorphous silicon sometimes called hydrogenated amorphous silicon
  • microcrystalline silicon such as microcrystalline silicon
  • polycrystalline silicon such as low-temperature polysilicon (LTPS)
  • LTPS low-temperature polysilicon
  • transistors with different configurations include transistors in which germanium (Ge) or the like is included in the channel formation region, transistors in which a compound semiconductor such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or silicon germanium (SiGe) is included in the channel formation region, transistors in which a carbon nanotube is included in the channel formation region, and transistors in which an organic semiconductor is included in the channel formation region.
  • a compound semiconductor such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN), or silicon germanium (SiGe) is included in the channel formation region
  • transistors in which a carbon nanotube is included in the channel formation region
  • FIG. 8A is a cross-sectional view showing some of the transistors in the memory circuit RESA.
  • FIG. 8A shows, as an example, a configuration in which an inverted staggered transistor MA1 is provided below, and a transistor MTCK is provided above it. Note that in FIG. 8A, the conductor MT1 that functions as the source or drain of the transistor MA1 is electrically connected to the conductor ME1 of the transistor MTCK via the conductors PG1 and PG2 that function as wiring or plugs.
  • the transistor MTCK and the transistor MA1 in FIG. 8A can be the transistor MN1 and the transistor MN2 of the memory circuit RESA in FIG. 6A.
  • the transistor MTCK and the transistor MA1 in FIG. 8A can be the transistor MN5 and the transistor MN2 of the memory circuit RESA in FIG. 6A.
  • the transistor MTCK and the transistor MA1 in FIG. 8A can be the transistor MN8 and the transistor MN2.
  • the transistor MN5 of the memory circuit RESA in FIG. 6A can be the transistor MTCK in FIG. 8A
  • the transistor MN1 of the memory circuit RESA in FIG. 6A can be the transistor MA1 in FIG. 8A.
  • FIG. 8B is a cross-sectional view showing some transistors in the memory circuit RESA, which is different from FIG. 8A.
  • FIG. 8B shows, as an example, a configuration in which a TGTC (Top Gate Top Contact) type transistor MA2 is provided below, and a transistor MTCK is provided above it.
  • the conductor MT2 functioning as the source or drain of the transistor MA2 is electrically connected to the conductor ME1 of the transistor MTCK via the conductor PG1 and conductor PG2 functioning as wiring or plugs.
  • transistors MA1 and MA2 shown in Figures 8A and 8B, respectively, can be Si transistors.
  • the transistor MTCK shown in each of Figures 8A and 8B may be the transistor MTHN described in embodiment 1.
  • the configuration of the memory circuit RES that can be provided in the shift register SR is not limited to the memory circuit RESA shown in Fig. 6A.
  • the configuration of the memory circuit RES that can be provided in the shift register SR may be the memory circuit RESB shown in Fig. 6B.
  • the memory circuit RESB in FIG. 6B is a modified example of the memory circuit RESA in FIG. 6A, and differs from the memory circuit RESA in that each transistor included in the memory circuit RESB is provided with a backgate.
  • the transistors MN1 to MN10 shown in FIG. 6A are, for example, n-channel transistors with a multi-gate structure having gates above and below the channel, and the transistors MN1 to MN10 have a backgate in addition to the gate.
  • the gate may be called the first gate (sometimes referred to as the front gate) and the backgate may be called the second gate to distinguish them.
  • the first gate and the second gate can be interchanged, and therefore the term “gate” can be interchanged with the term “backgate”.
  • the term “backgate” can be interchanged with the term "gate”.
  • connection configuration in which "the gate is electrically connected to the first wiring, and the backgate is electrically connected to the second wiring" can be replaced with a connection configuration in which "the backgate is electrically connected to the first wiring, and the gate is electrically connected to the second wiring".
  • each backgate of transistors MN1 to MN10 can be determined at the design stage.
  • the gate and the backgate may be electrically connected to increase the on-current of the transistor (in FIG. 6B, this applies to transistors MN1, MN3, MN5, MN6, MN8, and MN9).
  • wiring may be provided to electrically connect the backgate of the transistor to an external circuit, and a potential may be applied to the backgate of the transistor by the external circuit (in FIG. 6B, this applies to transistors MN2, MN4, MN7, and MN10).
  • transistors MN1 to MN10 are n-channel transistors, but depending on the situation, transistors MN1 to MN10 may be p-channel transistors.
  • transistors may be applicable not only to Figures 6A and 6B, but also to transistors described elsewhere in the specification or shown in other drawings.
  • the gates of transistors MN1, MN3, MN5, MN6, MN8, and MN9 are electrically connected to the back gate.
  • the second gate of transistor MN2 is electrically connected to wiring BG1.
  • the second gate of transistor MN4 is electrically connected to wiring BG2.
  • the gates of transistors MN7 and MN10 are electrically connected to wiring BG3.
  • Each of the wirings BG1 to BG3 functions as a wiring that applies a fixed potential, for example.
  • the fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential.
  • each of the wirings BG1 to BG3 may be applied with the same fixed potential or with different fixed potentials.
  • the two or more selected wirings may be the same wiring.
  • one or more wirings selected from the wirings BG1 to BG3 may be wirings that apply a variable potential instead of a fixed potential.
  • the wirings BG1 to BG3 are different wirings, different fixed potentials can be applied to the back gates of the transistors MN2, MN4, MN7, and MN10.
  • the threshold voltage of the transistor MN2, the threshold voltage of the transistor MN4, and the threshold voltages of the transistors MN7 and MN10 can be controlled independently.
  • the amount of off-current of transistors MN7 and MN10 can be made larger than the amount of off-current of transistor MN4. Therefore, by applying the memory circuit RESB of FIG. 6B to each of the multiple memory circuits RES of the shift register SR of FIG. 3 or FIG. 4, the drive speed of the shift register provided in the drive circuit SD can be further increased.
  • the configuration of the memory circuit RES that can be provided in the shift register SR may be the memory circuit RESPMS shown in FIG. 9A.
  • the memory circuit RESPMS has a circuit configuration in which the memory circuit RESA in FIG. 6A, which is a unipolar circuit including n-channel transistors, is rewritten into a unipolar circuit including p-channel transistors.
  • the memory circuit RESPMS has a circuit LGC and a circuit OPC, similar to the memory circuit RESA in FIG. 6A.
  • the circuit LGC has transistors MP1 to MP4 and a capacitance element C5
  • the circuit OPC has transistors MP5 to MP10 and a capacitance element C3 and a capacitance element C4.
  • each of the transistors MP1 to MP10 is a p-channel transistor.
  • the gate of the transistor MP1 is electrically connected to the terminal IT via the terminal LI, and the first terminal of the transistor MP1 is electrically connected to the wiring VSE16.
  • the gate of the transistor MP3 is electrically connected to the terminal CLK2, and the first terminal of the transistor MP3 is electrically connected to the wiring VSE17.
  • the gate of the transistor MP2 is electrically connected to the second terminal of the transistor MP3, the first terminal of the transistor MP4, and the first terminal of the capacitance element C5, the first terminal of the transistor MP2 is electrically connected to the second terminal of the transistor MP1, and the second terminal of the transistor MP2 is electrically connected to the wiring VDE16.
  • the first terminal of the transistor MP2 is electrically connected to the first terminal of the transistor MP5 and the first terminal of the transistor MP8 via the terminal LO1.
  • the gate of the transistor MP2 is electrically connected to the gate of the transistor MP7 and the gate of the transistor MP10 via the terminal LO2.
  • the gate of transistor MP4 is electrically connected to terminal IT via terminal LI, and the second terminal of transistor MP4 is electrically connected to wiring VDE18.
  • the gate of transistor MP5 is electrically connected to wiring VSE5, and the second terminal of transistor MP5 is electrically connected to the gate of transistor MP6 and the first terminal of capacitance element C3.
  • the first terminal of transistor MP6 is electrically connected to terminal CLK1, and the second terminal of transistor MP6 is electrically connected to the first terminal of transistor MP7, the second terminal of capacitance element C3, and terminal OT.
  • the second terminal of transistor MP7 is electrically connected to wiring VDE19.
  • the gate of transistor MP8 is electrically connected to wiring VSE19, and the second terminal of transistor MP8 is electrically connected to the gate of transistor MP9 and the first terminal of capacitance element C4.
  • the first terminal of transistor MP9 is electrically connected to terminal PWC, and the second terminal of transistor MP9 is electrically connected to the first terminal of transistor MP10, the second terminal of capacitance element C4, and terminal GT.
  • the second terminal of transistor MP10 is electrically connected to wiring VDE20.
  • Each of the wirings VDE16 to VDE20 functions as a wiring that applies a fixed potential, for example.
  • the fixed potential can be, for example, a high-level potential.
  • the wirings VDE16 to VDE20 may be applied with the same fixed potential or different fixed potentials. Two or more wirings selected from the wirings VDE16 to VDE20 may be applied with the same fixed potential, and the remaining wirings may be applied with a potential different from the constant potential.
  • two or more wirings that apply the same fixed potential may be the same wiring.
  • the wirings VDE16 and VDE17 may be the same wiring.
  • one or more of the wirings VDE16 to VDE20 may be wirings that provide a variable potential instead of a fixed potential.
  • Each of the wirings VSE16 to VSE19 functions as a wiring that applies a fixed potential, for example.
  • the fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential.
  • the wirings VSE16 to VSE19 may be applied with the same fixed potential or different fixed potentials. Two or more wirings selected from the wirings VSE16 to VSE19 may be applied with the same fixed potential, and the remaining wirings may be applied with a potential different from the fixed potential.
  • two or more wirings that apply the same fixed potential may be the same wiring.
  • the wirings VSE1 and VSE17 may be the same wiring.
  • one or more of the wirings VSE16 to VSE19 may be wirings that provide a variable potential instead of a fixed potential.
  • the circuit LGC in the memory circuit RESPMS is a unipolar circuit having p-channel transistors
  • the logic of signals, potentials, etc. handled in the memory circuit RESPMS is the inverse of the logic of signals, potentials, etc. handled in the memory circuit RESA in Figure 6A, which is a unipolar circuit having n-channel transistors.
  • a memory circuit RESPMS with high resistance to high voltages can be configured.
  • the operating speed of the memory circuit RESPMS can be increased, and as a result, the frame frequency of the display device DSP can be increased.
  • the configuration of the memory circuit RES that can be provided in the shift register SR may be the memory circuit RESCMS shown in FIG. 9B.
  • the memory circuit RESCMS has a circuit configuration in which the memory circuit RESA in FIG. 6A, which is a unipolar circuit including n-channel transistors, is rewritten into a CMOS (Complementary MOS) circuit including n-channel transistors and p-channel transistors.
  • CMOS Complementary MOS
  • the memory circuit RESCMS has a circuit LGC and a circuit OPC, similar to the memory circuit RESA in FIG. 6A.
  • the circuit LGC has transistors MP1, MN2, MP3, MN4, a capacitive element C5, and an inverter INV10
  • the circuit OPC has transistors MP6, MN7, MP9, and MP10.
  • the transistors MP1, MP3, MP6, and MP9 are p-channel transistors
  • the transistors MN2, MN4, MN7, and MN10 are n-channel transistors.
  • the inverter INV10 may be a unipolar circuit including either an n-channel transistor or a p-channel transistor, or a CMOS circuit including both.
  • the gate of the transistor MP1 is electrically connected to the output terminal of the inverter INV10.
  • the input terminal of the inverter INV10 is electrically connected to the terminal IT via the terminal LI.
  • the first terminal of the transistor MP1 is electrically connected to the wiring VDE1.
  • the gate of the transistor MP3 is electrically connected to the terminal CLK2, and the first terminal of the transistor MP3 is electrically connected to the wiring VDE2.
  • the gate of the transistor MN2 is electrically connected to the second terminal of the transistor MP3, the first terminal of the transistor MN4, and the first terminal of the capacitance element C5, the first terminal of the transistor MN2 is electrically connected to the second terminal of the transistor MN1, and the second terminal of the transistor MN2 is electrically connected to the wiring VSE1.
  • the first terminal of the transistor MN2 is electrically connected to the gate of the transistor MP6 and the gate of the transistor MP9 via the terminal LO1.
  • the gate of transistor MN2 is electrically connected to the gate of transistor MN7 and the gate of transistor MN10 via terminal LO2.
  • the gate of transistor MN4 is electrically connected to terminal IT via terminal LI, and the second terminal of transistor MN4 is electrically connected to wiring VSE3.
  • the first terminal of the transistor MP6 is electrically connected to the terminal CLK1, and the second terminal of the transistor MP6 is electrically connected to the first terminal of the transistor MN7 and the terminal OT.
  • the second terminal of the transistor MN7 is electrically connected to the wiring VSE4.
  • the first terminal of the transistor MP9 is electrically connected to the terminal PWC, and the second terminal of the transistor MP9 is electrically connected to the first terminal of the transistor MN10 and the terminal GT.
  • the second terminal of the transistor MN10 is electrically connected to the wiring VSE5.
  • wiring VDE1, wiring VDE2, and wiring VSE1 to wiring VSE5 the description of the wiring VDE1, wiring VDE2, and wiring VSE1 to wiring VSE5 shown in FIG. 6A can be referred to.
  • the terminal CLK2 is electrically connected to the gate of the transistor MP3, which is a p-channel transistor, so that the logic of the signal input to the gate of the transistor MP3 in the memory circuit RESCMS is the inverted logic of the signal input to the gate of the transistor MN3, which is an n-channel transistor, in the memory circuit RESA in FIG. 6A.
  • a memory circuit RESCMS with high resistance to high voltages can be configured.
  • the operating speed of the memory circuit RESCMS can be increased, and as a result, the frame frequency of the display device DSP can be increased.
  • the configuration of the memory circuit RES that can be provided in the shift register SR may be the memory circuit RESC shown in FIG.
  • the memory circuit RESC has terminals ITA and ITB that function as the first input terminals of the memory circuit RES in FIG. 3 or 4, and terminals OTA and OTB that function as the first output terminals of the memory circuit RES in FIG. 3 or 4.
  • the memory circuit RESC differs from the memory circuit RESA in that it has two first input terminals and two first output terminals.
  • terminal OTA of the previous stage memory circuit RESC is electrically connected to the terminal ITA of the next stage memory circuit RESC
  • the terminal OTB of the previous stage memory circuit RESC is electrically connected to the terminal ITB of the next stage memory circuit RESC.
  • the memory circuit RESC also has a terminal CLK3 and a terminal CLK4.
  • the terminals CLK3 and CLK4 are terminals that correspond to the second input terminal of the memory circuit RES in FIG. 3 or FIG. 4. Therefore, the number of wirings CLS shown in FIG. 3 or FIG. 4 can be two or more.
  • one of the wirings CLS electrically connected to terminal CLK3 or terminal CLK4 and one of the wirings CLS electrically connected to terminal PWC function as wirings that apply a pulse potential.
  • the pulse widths of the pulse potentials applied to terminal CLK3 and terminal CLK4 may be different from each other.
  • the memory circuit RESC has a terminal GT.
  • the terminal GT is a terminal that corresponds to the second output terminal of the memory circuit RES in FIG. 3 or FIG. 4.
  • the memory circuit RESC includes, as an example, transistors MN51 to MN59 and capacitance elements C6 to C8. As shown in FIG. 10, the memory circuit RESC is a unipolar circuit that does not include a p-channel transistor and includes an n-channel transistor.
  • the transistors MN51 to MN59 have a single-gate structure, but they may also have a multi-gate structure with gates above and below the channel.
  • the first terminal of the capacitance element C6 is electrically connected to the first terminal of the transistor MN52 and the terminal CLK4, and the second terminal of the capacitance element C6 is electrically connected to the first terminal of the transistor MN51, the gate of the transistor MN52, and the first terminal of the transistor MN53.
  • the second terminal of the transistor MN51 is electrically connected to the wiring VSE6, and the gate of the transistor MN51 is electrically connected to the terminal ITB.
  • the second terminal of the transistor MN53 is electrically connected to the wiring VSE7, and the gate of the transistor MN53 is electrically connected to the terminal CLK3.
  • the second terminal of the transistor MN52 is electrically connected to the gate of the transistor MN56, the first terminal of the transistor MN57, the gate of the transistor MN59, and the first terminal of the capacitance element C8.
  • the second terminal of the transistor MN57 is electrically connected to the wiring VSE9.
  • the second terminal of the capacitance element C8 is electrically connected to the wiring VSE10.
  • the first terminal of the transistor MN54 is electrically connected to the wiring VDE6, and the second terminal of the transistor MN54 is electrically connected to the first terminal of the transistor MN55, the gate of the transistor MN57, the first terminal of the transistor MN56, and the terminal OTB.
  • the second terminal of the transistor MN56 is electrically connected to the wiring VSE8.
  • the second terminal of the transistor MN55 is electrically connected to the gate of the transistor MN58 and the first terminal of the capacitance element C7, and the gate of the transistor MN55 is electrically connected to the wiring VDE7.
  • the first terminal of the transistor MN58 is electrically connected to the terminal CLK4, and the second terminal of the transistor MN58 is electrically connected to the second terminal of the capacitance element C7, the first terminal of the transistor MN59, the terminal OTA, and the terminal GT, and the second terminal of the transistor MN59 is electrically connected to the wiring VSE11.
  • each of the wirings VDE6 and VDE7 functions as a wiring that applies a fixed potential.
  • the fixed potential can be, for example, a high-level potential.
  • the wirings VDE6 and VDE7 may be applied with the same fixed potential or different fixed potentials.
  • the wirings VDE6 and VDE7 may be the same wiring.
  • one or both of the wirings VDE6 and VDE7 may be wirings that provide a variable potential instead of a fixed potential.
  • Each of the wirings VSE6 to VSE11 functions as a wiring that applies a fixed potential, for example.
  • the fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential.
  • each of the wirings VSE6 to VSE11 may be applied with the same fixed potential or different fixed potentials.
  • two or more wirings selected from each of the wirings VSE6 to VSE11 may be applied with the same fixed potential, and the remaining wirings may be applied with a potential different from the fixed potential.
  • two or more wirings that apply the same fixed potential may be the same wiring.
  • the wirings VSE6 and VSE7 may be the same wiring.
  • one or more of the wirings VSE6 to VSE11 may be wirings that provide a variable potential instead of a fixed potential.
  • the semiconductor device can be configured such that part of the memory circuit RES is driven by a low power supply voltage and the remaining part of the memory circuit RES is driven by a high power supply voltage.
  • the power supply voltage supplied to the shift register SR is lowered to drive the shift register SR.
  • the power supply voltage can be, for example, a potential difference between a high-level potential provided by the wirings VDE1 to VDE4 in FIG. 6A and a low-level potential provided by the wirings VSE1 to VSE5 in FIG. 6A.
  • the power supply voltage can be, for example, a voltage amplitude of a clock signal provided by the terminals CLK1, CLK2, and PWC in FIG. 6A.
  • the power supply voltage can be, for example, a potential difference between a high potential and a low potential of a start pulse signal input to the shift register SR.
  • the power consumption of the shift register can be reduced.
  • the voltage output from the first output terminal and the second output terminal of the memory circuit RES provided in the shift register SR also becomes lower.
  • the voltage output from the first output terminal and the second output terminal of the shift register SR can be the potential difference between the high level potential and the low level potential that can be output from the terminal.
  • a potential (high level potential or low level potential) corresponding to the clock signal of the terminal CLK1 or a low level potential provided by the wiring VSE4 is output from the terminal OT (corresponding to the first output terminal of the memory circuit RES in FIG. 3 or FIG. 4), and a potential (high level potential or low level potential) corresponding to the clock signal of the terminal PWC or a low level potential provided by the wiring VSE5 is output from the terminal GT (corresponding to the second output terminal of the memory circuit RES in FIG. 3 or FIG. 4).
  • the lower voltage is input to the enable input terminals of the multiple first latch circuits LA included in the holding circuit LTC1 in FIG. 3.
  • the image signal transmitted from the wiring VIS to one or more of the multiple first latch circuits LA may not be captured properly.
  • a semiconductor device is a memory circuit RES or a shift register SR including a memory circuit RES, which can lower the voltage output from the first output terminal of the memory circuit RES and increase the voltage output from the second output terminal of the memory circuit RES by driving a part of the memory circuit RES with a low power supply voltage and driving the remaining part of the memory circuit RES with a high power supply voltage.
  • the semiconductor device is a memory circuit RES or a shift register SR including a memory circuit RES, in which the signal transmitted from the previous memory circuit RES to the next memory circuit RES in FIG. 3 or FIG.
  • the signal transmitted from the memory circuit RES to the enable input terminal of the first latch circuit LA is a high voltage (e.g., a potential difference between a potential higher than the high-level potential and a low-level potential).
  • a high voltage e.g., a potential difference between a potential higher than the high-level potential and a low-level potential.
  • the memory circuit RESD1 shown in FIG. 11A shows an example of a circuit configuration of a memory circuit that can be applied to the multiple memory circuits RES included in the shift register SR of FIG. 3 or FIG. 4.
  • the memory circuit RESD1 shown in FIG. 11A has a circuit LGC and a circuit OPC. Note that the circuit OPC included in the memory circuit RESD1 has a different configuration from the circuit OPC shown in FIG. 6A and FIG. 6B.
  • the circuit OPC has a transistor MNC1, a transistor MNC2, a transistor MNH1, and a transistor MNH2.
  • the circuit LGC also has a terminal LI and terminals LO1 to LO4.
  • the first terminal of the transistor MNC1 is electrically connected to the terminal PWC
  • the second terminal of the transistor MNC1 is electrically connected to the first terminal of the transistor MNC2 and the terminal GT
  • the gate of the transistor MNC1 is electrically connected to the terminal LO1.
  • the second terminal of the transistor MNC2 is electrically connected to the wiring VSE22
  • the gate of the transistor MNC2 is electrically connected to the terminal LO2.
  • the first terminal of the transistor MNH1 is electrically connected to the terminal CLK5
  • the second terminal of the transistor MNH1 is electrically connected to the first terminal of the transistor MNH2 and the terminal OT
  • the gate of the transistor MNH1 is electrically connected to the terminal LO3.
  • the second terminal of the transistor MNH2 is electrically connected to the wiring VSE21, and the gate of the transistor MNH2 is electrically connected to the terminal LO4.
  • the circuit LGC of the memory circuit RESD1 in FIG. 11A like the circuit LGC of the memory circuit RESA in FIG. 6A, has the function of ideally outputting a high-level potential from terminal LO1 and outputting a low-level potential from terminal LO2 when a low-level potential is input to terminal CLK2 and a high-level potential is input to terminal IT. Also, when a high-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT, the circuit LGC in FIG. 11A ideally has the function of outputting a low-level potential from terminal LO1 and outputting a high-level potential from terminal LO2. Also, when a low-level potential is input to terminal CLK2 and a low-level potential is input to terminal IT, the circuit LGC in FIG. 11A has the function of maintaining the potential of terminal LO1 and maintaining the potential of terminal LO2.
  • the circuit LGC in FIG. 11A may ideally have a function of outputting a high-level potential from the terminal LO3 and a low-level potential from the terminal LO4 when a low-level potential is input to the terminal CLK2 and a high-level potential is input to the terminal IT.
  • the circuit LGC in FIG. 11A may ideally have a function of outputting a low-level potential from the terminal LO3 and a high-level potential from the terminal LO4.
  • the circuit LGC in FIG. 11A may ideally have a function of outputting a low-level potential from the terminal CLK2 and a low-level potential is input to the terminal IT.
  • the terminals LO1 and LO3 may be electrically connected, and the terminals LO2 and LO4 may be electrically connected.
  • the circuit LGC of the memory circuit RESD1 in FIG. 11A can have the same configuration as the circuit LGC of the memory circuit RESA in FIG. 6A.
  • a terminal LO3 may be provided so as to be electrically connected to the second terminal of the transistor MN1 and the first terminal of the transistor MN2
  • a terminal LO4 may be provided so as to be electrically connected to the gate of the transistor MN2, the second terminal of the transistor MN3, the first terminal of the transistor MN4, and the first terminal of the capacitance element C5.
  • terminal CLK2 and terminal PWC are terminals that correspond to the second input terminal of memory circuit RES in FIG. 3, similar to terminal CLK2 and terminal PWC of memory circuit RESA in FIG. 6A.
  • Terminal CLK5 is also a terminal that corresponds to the second input terminal of memory circuit RES in FIG. 3. Therefore, the number of wirings CLS shown in FIG. 3 can be three or more.
  • the terminal OT is, for example, a terminal that corresponds to the first output terminal of the memory circuit RES in FIG. 3, similar to the terminal OT of the memory circuit RESA in FIG. 6A.
  • the terminal GT is, for example, a terminal that corresponds to the second output terminal of the memory circuit RES in FIG. 3, similar to the terminal GT of the memory circuit RESA in FIG. 6A.
  • each of the wirings VSE21 and VSE22 functions as a wiring that applies a fixed potential.
  • the fixed potential can be, for example, a low-level potential.
  • the wirings VSE21 and VSE22 may be given the same fixed potential or different fixed potentials. Note that when the wirings VSE21 and VSE22 are given the same fixed potential, the wirings VSE1 and VSE2 may be the same wiring.
  • a start pulse signal from the wiring SP or a signal from the terminal OT of the previous memory circuit RESD1 is input to the terminal IT of the memory circuit RESD1.
  • the high potential side of these signals is a high-level potential VH
  • the low potential side is a low-level potential VL .
  • the voltage amplitude of these signals at this time is VH - VL .
  • a clock signal is input to each of the terminals CLK2 and CLK5 of the memory circuit RESD1.
  • the high potential side of each clock signal is a high-level potential VH
  • the low potential side is a low-level potential VL .
  • the potential difference between the high potential side and the low potential side of the clock signal is VH - VL .
  • the wirings VSE21 and VSE22 function as wirings that apply a low-level potential VL to the memory circuit RESD1.
  • a clock signal is applied to a terminal PWC of the memory circuit RESD1.
  • the potential difference between the high potential side and the low potential side of the clock signal applied to the terminal PWC is higher than the potential difference VH - VL between the high potential side and the low potential side of the clock signal applied to the terminals CLK2 and CLK5.
  • the high potential side of the clock signal applied to the terminal PWC may be VEXH , which is higher than VH , and the low potential side may be VL , and the potential difference between the high potential side and the low potential side of the clock signal may be VEXH - VL .
  • the high potential side of the clock signal applied to the terminal PWC will be VEXH
  • the low potential side will be VL .
  • the terminal GT of the memory circuit RESD1 outputs a potential obtained by subtracting the threshold voltage of the transistor MNC1 from VEXH . Furthermore, when the high-potential side VEXH of the clock signal transitions to the low-potential side VL at the terminal PWC thereafter, VL is output from the terminal GT of the memory circuit RESD1.
  • the transistor MNC1 is in an off state and the transistor MNC2 is in an on state, so that the terminal GT of the memory circuit RESD1 outputs VL .
  • V EXH which is higher than V H , may be output from the terminal GT of the memory circuit RESD1
  • transistors with high voltage resistance for the transistors MNC1 and MNC2.
  • transistor MTCK having a thick gate insulating film described in Embodiment 1 for the transistors MNC1 and MNC2.
  • the terminal OT of the memory circuit RESD1 outputs a potential obtained by subtracting the threshold voltage of the transistor MNH1 from VH . Note that thereafter, when the high-potential VH of the clock signal at the terminal CLK5 transitions to the low-potential VL , VL is output from the terminal OT of the memory circuit RESD1.
  • the transistor MNH1 is turned off and the transistor MNH2 is turned on, so that the terminal OT of the memory circuit RESD1 outputs VL .
  • VH may be output as a high-level potential from the terminal OT of the memory circuit RESD1. Because VH is a lower potential than VEXH , transistors having lower tolerance to voltage than the transistor MTCK can be used for the transistors MNH1 and MNH2. Since the shift register SR including the memory circuit RESD1 preferably has a high driving speed, it is preferable to use transistors having a high driving frequency for the transistors MNH1 and MNH2. In other words, it is preferable to use the transistor MTHN having a thin gate insulating film described in Embodiment 1 for the transistors MNH1 and MNH2.
  • the transistor MTHN having a thin gate insulating film may be applied to the transistor included in the circuit LGC of the memory circuit RESD1. This can increase the operating speed of the circuit LGC.
  • the high potential side of the signal output from the second output terminal of the memory circuit RES can be set to VEXH higher than VH .
  • VEXH is input to the enable input terminals of the multiple first latch circuits LA included in the holding circuit LTC1 of Fig. 3.
  • a signal voltage (potential difference between the high potential and low potential of the signal) VEXH -VL higher than VH -VL is input to the enable input terminal, making it easier for the first latch circuit to capture the image signal transmitted from the wiring VIS.
  • the configuration of the memory circuit RES in the semiconductor device of one embodiment of the present invention is not limited to the memory circuit RESD1 in FIG. 11A.
  • the configuration of the memory circuit RES in the semiconductor device of one embodiment of the present invention may be a configuration obtained by changing the memory circuit RESD1 in FIG. 11A depending on the situation.
  • the memory circuit RESD2 shown in FIG. 11B is a modified example of the memory circuit RESD1 in FIG. 11A and differs from the memory circuit RESD1 in that the transistors MNH1 and MNH2 are not provided and that the terminal OT is electrically connected to the terminal GT.
  • the circuit OPC has a transistor MNC1 and a transistor MNC2.
  • the circuit LGC also has terminals LI, LO1, and LO2.
  • the first terminal of transistor MNC1 is electrically connected to terminal PWC
  • the second terminal of transistor MNC1 is electrically connected to the first terminal of transistor MNC2, terminal GT, and terminal OT
  • the gate of transistor MNC1 is electrically connected to terminal LO1.
  • the second terminal of transistor MNC2 is electrically connected to wiring VSE22
  • the gate of transistor MNC2 is electrically connected to terminal LO2.
  • the circuit LGC of the memory circuit RESD2 in FIG. 11B like the circuit LGC of the memory circuit RESA in FIG. 6A, has the function of ideally outputting a high-level potential from terminal LO1 and outputting a low-level potential from terminal LO2 when a low-level potential is input to terminal CLK2 and a high-level potential is input to terminal IT.
  • the circuit LGC in FIG. 11A ideally has the function of outputting a low-level potential from terminal LO1 and outputting a high-level potential from terminal LO2.
  • the circuit LGC in FIG. 11A has the function of maintaining the potential of terminal LO1 and maintaining the potential of terminal LO2.
  • a clock signal having a potential difference between the high potential side and the low potential side of VEXH - VL is applied to the terminal PWC, similarly to the memory circuit RESD1 in FIG. 11A.
  • the wiring VSE22 functions as a wiring that applies a low-level potential VL to the memory circuit RESD2.
  • the high potential side of the signal output from the terminal GT is VEXH
  • the low potential side is VL
  • the high potential side of the signal output from the terminal OT is also VEXH
  • the low potential side is VL .
  • the high potential side of the signal outputted not only from the second output terminal but also from the first output terminal of the memory circuit RES can be set to VEXH, which is higher than VH .
  • VEXH which is higher than VH .
  • a signal whose high potential side is VEXH and whose low potential side is VL can be transmitted to the first input terminal of the next-stage memory circuit, which is electrically connected to the first output terminal of the memory circuit RES.
  • the memory circuit RESD3 shown in FIG. 12A is a modified example of the memory circuit RESD1 in FIG. 11A, and differs from the memory circuit RESD1 in that a transistor MNC3, a transistor MNH3, a capacitance element CPW, and a capacitance element CCL are newly provided, and in that the terminals LO3 and LO4 are not provided in the circuit LGC.
  • the circuit OPC has a transistor MNC1, a transistor MNC2, a transistor MNC3, a transistor MNH1, a transistor MNH2, a transistor MNH3, a capacitance element CPW, and a capacitance element CCL.
  • the first terminal of the transistor MNC3 is electrically connected to the first terminal of the transistor MNH3 and the terminal LO1.
  • the gate of the transistor MNC2 is electrically connected to the gate of the transistor MNH2 and the terminal LO2.
  • the second terminal of the transistor MNC3 is electrically connected to the gate of the transistor MNC1 and the first terminal of the capacitance element CPW, and the gate of the transistor MNC3 is electrically connected to the wiring VDE12.
  • the first terminal of the transistor MNC1 is electrically connected to the terminal PWC
  • the second terminal of the transistor MNC1 is electrically connected to the first terminal of the transistor MNC2, the second terminal of the capacitance element CPW, and the terminal GT.
  • the second terminal of the transistor MNC2 is electrically connected to the wiring VSE22.
  • the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1 and the first terminal of the capacitance element CCL, and the gate of the transistor MNH3 is electrically connected to the wiring VDE11.
  • the first terminal of the transistor MNH1 is electrically connected to the terminal CLK5, and the second terminal of the transistor MNH1 is electrically connected to the first terminal of the transistor MNH2, the second terminal of the capacitance element CCL, and the terminal OT.
  • the second terminal of the transistor MNH2 is electrically connected to the wiring VSE21.
  • circuit LGC in FIG. 12A please refer to the explanation of the circuit LGC in FIG. 11B.
  • terminal CLK5 and the terminal PWC shown in FIG. 12A the description of the terminal CLK5 and the terminal PWC of the memory circuit RESD2 in FIG. 11B can be referred to.
  • the wiring VDE11 and the wiring VDE12 function as wirings that apply a fixed potential.
  • the fixed potential can be, for example, a high-level potential.
  • the wirings VDE11 and VDE12 may be applied with the same fixed potential or different fixed potentials.
  • the wirings VDE11 and VDE12 may be the same wiring.
  • the wirings VDE11 and VDE12 are each a wiring that applies VH as a high-level potential.
  • the transistor MNC2 is turned off and the potential of the terminal GT remains at VL .
  • the potential of the second terminal (terminal GT) of the transistor MNC1 rises from VL .
  • the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW are in a floating state, so that the potential of the second terminal (terminal GT) of the capacitance element CPW rises, and the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW also rise due to the capacitive coupling of the capacitance element CPW.
  • the potential of the gate of transistor MNC3 can be increased by utilizing the capacitive coupling of capacitance element CPW.
  • the term “bootstrap” refers to using capacitive coupling to increase the gate potential in conjunction with an increase in the potential of the first or second terminal of the transistor.
  • the circuit OPC can be configured without providing the capacitance element CPW. In this case, the circuit area of the circuit OPC can be reduced.
  • a high-level potential VH on the high potential side of the signal flowing from the terminal CLK5 can be output to the terminal OT by bootstrap using the capacitor CCL.
  • a voltage VEXH higher than VH may be applied to the potential VH-Vth_MNC3 of the second terminal of the transistor MNC3 by bootstrap using the capacitance element CPW. Therefore, it is preferable to use a transistor with high voltage resistance for the transistor MNC3. In other words, it is preferable to use the transistor MTCK having a thick gate insulating film described in the first embodiment for the transistor MNC3.
  • the shift register SR including the memory circuit RESD3 has a high driving speed
  • the transistor MNH3 a voltage higher than VH may be applied to the second terminal of the transistor MNH3 by bootstrap using the capacitance element CCL. For this reason, a transistor having high resistance to voltage may be used as the transistor MNH3. In other words, the transistor MTCK having a thick gate insulating film described in the first embodiment may be used as the transistor MNH3.
  • transistors MNH1, MNH2, MNC1, and MNC2 please refer to the respective descriptions of transistors MNH1, MNH2, MNC1, and MNC2 provided in memory circuit RESD1 in FIG. 11.
  • the memory circuit RESD3 in FIG. 12A may be changed to the configuration of the memory circuit RESD4 shown in FIG. 12B.
  • the memory circuit RESD4 in FIG. 12B has a configuration in which the transistors MNH3 and MNC3 in the circuit OPC of the memory circuit RESD3 in FIG. 12A are combined into the transistor MNH3.
  • the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitance element CCL, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW.
  • the memory circuit RESD4 in FIG. 12B can increase the gate potential of the transistor MNC1 by bootstrap using the capacitance element CPW, and can increase the gate potential of the transistor MNH1 by bootstrap using the capacitance element CCL.
  • the memory circuit RESD3 in FIG. 12A may be changed to the configuration of the memory circuit RESD5 shown in FIG. 13.
  • the memory circuit RESD5 shown in FIG. 13 has a configuration in which the terminals OT and GT of the memory circuit RESD3 in FIG. 12A are combined together.
  • the transistors MNH1 to MNH3 and the capacitance element CCL are not provided, and the terminal OT is electrically connected to the terminal GT, the second terminal of the transistor MNC1, the second terminal of the capacitance element CPW, and the first terminal of the transistor MNC2.
  • the memory circuit RESD5 in Fig. 13 can increase the potential of the gate of the transistor MNC1 by bootstrap using a capacitance element CPW. Similarly to the memory circuit RESD2 in Fig. 11B, the memory circuit RESD5 in Fig. 13 can set the high potential side of the signal output from the terminal OT to VEXH higher than the high-level potential VH , and set the low potential side to VL .
  • the memory circuit RESD6 shown in FIG. 14A is a modified example of the memory circuit RESD3 in FIG. 12A, and differs from the memory circuit RESD3 in that the gate of the transistor MNC3 is electrically connected to the first terminal of the transistor MNC3 rather than the wiring VDE12, and that the gate of the transistor MNH3 is electrically connected to the first terminal of the transistor MNH3 rather than the wiring VDE11.
  • the transistor MNC3 since the first terminal of the transistor MNC3 and the gate of the transistor MNC3 are electrically connected, the transistor MNC3 can be said to be diode-connected. Therefore, for example, when a high-level potential VH is input from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3, the potentials of the first terminal and gate of the transistor MNC3 become the high-level potential VH , and the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC3, and the first terminal of the capacitance element CPW become VH - Vth_MNC3 .
  • transistor MNC3 When the potential of the second terminal of transistor MNC3 reaches VH - Vth_MNC3 , transistor MNC3 is turned off, and the electrical connection point between the second terminal of transistor MNC3, the gate of transistor MNC1, and the first terminal of capacitance element CPW is in a floating state. Therefore, the potential VH - Vth_MNC3 of the gate of transistor MNC1 can be further increased by bootstrap using capacitance element CPW. Note that even if the potential of the gate of transistor MNC1 (the potential of the second terminal of transistor MNC3) increases, transistor MNC3 does not turn on.
  • the first terminal of the transistor MNH3 and the gate of the transistor MNH3 are electrically connected, so that the transistor MNH3 is diode-connected. For this reason, for example, when a high-level potential VH is input from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNH3, the potentials of the first terminal and gate of the transistor MNH3 become the high-level potential VH , so that the potentials of the second terminal of the transistor MNH3, the gate of the transistor MNH3, and the first terminal of the capacitor CCL become VH - Vth_MNH3 .
  • transistor MNH3 When the potential of the second terminal of transistor MNH3 reaches VH - Vth_MNH3 , transistor MNH3 is turned off, and the electrical connection point between the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitance element CCL is in a floating state. Therefore, the potential VH - Vth_MNC3 of the gate of transistor MNH1 can be further increased by bootstrap using capacitance element CCL. Note that even if the potential of the gate of transistor MNH1 (the potential of the second terminal of transistor MNH3) becomes high, transistor MNH3 does not turn on.
  • the circuit OPC of the memory circuit RESD6A shown in FIG. 14B is a modified example of the circuit OPC of the memory circuit RESD6 in FIG. 14A, and differs from the circuit OPC of the memory circuit RESD6 in FIG. 14A in that it is configured to be capable of releasing the charge stored in the first terminal of the capacitance element CPW (or the gate of transistor MNC1) and the first terminal of the capacitance element CCL (or the gate of transistor MNH1).
  • the circuit OPC of the memory circuit RESD6A shown in FIG. 14B differs from the circuit OPC of the memory circuit RESD6 in FIG. 14A in that it has transistors MNC4 and MNH4.
  • the first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNC3, the gate of transistor MNC1, and the first terminal of capacitance element CPW, the second terminal of transistor MNC4 is electrically connected to wiring VSE23, and the gate of transistor MNC4 is electrically connected to wiring RS1.
  • the first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitance element CCL, the second terminal of transistor MNH4 is electrically connected to wiring VSE24, and the gate of transistor MNH4 is electrically connected to wiring RS2.
  • Wiring VSE23 and wiring VSE24 function as wirings that provide a fixed potential, for example, similar to wiring VSE21 or wiring VSE22.
  • An example of a fixed potential is a low-level potential.
  • Another example of a fixed potential is a ground potential or a negative potential.
  • wiring VSE23 and wiring VSE24 may function as wirings that provide a variable potential.
  • the wirings VSE23 and VSE24 function as wirings for applying a low-level potential VL .
  • the wiring RS1 functions as, for example, a wiring that transmits a signal for selecting whether or not to release the charge accumulated in the first terminal of the capacitor CCL (or the gate of the transistor MNH1). Specifically, for example, when the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNH1) is not to be released, a low-level potential VL may be applied as a signal to the wiring RS1 to turn off the transistor MNH4. Also, for example, when the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNH1) is to be released, a high-level potential VH may be applied as a signal to the wiring RS1 to turn on the transistor MNH4.
  • a low-level potential VL can be applied to the wiring RS1 to turn off the transistor MNH3, and then a high-level potential VH can be applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNH3.
  • a low-level potential VL can be applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNH3 to turn off the transistor MNH3, and then a high-level potential VH can be applied to the wiring RS1 to turn on the transistor MNH4.
  • the potential applied by the wiring VSE23 is set to a low-level potential VL
  • the charge of the first terminal of the capacitor CCL flows to the wiring VSE23, and as a result, the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) becomes VL .
  • the wiring RS2 functions as a wiring that transmits a signal for selecting whether or not to release the charge stored in the first terminal of the capacitance element CPW (the gate of the transistor MNC1). Specifically, for example, when the charge of the first terminal of the capacitance element CPW (or the gate of the transistor MNC1) is not to be released, a low-level potential VL may be applied as a signal to the wiring RS2 to turn off the transistor MNC4. Furthermore, for example, when the charge of the first terminal of the capacitance element CPW (or the gate of the transistor MNC1) is to be released, a high-level potential VH may be applied as a signal to the wiring RS2 to turn on the transistor MNC4.
  • a low-level potential VL can be applied to the wiring RS2 to turn off the transistor MNC3, and then a high-level potential VH can be applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3.
  • a low-level potential VL can be applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3 to turn off the transistor MNC3, and then a high-level potential VH can be applied to the wiring RS2 to turn on the transistor MNC4.
  • the potential applied by the wiring VSE24 is set to a low-level potential VL
  • the charge of the first terminal of the capacitance element CCL (the charge of the gate of the transistor MNC1) flows to the wiring VSE24, and as a result, the potential of the first terminal of the capacitance element CPW (the potential of the gate of the transistor MNC1) becomes VL .
  • the transistor MTCK described in the first embodiment above can be applied to the transistor MNC4.
  • the transistor MTHN described in the first embodiment above can be applied to the transistor MNH4.
  • the transistor MTHN described in the first embodiment above can be applied to the transistor MNC4, and for example, the transistor MTCK described in the first embodiment above can be applied to the transistor MNH4.
  • the memory circuit RESD6 in FIG. 14A may be changed to the configuration of the memory circuit RESD7 shown in FIG. 15A.
  • the memory circuit RESD7 in FIG. 15A has a configuration in which the transistors MNH3 and MNC3 in the circuit OPC of the memory circuit RESD6 in FIG. 14A are combined into the transistor MNH3, similar to the memory circuit RESD4 in FIG. 12B.
  • the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitance element CCL, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW.
  • the memory circuit RESD7 in Fig. 15A has a transistor MNH3 diode-connected, and can supply VH- Vth_MNH3 , which is a potential obtained by subtracting the threshold voltage of the transistor MNC1 from the high-level potential output from the terminal LO1 of the circuit LGC, to the gates of the transistors MNH1 and MNC1 .
  • the memory circuit RESD7 in Fig. 15A can increase the potential of the gate of the transistor MNC1 by bootstrap using the capacitance element CPW, and can increase the potential of the gate of the transistor MNH1 by bootstrap using the capacitance element CCL.
  • the circuit OPC of the memory circuit RESD7A shown in FIG. 15B is a modified example of the circuit OPC of the memory circuit RESD7 of FIG. 15A, and differs from the circuit OPC of the memory circuit RESD7 of FIG. 15A in that it is configured to be capable of releasing the charge stored in the first terminal of the capacitance element CPW (or the gate of transistor MNC1) and the first terminal of the capacitance element CCL (or the gate of transistor MNH1).
  • the circuit OPC of the memory circuit RESD7A shown in FIG. 15B differs from the circuit OPC of the memory circuit RESD7 of FIG. 15A in that it has a transistor MNH4.
  • the first terminal of transistor MNH4 is electrically connected to the gate of transistor MNC1, the first terminal of capacitance element CPW, the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitance element CCL, the second terminal of transistor MNH4 is electrically connected to wiring VSE23, and the gate of transistor MNH4 is electrically connected to wiring RS1.
  • wiring RS1 and wiring VSE23 For details about wiring RS1 and wiring VSE23, please refer to the explanation of wiring RS1 and wiring VSE23 shown in Figure 14B.
  • the memory circuit RESD6 in FIG. 14A may be changed to the configuration of the memory circuit RESD8A shown in FIG. 16.
  • the memory circuit RESD8A shown in FIG. 16 is configured by combining the terminals OT and GT of the memory circuit RESD6A in FIG. 14B.
  • the transistors MNH1 to MNH4 and the capacitance element CCL are not provided, and the terminal OT is electrically connected to the terminal GT, the second terminal of the transistor MNC1, the second terminal of the capacitance element CPW, and the first terminal of the transistor MNC2.
  • the memory circuit RESD8A in Fig. 16 can increase the potential of the gate of the transistor MNC1 by bootstrap using the capacitance element CPW. Similarly to the memory circuit RESD5 in Fig. 13, the memory circuit RESD8A in Fig. 16 can set the high potential side of the signal output from the terminal OT to VEXH higher than the high-level potential VH , and the low potential side to VL .
  • the memory circuit RESD9 shown in FIG. 17A is a modified example of the memory circuit RESD3 in FIG. 12A, and differs from the memory circuit RESD3 in that the gate of the transistor MNC3 is electrically connected to the terminal LO1 of the circuit LGC instead of the wiring VDE12, the first terminal of the transistor MNC3 is electrically connected to the wiring VDE14, the gate of the transistor MNH3 is electrically connected to the terminal LO1 of the circuit LGC instead of the wiring VDE11, and the first terminal of the transistor MNH3 is electrically connected to the wiring VDE13.
  • the wiring VDE13 and the wiring VDE14 function as wirings that apply a fixed potential.
  • the fixed potential can be, for example, a high-level potential.
  • the wirings VDE13 and VDE14 may be applied with the same fixed potential or different fixed potentials.
  • the wirings VDE13 and VDE14 may be the same wiring.
  • the wirings VDE13 and VDE14 are each a wiring that applies VH as a high-level potential.
  • the gate-source voltage of the transistor MNH3 (at this timing, the voltage between the gate and the second terminal) becomes VH - VL , so that the transistor MNH3 is turned on.
  • a current flows from the wiring VDE13 through the transistor MNH3 to the first terminal of the capacitance element CCL (or the gate of the transistor MNH1), and the first terminal of the capacitance element CCL is accumulated, so that the potential of the first terminal of the capacitance element CCL (the potential of the gate of the transistor MNH1) rises until the transistor MNH3 is turned off.
  • the transistor MNH3 is turned off when the gate-source voltage of the transistor MNH3 decreases to Vth_MNH3 , so that the potential of the first terminal of the capacitance element CCL1 (the potential of the second terminal of the transistor MNH3) at this time becomes VH - Vth_MNH3 .
  • the gate-source voltage of the transistor MNC3 (at this timing, the voltage between the gate and the second terminal) becomes VH - VL , and the transistor MNC3 becomes on.
  • a current flows from the wiring VDE14 through the transistor MNC3 to the first terminal of the capacitance element CPW (or the gate of the transistor MNC1), and the first terminal of the capacitance element CPW is accumulated, and the potential of the first terminal of the capacitance element CPW (the potential of the gate of the transistor MNC1) rises until the transistor MNC3 becomes off.
  • the transistor MNC3 becomes off when the gate-source voltage of the transistor MNC3 becomes low to Vth_MNC3 , and the potential of the first terminal of the capacitance element CPW1 (the potential of the second terminal of the transistor MNC3) at this time becomes VH - Vth_MNC3 .
  • the transistor MNH3 when the potential of the second terminal of the transistor MNH3 reaches VH - Vth_MNH3 , the transistor MNH3 is turned off, and therefore the electrical connection point between the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitor CCL is turned on. After that, a low-level potential VL is applied from the terminal LO1 of the circuit LGC to each of the gates of the transistor MNH3.
  • VH from the terminal CLK5 to the first terminal of the transistor MNH1
  • the potential VH - Vth_MNH3 of the gate of the transistor MNH1 can be further increased by bootstrap using the capacitor CCL. Note that even if the potential of the gate of the transistor MNH1 (the potential of the second terminal of the transistor MNH3) becomes high, the transistor MNH3 does not turn on.
  • the circuit OPC of the memory circuit RESD9A shown in FIG. 17B is a modified example of the circuit OPC of the memory circuit RESD9 of FIG. 17A, and differs from the circuit OPC of the memory circuit RESD9 of FIG. 17A in that it is configured to be able to release the charge stored in the first terminal of the capacitance element CPW (or the gate of transistor MNC1) and to be able to release the charge stored in the first terminal of the capacitance element CCL (or the gate of transistor MNH1).
  • the circuit OPC of the memory circuit RESD9A shown in FIG. 17B differs from the circuit OPC of the memory circuit RESD9 of FIG. 17A in that it has transistors MNC4 and MNH4.
  • the first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNC3, the gate of transistor MNC1, and the first terminal of capacitance element CPW, the second terminal of transistor MNC4 is electrically connected to wiring VSE23, and the gate of transistor MNC4 is electrically connected to wiring RS1.
  • the first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitance element CCL, the second terminal of transistor MNH4 is electrically connected to wiring VSE24, and the gate of transistor MNH4 is electrically connected to wiring RS2.
  • wiring VSE23 and wiring VSE24 the description of wiring VSE23 and wiring VSE24 of the memory circuit RESD6A in FIG. 14B can be referred to.
  • wiring RS1 and wiring RS2 the description of wiring RS1 and wiring RS2 of the memory circuit RESD6A in FIG. 14B can be referred to.
  • transistors MNH4 and MNC4 the description of transistors MNH4 and MNC4 of the memory circuit RESD6A in FIG. 14B can be referred to.
  • a low-level potential VL is applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNH3 to turn off the transistor MNH3, and then a high-level potential VH is applied to the wiring RS1 to turn on the transistor MNH4.
  • the potential applied by the wiring VSE23 is set to the low-level potential VL , the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNH1) flows to the wiring VSE23, and as a result, the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) becomes VL .
  • the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) is to be lowered (when the potential is to be VL )
  • a low-level potential VL is applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3 to turn off the transistor MNC3
  • a high-level potential VH is applied to the wiring RS2 to turn on the transistor MNC4.
  • the potential applied by the wiring VSE24 is set to the low-level potential VL , the charge of the first terminal of the capacitor CCL (the charge of the gate of the transistor MNC1) flows to the wiring VSE24, and as a result, the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) becomes VL .
  • the memory circuit RESD9 in FIG. 16 may be changed to the configuration of the memory circuit RESD10 shown in FIG. 18A.
  • the memory circuit RESD10 in FIG. 18A has a configuration in which the transistors MNH3 and MNC3 in the circuit OPC of the memory circuit RESD9 in FIG. 14A are combined into the transistor MNH3, similar to the memory circuit RESD4 in FIG. 12B and the memory circuit RESD7 in FIG. 15A.
  • the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitance element CCL, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW.
  • the memory circuit RESD10 in Fig. 18A has a configuration in which the terminal LO1 of the circuit LGC is electrically connected to the gate of the transistor MNH3, and VH - Vth_MNH3 , which is a potential obtained by subtracting the threshold voltage of the transistor MNH3 from the wiring VDE13, can be applied to the gates of the transistors MNH1 and MNC1.
  • the potential of the gate of the transistor MNC1 can be increased by bootstrap using the capacitor CPW
  • the potential of the gate of the transistor MNH1 can be increased by bootstrap using the capacitor CCL.
  • the circuit OPC of the memory circuit RESD10A shown in FIG. 18B is a modified example of the circuit OPC of the memory circuit RESD10 of FIG. 18A, and differs from the circuit OPC of the memory circuit RESD10 of FIG. 18A in that it is configured to be capable of releasing the charge stored in the first terminal of the capacitance element CPW (or the gate of transistor MNC1) and the first terminal of the capacitance element CCL (or the gate of transistor MNH1).
  • the circuit OPC of the memory circuit RESD10A shown in FIG. 18B differs from the circuit OPC of the memory circuit RESD10 of FIG. 18A in that it has a transistor MNH4.
  • the first terminal of transistor MNH4 is electrically connected to the gate of transistor MNC1, the first terminal of capacitance element CPW, the second terminal of transistor MNH3, the gate of transistor MNH1, and the first terminal of capacitance element CCL, the second terminal of transistor MNH4 is electrically connected to wiring VSE23, and the gate of transistor MNH4 is electrically connected to wiring RS1.
  • wiring RS1 and wiring VSE23 For details about wiring RS1 and wiring VSE23, please refer to the explanation of wiring RS1 and wiring VSE23 shown in Figure 17B.
  • the memory circuit RESD9 in FIG. 17A may be changed to the configuration of the memory circuit RESD11 shown in FIG. 19A.
  • the memory circuit RESD11 shown in FIG. 19 is configured by combining the terminals OT and GT of the memory circuit RESD9 in FIG. 17A.
  • the transistors MNH1 to MNH4 and the capacitance element CCL are not provided, and the terminal OT is electrically connected to the terminal GT, the second terminal of the transistor MNC1, the second terminal of the capacitance element CPW, and the first terminal of the transistor MNC2.
  • the memory circuit RESD11 in Fig. 19A can increase the gate potential of the transistor MNC1 by bootstrap using a capacitor CPW. Also, the memory circuit RESD11 in Fig. 19A can set the high potential side of the signal output from the terminal OT to VEXH higher than the high-level potential VH and the low potential side to VL , similar to the memory circuit RESD5 in Fig. 13 and the memory circuit RESD8A in Fig. 16.
  • the memory circuit RESD11 in FIG. 19A may be modified to a configuration capable of releasing the charge stored in the first terminal of the capacitance element CPW (or the gate of the transistor MNC1).
  • a transistor MNC4 may be provided in the circuit OPC as in the memory circuit RESD11A in FIG. 19B. Note that for an example of the operation of the memory circuit RESD11A in FIG. 19B, the description of the example of the operation of the memory circuit RESD9A in FIG. 17B can be referred to.
  • ⁇ Configuration Example 11 of Memory Circuit RES>> 20A is a modification of the memory circuit RESD3 in FIG 12A and differs from the memory circuit RESD3 in that a transistor MNF1 is provided. That is, in the memory circuit RESD12 in FIG 20A, the circuit OPC includes a transistor MNF1 in addition to the transistors MNH1 to MNH3, the transistors MNC1 to MNC3, the capacitor CCL, and the capacitor CPW.
  • connection configuration of the circuit OPC of the memory circuit RESD12 in FIG. 20A is the same as the connection configuration of the memory circuit RESD3 in FIG. 12A, in addition to that, the first terminal of the transistor MNF1 is electrically connected to the terminal LO1 of the circuit LGC, the first terminal of the transistor MNH3, and the first terminal of the transistor MNC3, the second terminal of the transistor MNF1 is electrically connected to the wiring VDE15, and the gate of the transistor MNF1 is electrically connected to the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW.
  • the wiring VDE15 functions as a wiring that applies a fixed potential.
  • the fixed potential can be, for example, a high-level potential.
  • the fixed potential of the wiring VDE15 may be equal to or different from the fixed potentials applied by the wirings VDE11 and VDE12.
  • the wiring VDE15 may be equal to two of the fixed potentials applied by the wirings VDE11 and VDE12.
  • the wirings VDE11, VDE12, and VDE15 may be the same wiring.
  • the wirings VDE11, VDE12, and VDE15 are each a wiring that applies VH as a high-level potential.
  • circuit LGC For the circuit LGC, please refer to the description of the circuit LGC in the memory circuit RESD3 in FIG. 12A.
  • the description of the terminal PWC, the wiring VSE21, and the wiring VSE22 in the memory circuit RESD3 in FIG. 12A can be referred to.
  • the transistors MNH2 and MNC2 are each turned off, and the potential of the terminal OT and the potential of the terminal GT remain at VL .
  • the potential of the gate of the transistor MNF1 is VH - Vth_MNC3 .
  • the potential of the first terminal of the transistor MNF1 is VH provided from the terminal LO1
  • the potential of the second terminal of the transistor MNF1 is VH provided from the wiring VDE15. Therefore, if the threshold voltage of the transistor MNF1 is an appropriate value, the transistor MNF1 is turned off.
  • VMF1 is preferably a potential lower than VH and extremely close to VH .
  • the circuit LGC can be a circuit that can be temporarily stopped in some cases.
  • the potential of the second terminal of the transistor MNH1 rises from VL .
  • the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitance element CCL are in a floating state, so that the potentials of the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitance element CCL rise due to bootstrap by the capacitance element CCL.
  • the circuit OPC of the memory circuit RESD12 in FIG. 20A can output to the terminal OT a signal whose high potential side is VH and whose low potential side is VL .
  • the potential of the second terminal of the transistor MNC1 rises from VL .
  • the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW are in a floating state, so that the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW rise due to bootstrap by the capacitance element CPW.
  • the potentials of the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW become VH - Vth_MNC3 + ( VEXH - VL ).
  • the potential of the first terminal of the transistor MNF1 is VH (or VMNF1 ) and the potential of the second terminal of the transistor MNF1 is VH. Therefore, if the threshold voltage of the transistor MNF1 has an appropriate value, the transistor MNF1 can be turned on.
  • the 20A can output to the terminal GT a signal whose high potential side is V EXH and whose low potential side is V L. Furthermore, even if noise is input to the circuit OPC in the memory circuit RESD12 in FIG 20A, the signals output from the terminals OT and GT can be stabilized.
  • the shift register SR including the memory circuit RESD12 in FIG. 20A has a high driving speed
  • a transistor with a high driving frequency may be used for the transistor MNF1.
  • the transistor MTHN having a thin gate insulating film described in the first embodiment may be used for the transistor MNF1.
  • transistors MNH1 to MNH3 and the transistors MNC1 to MNC3 refer to the respective descriptions of the transistors MNH1 to MNH3 and the transistors MNC1 to MNC3 provided in the memory circuit RESD3 in FIG. 12.
  • the memory circuit RESD12 in FIG. 20A may be changed to the configuration of the memory circuit RESD12A shown in FIG. 20B.
  • the memory circuit RESD12A shown in FIG. 20B has a configuration in which the terminals OT and GT of the memory circuit RESD12 in FIG. 20A are combined together.
  • the transistors MNH1 to MNH3 and the capacitance element CCL are not provided, and the terminal OT is electrically connected to the terminal GT, the second terminal of the transistor MNC1, the second terminal of the capacitance element CPW, and the first terminal of the transistor MNC2.
  • the memory circuit RESD12A in Fig. 20B can increase the potential of the gate of the transistor MNC1 by bootstrap using a capacitor CPW, similar to the memory circuit RESD5 in Fig. 13, the memory circuit RESD8A in Fig. 16, the memory circuit RESD11 in Fig. 19A, and the memory circuit RESD11A in Fig. 19B.
  • the memory circuit RESD12A in Fig. 20B can set the high potential side of the signal output from the terminal OT to VEXH higher than the high-level potential VH, and the low potential side to VL , similar to the memory circuit RESD5 in Fig. 13, the memory circuit RESD8A in Fig. 16, the memory circuit RESD11 in Fig. 19A, and the memory circuit RESD11A in Fig. 19B.
  • the memory circuit RESD12 in FIG. 20A may be changed to the configuration of a memory circuit RESD12B shown in FIG. 21A.
  • the memory circuit RESD12B shown in FIG. 21A differs from the memory circuit RESD12 in FIG. 20A in that the gate of the transistor MNF1 is electrically connected to the second terminal of the transistor MNH3, the gate of the transistor MNH1, and the first terminal of the capacitance element CCL, rather than to the second terminal of the transistor MNC3, the gate of the transistor MNC1, and the first terminal of the capacitance element CPW.
  • the memory circuit RESD12B shown in FIG. 21A is configured to turn on the transistor MNF1 by increasing the gate potential of the transistor MNF1 through bootstrap of the capacitance element CCL.
  • the gate potential of the transistor MNF1 that rises through bootstrap of the capacitance element CCL is lower than the gate potential of the transistor MNF1 that rises through bootstrap of the capacitance element CPW in the memory circuit RESD12 of FIG. 21A.
  • the transistor MNF1 can be sufficiently turned on by increasing the gate potential of the transistor MNF1 through bootstrap of the capacitance element CCL.
  • the signals output from the terminals OT and GT can be stabilized.
  • the memory circuit RESD12 in FIG. 20A may be changed to the configuration of the memory circuit RESD13 shown in FIG. 21B.
  • the memory circuit RESD13 in FIG. 21B has a configuration in which the transistors MNH3 and MNC3 in the circuit OPC of the memory circuit RESD12 in FIG. 20A are combined into the transistor MNH3.
  • the second terminal of the transistor MNH3 is electrically connected to the gate of the transistor MNH1, the first terminal of the capacitance element CCL, the gate of the transistor MNC1, the first terminal of the capacitance element CPW, and the gate of the transistor MNF1.
  • the memory circuit RESD13 in FIG. 21B can increase the gate potential of the transistor MNC1 by bootstrap using the capacitance element CPW, and can increase the gate potential of the transistor MNH1 by bootstrap using the capacitance element CCL.
  • the memory circuit RESD12 in FIG. 20A may be changed to the configuration of the memory circuit RESD14 shown in FIG. 22A.
  • the memory circuit RESD14 in FIG. 22A differs from the memory circuit RESD12 in that the gate of the transistor MNH3 is electrically connected to the first terminal of the transistor MNH3 instead of the wiring VDE11, and the gate of the transistor MNC3 is electrically connected to the first terminal of the transistor MNC3 instead of the wiring VDE12.
  • the circuit OPC of the memory circuit RESD14A shown in FIG. 22B is a modified example of the circuit OPC of the memory circuit RESD14 of FIG. 22A, and differs from the circuit OPC of the memory circuit RESD14 of FIG. 22A in that it is configured to be capable of releasing the charge stored in the first terminal of the capacitance element CCL (or the gate of transistor MNH1) and the charge stored in the first terminal of the capacitance element CPW (or the gate of transistor MNC1).
  • the circuit OPC of the memory circuit RESD14A shown in FIG. 22B differs from the circuit OPC of the memory circuit RESD14 of FIG. 22A in that it has transistors MNC4 and MNH4.
  • the first terminal of transistor MNH4 is electrically connected to the gate of transistor MNH1, the first terminal of capacitance element CCL, and the second terminal of transistor MNH3, the second terminal of transistor MNH4 is electrically connected to wiring VSE23, and the gate of transistor MNH4 is electrically connected to wiring RS1.
  • the first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNC3, the gate of transistor MNC1, the first terminal of capacitance element CPW, and the gate of transistor MNF1, the second terminal of transistor MNC4 is electrically connected to wiring VSE24, and the gate of transistor MNC4 is electrically connected to wiring RS2.
  • wiring RS1, wiring RS2, wiring VSE23, and wiring VSE24 the description of wiring RS1, wiring RS2, wiring VSE23, and wiring VSE24 of the memory circuit RESD6A shown in FIG. 14B can be referred to. Also, for transistors MNH4 and MNC4, the description of transistors MNH4 and MNC4 of the memory circuit RESD6A shown in FIG. 14B can be referred to.
  • a low-level potential VL can be applied to the wiring RS1 to turn off the transistor MNH4, and then a high-level potential VH can be applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNH3.
  • a low-level potential VL can be applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNH3 to turn off the transistor MNH3, and then a high-level potential VH can be applied to the wiring RS1 to turn on the transistor MNH4.
  • the potential applied by the wiring VSE23 is set to a low-level potential VL
  • the charge of the first terminal of the capacitor CCL flows to the wiring VSE23, and as a result, the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) becomes VL .
  • the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) is to be high (when the potential is to be VH - Vth_MNC3 )
  • a low-level potential VL can be applied to the wiring RS2 to turn off the transistor MNC4, and then a high-level potential VH can be applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3.
  • a low-level potential VL can be applied from the terminal LO1 of the circuit LGC to the first terminal of the transistor MNC3 to turn off the transistor MNC3, and then a high-level potential VH can be applied to the wiring RS2 to turn on the transistor MNC4.
  • the potential applied by the wiring VSE24 is set to a low-level potential VL
  • the charge of the first terminal of the capacitance element CCL (the charge of the gate of the transistor MNC1) flows to the wiring VSE24, and as a result, the potential of the first terminal of the capacitance element CPW (the potential of the gate of the transistor MNC1) becomes VL .
  • the memory circuit RESD12 in FIG. 20A may be changed to the configuration of the memory circuit RESD15 shown in FIG. 23.
  • wiring VDE13 and wiring VDE14 please refer to the description of wiring VDE13 and wiring VDE14 of memory circuit RESD9 in Figure 17A.
  • the circuit OPC of the memory circuit RESD15A shown in FIG. 24 is a modified example of the circuit OPC of the memory circuit RESD15 of FIG. 23, and differs from the circuit OPC of the memory circuit RESD15 of FIG. 23 in that it is configured to be capable of discharging the charge stored in the first terminal of the capacitance element CCL (or the gate of transistor MNH1) and the charge stored in the first terminal of the capacitance element CPW (or the gate of transistor MNC1).
  • the circuit OPC of the memory circuit RESD15A shown in FIG. 24 differs from the circuit OPC of the memory circuit RESD15 of FIG. 23 in that it has transistors MNC4 and MNH4.
  • the first terminal of transistor MNH4 is electrically connected to the gate of transistor MNH1, the first terminal of capacitance element CCL, and the second terminal of transistor MNH3, the second terminal of transistor MNH4 is electrically connected to wiring VSE23, and the gate of transistor MNH4 is electrically connected to wiring RS1.
  • the first terminal of transistor MNC4 is electrically connected to the second terminal of transistor MNC3, the gate of transistor MNC1, the first terminal of capacitance element CPW, and the gate of transistor MNF1, the second terminal of transistor MNC4 is electrically connected to wiring VSE24, and the gate of transistor MNC4 is electrically connected to wiring RS2.
  • wiring RS1, wiring RS2, wiring VSE23, and wiring VSE24 the description of wiring RS1, wiring RS2, wiring VSE23, and wiring VSE24 of the memory circuit RESD9A shown in FIG. 17B can be referred to.
  • a low-level potential VL can be applied to the wiring RS1 to turn off the transistor MNH4, and then a high-level potential VH can be applied from the terminal LO1 of the circuit LGC to the gate of the transistor MNH3.
  • a low-level potential VL can be applied from the terminal LO1 of the circuit LGC to the gate of the transistor MNH3 to turn off the transistor MNH3, and then a high-level potential VH can be applied to the wiring RS1 to turn on the transistor MNH4.
  • the potential applied by the wiring VSE23 is set to a low-level potential VL
  • the charge of the first terminal of the capacitor CCL flows to the wiring VSE23, and as a result, the potential of the first terminal of the capacitor CCL (the potential of the gate of the transistor MNH1) becomes VL .
  • the potential of the first terminal of the capacitor CPW (the potential of the gate of the transistor MNC1) is to be high (when the potential is to be VH - Vth_MNC3 )
  • a low-level potential VL can be applied to the wiring RS2 to turn off the transistor MNC4, and then a high-level potential VH can be applied from the terminal LO1 of the circuit LGC to the gate of the transistor MNC3.
  • a low-level potential VL can be applied from the terminal LO1 of the circuit LGC to the gate of the transistor MNC3 to turn off the transistor MNC3, and then a high-level potential VH can be applied to the wiring RS2 to turn on the transistor MNC4.
  • the potential applied by the wiring VSE24 is set to a low-level potential VL
  • the charge of the first terminal of the capacitance element CCL (the charge of the gate of the transistor MNC1) flows to the wiring VSE24, and as a result, the potential of the first terminal of the capacitance element CPW (the potential of the gate of the transistor MNC1) becomes VL .
  • Fig. 25A shows an example of a circuit configuration of a level shifter circuit that can be applied to the level shifter circuit LS[1] to the level shifter circuit LS[5] in Fig. 4.
  • the level shifter circuit LSa shown in FIG. 25A is an example of a circuit configuration that can be applied to the level shifter circuit LS in FIG. 4, and includes transistors MN11 to MN13. As shown in FIG. 25A, the level shifter circuit LSa is a unipolar circuit that does not include p-channel transistors and includes n-channel transistors.
  • the level shifter circuit LSa also has a terminal IN1L, a terminal IN2L, and a terminal OUTL.
  • the gate of transistor MN11 is electrically connected to wiring VE1
  • the first terminal of transistor MN11 is electrically connected to terminal IN1L
  • the second terminal of transistor MN11 is electrically connected to the gate of transistor MN12.
  • the first terminal of transistor MN12 is electrically connected to wiring VE2.
  • the gate of transistor MN13 is electrically connected to terminal IN2L
  • the first terminal of transistor MN13 is electrically connected to the second terminal of transistor MN12 and terminal OUTL
  • the second terminal of transistor MN13 is electrically connected to wiring VE3.
  • terminal IN1L corresponds to the input terminal of the level shifter circuit LS in Figure 4.
  • terminal IN2L receives a signal that is the inverted logic of the signal that is input to terminal IN1L. For example, when a low-level potential is input to terminal IN1L, a high-level potential is input to terminal IN2L. Also, for example, when a high-level potential is input to terminal IN1L, a low-level potential is input to terminal IN2L. For this reason, it is preferable to electrically connect, for example, the output terminal of an inverter to terminal IN2L, and electrically connect terminal IN1L to the input terminal of the inverter.
  • the wiring VE1 functions as a wiring that applies a fixed potential.
  • the fixed potential is preferably a potential that is the same as the high-level potential that can be output from the second output terminal of the memory circuit RES.
  • the wiring VE1 may be a wiring that applies a variable potential instead of a fixed potential.
  • the wiring VE2 functions as a wiring that applies a fixed potential.
  • the fixed potential is preferably a potential higher than the high-level potential that can be output from the second output terminal of the memory circuit RES.
  • the fixed potential may also be a potential that is the same height as the low-level potential that can be output from the second output terminal of the memory circuit RES.
  • the wiring VE2 may also be a wiring that applies a variable potential instead of a fixed potential.
  • the wiring VE3 functions as a wiring that applies a fixed potential.
  • the potential is preferably a low-level potential that can be output from the second output terminal of the memory circuit RES, or a ground potential.
  • the wiring VE3 may be a wiring that applies a variable potential instead of a fixed potential.
  • the transistor MN11 has the function of transmitting a signal from the terminal IN1L to the gate of the transistor MN12. For this reason, it is preferable to use a transistor with a high driving frequency for the transistor MN11. In other words, it is preferable to use the transistor MTHN described in the first embodiment for the transistor MN11. Note that if it is desired to increase the voltage tolerance of the transistor MN11, the transistor MTHN may be used for the transistor MN11 instead of the transistor MTCK.
  • the level shifter circuit LSa as described above, a potential higher than the high-level potential that can be output from the second output terminal of the memory circuit RES is applied from the wiring VE2 to the first and second terminals of the transistor MN12 or the first terminal of the transistor MN13. For this reason, it is preferable to use transistors having high resistance to voltage for the transistors MN12 and MN13. In other words, it is preferable to use the transistor MTCK described in the first embodiment for the transistors MN12 and MN13. Note that if it is desired to increase the drive frequency of the transistors MN12 and MN13, the transistors MTHN may be used for the transistors MN12 and MN13 instead of the transistors MTCK.
  • the level shifter circuit LSb1 shown in FIG. 25B is a modified example of the level shifter circuit LSa in FIG. 25A, and differs from the level shifter circuit LSa in that it does not include transistor MN11 and that the gate of transistor MN12 is electrically connected to the first terminal of transistor MN12.
  • the terminal IN2L of the level shifter circuit LSa receives an inverted signal of the signal input to the terminal IN1L
  • the terminal IN2L of the level shifter LSB1 in the level shifter circuit LSb1 receives an inverted signal of the signal output from the second output terminal of the memory circuit RES.
  • the configuration of the level shifter circuit LSb1 can be changed during the circuit design stage.
  • the level shifter circuit LSb2 shown in FIG. 25C may be applied to the level shifter circuit LS included in the amplifier circuit LVS shown in FIG. 3 or 4.
  • the level shifter circuit LSb2 shown in FIG. 25C is a modified example of the level shifter circuit LSb1 in FIG. 25B, and differs from the level shifter circuit LSb1 in that the gate of the transistor MN12 is electrically connected to the second terminal of the transistor MN12, not the first terminal of the transistor MN12.
  • transistor MN12 shown in FIG. 25C is a normally-on transistor.
  • a normally-off OS transistor means that a current per 1 ⁇ m of channel width flowing through the transistor when the gate-source voltage is 0 V is 1 ⁇ 10 ⁇ 20 A or less at room temperature, 1 ⁇ 10 ⁇ 18 A or less at 85° C., or 1 ⁇ 10 ⁇ 16 A or less at 125° C.
  • a normally-on transistor means that a channel exists even when the gate-source voltage is 0 V, and a current flows through the transistor.
  • the level shifter circuit LSb3 shown in FIG. 25D may be applied to the level shifter circuit LS included in the amplifier circuit LVS shown in FIG. 3 or 4.
  • the level shifter circuit LSb3 shown in FIG. 25D is a modified example of the level shifter circuit LSb1 in FIG. 25B, and differs from the level shifter circuit LSb1 in that the transistor MN12 is changed to a resistor R.
  • the first terminal of resistor R is electrically connected to wiring VE2, and the second terminal of resistor R is electrically connected to the first terminal of transistor MN13 and terminal OUTL.
  • the level shifter circuit LSb4 shown in FIG. 25E may be applied to the level shifter circuit LS included in the amplifier circuit LVS shown in FIG. 3 or 4.
  • the level shifter circuit LSb4 shown in FIG. 25E is a modified example of the level shifter circuit LSb1 in FIG. 25B, and differs from the level shifter circuit LSb1 in that the transistor MN12 is changed to a diode DI.
  • the input terminal of the diode is electrically connected to the wiring VE2, and the output terminal of the diode is electrically connected to the first terminal of the transistor MN13 and the terminal OUTL.
  • Fig. 26A shows an example of a circuit configuration of a latch circuit that can be applied to the first latch circuit LA or the second latch circuit LB shown in Fig. 3 or 4.
  • the first latch circuit LA (second latch circuit LB) shown in FIG. 26A has inverters INV1 to INV5, a switch SW1, and a switch SW2.
  • the first latch circuit LA (second latch circuit LB) also has an input terminal D, an output terminal Q, and an enable input terminal E.
  • switch SW1 or switch SW2 for example, an electrical switch such as an analog switch or a mechanical switch may be applied. Also, one of the electrical switches may be an OS transistor.
  • switches SW1 and SW2 shown in FIG. 26A are assumed to be in an on state when a high-level potential is applied to the control terminals, and in an off state when a low-level potential is applied to the control terminals.
  • the input terminal of the inverter INV1 is electrically connected to the input terminal D, and the output terminal of the inverter INV1 is electrically connected to the first terminal of the switch SW1.
  • the input terminal of the inverter INV2 is electrically connected to the input terminal of the inverter INV3, the second terminal of the switch SW1, and the first terminal of the switch SW2, and the output terminal of the inverter INV2 is electrically connected to the output terminal Q.
  • the output terminal of the inverter INV3 is electrically connected to the input terminal of the inverter INV4, and the output terminal of the inverter INV4 is electrically connected to the second terminal of the switch SW2.
  • the input terminal of the inverter INV5 is electrically connected to the enable input terminal E and the control terminal of the switch SW1, and the output terminal of the inverter INV5 is electrically connected to the control terminal of the switch SW2.
  • the switch SW1 when a high-level potential is input to the enable input terminal E, the switch SW1 is in a conductive state and the switch SW2 is in a non-conductive state. Therefore, the signal input to the input terminal D is output to the output terminal Q via the inverters INV1 and INV2. In addition, the signal input to the input terminal D is input to the first terminal of the switch SW2 via the inverters INV1, INV3, and INV4.
  • the switch SW1 becomes non-conductive and the switch SW2 becomes conductive.
  • the inverters INV3 and INV4 can hold the signal previously input to the input terminal D. The signal is then output to the output terminal Q via the inverter INV2.
  • FIG. 26B shows the circuit configuration of an inverter that can be applied to each of the inverters INV1 to INV5.
  • the inverter INV shown in FIG. 26B has transistors MN21 to MN24 and a capacitance element C21.
  • the inverter INV is a unipolar circuit that does not include a p-channel transistor and includes an n-channel transistor.
  • the input terminal of the inverter INV is electrically connected to the gate of the transistor MN21 and the gate of the transistor MN23.
  • the gate of the transistor MN22 is electrically connected to the first terminal of the transistor MN22 and the wiring VE11, and the second terminal of the transistor MN22 is electrically connected to the first terminal of the transistor MN21, the gate of the transistor MN24, and the first terminal of the capacitance element C21.
  • the second terminal of the transistor MN21 is electrically connected to the wiring VE13.
  • the first terminal of the transistor MN24 is electrically connected to the wiring VE12, and the second terminal of the transistor MN24 is electrically connected to the second terminal of the capacitance element C21, the first terminal of the transistor MN23, and the output terminal of the inverter INV.
  • the second terminal of the transistor MN23 is electrically connected to the wiring VE14.
  • the wiring VE11 and the wiring VE12 function as wirings that apply a fixed potential.
  • the fixed potential is preferably a high-level potential.
  • the fixed potentials applied by the wiring VE11 and the wiring VE12 may be equal to each other or may be different from each other.
  • one or both of the wiring VE11 and the wiring VE12 may be wirings that apply a variable potential instead of a fixed potential.
  • wiring VE13 and wiring VE14 function as wirings that apply a fixed potential.
  • the fixed potential is preferably a low-level potential or a ground potential.
  • the fixed potentials applied by wiring VE13 and wiring VE14 may be equal to each other or may be different from each other.
  • one or both of wiring VE11 and wiring VE12 may be wirings that apply a variable potential instead of a fixed potential.
  • transistors MN21 to MN24 function as circuit elements for inverting the logic of the signal from the input terminal of the inverter INV and outputting the signal with the inverted logic to the output terminal of the inverter INV. Therefore, it is preferable that the time it takes from inputting a signal to the input terminal of the inverter INV to outputting the signal from the output terminal of the inverter INV is short. In other words, it is preferable to use transistors with a high drive frequency for transistors MN21 to MN24 provided in the inverter INV. In other words, it is preferable to use transistors MTHN described in embodiment 1 above for transistors MN21 to MN24.
  • transistors MTCK may be used for transistors MN21 to MN24 instead of transistors MTHN.
  • FIG. 26C shows a circuit configuration of a switch that can be applied to each of switches SW1 and SW2.
  • the switch SW shown in FIG. 26C has a transistor MN26, a transistor MN27, and a capacitance element C22.
  • the switch SW is a unipolar circuit that does not include a p-channel transistor and includes an n-channel transistor.
  • the first terminal of the transistor MN26 is electrically connected to the enable input terminal E of the switch SW, the second terminal of the transistor MN26 is electrically connected to the gate of the transistor MN27 and the first terminal of the capacitance element C22, and the gate of the transistor MN26 is electrically connected to the wiring VE15.
  • the first terminal of the transistor MN27 is electrically connected to the first terminal of the switch SW, and the second terminal of the transistor MN27 is electrically connected to the second terminal of the capacitance element C22 and the second terminal of the switch SW2.
  • the wiring VE15 functions as a wiring that applies a fixed potential.
  • the fixed potential is preferably a high-level potential.
  • the fixed potentials applied by each of the wirings VE15 may be equal to each other or may be different from each other.
  • one or both of the wirings VE15 may be wirings that apply a variable potential instead of a fixed potential.
  • the transistor MN27 functions as a circuit element that switches between a conductive state and a non-conductive state between the input terminal and the output terminal of the switch SW. For this reason, it is preferable that the switching speed of the transistor MN27 is fast. For this reason, it is preferable to use a transistor with a high drive frequency for the transistor MN27 provided in the switch SW. In other words, it is preferable to use the transistor MTHN described in the first embodiment for the transistor MN27. Note that if it is desired to increase the voltage resistance of the transistor MN27, the transistor MTCK may be used for the transistor MN27 instead of the transistor MTHN.
  • transistor MN26 If you want to increase the voltage resistance of transistor MN26, you can use transistor MTCK. If you want to increase the drive frequency, you can use transistor MTHN.
  • Fig. 27A shows an example of a circuit configuration of a source follower circuit that can be applied to the source follower circuit SAM[1] to the source follower circuit SAM[5] shown in Fig. 3 or Fig. 4.
  • the source follower circuit SAM shown in FIG. 27A has transistors MN31 to MN38, a capacitance element C1, and a capacitance element C2.
  • the source follower circuit SAM also has a terminal IP and a terminal OP.
  • the first terminal of transistor MN31 is electrically connected to terminal IP
  • the second terminal of transistor MN31 is electrically connected to the first terminal of transistor MN32 and the first terminal of capacitance element C1
  • the gate of transistor MN31 is electrically connected to wiring DR1.
  • the second terminal of capacitance element C1 is electrically connected to wiring VE23.
  • the first terminal of transistor MN35 is electrically connected to wiring SG
  • the second terminal of transistor MN35 is electrically connected to the gate of transistor MN36 and the first terminal of capacitance element C2
  • the gate of transistor MN35 is electrically connected to wiring DR2.
  • the second terminal of transistor MN32 is electrically connected to the first terminal of transistor MN33 and the second terminal of capacitance element C2, and the gate of transistor MN32 is electrically connected to wiring DR3.
  • the first terminal of the transistor MN36 is electrically connected to the wiring VE22, and the second terminal of the transistor MN36 is electrically connected to the second terminal of the transistor MN33, the first terminal of the transistor MN37, and the first terminal of the transistor MN34.
  • the gate of the transistor MN33 is electrically connected to the wiring DR4.
  • the second terminal of the transistor MN37 is electrically connected to the wiring VE24, and the gate of the transistor MN37 is electrically connected to the wiring VBIS.
  • the second terminal of the transistor MN34 is electrically connected to the first terminal of the transistor MN38 and the terminal OP, and the gate of the transistor MN34 is electrically connected to the wiring DR5.
  • the second terminal of the transistor MN38 is electrically connected to the wiring VE25, and the gate of the transistor MN38 is electrically connected to the wiring INIT.
  • the wirings DR1 to DR5 and the wiring INIT function as wirings that transmit signals for controlling the source follower circuit SAM. For this reason, it is preferable that the signals transmitted by the wirings DR1 to DR5 and the wiring INIT have variable potentials.
  • the wiring SG functions as a wiring that applies a fixed potential.
  • the fixed potential is preferably equal to or higher than the low-level potential applied by wirings VE23 to VE25 described later, or equal to or higher than the ground potential, and equal to or lower than the high-level potential applied by wiring VE22.
  • the fixed potential may be a potential outside the above range.
  • the wiring SG may be a wiring that applies a variable potential instead of a fixed potential.
  • the wiring VE22 functions as a wiring that applies a fixed potential.
  • the fixed potential is preferably a high-level potential.
  • the wiring VE22 may be a wiring that applies a variable potential instead of a fixed potential.
  • wirings VE23 to VE25 function as wirings that apply a fixed potential.
  • the fixed potential is preferably a low-level potential or a ground potential.
  • the fixed potentials applied by each of wirings VE23 to VE25 may be equal to each other or may be different from each other.
  • one or more of wirings VE23 to VE25 may be wirings that apply a variable potential instead of a fixed potential.
  • the wiring VBIS functions as a wiring that provides a fixed potential to the gate of the transistor MN37.
  • the wiring VE24 is electrically connected to the second terminal of the transistor MN37, and when the wiring VE24 provides a fixed potential to the second terminal of the transistor MN37, the transistor MN37 functions as a constant current source.
  • the terminal IP corresponds, for example, to the input terminal of the source follower circuit SAM in FIG. 3 or FIG. 4.
  • the terminal OP corresponds, as an example, to the output terminal of the source follower circuit SAM in FIG. 3 or FIG. 4.
  • FIG. 27B is a timing chart showing an example of the operation of the source follower circuit SAM shown in FIG. 27A.
  • the timing chart in FIG. 27B shows the changes in the potential of the wirings DR1 to DR5 and the wiring INIT at and around times T1 to T4. Note that in the timing chart in FIG. 27B, a high-level potential is indicated as "High” and a low-level potential is indicated as “Low.”
  • the wiring VE22 serves as a wiring for applying a high-level potential VDH
  • the wirings VE23 to VE25 serve as wirings for applying a low-level potential VSS
  • the wiring SG serves as a wiring for applying a reference potential VX .
  • initialization is performed in the source follower circuit SAM.
  • the wiring DR1, the wiring DR3, and the wiring DR5 are each at a low level potential
  • the wiring DR2, the wiring DR4, and the wiring INIT are each at a high level potential.
  • the transistors MN31, MN32, and MN34 are turned off. Also, the transistors MN33, MN35, and MN38 are turned on. Because the transistor MN35 is turned on, the first terminal of the capacitance element C2 and the wiring SG are electrically connected, and the potential of the first terminal of the capacitance element C2 becomes the potential VX provided by the wiring SG.
  • the second terminal of the capacitance element C2 and the wiring VE22 are in a conductive state.
  • the potential of the second terminal of the capacitance element C2 rises until the amount of current flowing between the source and drain of the transistor MN36 becomes equal to the amount of current flowing between the source and drain of the transistor MN37. This is because the rise in the potential of the second terminal of the capacitance element C2 reduces the gate-source voltage of the transistor MN36, and the amount of current flowing between the source and drain of the transistor MN36 decreases.
  • the potential of the second terminal of the capacitance element C2 at this time is VY .
  • the amount of current flowing between the source and drain of transistor MN36 can be set to the amount of current flowing between the source and drain of transistor MN37.
  • the potential of wiring DR2 is changed from a high level potential to a low level potential to turn off transistor MN35, thereby maintaining the voltage between the first and second terminals of capacitance element C2 according to the amount of current.
  • an input signal is input to the terminal IP of the source follower circuit SAM.
  • the wiring DR1 and the wiring DR3 are at a high level potential
  • the wiring DR2, the wiring DR4, and the wiring DR5 are at a low level potential. Note that, between time T2 and time T3 in the timing chart of FIG. 27B, the wiring INIT is at a high level potential, but it may be at a low level potential.
  • the transistors MN31 and MN32 are turned on. Also, the transistors MN33, MN34, and MN35 are turned off. Since the transistors MN31 and MN32 are turned on, the terminal IP and the second terminal of the capacitance element C2 are in a conductive state, and the potential VY of the second terminal of the capacitance element C2 rises to a potential Vin corresponding to the input signal provided by the terminal IP. Also, since the first terminal of the capacitance element C2 is in a floating state at this time, the potential of the first terminal of the capacitance element C2 also changes as the potential of the second terminal of the capacitance element C2 changes.
  • the capacitance coupling coefficient related to the capacitance element C2 and the parasitic capacitance around it is K
  • the potential of the first terminal of the capacitance element C2 changes from VX to VX + K (Vin - VY ).
  • K 1
  • the potential of the first terminal of the capacitance element C2 becomes VX + Vin - VY .
  • the gate-source voltage of the transistor MN36 becomes high, and the amount of current flowing between the source and drain also becomes large.
  • the source follower circuit SAM shown in FIG. 27A also functions as a sample-and-hold circuit. Therefore, after the potential corresponding to the input signal input from terminal IP is held in capacitance elements C1 and C2, the holding circuit LTC2 that inputs a signal to terminal IP can be stopped.
  • transistors MN31 through MN35, transistor MN37, and transistor MN38 have the function of transmitting a signal from terminal IP to terminal OP. For this reason, it is preferable to use transistors with a high driving frequency for each of the above transistors. In other words, it is preferable to use transistor MTHN described in embodiment 1 for transistors MN31 through MN35, transistor MN37, and transistor MN38. Note that if it is desired to increase the voltage tolerance of transistors MN31 through MN35, transistor MN37, and transistor MN38, transistor MTCK may be used for each of the above transistors instead of transistor MTHN.
  • transistor MN36 In addition, in the level shifter circuit LS, a voltage increased by capacitive coupling is applied to the gate of transistor MN36. For this reason, it is preferable to use a transistor having high resistance to voltage for transistor MN36. In other words, it is preferable to use transistor MTCK described in the first embodiment for transistor MN36. Note that if it is desired to increase the drive frequency of transistor MN36, transistor MTHN may be used for transistor MN36 instead of transistor MTCK.
  • transistor MTCK may be used for transistor MN37.
  • transistor MTCK1 shown in Figures 60A to 60C, transistor MTHN1 shown in Figures 61A to 61C, transistor MTCK2 shown in Figures 62A to 62C, and transistor MTHN2 shown in Figures 63A to 63C, which have a channel length (for example, the length from the source electrode to the drain electrode in the channel formation region) longer than transistor MTCK and transistor MTHN, may be used.
  • transistors MTCK1, MTHN1, MTCK2, and MTHN2 will be described later in embodiment 4.
  • circuit that can be used for the source follower circuit SAM in FIG. 3 or FIG. 4 is not limited to the source follower circuit SAM in FIG. 27A described above.
  • a circuit that is a modified version of the source follower circuit SAM in FIG. 27A can be used as the source follower circuit SAM in FIG. 3 or FIG. 4.
  • the source follower circuit SAM in FIG. 27A may be changed to the source follower circuit SAM shown in FIG. 28.
  • the source follower circuit shown in FIG. 28 differs from the source follower circuit SAM in FIG. 27A in that a switch SWP is provided between the first terminal of the transistor MN36 and the wiring VE22.
  • the first terminal of the switch SWP is electrically connected to the wiring VE22
  • the second terminal of the switch SWP is electrically connected to the first terminal of the transistor MN36
  • the control terminal of the switch SWP is electrically connected to the wiring SWPL.
  • the wiring SWPL functions as a wiring that transmits a signal to control the switching of the switch SWP between the on and off states.
  • the switch SWP has the role of making the connection between the wiring VE22 and the first terminal of the transistor MN36 conductive or non-conductive. Therefore, for example, by turning off the switch SWP, the supply of power from the wiring VE22 to the first terminal of the transistor MN36 can be stopped, and as a result, the source follower circuit SAM of FIG. 28 can be temporarily stopped. Therefore, since no power is supplied while the operation of the source follower circuit SAM of FIG. 28 is stopped, the power consumption in the source follower circuit SAM can be reduced.
  • the circuit LTCSF shown in FIG. 29A has been designed to address the above issues, and has a function as a latch circuit that temporarily holds an image signal, and a function as a source follower circuit that amplifies the image signal. Note that FIG. 29A also illustrates a shift register SR and a conversion circuit CVT to show the electrical connection configuration of the circuit LTCSF.
  • the circuit LTCSF has a switch SW0, a switch SW3a, a switch SW3b, a switch SW4a, a switch SW4b, a source follower circuit SAMa, and a source follower circuit SAMb.
  • Switches SW0, SW3a, SW3b, and SW4a can each be, for example, a switch that can be used as switch SW1 or switch SW2 described above.
  • each of the switches SW0, SW3a, SW3b, and SW4a shown in FIG. 29A is turned on when a high-level potential is applied to the control terminal, and turned off when a low-level potential is applied to the control terminal.
  • the source follower circuit SAM shown in FIG. 27A can be used, for example.
  • the first terminal of the switch SW0 is electrically connected to the wiring VDL
  • the second terminal of the switch SW0 is electrically connected to the first terminal of the switch SW3a and the first terminal of the switch SW3b
  • the control terminal of the switch SW0 is electrically connected to the shift register SR.
  • the control terminal of the switch SW0 is electrically connected to the second output terminal of the memory circuit RES included in the shift register SR (not shown in FIG. 29A).
  • the wiring electrically connecting the switch SW0 and the shift register SR is referred to as the wiring SWL0.
  • the second terminal of the switch SW3a is electrically connected to the input terminal of the source follower circuit SAMa, and the control terminal of the switch SW3a is electrically connected to the wiring SWL3a.
  • the second terminal of the switch SW3b is electrically connected to the input terminal of the source follower circuit SAMb, and the control terminal of the switch SW3b is electrically connected to the wiring SWL3b.
  • the first terminal of the switch SW4a is electrically connected to the output terminal of the source follower circuit SAMa
  • the second terminal of the switch SW4a is electrically connected to the input terminal of the conversion circuit CVT
  • the control terminal of the switch SW4a is electrically connected to the wiring SWL4a.
  • the first terminal of the switch SW4b is electrically connected to the output terminal of the source follower circuit SAMb
  • the second terminal of the switch SW4b is electrically connected to the input terminal of the conversion circuit CVT
  • the control terminal of the switch SW4b is electrically connected to the wiring SWL4b.
  • the second terminal of the switch SW4a and the second terminal of the switch SW4b are electrically connected to the input terminal of the digital-to-analog conversion circuit DAC included in the conversion circuit CVT (not shown in FIG. 27).
  • FIG. 29B is a timing chart showing an example of the operation of the circuit LTCSF shown in FIG. 29A.
  • the timing chart in FIG. 29B shows the change in the image signal input to the wiring VDL and the change in the potential of the wiring SW0, wiring SWL3a, wiring SWL3b, wiring SWL4a, and wiring SWL4b from time T11 to time T14 and around those times. Note that in the timing chart in FIG. 29B, a high-level potential is indicated as "High” and a low-level potential is indicated as "Low.”
  • a high-level potential is input from the shift register SR to the control terminal of switch SW0 via wiring SWL0.
  • a high-level potential is also applied to wiring SWL3a and wiring SWL4b, and a high-level potential is input to the control terminal of switch SW3a and the control terminal of switch SW4b.
  • a low-level potential is also applied to wiring SWL3b and wiring SWL4a, and a low-level potential is input to the control terminal of switch SW3b and the control terminal of switch SW4a.
  • switches SW0, SW3a, and SW4b are turned on, and switches SW3b and SW4a are turned off.
  • the image signal SIG[1] is input from the wiring VDL to the first terminal of the switch SW0.
  • the image signal SIG[1] is input to the source follower circuit SAMa via the switches SW0 and SW3a.
  • a potential according to the image signal SIG[1] is held in the first terminal of the capacitive element C1 and the second terminal of the capacitive element C2 shown in FIG. 27A, and the amplified image signal SIG[1] is output from the output terminal (terminal OP) of the source follower circuit SAMa.
  • the switch SW4a since the switch SW4a is in the off state, the image signal SIG[1] output from the output terminal (terminal OP) of the source follower circuit SAMa does not reach the conversion circuit CVT.
  • an image signal held in the source follower circuit SAMb before time T11 is input from the output terminal of the source follower circuit SAMb to the conversion circuit CVT via the switch SW4b. Therefore, between time T11 and time T12, the image signal is converted from digital data to analog data and input to the pixel circuit PX of the pixel array PXA.
  • a high-level potential is input from the shift register SR to the control terminal of switch SW0 via wiring SWL0.
  • a high-level potential is also applied to wiring SWL3b and wiring SWL4a, and a high-level potential is input to each of the control terminals of switches SW3b and SW4a.
  • a low-level potential is also applied to wiring SWL3a and wiring SWL4b, and a low-level potential is input to each of the control terminals of switches SW3a and SW4b.
  • switches SW0, SW3b, and SW4a are turned on, and switches SW3a and SW4b are turned off.
  • the image signal SIG[2] is input from the wiring VDL to the first terminal of the switch SW0.
  • the image signal SIG[2] is input to the source follower circuit SAMb via the switches SW0 and SW3b.
  • a potential according to the image signal SIG[2] is held in the first terminal of the capacitive element C1 and the second terminal of the capacitive element C2 shown in FIG. 27A, and the amplified image signal SIG[2] is output from the output terminal (terminal OP) of the source follower circuit SAMb.
  • the switch SW4b is in the off state, the image signal SIG[2] output from the output terminal (terminal OP) of the source follower circuit SAMb does not reach the conversion circuit CVT.
  • the image signal SIG[1] held in the source follower circuit SAMa from time T11 to time T12 is input from the output terminal of the source follower circuit SAMa to the conversion circuit CVT via the switch SW4a. Therefore, from time T13 to time T14, the image signal SIG[1] is converted from digital data to analog data and input to the pixel circuit PX of the pixel array PXA.
  • the source follower circuits SAMa and SAMb each of which has the function of holding a potential according to an input signal, it is possible to hold an input signal in one source follower circuit and output a signal previously held in the other source follower circuit.
  • the first latch circuit LA and the second latch circuit LB are electrically connected in series as in FIG. 3 or FIG. 4, attenuation of the image signal may occur, but by using the circuit LTCSF described above, it is possible to temporarily hold the image signal and prevent attenuation of the image signal.
  • the semiconductor device according to one embodiment of the present invention is not limited to the configuration of each circuit described above.
  • the semiconductor device according to one embodiment of the present invention may have a configuration in which each circuit described above is modified as appropriate.
  • FIG. 30A is a circuit diagram showing an example of a circuit configuration that can be applied to the pixel circuit PX of the display device DSP described in the first embodiment.
  • the pixel circuit PX1 shown in FIG. 30A includes, as an example, a transistor Tr1, a transistor Tr2, a capacitance element Cs1, a capacitance element Cs2, and a light-emitting device ED.
  • the light-emitting device ED examples include a light-emitting device containing an organic EL material, a light-emitting device containing an inorganic EL material, and a light-emitting diode (e.g., a micro LED (Light Emitting Diode)).
  • the pixel circuit PX1 can be a pixel circuit to which one or more of the above-mentioned light-emitting devices ED are applied. In this embodiment, the pixel circuit PX of the pixel array PXA is described as being applied with a light-emitting device containing an organic EL material.
  • the luminance of light emitted from a light-emitting device capable of emitting particularly high luminance light can be, for example, 500 cd/m 2 or more, preferably 1000 cd/m 2 or more and 10000 cd/m 2 or less, and more preferably 2000 cd/m 2 or more and 5000 cd/m 2 or less.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring SL
  • the second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr2 and the first terminal of the capacitance element Cs1
  • the gate of the transistor Tr1 is electrically connected to the wiring GL.
  • the first terminal of the transistor Tr2 is electrically connected to the wiring IL
  • the second terminal of the transistor Tr2 is electrically connected to the second terminal of the capacitance element Cs1, the first terminal of the capacitance element Cs2, and the anode of the light-emitting device ED.
  • the second terminal of the capacitance element Cs2 is electrically connected to the wiring VCOM.
  • the cathode of the light-emitting device ED is electrically connected to the wiring VCAT.
  • the wiring SL corresponds to the wiring SLS shown in FIG. 1 and the wiring SL[1] to wiring SL[5] shown in FIG. 3 or FIG. 4, and functions as a wiring for transmitting an image signal from the driver circuit SD to the pixel circuit PX1.
  • the wiring GL corresponds to the wiring GLS shown in FIG. 1 and the wiring GL[1] to wiring GL[m] shown in FIG. 5, and functions as a wiring for transmitting a selection signal from the driver circuit GD to the pixel circuit PX1.
  • the wiring IL functions as a wiring for supplying current to the anode of the light-emitting device ED. For this reason, the wiring IL is sometimes called a current supply line.
  • the wiring VCOM functions as a wiring that provides a fixed potential to the second terminal of the capacitance element Cs2.
  • the fixed potential may be called a common potential.
  • the common potential may be a low-level potential, a ground potential, or a negative potential.
  • the wiring VCOM may also be a wiring that provides a common potential to the second terminal of the capacitance element Cs2 provided in another pixel circuit PX1 in the same pixel array PXA.
  • the wiring VCAT functions as a wiring that applies a fixed potential to the cathode of the light-emitting device ED.
  • this fixed potential may be called a cathode potential.
  • the cathode potential may be, for example, a low-level potential, a ground potential, or a negative potential.
  • the wiring VCAT may also be a wiring that applies a cathode potential to the cathode of a light-emitting device ED provided in another pixel circuit PX1 in the same pixel array PXA.
  • the common potential provided by the wiring VCOM and the cathode potential provided by the wiring VCAT may be equal to each other.
  • the wiring VCOM and the wiring VCAT may be the same wiring (not shown).
  • the transistor Tr1 functions as a write transistor for an image signal in the pixel circuit PX. For this reason, if it is desired to increase the frame frequency of the display device DSP, it is preferable to use a transistor with a high drive frequency for the transistor Tr1. For example, it is preferable to use a transistor with a thin gate insulating film for the transistor Tr1. Specifically, it is preferable to use, for example, the transistor MTHN described in the above embodiment, or the transistor MTHN1 or the transistor MTHN2 described in embodiment 4 for the transistor Tr1. Note that, if it is desired to use a transistor with high resistance to voltage for the transistor Tr1, for example, the transistor MTCK described in the above embodiment, or the transistor MTCK1 or the transistor MTCK2 described in embodiment 4 may be used.
  • the transistor Tr2 also functions as a drive transistor for controlling the amount of current flowing between the anode and cathode of the light emitting device ED in the pixel circuit PX. For this reason, when the potential according to the image signal is high, it is preferable to use a transistor having high resistance to voltage for the transistor Tr2. For example, it is preferable to use a transistor having a thick gate insulating film for the transistor Tr2. Specifically, it is preferable to use, for example, the transistor MTCK described in the above embodiment, or the transistor MTCK1 or the transistor MTCK2 described in embodiment 4 for the transistor Tr2. Note that when it is desired to use a transistor having a high drive frequency for the transistor Tr2, for example, the transistor MTHN described in the above embodiment, or the transistor MTHN1 or the transistor MTHN2 described in embodiment 4 may be used.
  • FIG. 30B is a circuit diagram showing an example of a circuit configuration that can be applied to the pixel circuit PX of the display device DSP described in the first embodiment and that is different from the pixel circuit of FIG. 30A.
  • the pixel circuit PX2 shown in FIG. 30B includes, as an example, a transistor Tr1, a transistor Tr2, a transistor Tr3, a transistor Tr4, a capacitance element Cs1, a capacitance element Cs3, and a light-emitting device ED.
  • the transistor Tr1, the transistor Tr2, the capacitance element Cs1, and the light-emitting device ED please refer to the description of the transistor Tr1, the transistor Tr2, the capacitance element Cs1, and the light-emitting device ED included in the pixel circuit PX1 above.
  • the pixel circuit PX2 not only emits light with an intensity according to the input image signal, but also has the function of correcting the threshold voltage of the driving transistor, transistor Tr2.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring SL
  • the second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr2 and the first terminal of the capacitance element Cs1
  • the gate of the transistor Tr1 is electrically connected to the wiring GL1.
  • the first terminal of the transistor Tr2 is electrically connected to the first terminal of the transistor Tr3, and the second terminal of the transistor Tr2 is electrically connected to the second terminal of the capacitance element Cs1, the first terminal of the capacitance element Cs3, the first terminal of the transistor Tr4, and the anode of the light-emitting device ED.
  • the second terminal of the transistor Tr3 is electrically connected to the wiring VEL
  • the gate of the transistor Tr3 is electrically connected to the wiring GL2.
  • the second terminal of the capacitance element Cs3 is electrically connected to the wiring VEL.
  • the second terminal of the transistor Tr4 is electrically connected to the wiring INIL, and the gate of the transistor Tr4 is electrically connected to the wiring GL3.
  • the cathode of the light-emitting device ED is electrically connected to the wiring VCAT.
  • wiring SL and wiring VCAT For information about the wiring SL and wiring VCAT, please refer to the description of the wiring SL and wiring VCAT that are electrically connected to the pixel circuit PX1 in Figure 30A.
  • the wiring GL1, wiring GL2, and wiring GL3 correspond to the wiring GLS shown in FIG. 1, and function as wiring for transmitting a selection signal from the driving circuit GD to the pixel circuit PX.
  • the wiring VEL functions as a wiring for applying a potential to the anode of the light-emitting device ED.
  • the wiring INIL functions as a wiring for applying a potential to the anode of the light-emitting device ED.
  • the potential can be, for example, an initialization potential for resetting the anode potential of the light-emitting device ED.
  • transistors with high voltage resistance for transistors Tr3 and Tr4.
  • transistors with thick gate insulating films for transistors Tr3 and Tr4.
  • transistor MTCK described in the above embodiment
  • transistor MTCK1 or transistor MTCK2 described in embodiment 4
  • transistor MTHN described in the above embodiment
  • transistor MTHN1 or transistor MTHN2 described in embodiment 4 may be used.
  • the transistors Tr1 and Tr2 may be transistors having back gates.
  • the pixel circuit PX2 may be configured such that the back gate of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, and the back gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr2.
  • the transistor MTHN1 or the transistor MTHN2 having a back gate electrode which will be described in embodiment 4, for the transistor Tr1.
  • FIG. 30C is a circuit diagram showing an example of a circuit configuration that can be applied to the pixel circuit PX of the display device DSP described in the first embodiment and that is different from the pixel circuits of FIGS. 30A and 30B.
  • the pixel circuit PX3 shown in FIG. 30C includes, as an example, a transistor Tr1, a transistor Tr2, a transistor Tr4, a transistor Tr5, a capacitance element Cs1, and a light-emitting device ED.
  • pixel circuit PX3 Like pixel circuit PX2, pixel circuit PX3 not only emits light with an intensity according to the input image signal, but also has the function of correcting the threshold voltage of transistor Tr2, which is the drive transistor.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring SL, the second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr2, the first terminal of the transistor Tr5, and the first terminal of the capacitance element Cs1, and the gate of the transistor Tr1 is electrically connected to the wiring GL1.
  • the first terminal of the transistor Tr2 is electrically connected to the wiring VEL, and the second terminal of the transistor Tr2 is electrically connected to the second terminal of the capacitance element Cs1, the first terminal of the transistor Tr4, and the anode of the light-emitting device ED.
  • the second terminal of the transistor Tr5 is electrically connected to the wiring VBL, and the gate of the transistor Tr5 is electrically connected to the wiring GL4.
  • the second terminal of the transistor Tr4 is electrically connected to the wiring INIL, and the gate of the transistor Tr4 is electrically connected to the wiring GL3.
  • the cathode of the light-emitting device ED is electrically connected to the wiring VCAT.
  • wiring SL For the wiring SL, wiring VCAT, wiring VEL, and wiring INIL, refer to the description of the wiring SL, wiring VCAT, wiring VEL, and wiring INIL that are electrically connected to the pixel circuit PX2 in Figure 30B.
  • the wiring GL1, wiring GL3, and wiring GL4 correspond to the wiring GLS shown in FIG. 1, and function as wiring for transmitting a selection signal from the driving circuit GD to the pixel circuit PX.
  • the wiring VBL functions as a wiring for applying a fixed potential to the first terminal of the capacitance element Cs1.
  • the fixed potential is, for example, a potential input to the gate of the transistor Tr2 when correcting the threshold voltage of the transistor Tr2, and is preferably approximately equal to the potential applied by the wiring VEL.
  • transistor Tr5 It is preferable to use a transistor having high resistance to voltage for transistor Tr5.
  • transistor MTCK described in the above embodiment
  • transistor MTCK1 or transistor MTCK2 described in embodiment 4
  • transistor Tr5 Note that if it is desired to use a transistor having a high driving frequency for transistor Tr5, for example, transistor MTHN described in the above embodiment, or transistor MTHN1 or transistor MTHN2 described in embodiment 4 may be used.
  • FIG. 30D is a circuit diagram showing an example of a circuit configuration that can be applied to the pixel circuit PX of the display device DSP described in the first embodiment and is different from the pixel circuits of FIGS. 30A to 30C.
  • the pixel circuit PX4 shown in FIG. 30D includes, as an example, a transistor Tr1, a transistor Tr2, a transistor Tr4, a capacitance element Cs1, and a light-emitting device ED.
  • pixel circuit PX4 also has the function of emitting light with a luminance according to the input image signal.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring SL
  • the second terminal of the transistor Tr1 is electrically connected to the gate of the transistor Tr2 and the first terminal of the capacitance element Cs1
  • the gate of the transistor Tr1 is electrically connected to the wiring GL1.
  • the first terminal of the transistor Tr2 is electrically connected to the wiring VEL
  • the second terminal of the transistor Tr2 is electrically connected to the second terminal of the capacitance element Cs1, the first terminal of the transistor Tr4, and the anode of the light-emitting device ED.
  • the second terminal of the transistor Tr4 is electrically connected to the wiring INIL
  • the gate of the transistor Tr4 is electrically connected to the wiring GL3.
  • the cathode of the light-emitting device ED is electrically connected to the wiring VCAT.
  • wiring SL For wiring SL, wiring VCAT, wiring INIL, wiring GL1, and wiring GL3, the description of wiring SL and wiring VCAT electrically connected to pixel circuit PX3 in Figure 30C can be referred to.
  • the transistor Tr2 may be a transistor having a back gate.
  • the pixel circuit PX4 may be configured such that the back gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr2.
  • FIG. 32A is a circuit diagram showing a configuration example of a circuit that can be applied to the pixel circuit PX of the display device DSP described in the first embodiment and that is different from the pixel circuits of FIGS. 30A to 30D.
  • the pixel circuit PX5 shown in FIG. 32A includes, as an example, transistors Tr1 to Tr4, transistors Tr6 and Tr7, a capacitance element Cs1, and a light-emitting device ED.
  • the description of the transistors Tr1 to Tr4, the capacitance element Cs1, and the light-emitting device ED included in the pixel circuit PX2 above can be referenced.
  • pixel circuit PX5 Like pixel circuits PX2 and PX3, pixel circuit PX5 not only emits light with an intensity according to the input image signal, but also has the function of correcting the threshold voltage of transistor Tr2, which is the drive transistor.
  • the first terminal of the transistor Tr1 is electrically connected to the wiring SL
  • the second terminal of the transistor Tr1 is electrically connected to the first terminal of the transistor Tr2 and the first terminal of the transistor Tr7
  • the gate of the transistor Tr1 is electrically connected to the wiring GL1.
  • the second terminal of the transistor Tr2 is electrically connected to the first terminal of the transistor Tr3 and the first terminal of the transistor Tr6, and the gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr6 and the first terminal of the capacitance element Cs1.
  • the second terminal of the transistor Tr3 is electrically connected to the wiring VEL
  • the gate of the transistor Tr3 is electrically connected to the wiring GL2.
  • the gate of the transistor Tr6 is electrically connected to the gate of the transistor Tr4 and the wiring GL3.
  • the second terminal of the transistor Tr7 is electrically connected to the first terminal of the transistor Tr4, the second terminal of the capacitance element Cs1, and the anode of the light-emitting device ED.
  • the second terminal of the transistor Tr4 is electrically connected to the wiring INIL.
  • the cathode of the light-emitting device ED is electrically connected to the wiring VCAT.
  • wiring SL For the wiring SL, wiring VCAT, wiring VEL, and wiring INIL, refer to the description of the wiring SL, wiring VCAT, wiring VEL, and wiring INIL that are electrically connected to the pixel circuit PX2 in Figure 30B.
  • the wiring GL1, wiring GL2, wiring GL3, and wiring GL5 correspond to the wiring GLS shown in FIG. 1, and function as wiring for transmitting a selection signal from the driving circuit GD to the pixel circuit PX.
  • transistors with high voltage resistance for transistors Tr6 and Tr7.
  • transistors with thick gate insulating films for transistors Tr6 and Tr7.
  • transistor MTCK described in the above embodiment
  • transistor MTCK1 or transistor MTCK2 described in embodiment 4 for transistors Tr6 and Tr7.
  • transistor MTHN described in the above embodiment
  • transistor MTHN1 or transistor MTHN2 described in embodiment 4 may be used.
  • the pixel circuit of the semiconductor device of one embodiment of the present invention is not limited to the configuration of the pixel circuit PX5 shown in FIG. 32A, and the circuit configuration of the pixel circuit PX5 may be changed as appropriate.
  • a capacitance element Cs4 may be provided in the pixel circuit PX5 in FIG. 32A.
  • a first terminal of the capacitance element Cs4 is electrically connected to the gate of the transistor Tr1 and the wiring GL1, and a second terminal of the capacitance element Cs4 is electrically connected to the first terminal of the transistor Tr4, the second terminal of the transistor Tr7, the second terminal of the capacitance element Cs1, and the anode of the light-emitting device ED.
  • the transistors Tr1, Tr2, and Tr6 may be transistors having back gates.
  • the pixel circuit PX5A may be configured such that the back gate of the transistor Tr1 is electrically connected to the gate of the transistor Tr1, the back gate of the transistor Tr2 is electrically connected to the second terminal of the transistor Tr2, and the back gate of the transistor Tr6 is electrically connected to the gate of the transistor Tr6.
  • the transistor MTHN1 or the transistor MTHN2 having a back gate electrode which will be described in embodiment 4, for the transistor Tr1.
  • pixel circuit configuration example 6 In the above pixel circuit configuration example 1 to pixel circuit configuration example 5, configuration examples of a pixel circuit PX having a light-emitting device ED have been described, but the pixel circuit PX provided in the display device DSP described in the above embodiment 1 may also be configured to include, for example, a liquid crystal display device.
  • the pixel circuit PX6 shown in FIG. 34 is a pixel circuit that can be applied to the pixel circuit PX described in the first embodiment above, and differs from the pixel circuits PX1 to PX5 and the pixel circuit PX5A in that it includes a liquid crystal display device LCR.
  • the pixel circuit PX6 includes, as an example, a transistor Tr8, a capacitance element Cs5, and a liquid crystal display device LCR.
  • the first terminal of the transistor Tr8 is electrically connected to the first terminal of the capacitance element Cs5 and the first terminal of the liquid crystal display device LCR, the second terminal of the transistor Tr8 is electrically connected to the wiring SL, and the gate of the transistor Tr8 is electrically connected to the wiring GL6.
  • the second terminal of the capacitance element Cs5 is electrically connected to the wiring CSL.
  • the second terminal of the liquid crystal display device LCR is electrically connected to the wiring COM.
  • the wiring SL corresponds to the wiring SLS shown in FIG. 1 and the wiring SL[1] to wiring SL[5] shown in FIG. 3 or FIG. 4, and functions as a wiring for transmitting an image signal from the driver circuit SD to the pixel circuit PX6.
  • the wiring GL6 corresponds to the wiring GLS shown in FIG. 1 and the wiring GL[1] to wiring GL[m] shown in FIG. 5, and functions as a wiring for transmitting a selection signal from the driver circuit GD to the pixel circuit PX6.
  • the wiring CSL functions as a wiring that applies a fixed potential to the second terminal of the capacitance element Cs5.
  • the fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential.
  • the wiring CSL may also be a wiring that applies a common potential to the second terminal of the capacitance element Cs2 provided in another pixel circuit PX1 in the same pixel array PXA.
  • the wiring COM functions as a wiring that applies a fixed potential to the second terminal of the liquid crystal display device LCR.
  • the fixed potential may be called a common potential.
  • the common potential may be a low-level potential, a ground potential, or a negative potential.
  • the wiring COM may also be a wiring that applies a common potential to the second terminal of the liquid crystal display device LCR provided in another pixel circuit PX6 in the same pixel array PXA.
  • the fixed potential provided by the wiring CSL and the common potential provided by the wiring COM may be equal to each other.
  • the wiring CSL and the wiring COM may be the same wiring (not shown).
  • the transistor Tr8 functions as a write transistor for an image signal in the pixel circuit PX6. For this reason, if it is desired to increase the frame frequency of the display device DSP, it is preferable to use a transistor with a high drive frequency for the transistor Tr8. For example, it is preferable to use a transistor with a thin gate insulating film for the transistor Tr8. Specifically, it is preferable to use, for example, the transistor MTHN described in the above embodiment, or the transistor MTHN1 or the transistor MTHN2 described in embodiment 4 for the transistor Tr8. Note that, if it is desired to use a transistor with high resistance to voltage for the transistor Tr8, for example, the transistor MTCK described in the above embodiment, or the transistor MTCK1 or the transistor MTCK2 described in embodiment 4 may be used.
  • a in each figure shows a schematic plan view.
  • B in each figure is a schematic cross-sectional view corresponding to the portion of dashed line A1-A2 shown in each A, and is also a schematic cross-sectional view in the X direction.
  • C in each figure is a schematic cross-sectional view corresponding to the portion of dashed line A3-A4 shown in each A, and is also a schematic cross-sectional view in the Y direction.
  • D in each figure is a schematic cross-sectional view corresponding to the portion of dashed line A5-A6 shown in each A, and is also a schematic cross-sectional view in the Y direction.
  • insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be formed using appropriate film formation methods such as sputtering, CVD, MBE (Molecular Beam Epitaxy), PLD, or ALD.
  • a substrate (not shown) is prepared, and an insulator IS1 and a conductive film ME1A are formed in that order on the substrate (see Figures 35A to 35D).
  • the substrate may be, for example, a semiconductor substrate (e.g., a single crystal substrate made of silicon or germanium).
  • the substrate may be, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film.
  • SOI Silicon On Insulator
  • glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda lime glass.
  • Examples of flexible substrates, laminated films, and base films include the following.
  • plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) are exemplified.
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyethersulfone
  • PTFE polytetrafluoroethylene
  • one example may be a synthetic resin such as an acrylic resin.
  • examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride.
  • examples include polyamide, polyimide, aramid, epoxy resin, inorganic deposition film, and paper.
  • a substrate having elements provided thereon may be used. Examples of elements provided on the substrate include a capacitance element, a resistance element, a switch element, a light-emitting element, and a memory element.
  • the insulator IS1 functions as an interlayer film, for example.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used.
  • silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, or silicon oxide with vacancies can be used for the insulator IS1.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.
  • resin can be used for the insulator IS1.
  • the material used for the insulator IS1 may be an appropriate combination of the insulating materials described above.
  • the relative dielectric constant of the insulator IS1 is preferably less than 4, and more preferably less than 3.
  • Examples of insulating materials with a low relative dielectric constant include silicon oxide, silicon oxynitride, and silicon nitride oxide.
  • the conductive film ME1A is a film that will become the conductor ME1 in a later process.
  • a part of the conductor ME1 also functions as either the source electrode or the drain electrode of the transistor MTCK.
  • another part of the conductor ME1 also functions as either the source electrode or the drain electrode of the transistor MTHN. For this reason, it is preferable to use a highly conductive material for the conductive film ME1A.
  • a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, or an alloy containing two or more of the above-mentioned metal elements, or an alloy combining two or more of the above-mentioned metal elements.
  • tantalum nitride titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel for the conductive film ME1A.
  • Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are preferred because they are conductive materials that are difficult to oxidize, or materials that maintain their conductivity even when they absorb oxygen.
  • the conductor may be, for example, a semiconductor with high electrical conductivity, such as polycrystalline silicon containing an impurity element (e.g., phosphorus or arsenic), or a silicide (e.g., nickel silicide).
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing nitrogen.
  • a laminate structure may be formed by combining the above-mentioned material containing a metal element with a conductive material containing oxygen and a conductive material containing nitrogen.
  • the conductor ME1 may have a first conductor and a second conductor surrounded by the first conductor (not shown).
  • the first conductor may be titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide, which are conductive materials that have the function of suppressing the diffusion of oxygen
  • the second conductor may be a conductive material mainly composed of highly conductive tungsten, copper, or aluminum.
  • the conductive film ME1A is processed into a band shape using lithography to form the conductor ME1 (see Figures 36A to 36D).
  • a part of the conductor ME1 is formed to extend in a direction parallel to the dashed dotted line A3-A4 (Y direction)
  • another part of the conductor ME1 is formed to extend in a direction parallel to the dashed dotted line A5-A6 (Y direction).
  • the above processing can be performed using a dry etching method or a wet etching method, and the dry etching method is particularly suitable for fine processing.
  • the resist is exposed through a mask.
  • the exposed area is then removed or left using a developer to form a resist mask.
  • a conductor, semiconductor, or insulator can be processed into a desired shape by etching through the resist mask.
  • a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, or EUV (Extreme Ultraviolet) light.
  • a liquid immersion technique may be used in which a liquid (e.g., water) is filled between the substrate and the projection lens and exposure is performed.
  • an electron beam or an ion beam may be used instead of the light described above.
  • the resist mask can be removed by performing a dry etching process such as ashing, a wet etching process, a dry etching process followed by a wet etching process, or a dry etching process followed by a wet etching process.
  • a hard mask made of an insulator or conductor may be used under the resist mask.
  • an insulating or conductive film that will be the hard mask material is formed on the conductive film ME1A, a resist mask is formed on top of that, and the hard mask material is etched to form a hard mask of the desired shape.
  • Etching of the conductive film ME1A etc. may be performed after removing the resist mask, or may be performed while leaving the resist mask in place. In the latter case, the resist mask may disappear during etching.
  • the hard mask may be removed by etching.
  • the material of the hard mask does not affect subsequent processes or can be used in subsequent processes, it is not necessarily necessary to remove the hard mask.
  • the insulating film IS2A is formed on the conductor ME1 (see Figures 37A to 37D).
  • the insulating film IS2A can be formed by using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the insulating film IS2A may be subjected to a planarization process such as a chemical mechanical polishing (CMP) method to planarize the upper surface of the insulating film IS2A (not shown).
  • CMP chemical mechanical polishing
  • the insulating film IS2A is a film that will become the insulator IS2 in a later process.
  • the insulator IS2 also functions as an interlayer film, for example. For this reason, it is preferable that the insulator IS2 has an insulating material with a low relative dielectric constant. By using an insulating material with a low relative dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.
  • the insulating film IS2A can be made of, for example, a material that can be used for the insulator IS1.
  • the semiconductor SC1 formed in a later process is a metal oxide that functions as an oxide semiconductor
  • These materials can easily form a region containing oxygen that is desorbed by heating, and can supply the desorbed oxygen to the metal oxide.
  • the carrier concentration of the metal oxide decreases at the interface and near the interface of the semiconductor SC1 that is in contact with the insulator IS2, and the interface and near the interface of the semiconductor SC1 become i-type or substantially i-type. Therefore, the interface and near the interface of the semiconductor SC1 function as a channel formation region in the transistor MTCK or the transistor MTHN.
  • a conductive film ME2A is formed on the insulating film IS2A (see Figures 37A to 37D).
  • the conductive film ME2A is a film that will become the conductor ME2 in a later process.
  • a part of the conductor ME2 also functions as the other of the source electrode or drain electrode of the transistor MTCK.
  • Another part of the conductor ME2 also functions as the other of the source electrode or drain electrode of the transistor MTHN. For this reason, it is preferable to use a highly conductive material for the conductive film ME2A.
  • the conductive film ME2A can be made of, for example, a material that can be used for the conductor ME1.
  • the conductive film ME2A is processed into a band shape using lithography to form the conductive film ME2B (see Figures 38A to 38D).
  • the conductive film ME2B is formed so as to extend in a direction parallel to the dashed dotted line A1-A2 (X direction) and to have an area that overlaps with part of the conductor ME1.
  • the lithography method described in Figures 36A to 36D can be referenced for the lithography method.
  • the insulating film IS2A and the conductive film ME2B are processed using lithography to form an insulator IS2 and a conductor ME2 having openings KK1 and KK2 (see Figures 39A to 39D).
  • the above processing can be performed using a dry etching method or a wet etching method, and processing using a dry etching method is particularly suitable for fine processing.
  • the insulating film IS2A and the conductive film ME2B may be processed under different conditions.
  • the opening KK1 or the opening KK2 has a tapered shape with a taper angle that is approximately perpendicular (70° or more and 110° or less) to the X-Y plane, for example.
  • the opening KK1 or the opening KK2 may have a tapered shape with a taper angle that is 30° or more and less than 70°, or a taper angle that is greater than 0° and less than 30°, for example, to the X-Y plane.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface.
  • the angle between the inclined side and the substrate surface is referred to as the taper angle.
  • a tapered shape having a taper angle of more than 0° and less than 90° is referred to as a forward taper shape
  • a tapered shape having a taper angle of more than 90° and less than 180° is referred to as a reverse taper shape.
  • opening KK1 and opening KK2 in a plan view is illustrated as a circle, but the shape may be a shape including a curve (for example, an ellipse, a triangle with rounded corners, a rectangle, a pentagon, etc.), or a shape with corners (a polygon such as a triangle, a rectangle, a pentagon, etc.).
  • a curve for example, an ellipse, a triangle with rounded corners, a rectangle, a pentagon, etc.
  • a shape with corners a polygon such as a triangle, a rectangle, a pentagon, etc.
  • by-products generated in the above etching process may be formed in layers on the side surfaces of the openings KK1 and KK2 (the respective side surfaces of the insulator IS2 and the conductor ME2).
  • the layered by-products are formed between the insulator IS2 and the conductor ME2 and the semiconductor film SC1A described below. Therefore, it is preferable to remove the layered by-products formed in contact with the insulator IS2 and the conductor ME2.
  • a semiconductor film SC1A is formed on the conductor ME1, on the insulator IS2, and on the conductor ME2 (see Figures 40A to 40D). Specifically, inside each of the openings KK1 and KK2, the semiconductor film SC1A is formed on the upper surface of the conductor ME1, on the side of the insulator IS2, and on the side of the conductor ME2. Outside the openings KK1 and KK2, the semiconductor film SC1A is formed on the upper surface of the conductor ME2 and on the upper surface of the insulator IS2.
  • the semiconductor film SC1A is formed on the bottom surface and inner side surface of each of the openings KK1, the bottom surface and inner side surface of each of the openings KK2, on the conductor ME2, and on the insulator IS2.
  • the semiconductor film SC1A can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the semiconductor film SC1A is preferably formed using the ALD method.
  • the semiconductor film SC1A is preferably formed to a thin thickness, and it is necessary to reduce the variation in the film thickness.
  • the ALD method is a film formation method in which a precursor and a reactant (e.g., an oxidizing agent) are alternately introduced, and the film thickness can be adjusted by the number of times this cycle is repeated, so that precise film thickness adjustment is possible.
  • the semiconductor film SC1A needs to be formed with good coverage on the bottom surface and inner side surface of the opening KK1 and the bottom surface and inner side surface of the opening KK2.
  • the semiconductor film SC1A is formed with good coverage on the upper surface of the conductor ME1 and the side surface of the conductor ME2 in each of the openings KK1 and KK2.
  • a layer of atoms can be deposited one by one on the bottom surface and inner side surface of each of the openings, so that the semiconductor film SC1A can be formed with good coverage on the openings.
  • the deposition of the semiconductor film SC1A is not limited to the ALD method.
  • a sputtering method may be used.
  • the semiconductor film SC1A is a film that will become the semiconductor SC1 in a later process.
  • a portion of the semiconductor SC1 functions as the channel formation regions of the transistor MTCK and the transistor MTHN that will be formed in a later process.
  • Another portion of the semiconductor SC1 may function as one of a pair of electrodes of the capacitive element C1 that will be formed in a later process.
  • the semiconductor film SC1A can be, for example, a metal oxide that functions as an oxide semiconductor.
  • the transistor MTCK and the transistor MTHN are OS transistors.
  • the metal oxide preferably contains at least indium or zinc.
  • the metal oxide contains indium and zinc.
  • the element M is contained.
  • the element M one or more selected from aluminum, gallium, silicon, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony can be used.
  • the element M is one or more of aluminum, gallium, yttrium, and tin. It is even more preferable that the element M contains one or both of gallium and tin.
  • In-Ga-Zn oxide for the semiconductor film SC1A.
  • it is more preferable to use a metal oxide having a composition of In:Ga:Zn 1:1:1 [atomic ratio] or a composition close thereto, a composition of 4:2:3 [atomic ratio] or a composition close thereto, or a composition of 3:1:2 [atomic ratio] or a composition close thereto.
  • the carrier concentration of the channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably less than 1 ⁇ 10 17 cm ⁇ 3 , more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more. Note that in order to reduce the carrier concentration of the oxide semiconductor film, it is only necessary to reduce the impurity concentration in the oxide semiconductor film and reduce the density of defect states.
  • a low impurity concentration and a low density of defect states are referred to as high-purity intrinsic or substantially high-purity intrinsic.
  • an oxide semiconductor having a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Furthermore, charges captured in the trap states of the oxide semiconductor may take a long time to disappear and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • impurities in an oxide semiconductor refer to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • V O impurity or oxygen vacancy
  • OS transistor oxide semiconductor
  • the electrical characteristics of the transistor may fluctuate and the reliability may decrease.
  • a defect hereinafter, sometimes referred to as V OH
  • V OH a defect in which hydrogen is introduced into V O in the oxide semiconductor may be formed, and electrons that serve as carriers may be generated.
  • the transistor when V O is contained in the channel formation region of an oxide semiconductor, the transistor is likely to be normally on (a channel exists even when the gate-source voltage is 0 V, and a current flows through the transistor). Therefore, it is preferable that impurities, oxygen vacancies, and V OH are reduced as much as possible in the channel formation region of the oxide semiconductor.
  • the semiconductor film SC1A preferably has a laminated structure of multiple oxide layers with different atomic ratios of each metal atom.
  • a first metal oxide and a second metal oxide formed on the first metal oxide as metal oxides.
  • each metal oxide contains at least indium (In) and element M
  • the ratio of the number of atoms of element M contained in the first metal oxide to the number of atoms of all elements constituting the first metal oxide is higher than the ratio of the number of atoms of element M contained in the second metal oxide to the number of atoms of all elements constituting the second metal oxide.
  • the atomic ratio of element M contained in the first metal oxide to In is higher than the atomic ratio of element M contained in the second metal oxide to In.
  • the energy of the conduction band minimum of the first metal oxide is higher than the energy of the conduction band minimum of the second metal oxide.
  • the electron affinity of the first metal oxide is smaller than the electron affinity of the second metal oxide.
  • the energy level of the conduction band minimum changes smoothly.
  • the energy level of the conduction band minimum at the junction between the first metal oxide and the second metal oxide changes continuously or is a continuous junction.
  • the first metal oxide and the second metal oxide have a common element other than oxygen (as the main component), so that a mixed layer with a low density of defect levels can be formed.
  • the second metal oxide is In-Ga-Zn oxide (indium-gallium-zinc oxide)
  • the first metal oxide can be In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide.
  • a composition close thereto includes a range of ⁇ 30% of the desired atomic ratio.
  • the main carrier path is the second metal oxide.
  • the metal oxide may have a laminated structure of the second metal oxide and the first metal oxide formed on the second metal oxide. This configuration can prevent an increase in contact resistance between the conductor ME1 or ME2 and the metal oxide. Also, damage caused by the deposition of the insulator GI1 (described in detail later) on the second metal oxide can be reduced.
  • the oxygen concentration may be reduced in the vicinity of the conductor in the semiconductor SC1.
  • a metal compound layer containing the metal contained in the conductor and components of the semiconductor SC1 may be formed in the vicinity of the conductor in the semiconductor SC1. In such a case, the carrier concentration increases in the region of the semiconductor SC1 in the vicinity of the conductor, and the region becomes a low-resistance region.
  • the semiconductor SC1 can be made of a material containing silicon, for example.
  • the silicon include amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon (including low-temperature polysilicon (LTPS)), or single crystal silicon.
  • amorphous silicon sometimes called hydrogenated amorphous silicon
  • microcrystalline silicon microcrystalline silicon
  • polycrystalline silicon including low-temperature polysilicon (LTPS)
  • LTPS low-temperature polysilicon
  • single crystal silicon single crystal silicon.
  • the semiconductor film SC1A is described as including a metal oxide that functions as an oxide semiconductor.
  • the semiconductor film SC1A is processed using a lithography method to form the semiconductor SC1 so that a part of the insulator IS2 and a part of the conductor ME2 are exposed.
  • the semiconductor SC1 is processed so as to overlap with the conductor ME2 (see Figures 41A to 41D).
  • the lithography method can be referred to as described in Figures 36A to 36D.
  • the insulator GI1 and the insulating film GI2A are formed on the insulator IS2, the conductive film ME2, and the semiconductor SC1 (see Figures 42A to 42D).
  • the insulating film GI2A is a film that will become the insulator GI2 in a later process.
  • the insulator GI1 and the insulating film GI2A can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • Insulators GI1 and GI2 function as gate insulating films for transistors MTCK and MTHN, respectively.
  • insulator GI1 or the insulating film GI2A it is preferable to use a single layer or a multilayer of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3 (BST).
  • a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO 3 ), or (Ba,Sr)TiO 3 (BST).
  • an oxide having aluminum and hafnium, an oxynitride having aluminum and hafnium, an oxide having silicon and hafnium, an oxynitride having silicon and hafnium, or a nitride having silicon and hafnium may be used as an insulator with a high relative dielectric constant.
  • the insulator GI1 or the insulating film GI2A may be an insulating layer formed by stacking the above-mentioned high-k material with silicon oxide or silicon oxynitride. This allows an insulating layer that has a high relative dielectric constant and is also thermally stable to be used as the gate insulating film of each of the transistors MTCK and MTHN.
  • the insulator GI1 and the insulating film GI2A may be made of the same material or different materials.
  • the microwave treatment refers to a treatment using an apparatus having a power source that generates high-density plasma using microwaves, for example.
  • microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.
  • the microwave treatment may be performed at a stage where the silicon oxide film or the silicon oxynitride film is formed.
  • microwave processing can use high frequency waves such as microwaves or RF, oxygen plasma, oxygen radicals, and the like.
  • a microwave processing device having a power source that generates high density plasma using microwaves for example.
  • the frequency of the microwave processing device may be 300 MHz or more and 300 GHz or less, preferably 2.4 GHz or more and 2.5 GHz or less, for example, 2.45 GHz.
  • the power of the power source that applies microwaves of the microwave processing device may be 1000 W or more and 10000 W or less, preferably 2000 W or more and 5000 W or less.
  • the microwave processing device may have a power source that applies RF to the substrate side.
  • oxygen ions generated by high density plasma can be efficiently guided into the semiconductor SC1, which is a metal oxide.
  • the semiconductor SC1 which is a metal oxide.
  • VOH contained in the region of the semiconductor SC1 can be separated and hydrogen can be removed from the region.
  • VOH contained in the region can be reduced.
  • oxygen radicals generated by the oxygen plasma to the oxygen vacancies formed in the region, it is possible to further reduce the oxygen vacancies in the region and to lower the carrier concentration.
  • the insulating film GI2A is processed using a lithography method to form an insulator GI2 so that a portion of the insulator GI1 is exposed (see Figures 43A to 43D).
  • the insulator GI2 is formed to extend in a direction parallel to the dashed dotted line A3-A4 (Y direction) so as to include an area overlapping the semiconductor SC1 formed in the opening KK1.
  • the insulator GI2 is not formed at least in an area overlapping the semiconductor SC1 formed in the opening KK2.
  • the lithography method described in Figures 36A to 36D can be referred to for the lithography method.
  • the insulator GI2A In order to optimally form the insulator GI2, it is preferable to use a material for the insulating film GI2A that has an etching selectivity with respect to the insulator GI1.
  • a conductive film ME3A is formed on the insulators GI1 and GI2 (see Figs. 44A to 44D).
  • the conductive film ME3A is formed so as to fill each of the openings KK1 and KK2.
  • Each of the conductive films ME3A can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the conductive film ME3A is a film that will become the conductor ME3 in a later process.
  • a part of the conductor ME3 also functions as the gate electrode of the transistor MTCK.
  • Another part of the conductor ME3 also functions as the gate electrode of the transistor MTHN. For this reason, it is preferable to use a highly conductive material for the conductive film ME3.
  • the conductive film ME3A can be made of a material that can be used for the conductor ME1, for example.
  • the conductive film ME3A is processed into a band shape using lithography to form the conductive film ME3 (see Figures 45A to 45D).
  • a portion of the conductor ME3 is formed so as to extend in a direction parallel to the dashed dotted line A3-A4 (Y direction) and overlap with the conductor ME1.
  • Another portion of the conductive film ME3 is formed so as to extend in a direction parallel to the dashed dotted line A5-A6 (Y direction) and overlap with another conductor ME1.
  • the lithography method described in Figures 36A to 36D can be referenced for the lithography method.
  • insulator IS3 is deposited on insulator GI1, insulator GI2, and conductor ME3 (see Figures 2A to 2D).
  • the insulator IS3 is, for example, a film that functions as an interlayer film. Therefore, it is preferable that the insulator IS3 has an insulating material with a low relative dielectric constant. By using an insulating material with a low relative dielectric constant as the interlayer film, the parasitic capacitance that occurs between the wirings can be reduced.
  • insulator IS1 a material that can be used for the insulator IS1 can be used as the insulator IS3.
  • the conductor ME3 is formed below the insulator IS3. For this reason, it is preferable to use, for example, silicon nitride as a barrier insulating film for the insulator IS3 to suppress the diffusion of oxygen in order to prevent the conductor ME3 from being oxidized.
  • the above manufacturing method makes it possible to manufacture the transistor MTCK, which has high resistance to high voltages, and the transistor MTHN, which has a high drive frequency, as shown in Figures 2A to 2D.
  • the manufacturing method of the semiconductor device of one embodiment of the present invention is not limited to the above.
  • the manufacturing method may be changed as appropriate. Even if the configuration of the semiconductor device is changed due to a change in the manufacturing method, the semiconductor device can be considered as one embodiment of the present invention.
  • the transistors MTCK and MTHN shown in Figures 46A to 46D are modified examples of the transistors MTCK and MTHN of Figures 2A to 2D, and are configured in such a way that the insulator GI2 included in part of the gate insulating film of the transistor MTCK of Figures 2A to 2C is also formed on the conductor ME2 included in the transistor MTHN of Figures 2B and 2D.
  • insulators GI1 and GI2 are located between conductors ME2 and ME3. In other words, the distance between conductors ME2 and ME3 in transistor MTHN can be increased. This makes it possible to reduce the parasitic capacitance between conductors ME2 and ME3 in transistor MTHN, thereby increasing the drive frequency of transistor MTHN.
  • the transistors MTCK and MTHN shown in Figures 47A to 47D are modified examples of the transistors MTCK and MTHN of Figures 2A to 2D, and are configured such that the taper angles of the opening KK1 in the transistor MTCK and the opening KK2 in the transistor MTHN of Figures 2A to 2D are each approximately 60°.
  • the transistors MTCK and MTHN shown in Figures 47A to 47D can be fabricated, for example, by setting the taper angles of the openings KK1 and KK2 to approximately 60° with respect to the surface of the substrate (not shown) or the insulator IS1 in the fabrication process of the transistors MTCK and MTHN described in Figures 39A to 39D.
  • the transistor MTCK shown in Figures 48A to 48C is a modified example of the transistor MTCK of Figures 2A to 2C, and differs from the transistor MTCK of Figures 2A to 2C in that the insulator GI2 is formed only in the area overlapping the semiconductor SC1.
  • the transistor MTCK shown in Figures 48A to 48C can be obtained, for example, by forming an insulating film GI2A in the manufacturing process of the transistor MTCK and the transistor MTHN described in Figures 42A to 42C, and then processing the insulating film GI2A in the lithography method described in Figures 43A to 43C so that the end of the insulator GI2 is included in the area overlapping the semiconductor SC1. As a result, insulator G1 and conductor ME3 are formed in this order in the area on the conductor ME2 that is not overlapped by the semiconductor SC1.
  • insulator G1, insulator GI2, and conductor ME3 are formed in that order in the region on conductor ME2 that is not overlapped by semiconductor SC1, so the thickness of the insulator between conductor ME2 and conductor ME3 in that region of the transistor MTCK of Figures 48A to 48C can be made thinner than the thickness of the insulator between conductor ME2 and conductor ME3 in that region of the transistor MTCK of Figures 2A to 2C.
  • the thickness of the insulator between the conductor ME2 and the conductor ME3 is thin, so a capacitive element can be provided in that region.
  • a capacitive element can be provided between the gate and the other of the source and drain of the transistor MTCK of Figures 48A to 48C.
  • Examples of configurations in which a capacitance element is provided between the gate and source or drain of a transistor include the electrical connection configuration of transistor MN6 and capacitance element C3 in FIG. 6A, and the electrical connection configuration of transistor MN8 and capacitance element C4 in FIG. 6A.
  • connection configuration for example, a case where the gate and source of a transistor are electrically connected via a capacitance element.
  • the voltage of the capacitance element is the gate-source voltage that turns the transistor on and a high-level potential is input from the drain
  • a current flows from the drain to the source, causing the source potential to rise.
  • the gate potential of the transistor rises as the source potential rises.
  • the above-mentioned connection configuration even if the source potential changes, the gate-source voltage is maintained, so the source potential can be raised to a high-level potential provided from the drain side (corresponding to the bootstrap described for the memory circuit RESD3 in FIG. 14A).
  • transistor MTCK in Figures 48A to 48C can be said to have a suitable configuration when performing bootstrap, as described above.
  • the transistors MTCK and MTHN shown in Figures 49A to 49D are modified examples of the transistors MTCK and MTHN of Figures 2A to 2D, and the gate electrodes of the transistors MTCK and MTHN have a stacked structure of a conductor ME3 and a conductor ME3S.
  • the transistor MTCK shown in Figures 49A to 49D has a configuration in which, for example, a conductor ME3 with high film-forming properties is formed on the bottom surface and inner side surface of the opening KK1, and a conductor ME3S with high conductivity is formed on the conductor ME3. Therefore, the conductor ME3S functions as an auxiliary electrode for the conductor ME3.
  • the conductor ME3S may be formed by, for example, sputtering, CVD, MBE, PLD, or ALD. It is preferable to use, for example, a material that has a lower resistivity than the conductor ME3 among materials that can be used for the conductor ME1 for the conductor ME3S.
  • an auxiliary electrode similar to conductor ME3S may be provided on another conductor.
  • an auxiliary electrode similar to conductor ME3S may be provided on one or both of conductor ME1 and conductor ME2.
  • the auxiliary electrode may be provided below conductor ME1 rather than on conductor ME1.
  • the auxiliary electrode may be provided below conductor ME2 rather than on conductor ME2.
  • the transistors MTCK and MTHN shown in Figures 50A to 50D are further modified examples of the transistors MTCK and MTHN of Figures 2A to 2D, and are configured such that an insulator IB1 is provided on the upper surface of the insulator IS1, an insulator IB2 is provided on the upper surfaces of the insulator IB1 and the conductor ME1, an insulator IB3 is provided on the upper surface of the insulator IS2, and an insulator IB4 is provided on the upper surfaces of the insulators GI1, GI2, and ME3.
  • an insulator IB1 is formed (not shown).
  • an insulator IB2 is formed (not shown) on the upper surface of the insulator IB1 and the upper surface of the conductor ME1.
  • an insulator IB3 is formed (not shown). Then, after the manufacturing process of the transistor MTCK and the transistor MTHN in Figures 45A to 45D, an insulator IB4 is formed on the upper surface of the insulator GI1, the upper surface of the insulator GI2, and the upper surface of the conductor ME3 (not shown). After that, an insulator IS3 is provided on the upper surface of the insulator IB4, thereby manufacturing the transistor MTCK and the transistor MTHN shown in Figures 50A to 50D.
  • the insulator IB1 for example, preferably functions as a barrier insulating film that suppresses impurities such as water, hydrogen, nitrogen, and oxygen contained in the insulator IS1 from mixing into the conductor ME1 and the semiconductor SC1.
  • the insulator IB2 for example, preferably functions as a barrier insulating film that suppresses impurities such as water, hydrogen, nitrogen, and oxygen contained in the insulator IS2 from mixing into the conductor ME1.
  • the insulator IB4 for example, preferably functions as a barrier insulating film that suppresses impurities such as water, hydrogen, nitrogen, and oxygen contained in the insulator IS3 from mixing into the conductor ME2, the conductor ME3, and the semiconductor SC1.
  • the insulators IB1 to IB4 are preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O , NO, or NO2 ), and copper atoms (through which the above impurities are unlikely to permeate), or are preferably made of an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and/or oxygen molecules) (through which the above oxygen is unlikely to permeate).
  • impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O , NO, or NO2 ), and copper atoms (through which the above impurities are unlikely to permeate)
  • oxygen e.g., oxygen atoms and/or oxygen molecules
  • Insulators having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen may be, for example, insulators containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, used in a single layer or in a multilayer.
  • insulators having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen may be, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • insulators having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen may be, for example, oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulators that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, and silicon nitride.
  • the insulators IB1 to IB4 it is preferable to use aluminum oxide or silicon nitride for the insulators IB1 to IB4. This can suppress impurities such as water and hydrogen from diffusing from below the insulator IB1 to the transistors MTCK and MTHN. Also, it can suppress impurities such as water and hydrogen from diffusing from above the insulator IB4 to the transistors MTCK and MTHN.
  • the deposition method for each of the insulators IB1 to IB4 may be, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • transistors MTCK and MTHN shown in Figures 50A to 50D may be configured to not include 1 to 3 selected from the insulators IB1 to IB4.
  • the provision of a barrier insulating film can suppress the diffusion of impurities into conductors and semiconductors.
  • the transistors MTCK and MTHN shown in Figures 51A to 51D are modified examples of the transistors MTCK and MTHN shown in Figures 2A to 2D, and the order in which the conductor ME3 and the insulator GI2 are formed is different. Therefore, in the transistor MTHN, the insulator GI2 is formed on the upper surface of the conductor ME3.
  • FIGS. 52A to 52D are schematic diagrams showing the process of fabricating the transistor MTCK and the transistor MTHN shown in Figs. 51A to 51D.
  • Figs. 52A to 52D show a configuration in which an insulator GI1 and a conductive film ME3A are formed in this order on the insulator IS2, the conductive film ME2, and the semiconductor SC1 after the process of fabricating the transistor MTCK and the transistor MTHN shown in Figs. 41A to 41D.
  • the conductive film ME3A is processed into a band shape using lithography to form the conductor ME3 (see Figures 53A to 53D).
  • the conductor ME3 is formed to extend in a direction parallel to the dashed dotted line A5-A6 (Y direction), to fill the opening KK2, and to have an area that overlaps with part of the conductor ME1.
  • the lithography method described in Figures 36A to 36D can be referenced.
  • the lithography method is performed to such an extent that the insulator GI1 remains in areas other than the area where the conductor ME3 is formed.
  • a portion of the conductor ME3 also functions as the gate electrode of the transistor MTHN.
  • the insulator GI2 is deposited on the insulator GI1 and on the conductor ME3 (see Figures 54A to 54D).
  • the insulator GI2 is deposited on the insulator GI1 with good film-forming properties. Therefore, it is preferable to deposit the insulator GI2 using the ALD method.
  • the insulator GI2 can be deposited using a deposition method other than the ALD method, such as a sputtering method, a CVD method, an MBE method, or a PLD method.
  • a conductive film MEa3A is formed on the insulator GI2 (see Figures 55A to 55D).
  • the conductive film MEa3A is formed so as to fill the opening KK1.
  • the conductive film MEa3A can be formed using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method.
  • the conductive film MEa3A is a film that will become the conductor MEa3 in a later process. A part of the conductor MEa3 functions as the gate electrode of the transistor MTCK.
  • the conductive film MEa3A can be made of a material that can be used for the conductor ME3.
  • the conductive film ME3aA is processed into a band shape using lithography to form the conductive film MEa3 (see Figures 56A to 56D).
  • a portion of the conductor MEa3 is formed so as to extend in a direction parallel to the dashed dotted line A3-A4 (Y direction) and overlap with the conductor ME1.
  • the lithography method described in Figures 36A to 36D can be referenced for the lithography method.
  • a film of insulator IS3 is formed on insulator GI2 and conductor MEa3 (see Figures 51A to 51D).
  • the above manufacturing method can also be used to manufacture the transistor MTCK, which has high resistance to high voltages, and the transistor MTHN, which has a high drive frequency, as shown in Figures 51A to 51D.
  • the transistors MTCK and MTHN shown in FIGS. 57A to 57D are modified examples of the transistors MTCK and MTHN shown in FIGS. 2A to 2D, and have a configuration in which the insulators GI1 and GI2 are formed using a different method.
  • the manufacturing method shown in Figures 42A to 42B for example, after only the insulator GI1 is formed, lithography is used to form the insulator GI1 so that the insulator GI1 remains on a part of the conductor ME2 and on the semiconductor SC1. Then, the insulator GI2 is formed in the same manner as in the manufacturing method shown in Figures 42A to 42B, and the manufacturing method from Figures 43A to 43B onwards is performed, thereby manufacturing the transistor MTCK and transistor MTHN shown in Figures 57A to 57D.
  • the transistors MTCK and MTHN shown in Figures 57A to 57D may be further modified to the configurations of the transistors MTCK and MTHN shown in Figures 58A to 58D.
  • the transistors MTCK and MTHN shown in Figures 58A to 58D are configured in such a way that the insulator GI1 included in part of the gate insulating film of the transistor MTCK is also formed on the conductor ME2 included in the transistor MTHN in Figures 58B and 58D, similar to the transistors MTCK and MTHN in Figures 46A to 46D described in Modification Example 1.
  • insulators GI1 and GI2 are located between conductors ME2 and ME3. In other words, the distance between conductors ME2 and ME3 in transistor MTHN can be increased. This makes it possible to reduce the parasitic capacitance between conductors ME2 and ME3 in transistor MTHN, thereby increasing the drive frequency of transistor MTHN.
  • the transistors MTCK and MTHN shown in Figures 59A to 59D are modified examples of the transistors MTCK and MTHN of Figures 2A to 2D, and have a different configuration from the transistors MTCK and MTHN of Figures 2A to 2C in that an insulator GI1 is formed as the gate insulating film of the transistor MTCK, and an insulator GI3 is formed as the gate insulating film of the transistor MTHN.
  • an insulator GI1 is formed, and then lithography is used to form the insulator GI1 so that the insulator GI1 remains on the conductor ME2 and the semiconductor SC1 in the region where the transistor MTCK is formed.
  • an insulator GI3 is formed, and then lithography is used to form the insulator GI3 so that the insulator GI3 remains on the conductor ME2 and the semiconductor SC1 in the region where the transistor MTHN is formed.
  • transistors MTCK and MTHN shown in Figures 59A to 59D have their respective gate insulating films formed individually.
  • the thickness of the insulator GI1 is thicker than that of the insulator GI3.
  • the insulator GI3 can be made of a material that can be used for the insulators GI1 and GI2.
  • the gate insulating film of the transistor MTCK is formed first, but the gate insulating film of the transistor MTHN may be formed first, and then the gate insulating film of the transistor MTCK may be formed.
  • the above manufacturing method also makes it possible to produce a transistor MTCK with high voltage resistance and a transistor MTHN with a high drive frequency.
  • the transistor MTCK1 shown in Figures 60A to 60C is a modified example of the transistor MTCK of Figures 2A to 2C, and the channel formation region of the transistor MTCK1 is formed along the direction of the dotted line A1-A2 (the X direction in the X-Z plane in Figure 60B).
  • the transistor MTCK1 has a conductor ME3 that functions as a gate electrode, one of a pair of conductors ME2 that functions as one of the source electrode or drain electrode, the other of the pair of conductors ME2 that functions as the other of the source electrode or drain electrode, and a semiconductor SC1 included in the channel formation region.
  • the transistor MTCK1 is sometimes called a TGTC type transistor because the gate electrode is located above the channel formation region and the semiconductor SC1 is electrically connected to the conductor ME1.
  • the transistor MTCK1 also has a conductor ME1 that functions as a backgate electrode.
  • the backgate electrode like the gate electrode, has the function of generating an electric field in the semiconductor SC1.
  • the backgate electrode can change the number of carriers in the semiconductor SC1 depending on the potential applied to the backgate electrode, and as a result, can change the threshold voltage of the transistor MTCK1.
  • the insulator IS2 functions as a gate insulating film in the transistor MTCK1.
  • the insulator IS2 can be made of a material that can be used for the insulator GI1 or the insulator GI2.
  • the former is sometimes called the first gate insulating film or back gate insulating film, and the latter is sometimes called the second gate insulating film.
  • the transistor MTCK1 shown in Figures 60A to 60C includes insulators GI1 and GI2 as gate insulating films. Therefore, the transistor MTCK1 can be said to be a transistor with high resistance to voltage.
  • the gate insulating film of the transistor MTCK1 in Figures 60A to 60C does not need to include the insulator GI2.
  • the transistor MTHN1 shown in Figures 61A to 61C has a configuration in which the insulator GI2 is not provided in the transistor MTCK1 in Figures 60A to 60C, and has a thinner gate insulating film compared to the transistor MTCK1. For this reason, it can be said that the transistor MTHN1 is a transistor with a higher drive frequency than the transistor MTCK1.
  • Figures 60A to 60D show transistor MTHN that can be formed simultaneously with transistor MTCK1, but transistor MTCK1 can be formed simultaneously with transistor MTCK shown in Figures 2A to 2C.
  • Figures 61A to 61D show transistor MTHN that can be formed simultaneously with transistor MTHN1, but transistor MTHN1 can be formed simultaneously with transistor MTCK shown in Figures 2A to 2C.
  • the conductor ME3, which is the gate electrode of transistor MTCK1 is formed by lithography, but the gate electrode of transistor MTCK1 may be formed using another method.
  • the transistor MTCK2 shown in Figures 62A to 62C is a modified example of the transistor MTCK1 in Figures 60A to 60C, and differs from the transistor MTCK1 in Figures 60A to 60C in that a conductor ME4 that functions as a second gate electrode is embedded in an opening in the insulator IS3.
  • the conductor ME3 is not formed, and the insulator IS3 is formed on the insulators GI1 and GI2. After that, an opening is formed in the region of the insulator IS3 where the conductor ME1, the semiconductor SC1, and the insulator GI2 overlap, and the insulator GI4 and the conductor ME4 are formed in that order in the opening. Then, a planarization process such as a CMP method is performed, and the insulator IS3 is polished until it is exposed, thereby manufacturing the transistor.
  • a planarization process such as a CMP method
  • the insulating film GI4 is an insulator that functions as part of the gate insulating film of the transistor MTCK2, similar to the insulators GI1 and GI2. For this reason, the insulating film GI4 can be made of a material that can be used for the insulators GI1 and GI2. Note that since the insulator GI4 is formed on the side of the opening of the insulator IS3, it is preferable to use the ALD method, which has high coverage, as a method for depositing the insulator GI4.
  • the insulator GI4 functions as a film that prevents impurities such as oxygen contained in the insulator IS3 from diffusing into the conductor ME4, which would cause the conductor ME4 to be oxidized.
  • the insulator GI4 functions as a barrier insulating film. Note that if there is no need to prevent the diffusion of impurities from the insulator IS3 to the conductor ME4, the insulator GI4 does not need to be provided in the transistor MTCK2.
  • the conductor ME4 functions as the gate electrode of the transistor MTCK2. Therefore, the conductor ME4 can be made of a material that can be used for the conductor ME3.
  • the conductor ME4 that functions as the gate electrode is formed in a self-aligned manner so as to fill the opening formed in the insulator IS3.
  • the transistor MTCK2 in which the gate electrode is thus formed in a self-aligned manner so as to fill the opening is sometimes called a TGSA s-channel FET (Trench Gate Self Aligned s-channel FET).
  • the transistor MTCK2 shown in Figures 62A to 62C includes insulators GI1 and GI2 as gate insulating films. Therefore, the transistor MTCK2 can be said to be a transistor with high resistance to voltage.
  • the gate insulating film of the transistor MTCK2 in Figures 62A to 62C does not need to include the insulator GI2.
  • the transistor MTHN2 shown in Figures 63A to 63C has a configuration in which the insulator GI2 is not provided in the transistor MTCK2 in Figures 62A to 62C, and has a thinner gate insulating film than the transistor MTCK2. For this reason, it can be said that the transistor MTHN2 has a higher drive frequency than the transistor MTCK2.
  • Figures 62A to 62D show a transistor MTHN that can be formed simultaneously with transistor MTCK2, but transistor MTCK2 can be formed simultaneously with transistor MTCK shown in Figures 2A to 2C.
  • Figures 63A to 63D show a transistor MTHN that can be formed simultaneously with transistor MTHN2, but transistor MTHN2 can be formed simultaneously with transistor MTCK shown in Figures 2A to 2C.
  • the transistors MTCK and MTHN shown in Figures 64A to 64D have configurations different from those of the transistors MTCK and MTHN shown in Figures 2A to 2C.
  • the shape of an opening KK1 of the transistor MTCK is different from that of the transistor MTCK in Figures 2A to 2C.
  • the shape of an opening KK2 of the transistor MTHN is different from that of the transistor MTHN in Figures 2A to 2C.
  • an opening KK1 is provided so as to overlap with the upper surface of a portion of the conductor ME1 and the upper surface of a portion of the insulator IS1.
  • the opening KK1 is formed from above the portion of the conductor ME1 toward the +X direction in a plan view ( Figure 64A).
  • an opening KK2 is provided so as to overlap with the upper surface of a portion of the conductor ME1 and the upper surface of a portion of the insulator IS1.
  • the opening KK2 is formed from the portion of the conductor ME1 toward the +X direction in a plan view ( Figure 64A).
  • the conductor ME3 embedded in the openings KK1 and KK2 extends in the +X direction from a portion of the conductor ME1 in a plan view ( Figure 64A).
  • the conductor ME2 is provided in a portion of the periphery of the opening KK1. Specifically, as an example, the conductor ME2 has a U-shape, and the opening KK1 is located inside the U-shape. Similarly, in a plan view of the transistor MTHN (FIG. 64A), the conductor ME2 is provided in a portion of the periphery of the opening KK2. Specifically, as an example, the conductor ME2 has a U-shape, and the opening KK2 is located inside the U-shape.
  • conductor ME2, conductor ME3, semiconductor SC1, insulator GI1, and insulator GI2 are roughly the same. This configuration is obtained by forming a film of the materials listed above and then performing a planarization process such as a CMP method.
  • FIGS. 65A to 65D are schematic diagrams showing the process of fabricating the transistor MTCK and the transistor MTHN shown in Figs. 64A to 64D.
  • Figs. 65A to 65D show a configuration in which insulating films IS2A and IS4A are formed in this order on the insulator IS1 and the conductive film ME1 after the process of fabricating the transistor MTCK and the transistor MTHN shown in Figs. 36A to 36D.
  • the insulating film IS4A is processed using a lithography method to form an insulator IS4 (see Figures 66A to 66D).
  • a lithography method to form an insulator IS4 (see Figures 66A to 66D).
  • an opening is provided in the conductive film IS4A to serve as an area for forming the conductive film ME2B, which will be described later.
  • the lithography method described in Figures 36A to 36D can be referenced.
  • the insulating film IS4A can be made of a material that can be used for the insulating film IS2A.
  • the insulating film IS4A is processed by lithography, it is more preferable to use a material that can be used for the insulating film IS2A and that has an etching selectivity with respect to the insulating film IS2A as the material used for the insulating film IS4A.
  • a conductive film ME2A is formed on the insulating film IS2A and on the insulator IS4 (see Figures 67A to 67D).
  • the conductive film ME2A is a film that will become the conductor ME2 in a later process.
  • a part of the conductor ME2 also functions as the other of the source electrode or drain electrode of the transistor MTCK.
  • Another part of the conductor ME2 also functions as the other of the source electrode or drain electrode of the transistor MTHN. For this reason, it is preferable to use a highly conductive material for the conductive film ME2A.
  • a planarization process such as CMP is performed to polish the conductive film ME2A until the insulating film IS4A is exposed.
  • the conductive film ME2A is formed so as to be embedded as the conductive film ME2B in the opening of the insulating film IS4 formed in the steps of Figures 66A to 66D (see Figures 68A to 68D).
  • the conductive film ME2B is provided in contact with the upper surface of the insulating film IS2A and the side surface of the insulator IS4.
  • the insulating film IS2A and the conductive film ME2B are processed using a lithography method to form an insulator IS2 and a conductor ME2 having an opening KK1 and an opening KK2 (see Figures 69A to 69D).
  • the bottom surfaces of the openings KK1 and KK2 here include the top surface of the conductor ME1 and the top surface of the insulator IS1, which is different from the manufacturing process of the transistors MTCK and MTHN shown in Figures 39A to 39D.
  • the lithography method can be referred to as described in Figures 36A to 36D.
  • a semiconductor film SC1A is formed on the insulator IS1, the conductor ME1, the insulator IS2, and the conductor ME2 (see Figures 70A to 70D).
  • the semiconductor film SC1A is processed using a lithography method to form a semiconductor film SC1B so that a part of the insulator IS1, a part of the insulator IS2, and a part of the conductor ME2 are exposed (see Figures 71A to 71D). That is, the semiconductor film SC1B is provided on a part of the insulator IS1, on the conductor ME1, on the insulator IS2 (parts of the side surfaces of the opening KK1 and the opening KK2), and on the conductor ME2. Note that the lithography method described in Figures 36A to 36D can be referred to for the lithography method.
  • an insulating film GI1A that will become the insulator GI1 is formed on the insulator IS1, on the semiconductor film SC1B, and on the conductor ME2, and an insulating film GI2A that will become the insulator GI2 is formed on the insulating film GI1A (see Figures 72A to 72D).
  • the insulating film GI1 can be formed by using a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, in the same manner as the insulator GI1 described in Figures 42A to 42D.
  • a film formation method such as a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method, in the same manner as the insulator GI1 described in Figures 42A to 42D.
  • a conductive film ME3A is formed on the insulating film GI1A and on the insulating film GI2A (see FIG. 72A to FIG. 72D).
  • the conductive film ME3A is formed so as to fill each of the openings KK1 and KK2.
  • a planarization process such as CMP is performed to polish the conductive film ME3A, the insulating film GI2A, the insulating film GI1A, and the semiconductor film SC1B until the conductor ME2 and the insulator IS4 are exposed.
  • the conductive film ME3A is processed into the conductor ME3
  • the insulating film GI2A is processed into the insulator GI2
  • the insulating film GI1A is processed into the insulator GI1
  • the semiconductor film SC1B is processed into the semiconductor SC1 (see Figures 73A to 73C). This also results in the formation of the transistors MTCK and MTHN.
  • transistors MTCK and MTHN shown in Figures 73A to 73C are configured such that the conductor ME3 is embedded in the openings KK1 and KK2, and the heights of the conductor ME2, conductor ME3, semiconductor SC1, insulator GI1, and insulator GI2 are roughly the same as each other.
  • insulator IS3 is deposited on insulator GI1, insulator GI2, insulator IS4, semiconductor SC1, conductor ME2, and conductor ME3 (see Figures 64A to 64D).
  • the above manufacturing method makes it possible to manufacture a transistor (transistor MTCK) that is highly resistant to high voltages and a transistor (transistor MTHN) that has a high operating frequency, as shown in Figures 64A to 64D.
  • the method of embedding the conductor ME3 in the openings KK1 and KK2 does not use a mask, but instead selects the conductive film ME3A that will become the conductor ME3 in a self-aligned manner to form the conductor ME3. Therefore, the conductor ME3 can be formed without providing an alignment margin, which reduces the area occupied by the transistor MTCK or the transistor MTHN.
  • the transistors MTCK and MTHN shown in Figures 64A to 64D are configured such that the conductor ME3 is not formed above the conductor ME2 in the Z direction, so that the parasitic capacitance between the conductors ME2 and ME3 can be reduced.
  • the drive frequencies of the transistors MTCK and MTHN can be made higher than the drive frequencies of the transistors MTCK and MTHN shown in Figures 2A to 2D.
  • the side surfaces of the opening KK1 of the transistor MTCK and the opening KK2 of the transistor MTHN shown in Figures 64A to 64D are formed so as to be approximately perpendicular to the surface of the substrate (not shown) or the insulator IS1, but the angle between the side surface and the surface of the substrate (not shown) or the insulator IS1 may be greater than 0° and less than 70°.
  • the transistors MTCK and MTHN may be formed so that the openings KK1 and KK2 each have a taper angle greater than 0° and less than 70°, as shown in Figures 74A to 74D.
  • the carrier concentration of a channel formation region of the oxide semiconductor is 1 ⁇ 10 18 cm ⁇ 3 or less, preferably less than 1 ⁇ 10 17 cm ⁇ 3 , more preferably less than 1 ⁇ 10 16 cm ⁇ 3 , further preferably less than 1 ⁇ 10 13 cm ⁇ 3 , and further preferably less than 1 ⁇ 10 10 cm ⁇ 3 and 1 ⁇ 10 ⁇ 9 cm ⁇ 3 or more.
  • the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states.
  • a semiconductor having a low impurity concentration and a low density of defect states is referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor an oxide semiconductor with a low carrier concentration may be referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.
  • a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor may have a low density of trap states due to a low density of defect states. Furthermore, charges captured in the trap states of the oxide semiconductor may take a long time to disappear and may behave as if they were fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.
  • impurities in an oxide semiconductor refer to, for example, anything other than the main component that constitutes the oxide semiconductor.
  • an element with a concentration of less than 0.1 atomic % can be considered an impurity.
  • an OS transistor may form a defect in which hydrogen enters an oxygen vacancy in an oxide semiconductor (hereinafter, the defect may be referred to as VOH ), and generate electrons that serve as carriers.
  • VOH hydrogen enters an oxygen vacancy in an oxide semiconductor
  • the donor concentration in the channel formation region may increase.
  • the threshold voltage may vary.
  • the transistor when an oxygen vacancy is present in a channel formation region in an oxide semiconductor, the transistor is likely to be normally on (a state in which a channel exists even when no voltage is applied to a gate electrode and a current flows through the transistor, or a state in which a channel exists and a current flows through the transistor even when a gate-source voltage is 0 V). Therefore, it is preferable that impurities, oxygen vacancies, and VOH be reduced as much as possible in the channel formation region of an oxide semiconductor.
  • the band gap of the oxide semiconductor is preferably larger than that of silicon (typically 1.1 eV), and is preferably 2 eV or more, more preferably 2.5 eV or more, and even more preferably 3.0 eV or more.
  • the off current also referred to as off leakage current or Ioff
  • Ioff off leakage current
  • OS transistors use oxide semiconductors, which are semiconductor materials with a wide band gap, and therefore the short channel effect can be suppressed. In other words, OS transistors are transistors that do not have the short channel effect or have an extremely small short channel effect.
  • the short channel effect is a degradation of electrical characteristics that becomes evident as transistors are miniaturized (reduced channel length).
  • Specific examples of short channel effects include a decrease in threshold voltage, an increase in subthreshold swing value (sometimes written as S value), and an increase in leakage current.
  • the S value refers to the amount of change in gate voltage in the subthreshold region that changes the drain current by one order of magnitude at a constant drain voltage.
  • Characteristic length is widely used as an index of resistance to short channel effects.
  • Characteristic length is an index of how easily the potential of the channel formation region bends. The smaller the characteristic length, the steeper the potential rises, and therefore the more resistant it is to short channel effects.
  • OS transistors are accumulation-type transistors, while Si transistors are inversion-type transistors. Therefore, compared to Si transistors, OS transistors have smaller characteristic lengths between the source region and the channel-forming region, and between the drain region and the channel-forming region. Therefore, OS transistors are more resistant to the short-channel effect than Si transistors. In other words, when it is desired to manufacture a transistor with a short channel length, OS transistors are more suitable than Si transistors.
  • the OS transistor can also be regarded as having an n + / n ⁇ /n + accumulation-type junction-less transistor structure or an n + /n ⁇ /n + accumulation-type non-junction transistor structure in which the channel formation region is an n ⁇ type region and the source and drain regions are n + type regions.
  • the OS transistor can have good electrical characteristics even when the semiconductor device is miniaturized or highly integrated. For example, good electrical characteristics can be obtained even when the gate length of the OS transistor is 20 nm or less, 15 nm or less, 10 nm or less, 7 nm or less, or 6 nm or less, or 1 nm or more, 3 nm or more, or 5 nm or more.
  • the OS transistor can be suitably used as a transistor having a shorter channel length than that of a Si transistor.
  • the gate length is the length of the gate electrode in the direction in which carriers move inside the channel formation region when the transistor is operating, and refers to the width of the bottom surface of the gate electrode in a plan view of the transistor.
  • the cutoff frequency of the transistor can be improved.
  • the cutoff frequency of the transistor can be set to, for example, 50 GHz or more, preferably 100 GHz or more, and more preferably 150 GHz or more in a room temperature environment.
  • OS transistors As explained above, compared to Si transistors, OS transistors have the excellent advantages of having a smaller off-state current and being able to fabricate transistors with a short channel length.
  • the display device DSP1 for example, has a display region DIS, a driving circuit region DRV, and a terminal region TMR.
  • the display device DSP1 also has a substrate BS, and the display region DIS, the driving circuit region DRV, and the terminal region TMR are each located on the substrate BS.
  • the drive circuit region DRV also includes, as an example, drive circuits GDR1, GDR2, and SDR.
  • the substrate BS may be, for example, a semiconductor substrate (e.g., a single crystal substrate made of silicon or germanium).
  • the substrate BS may be, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, a paper containing a fibrous material, or a base film.
  • SOI Silicon On Insulator
  • glass substrates include, for example, barium borosilicate glass, aluminoborosilicate glass, or soda lime glass.
  • Examples of flexible substrates, laminated films, base films, and the like include plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE).
  • PET polyethylene terephthalate
  • PEN polyethylene naphthalate
  • PES polyethersulfone
  • PTFE polytetrafluoroethylene
  • another example may be a synthetic resin such as an acrylic resin.
  • Other examples include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride.
  • Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper. If the manufacturing process of the display device DSP1 includes a heat treatment, it is preferable to use a material with high heat resistance for the substrate BS.
  • the transistors included in the display area DIS and the drive circuit area DRV can be formed as Si transistors on the substrate BS.
  • the substrate on which the OS transistors are formed is not particularly limited, and as described above, a substrate that can be used for the substrate BS may be used.
  • one or more of the drive circuits GDR1, GDR2, and SDR included in the drive circuit region DRV may be mounted on the substrate BS as an integrated circuit (IC) using chip-on-glass (COG) technology.
  • IC integrated circuit
  • COG chip-on-glass
  • Each of the drive circuits GDR1 and GDR2 functions, for example, as a drive circuit for displaying an image in the display area DIS.
  • each of the drive circuits GDR1 and GDR2 functions as a gate driver circuit for the display area DIS.
  • the drive circuit SDR functions as a source driver circuit for the display area DIS.
  • the drive circuit GD of FIG. 1 described in the above embodiment can be applied to each of the drive circuits GDR1 and GDR2. Also, the drive circuit SD of FIG. 1 described in the above embodiment can be applied to the drive circuit SDR.
  • the terminal region TMR includes terminals for supplying image signals and power supply voltage from outside the display device DSP1 to the inside of the display device DSP1.
  • An FPC Flexible Printed Circuit
  • a chip may be mounted on the FPC as an IC using COF (Chip On Film) technology.
  • the IC may include, for example, a drive circuit for displaying an image in the display region DIS.
  • the display area DIS has, as an example, a plurality of pixels. Furthermore, the plurality of pixels may be arranged in a matrix in the display area DIS.
  • each of the multiple pixels can express one or multiple colors.
  • the multiple colors can be, for example, the three colors of red, green, and blue.
  • the multiple colors can be, for example, red, green, and blue, plus two or more colors selected from cyan, magenta, yellow, and white.
  • Each pixel expressing a different color is called a sub-pixel, and when white is expressed by multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively called a pixel.
  • sub-pixels are referred to as pixels and described.
  • the display device of one embodiment of the present invention is not limited to the configuration of the display device DSP1 illustrated in FIG. 75A.
  • the display device of one embodiment of the present invention may have the configuration of the display device DSP2 illustrated in FIG. 75B.
  • the display device DSP2 shown in FIG. 75B has, as an example, a display area DIS, a circuit area SIC, and a terminal area TMR.
  • the display device DSP2 also has a substrate BS, similar to the display device DSP1.
  • the display device DSP2 differs from the display area DSP1 in that the circuit area SIC and the terminal area TMR are provided on the substrate BS, and the display area DIS is provided on the circuit area SIC.
  • the circuit region SIC has the drive circuit region DRV described above, as an example.
  • the circuit region SIC may also include various functional circuits other than the drive circuit region DRV. In this embodiment, the functional circuits are considered to be included in the functional circuit region MFNC.
  • the functional circuit area MFNC may include a GPU (Graphics Processing Unit). Furthermore, if the display device DSP2 includes a touch panel, the functional circuit area MFNC may include a sensor controller that controls a touch sensor included in the touch panel. The sensor controller corresponds to the drive circuit TSD in the display device of FIG. 1.
  • the functional circuit region MFNC may include an EL correction circuit.
  • the EL correction circuit has a function of, for example, appropriately adjusting the amount of current input to a light-emitting device containing an organic EL material. Since the brightness of a light-emitting device containing an organic EL material when emitting light is proportional to the current, if the characteristics of a drive transistor electrically connected to the light-emitting device are poor, the brightness of the light emitted by the light-emitting device may be lower than the desired brightness.
  • the EL correction circuit monitors the amount of current flowing through the light-emitting device, and when the amount of current is smaller than the desired amount of current, it can increase the amount of current flowing through the light-emitting device to increase the brightness of light emitted by the light-emitting device. Conversely, when the amount of current is larger than the desired amount of current, it may adjust the amount of current flowing through the light-emitting device to be smaller.
  • the functional circuit area MFNC may also include a gamma correction circuit.
  • FIG. 76 is a block diagram showing an example of the configuration of the display device DSP2 shown in FIG. 75B.
  • the display device DSP2 shown in FIG. 76 has, as an example, a display area DIS and a circuit area SIC. Also, while FIG. 76 shows a sensor PDA, the sensor PDA may be disposed inside or outside the display device DSP2.
  • the display device DSP1 in FIG. 75A may also be electrically connected to a functional circuit region MFNC located outside the display device DSP1 via the terminal region TMR.
  • the configuration of the display device DSP1 in this case can be considered to be the same as the configuration of the display device DSP2 shown in FIG. 76.
  • thick solid lines indicate multiple wiring or bus wiring.
  • a plurality of pixel circuits PX are arranged in a matrix in the display area DIS.
  • the pixel circuits PX may be pixel circuits to which one or more selected from a liquid crystal display device, a light-emitting device containing an organic EL material, a light-emitting device containing an inorganic EL material, and a light-emitting device containing a light-emitting diode such as a micro LED are applied.
  • the pixel circuits PX in the display area DIS are described as being applied to light-emitting devices containing an organic EL material.
  • the circuit region SIC has a drive circuit region DRV and a functional circuit region MFNC, as described above.
  • the drive circuit region DRV functions as a peripheral circuit for driving the display region DIS, for example.
  • the drive circuit region DRV has, for example, a drive circuit SDR, a digital-to-analog conversion circuit DAD, a drive circuit GDR, and a level shifter circuit LV.
  • the drive circuit SDR corresponds, for example, to the drive circuit SD in FIG. 1
  • the drive circuit GDR corresponds, for example, to the drive circuit GD in FIG. 1.
  • the level shifter circuit LV corresponds to the amplifier circuit LVS illustrated in FIG. 4.
  • the functional circuit area MFNC may be provided with circuits such as a memory device in which image data to be displayed in the display area DIS is stored, a decoder for restoring encoded image data, a GPU for processing image data, a power supply circuit, a correction circuit, or a CPU.
  • the functional circuit area MFNC has, as an example, a memory device MEM, a GPU 22, an EL correction circuit ECR, a timing controller TMC, a CPU (NoffCPU (registered trademark)) 21, a sensor controller SCC, and a power supply circuit EPS.
  • the display device DSP2 in FIG. 76 is configured such that, as an example, bus wiring BSL is electrically connected to each of the circuits included in the drive circuit region DRV and the circuits included in the functional circuit region MFNC.
  • the drive circuit SDR has a function of transmitting image data to the pixel circuits PX included in the display area DIS. Therefore, the drive circuit SDR is electrically connected to the pixel circuits PX via the wiring SL.
  • the digital-to-analog conversion circuit DAD has a function of converting image data that has been digitally processed by, for example, the GPU or correction circuit described below, into analog data.
  • the image data converted into analog data is sent to the display area DIS via the drive circuit SDR.
  • the digital-to-analog conversion circuit DAD may be included in the drive circuit SDR, or the image data may be sent in the following order: drive circuit SDR, digital-to-analog conversion circuit DAD, and display area DIS.
  • the digital-to-analog conversion circuit DAD corresponds to the conversion circuit CVT shown in FIG. 3 or FIG. 4.
  • the driving circuit GDR has a function of selecting the pixel circuit PX to which image data is to be sent in the display area DIS. Therefore, the driving circuit GDR is electrically connected to the pixel circuit PX via the wiring GL.
  • the amplifier circuit LVS has the function of converting signals input to the drive circuit SDR, digital-to-analog conversion circuit DAD, drive circuit GDR, etc., to an appropriate level, as an example.
  • the memory device MEM has a function of storing image data to be displayed in the display area DIS.
  • the memory device MEM can be configured to store image data as digital data or analog data.
  • the memory device MEM When storing image data in the memory device MEM, it is preferable that the memory device MEM is a non-volatile memory. In this case, for example, a NAND type memory can be used as the memory device MEM.
  • the memory device MEM when temporary data generated by the GPU 22, the EL correction circuit ECR, the CPU 21, etc. is stored in the memory device MEM, it is preferable to use a volatile memory as the memory device MEM.
  • a volatile memory for example, an SRAM (Static Random Access Memory), a DRAM (Dynamic Random Access Memory), etc. can be used as the memory device MEM.
  • the GPU 22 has a function of performing processing to draw image data read from the memory device MEM in the display area DIS.
  • the GPU 22 is configured to perform pipeline processing in parallel, so that the image data to be displayed in the display area DIS can be processed at high speed.
  • the GPU 22 can also function as a decoder to restore encoded images.
  • the functional circuit region MFNC may also include a plurality of circuits capable of improving the display quality of the display region DIS.
  • circuits may include a correction circuit (a circuit for correcting color adjustment or dimming) that detects color unevenness in the image displayed in the display region DIS and corrects the color unevenness to create an optimal image.
  • a correction circuit a circuit for correcting color adjustment or dimming
  • an EL correction circuit may be provided in the functional circuit region MFNC.
  • the functional circuit region MFNC includes an EL correction circuit ECR.
  • artificial intelligence may be used for the image correction described above.
  • the current flowing through the display device (or the voltage applied to the display device) provided in the pixel may be monitored and acquired, and the image displayed in the display area DIS may be acquired by an image sensor or the like, and the current (or voltage) and the image may be treated as input data for an artificial intelligence calculation (e.g., an artificial neural network, etc.), and the output result may be used to determine whether or not the image needs to be corrected.
  • an artificial intelligence calculation e.g., an artificial neural network, etc.
  • artificial intelligence calculations can be applied not only to image correction, but also to upconversion processing of image data. This makes it possible to display high-quality images in the display area DIS by upconverting image data with a low screen resolution to match the image resolution of the display area DIS.
  • artificial intelligence calculations can also be applied to downconversion processing of image data.
  • the above-mentioned artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit area MFNC.
  • various correction calculations can be performed using the GPU 22.
  • the GPU 22 may also include a circuit 22a that corrects color unevenness and a circuit 22b that performs up-conversion processing.
  • the GPU that performs the calculations for artificial intelligence is called an AI accelerator.
  • the GPU provided in the functional circuit area MFNC may be described as an AI accelerator.
  • the timing controller TMC has a function of varying the frame rate at which an image is displayed in the display area DIS. For example, when a still image is displayed in the display area DIS, the display device DSP2 can be driven by the timing controller TMC at a lower frame rate, and when a moving image is displayed in the display area DIS, the display device DSP2 can be driven by the timing controller TMC at an increased frame rate. In other words, by providing the timing controller TMC in the display device DSP2, the frame rate can be changed according to a still image or a moving image. In particular, when a still image is displayed in the display area DIS, the display device DSP2 can be operated at a lower frame rate, thereby reducing the power consumption of the display device DSP2.
  • the CPU 21 has a function to perform general-purpose processing such as, for example, running an operating system, controlling data, performing various calculations, and running programs.
  • the CPU 21 has a role to execute commands such as, for example, writing or reading image data in the memory device MEM, correcting image data, or performing operations on a sensor, which will be described later.
  • the CPU 21 may have a function to transmit control signals to one or more selected from circuits included in the functional circuit area MFNC, such as the memory device, GPU, correction circuit, timing controller, and high-frequency circuit.
  • the CPU 21 may also have a circuit (hereinafter referred to as a backup circuit) that temporarily backs up data. It is preferable that the backup circuit can retain the data even if, for example, the supply of power supply voltage is stopped. For example, when a still image is displayed in the display area DIS, the CPU 21 can stop functioning until an image different from the current still image is displayed. Therefore, the data being processed by the CPU 21 can be temporarily saved in the backup circuit, and then the supply of power supply voltage to the CPU 21 is stopped to stop the CPU 21, thereby reducing the dynamic power consumption of the CPU 21. Furthermore, in this specification, a CPU having a backup circuit is referred to as a Noff CPU.
  • the sensor controller SCC has a function of controlling the sensor PDA. Also, in FIG. 76, wiring SNCL is illustrated as wiring for electrically connecting the sensor PDA and the sensor controller SCC.
  • the sensor PDA can be, for example, a touch sensor that can be provided above, below, or inside the display area DIS.
  • the sensor PDA can be, for example, an illuminance sensor.
  • the brightness (luminance) of the image displayed in the display area DIS can be changed according to the external light. For example, when the external light is bright, the luminance of the image displayed in the display area DIS can be increased to improve the visibility of the image. Conversely, when the external light is dark, the luminance of the image displayed in the display area DIS can be decreased to reduce power consumption.
  • the sensor PDA can be, for example, an image sensor.
  • an image can be acquired by the image sensor, and the image can be displayed in the display area DIS.
  • the power supply circuit EPS has a function of generating voltages to be supplied to the circuits included in the drive circuit region DRV, the circuits included in the functional circuit region MFNC, the pixels included in the display region DIS, and the like, as an example.
  • the power supply circuit EPS may also have a function of selecting the circuit to which the voltage is to be supplied.
  • the power supply circuit EPS can reduce the power consumption of the entire display device DSP by stopping the supply of voltage to each circuit included in the drive circuit region DRV (e.g., the drive circuit SDR, the digital-to-analog conversion circuit DAD, etc.) and each circuit included in the functional circuit region MFNC (e.g., the CPU 21, the GPU 22, etc.).
  • DRV drive circuit region
  • MFNC functional circuit region
  • the display device DSP1A shown in FIG. 77 is a cross-sectional configuration example of the display device DSP1 shown in FIG. 75A.
  • the display device DSP1A is configured such that pixel circuits, drive circuits, etc. are provided on a substrate 310.
  • the drive circuit region DRV and display region DIS shown in FIG. 75A are illustrated.
  • the substrate 310 in FIG. 77 corresponds to the substrate BS shown in FIG. 75A.
  • the diagonal size of the display device DSP1A can be determined, for example, by the type and size of the substrate 310. For example, when manufacturing a display device with a diagonal size of 30 inches or more, 50 inches or more, 70 inches or more, or 100 inches or more for a television device or an electronic device for digital signage, a glass substrate can be used as the substrate 310. For example, when manufacturing a display device with a diagonal size of 10 inches or less, 5 inches or less, 1.5 inches or less, 1 inch or less, or 0.5 inches or less for an XR device or a wearable information terminal, a semiconductor substrate can be used as the substrate 310.
  • the display device DSP1A can support various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, or 32:9.
  • the transistor MTHN and the transistor MTCK are formed on the substrate 310.
  • the light-emitting device 130 (light-emitting device 130R, light-emitting device 130G, and light-emitting device 130B in FIG. 77) is provided above the transistor MTHN and the transistor MTCK.
  • the transistor MTCK is included in the display area DIS, and functions, for example, as a transistor that the pixel circuit PX has.
  • the transistor MTHN functions as a transistor that is included in the drive circuit area DRV.
  • the transistor MTCK can be the transistor MTCK described in embodiment 1
  • the transistor MTHN can be the transistor MTHN described in embodiment 1.
  • the light-emitting device 130 can be a light-emitting device included in the pixel circuit PX.
  • Transistors MTCK and MTHN are provided on a substrate 310. Note that for the insulators, conductors, and semiconductors around transistors MTCK and MTHN, refer to embodiments 1 and 3.
  • an insulator IS3 is formed above the transistor MTHN and the transistor MTCK.
  • an insulator 574 and an insulator 581 are stacked in this order on the insulator IS3.
  • the insulator 574 preferably has a function of suppressing the diffusion of impurities such as water and hydrogen (e.g., hydrogen atoms and/or hydrogen molecules).
  • the insulator 574 preferably functions as a barrier insulating film that suppresses the impurities from entering the transistors MTHN and MTCK.
  • the insulator 574 also preferably has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and/or oxygen molecules).
  • the insulator 574 preferably has lower oxygen permeability than the insulators IS2 and IS3.
  • the insulator 574 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen. Therefore, the insulator 574 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N2O , NO, and NO2 ), and copper atoms (through which the above impurities are unlikely to permeate). Alternatively, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (e.g., oxygen atoms and/or oxygen molecules) (through which the above oxygen is unlikely to permeate).
  • oxygen e.g., oxygen atoms and/or oxygen molecules
  • Insulators having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen may be, for example, insulators containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, used in a single layer or in a laminated form.
  • insulators having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen may be, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide.
  • insulators having the function of suppressing the permeation of impurities such as water and hydrogen and oxygen may be, for example, oxides containing aluminum and hafnium (hafnium aluminate).
  • Examples of insulators that have the function of suppressing the permeation of impurities such as water and hydrogen, and oxygen include metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, and silicon nitride.
  • the insulator 574 it is preferable to use aluminum oxide or silicon nitride for the insulator 574. This can prevent impurities such as water and hydrogen from diffusing from above the insulator 574 to the transistor MTHN side and the transistor MTCK. Alternatively, it can prevent oxygen contained in the insulator IS3, etc. from diffusing above the insulator 574.
  • the insulator 581 is a film that functions as an interlayer film, and preferably has a lower dielectric constant than the insulator 574.
  • the relative dielectric constant of the insulator 581 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 581 is preferably 0.7 times or less the relative dielectric constant of the insulator 574, and more preferably 0.6 times or less.
  • the insulator 581 has a reduced concentration of impurities such as water and hydrogen in the film.
  • impurities such as water and hydrogen in the film.
  • silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used for the insulator 581.
  • silicon oxide to which fluorine has been added, silicon oxide to which carbon has been added, silicon oxide to which carbon and nitrogen have been added, or silicon oxide having vacancies can be used for the insulator 581.
  • silicon oxide and silicon oxynitride are preferable because they are thermally stable.
  • materials such as silicon oxide, silicon oxynitride, and silicon oxide having vacancies are preferable because they can easily form a region containing oxygen that is desorbed by heating.
  • a resin can be used for the insulator 581.
  • the material that can be used for the insulator 581 may be an appropriate combination of the above-mentioned materials.
  • Insulators 592 and 594 are layered in this order on insulators 574 and 581.
  • the insulator 592 is preferably an insulating film (referred to as a barrier insulating film) having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 310, the transistor MTCK, and the transistor MTHN to a region above the insulator 592 (e.g., a region where the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B are provided). Therefore, the insulator 592 is preferably an insulating material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (the impurities are unlikely to permeate through the insulating material).
  • a barrier insulating film referred to as a barrier insulating film having a barrier property that prevents impurities such as water and hydrogen from diffusing from the substrate 310, the transistor MTCK, and the transistor MTHN to a region above the insulator 592 (e.g., a region
  • the insulator 592 is preferably an insulating material having a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., N 2 O, NO, and NO 2 ), and copper atoms (the oxygen is unlikely to permeate through the insulating material).
  • the insulator 592 is preferably an insulating material having a function of suppressing the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules).
  • An example of a film that has barrier properties against hydrogen is silicon nitride formed by the CVD method.
  • the amount of desorption of hydrogen can be analyzed, for example, by thermal desorption spectrometry (TDS).
  • TDS thermal desorption spectrometry
  • the amount of desorption of hydrogen from the insulator 324 may be 10 ⁇ 10 15 atoms/cm 2 or less, preferably 5 ⁇ 10 15 atoms/cm 2 or less, calculated per area of the insulator 324, when the film surface temperature is in the range of 50° C. to 500° C., as calculated in terms of hydrogen atoms , in TDS .
  • insulator 594 is preferably an interlayer film with a low dielectric constant. For this reason, materials that can be used for insulator 581 can be used for insulator 594.
  • the insulator 594 has a lower dielectric constant than the insulator 592.
  • the relative dielectric constant of the insulator 594 is preferably less than 4, and more preferably less than 3.
  • the relative dielectric constant of the insulator 594 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 592.
  • a conductor MPG that functions as a plug or wiring is embedded in the insulator GI1 and the insulator IS3, and a conductor 596 that functions as a plug or wiring is embedded in the insulator 592 and the insulator 594.
  • the conductor MPG and the conductor 596 are electrically connected to a light-emitting device or the like that is provided above the insulator 594.
  • the same reference numeral may be given to multiple structures.
  • the wiring and the plug that connects to the wiring may be one body. That is, there are cases where a part of the conductor functions as the wiring, and cases where a part of the conductor functions as the plug.
  • the materials for each plug and wiring can be one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials, either in a single layer or in a laminated form. It is preferable to use a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferably used. Alternatively, it is preferable to form the wiring from a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be reduced.
  • Insulator 598 and insulator 599 are formed in sequence on insulator 594 and conductor 596.
  • the insulator 598 is an insulator having barrier properties against one or more selected from hydrogen, oxygen, and water, similar to the insulator 592.
  • the insulator 599 is an insulator having a relatively low dielectric constant, similar to the insulator 594, in order to reduce the parasitic capacitance that occurs between wirings.
  • the insulator 599 functions as an interlayer insulating film and a planarizing film.
  • the light-emitting device 130 and the connection portion 140 are formed on the insulator 599.
  • connection portion 140 may be called a cathode contact portion, and is electrically connected to the cathode electrodes of the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B.
  • the connection portion 140 has one or more conductors selected from the conductors 112a to 112c described below, at least one conductor from the conductors 126a to 126c described below, one or more conductors selected from the conductors 129a to 129c described below, a common layer 114 described below, and a common electrode 115 described below.
  • connection portion 140 may be provided so as to surround the four sides of the display portion in a plan view, or may be provided within the display portion (e.g., between adjacent light-emitting devices 130) (not shown).
  • Light-emitting device 130R has conductor 112a, conductor 126a on conductor 112a, and conductor 129a on conductor 126a. Conductors 112a, 126a, and 129a can all be called pixel electrodes, or some of them can be called pixel electrodes.
  • Light-emitting device 130G has conductor 112b, conductor 126b on conductor 112b, and conductor 129b on conductor 126b. As with light-emitting device 130R, conductors 112b, 126b, and conductor 129b can all be called pixel electrodes, or some of them can be called pixel electrodes.
  • Light-emitting device 130B has conductor 112c, conductor 126c on conductor 112c, and conductor 129c on conductor 126c. As with light-emitting device 130R and light-emitting device 130G, conductor 112c, conductor 126c, and conductor 129c may all be referred to as pixel electrodes, or some of them may be referred to as pixel electrodes.
  • the conductors 112a to 112c and the conductors 126a to 126c may be, for example, a conductive layer that functions as a reflective electrode.
  • a conductor with high reflectivity to visible light for example, silver, aluminum, or an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film) may be applied.
  • the conductors 112a to 112c and the conductors 126a to 126c may be, for example, a laminated film of aluminum sandwiched between a pair of titanium films (a laminated film in the order of Ti, Al, and Ti), or a laminated film of silver sandwiched between a pair of indium tin oxide films (a laminated film in the order of ITO, Ag, and ITO).
  • a conductive layer functioning as a reflective electrode may be used for the conductors 112a to 112c, and a conductor having high light-transmitting properties may be used for the conductors 126a to 126c.
  • Examples of conductors having high light-transmitting properties include an alloy of silver and magnesium, and indium tin oxide (sometimes referred to as ITO).
  • the conductors 129a to 129c can be, for example, a conductive layer that functions as a transparent electrode.
  • the conductive layer that functions as a transparent electrode can be, for example, the above-mentioned conductor with high light-transmitting properties.
  • microcavity structure (microresonator structure) may be provided in the light-emitting device 130, which will be described in detail later.
  • the microcavity structure refers to a structure in which the distance between the bottom surface of the light-emitting layer and the top surface of the lower electrode is set to a thickness according to the wavelength of the color of light emitted by the light-emitting layer.
  • a conductive material that is light-transmitting and light-reflective for the conductors 129a to 129c which are the upper electrodes (common electrodes)
  • a conductive material that is light-reflective for the conductors 112a to 112c and conductors 126a to 126c which are the lower electrodes (pixel electrodes).
  • the microcavity structure refers to a structure in which the optical distance between the lower electrode and the light-emitting layer is adjusted to (2n-1) ⁇ /4 (where n is a natural number greater than or equal to 1, and ⁇ is the wavelength of the light emission to be amplified).
  • n a natural number greater than or equal to 1
  • ⁇ the wavelength of the light emission to be amplified.
  • the conductor 112a is connected to the conductor 596 embedded in the insulator 594 through an opening provided in the insulator 599.
  • the end of the conductor 126a is located outside the end of the conductor 112a.
  • the end of the conductor 126a and the end of the conductor 129a are aligned or approximately aligned.
  • the conductor 112b in the light-emitting device 130G and the conductor 112b in the light-emitting device 130B are similar to the conductor 112a in the light-emitting device 130R, so a detailed description will be omitted. Also, the conductor 126b in the light-emitting device 130G and the conductor 126b in the light-emitting device 130B are similar to the conductor 126a in the light-emitting device 130R, so a detailed description will be omitted.
  • the conductor 129b in the light-emitting device 130G and the conductor 129c in the light-emitting device 130B are similar to the conductor 129a in the light-emitting device 130R, so a detailed description will be omitted.
  • Conditions are formed in conductor 112a, conductor 112b, and conductor 112c so as to cover the openings provided in insulator 599.
  • Layer 128 is embedded in the depressions.
  • the layer 128 has a function of planarizing the recesses of the conductors 112a to 112c.
  • Conductors 126a to 126c that are electrically connected to the conductors 112a to 112c are provided on the conductors 112a to 112c and on the layer 128. Therefore, the regions that overlap with the recesses of the conductors 112a to 112c can also be used as light-emitting regions, and the aperture ratio of the pixel can be increased.
  • Layer 128 may be an insulating layer or a conductive layer.
  • Various inorganic insulating materials, organic insulating materials, and conductive materials can be used as appropriate for layer 128.
  • layer 128 is preferably formed using an insulating material.
  • an insulating layer containing an organic material can be suitably used.
  • acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins can be applied to layer 128.
  • a photosensitive resin can be used for layer 128. Examples of photosensitive resins include positive-type materials and negative-type materials.
  • layer 128 By using a photosensitive resin, layer 128 can be manufactured by only the steps of exposure and development, and the influence of dry etching or wet etching on the surfaces of conductors 112a, 112b, and 112c can be reduced. In addition, by forming layer 128 using a negative photosensitive resin, layer 128 can sometimes be formed using the same photomask (exposure mask) as the photomask used to form the opening in insulator 599.
  • FIG. 77 shows an example in which the top surface of layer 128 has a flat portion
  • the shape of layer 128 is not particularly limited.
  • the top surface of layer 128 may have a shape that has a concave curved surface at the center and its vicinity in a cross-sectional view.
  • layer 128 may have a shape that has a convex curved surface at the center and its vicinity in a cross-sectional view.
  • layer 128 may have a shape that has a concave curved surface and a convex curved surface at the center and its vicinity.
  • Light-emitting device 130R has a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114.
  • Light-emitting device 130G has a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114.
  • Light-emitting device 130B has a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.
  • the first layer 113a is formed so as to cover the upper and side surfaces of the conductor 126a and the upper and side surfaces of the conductor 129a.
  • the second layer 113b is formed so as to cover the upper and side surfaces of the conductor 126b and the upper and side surfaces of the conductor 129b.
  • the third layer 113c is formed so as to cover the upper and side surfaces of the conductor 126c and the upper and side surfaces of the conductor 129c.
  • the entire area in which the conductors 126a, 126b, and 126c are provided can be used as the light-emitting area of the light-emitting device 130R, the light-emitting device 130G, and the light-emitting device 130B, thereby increasing the aperture ratio of the pixel.
  • first layer 113a and common layer 114 can be collectively referred to as the EL layer.
  • second layer 113b and common layer 114 can be collectively referred to as the EL layer.
  • third layer 113c and common layer 114 can be collectively referred to as the EL layer.
  • the configuration of the light-emitting device of this embodiment may be a single structure or a tandem structure.
  • the first layer 113a, the second layer 113b, and the third layer 113c are processed into an island shape by photolithography. Therefore, the angle between the top surface and the side surface of each of the first layer 113a, the second layer 113b, and the third layer 113c at their ends is close to 90 degrees.
  • an organic film formed using FMM Fine Metal Mask
  • the top surface is formed in a slope shape over a range of 1 ⁇ m to 10 ⁇ m, for example, resulting in a shape in which it is difficult to distinguish between the top surface and the side surface.
  • the first layer 113a, the second layer 113b, and the third layer 113c have a clear distinction between the top and side surfaces.
  • one side surface of the first layer 113a and one side surface of the second layer 113b are arranged opposite each other. This is the same for any combination of the first layer 113a, the second layer 113b, and the third layer 113c.
  • the first layer 113a, the second layer 113b, and the third layer 113c each have at least a light-emitting layer.
  • the first layer 113a has a light-emitting layer that emits red light
  • the second layer 113b has a light-emitting layer that emits green light
  • the third layer 113c has a light-emitting layer that emits blue light.
  • each light-emitting layer may be of a color other than cyan, magenta, yellow, or white.
  • the first layer 113a, the second layer 113b, and the third layer 113c preferably have a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer.
  • the surfaces of the first layer 113a, the second layer 113b, and the third layer 113c may be exposed during the manufacturing process of the display device, so by providing a carrier transport layer on the light-emitting layer, it is possible to prevent the light-emitting layer from being exposed to the outermost surface and reduce damage to the light-emitting layer. This can improve the reliability of the light-emitting device.
  • the common layer 114 has, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or may have a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting devices 130R, 130G, and 130B.
  • the common electrode 115 is shared by the light-emitting devices 130R, 130G, and 130B. As shown in FIG. 77, the common electrode 115 shared by the multiple light-emitting devices is electrically connected to a conductor included in the connection portion 140.
  • the insulator 125 preferably has a function as a barrier insulating layer against water and/or oxygen.
  • the insulator 125 preferably has a function of suppressing the diffusion of water and/or oxygen.
  • the insulator 125 preferably has a function of capturing or fixing (also called gettering) water and/or oxygen.
  • the insulator 125 has a function as a barrier insulating layer or a gettering function, it is possible to suppress the intrusion of impurities (typically, water and/or oxygen) that may diffuse from the outside into each light-emitting device. With this configuration, a highly reliable light-emitting device and further a highly reliable display panel can be provided.
  • the insulator 125 has a low impurity concentration. This can prevent impurities from entering the EL layer from the insulator 125 and causing deterioration of the EL layer. Furthermore, by lowering the impurity concentration in the insulator 125, it is possible to improve the barrier properties against water and/or oxygen. For example, it is desirable that the insulator 125 has a sufficiently low hydrogen concentration or a sufficiently low carbon concentration, or preferably both.
  • an insulating layer containing an organic material can be suitably used.
  • the organic material it is preferable to use a photosensitive organic resin, for example, a photosensitive resin composition containing an acrylic resin.
  • the viscosity of the material of the insulator 127 may be 1 cP or more and 1500 cP or less, and preferably 1 cP or more and 12 cP or less. By setting the viscosity of the material of the insulator 127 within the above range, the insulator 127 having a tapered shape, which will be described later, can be formed relatively easily.
  • acrylic resin does not only refer to polymethacrylic acid ester or methacrylic resin, but may refer to all acrylic polymers in a broad sense.
  • a tapered shape refers to a shape in which at least a portion of the side of the structure is inclined with respect to the substrate surface.
  • the structure it is preferable for the structure to have a region in which the angle between the inclined side and the substrate surface (also called the taper angle) is less than 90°.
  • the insulator 127 may have a tapered shape on the side as described later, and the organic material that can be used for the insulator 127 is not limited to the above.
  • the insulator 127 may be made of acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, or precursors of these resins.
  • the insulator 127 may be made of organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin.
  • the insulator 127 may be made of a photoresist, for example, as a photosensitive resin.
  • the photosensitive resin may be a positive material or a negative material.
  • the insulator 127 may be made of a material that absorbs visible light. By having the insulator 127 absorb the light emitted from the light-emitting device, it is possible to suppress leakage of light from the light-emitting device to an adjacent light-emitting device via the insulator 127 (stray light). This makes it possible to improve the display quality of the display panel. In addition, since the display quality can be improved without using a polarizing plate in the display panel, it is possible to make the display panel lighter and thinner.
  • Materials that absorb visible light include materials containing pigments such as black, materials containing dyes, resin materials with light absorbing properties (e.g., polyimide), and resin materials that can be used in color filters (color filter materials).
  • resin materials with light absorbing properties e.g., polyimide
  • color filter materials resin materials that can be used in color filters
  • by mixing three or more colors of color filter materials it is possible to create a resin layer that is black or close to black.
  • the insulator 127 can be formed using a wet film formation method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • a wet film formation method such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife method, slit coating, roll coating, curtain coating, or knife coating.
  • the insulator 127 is formed at a temperature lower than the heat resistance temperature of the EL layer.
  • the substrate temperature when forming the insulator 127 is typically 200°C or less, preferably 180°C or less, more preferably 160°C or less, more preferably 150°C or less, and more preferably 140°C or less.
  • the structure of the insulator 127 etc. will be explained using the structure of the insulator 127 between the light-emitting device 130R and the light-emitting device 130G as an example. The same can be said about the insulator 127 between the light-emitting device 130G and the light-emitting device 130B, and the insulator 127 between the light-emitting device 130B and the light-emitting device 130R.
  • the end of the insulator 127 on the second layer 113b may be used as an example below, but the same can be said about the end of the insulator 127 on the first layer 113a and the end of the insulator 127 on the third layer 113c.
  • Insulator 127 preferably has a tapered shape with a taper angle ⁇ 1 on the side in a cross-sectional view of the display device.
  • Taper angle ⁇ 1 is the angle between the side of insulator 127 and the substrate surface.
  • it is not limited to the substrate surface, and may be the angle between the top surface of the flat portion of insulator 125 or the top surface of the flat portion of second layer 113b and the side of insulator 127.
  • the side of insulator 125 and the side of mask layer 118a may also be tapered.
  • the taper angle ⁇ 1 of the insulator 127 is less than 90°, preferably 60° or less, and more preferably 45° or less.
  • the upper surface of the insulator 127 preferably has a convex curved shape.
  • the convex curved shape of the upper surface of the insulator 127 preferably bulges gently toward the center.
  • the convex curved portion at the center of the upper surface of the insulator 127 preferably has a shape that smoothly connects to the tapered portion at the end of the side surface.
  • the insulator 127 is also formed in the region between the two EL layers (e.g., the region between the first layer 113a and the second layer 113b). At this time, a part of the insulator 127 is disposed in a position sandwiched between a side edge of one EL layer (e.g., the first layer 113a) and a side edge of the other EL layer (e.g., the second layer 113b).
  • one end of the insulator 127 overlaps with the conductor 126a that functions as a pixel electrode, and the other end of the insulator 127 overlaps with the conductor 126b that functions as a pixel electrode.
  • the end of the insulator 127 can be formed on a roughly flat region of the first layer 113a (second layer 113b). Therefore, it becomes relatively easy to process the tapered shape of the insulator 127 as described above.
  • the insulator 127 As described above, by providing the insulator 127, etc., it is possible to prevent the formation of discontinuities and locally thin areas in the common layer 114 and common electrode 115 from the roughly flat area of the first layer 113a to the roughly flat area of the second layer 113b. This makes it possible to prevent connection failures caused by discontinuities and increases in electrical resistance caused by locally thin areas in the common layer 114 and common electrode 115 between the light-emitting devices.
  • the display device of this embodiment can narrow the distance between light-emitting devices.
  • the distance between light-emitting devices, between EL layers, or between pixel electrodes can be less than 10 ⁇ m, 8 ⁇ m or less, 5 ⁇ m or less, 3 ⁇ m or less, 2 ⁇ m or less, 1 ⁇ m or less, 500 nm or less, 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less.
  • the display device of this embodiment has an area where the distance between two adjacent island-shaped EL layers is 1 ⁇ m or less, preferably an area where the distance is 0.5 ⁇ m (500 nm) or less, and more preferably an area where the distance is 100 nm or less. In this way, by narrowing the distance between each light-emitting device, a display device with high definition and large aperture ratio can be provided.
  • a protective layer 131 is provided on the light-emitting device 130.
  • the protective layer 131 is a film that functions as a passivation film that protects the light-emitting device 130.
  • impurities such as water and oxygen
  • aluminum oxide, silicon nitride, or silicon oxynitride can be used for the protective layer 131.
  • the protective layer 131 and the substrate 110 are bonded via an adhesive layer 107.
  • a solid sealing structure or a hollow sealing structure can be applied to seal the light-emitting device.
  • the space between the substrate 310 and the substrate 110 is filled with an adhesive layer 107, and a solid sealing structure is applied.
  • the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied.
  • the adhesive layer 107 may be provided so as not to overlap with the light-emitting device.
  • the space may also be filled with a resin different from the adhesive layer 107 provided in a frame shape.
  • various types of curing adhesives can be used, such as ultraviolet-curing photocuring adhesives, reaction-curing adhesives, heat-curing adhesives, and anaerobic adhesives.
  • these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins.
  • epoxy resins with low moisture permeability are preferred.
  • Two-part mixed resins may also be used.
  • An adhesive sheet may also be used.
  • the display device of one embodiment of the present invention may be a bottom emission type in which light emitted from the light-emitting device is emitted toward the substrate 310, rather than a top emission type.
  • a substrate that has high transparency to visible light may be selected as the substrate 310.

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