WO2024109750A1

WO2024109750A1 - Read circuit for memory

Info

Publication number: WO2024109750A1
Application number: PCT/CN2023/133022
Authority: WO
Inventors: 郝午阳; 熊保玉; 余赣湘
Original assignee: 浙江驰拓科技有限公司
Priority date: 2022-11-21
Filing date: 2023-11-21
Publication date: 2024-05-30
Also published as: CN118057530A

Abstract

The present disclosure provides a read circuit for a memory, comprising: a sense amplifier, a read array connected to the sense amplifier, and a reference circuit. The read array comprises a plurality of storage units located in one column. The reference circuit comprises a reference resistor and a reference array, and the reference array is used for matching a leakage current generated, by a storage unit that is not enabled, during a read operation of the read array.

Description

Memory read circuit

This disclosure claims priority to a Chinese patent application filed with the Chinese Patent Office on November 21, 2022, with application number 2022114635508 and application name “READ CIRCUIT OF MEMORY,” the entire contents of which are incorporated by reference in this disclosure.

Technical Field

The present disclosure relates to the technical field of integrated circuit design, and in particular to a read circuit of a memory.

Background technique

Reading the information stored in MRAM is achieved by detecting the resistance of the memory cell. The resistance of the memory cell has two states, high resistance state Rap ("AP" state) or low resistance state Rp ("P" state). When performing a read operation, by applying a clamping voltage (Vclamp), the resistance of the memory cell will generate a read current pulse Idata, and the reference resistor Rref will generate a reference current Iref by applying a reference voltage (Vref). The sensitive amplifier can identify whether the memory cell is in a high resistance state or a low resistance state by comparing the read current Idata and the reference current Iref, and can read "1" or "0".

In the process of implementing the present disclosure, the inventors found that there are at least the following technical problems in the related art:

For the memory cells located in the same column, only one of them is turned on during the read operation, and the other memory cells are in the off state. However, due to the existence of subthreshold leakage, a small amount of leakage current Ileak still passes through the memory cells in the off state, and the higher the temperature, the greater the leakage current. As shown in Figure 1, the data terminal current Iap_high in the ap state at high temperature will be greater than the data terminal current Iap_low in the ap state at low temperature due to the influence of leakage. However, the reference terminal current Iref basically does not change with the change of temperature. This will cause the read window at high temperature to be reduced, or even disappear, affecting the read yield.

Summary of the invention

In order to solve the above problems, the present disclosure provides a read circuit of a memory, which can reduce the influence of leakage current on the read window.

The present disclosure provides a memory read circuit, comprising:

A read array including a plurality of memory cells in a column;

Clamp control MOS tube, the gate terminal of the clamp control MOS tube inputs a clamp voltage for Generating a data terminal current on the read array;

A reference circuit, comprising a reference resistor and a reference array, wherein the reference array is used to match the leakage current generated by the unopened memory cells of the read array during a read operation;

A reference control MOS tube, wherein a reference voltage is input to a gate terminal of the reference control MOS tube so as to generate a reference terminal current on the reference circuit;

A sensitive amplifier, one end of which is connected to the read array through the clamp control MOS tube, and the other end of which is connected to the reference circuit through the reference control MOS tube, and the sensitive amplifier is used to output a reading result by comparing the data end current with the reference end current.

In some embodiments of the present application, each of the storage units includes a magnetic tunnel junction and a switch tube connected to the magnetic tunnel junction.

In some embodiments of the present application, the reference array includes a plurality of memory cells located in a column, the memory cell structure of the reference array is the same as the memory cell structure of the read array, the number of memory cells included in the reference array is one less than the number of memory cells included in the read array, the bit line of the reference array is connected to the reference control MOS tube, and the source line of the reference array is connected to the ground line.

In some embodiments of the present application, the reference resistor includes a reference unit and a first resistor, the reference unit is implemented by a memory cell, the structure of the reference unit is the same as the memory cell structure of the read array, the magnetic tunnel junction state in the reference unit is a parallel state, the switch state in the reference unit is controlled by a reference word line, and the reference unit and the reference array share a bit line and a source line;

The first resistor is connected between a source line and a ground line of the reference array, and together with the reference unit forms a reference resistor for a read operation.

In some embodiments of the present application, the resistance of the first resistor is R, and satisfies Rp＜Rp+R＜Rap, where Rp represents the resistance of the magnetic tunnel junction in a parallel state, and Rap represents the resistance of the magnetic tunnel junction in an antiparallel state.

In some embodiments of the present application, the reference array and the reference cell are implemented by a redundant column of a storage array, the number of storage cells included in the redundant column is the same as the number of storage cells included in the read array, and the structure of the storage cells included in the redundant column is the same as the structure of the storage cells included in the read array, any one storage cell of the redundant column serves as the reference cell, and the other storage cells of the redundant column except the reference cell constitute the reference array.

In some embodiments of the present application, the read circuit of the memory further includes:

A first branch switch connected between the clamp control MOS tube and the bit line of the read array;

A second branch switch connected between a source line and a ground line of the read array;

The third branch switch is connected between the bit line of the reference array and the reference control MOS tube.

In some embodiments of the present application, the reference resistor includes a second resistor, which is connected between the reference control MOS tube and a ground line to constitute a reference resistor for a read operation.

In some embodiments of the present application, the resistance of the second resistor is between Rp and Rap, where Rp represents the resistance of the magnetic tunnel junction in a parallel state, and Rap represents the resistance of the magnetic tunnel junction in an antiparallel state.

A fourth branch switch connected between the clamp control MOS tube and the bit line of the read array;

a fifth branch switch connected between a source line and a ground line of the read array;

a sixth branch switch connected between the bit line of the reference array and the reference control MOS tube;

The seventh branch switch is connected between the second resistor and the reference control MOS tube.

The memory read circuit provided by the present disclosure adds a reference array in the reference circuit. The reference array can match the leakage generated by the unactivated memory cells in the read array, thereby reducing the influence of the leakage on the read window.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a related art showing a reduction in a read window due to leakage current at high temperature;

FIG2 is a schematic diagram of the structure of a read circuit of a memory provided in some embodiments of the present disclosure;

FIG3 is a schematic diagram showing the principle of implementing leakage current matching using the read circuit of the memory of FIG2 ;

FIG4 is a schematic diagram of the structure of a read circuit of a memory provided in some other embodiments of the present disclosure;

FIG5 is a schematic diagram showing the principle of implementing leakage current matching using the read circuit of the memory of FIG4 ;

FIG6 is a schematic diagram showing the effect of applying the present disclosure to reduce the influence of leakage current on the read window.

The above drawings include the following reference numerals:
101, read array; 102, reference array; 103, reference cell.

Detailed ways

In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "comprises" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

In the present disclosure, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the drawings. These terms are mainly used to better describe the present disclosure and its embodiments, and are not used to limit the indicated devices, elements or components to have a specific orientation, or to be constructed and operated in a specific orientation.

In addition, some of the above terms may be used to express other meanings in addition to indicating orientation or positional relationship. For example, the term "on" may also be used to express a certain dependency or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in this disclosure can be understood according to specific circumstances.

In addition, the terms "installed", "set", "provided with", "connected", "connected", and "socketed" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, elements, or components. For those of ordinary skill in the art, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

In conjunction with the accompanying drawings, some embodiments of the present disclosure are described in detail below. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

The present disclosure provides a memory read circuit, the read circuit comprising: a read array, a clamp control MOS tube, a reference circuit, a reference control MOS tube and a sense amplifier, wherein:

The read array includes a plurality of memory cells located in a column;

The clamping control MOS tube gate input clamping voltage is used to generate data terminal current on the read array;

The reference circuit includes a reference resistor and a reference array, the reference array being used to match the leakage current generated by the unopened memory cells of the read array during the read operation;

The reference voltage is input to the gate terminal of the reference control MOS tube, and is used to generate a reference terminal current on the reference circuit;

One end of the sensitive amplifier is connected to the read array through a clamp control MOS tube, and the other end of the sensitive amplifier is connected to the reference circuit through a reference control MOS tube. The sensitive amplifier is used to compare the data end. Current and reference terminal current, output reading results.

As some implementation methods, FIG. 2 shows a schematic diagram of a circuit structure of a read circuit of a memory. As shown in FIG. 2 , the read circuit of the memory includes: a read array 101, a clamp control MOS tube M1, a reference circuit, a reference control MOS tube M2 and a sense amplifier SA, wherein:

The read array 101 may be any column of the memory array, including 2 ⁿ (n is a positive integer) memory cells located in one column, each memory cell including a magnetic tunnel junction and a switch connected to the magnetic tunnel junction. The switch state of the switch of each memory cell is controlled by a corresponding WL<2 ⁿ -1:0> signal.

The gate terminal of the clamp control MOS tube M1 inputs a clamp voltage Vclamp, which is used to generate a data terminal current on the read array.

The reference circuit includes a reference resistor and a reference array 102. The reference array 102 is used to match the leakage current generated by the non-enabled memory cells of the read array during a read operation.

A reference voltage Vref is input to the gate terminal of the reference control MOS tube M2 to generate a reference terminal current on the reference circuit;

One end of the sense amplifier SA is connected to the read array 101 through the clamp control MOS tube M1, and the other end of the sense amplifier SA is connected to the reference circuit through the reference control MOS tube M2. The sense amplifier is used to output the reading result by comparing the data terminal current and the reference terminal current.

Specifically, in these embodiments, the reference array 102 includes a plurality of memory cells located in a column, the memory cell structure of the reference array 102 is the same as the memory cell structure of the read array 101, the number of memory cells included in the reference array 102 is one less than the number of memory cells included in the read array 101, the bit line of the reference array 102 is connected to the reference control MOS tube M2, and the source line of the reference array is connected to the ground line. As for the state of the magnetic tunnel junction in each memory cell of the reference array 102, there is no special limitation, and it can be a parallel state or an anti-parallel state.

In these embodiments, the reference resistor includes a reference unit 103 and a first resistor RINT. The reference unit 103 is implemented by a memory unit. The structure of the reference unit 103 is the same as the memory unit structure of the read array 101. The magnetic tunnel junction state in the reference unit 103 is a parallel state. The switch state in the reference unit 103 is controlled by a reference word line WL_REF. The reference unit 103 and the reference array 102 share a bit line and a source line. The first resistor RINT is connected between the source line and the ground line of the reference array, and together with the reference unit 103, it constitutes a reference resistor for the read operation. The resistance value of the first resistor RINT is R, and satisfies Rp＜Rp+R＜Rap, Rp represents the resistance of the magnetic tunnel junction in the parallel state, and Rap represents the resistance of the magnetic tunnel junction in the antiparallel state.

As shown in FIG. 2 , the reference array 102 and the reference cell 103 can be implemented by a redundant column of a storage array. The redundant column contains the same number of storage cells as the read array, and the structure of the storage cells is similar. Similarly, any one memory cell in the redundant column serves as the reference cell 103 , and the other memory cells in the redundant column except the reference cell constitute the reference array 102 .

In addition, as shown in FIG. 2 , the read circuit in these embodiments further includes:

The first branch switch K1 is connected between the clamp control MOS tube M1 and the bit line of the read array 101;

The second branch switch K2 is connected between the source line and the ground line of the read array 101;

The third branch switch K3 is connected between the bit line of the reference array 102 and the reference control MOS transistor M2. Through the branch switch, different read arrays can be selected, and the data of the column to which it is connected is read.

For the memory read circuit provided in these implementations, there is no need to change the array structure, and a redundant column of the memory array is directly used to implement the reference unit and the reference array. Only an additional resistor needs to be connected in series, which is simple to implement and has strong applicability.

To illustrate the technical effect of the embodiment of the present disclosure, with reference to FIG3 , the read array is composed of 1024 memory cells, and the switch state of the switch tube of each memory cell is controlled by the corresponding WL<1023:0> signal. The control signals of the reference array are all turned off, WL_REF controls the switch of the reference cell, and the MTJ state in the reference cell is Rp state.

During the read operation, Vref, Vclamp and branch switches K1, K2, and K3 are turned on, and the storage cells to be read are turned on by controlling WL<1023>. At the same time, WL_REF is turned on, and the leakage of the unopened storage cells in the read array and the leakage of the reference array can match each other, avoiding the difference in current between the data end and the reference end due to leakage, and solving the problem of reduced read window.

On the other hand, as some other embodiments, FIG. 4 shows a schematic diagram of a circuit structure of a read circuit of a memory, which is different from the structure of FIG. 2 in that the reference resistor is implemented differently. In these embodiments, the reference resistor includes a second resistor Rref, which is connected between a reference control MOS tube and a ground line to constitute a reference resistor for a read operation. The resistance value of the second resistor Rref is between Rp and Rap, where Rp represents the resistance of the magnetic tunnel junction in a parallel state, and Rap represents the resistance of the magnetic tunnel junction in an antiparallel state.

In addition, as shown in FIG. 4 , the read circuit in these embodiments further includes:

The fourth branch switch K4 is connected between the clamp control MOS tube and the bit line of the read array;

A fifth branch switch K5 is connected between a source line and a ground line of the read array;

The sixth branch switch K6 is connected between the bit line of the reference array and the reference control MOS tube;

The seventh branch switch K7 is connected between the second resistor and the reference control MOS tube.

For the read circuit of the memory provided in these embodiments, there is no need to design a reference resistor, and the reference array only needs one less storage unit than the read array, which is simple to implement and has strong applicability.

To illustrate the technical effect of the embodiment of the present disclosure, referring to Figure 5, the read array is composed of 1024 storage units, and the switch state of each storage unit is controlled by the corresponding WL<1023:0> signal. The control signals of the reference array are all turned off.

During the read operation, Vref, Vclamp and branch switches K4, K5, K6, and K7 are turned on, and the storage cells to be read are turned on by controlling WL<1023>. The leakage of the unopened storage cells in the read array and the leakage of the reference array can match each other, avoiding the difference in current between the data terminal and the reference terminal due to leakage, and solving the problem of reduced read window. As shown in FIG6, after applying the read circuit of the embodiment of the present disclosure, the read window will not be reduced at high temperature.

The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A memory read circuit, comprising:

A read array including a plurality of memory cells in a column;

A clamp control MOS tube, wherein a clamp voltage is input to a gate terminal of the clamp control MOS tube to generate a data terminal current on the read array;

A reference circuit, comprising a reference resistor and a reference array, wherein the reference array is used to match the leakage current generated by the unopened memory cells of the read array during a read operation;

A reference control MOS tube, a reference voltage is input to the gate terminal of the reference control MOS tube, and is used to generate a reference terminal current on the reference circuit;

A sensitive amplifier, one end of which is connected to the read array through the clamp control MOS tube, and the other end of which is connected to the reference circuit through the reference control MOS tube, and the sensitive amplifier is used to output a reading result by comparing the data end current with the reference end current.
The memory read circuit according to claim 1, wherein each of the memory cells comprises a magnetic tunnel junction and a switch connected to the magnetic tunnel junction.
The memory read circuit according to claim 1, wherein the reference array comprises a plurality of memory cells located in a column, the memory cell structure of the reference array is the same as the memory cell structure of the read array, the number of memory cells included in the reference array is one less than the number of memory cells included in the read array, the bit line of the reference array is connected to the reference control MOS tube, and the source line of the reference array is connected to the ground line.
The memory read circuit according to claim 3, wherein:

The reference resistor includes a reference unit and a first resistor. The reference unit is implemented by a memory unit. The structure of the reference unit is the same as that of the memory unit of the read array. The magnetic tunnel junction state in the reference unit is a parallel state. The state of the switch tube in the reference unit is controlled by a reference word line. The reference unit and the reference array share a bit line and a source line.

The first resistor is connected between a source line and a ground line of the reference array, and together with the reference unit forms a reference resistor for a read operation.
The memory read circuit according to claim 4, wherein the resistance of the first resistor is R, and satisfies Rp＜Rp+R＜Rap, Rp represents the resistance of the magnetic tunnel junction in a parallel state, and Rap represents the resistance of the magnetic tunnel junction in an antiparallel state.
The memory read circuit according to claim 4, wherein the reference array and the reference cell are implemented by a redundant column of a memory array, the number of memory cells included in the redundant column is the same as the number of memory cells included in the read array, and the structure of the memory cells included in the redundant column is the same as the structure of the memory cells included in the read array, any one memory cell in the redundant column is used as the reference cell, and the other memory cells in the redundant column except the reference cell constitute the reference array.
The memory read circuit according to claim 4, wherein the memory read circuit further comprises:

A first branch switch connected between the clamp control MOS tube and the bit line of the read array;

A second branch switch connected between a source line and a ground line of the read array;

The third branch switch is connected between the bit line of the reference array and the reference control MOS tube.
The memory read circuit according to claim 3, wherein the reference resistor comprises a second resistor, and the second resistor is connected between the reference control MOS tube and the ground line to constitute a reference resistor for the read operation.
The memory read circuit according to claim 8, wherein the resistance of the second resistor is between Rp and Rap, Rp represents the resistance of the magnetic tunnel junction in a parallel state, and Rap represents the resistance of the magnetic tunnel junction in an antiparallel state.
The memory read circuit according to claim 8, wherein the memory read circuit further comprises:

A fourth branch switch connected between the clamp control MOS tube and the bit line of the read array;

a fifth branch switch connected between a source line and a ground line of the read array;

a sixth branch switch connected between the bit line of the reference array and the reference control MOS tube;

The seventh branch switch is connected between the second resistor and the reference control MOS tube.