JPH04241298A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain the memory suitable for a high integration by preventing lowering in the continuity current of a memory cell caused by the large capacitance of semiconductor memory. CONSTITUTION:By providing a boosting circuit 9, a power source voltage is boosted, and a voltage having a higher level than the power source voltage is generated. Then, the higher voltage is supplied to a X decoder 3 and a Y decoder 7, making output from the X decoder and the Y decoder higher than the power source potential.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, particularly a mask ROM type semiconductor memory device.

0002

2. Description of the Related Art Mask ROMs have been used as data memories and, more recently, as kanji fonts, and have always been required to have a large capacity. For this reason, various improvements have been made to the memory cell configuration. For example, in the past, it was common to have a configuration in which memory cells were arranged in parallel between a bit line and a ground potential called a NOR type, but recently, a configuration called a NAND type where multiple memory cells were arranged in series between a bit line and a ground potential has become common. A device having a configuration arranged in the following has been used.

FIG. 3 is a block diagram of the memory periphery of a mask ROM using this NAND type memory cell. In the figure, 1 indicates an address signal in the X direction (X address signal ), 2 is an input circuit provided for the X address signal 1, 3 is an X decoder circuit for selecting one word line corresponding to the set X address signal, and 4 is a NAND type memory cell arranged in a matrix. The arranged memory cell array, 5 is a Y-direction address signal (Y address signal) input from the outside to select a bit line, 6 is an input circuit provided for the Y address signal 5, 7 is a set Y address A Y decoder circuit 8 is for selecting one bit line corresponding to a signal, and a select gate 8 is for making the bit line selected based on the Y address signal 5 readable. Before explaining the operation, the configuration of the NAND memory will be explained here to facilitate understanding.

FIG. 2 shows one NAND type memory, and in the figure, 10 is a bit line connected to a read circuit (not shown). 11 is the select gate, 12
is the output signal of the Y decoder 7, which makes only the select gate 11 of the selected bit line conductive and selects the bit line. Reference numerals 13, 15, and 17 each represent a memory transistor constituting a memory cell, and the threshold value thereof is usually set in accordance with the stored information. Further, each memory transistor 13, 15, 17 is connected in series within one bit line 10 as shown. This is NAND
This is why it is called a kata. Each word line 14, 16, 18
A word line selection signal is input to each of the memory cells, and the memory cells operate to select one of the memory cells connected in series. Reference numeral 19 indicates one NAND type memory cell component.

Next, the operation will be explained with reference to FIGS. 2 and 3. First, in a readable state, X address 1 and Y address 5 are input from the outside. Then, internal address signals are generated in input circuits 2 and 6, which are input to X decoder 3 and Y decoder 7. X decoder 3 selects one word line from a plurality of word lines, and Y decoder 7 A selection signal for selecting one of the bit lines is generated and the select gate 8
is input.

As described above, one predetermined memory cell on the memory cell array 4 is selected. To explain this in more detail with reference to FIG. 2, by word line selection, for example, only the word line (I) 14 is selected. becomes "L" level, and the other word lines 16 and 18 become "H" level (
(same level as the applied power supply voltage). Note that when storing information “0” in NAND type memory, the threshold value of the memory cell is set to an enhancement type (Vth>0), and information “0” is stored in the NAND type memory.
1", the threshold value of the memory is set to be a depression type (Vth<0), so the word line potential is selected when it goes to "L" level as described above. In addition, the bit line selection signal 12 becomes "H" level (same level as the applied power supply voltage), and the select gate 11 becomes conductive.Therefore, if the Vth of the memory cell 13 is positive, the memory cell 13 becomes non-conductive. , and when Vth is negative, it becomes conductive.Since the gate signals of the other memory cells forming the NAND configuration are at the "H" level, they become conductive regardless of whether Vth of each memory cell is positive or negative. Therefore, depending on the information stored in the memory cell 13, whether or not a current is generated in the bit line 10 is generated, and the bit line 10 is electrically connected to a readout circuit (not shown) by conduction of the select gate 11, so that the memory The information stored in the cell 13 is output to the outside.

[0007]

[Problem to be Solved by the Invention] Since the conventional semiconductor memory device (mask ROM) is configured as described above,
In particular, in the case of a NAND mask ROM, the memory transistors are connected in series, so the series resistance is large and the conduction current when the memory cell is conductive is small.In particular, as the number of NAND stages is increased and higher integration is aimed at, the conduction current becomes even smaller and the conduction current becomes smaller. When the current becomes small, there are problems such as unstable operation and slow operation speed.

The present invention has been made to solve the above-mentioned problems, and provides a mask ROM that can operate stably even when the number of NAND stages of memory cells increases and that operates at high speed.
The purpose is to obtain.

[0009]

[Means for Solving the Problems] A semiconductor memory device according to the present invention includes a booster circuit that generates an internal power supply level higher than the level of an externally supplied power supply voltage on the same substrate, and outputs the output of the booster circuit. This high voltage is used as the signal level for selecting the bit line and word line of the memory cell.

0010

[Operation] In this invention, a booster circuit is provided on the same substrate, the booster circuit generates an internal power supply level higher than the level of the power supply voltage supplied from the outside, and this high voltage is applied to the bit line and word line of the memory cell. Since it is used as a line selection signal level, the current when the memory cell is turned on can be increased.

[0011]

[Embodiment] FIG. 1 shows a mask ROM according to an embodiment of the present invention.
3 is a block diagram of the surroundings of a NAND type memory, in which the same reference numerals as in FIG. X decoder 3 with internal power supply
and is used for the output section of the Y decoder 7. In addition, NAN
The constituent parts of the D-type memory cell are as described in the conventional example.

Next, the operation will be explained using FIGS. 1 and 2. First, in the read-enabled state, the booster circuit 9 enters the operating state upon receiving the read control signal, generates an internal power supply with a higher voltage than the externally applied power supply voltage, and this internal power supply
It is supplied as power to the output circuit sections of the decoder 3 and Y decoder 7.

Next, X address 1 and Y address 5 are input from the outside. Then, internal address signals are generated in input circuits 2 and 6, which are input to X decoder 3 and Y decoder 7. A selection signal for selecting a bit line is generated and input to the select gate 8. As described above, one predetermined memory cell on the memory cell array 4 is selected.Continuing to explain the above operation in detail with reference to FIG.
) 14 becomes “L” level, and the other word lines 16,
18 becomes the "H" level, which is the same level as the internal power supply generated by boosting the applied power supply voltage by the booster circuit 9. Further, the bit line selection signal 12 also becomes the "H" level, which is the same level as the internal power supply generated by boosting the applied power supply voltage by the booster circuit 9.
The select gate 11 conducts with a conduction resistance that is sufficiently lower than that in the conventional case. Therefore, when the Vth of the memory cell 13 is positive, the memory cell 13 becomes non-conductive, and when Vth is negative, the memory cell 13 becomes conductive. Other memory cells 1 forming a NAND configuration
Since the gate signals of transistors 5 and 17 are boosted to the "H" level, they are conductive under sufficiently lower conduction resistance than the conventional example, regardless of whether Vth is positive or negative. Therefore, depending on the information stored in the memory cell 13, whether or not a current is generated in the bit line is generated, and this bit line is electrically connected to a reading circuit (not shown) by conduction of the select gate 11, so that the memory cell 13 The stored information is output to the outside.

[0014] As mentioned above, the conduction current generated in the bit line 10 when the memory cell 13 is conductive is considerably larger than that in the conventional example because the conduction resistance of the select gate 11 and other NAND memory cells 15 and 17 is reduced. .

As described above, according to this embodiment, the booster circuit 9
, the power supply voltage is boosted by the read control signal to generate an internal power supply, and this is supplied to the output parts of the X decoder 3 and Y decoder 7. It is possible to increase the current when the type memory 19 is conductive, and as a result, even if the device has a large capacity and the number of connected NAND stages (the number of memory transistor stages forming a NAND memory cell) increases, the conduction current can be increased. It is possible to obtain a mask ROM that does not decrease, is capable of stable operation, and has high operating speed.

In the above embodiment, the NAND type mask R
Although the OM has been described, a similar effect can be expected in a NOR type mask ROM as well, if the conduction current becomes smaller due to an increase in capacity.

[0017]

As described above, according to the semiconductor memory device of the present invention, a booster circuit that boosts the power supply voltage and generates a voltage higher than the power supply voltage is provided, and the high voltage that is the output of the circuit is connected to the bit line and Since it is used as a word line selection signal, it is possible to increase the current when the memory is conducting, and to obtain a mask ROM that can operate stably and has a high operating speed even when the degree of integration increases and the number of memory stages increases. It has the effect of being able to

[Brief explanation of the drawing]

FIG. 1: NAN of a mask ROM according to an embodiment of the present invention.
FIG. 2 is a block diagram of a peripheral portion of a D-type memory.

FIG. 2 NAN of mask ROM according to the present invention and conventional example
FIG. 2 is a diagram for explaining the structure and operation of a D-type memory.

FIG. 3 is a block diagram of a peripheral portion of a NAND type memory of a conventional mask ROM.

[Explanation of symbols]

1 X address signal 2 Input circuit 3.X decoder 4 Memory cell array 5 Y address signal 6 Input circuit 7 Y decoder 8 Select gate 9 Boost circuit

Claims (1)

[Claims] 1. A semiconductor having a memory configuration in which a plurality of MOS transistors formed at regular intervals on a semiconductor substrate are connected in series or in parallel, and having a selection circuit for selecting bit lines and word lines of the memory. The storage device is characterized by comprising a booster circuit that boosts the power supply voltage, supplies the boosted circuit output to the bit line and word line selection circuits, and makes these selection circuit outputs at a level higher than the power supply potential. semiconductor storage device.