WO2024109644A1 - 忆阻器阵列的操作方法、数据处理装置 - Google Patents

忆阻器阵列的操作方法、数据处理装置 Download PDF

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WO2024109644A1
WO2024109644A1 PCT/CN2023/132237 CN2023132237W WO2024109644A1 WO 2024109644 A1 WO2024109644 A1 WO 2024109644A1 CN 2023132237 W CN2023132237 W CN 2023132237W WO 2024109644 A1 WO2024109644 A1 WO 2024109644A1
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memristor
row
array
voltage
memristor array
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PCT/CN2023/132237
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English (en)
French (fr)
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吴华强
李嘉宁
揭路
伍冬
姚鹏
潘思宁
高滨
钱鹤
唐建石
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清华大学
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Publication of WO2024109644A1 publication Critical patent/WO2024109644A1/zh

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00

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  • Embodiments of the present disclosure relate to an operating method of a memristor array and a data processing device.
  • each memristor unit in the memristor array adopts a 1T1R (1 transistor 1 memristor) basic unit structure, in which the memristor is connected in series to one electrode (such as the drain) of the transistor.
  • one electrode such as the drain
  • a control voltage is applied to the gate of the transistor to fully open (conduct) the transistor so that the transistor is in the linear region.
  • the transistor is equivalent to a linear resistor.
  • the entire memristor array is equivalent to a resistor network, in which there is a serious voltage drop (IR drop). Therefore, when using the current-sensing quantization output method, the above operation method has very high requirements on the accuracy of the external driver and the quantization circuit (especially the clamping circuit). This ultimately leads to the limited calculation accuracy of the traditional memristor storage and computing, and the difficulty of external circuit design increases, and its area, power consumption and speed become the bottleneck of system performance.
  • At least one embodiment of the present disclosure provides an operating method for a memristor array, wherein the memristor array includes a plurality of rows and columns of memristor units, a word corresponding to each row in the memristor array, and a
  • the memristor array comprises a word line, a bit line corresponding to each row in the memristor array, and a source line corresponding to each column in the memristor array.
  • Each memristor unit comprises a transistor and a memristor. The gate of the transistor is connected to the word line corresponding to the row where the memristor unit is located. The first electrode of the transistor is connected to the source line corresponding to the column where the memristor unit is located.
  • the second electrode of the transistor is connected to the first end of the memristor, and the second end of the memristor is connected to the bit line corresponding to the row where the memristor unit is located.
  • the operation method comprises a matrix-vector multiplication operation, wherein the matrix-vector multiplication operation comprises: applying the input voltages corresponding to the input data of each row in the memristor array to the word lines of each row in the memristor array; applying the source line voltages to the source lines of each column in the memristor array, so that the transistors in each memristor unit in each row in the memristor array are turned on and work in the saturation region; applying the first fixed voltage to the bit lines of each row in the memristor array; and detecting the output current on the source lines of each column in the memristor array to obtain the output result.
  • At least one embodiment of the present disclosure provides a data processing device, comprising: a word line driver, a source line driver, a bit line driver, an output processing circuit, and a memristor array
  • the memristor array comprises a plurality of rows and columns of memristor units, word lines corresponding to each row in the memristor array, bit lines corresponding to each row in the memristor array, and source lines corresponding to each column in the memristor array
  • each memristor unit comprises a transistor and a memristor, a gate of the transistor is connected to the word line corresponding to the row where the memristor unit is located, a first electrode of the transistor is connected to the source line corresponding to the column where the memristor unit is located, a second electrode of the transistor is connected to a first end of the memristor, a second end of the memristor is connected to a bit line corresponding to the row where the memristor unit is located, the word lines of each row are coupled
  • the word line driver is configured to apply the input voltage corresponding to the input data of each row in the memristor array to the word line of each row in the memristor array;
  • the source line driver is configured to apply the source line voltage to the source line of each column in the memristor array, so that the transistors in each memristor unit in each row of the memristor array are turned on and operate in the saturation region;
  • the bit line driver is configured to apply a first fixed voltage to the bit line of each row in the memristor array;
  • the output processing circuit is configured to detect the output current on the source line of each column in the memristor array to obtain the output result.
  • FIG. 1A shows a schematic diagram of a memristor unit having a 1T1R structure.
  • FIG. 1B shows a schematic diagram of a memristor unit having a 2T2R structure.
  • FIG. 2 shows a schematic diagram of an exemplary memristor array structure.
  • FIG. 3 shows the operation mode of a conventional memristor array when performing a matrix-vector multiplication operation.
  • FIG. 4 shows a schematic diagram of a buffered memristor cell according to at least one embodiment of the present disclosure.
  • FIG. 5 shows a method of applying an operating voltage to a memristor unit of a 1T1R structure according to at least one embodiment of the present disclosure.
  • FIG. 6 shows a method of applying an operating voltage to a memristor unit of a 2T2R structure according to at least one embodiment of the present disclosure.
  • FIG. 7 illustrates an operation mode of a memristor array when performing a matrix-vector multiplication operation according to an example of the present disclosure.
  • FIG. 8 shows a schematic diagram of a memristor array with global bit lines according to an example of the present disclosure.
  • FIG. 9 illustrates an operation mode of performing a setting operation or an initialization operation in a programming operation of a memristor array according to an example of the present disclosure.
  • FIG. 10 illustrates an operation mode of a memristor array during a reset operation in a programming operation according to an example of the present disclosure.
  • FIG. 11 shows a schematic diagram of a processing device according to at least one embodiment of the present disclosure.
  • Memristor e.g., resistive random access memory, phase change memory, conductive bridge memory, etc.
  • memristor is a non-volatile device whose conductance state can be adjusted by applying external stimuli.
  • memristor has the characteristics of adjustable resistance and non-volatility, so it is widely used in storage and computing applications, such as forward calculation (inference) of artificial neural networks.
  • an array composed of memristors can be used to complete matrix-vector multiplication (multiplication and accumulation) calculations in parallel, and storage and calculation occur in each device in the array. Based on this computing architecture, storage and computing can be realized without the need for large amounts of data movement.
  • Fig. 1A shows a schematic diagram of a memristor unit with a 1T1R structure.
  • the memristor unit with a 1T1R structure includes a transistor M1 and a memristor R1.
  • the transistor M1 when the transistor M1 is an N-type transistor, its gate is connected to the word line WL, for example, when the word line WL is input with a high level, the transistor M1 is turned on; the first electrode of the transistor M1 can be a source and is configured to be connected to the source line SL; the second electrode of the transistor M1 can be a drain and is configured to be connected to the second end of the memristor R1, and the first end of the memristor R1 is connected to the bit line BL.
  • the transistor M1 when the transistor M1 is a P-type transistor, its gate is connected to the word line WL, for example, when the word line WL inputs a low level, the transistor M1 is turned on; the first electrode of the transistor M1 can be a drain and is configured to be connected to the source line SL; the second electrode of the transistor M1 can be a source and is configured to be connected to the second end of the memristor R1, and the first end of the memristor R1 is connected to the bit line BL.
  • the resistive memory structure may also be implemented as other structures, such as a structure in which the first end of the memristor R1 is connected to the transistor and the second end is connected to the source line SL, and the embodiments of the present disclosure are not limited to this.
  • the function of the word line WL is to apply a corresponding voltage to the gate of the transistor M1, thereby controlling the transistor M1 to be turned on or off.
  • the memristor R1 When operating the memristor R1, such as performing a set operation or a reset operation, it is necessary to turn on the transistor M1 first, that is, it is necessary to apply a turn-on voltage to the gate of the transistor M1 through the word line WL. After the transistor M1 is turned on, for example, a voltage can be applied to the memristor R1 through the source line SL and the bit line BL to change the resistance state of the memristor R1.
  • a set voltage can be applied through the bit line BL to make the memristor R1 in a low resistance state; for another example, a reset voltage can be applied through the source line SL to make the memristor R1 in a high resistance state.
  • the resistance value of the high resistance state is more than 100 times the resistance value of the low resistance state, for example, more than 1000 times.
  • the operation of changing the memristor R1 from a high resistance state to a low resistance state is called a set operation; the operation of changing the memristor R1 from a low resistance state to a high resistance state is called a reset operation.
  • the initialization process of the memristor refers to applying a higher voltage to the memristor, thereby inducing the formation of conductive filaments inside the memristor. By applying a set voltage or a reset voltage between the electrodes of the memristor, the conductive filaments inside the memristor can be restored or broken.
  • the initialization operation usually only needs to be performed once in the life cycle of the resistive random access memory.
  • Memristor R1 has a threshold voltage, and when the input voltage amplitude is less than the threshold voltage of memristor R1, the resistance value (or conductance value) of memristor R1 will not change.
  • the resistance value (or conductance value) of memristor R1 can be used for calculation by inputting a voltage less than the threshold voltage; the resistance value (or conductance value) of memristor R1 can be changed by inputting a voltage greater than the threshold voltage.
  • Fig. 1B shows a schematic diagram of a memristor unit with a 2T2R structure.
  • the memristor unit with a 2T2R structure includes two transistors M1 and M2 and two memristors R1 and R2. The following description is made by taking the transistors M1 and M2 both being N-type transistors as an example.
  • the gate of transistor M1 is connected to word line WL1, for example, when word line WL1 of M1 is input with a high level, transistor M1 is turned on; the gate of transistor M2 is connected to word line WL2, for example, when word line WL2 of M2 is input with a high level, transistor M2 is turned on; the first electrode of transistor M1 may be a source electrode and configured to be connected to source line SL, the first electrode of transistor M2 may be a source electrode and configured to be connected to source line SL, the first electrode of transistor M1 is connected to the first electrode of transistor M2, and they are connected to source line SL together.
  • the second electrode of transistor M1 may be a drain electrode and configured to be connected to the second electrode (for example, negative electrode) of memristor R1, the first electrode (for example, positive electrode) of memristor R1 is connected to bit line BL1;
  • the second electrode of transistor M2 may be a drain electrode and configured to be connected to the second electrode (for example, negative electrode) of memristor R2, the first electrode (for example, positive electrode) of memristor R2 is connected to bit line BL2.
  • the transistors M1 and M2 in the 2T2R structure memristor unit can also both be P-type transistors, or one can be a P-type transistor and the other an N-type transistor. Different types of transistors have different control voltages, so the control voltage needs to be changed accordingly when applying, which will not be repeated here.
  • FIG2 is a schematic diagram showing an exemplary memristor array structure.
  • the memristor array is composed of a plurality of memristor units, which form an array of M rows and N columns, where M and N are both positive integers (e.g., greater than 2, and can be 100 or more).
  • Each memristor unit includes a switch element and one or more memristors.
  • WL ⁇ 1>, WL ⁇ 2>, ... WL ⁇ M> represent the word lines of the first row, the second row, ...
  • the control electrode of the element (for example, the gate of the transistor) is connected to the word line corresponding to the row;
  • BL ⁇ 1>, BL ⁇ 2>...BL ⁇ M> respectively represent the bit lines of the first row, the second row...the Mth row, and the memristors in the memristor unit circuit of each row are connected to the bit lines corresponding to the row;
  • SL ⁇ 1>, SL ⁇ 2>...SL ⁇ N> respectively represent the source lines of the first column, the second column...the Nth column, and the source electrodes of the transistors in the memristor unit circuit of each column are connected to the source lines corresponding to the column.
  • the memristor unit in the memristor array of FIG2 may be, for example, a 1T1R structure or a 2T2R structure.
  • the 2T2R structure if the two transistors are of the same type, the gates of the two transistors may be connected to the same word line, and the two memristors are connected to two different bit lines, that is, one row in the array has one word line and two bit lines; if the two transistors are of different types, the gates of the two transistors may be connected to two different word lines, and the two memristors are connected to two different bit lines, that is, one row in the array has two word lines and two bit lines.
  • the embodiments of the present disclosure have no restrictions on the type and structure of the memristor device.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (e.g., MOS transistors).
  • the source and drain of the transistors used may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the weight matrix of a neural network layer can be mapped to the conductance value matrix of a memristor array, the data to be processed is mapped as the input voltage of the array word line, and the processing result is represented by the output current of the array source line.
  • the conductance of the memristor can be used for forward calculation (such as matrix-vector multiplication).
  • FIG3 shows the operation mode of a conventional memristor array when performing matrix-vector multiplication.
  • the memristor units of the 1T1R structure in the same row share the word line WL and the bit line BL, and the memristor units in the same column share the source line SL.
  • the values of the matrix elements are mapped to the resistance values of the memristors in the corresponding memristor units in the memristor array; secondly, each data element of the vector is applied to each bit line as an input voltage after digital-to-analog conversion, a transistor turn-on voltage is applied to each word line so that each transistor is turned on together and works in the linear region, and a fixed voltage (such as a ground voltage) is applied to each source line.
  • a voltage difference is applied to each memristor in the memristor array (i.e., the input voltage applied to the corresponding common bit line BL in a row minus the fixed voltage applied to the corresponding source line SL), thereby generating a current on the memristor, and the current generated by a column of memristor units converges on the corresponding source line SL as the output current.
  • the matrix-vector multiplication calculation is specifically performed as follows. According to Kirchhoff's law, the output current of the memristor array can be obtained according to the following formula:
  • Vi is the input voltage of the bit line BL in the i-th row of the memristor array
  • Gij is the conductance value of the memristor in the i-th row and j-th column of the memristor array
  • Ij is the output current on the source line SL in the j-th column of the memristor array
  • Vsl is the fixed voltage applied to the source line SL of the memristor array during the calculation process.
  • a gate voltage is applied to the gate of the transistor so that the transistor operates in the linear region, so that the on-resistance of the transistor is negligible relative to the resistance value of the memristor; at this time, a voltage is applied to each of the source line SL and the bit line BL so that a voltage difference is formed between the source line SL and the bit line BL, and the voltage difference is directly applied to the memristor to generate a current output on the source line SL.
  • the driver that provides the source line voltage and the driver that provides the bit line voltage see a low-resistance load.
  • the current computing method of the memristor array used to realize storage and computing integration inevitably has a significant voltage drop (IR drop) effect, which leads to accuracy problems and huge external circuit overhead under the limitations of driving capability and accuracy.
  • IR drop voltage drop
  • the memristor array includes multiple rows and columns of memristor units, word lines corresponding to each row in the memristor array, bit lines corresponding to each row in the memristor array, and source lines corresponding to each column in the memristor array, each memristor unit includes a transistor and a memristor, the gate of the transistor is connected to the word line corresponding to the row where the memristor unit is located, the first electrode of the transistor is connected to the source line corresponding to the column where the memristor unit is located, the second electrode of the transistor is connected to the first end of the memristor, and the second end of the memristor is connected to the bit line corresponding to the row where the memristor unit is located.
  • the operation method includes performing a matrix-vector multiplication operation using the memristor array, or performing a programming operation on the memristors of the memristor units in the memristor array, where the programming operation includes a set operation or a reset operation.
  • FIG4 shows a schematic diagram of a novel buffered memristor unit according to at least one embodiment of the present disclosure, which can be used for storage-computation-in-one operations, such as matrix-vector multiplication operations.
  • the input voltage is applied to the memristor through a buffer circuit, and the current flowing through the memristor is also output through a buffer circuit.
  • the input buffer circuit is used to convert the low input impedance of the memristor unit into a high input impedance, and the output buffer circuit is used to suppress the influence of the voltage change at the current output end on the current.
  • the memristor unit of the embodiment of the present disclosure is the same in structure composition as the memristor unit of the 1T1R structure shown in FIG. 1A, and both include a memristor and a transistor (e.g., a MOS transistor).
  • the operation voltage application method for the memristor unit of the 1T1R structure is different from the operation voltage application method of the current memristor unit as shown in FIG. 3.
  • the embodiment of the present disclosure is based on making the transistor in different working states and avoiding problems such as voltage drop and precision reduction caused by the current operation voltage application method based on different working mechanisms.
  • FIG5 shows an operation voltage application method for a memristor unit of a 1T1R structure according to at least one embodiment of the present disclosure.
  • the operation voltage application method of the memristor unit of a 1T1R structure by controlling the control voltage (word line voltage) applied to the gate of the transistor and the source line voltage applied to the source line SL within a certain range, and grounding the bit line voltage of the bit line BL, for example, the transistor in the memristor unit operates in a saturation region.
  • the 1T1R memristor unit in which the transistor operates in a saturation region can be called a source follower unit.
  • the gate of the transistor in the source follower unit serves as a voltage input terminal, and the input voltage is buffered and applied to the memristor through the source follower structure, and the current through the memristor flows through the transistor to the source line.
  • the transistor in the source follower unit acts as an input voltage buffer circuit so that the input voltage is applied to the gate of the transistor and then buffered to the memristor, thereby increasing the impedance of the voltage input terminal.
  • the transistor also acts as an output current buffer, and it operates in a saturation region to suppress the influence of the source line voltage change on the output current.
  • V is the gate voltage of the source follower unit
  • G is the conductance of the memristor in the source follower unit
  • a is the voltage transfer coefficient of the source follower
  • b and c are coefficients related to the selected gate voltage and the conductance range of the memristor, and are constants in the calculation process.
  • the above coefficients a, b and c can be obtained by measurement or experience.
  • the current of the source follower unit in the forward calculation process is linearly related to the gate voltage of the source follower unit and the conductance of the memristor.
  • a memristor unit (source follower unit) with a 2T2R structure is constructed based on the memristor unit with the 1T1R structure (ie, the source follower unit).
  • FIG6 shows a method for applying an operating voltage to a 2T2R memristor unit according to at least one embodiment of the present disclosure.
  • an exemplary 2T2R memristor unit includes 1 NMOS transistor and a PMOS transistor, the first electrodes (e.g., drains) of the two transistors are electrically connected to each other and to the corresponding source line SL, and the gates of the two transistors are respectively connected to two different word lines; the first ends of the two memristors are respectively electrically connected to the second electrodes (e.g., sources) of the two transistors, and the second ends of the two memristors are connected to two different bit lines.
  • the first electrodes e.g., drains
  • the second electrodes e.g., sources
  • the following description is made by taking a memristor unit of a 1T1R structure as an example, wherein the transistor in the memristor unit is an NMOS transistor.
  • the embodiments of the present disclosure are not limited to this situation, and the specific operation mode can be adjusted accordingly according to the type and quantity of the transistors.
  • the operation method for the above-mentioned memristor array includes a matrix-vector multiplication operation, which includes: applying input voltages corresponding to input data of each row in the memristor array to word lines of each row in the memristor array; applying source line voltages to source lines of each column in the memristor array, so that the transistors in each memristor unit in each row of the memristor array are turned on and operate in the saturation region; applying a first fixed voltage to the bit lines of each row in the memristor array; and detecting the output current on the source lines of each column in the memristor array to obtain an output result.
  • a matrix-vector multiplication operation which includes: applying input voltages corresponding to input data of each row in the memristor array to word lines of each row in the memristor array; applying source line voltages to source lines of each column in the memristor array, so that the transistors in each memristor unit in each row of the memristor array are turned on and operate
  • FIG7 shows the operation mode of performing matrix-vector multiplication according to an example memristor array of the present disclosure.
  • the memristor units of the 1T1R structure in the same row share the word line WL and the bit line BL, and the memristor units in the same column share the source line SL.
  • the matrix unit value (weight value) is mapped to the resistance value of the memristor in the corresponding memristor unit in the memristor array; secondly, each data element of the vector is applied to each word line as an input voltage after digital-to-analog conversion, and these input voltages turn on each transistor, apply a source line voltage to each source line so that each transistor works in the saturation region, and apply a fixed voltage (an example of the first fixed voltage, such as a ground voltage) to each bit line.
  • a fixed voltage an example of the first fixed voltage, such as a ground voltage
  • Vi is the word line voltage (input voltage) applied to the word line of the i-th row in the memristor array
  • Gij is the conductance value of the memristor in the i-th row and j-th column of the memristor array
  • Ij is the source line SL of the j-th column of the memristor array.
  • the source line voltages applied to each source line SL can be the same, and the voltage size can be selected so that each crystal works in the saturation region.
  • each row of word lines WL is connected to the gate of the transistor in each memristor unit in the row, no current will flow through the word lines WL during the forward calculation process, and no voltage drop (IR drop) will be formed between different positions on the word lines WL. Therefore, the word line voltage of each unit will not deviate from the voltage provided by the peripheral word line driver.
  • the word line as the voltage input terminal only brings a capacitive load (high impedance load) to the word line driver, which greatly reduces the design power consumption and area of the word line driver.
  • the current of each column of memristor units converges on the source line SL corresponding to the column as the output current. Therefore, due to the relatively large current and relatively long wiring on the source line SL, there is a voltage drop between different positions. However, the impact of the voltage drop on the output current is greatly reduced because the transistors work in the saturation region. Similarly, since the transistors in the memristor unit all work in the saturation region, the output current of each column is little affected by the source line voltage fluctuation applied to the source line SL, and the source line voltage does not need to be precisely clamped, which can reduce the area and power consumption of the external clamping circuit.
  • the memristor array may also short-circuit all the bit lines BL to form one or more global bit lines GBL.
  • the global bit lines GBL can further reduce the voltage drop on the bit lines BL.
  • Fig. 8 shows a schematic diagram of a memristor array with global bit lines according to an example of the present disclosure.
  • the memristor array with this structure can also perform matrix-vector multiplication calculations (and programming operations to be described later) in the manner shown in Fig. 7 .
  • the above matrix-vector multiplication operation also includes performing digital-to-analog conversion on the input data of each row in the memristor array to obtain a corresponding input voltage.
  • the output current of each column in the memristor array is converted into a digital form to obtain an output result in digital form.
  • the conductance value of the memristor can be changed so that the conductance value of the memristor corresponds to the weight value that needs to be mapped.
  • This operation is called a programming operation.
  • the programming operation includes a set operation and a reset operation.
  • the setting operation includes: applying a first control to the word line of the row where the memristor unit to be set is located. A voltage is applied to turn on the transistor of the set memristor unit, and a second control voltage is applied to other word lines in the memristor array to turn off the transistors of the memristor units in other rows; a corresponding setting voltage is applied to the bit line of the row where the set memristor unit is located, and a first fixed voltage is applied to other bit lines of the memristor array; a first fixed voltage is applied to the source line of the column where the set memristor unit is located, and a setting voltage is applied to other source lines of the memristor array.
  • the second control voltage is the same as the first operating voltage, for example, both are the ground voltage (GND).
  • GND ground voltage
  • FIG. 9 shows an operation mode of a set operation or initialization (forming) operation in a programming operation of an example memristor array according to the present disclosure.
  • the memristor cells of the 1T1R structure of the example in the same row share the word line WL and the bit line BL, and the memristor cells in the same column share the source line SL.
  • a high level is applied to the word line WL corresponding to the row where the memristor unit selected for setting/initialization is located so that the transistor connected to the word line is turned on, and the source line SL of the column where the memristor unit selected for setting/initialization is located is set to a fixed voltage (low level, such as grounding), and at the same time, the bit line BL or global bit line of the row where the memristor unit is located is set to the required operating voltage, and the operating voltage is a high level, such as the value of the setting voltage or initialization voltage required for the setting/initialization operation, so that the setting/initialization operation for the memristor unit can be achieved.
  • the reset operation includes: applying a first control voltage to the word line of the row where the set memristor unit is located to turn on the transistor of the set memristor unit, applying a second control voltage to other word lines of the memristor array to turn off the transistors of the memristor units in other rows, and applying a first fixed voltage to the bit lines of each row in the memristor array; applying a reset voltage to the source line of the column where the set memristor unit is located, and applying a first operating voltage to other source lines of the memristor array.
  • the second control voltage is the same as the first operating voltage, for example, both are the ground voltage (GND).
  • GND ground voltage
  • FIG10 shows an operation mode of a memristor array according to an example of the present disclosure during a reset operation in a programming operation.
  • the memristor array corresponds to the memristor array shown in FIG8 .
  • the word line WL corresponding to the row where the memristor unit selected for reset is located is set to a high level so that the transistor connected to the word line is turned on.
  • the source line SL of the column where the memristor unit to be reset is located is set to a reset voltage (high level), and at the same time, the bit line or global bit line of the row where the memristor unit is located is set to a fixed voltage (low level, such as grounding), so as to achieve the reset operation of the memristor unit.
  • the source lines SL of the columns where other unselected memristor units in the row where the memristor unit selected for reset is located are set to the same low level (such as grounding) as the bit line BL (so that the voltage difference between the two ends of the memristors in these memristor units is 0), and the word lines WL of other rows are set to a low level so that the transistors connected to these word lines are turned off, so that only the memristor unit selected for reset is reset, and other memristor units are not reset.
  • An embodiment of the present disclosure further provides a data processing device, which is based on the above-mentioned memristor and the corresponding operation method.
  • Fig. 11 shows a schematic diagram of a data processing device provided according to at least one embodiment of the present disclosure.
  • the data processing device includes a word line driver, a source line driver, a bit line driver, an output processing circuit and a memristor array.
  • the memristor array may be, for example, the memristor array shown in FIG7 and FIG8.
  • the above-mentioned word line driver is configured to apply the input voltage corresponding to the input data of each row in the memristor array to the word line of each row in the memristor array;
  • the source line driver is configured to apply the source line voltage to the source line of each column in the memristor array, so that the transistors in each memristor unit of each row in the memristor array are turned on and work in the saturation region;
  • the bit line driver is configured to apply the first fixed voltage to the bit line corresponding to each row in the memristor array;
  • the output processing circuit is configured to detect the output current on the source line of each column in the memristor array to obtain the output result.
  • the data processing device further includes an input circuit, wherein the input circuit is configured to perform digital-to-analog conversion (DAC) on input data of each row in the memristor array to obtain a corresponding input voltage, and provide the corresponding input voltage to a word line driver.
  • DAC digital-to-analog conversion
  • the output processing circuit is further configured to receive the output current of each column in the memristor array, and perform analog-to-digital conversion (ADC) on the output current to obtain an output result in digital form.
  • ADC analog-to-digital conversion
  • driver, processing circuits and input circuits may be implemented by digital circuits, analog circuits or any combination thereof.
  • each memristor cell includes a single transistor and a single memristor, and the transistor and the memristor are connected to each other and to the corresponding word lines, bit lines and source lines as described above; or, each memristor cell includes two transistors and two memristors, and the two transistors and the two memristors are connected to each other and to the corresponding word lines, bit lines and source lines as described above.
  • the above are connected to each other, and the first electrodes of the two transistors are electrically connected to each other and electrically connected to the source line corresponding to the row where the memristor unit is located, the gates of the two transistors are respectively connected to two different word lines corresponding to the row where the memristor unit is located, and the second ends of the two memristors are electrically connected to two different bit lines corresponding to the row where the memristor unit is located.
  • At least one embodiment of the present disclosure proposes a new storage and computing structure based on a memristor array, that is, a memristor storage and computing circuit structure based on a buffered unit structure, which can alleviate the impact of the voltage drop (IR drop) caused by large current in the memristor array on the calculation accuracy and reduce the difficulty of designing external circuits. It not only eliminates the static current load of the driver during calculation, but also greatly reduces the clamping accuracy requirements of the quantization module, so that the memristor storage and computing system can achieve higher energy efficiency and computing power.
  • IR drop voltage drop
  • At least one embodiment of the present disclosure further provides an electronic device, which includes the above-mentioned data processing device.
  • the electronic device can be implemented as any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a home appliance, a communication base station, an industrial controller, a server, etc., or it can be a combination of any data processing device and hardware, and the embodiments of the present disclosure are not limited to this.

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Abstract

一种忆阻器阵列的操作方法以及数据处理装置。该忆阻器阵列的操作方法包括矩阵向量乘法操作，该矩阵向量乘法操作包括：将忆阻器阵列中各行的输入数据分别对应的输入电压施加在忆阻器阵列中各行的字线上；对忆阻器阵列中各列的源线分别施加源线电压，以使得忆阻器阵列中各行的各个忆阻器单元中的晶体管导通并工作在饱和区；对忆阻器阵列中各行的位线施加第一固定电压；检测忆阻器阵列中各列的源线上的输出电流以得到输出结果。该操作方法能够缓解忆阻器阵列中大电流导致的电压降对计算精度的影响，并且降低外部电路的设计难度。

Description

忆阻器阵列的操作方法、数据处理装置
本申请要求于2022年11月23日递交的中国专利申请第202211477580.4号的优先权，在此出于所有目标全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种忆阻器阵列的操作方法、数据处理装置。
背景技术
忆阻器存算一体技术有望打破传统冯诺依曼架构瓶颈，实现器件级存储与计算融合，避免数据搬运过程，由此大幅节省延时和能耗开销，因此被认为是下一代智能系统的核心。然而，忆阻器阵列中每个忆阻器单元采用1T1R(1晶体管1忆阻器)基本单元结构，其中，忆阻器串联在晶体管的一极(例如漏极)，例如进行前向计算时在晶体管的栅极上施加控制电压以完全打开(导通)晶体管使得晶体管处于线性区，此时晶体管等效于线性电阻。在工作中，整个忆阻器阵列相当于电阻网络，在该电阻网络中存在严重的电压降(IR drop)。因此，在采用电流感知的量化输出方式时，上述操作方式对外部驱动器和量化电路(特别是钳位电路)的精度要求非常高。这也最终导致传统忆阻器存算一体计算精度受限，且外部电路设计难度增大并且其面积、功耗和速度成为系统性能瓶颈。
为此，在1T1R的基础上，人们还提出了2T2R(2晶体管2忆阻器)的忆阻器单元的基本结构，这种结构通过本地的电流差分计算，减少走线上的累积电流，缓解电压降问题，提高计算精度；也有人提出采用电压域或电荷域量化感知的思路，但是这些方法可能牺牲速度和精度,同时忆阻器阵列的规模仍然受限。因此，提出并验证新型的阵列单元以满足高算力需求下的阵列规模增长并精简的外围电路变得十分必要。
发明内容
本公开的至少一个实施例提供了一种用于忆阻器阵列的操作方法，其中，所述忆阻器阵列包括多行多列忆阻器单元、对应于所述忆阻器阵列中各行的字 线、对应于所述忆阻器阵列中各行的位线、对应于所述忆阻器阵列中各列的源线，每个忆阻器单元包括晶体管和忆阻器，所述晶体管的栅极连接到所述忆阻器单元所在行对应的字线，所述晶体管的第一极连接到所述忆阻器单元所在列对应的源线，所述晶体管的第二极连接到所述忆阻器的第一端，所述忆阻器的第二端连接到所述忆阻器单元所在行对应的位线。其中，所述操作方法包括矩阵向量乘法操作，其中，所述矩阵向量乘法操作包括：将所述忆阻器阵列中各行的输入数据分别对应的输入电压施加在所述忆阻器阵列中各行的字线上；对所述忆阻器阵列中各列的源线分别施加源线电压，以使得所述忆阻器阵列中各行的各个忆阻器单元中的晶体管导通并工作在饱和区；对所述忆阻器阵列中各行的位线施加第一固定电压；检测所述忆阻器阵列中各列的源线上的输出电流以得到输出结果。
本公开的至少一个实施例提供了一种数据处理装置，包括：字线驱动器、源线驱动器、位线驱动器、输出处理电路、忆阻器阵列，其中，所述忆阻器阵列包括多行多列忆阻器单元、对应于所述忆阻器阵列中各行的字线、对应于所述忆阻器阵列中各行的位线、对应于所述忆阻器阵列中各列的源线，每个忆阻器单元包括晶体管和忆阻器，所述晶体管的栅极连接到所述忆阻器单元所在行对应的字线，所述晶体管的第一极连接到所述忆阻器单元所在列对应的源线，所述晶体管的第二极连接到所述忆阻器的第一端，所述忆阻器的第二端连接到所述忆阻器单元所在行对应的位线，所述各行的字线耦接到所述字线驱动器，所述各列的源线耦接到所述源线处理电路，所述各行的位线耦接到所述位线处理电路。其中，所述字线驱动器配置为将所述忆阻器阵列中各行的输入数据分别对应的输入电压施加在所述忆阻器阵列中各行的字线上；所述源线驱动器配置为对所述忆阻器阵列中各列的源线分别施加源线电压，以使得所述忆阻器阵列中各行的各个忆阻器单元中的晶体管导通并工作在饱和区；所述位线驱动器配置为对所述忆阻器阵列中各行的位线施加第一固定电压；所述输出处理电路配置为检测所述忆阻器阵列中各列的源线上的输出电流以得到输出结果。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1A示出了一种具有1T1R结构的忆阻器单元的示意图。
图1B示出了一种具有2T2R结构的忆阻器单元的示意图。
图2示出了一种示例性忆阻器阵列结构的示意图。
图3示出了传统的忆阻器阵列的进行矩阵向量乘法运算时的操作方式。
图4示出了根据本公开的至少一个实施例的缓冲式的忆阻器单元的示意图。
图5示出了根据本公开至少一实施例的对于1T1R结构的忆阻器单元的操作电压施加方式。
图6示出了根据本公开至少一实施例的对于2T2R结构的忆阻器单元的操作电压施加方式。
图7示出了根据本公开一示例忆阻器阵列的进行矩阵向量乘法运算时的操作方式。
图8示出了根据本公开一示例的具有全局位线的忆阻器阵列的示意图。
图9示出了根据本公开一示例忆阻器阵列的进行编程操作中的设置操作或初始化操作时的操作方式。
图10示出了根据本公开一示例忆阻器阵列的进行编程操作中的复位操作时的操作方式。
图11示出了根据本公开至少一实施例的处理装置的示意图。
具体实施方式
为了使得本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而 是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
忆阻器(例如，阻变存储器、相变存储器、导电桥存储器等)是一种可以通过施加外部激励，调节其电导状态的非易失型器件。忆阻器作为一种二端器件，具有电阻可调节且非挥发的特性，因此被广泛应用于存算一体运用，例如用于人工神经网络的前向计算(推理)等。根据基尔霍夫电流定律和欧姆定律，由忆阻器构成的阵列可以用于并行的完成矩阵向量乘法(乘累加)计算，且存储和计算都发生在阵列各器件中。基于这种计算架构，可以实现不需要大量数据搬移的存算一体计算。
图1A示出了一种具有1T1R结构的忆阻器单元的示意图。如图1A所示，1T1R结构的忆阻器单元包括一个晶体管M1和一个忆阻器R1。
例如，当晶体管M1采用N型晶体管时，其栅极和字线WL连接，例如字线WL输入高电平时晶体管M1导通；晶体管M1的第一极可以是源极并被配置为和源线SL连接；晶体管M1的第二极可以是漏极并被配置为和忆阻器R1的第二端连接，忆阻器R1的第一端和位线BL连接。
例如，当晶体管M1采用P型晶体管时，其栅极和字线WL连接，例如字线WL输入低电平时晶体管M1导通；晶体管M1的第一极可以是漏极并被配置为和源线SL连接；晶体管M1的第二极可以是源极并被配置为和忆阻器R1的第二端连接，忆阻器R1的第一端和位线BL连接。
需要说明的是，阻变存储器结构还可以实现为其他结构，例如忆阻器R1的第一端与晶体管连接而第二端与源线SL连接的结构，本公开的实施例对此不作限制。
字线WL的作用是对晶体管M1的栅极施加相应电压，从而控制晶体管M1导通或关闭。在对忆阻器R1进行操作时，例如进行置位操作或复位操作，均需要先开启晶体管M1，即需要通过字线WL对晶体管M1的栅极施加导通电压。在晶体管M1导通后，例如，可以通过在源线SL和位线BL向忆阻器R1施加电压，以改变忆阻器R1的阻态。例如，可以通过位线BL施加置位电压，以使得该忆阻器R1处于低阻态；又例如，可以通过源线SL施加复位电压，以使得该忆阻器R1处于高阻态。例如，高阻态的电阻值为低阻态的电阻值100倍以上，例如1000倍以上。
在本公开的实施例中，将忆阻器R1从高阻态变为低阻态的操作称为置位(Set)操作；将忆阻器R1从低阻态变为高阻态的操作称为复位(Reset)操作。另外，忆阻器的初始化过程是指对忆阻器施加一个较高的电压，从而诱导忆阻器的内部形成导电细丝。通过在忆阻器的电极间施加置位电压或复位电压，可以使得忆阻器内部的导电细丝恢复或断裂。初始化操作在阻变存储器的生命周期中通常只需要进行一次。
忆阻器R1具有阈值电压，在输入电压幅度小于忆阻器R1的阈值电压时，不会改变忆阻R1的电阻值(或电导值)。在这种情况下，可以通过输入小于阈值电压的电压，利用忆阻器R1的电阻值(或电导值)进行计算；可以通过输入大于阈值电压的电压，改变忆阻器R1的电阻值(或电导值)。
图1B示出了一种具有2T2R结构的忆阻器单元的示意图。如图1B所示，2T2R结构的忆阻器单元包括两个晶体管M1和M2以及两个忆阻器R1和R2。下面以晶体管M1和M2均采用N型晶体管为例进行说明。
晶体管M1的栅极和字线WL1相连，例如M1的字线WL1输入高电平时晶体管M1导通，晶体管M2的栅极和字线WL2相连，例如M2的字线WL2输入高电平时晶体管M2导通；晶体管M1的第一极可以是源极并被配置为和源线SL连接，晶体管M2的第一极可以是源极并被配置为和源线SL连接，晶体管M1的第一极与晶体管M2的第一极相连，并一起连接至源线SL。晶体管M1的第二极可以是漏极并被配置为和忆阻器R1的第二极(例如负极)连接，忆阻器R1的第一极(例如正极)和位线BL1连接；晶体管M2的第二极可以是漏极并被配置为和忆阻器R2的第二极(例如负极)连接，忆阻器R2的第一极(例如正极)和位线BL2连接。
需要说明的是，2T2R结构的忆阻器单元中的晶体管M1和M2也可以均采用P型晶体管，或者一个为P型晶体管而另一个为N型晶体管，不同类型的晶体管的控制电压不同，因此在施加控制电压时需要相应地改变，这里不再赘述。
图2示出了一种示例性忆阻器阵列结构的示意图。如图2所示，该忆阻器阵列由多个忆阻器单元构成，该多个忆阻器单元构成一个M行N列的阵列，M和N均为正整数(例如大于2，可以为100或更多)。每个忆阻器单元包括开关元件和一个或多个忆阻器。在图2中，WL<1>、WL<2>……WL<M>分别表示第一行、第二行……第M行的字线，每一行的忆阻器单元电路中的开关 元件的控制极(例如晶体管的栅极)和该行对应的字线连接；BL<1>、BL<2>……BL<M>分别表示第一行、第二行……第M行的位线，每行的忆阻器单元电路中的忆阻器和该行对应的位线连接；SL<1>、SL<2>……SL<N>分别表示第一列、第二列……第N列的源线，每一列的忆阻器单元电路中的晶体管的源极和该列对应的源线连接。
图2的忆阻器阵列中的忆阻器单元例如可以为1T1R结构或者2T2R结构。对于2T2R结构，如果两个晶体管是同一类型，则两个晶体管的栅极可以连接到同一条字线，而两个忆阻器连接不同的两条位线，即阵列中一行具有一条字线和两条位线；如果两个晶体管是不同类型，则两个晶体管的栅极可以连接到不同的两条字线，而两个忆阻器连接不同的两条位线，即阵列中一行具有两条字线和两条位线。
本公开的实施例对于忆阻器器件的类型、结构等没有限制。需要说明的是，本公开的实施例中采用的晶体管可以为薄膜晶体管或场效应晶体管(例如MOS晶体管)。所采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。
例如，神经网络层的权重矩阵可以映射为忆阻器阵列的电导值矩阵，待处理的数据作为输入映射为阵列字线的输入电压，处理结果则由阵列源线的输出电流表示。通过输入小于忆阻器阵列中各个忆阻器的阈值电压的电压差，就可以利用忆阻器的电导进行前向计算(例如矩阵向量乘法运算)。
图3示出了传统的忆阻器阵列的进行矩阵向量乘法运算时的操作方式。如图3所示，同一行的1T1R结构的忆阻器单元共用字线WL和位线BL，同一列的忆阻器单元共用源线SL。为了进行矩阵向量乘法计算，首先，将矩阵元素的值(例如神经网络的权重值)映射为忆阻器阵列中对应的忆阻器单元中的忆阻器的阻值；其次，向量的各个数据元素在经数模转换后作为输入电压施加到各条位线上，对各条字线施加晶体管开启电压使得各晶体管一同导通且工作在线性区，在各条源线上施加固定电压(例如接地电压)。
因此，对于忆阻器阵列中的各个忆阻器上施加了电压差(即对应的一行共用的位线BL上施加的输入电压减去在对应的源线SL上施加的固定电压)，由此在忆阻器上有电流产生，一列忆阻器单元产生的电流在对应的源线SL上汇聚作为输出电流。该矩阵向量乘法计算具体如下进行。根据基尔霍夫定律，忆阻器阵列的输出电流可以根据下述公式得出：
其中，Vi为忆阻器阵列中第i行的位线上BL的输入电压，Gij为忆阻器阵列的第i行第j列的忆阻器的电导值，Ij为忆阻器阵列第j列源线SL上的输出电流，Vsl计算过程中在忆阻器阵列的源线SL上施加的固定电压。
上述操作中，1T1R的忆阻器单元在进行前向计算的情形中，晶体管的栅极被施加栅极电压以使得晶体管管工作在线性区，从使得晶体管的导通电阻相对忆阻器的电阻值忽略不计；此时，在源线SL和位线BL各自施加一个电压使得在源线SL和位线BL之间形成电压差，该电压差直接加在忆阻器上从而产生电流在源线SL上输出。在该前向计算过程中，对于提供源线电压的驱动器和位线电压的驱动器而言看到的是低阻负载。
如上所述，目前的用于实现存算一体的忆阻器阵列的计算方式，无可避免地存在显著的电压降(IR drop)效应，由此导致精度问题以及导致驱动能力和精度限制下的巨大外部电路开销。
针对上述问题，本公开的至少一实施例提供了一种用于忆阻器阵列的操作方法以及对应的数据处理装置。该忆阻器阵列包括多行多列忆阻器单元、对应于忆阻器阵列中各行的字线、对应于忆阻器阵列中各行的位线、对应于忆阻器阵列中各列的源线，每个忆阻器单元包括晶体管和忆阻器，晶体管的栅极连接到忆阻器单元所在行对应的字线，晶体管的第一极连接到与忆阻器单元所在列对应的源线，晶体管的第二极连接到忆阻器的第一端，忆阻器的第二端连接到忆阻器单元所在行对应的位线。
例如，该操作方法包括使用忆阻器阵列进行矩阵向量乘法操作，或者对于忆阻器阵列中的忆阻器单元的忆阻器进行编程操作，该编程操作包括设置操作或复位操作。
图4示出了根据本公开的至少一个实施例的新型缓冲式的忆阻器单元的示意图，该忆阻器单元可以用于存算一体操作，例如矩阵向量乘法运算。与图1A所示的1T1R单元直接在忆阻器两端施加操作电压的方式不同，如图4所示，在本公开的至少一个实施例中，输入电压会通过一个缓冲电路再施加到忆阻器上，并且流过忆阻器的电流也会通过一个缓冲电路再进行输出。输入缓冲电路用于将忆阻器单元的低输入阻抗转换成高输入阻抗，输出缓冲电路用于抑制电流输出端电压变化对电流的影响。
在至少一个示例中，本公开实施例的忆阻器单元在结构组成上与图1A所示的1T1R结构的忆阻器单元相同，均包括一个忆阻器和一个晶体管(例如MOS晶体管)。但是，在本公开的各个实施例中，对于该1T1R结构的忆阻器单元的操作电压施加方式与如图3所示的当前的忆阻器单元的操作电压施加方式不同，本公开实施例基于使得晶体管处于不同的工作状态，基于不同的工作机理避免了当前的操作电压施加方式导致的例如电压降、精度下降等问题。
图5示出了根据本公开至少一实施例的对于1T1R结构的忆阻器单元的操作电压施加方式。如图5所示，在1T1R结构的忆阻器单元的操作电压施加方式中，通过将施加到晶体管的栅极的控制电压(字线电压)和施加到源线SL的源线电压控制在一定范围之内，并且将位线BL的位线电压例如接地，使得忆阻器单元中的晶体管工作在饱和区。可以将晶体管工作在饱和区的1T1R忆阻器单元称为源跟随器单元。源跟随器单元中的晶体管的栅极作为电压输入端，经过源跟随器结构将输入电压缓冲再施加到忆阻器上，通过忆阻器的电流流经晶体管到达源线。在这一过程中，源跟随器单元中的晶体管一方面作为输入电压缓冲电路使得输入电压施加在晶体管的栅极再缓冲到忆阻器上，从而增加了电压输入端的阻抗。另一方面，晶体管也起到输出电流缓冲的作用，其工作在饱和区从而抑制源线电压变化对输出电流的影响。
对于图5所示的操作电压施加方式，前向计算的过程中源跟随器单元的晶体管工作在饱和区，此时通过源跟随器单元的电流基本满足以下公式：
I＝f(V)*g(G)
f(V)＝a(V+b)
g(G)＝G+c
其中，V为源跟随器单元的栅极电压，G为源跟随器单元中忆阻器的电导，a为源跟随器的电压传递系数，b、c是与所选栅极电压和忆阻器电导范围相关的系数，在计算过程中是常量。上述系数a、b和c可以通过测量或经验获得。如上式所示，前向计算过程中源跟随器单元的电流与源跟随器单元的栅极电压以及忆阻器的电导呈现线性的关系。
在本公开的另一个示例中，上述1T1R结构的忆阻器单元(即上述源跟随器单元)的基础上再构建2T2R结构的忆阻器单元(源跟随器单元)。
图6示出了根据本公开至少一实施例的对于2T2R结构的忆阻器单元的操作电压施加方式。如图6所示，示例性的2T2R结构的忆阻器单元包括1个 NMOS晶体管和一个PMOS晶体管，这两个晶体管第一极(例如漏极)彼此电连接且电连接到对应的源线SL，两个晶体管的栅极分别连接到两条不同的字线；两个忆阻器的第一端分别电连接到两个晶体管的第二极(例如源极)上，两个忆阻器的第二端连接到两条不同的位线。使得两个晶体管开启所需两个的字线电压彼此不同，通过NMOS晶体管的电流与通过PMOS晶体管的电流做差分之后再汇聚在源线SL上，从而可以用于实现正负权重，并且也可相应地减小源线SL上的工作电流。
下面以1T1R结构的忆阻器单元为例进行说明，其中，且忆阻器单元中的晶体管为NMOS晶体管。本公开的实施例不限于该情形，具体操作方式可以根据晶体管的类型、数量等进行相应地调整。
在本公开的实施例中，对于上述忆阻器阵列的操作方法包括矩阵向量乘法操作，该矩阵向量乘法操作包括：将忆阻器阵列中各行的输入数据分别对应的输入电压施加在忆阻器阵列中各行的字线上；对忆阻器阵列中各列的源线分别施加源线电压，以使得忆阻器阵列中各行的各个忆阻器单元中的晶体管导通并工作在饱和区；对忆阻器阵列中各行的位线施加第一固定电压；检测忆阻器阵列中各列的源线上的输出电流以得到输出结果。
图7示出了根据本公开一示例忆阻器阵列的进行矩阵向量乘法运算时的操作方式。对于该示例的1T1R结构的忆阻器单元的忆阻器阵列中，同一行的1T1R结构的忆阻器单元共用字线WL和位线BL，同一列的忆阻器单元共用源线SL。为了进行矩阵向量乘法计算，首先，将矩阵单元值(权重值)映射为忆阻器阵列中对应的忆阻器单元中的忆阻器的阻值；其次，向量的各个数据元素在经数模转换后作为输入电压施加到各条字线上，这些输入电压使得各晶体管导通，对各条源线施加源线电压以使得各晶体管工作在饱和区，在各条位线上施加固定电压(第一固定电压的示例，例如接地电压)。在忆阻器上有电流流过，一列忆阻器单元产生的电流在对应的源线SL上汇聚作为输出电流。

f(Vi)＝a(Vi+b)
g(Gij)＝Gij+c
其中，Vi为忆阻器阵列中第i行的字线上施加的字线电压(输入电压)，Gij为忆阻器阵列的第i行第j列的忆阻器的电导值，Ij为忆阻器阵列第j列的源线SL 上的输出电流。该计算过程中，每条源线SL上施加的源线电压可以彼此相同，所选择的电压大小以使得每个晶体都工作于饱和区即可。
在上述计算过程中，由于每一行字线WL连接的是该行中每个忆阻器单元中的晶体管的栅极，因此前向计算过程中字线WL上并不会有电流通过，字线WL上的不同位置之间并不会形成电压降(IR drop)，因此各个单元的字线电压均不会偏离外围的字线驱动器所提供的电压。另外对于字线驱动器的设计来说，字线作为电压输入端带给字线驱动器的只有电容性负载(高阻抗负载)，因此也大大降低字线驱动器的设计功耗和面积。
此外，每一列忆阻器单元的电流汇聚在该列对应的源线SL上作为输出电流，因此源线SL上由于相对较大的电流以及相对较长的走线，因此在不同的位置之间是存在电压降的，然而该电压降对输出电流的影响则因晶体管工作在饱和区而大大减小。同样地，由于忆阻器单元中晶体管均工作在饱和区，每列的输出电流受源线SL上施加的源线电压波动的影响很小，源线电压不需要精确的钳位，这就可以减小外部钳位电路的面积和功耗开销。
在另一个示例中，为了优化忆阻器阵列操作，忆阻器阵列还可以将全部位线BL短接，从而形成一条或多条全局位线GBL，该全局位线GBL能够进一步减小在位线BL上的电压降。
图8示出了根据本公开一示例的具有全局位线的忆阻器阵列的示意图。该结构的忆阻器阵列同样可以图7所示的方式进行矩阵向量乘法计算(以及后面将要描述的编程操作)。
例如，上述矩阵向量乘法操作还包括将忆阻器阵列中各行的输入数据进行数模转换以得到对应的输入电压。
例如，上述的矩阵向量乘法中，将忆阻器阵列中各列的输出电流进行模数转换以得到数字形式的输出结果。
如上所述，对于本公开的实施例中，为使用忆阻器阵列进行矩阵向量乘法计算，需要首先将矩阵元素的值(例如神经网络的权重值)映射为忆阻器阵列中的忆阻器的阻值，即对忆阻器阵列进行编程操作。
通过输入大于忆阻器阵列中各个忆阻器的阈值电压的操作电压，则可以改变忆阻器的电导值，使得忆阻器的电导值与需要被映射的权重值对应，该操作被称为编程操作。编程操作包括设置操作和复位操作。
例如，设置操作包括：对被设置的忆阻器单元所在行的字线施加第一控制 电压以使得所诉被设置的忆阻器单元的晶体管导通，而对忆阻器阵列中的其他字线施加第二控制电压以使得其他行中的忆阻器单元的晶体管截止；对被设置的忆阻器单元所在行的位线施加对应的设置电压，对忆阻器阵列的其他位线施加第一固定电压；对被设置的忆阻器单元所在列的源线施加第一固定电压，对忆阻器阵列的其他源线施加设置电压。
例如，该第二控制电压与第一操作电压相同，例如，均为接地电压(GND)。
图9示出了根据本公开一示例忆阻器阵列的进行编程操作中的设置(set)操作或初始化(forming)操作时的操作方式。对于该示例的1T1R结构的忆阻器单元的忆阻器阵列中，同一行的1T1R结构的忆阻器单元共用字线WL和位线BL，同一列的忆阻器单元共用源线SL。
如图9所示，设置/初始化操作时，对选中以进行设置/初始化的忆阻器单元所在的行对应的字线WL施加高电平以使得与该字线连接的晶体管导通，将选中以进行设置/初始化的忆阻器单元所在列的源线SL置为固定电压(低电平，例如接地)，与此同时将该忆阻器单元所在行的位线BL或全局位线置为所需要的操作电压，该操作电压为高电平例如对应需要设置/初始化操作所需要的设置电压或初始化电压的值，如此可以实现对于该忆阻器单元的设置/初始化操作。另外，同时还需要将所选中的忆阻器单元所在行的其他未选中的忆阻器单元的源线SL置为与位线BL相同的高电平(由此这些忆阻器单元中的忆阻器两端的电压差为0)，并将忆阻器阵列中的其他行的字线WL置为低电平以使得与这些字线连接的晶体管截止，由此使得只有被选中的忆阻器单元进行设置/初始化操作，而其他忆阻器单元不会进行设置/初始化操作。
例如，复位操作包括：对被设置的忆阻器单元所在行的字线施加第一控制电压以使得被设置的忆阻器单元的晶体管导通，而对忆阻器阵列的其他字线施加第二控制电压以使得其他行中的忆阻器单元的晶体管截止，对忆阻器阵列中各行的位线施加第一固定电压；对被设置的忆阻器单元所在列的源线施加复位电压，对忆阻器阵列的其他源线施加第一操作电压。
例如，该第二控制电压与第一操作电压相同，例如，均为接地电压(GND)。
图10示出了根据本公开一示例忆阻器阵列的进行编程操作中的复位(reset)操作时的操作方式。该忆阻器阵列对应于图8所示的忆阻器阵列。
如图10所示，在进行复位操作时，对选中以进行复位的忆阻器单元所在的行对应的字线WL置为高电平以使得与该字线连接的晶体管导通，所选中以 进行复位的忆阻器单元所在列的源线SL置为复位电压(高电平)，与此同时将该忆阻器单元所在行的位线或全局位线置为固定电压(低电平，例如接地)，如此实现对该忆阻器单元的复位操作。另外，将所选中以进行复位的忆阻器单元所在行的其他未选中的忆阻器单元所在列的源线SL置为与位线BL相同的低电平(例如接地)(由此这些忆阻器单元中的忆阻器两端的电压差为0)，并将其他行的字线WL置为低电平以使得与这些字线连接的晶体管截止，由此使得只有被选中以进行复位的忆阻器单元被进行复位操作，而其他忆阻器单元不会进行复位操作。
本公开的实施例还提供了一种数据处理装置，该数据处理装置基于上述忆阻器以及相应的操作方式。
图11示出了根据本公开的至少一个实施例提供的数据处理装置的示意图。如图11所示，该数据处理装置包括字线驱动器、源线驱动器、位线驱动器、输出处理电路和忆阻器阵列。
该忆阻器阵列例如可以为图7～图8所示的忆阻器阵列。上述字线驱动器配置为将忆阻器阵列中各行的输入数据分别对应的输入电压施加在忆阻器阵列中各行的字线上；源线驱动器配置为对忆阻器阵列中各列的源线分别施加源线电压，以使得忆阻器阵列中各行的各个忆阻器单元中的晶体管导通并工作在饱和区；位线驱动器配置为将对应于忆阻器阵列中各行的位线施加第一固定电压；输出处理电路配置为检测忆阻器阵列中各列的源线上的输出电流以得到输出结果。
例如，该数据处理装置还包括输入电路，其中，输入电路配置为将忆阻器阵列中各行的输入数据进行数模转换(DAC)以得到对应的输入电压，并将对应的输入电压提供至字线驱动器。
例如，在上述数据处理装置中，输出处理电路还配置为接收忆阻器阵列中各列的输出电流，并将输出电流进行模数转换(ADC)以得到数字形式的输出结果。
上述各驱动器、处理电路和输入电路可以通过数字电路、模拟电路或它们的任意组合实现。
如上所述，每个忆阻器单元包括单个晶体管和单个忆阻器，并且晶体管和忆阻器按如上所述彼此连接以及与对应的字线、位线和源线连接；或者，每个忆阻器单元包括两个晶体管和两个忆阻器，两个晶体管和两个忆阻器分别按如 上所述彼此连接，并且，两个晶体管的第一极彼此电连接且电连接到连接到忆阻器单元所在行对应的源线，两个晶体管的栅极分别连接到忆阻器单元所在行对应的两条不同字线，两个忆阻器的第二端电连接到连接到忆阻器单元所在行对应的两条不同位线。
本公开的至少一实施例提出的新的基于忆阻器阵列的存算一体结构，即基于缓冲式单元结构的忆阻器存算一体电路结构，能够缓解忆阻器阵列中大电流导致的电压降(IR drop)对计算精度的影响，并且降低外部电路的设计难度，既消除了驱动器在计算时的静态电流负载，且大大降低了量化模块的钳位精度要求，使得忆阻器存算一体系统能够实现更高的能效和算力。
例如，本公开的至少一实施例还提供了一种电子装置，该电子装置包括上述数据处理装置，例如，该电子装置可以实现为手机、平板电脑、笔记本电脑、电子书、游戏机、电视机、数码相框、导航仪、家用电器、通信基站、工业控制器、服务器等任何设备，也可以为任意的数据处理装置及硬件的组合，本公开的实施例对此不作限制。
对于本公开，还有以下几点需要说明：
(1)本公开实施例附图只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)为了清晰起见，在用于描述本发明的实施例的附图中，层或结构的厚度和尺寸被放大。可以理解，当诸如层、膜、区域或基板之类的元件被称作位于另一元件“上”或“下”时，该元件可以“直接”位于另一元件“上”或“下”，或者可以存在中间元件。
(3)在不冲突的情况下，本公开的实施例及实施例中的特征可以相互组合以得到新的实施例。
以上所述仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，本公开的保护范围应以所述权利要求的保护范围为准。

Claims (12)

  1. 一种用于忆阻器阵列的操作方法，其中，所述忆阻器阵列包括多行多列忆阻器单元、对应于所述忆阻器阵列中各行的字线、对应于所述忆阻器阵列中各行的位线、对应于所述忆阻器阵列中各列的源线，每个忆阻器单元包括晶体管和忆阻器，所述晶体管的栅极连接到所述忆阻器单元所在行对应的字线，所述晶体管的第一极连接到所述忆阻器单元所在列对应的源线，所述晶体管的第二极连接到所述忆阻器的第一端，所述忆阻器的第二端连接到所述忆阻器单元所在行对应的位线，
    所述操作方法包括矩阵向量乘法操作，其中，所述矩阵向量乘法操作包括：
    将所述忆阻器阵列中各行的输入数据分别对应的输入电压施加在所述忆阻器阵列中各行的字线上；
    对所述忆阻器阵列中各列的源线分别施加源线电压，以使得所述忆阻器阵列中各行的各个忆阻器单元中的晶体管导通并工作在饱和区；
    对所述忆阻器阵列中各行的位线施加第一固定电压；
    检测所述忆阻器阵列中各列的源线上的输出电流以得到输出结果。
  2. 根据权利要求1所述的操作方法，其中，对所述忆阻器阵列中各行的位线施加所述第一固定电压，包括：
    将所述忆阻器阵列中各行的位线彼此短接以施加所述第一固定电压。
  3. 根据权利要求1或2所述的操作方法，其中，所述矩阵向量乘法操作还包括：
    将所述忆阻器阵列中各行的输入数据进行数模转换以得到所述对应的输入电压。
  4. 根据权利要求1-3任一项所述的操作方法，其中，检测所述忆阻器阵列中各列的源线上的输出电流以得到所述输出结果，包括：
    将所述忆阻器阵列中各列的所述输出电流进行模数转换以得到数字形式的所述输出结果。
  5. 根据权利要求1-4任一项所述的操作方法，其中，所述操作方法还包括编程操作，其中，所述编程操作包括对于被设置的忆阻器单元的忆阻器的设置操作和复位操作。
  6. 根据权利要求5所述的操作方法，其中，所述设置操作包括：
    对所述被设置的忆阻器单元所在行的字线施加第一控制电压以使得所述 被设置的忆阻器单元的晶体管导通，而对所述忆阻器阵列中的其他字线施加第二控制电压以使得所述其他行中的忆阻器单元的晶体管截止；
    对所述被设置的忆阻器单元所在行的位线施加对应的设置电压，对所述忆阻器阵列的其他位线施加第一操作电压；
    对所述被设置的忆阻器单元所在列的源线施加所述第一操作电压，对所述忆阻器阵列的其他源线施加所述设置电压。
  7. 根据权利要求5所述的操作方法，其中，所述复位操作包括：
    对所述被设置的忆阻器单元所在行的字线施加第一控制电压以使得所述被设置的忆阻器单元的晶体管导通，而对所述忆阻器阵列的其他字线施加第二控制电压以使得其他行中的忆阻器单元的晶体管截止；
    对所述忆阻器阵列中各行的位线施加第一操作电压；
    对所述被设置的忆阻器单元所在列的源线施加复位电压，对所述忆阻器阵列的其他源线施加所述第一操作电压。
  8. 根据权利要求6或7所述的操作方法，其中，所述第二控制电压与所述第一操作电压相同。
  9. 一种数据处理装置，包括：
    字线驱动器、源线驱动器、位线驱动器和输出处理电路；以及
    忆阻器阵列，其中，所述忆阻器阵列包括多行多列忆阻器单元、对应于所述忆阻器阵列中各行的字线、对应于所述忆阻器阵列中各行的位线、对应于所述忆阻器阵列中各列的源线，每个忆阻器单元包括晶体管和忆阻器，所述晶体管的栅极连接到所述忆阻器单元所在行对应的字线，所述晶体管的第一极连接到所述忆阻器单元所在列对应的源线，所述晶体管的第二极连接到所述忆阻器的第一端，所述忆阻器的第二端连接到所述忆阻器单元所在行对应的位线，所述各行的字线耦接到所述字线驱动器，所述各列的源线耦接到所述源线处理电路，所述各行的位线耦接到所述位线处理电路，
    其中，
    所述字线驱动器配置为将所述忆阻器阵列中各行的输入数据分别对应的输入电压施加在所述忆阻器阵列中各行的字线上，
    所述源线驱动器配置为对所述忆阻器阵列中各列的源线分别施加源线电压，以使得所述忆阻器阵列中各行的各个忆阻器单元中的晶体管导通并工作在饱和区，
    所述位线驱动器配置为对所述忆阻器阵列中各行的位线施加第一固定电压，
    所述输出处理电路配置为检测所述忆阻器阵列中各列的源线上的输出电流以得到输出结果。
  10. 根据权利要求9所述的数据处理装置，还包括输入电路，其中，所述输入电路配置为将所述忆阻器阵列中各行的输入数据进行数模转换以得到所述对应的输入电压，并将所述对应的输入电压提供至所述字线驱动器。
  11. 根据权利要求9或10所述的数据处理装置，其中，所述输出处理电路还配置为接收所述忆阻器阵列中各列的输出电流，并将所述输出电流进行模数转换以得到数字形式的所述输出结果。
  12. 根据权利要求9-11任一项所述的数据处理装置，其中，每个所述忆阻器单元包括单个晶体管和单个忆阻器，或者，
    每个所述忆阻器单元包括两个晶体管和两个忆阻器，所述两个晶体管的第一极彼此电连接且电连接到连接到所述忆阻器单元所在行对应的源线，所述两个晶体管的栅极分别连接到所述忆阻器单元所在行对应的两条不同字线，所述两个忆阻器的第二端电连接到连接到所述忆阻器单元所在行对应的两条不同位线。
PCT/CN2023/132237 2022-11-23 2023-11-17 忆阻器阵列的操作方法、数据处理装置 WO2024109644A1 (zh)

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