WO2023130487A1 - 基于忆阻器阵列的数据处理方法、电子装置 - Google Patents

基于忆阻器阵列的数据处理方法、电子装置 Download PDF

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WO2023130487A1
WO2023130487A1 PCT/CN2022/071337 CN2022071337W WO2023130487A1 WO 2023130487 A1 WO2023130487 A1 WO 2023130487A1 CN 2022071337 W CN2022071337 W CN 2022071337W WO 2023130487 A1 WO2023130487 A1 WO 2023130487A1
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matrix
array
sub
memristor
row
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English (en)
French (fr)
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吴华强
刘正午
赵涵
唐建石
高滨
钱鹤
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清华大学
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/4806—Computations with complex numbers
    • G06F7/4812—Complex multiplication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present disclosure relate to a data processing method and an electronic device based on a memristor array.
  • Memristor (such as resistive change memory, phase change memory, conductive bridge memory, etc.) is a new type of micro-nano electronic device, which can adjust its conductance state by applying external excitation.
  • Memristor-based neuromorphic computing breaks through the von Neumann architecture of traditional computing devices. Computing and storage are done in the same place, which reduces the time for data transfer, and requires high energy efficiency, low power consumption, and area for computing. smaller. Realizing analog computing based on memristor arrays using physical laws is a hot research field in recent years.
  • At least one embodiment of the present disclosure provides a data processing method based on a memristor array, wherein the data processing includes matrix-vector multiplication in the complex field, and the memristor array includes a plurality of memristors arranged in an array
  • the memristor unit is configured to perform multiplication and operation
  • the data processing method includes: acquiring a plurality of first analog signals; setting the memristor array, and writing the data corresponding to the parameter matrix of the data processing into the A memristor array, wherein the matrix of the complex number field includes a real part matrix and an imaginary part matrix, and the parameter matrix includes the real part matrix, the imaginary part matrix and the imaginary part negative obtained based on the imaginary part matrix matrix, wherein the parameter elements in the negative imaginary part matrix correspond to the parameter elements in the imaginary part matrix one by one, and each parameter element in the negative imaginary part matrix is the corresponding parameter in the imaginary part matrix
  • the negative value of the element respectively input the plurality of first analog signals into the plurality of column signal input terminals of
  • the memristor array includes a first sub-array, a second sub-array, a third sub-array and a fourth sub-array
  • the memristor array is set , writing the data corresponding to the parameter matrix of the data processing into the memristor array, including: mapping multiple parameter elements in the real part matrix to the first A sub-array and the fourth sub-array, mapping multiple parameter elements in the imaginary part matrix to the third sub-array in the form of the imaginary part matrix, and multiple parameter elements in the imaginary part negative matrix parameter elements are mapped to the second subarray in the form of the negative imaginary part matrix, wherein the first subarray and the second subarray are located in the same row of the memristor array but on the row side do not overlap upward, the third sub-array and the fourth sub-array are located in the same row of the memristor array but do not overlap in the row direction, the first sub-array and the third sub-
  • the first sub-array and the third sub-array are located in the same column of the memristor array, and the second sub-array and the A fourth sub-array is located in the same column in the memristor array.
  • the memristor array includes at least 2N rows and 2M columns
  • the first sub-array includes the i-th row to the i-th row in the memristor array +N-1 row, column j to column j+M-1
  • the second sub-array includes row i to row i+N-1 in the memristor array, row j+k+ Column M-1 to column j+k+2M-2
  • the third sub-array includes row i+g+N-1 to row i+g+2N-2 in the memristor array
  • the fourth sub-array includes the i+g+N-1th row to the i+g+2N-2th row in the memristor array, and the j+th Column k+M-1 to column j+k+2M-2, wherein M, N, i, j, k and g are positive integers
  • the real part matrix includes a plurality of parameter elements arranged in an array of N rows and M columns, and the multiple parameter elements in the real part matrix are divided according to The form of the real part matrix is mapped to the first subarray and the fourth subarray, including: mapping the N parameter elements in the same row in the real part matrix to the first subarray respectively N memristor units in the same row, and N memristor units in the same row in the fourth sub-array; M parameter elements located in the same column in the real part matrix are respectively mapped to the first M memristor units in the same column of a sub-array, and M memristor units in the same column of the fourth sub-array.
  • each of the plurality of first analog signals includes a first real part analog signal and a first imaginary part analog signal
  • obtaining the plurality of first An analog signal comprising: acquiring a vector in the complex domain used for the data processing, wherein the vector in the complex domain includes a real part vector and an imaginary part vector; encoding the real part vector and the imaginary part vector respectively processing to obtain a plurality of first real part analog signals and a plurality of first imaginary part analog signals.
  • respectively inputting the plurality of first analog signals into the plurality of column signal input terminals of the set memristor array includes: inputting the plurality of first analog signals into input the first real part analog signals to the column signal input ports of the first sub-array and the third sub-array respectively; input the plurality of first imaginary part analog signals to the second sub-array and the second sub-array respectively The column signal input terminal of the fourth sub-array.
  • each of the plurality of second analog signals includes a second real part analog signal and a second imaginary part analog signal
  • the first subarray and The second sub-array shares the same row signal output terminal
  • the third sub-array and the fourth sub-array share the same row signal output terminal
  • the plurality of row signal output terminals of the memristor array are respectively
  • Obtaining a plurality of second analog signals after performing the data processing includes: obtaining a plurality of second real part analog signals according to the current signal output from the row signal output end of the first subarray; A plurality of second real part imaginary part signals are obtained from the current signal output by the row signal output end.
  • the data processing method provided in at least one embodiment of the present disclosure further includes: performing analog-to-digital conversion processing on the plurality of second real part analog signals to obtain the real part operation result of the matrix-vector multiplication operation; performing analog-to-digital conversion processing on the plurality of second imaginary part analog signals to obtain an imaginary part operation result of the matrix-vector multiplication operation.
  • the parameter matrix is expressed as
  • W real is the real part matrix
  • W img is the imaginary part matrix
  • -W img is the imaginary part negative matrix
  • the parameter matrix includes P rows and Q columns, and the parameter elements in the mth row and nth column in the parameter matrix are determined by the mth row in the first submatrix
  • the parameter element in the nth column and the parameter element in the mth row and nth column in the second sub-matrix are jointly represented, m, n, P and Q are positive integers, and the first sub-matrix includes the first parameter element in P rows, so
  • the second sub-matrix includes P rows of second parameter elements, the P rows of first parameter elements correspond to the row and column positions of the P rows of second parameter elements, and the first sub-matrix and the second sub-matrix Arranging in the first matrix form of 2P rows and Q columns, setting the memristor array, and writing the data corresponding to the parameter matrix of the data processing into the memristor array, including: writing the first sub The matrix and the second sub-matrix are mapped to the memristor
  • the multiple second analog signals after the data processing are respectively obtained at the multiple row signal output terminals of the memristor array, including: determining at least A group of rows to be processed, wherein each group of the at least one group of rows to be processed includes a row of target memristor cells corresponding to a row of the P rows of first parameter elements, and a row of target memristor cells corresponding to the P row A row of target memristor cells corresponding to a row of the P rows of the second parameter elements in the row of the first parameter elements; the two rows of targets included in each group of the at least one group of rows to be processed performing current preprocessing on the current signals of two of the plurality of row signal output ends respectively corresponding to the memristor units, so as to obtain the plurality of second simulation signals corresponding to each group of the at least one group of rows to be processed Signal.
  • the memristor array includes a first memristor array and a second memristor array, and the parameters of the uth row and vth column in the parameter matrix
  • the first sub-matrix is correspondingly mapped to the first memristor array in the form of the parameter matrix
  • the second sub-matrix is correspondingly mapped to the second memristor array in the form of the parameter matrix device array.
  • a plurality of second analog signals after performing the data processing are respectively obtained at a plurality of row signal output terminals of the memristor array, including: The current signal of each of the plurality of row signal output terminals in the first memristor array and the current of each of the corresponding plurality of row signal output terminals in the second memristor array The signal is subjected to current preprocessing to obtain the plurality of second analog signals.
  • the current preprocessing is current subtraction processing or current addition processing.
  • the data processing is discrete Fourier transform
  • the matrix in the complex domain is the coefficient matrix of the discrete Fourier transform
  • the real part matrix is the real part of the coefficient matrix
  • the imaginary part matrix is the imaginary part of the coefficient matrix
  • At least one embodiment of the present disclosure provides an electronic device, including: a memristor array configured to perform multiplication and operation; a signal acquisition device configured to acquire a plurality of first analog signals; a control drive circuit, wherein the The control driving circuit is configured to perform the following steps: setting the memristor array, writing data corresponding to the parameter matrix of the data processing into the memristor array, wherein the matrix of the complex field includes a real part Matrix and imaginary part matrix, the parameter matrix includes the real part matrix, the imaginary part matrix and the imaginary part negative matrix obtained based on the imaginary part matrix, wherein, the parameter elements in the imaginary part negative matrix are the same as the The parameter elements in the imaginary part matrix are in one-to-one correspondence, and each parameter element in the imaginary part negative matrix is the negative value of the corresponding parameter element in the imaginary part matrix; the plurality of first analog signals are respectively input The set multiple column signal input ends of the memristor array control the operation of the memristor array to perform the data processing on the multiple first analog signals, and
  • the memristor array includes a first sub-array, a second sub-array, a third sub-array, and a fourth sub-array
  • the control driving circuit executes setting the The memristor array, when writing the data corresponding to the parameter matrix of the data processing into the memristor array, includes performing the following steps: the plurality of parameter elements in the real part matrix respectively according to the real The form of the partial matrix is mapped to the first sub-array and the fourth sub-array, and the multiple parameter elements in the imaginary part matrix are mapped to the third sub-array according to the form of the imaginary part matrix, and A plurality of parameter elements in the negative imaginary part matrix are mapped to the second subarray in the form of the negative imaginary part matrix, wherein the first subarray and the second subarray are located in the memristor the same row in the memristor array but do not overlap in the row direction, the third sub-array and the fourth sub-
  • Fig. 1 shows a kind of DFT realization method based on memristor array
  • Fig. 2 shows a schematic structure of a memristor array
  • 3A is a schematic diagram of a memristor unit with a 1T1R structure
  • 3B is a schematic diagram of a memristor unit with a 2T2R structure
  • FIG. 4 is a schematic flowchart of a data processing method based on a memristor array provided by at least one embodiment of the present disclosure
  • Fig. 5 is a schematic diagram of the realization principle of a memristor array provided by at least one embodiment of the present disclosure
  • FIG. 6 is a schematic diagram of a memristor array for data processing provided by at least one embodiment of the present disclosure
  • FIG. 7A is a schematic diagram of a thermal diagram of a real part matrix element provided by at least one embodiment of the present disclosure.
  • FIG. 7B is a schematic diagram of a thermodynamic diagram of an imaginary part matrix element provided by at least one embodiment of the present disclosure.
  • FIG. 7C is a schematic diagram of a heat map of a parameter matrix element provided by at least one embodiment of the present disclosure.
  • FIG. 8 is a schematic diagram of a memristor array after writing a parameter matrix provided by at least one embodiment of the present disclosure
  • FIG. 9 is a schematic diagram of another memristor array after writing a parameter matrix provided by at least one embodiment of the present disclosure.
  • FIG. 10A is a schematic diagram of a conductance mapping thermal diagram of a first sub-matrix provided by at least one embodiment of the present disclosure
  • 10B is a schematic diagram of a conductance mapping matrix thermal diagram of a second sub-matrix provided by at least one embodiment of the present disclosure
  • Fig. 11A is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • FIG. 11B is a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • FIG. 11C is a schematic diagram of another electronic device provided by at least one embodiment of the present disclosure.
  • DFT Discrete Fourier Transform
  • x[a] is a complex number, representing the time-domain sampling of the input signal
  • y[b] is a complex number, representing the frequency-domain sampling of the output signal
  • N is a real number, representing the length of the signal segment
  • i is the imaginary unit .
  • the coefficient matrix of Liye transform, W real and W img are the real part and imaginary part of W, respectively.
  • W real and W img can be represented by formula (3) and formula (4) respectively:
  • 2 ⁇ (N- 1) means 2 ⁇ (N-1) ⁇ (N-1), and so on.
  • Figure 1 shows a DFT implementation method based on a memristor array.
  • this scheme mainly uses the characteristics of memristors to realize vector matrix multiplication.
  • the conductance matrices of two memristor arrays are used to map the real part W real and the imaginary part W img of the DFT matrix respectively, and the real part W img of the input signal.
  • the part Re(x) (that is, x real in formula (2)) and the imaginary part Im(x) (that is, x img in formula (2)) are represented by voltage pulses respectively, and added to the corresponding array, we can get Re(W) + (that is, W real x real in formula (2), Re(W) - (that is, W img x img in formula (2), Im(W) + (that is, in formula (2) W real x img ) and Im(W) - (that is, W img x real in formula (2)) are the intermediate results of the four operations (operation intermediate items).
  • peripheral auxiliary operation circuits are required to perform addition and subtraction operations.
  • Auxiliary operational circuits such as operational amplifiers have considerable area overhead. If each output corresponds to using 2 opamps (one for subtraction in W real x real -W img x img and one for addition in W real x img +W img x real ), then for N (eg , 64, 128) point DFT requires 2 ⁇ N (for example, 128, 256) operational amplifiers, thus increasing additional circuit area and computational power consumption overhead.
  • At least one embodiment of the present disclosure provides a data processing method and an electronic device based on a memristor array.
  • the data processing method based on the memristor array includes: acquiring a plurality of first analog signals; setting the memristor array, and writing the data corresponding to the parameter matrix of data processing into the memristor array, wherein the matrix of the complex number domain includes The real part matrix and the imaginary part matrix, the parameter matrix includes the real part matrix, the imaginary part matrix and the imaginary part negative matrix obtained based on the imaginary part matrix, wherein the parameter elements in the imaginary part negative matrix and the parameter elements in the imaginary part matrix are one by one Corresponding, and each parameter element in the negative imaginary part matrix is the negative value of the corresponding parameter element in the imaginary part matrix; input a plurality of first analog signals into multiple column signal input terminals of the set memristor array respectively, and control The memristor array is operated to perform data processing on a plurality of first analog signals, and a plurality of second analog signals after data processing are respectively obtained at
  • the data processing method based on the memristor array deforms and designs the operation formula of the matrix-vector multiplication in the complex field to obtain the corresponding parameter matrix.
  • the complex field matrix can be obtained by one calculation.
  • Vector multiplication operation results, thereby reducing the area and power consumption overhead of auxiliary operation circuits around the memristor array.
  • At least one embodiment of the present disclosure also provides an electronic device corresponding to the data processing method based on the memristor array.
  • Fig. 2 shows a schematic structure of a memristor array
  • the memristor array is composed of a plurality of memristor units, and the plurality of memristor units form an array of r rows and s columns, and r and s are is a positive integer.
  • Each memristor cell includes a switching element and one or more memristors.
  • WL ⁇ 1>, WL ⁇ 2>...WL ⁇ r> represent the word lines of the first row, the second row...the r-th row respectively, and the switching elements in the memristor cells of each row
  • the control electrode (such as the gate of the transistor) is connected to the word line corresponding to the row;
  • BL ⁇ 1>, BL ⁇ 2>...BL ⁇ s> respectively represent the bit lines of the first column, the second column...the sth column , the memristors in the memristor units of each column are connected to the corresponding bit line of the column;
  • SL ⁇ 1>, SL ⁇ 2>...SL ⁇ r> respectively represent the first row, the second row...rth row
  • the source lines of the rows, the sources of the transistors in the memristor units of each row are connected to the corresponding source lines of the row.
  • the above memristor array can be completed in parallel Multiply and accumulate calculations.
  • the memristor unit in the memristor array of FIG. 2 may have, for example, a 1T1R structure or a 2T2R structure, wherein the memristor unit of the 1T1R structure includes a transistor and a memristor, and the memristor unit of the 2T2R structure includes two transistor and two memristors. It should be noted that the present disclosure does not limit the structure of the memristor unit, and memristor units of other structural forms that can realize multiply-accumulate operations may also be used.
  • the transistors used in the embodiments of the present disclosure may be thin film transistors or field effect transistors (such as MOS field effect transistors) or other switching devices with the same characteristics.
  • the source and drain of the transistor used here may be symmetrical in structure, so there may be no difference in structure between the source and drain.
  • the two poles (ie source and drain) of the transistor except the gate it is directly described that one of them is the first pole and the other is the second pole.
  • FIG. 3A is a schematic diagram of a memristor unit with a 1T1R structure. As shown in FIG. 3A , the 1T1R memristor unit includes a transistor M1 and a memristor R1 .
  • the embodiment of the present disclosure does not limit the type of transistor used.
  • the transistor M1 when the transistor M1 is an N-type transistor, its gate is connected to the word line WL.
  • the transistor M1 is turned on when the word line WL inputs a high level;
  • One pole may be a source and be configured to be connected to the source line SL, for example, the transistor M1 may receive a reset voltage through the source line SL;
  • the second pole of the transistor M1 may be a drain and be configured to be connected to the second pole of the memristor R1 ( For example, the negative pole) is connected, and the first pole (for example, the positive pole) of the memristor R1 is connected to the bit line BL, for example, the memristor R1 can receive a set voltage through the bit line BL.
  • the transistor M1 when the transistor M1 is a P-type transistor, its gate is connected to the word line WL, for example, the transistor M1 is turned on when the word line WL inputs a low level; the first pole of the transistor M1 can be a drain and is configured to be connected to the source line SL , for example, the transistor M1 can receive the reset voltage through the source line SL; the second pole of the transistor M1 can be a source and is configured to be connected to the second pole (such as the negative pole) of the memristor R1, and the first pole of the memristor R1 ( For example, the positive electrode) is connected to the bit line BL, for example, the memristor R1 can receive a set voltage through the bit line BL.
  • the memristor structure can also be implemented as other structures, for example, a structure in which the second pole of the memristor R1 is connected to the source line SL, which is not limited in the embodiments of the present disclosure.
  • the transistor M1 adopts an N-type transistor as an example for illustration.
  • the function of the word line terminal WL is to apply a corresponding voltage to the gate of the transistor M1 so as to control the transistor M1 to be turned on or off.
  • the transistor M1 When operating the memristor R1 , such as a set operation or a reset operation, the transistor M1 needs to be turned on first, that is, a turn-on voltage needs to be applied to the gate of the transistor M1 through the word line terminal WL. After the transistor M1 is turned on, for example, a voltage can be applied to the memristor R1 through the source line terminal SL and the bit line terminal BL, so as to change the resistance state of the memristor R1.
  • a set voltage can be applied through the bit line terminal BL, so that the memristor R1 is in a low resistance state; another example, a reset voltage can be applied through a source line terminal SL, so that the memristor R1 is in a high resistance state.
  • the resistance value of the high-resistance state is more than 100 times, for example, more than 1000 times of the resistance value of the low-resistance state.
  • the resistance value of the memristor R1 can be made smaller and smaller by simultaneously applying a voltage to the word line terminal WL and the bit line terminal BL, that is, the memristor R1 changes from the high resistance state to
  • the operation of changing the memristor R1 from a high-resistance state to a low-resistance state is called a set operation; by applying a voltage at the word line terminal WL and the source line terminal SL at the same time, the memristor R1 can be set.
  • the memristor R1 has a threshold voltage, and when the input voltage amplitude is smaller than the threshold voltage of the memristor R1, the resistance value (or conductance value) of the memristor R1 will not be changed.
  • the resistance value (or conductance value) of the memristor R1 can be used for calculation by inputting a voltage smaller than the threshold voltage; the resistance value (or conductance value) of the memristor R1 can be changed by inputting a voltage greater than the threshold voltage conductivity value).
  • FIG. 3B is a schematic diagram of a memristor unit with a 2T2R structure.
  • the memristor cell of the 2T2R structure includes two transistors M1 and M2 and two memristors R1 and R2.
  • the transistors M1 and M2 are both N-type transistors as an example.
  • the gate of the transistor M1 is connected to the word line terminal WL1, for example, when the word line terminal WL1 of M1 inputs a high level, the transistor M1 is turned on, and the gate of the transistor M2 is connected to the word line terminal WL2, for example, the word line terminal WL2 of M2 inputs a high level
  • the transistor M2 is turned on;
  • the first pole of the transistor M1 can be the source and is configured to be connected to the source terminal SL, for example, the transistor M1 can receive a reset voltage through the source terminal SL, and the first pole of the transistor M2 can be the source And configured to be connected to the source terminal SL, for example, the transistor M2 can receive the reset voltage through the source terminal SL, the first electrode of the transistor M1 is connected to the first electrode of the transistor M2, and are connected to the source terminal SL together.
  • the second pole of the transistor M1 may be a drain and is configured to be connected to a second pole (such as a negative pole) of the memristor R1, and a first pole (such as a positive pole) of the memristor R1 is connected to a bit line terminal BL1, such as a memristor R1
  • the resistor R1 can receive the set voltage through the bit line terminal BL1;
  • the second pole of the transistor M2 can be a drain and is configured to be connected to the second pole (eg negative pole) of the memristor R2, and the first pole of the memristor R2 Pole (such as the positive pole) is connected to the bit line terminal BL2, for example, the memristor R2 can receive a set voltage through the bit line terminal BL2.
  • transistors M1 and M2 in the memristor unit of the 2T2R structure may both use P-type transistors, which will not be repeated here.
  • FIG. 4 is a schematic flowchart of a data processing method based on a memristor array provided by at least one embodiment of the present disclosure.
  • the data processing method based on the memristor array provided by the embodiment of the present disclosure includes steps S110 to S130, and the memristor array includes a plurality of memristor units arranged in an array and is configured as Can perform multiplication and operation (that is, multiplication and accumulation operation, the multiplication product results are accumulated and processed to obtain the sum value after the multiplication and accumulation results are accumulated).
  • the memristor array includes a plurality of memristor units arranged in an array and is configured as Can perform multiplication and operation (that is, multiplication and accumulation operation, the multiplication product results are accumulated and processed to obtain the sum value after the multiplication and accumulation results are accumulated).
  • a schematic structural diagram of the memristor array is shown in FIG. 2 , and each memristor unit may have a 1T1R structure as shown in FIG. 3A or a 2T2R structure as shown in FIG. 3B .
  • step S110 a plurality of first analog signals are acquired.
  • step S120 a memristor array is set, and data corresponding to a parameter matrix for data processing is written into the memristor array.
  • a matrix in the complex field includes a real part matrix and an imaginary part matrix
  • a parameter matrix includes a real part matrix, an imaginary part matrix, and a negative imaginary part matrix obtained based on the imaginary part matrix
  • the parameter elements in the imaginary part negative matrix correspond to the parameter elements in the imaginary part matrix one by one, and each parameter element in the imaginary part negative matrix is the negative value of the corresponding parameter element in the imaginary part matrix.
  • a negative imaginary part matrix is obtained by negating each parameter element in the imaginary part matrix.
  • step S130 a plurality of first analog signals are respectively input to a plurality of column signal input terminals of the set memristor array, and the operation of the memristor array is controlled to perform data processing on the plurality of first analog signals, and the memristor array
  • the plurality of row signal output ends of the array respectively obtain a plurality of second analog signals after data processing.
  • the multiple first analog signals are input signals to be subjected to data processing
  • the multiple second analog signals are output signals after data processing is performed on the input signals.
  • the first analog signal is an analog voltage signal
  • the second analog signal is an analog current signal
  • each first analog signal may include a first real part analog signal and a first imaginary part analog signal
  • each second analog signal may include a second real part analog signal and a second imaginary part analog signal
  • calculation formula of complex field matrix-vector multiplication can be expressed as the following form:
  • the above formula (5) is the representation of the calculation formula of matrix-vector multiplication in the complex field
  • W t is the parameter matrix for data processing
  • W real is the real part matrix
  • W img is The imaginary part matrix
  • -W img is the negative matrix of the imaginary part
  • y t is the operation result of the matrix-vector multiplication operation
  • the operation result includes the real part operation result y real and the imaginary part operation result y img
  • x t is a vector in the complex field for data processing, including the real part vector x real and the imaginary part vector x img .
  • obtaining the plurality of first analog signals may include: obtaining a vector x t in the complex domain for data processing, wherein the vector x t in the complex domain includes a real part vector x real and an imaginary part vector x img ; respectively encode the real part vector x real and the imaginary part vector x img to obtain a plurality of first real part analog signals and a plurality of first imaginary part analog signals.
  • the vector x t in the complex field is encoded into a voltage pulse vector through encoding processing, that is, each parameter element in the real part vector x real and the imaginary part vector x img is encoded into a corresponding voltage pulse, thereby obtaining the real part vector
  • the first real part analog signal corresponding to each parameter element in x real and the first imaginary part analog signal corresponding to each parameter element in the imaginary part vector x real is encoded into a voltage pulse vector through encoding processing, that is, each parameter element in the real part vector x real and the imaginary part vector x img is encoded into a corresponding voltage pulse, thereby obtaining the real part vector
  • the first real part analog signal corresponding to each parameter element in x real and the first imaginary part analog signal corresponding to each parameter element in the imaginary part vector x real is encoded into a voltage pulse vector through encoding processing, that is, each parameter element in the real part vector x real and the imaginary part vector x img is encoded into a corresponding voltage pulse, thereby
  • the encoding process includes digital-to-analog conversion processing.
  • the number of pulses can be used to encode the parameter elements, and the pulse amplitude encoding can also be used to encode the parameter elements.
  • the specific process of the encoding process in this disclosure No limit.
  • the vector x t in the complex field used for data processing can be a digital signal with a length of N, that is, the real part vector x real is the real part of the digital signal, and the imaginary part vector x img is the imaginary part of the digital signal.
  • the digital signal may be a pre-stored digital signal; for example, the digital signal may be a digital signal acquired in real time. Digital-to-analog conversion is performed on the digital signal to obtain a plurality of first analog signals.
  • the memristor array includes a first sub-array, a second sub-array, a third sub-array and a fourth sub-array.
  • step S120 may include: mapping the multiple parameter elements in the real part matrix to the first sub-array and the fourth sub-array respectively in the form of real part matrix, and mapping the multiple parameter elements in the imaginary part matrix according to the imaginary part matrix
  • the form of the imaginary part negative matrix is mapped to the third sub-array
  • the multiple parameter elements in the imaginary part negative matrix are mapped to the second sub-array in the form of the imaginary part negative matrix, wherein the first sub-array and the second sub-array are located in the memristor array the same row in the memristor array but do not overlap in the row direction, the third sub-array and the fourth sub-array are located in the same row in the memristor array but do not overlap in the row direction, the first sub-array and the third sub-array do not overlap in the column direction overlapping.
  • the first sub-array and the third sub-array are located in the same column in the memristor array, and the second sub-array and the fourth sub-array are located in the same column in the memristor array.
  • the first sub-array and the third sub-array are located in different columns in the memristor array
  • the second sub-array and the fourth sub-array are located in different columns in the memristor array.
  • FIG. 5 is a schematic diagram of an implementation principle of a memristor array provided by at least one embodiment of the present disclosure.
  • complex field matrix-vector multiplication can be realized by a memristor array, that is, a memristor array can be used to represent W real , -W img , W
  • the parameter matrix W t composed of real and W img .
  • a part of the memristor array is directly used to represent the imaginary negative matrix -W img , and the multiplication-accumulation calculation is directly performed on the memristor array through Kirchhoff's current law, which reduces the number of pairs set on the periphery of the memristor array.
  • the overhead of processing circuits such as operational amplifiers for addition and subtraction of intermediate results of operations can be achieved in one operation to obtain all the results of matrix-vector multiplication in the complex field, improving computational efficiency, reducing circuit overhead, and saving circuit area.
  • FIG. 6 is a schematic diagram of a memristor array for data processing provided by at least one embodiment of the present disclosure.
  • the memristor array includes at least 2N rows and 2M columns, and both M and N are positive integers.
  • the memristor array may include a first sub-array, a second sub-array, a third sub-array, and a fourth sub-array.
  • SL ⁇ i>, SL ⁇ i+1>... SL ⁇ i+N-1> represent the i-th row, i+1th row...i+N-1th row Source line, the source of the transistor in the first sub-array and the second sub-array is connected to the source line of the i-th row, the i+1th row...the i+N-1th row; SL ⁇ i+g+N- 1>, SL ⁇ i+g+N>...
  • SL ⁇ i+g+2N-2> respectively represent row i+g+N-1, row i+g+N...row i+g+2N - the source line of row 2, the source electrodes of the transistors in the third sub-array and the fourth sub-array, and row i+g+N-1, row i+g+N... i+g+2N-2 Line source connection.
  • BL ⁇ j>, BL ⁇ j+1>... BL ⁇ j+M-1> represent the bit lines of column j, column j+1...column j+M-1 respectively, the first sub
  • the memristors in the memristor cells in the array and the third sub-array are connected to the bit lines in column j, column j+1... column j+M-1;
  • BL ⁇ j+k+2M-2> represent column j+k+M-1, column j+k+M...
  • bit lines of 2 columns, the memristors in the memristor cells in the second sub-array and the fourth sub-array are related to the j+k+M-1th column, the j+k+Mth column...j+kth column Bit line connections for +2M-2 columns.
  • i, j, k and g are positive integers.
  • the first sub-array and the second sub-array can be located in the same row in the memristor array but do not overlap in the row direction.
  • the third sub-array and the fourth sub-array may be located in the same row of the memristor array but do not overlap in the row direction, and the first and third sub-arrays do not overlap in the column direction.
  • the length of its signal segment is N.
  • the parameter matrix W t used for data processing corresponding to the DFT includes 2N rows and 2N columns. Therefore, the memristor array shown in FIG. 6 after mapping the parameter matrix W t corresponding to the DFT also includes 2N rows and 2N columns, that is, M is equal to N. Wherein, M and N are positive integers.
  • the real part matrix includes a plurality of parameter elements arranged in an array of N rows and M columns.
  • Mapping multiple parameter elements in the real part matrix to the first sub-array and the fourth sub-array respectively in the form of a real part matrix includes: mapping N parameter elements in the same row in the real part matrix to the first sub-array respectively N memristor units in the same row in the array, and N memristor units in the same row in the fourth sub-array; M parameter elements in the same column in the real part matrix are respectively mapped to the same M memristor cells in a column, and M memristor cells in the same column of the fourth sub-array.
  • the imaginary part matrix includes a plurality of parameter elements arranged in an array of N rows and M columns.
  • Mapping multiple parameter elements in the imaginary part matrix to the third subarray in the form of the imaginary part matrix includes: mapping the N parameter elements in the same row in the imaginary part matrix to the N parameter elements in the same row in the third subarray respectively a memristor unit, and map the M parameter elements in the same column in the imaginary part matrix to the M memristor units in the same column of the third sub-array respectively.
  • the negative imaginary part matrix includes a plurality of parameter elements arranged in an array of N rows and M columns.
  • Mapping the parameter elements in the imaginary part negative matrix to the second subarray in the form of the imaginary part negative matrix includes: mapping the N parameter elements in the same row in the imaginary part negative matrix to the same row in the second subarray respectively For the N memristor units, the M parameter elements located in the same column in the negative imaginary part matrix are respectively mapped to the M memristor units in the same column of the second sub-array.
  • each memristor unit may have a 1T1R structure, as shown in FIG. 3A , that is, each memristor unit includes a memristor, and the conductance value of the memristor represents the corresponding parameter element.
  • each memristor unit can be a 2T2R structure, as shown in Figure 3B, that is, each memristor unit includes two memristors, and the conductance values of the two memristors can be used to realize the negative value of the parameter element , so that multiple memristor units can be used to achieve richer and more complex data processing.
  • step S130 respectively inputting a plurality of first analog signals into the plurality of column signal input ends of the set memristor array includes: inputting a plurality of first real part analog signals into the first sub-array and the first sub-array respectively The column signal input terminals of the three sub-arrays; respectively input a plurality of first imaginary part analog signals to the column signal input terminals of the second sub-array and the fourth sub-array.
  • the first sub-array and the third sub-array share the same column signal input end, and jointly receive a plurality of first real part analog signals obtained based on the real part vector x real .
  • the second sub-array and the fourth sub-array share the same column signal input terminal, and jointly receive a plurality of first imaginary part analog signals obtained based on the imaginary part vector x img .
  • the first sub-array and the third sub-array may not share the same column signal input terminal, and multiple first real part analog signals are respectively input into the first sub-array and the third sub-array through different column signal input terminals.
  • the second sub-array and the fourth sub-array may not share the same column signal input terminal, and multiple first real part analog signal inputs are respectively input to the second sub-array and the fourth sub-array through different column signal input terminals. array.
  • a plurality of first analog signals may be respectively applied to a plurality of column signal input terminals of the set memristor array, and at the same time, a turn-on signal is applied to a plurality of signal control terminals of the memristor array to detect and acquiring multiple current signals at multiple row signal output ends of the memristor array, and obtaining multiple second analog signals based on the multiple current signals.
  • the first real part analog signals V j , V j are input to the multiple column signal input terminals of the bit lines of the jth column, the j+1th column ... the j+M-1th column +1 ...V j+M-1 , multiple column signal input terminals of the bit lines in the j+k+M-1 column, the j+k+M column...the j+k+2M-2 column Input the first imaginary part analog signals V j+k+M-1 , V j+k+M ... V j+k+2M-2 .
  • the second real part analog signal I i , I i+1 ... I i+N-1 is output on the line signal output end of the line, the i+ g+N-1th row, the i+g+Nth row... Output the second imaginary part analog signal I i+g+N-1 , I i+g+N ... I i + g+2N-2 on the row signal output end of the source line of the i+g+2N-2th row .
  • a plurality of second analog signals after data processing are respectively obtained at the plurality of row signal output terminals of the memristor array, which may include: according to the current signal output by the row signal output terminals of the first sub-array Obtaining a plurality of second real part analog signals; obtaining a plurality of second real part imaginary part signals according to the current signal output from the row signal output end of the second subarray.
  • the data processing method based on a memristor array provided by at least one embodiment of the present disclosure may further include: performing analog-to-digital conversion processing on a plurality of second analog signals, so as to convert the plurality of second analog signals into a plurality of digital signal for further processing.
  • analog-to-digital conversion processing is performed on a plurality of second real part analog signals to obtain the real part operation result of the matrix-vector multiplication operation in the complex field, that is, the real part operation result y real in the formula (7);
  • An analog-to-digital conversion process is performed on the second imaginary part analog signal to obtain the imaginary part operation result of the matrix-vector multiplication operation in the complex field, that is, the imaginary part operation result y img in formula (7).
  • FIG. 7A is a schematic diagram of a thermal diagram of a real part matrix provided by at least one embodiment of the present disclosure
  • FIG. 7B is a schematic diagram of a thermal diagram of an imaginary part matrix provided by at least one embodiment of the present disclosure
  • the horizontal and vertical coordinates in the heat diagram shown in Figure 7A, Figure 7B and Figure 7C represent the length of the signal segment, and each point determined by the horizontal and vertical coordinates represents the parameter element of the corresponding position in the matrix, and the rectangle on the right side of the figure gradually changes
  • the color bars indicate the values of parameter elements at different positions in the cloud image, and different values correspond to different gray values, ranging from -1 to 1.
  • the matrix of the complex number domain can be the coefficient matrix of the discrete Fourier transform.
  • the coefficient matrix For the definition and expression form of the coefficient matrix, refer to formulas (1) to formulas (4).
  • formula (3) and formula (4) calculate the real part matrix W real and the imaginary part matrix W img of DFT, thus, get the real part matrix as shown in Fig. 7A
  • the heat map of W real and the heat map of the imaginary part matrix W img as shown in Figure 7B.
  • each parameter element in the imaginary part matrix W img is negated to obtain the negative imaginary part matrix -W img .
  • each parameter element may be represented by the conductance values of two memristors.
  • a difference between the conductance values of two memristors may be used to represent a A parametric element, or, a parametric element is represented by the sum of the conductance values of two memristors.
  • the parameter matrix may be jointly represented by a first sub-matrix and a second sub-matrix.
  • the parameter matrix includes P rows and Q columns, and the parameter elements in the mth row and nth column in the parameter matrix are composed of the parameter elements in the mth row and nth column in the first submatrix and the mth row and nth column in the second submatrix
  • the parameter elements of are collectively represented, and m, n, P and Q are positive integers. That is to say, the parameter element in row m and column n in the parameter matrix is the sum of the parameter element in row m and column n in the first submatrix and the parameter element in row m and column n in the second submatrix or Difference.
  • the first sub-matrix includes P rows of first parameter elements
  • the second sub-matrix includes P rows of second parameter elements
  • the row and column positions of P rows of first parameter elements and P rows of second parameter elements correspond one-to-one.
  • the first sub-matrix and the second sub-matrix are arranged in the form of the first matrix with 2P rows and Q columns.
  • the first sub-matrix and the second sub-matrix have the same matrix form as the aforementioned parameter matrix.
  • step S120 may include: mapping the first sub-matrix and the second sub-matrix to the memristor array in the form of a first matrix.
  • obtaining a plurality of second analog signals after performing data processing at a plurality of row signal output terminals of the memristor array may include: determining at least one group of rows to be processed, wherein at least one group Each group in the rows to be processed includes a row of target memristor cells corresponding to one row of P rows of first parameter elements, and a row of target memristor cells corresponding to one row of P rows of first parameter elements.
  • a row of target memristor units corresponding to one row performing current presetting on current signals of two of the plurality of row signal output terminals respectively corresponding to two rows of target memristor units included in at least one group of rows to be processed processing to obtain multiple second analog signals corresponding to each group in at least one group of rows to be processed.
  • current preprocessing is current subtraction processing or current addition processing.
  • FIG. 8 is a schematic diagram of a memristor array after writing a parameter matrix provided by at least one embodiment of the present disclosure.
  • V 1 to V Q in Fig. 8 are respectively Q first analog signals, which are respectively input into Q column signal input terminals, and I 1+ to I P+ and I 1- to I P- in Fig. 8 are respectively 2P Based on the 2P current signals output by the row signal output terminals, P second analog signals I 1 to I P are obtained based on the 2P current signals, where P and Q are positive integers.
  • Conductance matrix G t+ [G 11+ ...G 1Q+ ; ...; G P1+ ...G PQ+ ],
  • the conductance value G mn+ corresponding to the parameter element located in the mth row and nth column in the first sub-matrix W 1 and the conductance value G mn- corresponding to the parameter element located in the mth row and nth column in the second sub-matrix W 2 are jointly represented
  • the conductance value G mn corresponding to the parameter element for performing data processing, that is, the parameter matrix W for performing data processing is jointly represented by the first sub-matrix W 1 and the corresponding second sub-matrix W 2 .
  • each parameter element used to perform data processing can be represented by the difference between the parameter elements of the corresponding row and column positions in the first sub-matrix W1 and the second sub-matrix W2 , so that the first sub-matrix and the corresponding second sub-matrix can be used
  • Submatrix implements negative values of parameter elements to perform richer and complex data processing.
  • step S120 the first sub-matrix W 1 and the second sub-matrix W 2 are mapped into the memristor array in the form of the first matrix W 0 , for example, the first sub-matrix W 1 is mapped as shown in FIG. 8
  • the memristor sub-array A, the second sub-matrix W 2 is mapped to the memristor sub-array B shown in FIG. 8 .
  • the memristor sub-array A and the memristor sub-array B are shown in the area marked by the black thick solid line in FIG. 8 .
  • the specific mapping process is as described above, and will not be repeated here.
  • step S130 a group of rows to be processed corresponding to the memristor array shown in FIG. Memristor cells (G m1+ , G m2+ ... G mQ+ ), and a row of target memristor cells (G m1- , G m2- ... G mQ- ).
  • the current signal I m+ of the row signal output terminal of the mth row in the memristor array and the current signal I m- of the row signal output terminal of the P+mth row are subjected to current preprocessing to obtain the second analog signal I m .
  • the P second analog signals after data processing are obtained in the above manner.
  • the above current preprocessing is current subtraction processing.
  • the current preprocessing may also be current addition processing.
  • the mapping state shown in FIG. 8 is only an illustration.
  • the first sub-matrix and the second sub-matrix may also be mapped into the memristor array in units of rows, which is not limited in the present disclosure.
  • the parameter elements in the first row of the first submatrix are mapped to the first row of the memristor array
  • the parameter elements in the first row of the second submatrix are mapped to the second row of the memristor array
  • the parameter elements in the first row of the first submatrix are mapped to the second row of the memristor array.
  • the second row of parameter elements is mapped to the third row of the memristor array
  • the second row of parameter elements of the second sub-matrix is mapped to the fourth row of the memristor array, and so on.
  • two corresponding first memristor arrays and second memristor arrays can also be used, and the current signals at the corresponding row signal output terminals can be preprocessed to obtain the second analog signal, so as to realize the negative effect of the parameter elements. value, performing richer and more complex data processing.
  • the memristor array includes a first memristor array and a second memristor array
  • the parameter elements in the uth row and the vth column in the parameter matrix are composed of the parameter elements in the uth row and the vth column in the first sub-matrix and
  • the parameter elements in row u and column v in the second sub-matrix are jointly represented, where u and v are positive integers, and both the first sub-matrix and the second sub-matrix have the same matrix form as the parameter matrix.
  • step S120 may include: correspondingly mapping the first sub-matrix to the first memristor array in the form of a parameter matrix, and correspondingly mapping the second sub-matrix to the second memristor array in the form of a parameter matrix.
  • step S130 for example, obtaining a plurality of second analog signals after performing data processing at a plurality of row signal output terminals of the memristor array, including: outputting a plurality of row signals in the first memristor array The current signal of each of the terminals and the current signal of each of the corresponding plurality of row signal output terminals in the second memristor array are subjected to current preprocessing to obtain a plurality of second analog signals.
  • current preprocessing is current subtraction processing or current addition processing.
  • FIG. 9 is a schematic diagram of another memristor array after writing a parameter matrix provided by at least one embodiment of the present disclosure. This embodiment can realize the same data processing as the embodiment shown in FIG. 9 .
  • the memristor array shown in FIG. 9 includes a first memristor array and a second memristor array, and each memristor array has an independent control circuit, for example, has an independent column signal input terminal to respectively input Q
  • the first analog signals V 1 to V Q and the independent row signal output terminals are used to output the current signal I 1+ to the current signal I P+ and the current signal I 1- to the current signal I P- .
  • I 1 to I P in FIG. 9 represent P second analog signals after data processing.
  • the parameter matrix includes P rows and Q columns, and the parameter elements in the uth row and vth column in the parameter matrix are composed of the parameter elements in the uth row and vth column in the first submatrix and the uth row and vth column in the second submatrix.
  • the parameter elements are jointly represented, where u and v are positive integers. Both the first sub-matrix and the second sub-matrix have the same matrix form as the parameter matrix.
  • the first sub-matrix has P rows and Q columns
  • the second sub-matrix also has P rows and Q columns
  • the parameter elements corresponding to the row and column positions in the first sub-matrix and the second sub-matrix together represent a Parameter elements, for example, each parameter element used to perform data processing is represented by the sum or difference of the parameter elements at corresponding row and column positions in the first sub-matrix W 1 and the second sub-matrix W 2 .
  • the conductance value G uv+ corresponding to the parameter element located in the u-th row and the v-th column in the first sub-matrix W 1 and the conductance value G uv- corresponding to the parameter element located in the u-th row and the v-th column in the second sub-matrix W 2 are jointly represented
  • the conductance value G uv corresponding to the parameter element performing data processing That is, the parameter matrix W for performing data processing is jointly represented by the first sub-matrix W 1 and the corresponding second sub-matrix W 2 .
  • each parameter element used to perform data processing can be represented by the difference between the parameter elements of the corresponding row and column positions in the first sub-matrix W1 and the second sub-matrix W2 , so that the first sub-matrix and the corresponding second sub-matrix can be used
  • Submatrix implements negative values of parameter elements to perform richer and complex data processing.
  • step S120 the first sub-matrix is correspondingly mapped to the first memristor array in the form of a parameter matrix, and the second sub-matrix is correspondingly mapped to the second memristor array in the form of a parameter matrix. resistor array.
  • the specific mapping process is as described above, and will not be repeated here.
  • step S130 the current signal I u+ of the row signal output terminal of the u-th row in the first memristor array and the current signal I u- of the row signal output terminal of the u-th row in the second memristor array are performed
  • the current is preprocessed to obtain the second analog signal I u .
  • the P second analog signals after data processing are obtained in the above manner.
  • the above current preprocessing is current subtraction processing.
  • the current preprocessing may also be current addition processing.
  • the parameter elements for performing data processing in the parameter matrix W t are divided into the first sub-matrix and the second sub-matrix The difference between the parameter elements corresponding to the row and column positions in .
  • FIG. 10A is a schematic diagram of a conductance mapping thermal diagram of a first sub-matrix provided by at least one embodiment of the present disclosure
  • FIG. 10B is a schematic diagram of a thermal diagram of a conductance mapping matrix of a second sub-matrix provided by at least one embodiment of the present disclosure. .
  • the first sub-matrix W1 is mapped to the first memristor array in the manner in step S120, for example, the corresponding memristors are programmed to corresponding conductance states according to the first sub-matrix W1;
  • the second sub-matrix W2 is mapped to the memristor array in the manner in step S120, for example, the corresponding memristors are programmed to corresponding conductance states according to the second sub-matrix W2.
  • the parameter elements in the parameter matrix W t are jointly represented by the parameter elements mapped to the first sub-matrix of the first memristor array and the parameter elements corresponding to the row and column positions of the second sub-matrix mapped to the second memristor array.
  • the data processing method based on the memristor array can obtain the matrix-vector of the complex field in one calculation (or one calculation cycle) by negating and integrating the real part matrix and the imaginary part matrix of the matrix in the complex field. All the results of the multiplication operation greatly reduce the area and power consumption overhead of peripheral circuits used to implement functions such as addition and subtraction in traditional schemes, reduce power consumption, and increase calculation speed.
  • FIG. 11A is a schematic block diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • the electronic device 100 includes a memristor array 101 , a signal acquisition device 102 and a control driving circuit 103 .
  • the memristor array 101 is configured to perform multiplication and sum operations to perform data processing as described above.
  • the signal acquiring device 102 is configured to acquire a plurality of first analog signals.
  • the control driving circuit 103 is configured to perform steps S120 to S130.
  • the memristor array 101 may be the memristor array shown in FIG. 2 , the memristor array includes a plurality of memristor units arranged in an array, and the memristor array includes r rows and s columns.
  • each memristor unit includes a memristor, each memristor includes a first end and a second end, and the memristor can be set to an initial state, and can also be set (set) to have a certain The set state of the resistor value. When the memristor is in its initial state, its resistance is much greater than in the set state.
  • each memristor unit further includes a switch element, the switch element includes a control terminal, a first pole and a second pole, and the first terminal of the memristor is electrically connected to the first pole of the switch element.
  • the memristor array further includes r word lines, r source lines and s bit lines.
  • the r word lines correspond to the r rows respectively, and each word line is electrically connected to the control terminal of each switching element of a row of memristor units;
  • the r source lines correspond to r rows respectively, and each source line is connected to a row of memristor units
  • the second poles of each switching element are electrically connected;
  • the s bit lines correspond to s columns respectively, and each bit line is electrically connected to the second end of each memristor of a column of memristor units.
  • the signal acquisition device 102 includes a digital signal acquisition circuit and a digital-to-analog conversion circuit.
  • the digital signal acquisition circuit is configured to acquire multiple initial digital signals; the digital-to-analog conversion circuit is configured to perform digital-to-analog conversion processing on the multiple initial digital signals to obtain multiple first analog signals respectively.
  • control driving circuit 103 may include a source line driving circuit, a word line driving circuit and a bit line driving circuit.
  • the source line drive circuit is configured to detect a plurality of second analog signals and perform an initialization operation on the memristor array;
  • the word line drive circuit is configured to apply a turn-on signal to a plurality of signal control terminals of the memristor array and The array performs an initialization operation;
  • the bit line driving circuit is configured to apply input signals to a plurality of column signal input ends and perform an initialization operation to the memristor array, wherein the input signals at least include a plurality of first analog signals.
  • control driving circuit 103 may apply input signals to multiple column signal input terminals of the memristor array through the bit line driving circuit, and simultaneously apply the turn-on signal to multiple signal control terminals of the memristor array through the word line driving circuit, Finally, the current signals at the multiple row signal output terminals of the set memristor array are processed by the source line driving circuit to obtain multiple second analog signals.
  • the electronic device 100 may further include a data output circuit, wherein the data output circuit is configured to convert a plurality of second analog signals into digital signals, so as to respectively convert the plurality of second analog signals into a plurality of digital signals for use in for subsequent processing.
  • the data output circuit is configured to convert a plurality of second analog signals into digital signals, so as to respectively convert the plurality of second analog signals into a plurality of digital signals for use in for subsequent processing.
  • step S110 shown in FIG. 4 in the above-mentioned embodiment of the data processing method based on the memristor array
  • the circuit 103 is used to implement steps S120 to S130 shown in FIG. 4 .
  • steps S120 to S130 shown in FIG. 4 in the above-mentioned embodiment of the data processing method based on a memristor array. related descriptions.
  • the electronic device can achieve similar technical effects to the aforementioned data processing method based on the memristor array, which will not be repeated here.
  • FIG. 11B is a schematic diagram of an electronic device provided by at least one embodiment of the present disclosure.
  • the electronic device includes a signal acquisition device, a word line driver circuit, a bit line driver circuit, a source line driver circuit, a memristor array, and a data output circuit.
  • the signal acquisition device is configured to convert the digital signal into a plurality of first analog signals through a DAC (Digital to Analog converter), so as to be input to a plurality of column signal inputs of the memristor array during data processing end.
  • DAC Digital to Analog converter
  • the matrix used to perform matrix-vector multiplication in the complex field is M rows and N columns, M and N are positive integers, and the memristor array includes at least 2N source lines, 2N word lines and 2M bit lines, and The array is arranged as a plurality of memristor units with 2N rows and 2M columns (for example, corresponding to the memristor array with 2N rows and 2M columns in FIG. 6 ).
  • each memristor unit has a 1T1R structure, and the parameter matrix used for data processing is mapped to the memristor array. The specific process is as described in step S120 and will not be repeated here.
  • the process of implementing data processing through the word line driver circuit, the bit line driver circuit and the source line driver circuit is as described above, and will not be repeated here.
  • the word line driving circuit includes a plurality of multiplexers (Mux for short) for switching the input voltage of the word line
  • the bit line driving circuit includes a plurality of multiplexers for switching the input voltage of the bit line
  • the source line The driving circuit also includes a plurality of multiplexers for switching the input voltage of the source line.
  • a memristor array includes an operating mode and a computing mode.
  • the memristor unit When the memristor array is in the operation mode, the memristor unit is in an initialization state, and the values of the parameter elements in the parameter matrix can be written into the memristor array. For example, the input voltage of the source line, the input voltage of the bit line and the input voltage of the word line of the memristor are switched to corresponding preset voltage intervals through the multiplexer.
  • the input voltage of the word line is switched to a corresponding voltage range through the control signal WL_sw[1:2N] of the multiplexer in the word line driving circuit in FIG. 11B .
  • the word line input voltage is set to 2V (volts), for example, when the memristor is reset, the word line input voltage is set to 5V, for example, the word line input voltage It can be obtained through the voltage signal V_WL[1:2N] in FIG. 11B .
  • the input voltage of the source line is switched to a corresponding voltage range through the control signal SL_sw[1:2N] of the multiplexer in the source line driving circuit in FIG. 11B .
  • the word line input voltage is set to 0V, for example, when the memristor is reset, the source line input voltage is set to 2V, for example, the source line input voltage can be obtained by The voltage signal V_SL[1:2N] in 11B is obtained.
  • the bit line input voltage is switched to a corresponding voltage range through the control signal BL_sw[1:2M] of the multiplexer in the bit line driving circuit in FIG. 11B .
  • set the input voltage of the bit line to 2V
  • set the input voltage of the bit line to 0V
  • the input voltage of the source line can be set as shown in Fig.
  • the DAC in 11B is obtained.
  • the memristors in the memristor array are in a conductive state that can be used for calculation, and the bit line input voltage input by the column signal input terminal will not change the conductance value of the memristor, Data processing is accomplished by performing multiply-and-sum operations through the memristor array. For example, the word line input voltage is switched to a corresponding voltage range through the control signal WL_sw[1:2N] of the multiplexer in the word line driving circuit in FIG.
  • the voltage is set to 5V, for example, when no turn-on signal is applied, the word line input voltage of the corresponding row is set to 0V, for example, the GND signal is turned on; through the control signal SL_sw[1 of the multiplexer in the source line drive circuit in Figure 11B : 2N] switch the input voltage of the source line to a corresponding voltage range, for example, set the input voltage of the source line to 0V, so that the current signals of multiple row signal output terminals can flow into the data output circuit, through the bit line drive circuit in Figure 11B
  • the control signal BL_sw[1:2M] of the multiplexer switches the input voltage of the bit line to the corresponding voltage range, for example, the input voltage of the bit line is set to 0.1V-0.3V, so that the memristor array can be used for multiplication
  • the characteristics of the sum operation complete the data processing.
  • the data output circuit includes multiple ADCs (Analog to Digital converters, analog-to-digital converters), which can convert the current signals at multiple row signal output terminals into digital signals for subsequent processing.
  • ADCs Analog to Digital converters, analog-to-digital converters
  • FIG. 11C is a schematic diagram of another electronic device provided by at least one embodiment of the present disclosure.
  • the electronic device shown in FIG. 11C has the same structure as the electronic device shown in FIG. 11B , and also includes a signal acquisition device, a word line driver circuit, a bit line driver circuit, a source line driver circuit, a memristor array and a data output circuit.
  • the memristor array includes 2N source lines, 4N word lines and 4M bit lines, and a plurality of memristor units arranged in 2N rows and 2M columns (for example, corresponding to 2N rows and 2M columns in FIG. 6 memristor array).
  • each memristor unit has a 2T2R structure, and the parameter matrix used for data processing is mapped to different multiple sub-arrays in the memristor array for multiple times. The specific process is as described in step S120 and will not be repeated here.
  • the memristor array may also include 2N source lines, 2N word lines and 4M bit lines, and a plurality of memristor units arranged in 2N rows and 2M columns. Since the turn-on signal is applied to multiple signal control terminals of the memristor array at the same time when step S130 is performed, each word line can simultaneously control two memristors in each row of memristor cells.

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Abstract

本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法和电子装置。该基于忆阻器阵列的数据处理方法包括：获取多个第一模拟信号；设置忆阻器阵列，将对应于数据处理的参数矩阵的数据写入忆阻器阵列；将多个第一模拟信号分别输入设置后的忆阻器阵列的多个列信号输入端，控制忆阻器阵列操作以对多个第一模拟信号进行数据处理，在忆阻器阵列的多个行信号输出端分别得到执行数据处理后的多个第二模拟信号。该基于忆阻器阵列的数据处理方法通过将复数域矩阵向量乘法对应的参数矩阵映射到忆阻器阵列，实现一次计算即可得到复数域矩阵向量乘法运算结果，从而减少了忆阻器阵列外围的辅助运算电路的面积和功耗开销。

Description

基于忆阻器阵列的数据处理方法、电子装置
本申请要求于2022年1月7日递交的中国专利申请第202210016618.1号的优先权，在此全文引用上述中国专利申请公开的内容以作为本申请的一部分。
技术领域
本公开的实施例涉及一种基于忆阻器阵列的数据处理方法、电子装置。
背景技术
随着科学技术的进步和信息技术的快速发展，人们可以通过物联网传感技术采集得到大量的数据，并且需要对这些大量数据进行低功耗、高能效的分析及处理，以快速提取数据特征和信息。
忆阻器(例如阻变存储器、相变存储器、导电桥存储器等)是一种新型的微纳电子器件，可以通过施加外部激励，调节其电导状态。基于忆阻器的神经形态计算突破了传统计算设备的冯诺依曼架构，计算和存储在相同的地方完成，减少了数据搬运的时间，计算时所需能效较高、功耗较低、面积较小。基于忆阻器阵列利用物理定律实现模拟计算是近年来的热点研究领域。
发明内容
本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法，其中，所述数据处理包括复数域的矩阵-向量乘法运算，所述忆阻器阵列包括阵列排布的多个忆阻器单元且配置为能进行乘和运算，所述数据处理方法包括：获取多个第一模拟信号；设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，其中，所述复数域的矩阵包括实部矩阵和虚部矩阵，所述参数矩阵包括所述实部矩阵、所述虚部矩阵以及基于所述虚部矩阵得到的虚部负矩阵，其中，所述虚部负矩阵中的参数元素与所述虚部矩阵中的参数元素一一对应，且所述虚部负矩阵中的每个参数元素为所述虚部矩阵中对应参数元素的负值；将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，控制所述忆阻器阵列操作以对所述多个第一模拟 信号进行所述数据处理，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号。
例如，在本公开至少一实施例提供的数据处理方法中，所述忆阻器阵列包括第一子阵列、第二子阵列、第三子阵列和第四子阵列，设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，包括：将所述实部矩阵中的多个参数元素分别按照所述实部矩阵的形式映射于所述第一子阵列和所述第四子阵列，将所述虚部矩阵中的多个参数元素按照所述虚部矩阵的形式映射于所述第三子阵列，将所述虚部负矩阵中的多个参数元素按照所述虚部负矩阵的形式映射于所述第二子阵列，其中，所述第一子阵列和所述第二子阵列位于所述忆阻器阵列中的相同行但在行方向上不重叠，所述第三子阵列和所述第四子阵列位于所述忆阻器阵列中的相同行但在行方向上不重叠，所述第一子阵列和所述第三子阵列在列方向上不重叠。
例如，在本公开至少一实施例提供的数据处理方法中，所述第一子阵列和所述第三子阵列位于所述忆阻器阵列中的相同列，所述第二子阵列和所述第四子阵列位于所述忆阻器阵列中的相同列。
例如，在本公开至少一实施例提供的数据处理方法中，所述忆阻器阵列至少包括2N行2M列，所述第一子阵列包括所述忆阻器阵列中的第i行至第i+N-1行，第j列至第j+M-1列，所述第二子阵列包括所述忆阻器阵列中的第i行至第i+N-1行，第j+k+M-1列至第j+k+2M-2列，所述第三子阵列包括所述忆阻器阵列中的第i+g+N-1行至第i+g+2N-2行，第j列至第j+M-1列，所述第四子阵列包括所述忆阻器阵列中的第i+g+N-1行至第i+g+2N-2行，第j+k+M-1列至第j+k+2M-2列，其中，M、N、i、j、k和g为正整数。
例如，在本公开至少一实施例提供的数据处理方法中，所述实部矩阵包括阵列排布为N行M列的多个参数元素，将所述实部矩阵中的多个参数元素分别按照所述实部矩阵的形式映射于所述第一子阵列和所述第四子阵列，包括：将所述实部矩阵中位于同一行的N个参数元素分别映射于所述第一子阵列中同一行的N个忆阻器单元，以及所述第四子阵列中同一行的N个忆阻器单元；将所述实部矩阵中位于同一列中的M个参数元素分别映射于所述第一子阵列同一列的M个忆阻器单元，以及所述第四子阵列同一列的M个忆阻器单元。
例如，在本公开至少一实施例提供的数据处理方法中，所述多个第一模拟信号中的每个包括第一实部模拟信号和第一虚部模拟信号，获取所述多个第 一模拟信号，包括：获取用于所述数据处理的复数域的向量，其中，所述复数域的向量包括实部向量和虚部向量；分别对所述实部向量和所述虚部向量进行编码处理，以得到多个第一实部模拟信号和多个第一虚部模拟信号。
例如，在本公开至少一实施例提供的数据处理方法中，将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，包括：将所述多个第一实部模拟信号分别输入所述第一子阵列和所述第三子阵列的列信号输入端；将所述多个第一虚部模拟信号分别输入所述第二子阵列和所述第四子阵列的列信号输入端。
例如，在本公开至少一实施例提供的数据处理方法中，所述多个第二模拟信号中的每个包括第二实部模拟信号和第二虚部模拟信号，所述第一子阵列和所述第二子阵列共用相同的行信号输出端，所述第三子阵列和所述第四子阵列共用相同的行信号输出端，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号，包括：根据所述第一子阵列的行信号输出端输出的电流信号得到多个第二实部模拟信号；根据所述第二子阵列的行信号输出端输出的电流信号得到多个第二实部虚部信号。
例如，本公开至少一实施例提供的数据处理方法还包括：对所述多个第二实部模拟信号进行模数转换处理，以得到所述矩阵-向量乘法运算的实部运算结果；对所述多个第二虚部模拟信号进行模数转换处理，以得到所述矩阵-向量乘法运算的虚部运算结果。
例如，在本公开至少一实施例提供的数据处理方法中，所述参数矩阵表示为
Figure PCTCN2022071337-appb-000001
其中，W real为所述实部矩阵，W img为所述虚部矩阵，-W img为所述虚部负矩阵。
例如，在本公开至少一实施例提供的数据处理方法中，所述参数矩阵包括P行Q列，所述参数矩阵中的第m行第n列的参数元素由第一子矩阵中第m行第n列的参数元素和第二子矩阵中第m行第n列的参数元素共同表示，m、n、P和Q为正整数，所述第一子矩阵包括P行第一参数元素，所述第二子矩阵包括P行第二参数元素，所述P行第一参数元素与所述P行第二参数元素的行列位置一一对应，所述第一子矩阵和所述第二子矩阵排布成 2P行Q列的第一矩阵形式，设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，包括：将所述第一子矩阵和所述第二子矩阵按所述第一矩阵形式映射至所述忆阻器阵列。
例如，在本公开至少一实施例提供的数据处理方法中，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号，包括：确定至少一组待处理行，其中，所述至少一组待处理行中的每组包括与所述P行第一参数元素中的一行所对应的一行目标忆阻器单元，以及与对应于所述P行第一参数元素中的一行的所述P行第二参数元素中的一行所对应的一行目标忆阻器单元；对所述至少一组待处理行中的每组包括的所述两行目标忆阻器单元分别对应的所述多个行信号输出端中的两个的电流信号进行电流预处理，以得到所述至少一组待处理行中的每组对应的所述多个第二模拟信号。
例如，在本公开至少一实施例提供的数据处理方法中，所述忆阻器阵列包括第一忆阻器阵列和第二忆阻器阵列，所述参数矩阵中第u行第v列的参数元素由第一子矩阵中第u行第v列的参数元素和第二子矩阵中第u行第v列的参数元素共同表示，其中，u和v为正整数，所述第一子矩阵与所述第二子矩阵均具有与所述参数矩阵相同的矩阵形式，设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，包括：将所述第一子矩阵对应地按照所述参数矩阵的形式映射于所述第一忆阻器阵列，将所述第二子矩阵对应地按照所述参数矩阵的形式映射于所述第二忆阻器阵列。
例如，在本公开至少一实施例提供的数据处理方法中，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号，包括：对所述第一忆阻器阵列中的所述多个行信号输出端中的每个的电流信号和所述第二忆阻器阵列中对应的所述多个行信号输出端中的每个的电流信号进行电流预处理，以得到所述多个第二模拟信号。
例如，在本公开至少一实施例提供的数据处理方法中，所述电流预处理为电流相减处理或电流相加处理。
例如，在本公开至少一实施例提供的数据处理方法中，所述数据处理为离散傅里叶变换，所述复数域的矩阵为所述离散傅里叶变换的系数矩阵，所述实部矩阵为所述系数矩阵的实部部分，所述虚部矩阵为所述系数矩阵的虚 部部分。
例如，本公开至少一实施例提供一种电子装置，包括：忆阻器阵列，配置为能进行乘和运算；信号获取装置，配置为获取多个第一模拟信号；控制驱动电路，其中，所述控制驱动电路配置为执行以下步骤：设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，其中，所述复数域的矩阵包括实部矩阵和虚部矩阵，所述参数矩阵包括所述实部矩阵、所述虚部矩阵以及基于所述虚部矩阵得到的虚部负矩阵，其中，所述虚部负矩阵中的参数元素与所述虚部矩阵中的参数元素一一对应，且所述虚部负矩阵中的每个参数元素为所述虚部矩阵中对应参数元素的负值；将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，控制所述忆阻器阵列操作以对所述多个第一模拟信号进行所述数据处理，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号。
例如，在本公开至少一实施例提供的电子装置中，所述忆阻器阵列包括第一子阵列、第二子阵列、第三子阵列和第四子阵列，所述控制驱动电路执行设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列时，包括执行以下步骤：将所述实部矩阵中的多个参数元素分别按照所述实部矩阵的形式映射于所述第一子阵列和所述第四子阵列，将所述虚部矩阵中的多个参数元素按照所述虚部矩阵的形式映射于所述第三子阵列，将所述虚部负矩阵中的多个参数元素按照所述虚部负矩阵的形式映射于所述第二子阵列，其中，所述第一子阵列和所述第二子阵列位于所述忆阻器阵列中的相同行但在行方向上不重叠，所述第三子阵列和所述第四子阵列位于所述忆阻器阵列中的相同行但在行方向上不重叠，所述第一子阵列和所述第三子阵列在列方向上不重叠。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例的附图作简单地介绍，显而易见地，下面描述中的附图仅仅涉及本公开的一些实施例，而非对本公开的限制。
图1示出了一种基于忆阻器阵列的DFT实现方法；
图2示出了一种忆阻器阵列的示意性结构；
图3A为1T1R结构的忆阻器单元的示意图；
图3B为2T2R结构的忆阻器单元的示意图；
图4为本公开至少一实施例提供的一种基于忆阻器阵列的数据处理方法的示意性流程图；
图5为本公开至少一实施例提供的一种忆阻器阵列实现原理的示意图；
图6为本公开至少一实施例提供的一种用于数据处理的忆阻器阵列的示意图；
图7A为本公开至少一实施例提供的一种实部矩阵元素的热力图的示意图；
图7B为本公开至少一实施例提供的一种虚部矩阵元素的热力图的示意图；
图7C为本公开至少一实施例提供的一种参数矩阵元素的热力图的示意图；
图8为本公开至少一实施例提供的一种写入参数矩阵后的忆阻器阵列的示意图；
图9为本公开至少一实施例提供的另一种写入参数矩阵后的忆阻器阵列的示意图；
图10A为本公开至少一实施例提供的一种第一子矩阵的电导映射热力图的示意图；
图10B为本公开至少一实施例提供的一种第二子矩阵的电导映射矩阵热力图的示意图；
图11A为本公开至少一实施例提供的一种电子装置的示意性框图；
图11B为本公开至少一实施例提供的一种电子装置的示意图；以及
图11C为本公开至少一实施例提供的另一种电子装置的示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。同样，“一个”、“一”或者“该”等类似词语也不表示数量限制，而是表示存在至少一个。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系，当被描述对象的绝对位置改变后，则该相对位置关系也可能相应地改变。
下面通过几个具体的实施例对本公开进行说明。为了保持本公开实施例的以下说明清楚且简明，可省略已知功能和已知部件的详细说明。当本公开实施例的任一部件在一个以上的附图中出现时，该部件在每个附图中由相同或类似的参考标号表示。
离散傅里叶变换(Discrete Fourier Transform，DFT)是一种常用的信号处理算法，它将信号从时域变换到频域。DFT的定义可以由以下公式表示：
Figure PCTCN2022071337-appb-000002
公式(1)中，x[a]是复数，表示输入信号的时域采样；y[b]是复数，表示输出信号的频域采样；N是实数，表示信号段的长度；i是虚数单位。
例如，上述DFT计算公式可以改写为：
y＝Wx＝y real+iy img＝(W realx real-W imgx img)+i(W realX img+W imgx real)公式(2)
公式(2)中，输出信号y＝y real+iy img是信号的频域采样向量，输入信号x＝x real+ix img是信号的时域采样向量，W＝W real+iW img是离散傅里叶变换的系数矩阵，W real和W img分别是W的实部部分和虚部部分。
例如，W real和W img可以分别用公式(3)和公式(4)表示：
Figure PCTCN2022071337-appb-000003
Figure PCTCN2022071337-appb-000004
在公式(3)和公式(4)中，2π00表示2×π×0×0＝0，2π(N-1)0表示2×π×(N-1)×0＝0，2π(N-1)(N-1)表示2×π×(N-1)×(N-1)，以此类推。
图1示出了一种基于忆阻器阵列的DFT实现方法。如图1所示，该方案主要利用忆阻器实现向量矩阵乘法的特性，用两个忆阻器阵列的电导矩阵分别映射DFT矩阵的实部W real和虚部W img，将输入信号的实部Re(x)(即公式(2)中的x real)和虚部Im(x)(即公式(2)中的x img)，分别用电压脉冲表示，加到相应的阵列上，可以得到Re(W) +(即公式(2)中的W realx real)、Re(W) -(即公式(2)中的W imgx img)、Im(W) +(即公式(2)中的W realx img)和Im(W) -(即公式(2)中的W imgx real)四项运算中间结果(运算中间项)。这四项结果在阵列外经过运算放大器等电路实现加法和减法等功能，最后得到DFT计算结果的实部Re(X)(即公式(2)中的y real)和虚部Im(X)(即公式(2)中的y img)，从而得到完整的DFT计算结果。
上述基于忆阻器阵列的DFT实现方法中，除了忆阻器阵列本身执行向量矩阵乘法运算外，还需要外围辅助运算电路执行各项的加减运算。而运算放大器等辅助运算电路具有不小的面积开销。如果每个输出都对应使用2个运算放大器(一个用于W realx real-W imgx img中的减法，一个用于W realx img+W imgx real中的加法)，则对于N(例如，64，128)点DFT，需要2×N(例如，128，256)个运放，因而增加了额外的电路面积和计算功耗开销。
本公开至少一实施例提供一种基于忆阻器阵列的数据处理方法和电子装置。该基于忆阻器阵列的数据处理方法包括：获取多个第一模拟信号；设置忆阻器阵列，将对应于数据处理的参数矩阵的数据写入忆阻器阵列，其中，复数域的矩阵包括实部矩阵和虚部矩阵，参数矩阵包括实部矩阵、虚部矩阵以及基于虚部矩阵得到的虚部负矩阵，其中，虚部负矩阵中的参数元素与虚部矩阵中的参数元素一一对应，且虚部负矩阵中的每个参数元素为虚部矩阵中对应参数元素的负值；将多个第一模拟信号分别输入设置后的忆阻器阵列的多个列信号输入端，控制忆阻器阵列操作以对多个第一模拟信号进行数据处理，在忆阻器阵列的多个行信号输出端分别得到执行数据处理后的多个第二模拟信号。
该基于忆阻器阵列的数据处理方法对复数域矩阵向量乘法的运算公式进行变形设计以得到对应的参数矩阵，通过将该参数矩阵映射到忆阻器阵列，实现一次计算即可得到复数域矩阵向量乘法运算结果，从而减少了忆阻器阵列外围的辅助运算电路的面积和功耗开销。
本公开的至少一实施例还提供该基于忆阻器阵列的数据处理方法对应的电子装置。
下面结合附图对本公开的实施例进行详细说明，但是本公开并不限于这些具体的实施例。
图2示出了一种忆阻器阵列的示意性结构，该忆阻器阵列由多个忆阻器单元构成，该多个忆阻器单元构成一个r行s列的阵列，r和s均为正整数。每个忆阻器单元包括开关元件和一个或多个忆阻器。在图1中，WL<1>、WL<2>……WL<r>分别表示第一行、第二行……第r行的字线，每一行的忆阻器单元中的开关元件的控制极(例如晶体管的栅极)和该行对应的字线连接；BL<1>、BL<2>……BL<s>分别表示第一列、第二列……第s列的位线，每一列的忆阻器单元中的忆阻器和该列对应的位线连接；SL<1>、SL<2>……SL<r>分别表示第一行、第二行……第r行的源线，每一行的忆阻器单元中的晶体管的源极和该行对应的源线连接。根据基尔霍夫定律，通过设置忆阻器单元的状态(例如电阻值或电导值)并且在字线与位线施加相应的字线信号与位线信号，上述忆阻器阵列可以并行地完成乘积累加计算。
图2的忆阻器阵列中的忆阻器单元例如可以具有1T1R结构或者2T2R结构，其中，1T1R结构的忆阻器单元包括一个晶体管和一个忆阻器，2T2R结构的忆阻器单元包括两个晶体管和两个忆阻器。需要说明的是，本公开对忆阻器单元的结构不作限制，也可以采用可以实现乘积累加运算的其他结构形式的忆阻器单元。
需要说明的是，本公开的实施例中采用的晶体管均可以为薄膜晶体管或场效应晶体管(例如MOS场效应晶体管)或其他特性相同的开关器件。这里采用的晶体管的源极、漏极在结构上可以是对称的，所以其源极、漏极在结构上可以是没有区别的。在本公开的实施例中，为了区分晶体管除栅极之外的两极(即源极和漏极)，直接描述了其中一极为第一极，而另一极为第二极。
图3A为1T1R结构的忆阻器单元的示意图。如图3A所示，1T1R结构的忆阻器单元包括一个晶体管M1和一个忆阻器R1。
本公开的实施例对采用的晶体管的类型不作限定，例如当晶体管M1采用N型晶体管时，其栅极和字线WL连接，例如字线WL输入高电平时晶体管M1导通；晶体管M1的第一极可以是源极并配置为和源线SL连接，例如晶体管M1可以通过源线SL接收复位电压；晶体管M1的第二极可以是漏极并配置为和忆阻器R1的第二极(例如负极)连接，忆阻器R1的第一极(例如正极)和位线BL连接，例如忆阻器R1可以通过位线BL接收置位电压。例如当晶体管M1采用P型晶体管时，其栅极和字线WL连接，例如字线WL输入低电平时晶体管M1导通；晶体管M1的第一极可以是漏极并配置为和源线SL连接，例如晶体管M1可以通过源线SL接收复位电压；晶体管M1的第二极可以是源极并配置为和忆阻器R1的第二极(例如负极)连接，忆阻器R1的第一极(例如正极)和位线BL连接，例如忆阻器R1可以通过位线BL接收置位电压。需要说明的是，忆阻器结构还可以实现为其他结构，例如忆阻器R1的第二极与源线SL连接的结构，本公开的实施例对此不作限制。
下面各实施例均以晶体管M1采用N型晶体管为例进行说明。
字线端WL的作用是对晶体管M1的栅极施加相应电压，从而控制晶体管M1导通或关闭。在对忆阻器R1进行操作时，例如进行置位操作或复位操作，均需要先开启晶体管M1，即需要通过字线端WL对晶体管M1的栅极施加导通电压。在晶体管M1导通后，例如，可以通过在源线端SL和位线端BL向忆阻器R1施加电压，以改变忆阻器R1的阻态。例如，可以通过位线端BL施加置位电压，以使得该忆阻器R1处于低阻态；又例如，可以通过源线端SL施加复位电压，以使得该忆阻器R1处于高阻态。例如，高阻态的电阻值为低阻态的电阻值100倍以上，例如1000倍以上。
需要说明的是，在本公开的实施例中，通过字线端WL和位线端BL同时施加电压，可以使得忆阻器R1的电阻值越来越小，即忆阻器R1从高阻态变为低阻态，将使得忆阻器R1从高阻态变为低阻态的操作称为置位操作；通过字线端WL和源线端SL同时施加电压，可以使得忆阻器R1的电阻值越来越大，即忆阻器R1从低阻态变为高阻态，将使得忆阻器R1从低阻态变为高阻态的操作称为复位操作。例如，忆阻器R1具有阈值电压，在输入电压幅度小于忆阻器R1的阈值电压时，不会改变忆阻R1的电阻值(或电导值)。在这种情况下，可以通过输入小于阈值电压的电压，利用忆阻器R1的电阻值(或电导值)进行计算；可以通过输入大于阈值电压的电压，改变忆阻器R1的电阻 值(或电导值)。
图3B为2T2R结构的忆阻器单元的示意图。如图2B所示，2T2R结构的忆阻器单元包括两个晶体管M1和M2以及两个忆阻器R1和R2。下面以晶体管M1和M2均采用N型晶体管为例进行说明。
晶体管M1的栅极和字线端WL1相连，例如M1的字线端WL1输入高电平时晶体管M1导通，晶体管M2的栅极和字线端WL2相连，例如M2的字线端WL2输入高电平时晶体管M2导通；晶体管M1的第一极可以是源极并被配置为和源线端SL连接，例如晶体管M1可以通过源线端SL接收复位电压，晶体管M2的第一极可以是源极并被配置为和源线端SL连接，例如晶体管M2可以通过源线端SL接收复位电压，晶体管M1的第一极与晶体管M2的第一极相连，并一起连接至源线端SL。晶体管M1的第二极可以是漏极并被配置为和忆阻器R1的第二极(例如负极)连接，忆阻器R1的第一极(例如正极)和位线端BL1连接，例如忆阻器R1可以通过位线端BL1接收置位电压；晶体管M2的第二极可以是漏极并被配置为和忆阻器R2的第二极(例如负极)连接，忆阻器R2的第一极(例如正极)和位线端BL2连接，例如忆阻器R2可以通过位线端BL2接收置位电压。
需要说明的是，2T2R结构的忆阻器单元中的晶体管M1和M2也可以均采用P型晶体管，这里不再赘述。
图4为本公开至少一实施例提供的一种基于忆阻器阵列的数据处理方法的示意性流程图。
例如，如图4所示，本公开实施例提供的基于忆阻器阵列的数据处理方法包括步骤S110至S130，并且，该忆阻器阵列包括阵列排布的多个忆阻器单元且配置为能进行乘和运算(也即乘积累加运算，将乘法的乘积结果进行累加处理，以得到乘加结果累加后的和值)。例如，该忆阻器阵列的结构示意图如图2所示，每个忆阻器单元可以为如图3A所示的1T1R结构或者如图3B所示的2T2R结构。
在步骤S110，获取多个第一模拟信号。
在步骤S120，设置忆阻器阵列，将对应于数据处理的参数矩阵的数据写入忆阻器阵列。
例如，复数域的矩阵包括实部矩阵和虚部矩阵，参数矩阵包括实部矩阵、虚部矩阵以及基于虚部矩阵得到的虚部负矩阵。
例如，虚部负矩阵中的参数元素与虚部矩阵中的参数元素一一对应，且虚部负矩阵中的每个参数元素为虚部矩阵中对应参数元素的负值。例如，虚部负矩阵通过对虚部矩阵中的每个参数元素取负值得到。
在步骤S130，将多个第一模拟信号分别输入设置后的忆阻器阵列的多个列信号输入端，控制忆阻器阵列操作以对多个第一模拟信号进行数据处理，在忆阻器阵列的多个行信号输出端分别得到执行数据处理后的多个第二模拟信号。
例如，多个第一模拟信号为待进行数据处理的输入信号，多个第二模拟信号为对输入信号执行数据处理后的输出信号。
例如，第一模拟信号为模拟电压信号，第二模拟信号为模拟电流信号。
例如，每个第一模拟信号可以包括第一实部模拟信号和第一虚部模拟信号，每个第二模拟信号可以包括第二实部模拟信号和第二虚部模拟信号。
例如，在一些示例中，复数域矩阵向量乘法的计算公式可以表示为以下形式：
y t＝W tx t                    公式(5)
Figure PCTCN2022071337-appb-000005
y t＝[y real,y img] T                公式(7)
x t＝[x real,x img] T                公式(8)
例如，上述公式(5)为复数域矩阵-向量乘法的计算公式的表示形式；在上述公式(6)中，W t为用于数据处理的参数矩阵，W real为实部矩阵，W img为虚部矩阵，-W img为虚部负矩阵；在上述公式(7)中，y t为矩阵-向量乘法运算的运算结果，该运算结果包括实部运算结果y real和虚部运算结果y img；在上述公式(8)中，x t为用于数据处理的复数域的向量，包括实部向量x real和虚部向量x img。
例如，在步骤S110中，获取所述多个第一模拟信号可以包括：获取用于数据处理的复数域的向量x t，其中，复数域的向量x t包括实部向量x real和虚部向量x img；分别对实部向量x real和虚部向量x img进行编码处理，以得到多个第一实部模拟信号和多个第一虚部模拟信号。
例如，通过编码处理将复数域的向量x t编码成电压脉冲向量，也即将实部 向量x real和虚部向量x img中的每个参数元素编码成对应的电压脉冲，由此得到实部向量x real中每个参数元素对应的第一实部模拟信号和虚部向量x real中每个参数元素对应的第一虚部模拟信号。
例如，编码处理包括数模转换处理，在编码处理过程中，可以利用脉冲个数来对参数元素进行编码处理，也可以用脉冲幅度编码对参数元素进行编码处理，本公开对编码处理的具体过程不作限制。
例如，用于数据处理的复数域的向量x t可以为一段长度为N的数字信号，即实部向量x real为数字信号的实部部分，虚部向量x img为数字信号的虚部部分。
例如，数字信号可以为预先存储的数字信号；例如，数字信号可以为实时获取的数字信号。将数字信号进行数模转换处理以得到多个第一模拟信号。
例如，忆阻器阵列包括第一子阵列、第二子阵列、第三子阵列和第四子阵列。
例如，步骤S120可以包括：将实部矩阵中的多个参数元素分别按照实部矩阵的形式映射于第一子阵列和第四子阵列，将虚部矩阵中的多个参数元素按照虚部矩阵的形式映射于第三子阵列，将虚部负矩阵中的多个参数元素按照虚部负矩阵的形式映射于第二子阵列，其中，第一子阵列和第二子阵列位于忆阻器阵列中的相同行但在行方向上不重叠，第三子阵列和第四子阵列位于忆阻器阵列中的相同行但在行方向上不重叠，第一子阵列和第三子阵列在列方向上不重叠。
例如，第一子阵列和第三子阵列位于忆阻器阵列中的相同列，第二子阵列和第四子阵列位于忆阻器阵列中的相同列。
例如，在一些实施例中，第一子阵列和第三子阵列位于忆阻器阵列中的不同列，第二子阵列和第四子阵列位于忆阻器阵列中的不同列。例如，忆阻器阵列G t可以表示为G t＝[G 1,G 2,O 3,O 4；O 1,O 2,G 3,G 4]的形式，其中，G 1为第一子阵列，G 2为第二子阵列，G 3为第三子阵列，G 4为第四子阵列，O 1、O 2、O 3和O 4中的忆阻器为未被映射的初始状态。例如，当忆阻器处于未被映射的初始状态时，忆阻器电导接近0。
图5为本公开至少一实施例提供的一种忆阻器阵列实现原理的示意图。
例如，如图5所示，基于公式(5)～公式(8)的形式，复数域矩阵-向量乘法可以由忆阻器阵列实现，即用忆阻器阵列代表W real、-W img、W real和W img组成的参数矩阵W t。
例如，将实部向量x real对应的多个第一实部模拟信号输入忆阻器阵列中的W real和W img中 ，将虚部向量x img对应的多个第一虚部模拟信号输入忆阻器阵列中的-W img和W real中，由此，得到实部运算结果y real和虚部运算结果y img。
该方法直接用忆阻器阵列的一部分表示虚部负矩阵-W img，并通过基尔霍夫电流定律在忆阻器阵列上直接进行乘积累加计算，消减了设置在忆阻器阵列外围的对运算中间结果做加法、减法等的运算放大器等处理电路的开销，实现一次运算即可得到复数域的矩阵-向量乘法的全部运算结果，提升计算效率，降低电路开销，节约电路面积。
图6为本公开至少一实施例提供的一种用于数据处理的忆阻器阵列的示意图。
例如，如图6所示，忆阻器阵列至少包括2N行2M列，M和N均为正整数。
例如，如图6所示，忆阻器阵列可以包括第一子阵列、第二子阵列、第三子阵列和第四子阵列。
例如，如图6所示，SL<i>、SL<i+1>……SL<i+N-1>分别表示第i行、第i+1行……第i+N-1行的源线，第一子阵列和第二子阵列中的晶体管的源极和第i行、第i+1行……第i+N-1行的源线连接；SL<i+g+N-1>、SL<i+g+N>……SL<i+g+2N-2>分别表示第i+g+N-1行、第i+g+N行……第i+g+2N-2行的源线，第三子阵列和第四子阵列中的晶体管的源极和第i+g+N-1行、第i+g+N行……第i+g+2N-2行的源线连接。
例如，BL<j>、BL<j+1>……BL<j+M-1>分别表示第j列、第j+1列……第j+M-1列的位线，第一子阵列和第三子阵列中的忆阻器单元中的忆阻器与第j列、第j+1列……第j+M-1列的位线连接；BL<j+k+M-1>、BL<j+k+M>……BL<j+k+2M-2>分别表示第j+k+M-1列、第j+k+M列……第j+k+2M-2列的位线，第二子阵列和第四子阵列中的忆阻器单元中的忆阻器与第j+k+M-1列、第j+k+M列……第j+k+2M-2列的位线连接。其中，i、j、k和g为正整数。
例如，第一子阵列和第二子阵列可以位于忆阻器阵列中的相同行但在行方向上不重叠。例如，第一子阵列包括忆阻器阵列中的第i行至第i+N-1行，第j列至第j+M-1列，即第一子阵列G 1＝[G ij…G i(j+M-1)；…；G (i+N-1)j…G (i+N-1)(j+M-1)]；第二子阵列包括忆阻器阵列中的第i行至第i+N-1行，第j+k+M-1列至第 j+k+2M-2列，即第二子阵列G 2＝[G i(j+k+M-1)…G i(j+k+2M-2)；…；G (i+N-1)(j+k+M-1)…G (i+N- 1)(j+k+2M-2)]。
例如，第三子阵列和第四子阵列可以位于所述忆阻器阵列中的相同行但在行方向上不重叠，第一子阵列和第三子阵列在列方向上不重叠。例如，第三子阵列包括忆阻器阵列中的第i+g+N-1行至第i+g+2N-2行，第j列至第j+M-1列，即第三子阵列G 3＝[G (i+g+N-1)j…G (i+g+N-1)(j+M-1)；…；G (i+g+2N-2)j…G (i+g+2N-2)(j+M-1)]；第四子阵列包括忆阻器阵列中的第i+g+N-1行至第i+g+2N-2行，第j+k+M-1列至第j+k+2M-2列，即第四子阵列G 4＝[G (i+g+N-1)(j+k+M-1)…G (i+g+N-1)(j+k+2M-2)；…；G (i+g+2N-2)(j+k+M-1)…G (i+g+2N-2)(j+k+2M-2)]。
需要说明的是，对于例如公式(1)中的DFT，其信号段长度为N。根据公式(3)、公式(4)和公式(6)，该DFT对应的用于数据处理的参数矩阵W t包括2N行2N列。因此，该DFT对应的的参数矩阵W t映射后的例如图6所示的忆阻器阵列也包括2N行2N列，即M等于N。其中，M和N为正整数。
例如，实部矩阵包括阵列排布为N行M列的多个参数元素。将实部矩阵中的多个参数元素分别按照实部矩阵的形式映射于第一子阵列和第四子阵列，包括：将实部矩阵中位于同一行的N个参数元素分别映射于第一子阵列中同一行的N个忆阻器单元，以及第四子阵列中同一行的N个忆阻器单元；将实部矩阵中位于同一列中的M个参数元素分别映射于第一子阵列同一列的M个忆阻器单元，以及第四子阵列同一列的M个忆阻器单元。
例如，虚部矩阵包括阵列排布为N行M列的多个参数元素。将虚部矩阵中的多个参数元素按照虚部矩阵的形式映射于第三子阵列，包括：将虚部矩阵中位于同一行的N个参数元素分别映射于第三子阵列中同一行的N个忆阻器单元，将虚部矩阵中位于同一列中的M个参数元素分别映射于第三子阵列同一列的M个忆阻器单元。
例如，虚部负矩阵包括阵列排布为N行M列的多个参数元素。将虚部负矩阵中的参数元素按照虚部负矩阵的形式映射于第二子阵列，包括：将虚部负矩阵中位于同一行的N个参数元素分别映射于第二子阵列中同一行的N个忆阻器单元，将虚部负矩阵中位于同一列中的M个参数元素分别映射于第二子阵列同一列的M个忆阻器单元。
例如，每个忆阻器单元可以为1T1R结构，如图3A所示，也即每个忆阻器单元包括1个忆阻器，通过该忆阻器的电导值表示对应的参数元素。
例如，每个忆阻器单元可以为2T2R结构，如图3B所示，也即每个忆阻器单元包括两个忆阻器，可以利用两个忆阻器的电导值实现参数元素的负值，从而可以利用多个忆阻器单元实现更加丰富、复杂的数据处理。
例如，在步骤S130中，将多个第一模拟信号分别输入设置后的忆阻器阵列的多个列信号输入端，包括：将多个第一实部模拟信号分别输入第一子阵列和第三子阵列的列信号输入端；将多个第一虚部模拟信号分别输入第二子阵列和第四子阵列的列信号输入端。
例如，第一子阵列和第三子阵列共用相同的列信号输入端，共同接收基于实部向量x real得到的多个第一实部模拟信号。例如，第二子阵列和第四子阵列共用相同的列信号输入端，共同接收基于虚部向量x img得到的多个第一虚部模拟信号。
例如，第一子阵列和第三子阵列也可以不共用相同的列信号输入端，将多个第一实部模拟信号通过不同的列信号输入端分别输入第一子阵列和第三子阵列。同样的，第二子阵列和第四子阵列也可以不共用相同的列信号输入端，将多个第一实部模拟信号输入通过不同的列信号输入端分别输入第二子阵列和第四子阵列。
对于步骤S130，例如，可以将多个第一模拟信号分别施加至设置后的忆阻器阵列的多个列信号输入端，同时将开启信号施加至忆阻器阵列的多个信号控制端，检测并获取忆阻器阵列的多个行信号输出端的多个电流信号，并基于多个电流信号得到多个第二模拟信号。
例如，如图6所示，在第j列、第j+1列……第j+M-1列的位线的多个列信号输入端上输入第一实部模拟信号V j、V j+1……V j+M-1，在第j+k+M-1列、第j+k+M列……第j+k+2M-2列的位线的多个列信号输入端上输入第一虚部模拟信号V j+k+M-1、V j+k+M……V j+k+2M-2。经过第一子阵列、第二子阵列、第三子阵列和第四子阵列中忆阻器单元的计算处理，在第i行、第i+1行……第i+N-1行的源线的行信号输出端上输出第二实部模拟信号I i、I i+1……I i+N-1，在第i+g+N-1行、第i+g+N行……第i+g+2N-2行的源线的行信号输出端上输出第二虚部模拟信号I i+g+N-1、I i+g+N……I i+g+2N-2。
例如，在步骤S130中，在忆阻器阵列的多个行信号输出端分别得到执行数据处理后的多个第二模拟信号，可以包括：根据第一子阵列的行信号输出端输出的电流信号得到多个第二实部模拟信号；根据第二子阵列的行信号输出 端输出的电流信号得到多个第二实部虚部信号。
例如，本公开至少一实施例提供的基于忆阻器阵列的数据处理方法还可以包括：对多个第二模拟信号进行模数转换处理，以将多个第二模拟信号分别转换为多个数字信号以用于进行后续处理。
例如，对多个第二实部模拟信号进行模数转换处理，以得到复数域的矩阵-向量乘法运算的实部运算结果，也即公式(7)中的实部运算结果y real；对多个第二虚部模拟信号进行模数转换处理，以得到复数域的矩阵-向量乘法运算的虚部运算结果，也即公式(7)中的虚部运算结果y img。
下面以复数域的矩阵-向量乘法运算为离散傅里叶变换为例，具体描述及示出参数矩阵及忆阻器映射关系。
图7A为本公开至少一实施例提供的一种实部矩阵的热力图的示意图；图7B为本公开至少一实施例提供的一种虚部矩阵的热力图的示意图；图7C为本公开至少一实施例提供的一种参数矩阵的热力图的示意图。
例如，如图7A、图7B和图7C所示的热力图中的横纵坐标表示信号段长度，由横纵坐标确定每个点表示矩阵中对应位置的参数元素，图中右侧的矩形渐变色条表示云图中不同位置的参数元素的数值，不同数值对应不同的灰度值，数值范围从-1至1。
例如，复数域的矩阵可以为离散傅里叶变换的系数矩阵。关于系数矩阵的定义和表达形式参考公式(1)～公式(4)。以信号段长度N＝128为例，根据公式(3)和公式(4)，计算出DFT的实部矩阵W real和虚部矩阵W img，由此，得到如图7A所示为实部矩阵W real的热力图，以及如图7B所示为虚部矩阵W img的热力图。例如，将虚部矩阵W img中的每个参数元素取负值得到虚部负矩阵-W img。将实部矩阵W real、虚部矩阵W img和虚部负矩阵-W img按照公式(6)排列得到该DFT的参数矩阵W t，由此，得到如图7C所示为参数矩阵W t的热力图。
例如，参数元素的数值可能为正数也可能为负数，例如，每个参数元素可以利用两个忆阻器的电导值来表示，例如，利用两个忆阻器的电导值之差来代表一个参数元素，或者，利用两个忆阻器的电导值之和来代表一个参数元素。
例如，参数矩阵可以由第一子矩阵和第二子矩阵共同表示。例如，参数矩阵包括P行Q列，参数矩阵中的第m行第n列的参数元素由第一子矩阵中第m行第n列的参数元素和第二子矩阵中第m行第n列的参数元素共同表示， m、n、P和Q为正整数。也就是说，参数矩阵中的第m行第n列的参数元素为第一子矩阵中第m行第n列的参数元素和第二子矩阵中第m行第n列的参数元素之和或之差。
例如，第一子矩阵包括P行第一参数元素，第二子矩阵包括P行第二参数元素，P行第一参数元素与P行第二参数元素的行列位置一一对应，第一子矩阵和第二子矩阵排布成2P行Q列的第一矩阵形式。例如，第一子矩阵和第二子矩阵具有前述参数矩阵相同的矩阵形式。
例如，步骤S120可以包括：将第一子矩阵和第二子矩阵按第一矩阵形式映射至忆阻器阵列。
此时对于步骤S130，例如，在忆阻器阵列的多个行信号输出端分别得到执行数据处理后的多个第二模拟信号，可以包括：确定至少一组待处理行，其中，至少一组待处理行中的每组包括与P行第一参数元素中的一行所对应的一行目标忆阻器单元，以及与对应于P行第一参数元素中的一行的P行第二参数元素中的一行所对应的一行目标忆阻器单元；对至少一组待处理行中的每组包括的两行目标忆阻器单元分别对应的多个行信号输出端中的两个的电流信号进行电流预处理，以得到至少一组待处理行中的每组对应的多个第二模拟信号。
例如，电流预处理为电流相减处理或电流相加处理。
图8为本公开至少一实施例提供的一种写入参数矩阵后的忆阻器阵列的示意图。
例如，图8中的V 1至V Q分别为Q个第一模拟信号，分别输入Q个列信号输入端，图8中的I 1+至I P+和I 1-至I P-分别为2P个行信号输出端所输出的2P个电流信号，基于2P个电流信号得到P个第二模拟信号I 1至I P，P和Q为正整数。
例如，如图8所示，参数矩阵W对应于忆阻器的电导矩阵G 0＝[G 11…G 1Q；…；G P1…G PQ]，第一子矩阵W 1对应于忆阻器的电导矩阵G t+＝[G 11+…G 1Q+；…；G P1+…G PQ+]，第二子矩阵W 2对应于忆阻器的电导矩阵G t-＝[G 11-…G 1Q-；…；G P1-…G PQ-]，G表示参数元素的数值对应于忆阻器的电导值。第一子矩阵W 1中位于第m行第n列的参数元素对应的电导值G mn+和第二子矩阵W 2中位于第m行第n列的参数元素对应的电导值G mn-共同表示执行数据处理的参数元素对应的电导值G mn，也即是，用于执行数据处理的参数矩阵W由第 一子矩阵W 1和对应的第二子矩阵W 2共同表示。
例如，每个用于执行数据处理的参数元素可以由第一子矩阵W 1和第二子矩阵W 2中对应行列位置的参数元素之差表示，从而可以利用第一子矩阵和对应的第二子矩阵实现参数元素的负值，以执行更加丰富、复杂的数据处理。
例如，将第一子矩阵W 1和第二子矩阵W 2排布成2P行Q列的第一矩阵W 0形式，即W 0映射到忆阻器上的电导矩阵G t＝[G 11+…G 1Q+；…；G P1+…G PQ+；G 11-…G 1Q-；…；G P1-…G PQ-]。
例如，在步骤S120，将第一子矩阵W 1和第二子矩阵W 2按第一矩阵W 0的形式映射到忆阻器阵列中，例如，第一子矩阵W 1映射为图8所示的忆阻器子阵列A，第二子矩阵W 2映射为图8所示的忆阻器子阵列B。忆阻器子阵列A和忆阻器子阵列B如图8中黑色粗实线标记的区域所示。具体的映射过程如前所述，这里不再赘述。
例如，在步骤S130，图8所示的忆阻器阵列对应的一组待处理行包括：位于忆阻器子阵列A中的第m行(例如忆阻器阵列第m行)中的一行目标忆阻器单元(G m1+,G m2+…G mQ+)，以及位于忆阻器子阵列B中的第m行(例如忆阻器阵列第P+m行)中的一行目标忆阻器单元(G m1-,G m2-…G mQ-)。例如，将忆阻器阵列中的第m行的行信号输出端的电流信号I m+和第P+m行的行信号输出端的电流信号I m-进行电流预处理，以得到第二模拟信号I m。以此类推，按照上述方式得到执行数据处理后的P个第二模拟信号。
例如，上述电流预处理为电流相减处理。在另一些示例中，电流预处理也可以为电流相加处理。
需要说明的是，图8所示的映射状态仅是一种示意，例如，还可以将第一子矩阵和第二子矩阵以行为单位映射至忆阻器阵列中，本公开对此不作限制。例如，第一子矩阵的第一行参数元素映射至忆阻器阵列的第一行，第二子矩阵的第一行参数元素映射至忆阻器阵列的第二行，第一子矩阵的第二行参数元素映射至忆阻器阵列的第三行，第二子矩阵的第二行参数元素映射至忆阻器阵列的第四行，以此类推。
例如，还可以利用两个对应设置的第一忆阻器阵列和第二忆阻器阵列，并将对应的行信号输出端的电流信号进行预处理以得到第二模拟信号，以实现参数元素的负值，执行更加丰富、复杂的数据处理。
例如，忆阻器阵列包括第一忆阻器阵列和第二忆阻器阵列，参数矩阵中第 u行第v列的参数元素由第一子矩阵中第u行第v列的参数元素和第二子矩阵中第u行第v列的参数元素共同表示，其中，u和v为正整数，第一子矩阵与第二子矩阵均具有与参数矩阵相同的矩阵形式。
例如，步骤S120可以包括：将第一子矩阵对应地按照参数矩阵的形式映射于第一忆阻器阵列，将第二子矩阵对应地按照参数矩阵的形式映射于第二忆阻器阵列。
此时对于步骤S130，例如，在忆阻器阵列的多个行信号输出端分别得到执行数据处理后的多个第二模拟信号，包括：对第一忆阻器阵列中的多个行信号输出端中的每个的电流信号和第二忆阻器阵列中对应的多个行信号输出端中的每个的电流信号进行电流预处理，以得到多个第二模拟信号。
例如，电流预处理为电流相减处理或电流相加处理。
图9为本公开至少一实施例提供的另一种写入参数矩阵后的忆阻器阵列的示意图，该实施例可以与图9所示的实施例实现相同的数据处理。
图9所示的忆阻器阵列包括第一忆阻器阵列和第二忆阻器阵列，每个忆阻器阵列具有独立的控制电路，例如具有独立的列信号输入端，以分别输入Q个第一模拟信号V 1至V Q，以及独立的行信号输出端，以输出电流信号I 1+至电流信号I P+和电流信号I 1-至电流信号I P-。例如，图9中的I 1至I P表示P个经过数据处理后的第二模拟信号。
例如，参数矩阵包括P行Q列，参数矩阵中第u行第v列的参数元素由第一子矩阵中第u行第v列的参数元素和第二子矩阵中第u行第v列的参数元素共同表示，其中，u和v为正整数。第一子矩阵与第二子矩阵均具有与参数矩阵相同的矩阵形式。也即是，第一子矩阵为P行Q列，第二子矩阵也为P行Q列，第一子矩阵和第二子矩阵中对应行列位置的参数元素共同表示执行所述数据处理的一个参数元素，例如，每个用于执行数据处理的参数元素由第一子矩阵W 1和第二子矩阵W 2中对应行列位置的参数元素之和或之差表示。
例如，参数矩阵W对应于忆阻器的电导矩阵G 0＝[G 11…G 1Q；…；G P1…G PQ]，第一子矩阵W 1对应于忆阻器的电导矩阵G t+＝[G 11+…G 1Q+；…；G P1+…G PQ+]，第二子矩阵W 2对应于忆阻器的电导矩阵G t-＝[G 11-…G 1Q-；…；G P1-…G PQ-]。第一子矩阵W 1中位于第u行第v列的参数元素对应的电导值G uv+和第二子矩阵W 2中位于第u行第v列的参数元素对应的电导值G uv-共同表示执行数据处理的参数元素对应的电导值G uv。也即是，用于执行数据处理的参数矩阵W由第 一子矩阵W 1和对应的第二子矩阵W 2共同表示。
例如，每个用于执行数据处理的参数元素可以由第一子矩阵W 1和第二子矩阵W 2中对应行列位置的参数元素之差表示，从而可以利用第一子矩阵和对应的第二子矩阵实现参数元素的负值，以执行更加丰富、复杂的数据处理。
例如，如图9所示，在步骤S120，将第一子矩阵对应地按照参数矩阵的形式映射于第一忆阻器阵列，将第二子矩阵对应地按照参数矩阵的形式映射于第二忆阻器阵列。具体的映射过程如前所述，这里不再赘述。
例如，根据步骤S130，将第一忆阻器阵列中的第u行的行信号输出端的电流信号I u+和第二忆阻器阵列中的第u行的行信号输出端的电流信号I u-进行电流预处理，以得到第二模拟信号I u。以此类推，按照上述方式得到执行数据处理后的P个第二模拟信号。
例如，上述电流预处理为电流相减处理。在另一些示例中，电流预处理也可以为电流相加处理。
例如，以数据处理为离散傅里叶变换为例，参考图7A-图7C得到参数矩阵W t，将参数矩阵W t中用于执行数据处理的参数元素由第一子矩阵和第二子矩阵中对应行列位置的参数元素之差来表示。
图10A为本公开至少一实施例提供的一种第一子矩阵的电导映射热力图的示意图；图10B为本公开至少一实施例提供的一种第二子矩阵的电导映射矩阵热力图的示意图。
例如，如图10A和图10B所示，将参数矩阵W t映射到忆阻器阵列，映射时使用的最低忆阻器电导G min＝2uS，最高忆阻器电导G max＝20uS，uS表示电导单位。
如图10A所示，将第一子矩阵W1按照步骤S120中的方式映射到第一忆阻器阵列，例如，按照第一子矩阵W1将相应的忆阻器编程到相应的电导状态；如图10B所示，将第二子矩阵W2按照步骤S120中的方式映射到忆阻器阵列，例如，按照第二子矩阵W2将相应的忆阻器编程到相应的电导状态。参数矩阵W t中的参数元素由映射至第一忆阻器阵列的第一子矩阵和映射至第二忆阻器阵列的第二子矩阵对应行列位置的参数元素共同表示。
该基于忆阻器阵列的数据处理方法通过对复数域的矩阵的实部矩阵、虚部矩阵进行取负、整合设计，可以实现一次计算(或一个计算周期)即可得到复数域的矩阵-向量乘法操作的所有结果，大大减少了传统方案中用于实现加 减法等功能的外围电路的面积和功耗开销，降低了功耗，提高了计算速度。
与上述基于忆阻器阵列的数据处理方法相对应，本公开至少一实施例还提供一种电子装置，图11A为本公开至少一实施例提供的一种电子装置的示意性框图。
如图11A所示，电子装置100包括忆阻器阵列101、信号获取装置102以及控制驱动电路103。忆阻器阵列101配置为能进行乘和运算，以上述执行数据处理。信号获取装置102配置为获取多个第一模拟信号。控制驱动电路103被配置为执行步骤S120至S130。
例如，忆阻器阵列101可以采用图2所示的忆阻器阵列，忆阻器阵列包括阵列排布的多个忆阻器单元，忆阻器阵列包括r行s列。例如，每个忆阻器单元包括忆阻器，每个忆阻器包括第一端和第二端，且该忆阻器能被设置为初始状态，也能被设置(置位)为具有一定电阻值的置位状态。当忆阻器处于初始状态时，其电阻值远大于处于置位状态的电阻。例如，每个忆阻器单元还包括开关元件，开关元件包括控制端、第一极和第二极，忆阻器的第一端与开关元件的第一极电连接。
例如，忆阻器阵列还包括r条字线、r条源线和s条位线。r条字线分别与r行对应，每条字线与一行忆阻器单元的各个开关元件的控制端电连接；r条源线分别与r行对应，每条源线与一行忆阻器单元的各个开关元件的第二极电连接；s条位线分别与s列对应，且每条位线与一列忆阻器单元的各个忆阻器的第二端电连接。
例如，信号获取装置102包括数字信号获取电路和数模转换电路。例如，数字信号获取电路配置为获取多个初始数字信号；数模转换电路配置为对多个初始数字信号进行数模转换处理，以分别得到多个第一模拟信号。
例如，控制驱动电路103可以包括源线驱动电路、字线驱动电路和位线驱动电路。源线驱动电路配置为对多个第二模拟信号进行检测和对忆阻器阵列执行初始化操作；字线驱动电路配置为对忆阻器阵列的多个信号控制端施加开启信号和对忆阻器阵列执行初始化操作；位线驱动电路配置为对多个列信号输入端施加输入信号和对忆阻器阵列执行初始化操作，其中，输入信号至少包括多个第一模拟信号。
例如，控制驱动电路103可以通过位线驱动电路向忆阻器阵列的多个列信号输入端施加输入信号，通过字线驱动电路同时将开启信号施加至忆阻器 阵列的多个信号控制端，最终通过源线驱动电路对设置后的忆阻器阵列的多个行信号输出端的电流信号进行处理，以得到多个第二模拟信号。
例如，电子装置100还可以进一步包括数据输出电路，其中，该数据输出电路配置为将多个第二模拟信号转换为数字信号，以将多个第二模拟信号分别转换为多个数字信号以用于进行后续处理。
需要说明的是，关于通过信号获取装置102获取多个第一模拟信号的具体说明可以参考上述基于忆阻器阵列的数据处理方法的实施例中图4所示的步骤S110的相关描述；控制驱动电路103用于实现图4所示的步骤S120至步骤S130，关于控制驱动电路103的具体说明可以参考上述基于忆阻器阵列的数据处理方法的实施例中图4所示的步骤S120至步骤S130的相关描述。此外，电子装置可以实现与前述基于忆阻器阵列的数据处理方法相似的技术效果，在此不再赘述。
图11B为本公开至少一实施例提供的一种电子装置示意图。例如，如图11B所示，电子装置包括信号获取装置、字线驱动电路、位线驱动电路、源线驱动电路、忆阻器阵列以及数据输出电路。
例如，信号获取装置配置为将数字信号通过DAC(Digital to Analog converter，数字模拟转换器)转换为多个第一模拟信号，以在进行数据处理时输入至忆阻器阵列的多个列信号输入端。
例如，用于进行复数域的矩阵-向量乘法运算的矩阵为M行N列，M和N为正整数，忆阻器阵列至少包括2N条源线、2N条字线和2M条位线，以及阵列排布为2N行2M列的多个忆阻器单元(例如，对应于图6中2N行2M列的忆阻器阵列)。例如，每个忆阻器单元为1T1R结构，将用于数据处理的参数矩阵映射于忆阻器阵列，具体过程如步骤S120所述，这里不再赘述。
例如，通过字线驱动电路、位线驱动电路和源线驱动电路实现数据处理的过程如前所述，这里不再赘述。
例如，字线驱动电路包括多个多路选择器(Multiplexer，简称Mux)，用于切换字线输入电压，位线驱动电路包括多个多路选择器，用于切换位线输入电压，源线驱动电路也包括多个多路选择器，用于切换源线输入电压。
例如，忆阻器阵列包括操作模式和计算模式。当忆阻器阵列处于操作模式时，忆阻器单元处于初始化状态，可以将参数矩阵中的参数元素的数值写入忆阻器阵列中。例如，将忆阻器的源线输入电压、位线输入电压和字线输入电压 通过多路选择器切换至对应的预设电压区间。
例如，通过图11B中的字线驱动电路中的多路选择器的控制信号WL_sw[1:2N]将字线输入电压切换至相应的电压区间。例如在对忆阻器进行置位操作时，将字线输入电压设置为2V(伏特)，例如在对忆阻器进行复位操作时，将字线输入电压设置为5V，例如，字线输入电压可以通过图11B中的电压信号V_WL[1:2N]得到。
例如，通过图11B中的源线驱动电路中的多路选择器的控制信号SL_sw[1:2N]将源线输入电压切换至相应的电压区间。例如在对忆阻器进行置位操作时，将字线输入电压设置为0V，例如在对忆阻器进行复位操作时，将源线输入电压设置为2V，例如，源线输入电压可以通过图11B中的电压信号V_SL[1:2N]得到。
例如，通过图11B中的位线驱动电路中的多路选择器的控制信号BL_sw[1:2M]将位线输入电压切换至相应的电压区间。例如在对忆阻器进行置位操作时，将位线输入电压设置为2V，例如在对忆阻器进行复位操作时，将位线输入电压设置为0V，例如，源线输入电压可以通过图11B中DAC得到。
当忆阻器阵列处于计算模式时，此时，忆阻器阵列中的忆阻器处于可用于计算的导电状态，列信号输入端输入的位线输入电压不会改变忆阻器的电导值，以通过忆阻器阵列执行乘和运算完成数据处理。例如，通过图11B中的字线驱动电路中的多路选择器的控制信号WL_sw[1:2N]将字线输入电压切换至相应的电压区间，例如施加开启信号时，相应行的字线输入电压设置为5V，例如不施加开启信号时，相应行的字线输入电压设置为0V，例如接通GND信号；通过图11B中的源线驱动电路中的多路选择器的控制信号SL_sw[1:2N]将源线输入电压切换至相应的电压区间，例如将源线输入电压设置为0V，从而使得多个行信号输出端的电流信号可以流入数据输出电路，通过图11B中的位线驱动电路中的多路选择器的控制信号BL_sw[1:2M]将位线输入电压切换至相应的电压区间，例如将位线输入电压设置为0.1V-0.3V，从而利用忆阻器阵列可进行乘和运算的特性完成数据处理。
例如，数据输出电路包括多个ADC(Analog to Digital converter，模拟数字转换器)，可以将多个行信号输出端的电流信号转换为数字信号，以用于后续处理。
图11C为本公开至少一实施例提供的另一种电子装置示意图。
图11C所示的电子装置与图11B所示的电子装置的结构相同，也包括信号获取装置、字线驱动电路、位线驱动电路、源线驱动电路、忆阻器阵列以及数据输出电路。
例如，忆阻器阵列包括2N条源线、4N条字线和4M条位线，以及阵列排布为2N行2M列的多个忆阻器单元(例如，对应于图6中2N行2M列的忆阻器阵列)。例如，每个忆阻器单元为2T2R结构，将用于数据处理的参数矩阵多次映射于忆阻器阵列中不同的多个子阵列，具体过程如步骤S120所述，这里不再赘述。
需要说明的是，忆阻器阵列也可以包括2N条源线、2N条字线和4M条位线，以及阵列排布为2N行2M列的多个忆阻器单元。由于在执行步骤S130时为同时将开启信号施加至忆阻器阵列的多个信号控制端，可以由每条字线同时控制每行忆阻器单元中的两个忆阻器。
关于信号获取装置、控制驱动电路以及数据输出电路的描述如前所述，这里不再赘述。
以上描述仅为本公开的较佳实施例以及对所运用技术原理的说明。本领域技术人员应当理解，本公开中所涉及的公开范围，并不限于上述技术特征的特定组合而成的技术方案，同时也应涵盖在不脱离上述公开构思的情况下，由上述技术特征或其等同特征进行任意组合而形成的其它技术方案。例如上述特征与本公开中公开的(但不限于)具有类似功能的技术特征进行互相替换而形成的技术方案。
此外，虽然采用特定次序描绘了各操作，但是这不应当理解为要求这些操作以所示出的特定次序或以顺序次序执行来执行。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实施例中。相反地，在单个实施例的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实施例中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。
对于本公开，有以下几点需要说明：
(1)本公开实施例附图中，只涉及到与本公开实施例涉及到的结构，其他结构可参考通常设计。
(2)在不冲突的情况下，本公开同一实施例及不同实施例中的特征可以相互组合。
以上，仅为本公开的具体实施方式，但本公开的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应以权利要求的保护范围为准。

Claims (18)

  1. 一种基于忆阻器阵列的数据处理方法，其中，所述数据处理包括复数域的矩阵-向量乘法运算，所述忆阻器阵列包括阵列排布的多个忆阻器单元且配置为能进行乘和运算，
    所述数据处理方法包括：
    获取多个第一模拟信号；
    设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，其中，所述复数域的矩阵包括实部矩阵和虚部矩阵，所述参数矩阵包括所述实部矩阵、所述虚部矩阵以及基于所述虚部矩阵得到的虚部负矩阵，其中，所述虚部负矩阵中的参数元素与所述虚部矩阵中的参数元素一一对应，且所述虚部负矩阵中的每个参数元素为所述虚部矩阵中对应参数元素的负值；
    将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，控制所述忆阻器阵列操作以对所述多个第一模拟信号进行所述数据处理，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号。
  2. 根据权利要求1所述的数据处理方法，其中，所述忆阻器阵列包括第一子阵列、第二子阵列、第三子阵列和第四子阵列，
    设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，包括：
    将所述实部矩阵中的多个参数元素分别按照所述实部矩阵的形式映射于所述第一子阵列和所述第四子阵列，将所述虚部矩阵中的多个参数元素按照所述虚部矩阵的形式映射于所述第三子阵列，将所述虚部负矩阵中的多个参数元素按照所述虚部负矩阵的形式映射于所述第二子阵列，
    其中，所述第一子阵列和所述第二子阵列位于所述忆阻器阵列中的相同行但在行方向上不重叠，所述第三子阵列和所述第四子阵列位于所述忆阻器阵列中的相同行但在行方向上不重叠，所述第一子阵列和所述第三子阵列在列方向上不重叠。
  3. 根据权利要求2所述的数据处理方法，其中，所述第一子阵列和所述第三子阵列位于所述忆阻器阵列中的相同列，所述第二子阵列和所述第四子 阵列位于所述忆阻器阵列中的相同列。
  4. 根据权利要求2所述的数据处理方法，其中，所述忆阻器阵列至少包括2N行2M列，
    所述第一子阵列包括所述忆阻器阵列中的第i行至第i+N-1行，第j列至第j+M-1列，
    所述第二子阵列包括所述忆阻器阵列中的第i行至第i+N-1行，第j+k+M-1列至第j+k+2*M-2列，
    所述第三子阵列包括所述忆阻器阵列中的第i+g+N-1行至第i+g+2N-2行，第j列至第j+M-1列，
    所述第四子阵列包括所述忆阻器阵列中的第i+g+N-1行至第i+g+2N-2行，第j+k+M-1列至第j+k+2*M-2列，
    其中，M、N、i、j、k和g为正整数。
  5. 根据权利要求2-4任一项所述的数据处理方法，其中，所述实部矩阵包括阵列排布为N行M列的多个参数元素，
    将所述实部矩阵中的多个参数元素分别按照所述实部矩阵的形式映射于所述第一子阵列和所述第四子阵列，包括：
    将所述实部矩阵中位于同一行的N个参数元素分别映射于所述第一子阵列中同一行的N个忆阻器单元，以及所述第四子阵列中同一行的N个忆阻器单元；
    将所述实部矩阵中位于同一列中的M个参数元素分别映射于所述第一子阵列同一列的M个忆阻器单元，以及所述第四子阵列同一列的M个忆阻器单元。
  6. 根据权利要求1所述的数据处理方法，其中，所述多个第一模拟信号中的每个包括第一实部模拟信号和第一虚部模拟信号，
    获取所述多个第一模拟信号，包括：
    获取用于所述数据处理的复数域的向量，其中，所述复数域的向量包括实部向量和虚部向量；
    分别对所述实部向量和所述虚部向量进行编码处理，以得到多个第一实部模拟信号和多个第一虚部模拟信号。
  7. 根据权利要求6所述的数据处理方法，其中，将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，包括：
    将所述多个第一实部模拟信号分别输入所述第一子阵列和所述第三子阵列的列信号输入端；
    将所述多个第一虚部模拟信号分别输入所述第二子阵列和所述第四子阵列的列信号输入端。
  8. 根据权利要求2所述的数据处理方法，其中，所述多个第二模拟信号中的每个包括第二实部模拟信号和第二虚部模拟信号，
    所述第一子阵列和所述第二子阵列共用相同的行信号输出端，所述第三子阵列和所述第四子阵列共用相同的行信号输出端，
    在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号，包括：
    根据所述第一子阵列的行信号输出端输出的电流信号得到多个第二实部模拟信号；
    根据所述第三子阵列的行信号输出端输出的电流信号得到多个第二实部虚部信号。
  9. 根据权利要求8所述的数据处理方法，所述方法还包括：
    对所述多个第二实部模拟信号进行模数转换处理，以得到所述矩阵-向量乘法运算的实部运算结果；
    对所述多个第二虚部模拟信号进行模数转换处理，以得到所述矩阵-向量乘法运算的虚部运算结果。
  10. 根据权利要求1所述的数据处理方法，其中，所述参数矩阵表示为
    Figure PCTCN2022071337-appb-100001
    其中，W real为所述实部矩阵，W img为所述虚部矩阵，-W img为所述虚部负矩阵。
  11. 根据权利要求1-10任一项所述的数据处理方法，其中，所述参数矩阵包括P行Q列，所述参数矩阵中的第m行第n列的参数元素由第一子矩阵中第m行第n列的参数元素和第二子矩阵中第m行第n列的参数元素共同表示，m、n、P和Q为正整数，
    所述第一子矩阵包括P行第一参数元素，所述第二子矩阵包括P行第二参数元素，所述P行第一参数元素与所述P行第二参数元素的行列位置一一对应，
    所述第一子矩阵和所述第二子矩阵排布成2P行Q列的第一矩阵形式，
    设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，包括：
    将所述第一子矩阵和所述第二子矩阵按所述第一矩阵形式映射至所述忆阻器阵列。
  12. 根据权利要求11所述的数据处理方法，其中，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号，包括：
    确定至少一组待处理行，其中，所述至少一组待处理行中的每组包括与所述P行第一参数元素中的一行所对应的一行目标忆阻器单元，以及与对应于所述P行第一参数元素中的一行的所述P行第二参数元素中的一行所对应的一行目标忆阻器单元；
    对所述至少一组待处理行中的每组包括的所述两行目标忆阻器单元分别对应的所述多个行信号输出端中的两个的电流信号进行电流预处理，以得到所述至少一组待处理行中的每组对应的所述多个第二模拟信号。
  13. 根据权利要求1-10任一项所述的数据处理方法，其中，所述忆阻器阵列包括第一忆阻器阵列和第二忆阻器阵列，所述参数矩阵中第u行第v列的参数元素由第一子矩阵中第u行第v列的参数元素和第二子矩阵中第u行第v列的参数元素共同表示，其中，u和v为正整数，
    所述第一子矩阵与所述第二子矩阵均具有与所述参数矩阵相同的矩阵形式，
    设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，包括：将所述第一子矩阵对应地按照所述参数矩阵的形式映射于所述第一忆阻器阵列，
    将所述第二子矩阵对应地按照所述参数矩阵的形式映射于所述第二忆阻器阵列。
  14. 根据权利要求13所述的数据处理方法，其中，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号，包括：
    对所述第一忆阻器阵列中的所述多个行信号输出端中的每个的电流信号和所述第二忆阻器阵列中对应的所述多个行信号输出端中的每个的电流信号进行电流预处理，以得到所述多个第二模拟信号。
  15. 根据权利要求12或14所述的数据处理方法，其中，所述电流预处理 为电流相减处理或电流相加处理。
  16. 根据权利要求1-10任一项所述的数据处理方法，其中，所述数据处理为离散傅里叶变换，所述复数域的矩阵为所述离散傅里叶变换的系数矩阵，
    所述实部矩阵为所述系数矩阵的实部部分，所述虚部矩阵为所述系数矩阵的虚部部分。
  17. 一种电子装置，包括：
    忆阻器阵列，配置为能进行乘和运算；
    信号获取装置，配置为获取多个第一模拟信号；
    控制驱动电路，其中，所述控制驱动电路配置为执行以下步骤：
    设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列，其中，所述复数域的矩阵包括实部矩阵和虚部矩阵，所述参数矩阵包括所述实部矩阵、所述虚部矩阵以及基于所述虚部矩阵得到的虚部负矩阵，其中，所述虚部负矩阵中的参数元素与所述虚部矩阵中的参数元素一一对应，且所述虚部负矩阵中的每个参数元素为所述虚部矩阵中对应参数元素的负值；
    将所述多个第一模拟信号分别输入设置后的所述忆阻器阵列的多个列信号输入端，控制所述忆阻器阵列操作以对所述多个第一模拟信号进行所述数据处理，在所述忆阻器阵列的多个行信号输出端分别得到执行所述数据处理后的多个第二模拟信号。
  18. 根据权利要求17所述的电子装置，其中，所述忆阻器阵列包括第一子阵列、第二子阵列、第三子阵列和第四子阵列，
    所述控制驱动电路执行设置所述忆阻器阵列，将对应于所述数据处理的参数矩阵的数据写入所述忆阻器阵列时，包括执行以下步骤：
    将所述实部矩阵中的多个参数元素分别按照所述实部矩阵的形式映射于所述第一子阵列和所述第四子阵列，将所述虚部矩阵中的多个参数元素按照所述虚部矩阵的形式映射于所述第三子阵列，将所述虚部负矩阵中的多个参数元素按照所述虚部负矩阵的形式映射于所述第二子阵列，
    其中，所述第一子阵列和所述第二子阵列位于所述忆阻器阵列中的相同行但在行方向上不重叠，所述第三子阵列和所述第四子阵列位于所述忆阻器阵列中的相同行但在行方向上不重叠，所述第一子阵列和所述第三子阵列在列方向上不重叠。
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